1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/mfd/max77620.h> 2 #include <dt-bindings/mfd/max77620.h>
3 3
4 #include "tegra210.dtsi" 4 #include "tegra210.dtsi"
5 5
6 / { 6 / {
7 model = "NVIDIA Jetson TX1"; 7 model = "NVIDIA Jetson TX1";
8 compatible = "nvidia,p2180", "nvidia,t 8 compatible = "nvidia,p2180", "nvidia,tegra210";
9 9
10 aliases { 10 aliases {
11 rtc0 = "/i2c@7000d000/pmic@3c" 11 rtc0 = "/i2c@7000d000/pmic@3c";
12 rtc1 = "/rtc@7000e000"; 12 rtc1 = "/rtc@7000e000";
13 serial0 = &uarta; 13 serial0 = &uarta;
14 }; 14 };
15 15
16 chosen { 16 chosen {
17 stdout-path = "serial0:115200n 17 stdout-path = "serial0:115200n8";
18 }; 18 };
19 19
20 memory@80000000 { 20 memory@80000000 {
21 device_type = "memory"; 21 device_type = "memory";
22 reg = <0x0 0x80000000 0x1 0x0> 22 reg = <0x0 0x80000000 0x1 0x0>;
23 }; 23 };
24 24
25 gpu@57000000 { 25 gpu@57000000 {
26 vdd-supply = <&vdd_gpu>; 26 vdd-supply = <&vdd_gpu>;
27 }; 27 };
28 28
29 /* debug port */ 29 /* debug port */
30 serial@70006000 { 30 serial@70006000 {
31 /delete-property/ dmas; 31 /delete-property/ dmas;
32 /delete-property/ dma-names; 32 /delete-property/ dma-names;
33 status = "okay"; 33 status = "okay";
34 }; 34 };
35 35
36 serial@70006300 { <<
37 /delete-property/ reg-shift; <<
38 status = "okay"; <<
39 compatible = "nvidia,tegra30-h <<
40 reset-names = "serial"; <<
41 <<
42 bluetooth { <<
43 compatible = "brcm,bcm <<
44 device-wakeup-gpios = <<
45 shutdown-gpios = <&gpi <<
46 interrupt-parent = <&g <<
47 interrupts = <TEGRA_GP <<
48 interrupt-names = "hos <<
49 }; <<
50 }; <<
51 <<
52 i2c@7000c400 { <<
53 status = "okay"; <<
54 <<
55 power-sensor@40 { <<
56 compatible = "ti,ina32 <<
57 reg = <0x40>; <<
58 #address-cells = <1>; <<
59 #size-cells = <0>; <<
60 <<
61 input@0 { <<
62 reg = <0x0>; <<
63 label = "VDD_I <<
64 shunt-resistor <<
65 }; <<
66 <<
67 input@1 { <<
68 reg = <0x1>; <<
69 label = "VDD_G <<
70 shunt-resistor <<
71 }; <<
72 <<
73 input@2 { <<
74 reg = <0x2>; <<
75 label = "VDD_C <<
76 shunt-resistor <<
77 }; <<
78 }; <<
79 }; <<
80 <<
81 i2c@7000c500 { 36 i2c@7000c500 {
82 status = "okay"; 37 status = "okay";
83 38
84 /* module ID EEPROM */ 39 /* module ID EEPROM */
85 eeprom@50 { 40 eeprom@50 {
86 compatible = "atmel,24 41 compatible = "atmel,24c02";
87 reg = <0x50>; 42 reg = <0x50>;
88 43
89 label = "module"; 44 label = "module";
90 vcc-supply = <&vdd_1v8 45 vcc-supply = <&vdd_1v8>;
91 address-width = <8>; 46 address-width = <8>;
92 pagesize = <8>; 47 pagesize = <8>;
93 size = <256>; 48 size = <256>;
94 read-only; 49 read-only;
95 }; 50 };
96 }; 51 };
97 52
98 i2c@7000d000 { 53 i2c@7000d000 {
99 status = "okay"; 54 status = "okay";
100 clock-frequency = <400000>; 55 clock-frequency = <400000>;
101 56
102 pmic: pmic@3c { 57 pmic: pmic@3c {
103 compatible = "maxim,ma 58 compatible = "maxim,max77620";
104 reg = <0x3c>; 59 reg = <0x3c>;
105 interrupt-parent = <&t 60 interrupt-parent = <&tegra_pmc>;
106 interrupts = <51 IRQ_T 61 interrupts = <51 IRQ_TYPE_LEVEL_LOW>;
107 62
108 #interrupt-cells = <2> 63 #interrupt-cells = <2>;
109 interrupt-controller; 64 interrupt-controller;
110 65
111 #gpio-cells = <2>; 66 #gpio-cells = <2>;
112 gpio-controller; 67 gpio-controller;
113 68
114 pinctrl-names = "defau 69 pinctrl-names = "default";
115 pinctrl-0 = <&max77620 70 pinctrl-0 = <&max77620_default>;
116 71
117 fps { 72 fps {
118 fps0 { 73 fps0 {
119 maxim, 74 maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>;
120 maxim, 75 maxim,suspend-fps-time-period-us = <1280>;
121 }; 76 };
122 77
123 fps1 { 78 fps1 {
124 maxim, 79 maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>;
125 maxim, 80 maxim,suspend-fps-time-period-us = <1280>;
126 }; 81 };
127 82
128 fps2 { 83 fps2 {
129 maxim, 84 maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>;
130 }; 85 };
131 }; 86 };
132 87
133 max77620_default: pinm 88 max77620_default: pinmux {
134 gpio0 { 89 gpio0 {
135 pins = 90 pins = "gpio0";
136 functi 91 function = "gpio";
137 }; 92 };
138 93
139 gpio1 { 94 gpio1 {
140 pins = 95 pins = "gpio1";
141 functi 96 function = "fps-out";
142 drive- 97 drive-push-pull = <1>;
143 maxim, 98 maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
144 maxim, 99 maxim,active-fps-power-up-slot = <7>;
145 maxim, 100 maxim,active-fps-power-down-slot = <0>;
146 }; 101 };
147 102
148 gpio2_3 { 103 gpio2_3 {
149 pins = 104 pins = "gpio2", "gpio3";
150 functi 105 function = "fps-out";
151 drive- 106 drive-open-drain = <1>;
152 maxim, 107 maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
153 }; 108 };
154 109
155 gpio4 { 110 gpio4 {
156 pins = 111 pins = "gpio4";
157 functi 112 function = "32k-out1";
158 }; 113 };
159 114
160 gpio5_6_7 { 115 gpio5_6_7 {
161 pins = 116 pins = "gpio5", "gpio6", "gpio7";
162 functi 117 function = "gpio";
163 drive- 118 drive-push-pull = <1>;
164 }; 119 };
165 }; 120 };
166 121
167 regulators { 122 regulators {
168 in-ldo0-1-supp 123 in-ldo0-1-supply = <&vdd_pre>;
169 in-ldo7-8-supp 124 in-ldo7-8-supply = <&vdd_pre>;
170 in-sd3-supply 125 in-sd3-supply = <&vdd_5v0_sys>;
171 126
172 vdd_soc: sd0 { 127 vdd_soc: sd0 {
173 regula 128 regulator-name = "VDD_SOC";
174 regula 129 regulator-min-microvolt = <600000>;
175 regula 130 regulator-max-microvolt = <1400000>;
176 regula 131 regulator-always-on;
177 regula 132 regulator-boot-on;
178 133
179 regula 134 regulator-enable-ramp-delay = <146>;
180 regula 135 regulator-ramp-delay = <27500>;
181 136
182 maxim, 137 maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
183 }; 138 };
184 139
185 vdd_ddr: sd1 { 140 vdd_ddr: sd1 {
186 regula 141 regulator-name = "VDD_DDR_1V1_PMIC";
187 regula 142 regulator-always-on;
188 regula 143 regulator-boot-on;
189 144
190 regula 145 regulator-enable-ramp-delay = <130>;
191 regula 146 regulator-ramp-delay = <27500>;
192 147
193 maxim, 148 maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
194 }; 149 };
195 150
196 vdd_pre: sd2 { 151 vdd_pre: sd2 {
197 regula 152 regulator-name = "VDD_PRE_REG_1V35";
198 regula 153 regulator-min-microvolt = <1350000>;
199 regula 154 regulator-max-microvolt = <1350000>;
200 155
201 regula 156 regulator-enable-ramp-delay = <176>;
202 regula 157 regulator-ramp-delay = <27500>;
203 158
204 maxim, 159 maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
205 }; 160 };
206 161
207 vdd_1v8: sd3 { 162 vdd_1v8: sd3 {
208 regula 163 regulator-name = "VDD_1V8";
209 regula 164 regulator-min-microvolt = <1800000>;
210 regula 165 regulator-max-microvolt = <1800000>;
211 regula 166 regulator-always-on;
212 regula 167 regulator-boot-on;
213 168
214 regula 169 regulator-enable-ramp-delay = <242>;
215 regula 170 regulator-ramp-delay = <27500>;
216 171
217 maxim, 172 maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
218 }; 173 };
219 174
220 vdd_sys_1v2: l 175 vdd_sys_1v2: ldo0 {
221 regula 176 regulator-name = "AVDD_SYS_1V2";
222 regula 177 regulator-min-microvolt = <1200000>;
223 regula 178 regulator-max-microvolt = <1200000>;
224 regula 179 regulator-always-on;
225 regula 180 regulator-boot-on;
226 181
227 regula 182 regulator-enable-ramp-delay = <26>;
228 regula 183 regulator-ramp-delay = <100000>;
229 184
230 maxim, 185 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
231 }; 186 };
232 187
233 vdd_pex_1v05: 188 vdd_pex_1v05: ldo1 {
234 regula 189 regulator-name = "VDD_PEX_1V05";
235 regula 190 regulator-min-microvolt = <1050000>;
236 regula 191 regulator-max-microvolt = <1050000>;
237 192
238 regula 193 regulator-enable-ramp-delay = <22>;
239 regula 194 regulator-ramp-delay = <100000>;
240 195
241 maxim, 196 maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
242 }; 197 };
243 198
244 vddio_sdmmc: l 199 vddio_sdmmc: ldo2 {
245 regula 200 regulator-name = "VDDIO_SDMMC";
246 regula 201 regulator-min-microvolt = <1800000>;
247 regula 202 regulator-max-microvolt = <3300000>;
248 regula 203 regulator-always-on;
249 regula 204 regulator-boot-on;
250 205
251 regula 206 regulator-enable-ramp-delay = <62>;
252 regula 207 regulator-ramp-delay = <100000>;
253 208
254 maxim, 209 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
255 }; 210 };
256 211
257 vdd_cam_hv: ld 212 vdd_cam_hv: ldo3 {
258 regula 213 regulator-name = "VDD_CAM_HV";
259 regula 214 regulator-min-microvolt = <2800000>;
260 regula 215 regulator-max-microvolt = <2800000>;
261 216
262 regula 217 regulator-enable-ramp-delay = <50>;
263 regula 218 regulator-ramp-delay = <100000>;
264 219
265 maxim, 220 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
266 }; 221 };
267 222
268 vdd_rtc: ldo4 223 vdd_rtc: ldo4 {
269 regula 224 regulator-name = "VDD_RTC";
270 regula 225 regulator-min-microvolt = <850000>;
271 regula 226 regulator-max-microvolt = <850000>;
272 regula 227 regulator-always-on;
273 regula 228 regulator-boot-on;
274 229
275 regula 230 regulator-enable-ramp-delay = <22>;
276 regula 231 regulator-ramp-delay = <100000>;
277 232
278 maxim, 233 maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
279 }; 234 };
280 235
281 vdd_ts_hv: ldo 236 vdd_ts_hv: ldo5 {
282 regula 237 regulator-name = "VDD_TS_HV";
283 regula 238 regulator-min-microvolt = <3300000>;
284 regula 239 regulator-max-microvolt = <3300000>;
285 240
286 regula 241 regulator-enable-ramp-delay = <62>;
287 regula 242 regulator-ramp-delay = <100000>;
288 243
289 maxim, 244 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
290 }; 245 };
291 246
292 vdd_ts: ldo6 { 247 vdd_ts: ldo6 {
293 regula 248 regulator-name = "VDD_TS_1V8";
294 regula 249 regulator-min-microvolt = <1800000>;
295 regula 250 regulator-max-microvolt = <1800000>;
296 251
297 regula 252 regulator-enable-ramp-delay = <36>;
298 regula 253 regulator-ramp-delay = <100000>;
299 254
300 maxim, 255 maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
301 maxim, 256 maxim,active-fps-power-up-slot = <7>;
302 maxim, 257 maxim,active-fps-power-down-slot = <0>;
303 }; 258 };
304 259
305 avdd_1v05_pll: 260 avdd_1v05_pll: ldo7 {
306 regula 261 regulator-name = "AVDD_1V05_PLL";
307 regula 262 regulator-min-microvolt = <1050000>;
308 regula 263 regulator-max-microvolt = <1050000>;
309 regula 264 regulator-always-on;
310 regula 265 regulator-boot-on;
311 266
312 regula 267 regulator-enable-ramp-delay = <24>;
313 regula 268 regulator-ramp-delay = <100000>;
314 269
315 maxim, 270 maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
316 }; 271 };
317 272
318 avdd_1v05: ldo 273 avdd_1v05: ldo8 {
319 regula 274 regulator-name = "AVDD_SATA_HDMI_DP_1V05";
320 regula 275 regulator-min-microvolt = <1050000>;
321 regula 276 regulator-max-microvolt = <1050000>;
322 277
323 regula 278 regulator-enable-ramp-delay = <22>;
324 regula 279 regulator-ramp-delay = <100000>;
325 280
326 maxim, 281 maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
327 }; 282 };
328 }; 283 };
329 }; 284 };
330 }; 285 };
331 286
332 pmc@7000e400 { 287 pmc@7000e400 {
333 nvidia,invert-interrupt; 288 nvidia,invert-interrupt;
334 nvidia,suspend-mode = <0>; 289 nvidia,suspend-mode = <0>;
335 nvidia,cpu-pwr-good-time = <0> 290 nvidia,cpu-pwr-good-time = <0>;
336 nvidia,cpu-pwr-off-time = <0>; 291 nvidia,cpu-pwr-off-time = <0>;
337 nvidia,core-pwr-good-time = <4 292 nvidia,core-pwr-good-time = <4587 3876>;
338 nvidia,core-pwr-off-time = <39 293 nvidia,core-pwr-off-time = <39065>;
339 nvidia,core-power-req-active-h 294 nvidia,core-power-req-active-high;
340 nvidia,sys-clock-req-active-hi 295 nvidia,sys-clock-req-active-high;
341 }; <<
342 <<
343 mmc@700b0200 { <<
344 status = "okay"; <<
345 bus-width = <4>; <<
346 non-removable; <<
347 power-gpios = <&gpio TEGRA_GPI <<
348 vqmmc-supply = <&vdd_1v8>; <<
349 vmmc-supply = <&vdd_3v3_sys>; <<
350 #address-cells = <1>; <<
351 #size-cells = <0>; <<
352 <<
353 wifi@1 { <<
354 compatible = "brcm,bcm <<
355 reg = <1>; <<
356 interrupt-parent = <&g <<
357 interrupts = <TEGRA_GP <<
358 interrupt-names = "hos <<
359 }; <<
360 }; 296 };
361 297
362 /* eMMC */ 298 /* eMMC */
363 mmc@700b0600 { 299 mmc@700b0600 {
364 status = "okay"; 300 status = "okay";
365 bus-width = <8>; 301 bus-width = <8>;
366 non-removable; 302 non-removable;
367 vqmmc-supply = <&vdd_1v8>; 303 vqmmc-supply = <&vdd_1v8>;
368 }; 304 };
369 305
370 clk32k_in: clock-32k { 306 clk32k_in: clock-32k {
371 compatible = "fixed-clock"; 307 compatible = "fixed-clock";
372 clock-frequency = <32768>; 308 clock-frequency = <32768>;
373 #clock-cells = <0>; 309 #clock-cells = <0>;
374 }; 310 };
375 311
376 cpus { 312 cpus {
377 cpu@0 { 313 cpu@0 {
378 enable-method = "psci" 314 enable-method = "psci";
379 }; 315 };
380 316
381 cpu@1 { 317 cpu@1 {
382 enable-method = "psci" 318 enable-method = "psci";
383 }; 319 };
384 320
385 cpu@2 { 321 cpu@2 {
386 enable-method = "psci" 322 enable-method = "psci";
387 }; 323 };
388 324
389 cpu@3 { 325 cpu@3 {
390 enable-method = "psci" 326 enable-method = "psci";
391 }; 327 };
392 328
393 idle-states { 329 idle-states {
394 cpu-sleep { 330 cpu-sleep {
395 status = "okay 331 status = "okay";
396 }; 332 };
397 }; 333 };
398 }; 334 };
399 335
400 psci { 336 psci {
401 compatible = "arm,psci-0.2"; 337 compatible = "arm,psci-0.2";
402 method = "smc"; 338 method = "smc";
403 }; 339 };
404 340
405 vdd_gpu: regulator-vdd-gpu { 341 vdd_gpu: regulator-vdd-gpu {
406 compatible = "pwm-regulator"; 342 compatible = "pwm-regulator";
407 pwms = <&pwm 1 8000>; 343 pwms = <&pwm 1 8000>;
408 regulator-name = "VDD_GPU"; 344 regulator-name = "VDD_GPU";
409 regulator-min-microvolt = <710 345 regulator-min-microvolt = <710000>;
410 regulator-max-microvolt = <132 346 regulator-max-microvolt = <1320000>;
411 enable-gpios = <&pmic 6 GPIO_A 347 enable-gpios = <&pmic 6 GPIO_ACTIVE_HIGH>;
412 regulator-ramp-delay = <80>; 348 regulator-ramp-delay = <80>;
413 regulator-enable-ramp-delay = 349 regulator-enable-ramp-delay = <2000>;
414 regulator-settling-time-us = < 350 regulator-settling-time-us = <160>;
415 }; 351 };
416 }; 352 };
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