1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/mfd/max77620.h> 2 #include <dt-bindings/mfd/max77620.h>
3 3
4 #include "tegra210.dtsi" 4 #include "tegra210.dtsi"
5 5
6 / { 6 / {
7 model = "NVIDIA Jetson TX1"; 7 model = "NVIDIA Jetson TX1";
8 compatible = "nvidia,p2180", "nvidia,t 8 compatible = "nvidia,p2180", "nvidia,tegra210";
9 9
10 aliases { 10 aliases {
11 rtc0 = "/i2c@7000d000/pmic@3c" 11 rtc0 = "/i2c@7000d000/pmic@3c";
12 rtc1 = "/rtc@7000e000"; 12 rtc1 = "/rtc@7000e000";
13 serial0 = &uarta; 13 serial0 = &uarta;
14 }; 14 };
15 15
16 chosen { 16 chosen {
17 stdout-path = "serial0:115200n 17 stdout-path = "serial0:115200n8";
18 }; 18 };
19 19
20 memory@80000000 { 20 memory@80000000 {
21 device_type = "memory"; 21 device_type = "memory";
22 reg = <0x0 0x80000000 0x1 0x0> 22 reg = <0x0 0x80000000 0x1 0x0>;
23 }; 23 };
24 24
25 gpu@57000000 { 25 gpu@57000000 {
26 vdd-supply = <&vdd_gpu>; 26 vdd-supply = <&vdd_gpu>;
27 }; 27 };
28 28
29 /* debug port */ 29 /* debug port */
30 serial@70006000 { 30 serial@70006000 {
31 /delete-property/ dmas; 31 /delete-property/ dmas;
32 /delete-property/ dma-names; 32 /delete-property/ dma-names;
33 status = "okay"; 33 status = "okay";
34 }; 34 };
35 35
36 serial@70006300 { 36 serial@70006300 {
37 /delete-property/ reg-shift; 37 /delete-property/ reg-shift;
38 status = "okay"; 38 status = "okay";
39 compatible = "nvidia,tegra30-h 39 compatible = "nvidia,tegra30-hsuart";
40 reset-names = "serial"; 40 reset-names = "serial";
41 41
42 bluetooth { 42 bluetooth {
43 compatible = "brcm,bcm 43 compatible = "brcm,bcm43540-bt";
44 device-wakeup-gpios = 44 device-wakeup-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>;
45 shutdown-gpios = <&gpi 45 shutdown-gpios = <&gpio TEGRA_GPIO(H, 4) GPIO_ACTIVE_HIGH>;
46 interrupt-parent = <&g 46 interrupt-parent = <&gpio>;
47 interrupts = <TEGRA_GP 47 interrupts = <TEGRA_GPIO(H, 5) IRQ_TYPE_LEVEL_LOW>;
48 interrupt-names = "hos 48 interrupt-names = "host-wakeup";
49 }; 49 };
50 }; 50 };
51 51
52 i2c@7000c400 { 52 i2c@7000c400 {
53 status = "okay"; 53 status = "okay";
54 54
55 power-sensor@40 { 55 power-sensor@40 {
56 compatible = "ti,ina32 56 compatible = "ti,ina3221";
57 reg = <0x40>; 57 reg = <0x40>;
58 #address-cells = <1>; 58 #address-cells = <1>;
59 #size-cells = <0>; 59 #size-cells = <0>;
60 60
61 input@0 { 61 input@0 {
62 reg = <0x0>; 62 reg = <0x0>;
63 label = "VDD_I 63 label = "VDD_IN";
64 shunt-resistor 64 shunt-resistor-micro-ohms = <20000>;
65 }; 65 };
66 66
67 input@1 { 67 input@1 {
68 reg = <0x1>; 68 reg = <0x1>;
69 label = "VDD_G 69 label = "VDD_GPU";
70 shunt-resistor 70 shunt-resistor-micro-ohms = <10000>;
71 }; 71 };
72 72
73 input@2 { 73 input@2 {
74 reg = <0x2>; 74 reg = <0x2>;
75 label = "VDD_C 75 label = "VDD_CPU";
76 shunt-resistor 76 shunt-resistor-micro-ohms = <10000>;
77 }; 77 };
78 }; 78 };
79 }; 79 };
80 80
81 i2c@7000c500 { 81 i2c@7000c500 {
82 status = "okay"; 82 status = "okay";
83 83
84 /* module ID EEPROM */ 84 /* module ID EEPROM */
85 eeprom@50 { 85 eeprom@50 {
86 compatible = "atmel,24 86 compatible = "atmel,24c02";
87 reg = <0x50>; 87 reg = <0x50>;
88 88
89 label = "module"; 89 label = "module";
90 vcc-supply = <&vdd_1v8 90 vcc-supply = <&vdd_1v8>;
91 address-width = <8>; 91 address-width = <8>;
92 pagesize = <8>; 92 pagesize = <8>;
93 size = <256>; 93 size = <256>;
94 read-only; 94 read-only;
95 }; 95 };
96 }; 96 };
97 97
98 i2c@7000d000 { 98 i2c@7000d000 {
99 status = "okay"; 99 status = "okay";
100 clock-frequency = <400000>; 100 clock-frequency = <400000>;
101 101
102 pmic: pmic@3c { 102 pmic: pmic@3c {
103 compatible = "maxim,ma 103 compatible = "maxim,max77620";
104 reg = <0x3c>; 104 reg = <0x3c>;
105 interrupt-parent = <&t 105 interrupt-parent = <&tegra_pmc>;
106 interrupts = <51 IRQ_T 106 interrupts = <51 IRQ_TYPE_LEVEL_LOW>;
107 107
108 #interrupt-cells = <2> 108 #interrupt-cells = <2>;
109 interrupt-controller; 109 interrupt-controller;
110 110
111 #gpio-cells = <2>; 111 #gpio-cells = <2>;
112 gpio-controller; 112 gpio-controller;
113 113
114 pinctrl-names = "defau 114 pinctrl-names = "default";
115 pinctrl-0 = <&max77620 115 pinctrl-0 = <&max77620_default>;
116 116
117 fps { 117 fps {
118 fps0 { 118 fps0 {
119 maxim, 119 maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>;
120 maxim, 120 maxim,suspend-fps-time-period-us = <1280>;
121 }; 121 };
122 122
123 fps1 { 123 fps1 {
124 maxim, 124 maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>;
125 maxim, 125 maxim,suspend-fps-time-period-us = <1280>;
126 }; 126 };
127 127
128 fps2 { 128 fps2 {
129 maxim, 129 maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>;
130 }; 130 };
131 }; 131 };
132 132
133 max77620_default: pinm 133 max77620_default: pinmux {
134 gpio0 { 134 gpio0 {
135 pins = 135 pins = "gpio0";
136 functi 136 function = "gpio";
137 }; 137 };
138 138
139 gpio1 { 139 gpio1 {
140 pins = 140 pins = "gpio1";
141 functi 141 function = "fps-out";
142 drive- 142 drive-push-pull = <1>;
143 maxim, 143 maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
144 maxim, 144 maxim,active-fps-power-up-slot = <7>;
145 maxim, 145 maxim,active-fps-power-down-slot = <0>;
146 }; 146 };
147 147
148 gpio2_3 { 148 gpio2_3 {
149 pins = 149 pins = "gpio2", "gpio3";
150 functi 150 function = "fps-out";
151 drive- 151 drive-open-drain = <1>;
152 maxim, 152 maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
153 }; 153 };
154 154
155 gpio4 { 155 gpio4 {
156 pins = 156 pins = "gpio4";
157 functi 157 function = "32k-out1";
158 }; 158 };
159 159
160 gpio5_6_7 { 160 gpio5_6_7 {
161 pins = 161 pins = "gpio5", "gpio6", "gpio7";
162 functi 162 function = "gpio";
163 drive- 163 drive-push-pull = <1>;
164 }; 164 };
165 }; 165 };
166 166
167 regulators { 167 regulators {
168 in-ldo0-1-supp 168 in-ldo0-1-supply = <&vdd_pre>;
169 in-ldo7-8-supp 169 in-ldo7-8-supply = <&vdd_pre>;
170 in-sd3-supply 170 in-sd3-supply = <&vdd_5v0_sys>;
171 171
172 vdd_soc: sd0 { 172 vdd_soc: sd0 {
173 regula 173 regulator-name = "VDD_SOC";
174 regula 174 regulator-min-microvolt = <600000>;
175 regula 175 regulator-max-microvolt = <1400000>;
176 regula 176 regulator-always-on;
177 regula 177 regulator-boot-on;
178 178
179 regula 179 regulator-enable-ramp-delay = <146>;
180 regula 180 regulator-ramp-delay = <27500>;
181 181
182 maxim, 182 maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
183 }; 183 };
184 184
185 vdd_ddr: sd1 { 185 vdd_ddr: sd1 {
186 regula 186 regulator-name = "VDD_DDR_1V1_PMIC";
187 regula 187 regulator-always-on;
188 regula 188 regulator-boot-on;
189 189
190 regula 190 regulator-enable-ramp-delay = <130>;
191 regula 191 regulator-ramp-delay = <27500>;
192 192
193 maxim, 193 maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
194 }; 194 };
195 195
196 vdd_pre: sd2 { 196 vdd_pre: sd2 {
197 regula 197 regulator-name = "VDD_PRE_REG_1V35";
198 regula 198 regulator-min-microvolt = <1350000>;
199 regula 199 regulator-max-microvolt = <1350000>;
200 200
201 regula 201 regulator-enable-ramp-delay = <176>;
202 regula 202 regulator-ramp-delay = <27500>;
203 203
204 maxim, 204 maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
205 }; 205 };
206 206
207 vdd_1v8: sd3 { 207 vdd_1v8: sd3 {
208 regula 208 regulator-name = "VDD_1V8";
209 regula 209 regulator-min-microvolt = <1800000>;
210 regula 210 regulator-max-microvolt = <1800000>;
211 regula 211 regulator-always-on;
212 regula 212 regulator-boot-on;
213 213
214 regula 214 regulator-enable-ramp-delay = <242>;
215 regula 215 regulator-ramp-delay = <27500>;
216 216
217 maxim, 217 maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
218 }; 218 };
219 219
220 vdd_sys_1v2: l 220 vdd_sys_1v2: ldo0 {
221 regula 221 regulator-name = "AVDD_SYS_1V2";
222 regula 222 regulator-min-microvolt = <1200000>;
223 regula 223 regulator-max-microvolt = <1200000>;
224 regula 224 regulator-always-on;
225 regula 225 regulator-boot-on;
226 226
227 regula 227 regulator-enable-ramp-delay = <26>;
228 regula 228 regulator-ramp-delay = <100000>;
229 229
230 maxim, 230 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
231 }; 231 };
232 232
233 vdd_pex_1v05: 233 vdd_pex_1v05: ldo1 {
234 regula 234 regulator-name = "VDD_PEX_1V05";
235 regula 235 regulator-min-microvolt = <1050000>;
236 regula 236 regulator-max-microvolt = <1050000>;
237 237
238 regula 238 regulator-enable-ramp-delay = <22>;
239 regula 239 regulator-ramp-delay = <100000>;
240 240
241 maxim, 241 maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
242 }; 242 };
243 243
244 vddio_sdmmc: l 244 vddio_sdmmc: ldo2 {
245 regula 245 regulator-name = "VDDIO_SDMMC";
246 regula 246 regulator-min-microvolt = <1800000>;
247 regula 247 regulator-max-microvolt = <3300000>;
248 regula 248 regulator-always-on;
249 regula 249 regulator-boot-on;
250 250
251 regula 251 regulator-enable-ramp-delay = <62>;
252 regula 252 regulator-ramp-delay = <100000>;
253 253
254 maxim, 254 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
255 }; 255 };
256 256
257 vdd_cam_hv: ld 257 vdd_cam_hv: ldo3 {
258 regula 258 regulator-name = "VDD_CAM_HV";
259 regula 259 regulator-min-microvolt = <2800000>;
260 regula 260 regulator-max-microvolt = <2800000>;
261 261
262 regula 262 regulator-enable-ramp-delay = <50>;
263 regula 263 regulator-ramp-delay = <100000>;
264 264
265 maxim, 265 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
266 }; 266 };
267 267
268 vdd_rtc: ldo4 268 vdd_rtc: ldo4 {
269 regula 269 regulator-name = "VDD_RTC";
270 regula 270 regulator-min-microvolt = <850000>;
271 regula 271 regulator-max-microvolt = <850000>;
272 regula 272 regulator-always-on;
273 regula 273 regulator-boot-on;
274 274
275 regula 275 regulator-enable-ramp-delay = <22>;
276 regula 276 regulator-ramp-delay = <100000>;
277 277
278 maxim, 278 maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
279 }; 279 };
280 280
281 vdd_ts_hv: ldo 281 vdd_ts_hv: ldo5 {
282 regula 282 regulator-name = "VDD_TS_HV";
283 regula 283 regulator-min-microvolt = <3300000>;
284 regula 284 regulator-max-microvolt = <3300000>;
285 285
286 regula 286 regulator-enable-ramp-delay = <62>;
287 regula 287 regulator-ramp-delay = <100000>;
288 288
289 maxim, 289 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
290 }; 290 };
291 291
292 vdd_ts: ldo6 { 292 vdd_ts: ldo6 {
293 regula 293 regulator-name = "VDD_TS_1V8";
294 regula 294 regulator-min-microvolt = <1800000>;
295 regula 295 regulator-max-microvolt = <1800000>;
296 296
297 regula 297 regulator-enable-ramp-delay = <36>;
298 regula 298 regulator-ramp-delay = <100000>;
299 299
300 maxim, 300 maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
301 maxim, 301 maxim,active-fps-power-up-slot = <7>;
302 maxim, 302 maxim,active-fps-power-down-slot = <0>;
303 }; 303 };
304 304
305 avdd_1v05_pll: 305 avdd_1v05_pll: ldo7 {
306 regula 306 regulator-name = "AVDD_1V05_PLL";
307 regula 307 regulator-min-microvolt = <1050000>;
308 regula 308 regulator-max-microvolt = <1050000>;
309 regula 309 regulator-always-on;
310 regula 310 regulator-boot-on;
311 311
312 regula 312 regulator-enable-ramp-delay = <24>;
313 regula 313 regulator-ramp-delay = <100000>;
314 314
315 maxim, 315 maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
316 }; 316 };
317 317
318 avdd_1v05: ldo 318 avdd_1v05: ldo8 {
319 regula 319 regulator-name = "AVDD_SATA_HDMI_DP_1V05";
320 regula 320 regulator-min-microvolt = <1050000>;
321 regula 321 regulator-max-microvolt = <1050000>;
322 322
323 regula 323 regulator-enable-ramp-delay = <22>;
324 regula 324 regulator-ramp-delay = <100000>;
325 325
326 maxim, 326 maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
327 }; 327 };
328 }; 328 };
329 }; 329 };
330 }; 330 };
331 331
332 pmc@7000e400 { 332 pmc@7000e400 {
333 nvidia,invert-interrupt; 333 nvidia,invert-interrupt;
334 nvidia,suspend-mode = <0>; 334 nvidia,suspend-mode = <0>;
335 nvidia,cpu-pwr-good-time = <0> 335 nvidia,cpu-pwr-good-time = <0>;
336 nvidia,cpu-pwr-off-time = <0>; 336 nvidia,cpu-pwr-off-time = <0>;
337 nvidia,core-pwr-good-time = <4 337 nvidia,core-pwr-good-time = <4587 3876>;
338 nvidia,core-pwr-off-time = <39 338 nvidia,core-pwr-off-time = <39065>;
339 nvidia,core-power-req-active-h 339 nvidia,core-power-req-active-high;
340 nvidia,sys-clock-req-active-hi 340 nvidia,sys-clock-req-active-high;
341 }; 341 };
342 342
343 mmc@700b0200 { 343 mmc@700b0200 {
344 status = "okay"; 344 status = "okay";
345 bus-width = <4>; 345 bus-width = <4>;
346 non-removable; 346 non-removable;
347 power-gpios = <&gpio TEGRA_GPI 347 power-gpios = <&gpio TEGRA_GPIO(H, 0) GPIO_ACTIVE_HIGH>;
348 vqmmc-supply = <&vdd_1v8>; 348 vqmmc-supply = <&vdd_1v8>;
349 vmmc-supply = <&vdd_3v3_sys>; 349 vmmc-supply = <&vdd_3v3_sys>;
350 #address-cells = <1>; 350 #address-cells = <1>;
351 #size-cells = <0>; 351 #size-cells = <0>;
352 352
353 wifi@1 { 353 wifi@1 {
354 compatible = "brcm,bcm 354 compatible = "brcm,bcm4354-fmac";
355 reg = <1>; 355 reg = <1>;
356 interrupt-parent = <&g 356 interrupt-parent = <&gpio>;
357 interrupts = <TEGRA_GP 357 interrupts = <TEGRA_GPIO(H, 2) IRQ_TYPE_LEVEL_HIGH>;
358 interrupt-names = "hos 358 interrupt-names = "host-wake";
359 }; 359 };
360 }; 360 };
361 361
362 /* eMMC */ 362 /* eMMC */
363 mmc@700b0600 { 363 mmc@700b0600 {
364 status = "okay"; 364 status = "okay";
365 bus-width = <8>; 365 bus-width = <8>;
366 non-removable; 366 non-removable;
367 vqmmc-supply = <&vdd_1v8>; 367 vqmmc-supply = <&vdd_1v8>;
368 }; 368 };
369 369
370 clk32k_in: clock-32k { 370 clk32k_in: clock-32k {
371 compatible = "fixed-clock"; 371 compatible = "fixed-clock";
372 clock-frequency = <32768>; 372 clock-frequency = <32768>;
373 #clock-cells = <0>; 373 #clock-cells = <0>;
374 }; 374 };
375 375
376 cpus { 376 cpus {
377 cpu@0 { 377 cpu@0 {
378 enable-method = "psci" 378 enable-method = "psci";
379 }; 379 };
380 380
381 cpu@1 { 381 cpu@1 {
382 enable-method = "psci" 382 enable-method = "psci";
383 }; 383 };
384 384
385 cpu@2 { 385 cpu@2 {
386 enable-method = "psci" 386 enable-method = "psci";
387 }; 387 };
388 388
389 cpu@3 { 389 cpu@3 {
390 enable-method = "psci" 390 enable-method = "psci";
391 }; 391 };
392 392
393 idle-states { 393 idle-states {
394 cpu-sleep { 394 cpu-sleep {
395 status = "okay 395 status = "okay";
396 }; 396 };
397 }; 397 };
398 }; 398 };
399 399
400 psci { 400 psci {
401 compatible = "arm,psci-0.2"; 401 compatible = "arm,psci-0.2";
402 method = "smc"; 402 method = "smc";
403 }; 403 };
404 404
405 vdd_gpu: regulator-vdd-gpu { 405 vdd_gpu: regulator-vdd-gpu {
406 compatible = "pwm-regulator"; 406 compatible = "pwm-regulator";
407 pwms = <&pwm 1 8000>; 407 pwms = <&pwm 1 8000>;
408 regulator-name = "VDD_GPU"; 408 regulator-name = "VDD_GPU";
409 regulator-min-microvolt = <710 409 regulator-min-microvolt = <710000>;
410 regulator-max-microvolt = <132 410 regulator-max-microvolt = <1320000>;
411 enable-gpios = <&pmic 6 GPIO_A 411 enable-gpios = <&pmic 6 GPIO_ACTIVE_HIGH>;
412 regulator-ramp-delay = <80>; 412 regulator-ramp-delay = <80>;
413 regulator-enable-ramp-delay = 413 regulator-enable-ramp-delay = <2000>;
414 regulator-settling-time-us = < 414 regulator-settling-time-us = <160>;
415 }; 415 };
416 }; 416 };
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