1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 2
3 #include <dt-bindings/input/input.h> 3 #include <dt-bindings/input/input.h>
4 #include <dt-bindings/input/gpio-keys.h> 4 #include <dt-bindings/input/gpio-keys.h>
5 #include <dt-bindings/mfd/max77620.h> 5 #include <dt-bindings/mfd/max77620.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra.h> 6 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
7 #include "tegra210.dtsi" 7 #include "tegra210.dtsi"
8 8
9 / { 9 / {
10 aliases { 10 aliases {
11 serial0 = &uarta; 11 serial0 = &uarta;
12 }; 12 };
13 13
14 chosen { 14 chosen {
15 bootargs = "earlycon"; 15 bootargs = "earlycon";
16 stdout-path = "serial0:115200n 16 stdout-path = "serial0:115200n8";
17 }; 17 };
18 18
19 memory@80000000 { !! 19 memory {
20 device_type = "memory"; 20 device_type = "memory";
21 reg = <0x0 0x80000000 0x0 0xc0 21 reg = <0x0 0x80000000 0x0 0xc0000000>;
22 }; 22 };
23 23
24 pinmux: pinmux@700008d4 { 24 pinmux: pinmux@700008d4 {
25 status = "okay"; 25 status = "okay";
26 pinctrl-names = "boot"; 26 pinctrl-names = "boot";
27 pinctrl-0 = <&state_boot>; 27 pinctrl-0 = <&state_boot>;
28 28
29 state_boot: pinmux { 29 state_boot: pinmux {
30 pex_l0_rst_n_pa0 { 30 pex_l0_rst_n_pa0 {
31 nvidia,pins = 31 nvidia,pins = "pex_l0_rst_n_pa0";
32 nvidia,functio 32 nvidia,function = "rsvd1";
33 nvidia,pull = 33 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
34 nvidia,tristat 34 nvidia,tristate = <TEGRA_PIN_ENABLE>;
35 nvidia,enable- 35 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
36 nvidia,open-dr 36 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
37 nvidia,io-hv = 37 nvidia,io-hv = <TEGRA_PIN_DISABLE>;
38 }; 38 };
39 pex_l0_clkreq_n_pa1 { 39 pex_l0_clkreq_n_pa1 {
40 nvidia,pins = 40 nvidia,pins = "pex_l0_clkreq_n_pa1";
41 nvidia,functio 41 nvidia,function = "pe0";
42 nvidia,pull = 42 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
43 nvidia,tristat 43 nvidia,tristate = <TEGRA_PIN_DISABLE>;
44 nvidia,enable- 44 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
45 nvidia,open-dr 45 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
46 nvidia,io-hv = 46 nvidia,io-hv = <TEGRA_PIN_ENABLE>;
47 }; 47 };
48 pex_wake_n_pa2 { 48 pex_wake_n_pa2 {
49 nvidia,pins = 49 nvidia,pins = "pex_wake_n_pa2";
50 nvidia,functio 50 nvidia,function = "pe";
51 nvidia,pull = 51 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
52 nvidia,tristat 52 nvidia,tristate = <TEGRA_PIN_DISABLE>;
53 nvidia,enable- 53 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
54 nvidia,open-dr 54 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
55 nvidia,io-hv = 55 nvidia,io-hv = <TEGRA_PIN_ENABLE>;
56 }; 56 };
57 pex_l1_rst_n_pa3 { 57 pex_l1_rst_n_pa3 {
58 nvidia,pins = 58 nvidia,pins = "pex_l1_rst_n_pa3";
59 nvidia,functio 59 nvidia,function = "pe1";
60 nvidia,pull = 60 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
61 nvidia,tristat 61 nvidia,tristate = <TEGRA_PIN_DISABLE>;
62 nvidia,enable- 62 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
63 nvidia,open-dr 63 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
64 nvidia,io-hv = 64 nvidia,io-hv = <TEGRA_PIN_ENABLE>;
65 }; 65 };
66 pex_l1_clkreq_n_pa4 { 66 pex_l1_clkreq_n_pa4 {
67 nvidia,pins = 67 nvidia,pins = "pex_l1_clkreq_n_pa4";
68 nvidia,functio 68 nvidia,function = "pe1";
69 nvidia,pull = 69 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
70 nvidia,tristat 70 nvidia,tristate = <TEGRA_PIN_DISABLE>;
71 nvidia,enable- 71 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
72 nvidia,open-dr 72 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
73 nvidia,io-hv = 73 nvidia,io-hv = <TEGRA_PIN_ENABLE>;
74 }; 74 };
75 sata_led_active_pa5 { 75 sata_led_active_pa5 {
76 nvidia,pins = 76 nvidia,pins = "sata_led_active_pa5";
77 nvidia,pull = 77 nvidia,pull = <TEGRA_PIN_PULL_UP>;
78 nvidia,tristat 78 nvidia,tristate = <TEGRA_PIN_DISABLE>;
79 nvidia,enable- 79 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
80 nvidia,open-dr 80 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
81 }; 81 };
82 pa6 { 82 pa6 {
83 nvidia,pins = 83 nvidia,pins = "pa6";
84 nvidia,functio 84 nvidia,function = "rsvd1";
85 nvidia,pull = 85 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
86 nvidia,tristat 86 nvidia,tristate = <TEGRA_PIN_ENABLE>;
87 nvidia,enable- 87 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
88 nvidia,open-dr 88 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
89 }; 89 };
90 dap1_fs_pb0 { 90 dap1_fs_pb0 {
91 nvidia,pins = 91 nvidia,pins = "dap1_fs_pb0";
92 nvidia,functio 92 nvidia,function = "rsvd1";
93 nvidia,pull = 93 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
94 nvidia,tristat 94 nvidia,tristate = <TEGRA_PIN_ENABLE>;
95 nvidia,enable- 95 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
96 nvidia,open-dr 96 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
97 }; 97 };
98 dap1_din_pb1 { 98 dap1_din_pb1 {
99 nvidia,pins = 99 nvidia,pins = "dap1_din_pb1";
100 nvidia,functio 100 nvidia,function = "rsvd1";
101 nvidia,pull = 101 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
102 nvidia,tristat 102 nvidia,tristate = <TEGRA_PIN_ENABLE>;
103 nvidia,enable- 103 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
104 nvidia,open-dr 104 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
105 }; 105 };
106 dap1_dout_pb2 { 106 dap1_dout_pb2 {
107 nvidia,pins = 107 nvidia,pins = "dap1_dout_pb2";
108 nvidia,functio 108 nvidia,function = "rsvd1";
109 nvidia,pull = 109 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
110 nvidia,tristat 110 nvidia,tristate = <TEGRA_PIN_ENABLE>;
111 nvidia,enable- 111 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
112 nvidia,open-dr 112 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
113 }; 113 };
114 dap1_sclk_pb3 { 114 dap1_sclk_pb3 {
115 nvidia,pins = 115 nvidia,pins = "dap1_sclk_pb3";
116 nvidia,functio 116 nvidia,function = "rsvd1";
117 nvidia,pull = 117 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
118 nvidia,tristat 118 nvidia,tristate = <TEGRA_PIN_ENABLE>;
119 nvidia,enable- 119 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
120 nvidia,open-dr 120 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
121 }; 121 };
122 spi2_mosi_pb4 { 122 spi2_mosi_pb4 {
123 nvidia,pins = 123 nvidia,pins = "spi2_mosi_pb4";
124 nvidia,functio 124 nvidia,function = "rsvd2";
125 nvidia,pull = 125 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
126 nvidia,tristat 126 nvidia,tristate = <TEGRA_PIN_ENABLE>;
127 nvidia,enable- 127 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
128 nvidia,open-dr 128 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
129 }; 129 };
130 spi2_miso_pb5 { 130 spi2_miso_pb5 {
131 nvidia,pins = 131 nvidia,pins = "spi2_miso_pb5";
132 nvidia,functio 132 nvidia,function = "rsvd2";
133 nvidia,pull = 133 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
134 nvidia,tristat 134 nvidia,tristate = <TEGRA_PIN_ENABLE>;
135 nvidia,enable- 135 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
136 nvidia,open-dr 136 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
137 }; 137 };
138 spi2_sck_pb6 { 138 spi2_sck_pb6 {
139 nvidia,pins = 139 nvidia,pins = "spi2_sck_pb6";
140 nvidia,functio 140 nvidia,function = "rsvd2";
141 nvidia,pull = 141 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
142 nvidia,tristat 142 nvidia,tristate = <TEGRA_PIN_ENABLE>;
143 nvidia,enable- 143 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
144 nvidia,open-dr 144 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
145 }; 145 };
146 spi2_cs0_pb7 { 146 spi2_cs0_pb7 {
147 nvidia,pins = 147 nvidia,pins = "spi2_cs0_pb7";
148 nvidia,functio 148 nvidia,function = "rsvd2";
149 nvidia,pull = 149 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
150 nvidia,tristat 150 nvidia,tristate = <TEGRA_PIN_ENABLE>;
151 nvidia,enable- 151 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
152 nvidia,open-dr 152 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
153 }; 153 };
154 spi1_mosi_pc0 { 154 spi1_mosi_pc0 {
155 nvidia,pins = 155 nvidia,pins = "spi1_mosi_pc0";
156 nvidia,functio 156 nvidia,function = "rsvd1";
157 nvidia,pull = 157 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
158 nvidia,tristat 158 nvidia,tristate = <TEGRA_PIN_ENABLE>;
159 nvidia,enable- 159 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
160 nvidia,open-dr 160 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
161 }; 161 };
162 spi1_miso_pc1 { 162 spi1_miso_pc1 {
163 nvidia,pins = 163 nvidia,pins = "spi1_miso_pc1";
164 nvidia,functio 164 nvidia,function = "rsvd1";
165 nvidia,pull = 165 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
166 nvidia,tristat 166 nvidia,tristate = <TEGRA_PIN_ENABLE>;
167 nvidia,enable- 167 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
168 nvidia,open-dr 168 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
169 }; 169 };
170 spi1_sck_pc2 { 170 spi1_sck_pc2 {
171 nvidia,pins = 171 nvidia,pins = "spi1_sck_pc2";
172 nvidia,functio 172 nvidia,function = "rsvd1";
173 nvidia,pull = 173 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
174 nvidia,tristat 174 nvidia,tristate = <TEGRA_PIN_ENABLE>;
175 nvidia,enable- 175 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
176 nvidia,open-dr 176 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
177 }; 177 };
178 spi1_cs0_pc3 { 178 spi1_cs0_pc3 {
179 nvidia,pins = 179 nvidia,pins = "spi1_cs0_pc3";
180 nvidia,functio 180 nvidia,function = "rsvd1";
181 nvidia,pull = 181 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
182 nvidia,tristat 182 nvidia,tristate = <TEGRA_PIN_ENABLE>;
183 nvidia,enable- 183 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
184 nvidia,open-dr 184 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
185 }; 185 };
186 spi1_cs1_pc4 { 186 spi1_cs1_pc4 {
187 nvidia,pins = 187 nvidia,pins = "spi1_cs1_pc4";
188 nvidia,functio 188 nvidia,function = "rsvd1";
189 nvidia,pull = 189 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
190 nvidia,tristat 190 nvidia,tristate = <TEGRA_PIN_ENABLE>;
191 nvidia,enable- 191 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
192 nvidia,open-dr 192 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
193 }; 193 };
194 spi4_sck_pc5 { 194 spi4_sck_pc5 {
195 nvidia,pins = 195 nvidia,pins = "spi4_sck_pc5";
196 nvidia,functio 196 nvidia,function = "rsvd1";
197 nvidia,pull = 197 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
198 nvidia,tristat 198 nvidia,tristate = <TEGRA_PIN_ENABLE>;
199 nvidia,enable- 199 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
200 nvidia,open-dr 200 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
201 }; 201 };
202 spi4_cs0_pc6 { 202 spi4_cs0_pc6 {
203 nvidia,pins = 203 nvidia,pins = "spi4_cs0_pc6";
204 nvidia,functio 204 nvidia,function = "rsvd1";
205 nvidia,pull = 205 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
206 nvidia,tristat 206 nvidia,tristate = <TEGRA_PIN_ENABLE>;
207 nvidia,enable- 207 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
208 nvidia,open-dr 208 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
209 }; 209 };
210 spi4_mosi_pc7 { 210 spi4_mosi_pc7 {
211 nvidia,pins = 211 nvidia,pins = "spi4_mosi_pc7";
212 nvidia,functio 212 nvidia,function = "rsvd1";
213 nvidia,pull = 213 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
214 nvidia,tristat 214 nvidia,tristate = <TEGRA_PIN_ENABLE>;
215 nvidia,enable- 215 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
216 nvidia,open-dr 216 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
217 }; 217 };
218 spi4_miso_pd0 { 218 spi4_miso_pd0 {
219 nvidia,pins = 219 nvidia,pins = "spi4_miso_pd0";
220 nvidia,functio 220 nvidia,function = "rsvd1";
221 nvidia,pull = 221 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
222 nvidia,tristat 222 nvidia,tristate = <TEGRA_PIN_ENABLE>;
223 nvidia,enable- 223 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
224 nvidia,open-dr 224 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
225 }; 225 };
226 uart3_tx_pd1 { 226 uart3_tx_pd1 {
227 nvidia,pins = 227 nvidia,pins = "uart3_tx_pd1";
228 nvidia,functio 228 nvidia,function = "rsvd2";
229 nvidia,pull = 229 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
230 nvidia,tristat 230 nvidia,tristate = <TEGRA_PIN_ENABLE>;
231 nvidia,enable- 231 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
232 nvidia,open-dr 232 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
233 }; 233 };
234 uart3_rx_pd2 { 234 uart3_rx_pd2 {
235 nvidia,pins = 235 nvidia,pins = "uart3_rx_pd2";
236 nvidia,functio 236 nvidia,function = "rsvd2";
237 nvidia,pull = 237 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
238 nvidia,tristat 238 nvidia,tristate = <TEGRA_PIN_ENABLE>;
239 nvidia,enable- 239 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
240 nvidia,open-dr 240 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
241 }; 241 };
242 uart3_rts_pd3 { 242 uart3_rts_pd3 {
243 nvidia,pins = 243 nvidia,pins = "uart3_rts_pd3";
244 nvidia,functio 244 nvidia,function = "rsvd2";
245 nvidia,pull = 245 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
246 nvidia,tristat 246 nvidia,tristate = <TEGRA_PIN_ENABLE>;
247 nvidia,enable- 247 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
248 nvidia,open-dr 248 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
249 }; 249 };
250 uart3_cts_pd4 { 250 uart3_cts_pd4 {
251 nvidia,pins = 251 nvidia,pins = "uart3_cts_pd4";
252 nvidia,pull = 252 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
253 nvidia,tristat 253 nvidia,tristate = <TEGRA_PIN_DISABLE>;
254 nvidia,enable- 254 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
255 nvidia,open-dr 255 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
256 }; 256 };
257 dmic1_clk_pe0 { 257 dmic1_clk_pe0 {
258 nvidia,pins = 258 nvidia,pins = "dmic1_clk_pe0";
259 nvidia,functio 259 nvidia,function = "rsvd2";
260 nvidia,pull = 260 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
261 nvidia,tristat 261 nvidia,tristate = <TEGRA_PIN_ENABLE>;
262 nvidia,enable- 262 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
263 nvidia,open-dr 263 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
264 }; 264 };
265 dmic1_dat_pe1 { 265 dmic1_dat_pe1 {
266 nvidia,pins = 266 nvidia,pins = "dmic1_dat_pe1";
267 nvidia,functio 267 nvidia,function = "rsvd2";
268 nvidia,pull = 268 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
269 nvidia,tristat 269 nvidia,tristate = <TEGRA_PIN_ENABLE>;
270 nvidia,enable- 270 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
271 nvidia,open-dr 271 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
272 }; 272 };
273 dmic2_clk_pe2 { 273 dmic2_clk_pe2 {
274 nvidia,pins = 274 nvidia,pins = "dmic2_clk_pe2";
275 nvidia,functio 275 nvidia,function = "rsvd2";
276 nvidia,pull = 276 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
277 nvidia,tristat 277 nvidia,tristate = <TEGRA_PIN_ENABLE>;
278 nvidia,enable- 278 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
279 nvidia,open-dr 279 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
280 }; 280 };
281 dmic2_dat_pe3 { 281 dmic2_dat_pe3 {
282 nvidia,pins = 282 nvidia,pins = "dmic2_dat_pe3";
283 nvidia,functio 283 nvidia,function = "rsvd2";
284 nvidia,pull = 284 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
285 nvidia,tristat 285 nvidia,tristate = <TEGRA_PIN_ENABLE>;
286 nvidia,enable- 286 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
287 nvidia,open-dr 287 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
288 }; 288 };
289 dmic3_clk_pe4 { 289 dmic3_clk_pe4 {
290 nvidia,pins = 290 nvidia,pins = "dmic3_clk_pe4";
291 nvidia,pull = 291 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
292 nvidia,tristat 292 nvidia,tristate = <TEGRA_PIN_DISABLE>;
293 nvidia,enable- 293 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
294 nvidia,open-dr 294 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
295 }; 295 };
296 dmic3_dat_pe5 { 296 dmic3_dat_pe5 {
297 nvidia,pins = 297 nvidia,pins = "dmic3_dat_pe5";
298 nvidia,functio 298 nvidia,function = "rsvd2";
299 nvidia,pull = 299 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
300 nvidia,tristat 300 nvidia,tristate = <TEGRA_PIN_ENABLE>;
301 nvidia,enable- 301 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
302 nvidia,open-dr 302 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
303 }; 303 };
304 pe6 { 304 pe6 {
305 nvidia,pins = 305 nvidia,pins = "pe6";
306 nvidia,pull = 306 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
307 nvidia,tristat 307 nvidia,tristate = <TEGRA_PIN_DISABLE>;
308 nvidia,enable- 308 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
309 nvidia,open-dr 309 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
310 }; 310 };
311 pe7 { 311 pe7 {
312 nvidia,pins = 312 nvidia,pins = "pe7";
313 nvidia,functio 313 nvidia,function = "pwm3";
314 nvidia,pull = 314 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
315 nvidia,tristat 315 nvidia,tristate = <TEGRA_PIN_DISABLE>;
316 nvidia,enable- 316 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
317 nvidia,open-dr 317 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
318 }; 318 };
319 gen3_i2c_scl_pf0 { 319 gen3_i2c_scl_pf0 {
320 nvidia,pins = 320 nvidia,pins = "gen3_i2c_scl_pf0";
321 nvidia,functio 321 nvidia,function = "i2c3";
322 nvidia,pull = 322 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
323 nvidia,tristat 323 nvidia,tristate = <TEGRA_PIN_DISABLE>;
324 nvidia,enable- 324 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
325 nvidia,open-dr 325 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
326 nvidia,io-hv = 326 nvidia,io-hv = <TEGRA_PIN_DISABLE>;
327 }; 327 };
328 gen3_i2c_sda_pf1 { 328 gen3_i2c_sda_pf1 {
329 nvidia,pins = 329 nvidia,pins = "gen3_i2c_sda_pf1";
330 nvidia,functio 330 nvidia,function = "i2c3";
331 nvidia,pull = 331 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
332 nvidia,tristat 332 nvidia,tristate = <TEGRA_PIN_DISABLE>;
333 nvidia,enable- 333 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
334 nvidia,open-dr 334 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
335 nvidia,io-hv = 335 nvidia,io-hv = <TEGRA_PIN_DISABLE>;
336 }; 336 };
337 uart2_tx_pg0 { 337 uart2_tx_pg0 {
338 nvidia,pins = 338 nvidia,pins = "uart2_tx_pg0";
339 nvidia,pull = 339 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
340 nvidia,tristat 340 nvidia,tristate = <TEGRA_PIN_DISABLE>;
341 nvidia,enable- 341 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
342 nvidia,open-dr 342 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
343 }; 343 };
344 uart2_rx_pg1 { 344 uart2_rx_pg1 {
345 nvidia,pins = 345 nvidia,pins = "uart2_rx_pg1";
346 nvidia,functio 346 nvidia,function = "uartb";
347 nvidia,pull = 347 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
348 nvidia,tristat 348 nvidia,tristate = <TEGRA_PIN_ENABLE>;
349 nvidia,enable- 349 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
350 nvidia,open-dr 350 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
351 }; 351 };
352 uart2_rts_pg2 { 352 uart2_rts_pg2 {
353 nvidia,pins = 353 nvidia,pins = "uart2_rts_pg2";
354 nvidia,functio 354 nvidia,function = "rsvd2";
355 nvidia,pull = 355 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
356 nvidia,tristat 356 nvidia,tristate = <TEGRA_PIN_ENABLE>;
357 nvidia,enable- 357 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
358 nvidia,open-dr 358 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
359 }; 359 };
360 uart2_cts_pg3 { 360 uart2_cts_pg3 {
361 nvidia,pins = 361 nvidia,pins = "uart2_cts_pg3";
362 nvidia,functio 362 nvidia,function = "rsvd2";
363 nvidia,pull = 363 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
364 nvidia,tristat 364 nvidia,tristate = <TEGRA_PIN_ENABLE>;
365 nvidia,enable- 365 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
366 nvidia,open-dr 366 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
367 }; 367 };
368 wifi_en_ph0 { 368 wifi_en_ph0 {
369 nvidia,pins = 369 nvidia,pins = "wifi_en_ph0";
370 nvidia,pull = 370 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
371 nvidia,tristat 371 nvidia,tristate = <TEGRA_PIN_DISABLE>;
372 nvidia,enable- 372 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
373 nvidia,open-dr 373 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
374 }; 374 };
375 wifi_rst_ph1 { 375 wifi_rst_ph1 {
376 nvidia,pins = 376 nvidia,pins = "wifi_rst_ph1";
377 nvidia,functio 377 nvidia,function = "rsvd0";
378 nvidia,pull = 378 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
379 nvidia,tristat 379 nvidia,tristate = <TEGRA_PIN_ENABLE>;
380 nvidia,enable- 380 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
381 nvidia,open-dr 381 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
382 }; 382 };
383 wifi_wake_ap_ph2 { 383 wifi_wake_ap_ph2 {
384 nvidia,pins = 384 nvidia,pins = "wifi_wake_ap_ph2";
385 nvidia,pull = 385 nvidia,pull = <TEGRA_PIN_PULL_UP>;
386 nvidia,tristat 386 nvidia,tristate = <TEGRA_PIN_DISABLE>;
387 nvidia,enable- 387 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
388 nvidia,open-dr 388 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
389 }; 389 };
390 ap_wake_bt_ph3 { 390 ap_wake_bt_ph3 {
391 nvidia,pins = 391 nvidia,pins = "ap_wake_bt_ph3";
392 nvidia,pull = 392 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
393 nvidia,tristat 393 nvidia,tristate = <TEGRA_PIN_DISABLE>;
394 nvidia,enable- 394 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
395 nvidia,open-dr 395 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
396 }; 396 };
397 bt_rst_ph4 { 397 bt_rst_ph4 {
398 nvidia,pins = 398 nvidia,pins = "bt_rst_ph4";
399 nvidia,pull = 399 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
400 nvidia,tristat 400 nvidia,tristate = <TEGRA_PIN_DISABLE>;
401 nvidia,enable- 401 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
402 nvidia,open-dr 402 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
403 }; 403 };
404 bt_wake_ap_ph5 { 404 bt_wake_ap_ph5 {
405 nvidia,pins = 405 nvidia,pins = "bt_wake_ap_ph5";
406 nvidia,pull = 406 nvidia,pull = <TEGRA_PIN_PULL_UP>;
407 nvidia,tristat 407 nvidia,tristate = <TEGRA_PIN_DISABLE>;
408 nvidia,enable- 408 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
409 nvidia,open-dr 409 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
410 }; 410 };
411 ph6 { 411 ph6 {
412 nvidia,pins = 412 nvidia,pins = "ph6";
413 nvidia,functio 413 nvidia,function = "rsvd0";
414 nvidia,pull = 414 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
415 nvidia,tristat 415 nvidia,tristate = <TEGRA_PIN_ENABLE>;
416 nvidia,enable- 416 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
417 nvidia,open-dr 417 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
418 }; 418 };
419 ap_wake_nfc_ph7 { 419 ap_wake_nfc_ph7 {
420 nvidia,pins = 420 nvidia,pins = "ap_wake_nfc_ph7";
421 nvidia,functio 421 nvidia,function = "rsvd0";
422 nvidia,pull = 422 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
423 nvidia,tristat 423 nvidia,tristate = <TEGRA_PIN_ENABLE>;
424 nvidia,enable- 424 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
425 nvidia,open-dr 425 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
426 }; 426 };
427 nfc_en_pi0 { 427 nfc_en_pi0 {
428 nvidia,pins = 428 nvidia,pins = "nfc_en_pi0";
429 nvidia,functio 429 nvidia,function = "rsvd0";
430 nvidia,pull = 430 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
431 nvidia,tristat 431 nvidia,tristate = <TEGRA_PIN_ENABLE>;
432 nvidia,enable- 432 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
433 nvidia,open-dr 433 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
434 }; 434 };
435 nfc_int_pi1 { 435 nfc_int_pi1 {
436 nvidia,pins = 436 nvidia,pins = "nfc_int_pi1";
437 nvidia,functio 437 nvidia,function = "rsvd0";
438 nvidia,pull = 438 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
439 nvidia,tristat 439 nvidia,tristate = <TEGRA_PIN_ENABLE>;
440 nvidia,enable- 440 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
441 nvidia,open-dr 441 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
442 }; 442 };
443 gps_en_pi2 { 443 gps_en_pi2 {
444 nvidia,pins = 444 nvidia,pins = "gps_en_pi2";
445 nvidia,functio 445 nvidia,function = "rsvd0";
446 nvidia,pull = 446 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
447 nvidia,tristat 447 nvidia,tristate = <TEGRA_PIN_ENABLE>;
448 nvidia,enable- 448 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
449 nvidia,open-dr 449 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
450 }; 450 };
451 gps_rst_pi3 { 451 gps_rst_pi3 {
452 nvidia,pins = 452 nvidia,pins = "gps_rst_pi3";
453 nvidia,functio 453 nvidia,function = "rsvd0";
454 nvidia,pull = 454 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
455 nvidia,tristat 455 nvidia,tristate = <TEGRA_PIN_ENABLE>;
456 nvidia,enable- 456 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
457 nvidia,open-dr 457 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
458 }; 458 };
459 uart4_tx_pi4 { 459 uart4_tx_pi4 {
460 nvidia,pins = 460 nvidia,pins = "uart4_tx_pi4";
461 nvidia,functio 461 nvidia,function = "uartd";
462 nvidia,pull = 462 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
463 nvidia,tristat 463 nvidia,tristate = <TEGRA_PIN_DISABLE>;
464 nvidia,enable- 464 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
465 nvidia,open-dr 465 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
466 }; 466 };
467 uart4_rx_pi5 { 467 uart4_rx_pi5 {
468 nvidia,pins = 468 nvidia,pins = "uart4_rx_pi5";
469 nvidia,functio 469 nvidia,function = "uartd";
470 nvidia,pull = 470 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
471 nvidia,tristat 471 nvidia,tristate = <TEGRA_PIN_DISABLE>;
472 nvidia,enable- 472 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
473 nvidia,open-dr 473 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
474 }; 474 };
475 uart4_rts_pi6 { 475 uart4_rts_pi6 {
476 nvidia,pins = 476 nvidia,pins = "uart4_rts_pi6";
477 nvidia,functio 477 nvidia,function = "uartd";
478 nvidia,pull = 478 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
479 nvidia,tristat 479 nvidia,tristate = <TEGRA_PIN_DISABLE>;
480 nvidia,enable- 480 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
481 nvidia,open-dr 481 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
482 }; 482 };
483 uart4_cts_pi7 { 483 uart4_cts_pi7 {
484 nvidia,pins = 484 nvidia,pins = "uart4_cts_pi7";
485 nvidia,functio 485 nvidia,function = "uartd";
486 nvidia,pull = 486 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
487 nvidia,tristat 487 nvidia,tristate = <TEGRA_PIN_DISABLE>;
488 nvidia,enable- 488 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
489 nvidia,open-dr 489 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
490 }; 490 };
491 gen1_i2c_sda_pj0 { 491 gen1_i2c_sda_pj0 {
492 nvidia,pins = 492 nvidia,pins = "gen1_i2c_sda_pj0";
493 nvidia,functio 493 nvidia,function = "i2c1";
494 nvidia,pull = 494 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
495 nvidia,tristat 495 nvidia,tristate = <TEGRA_PIN_DISABLE>;
496 nvidia,enable- 496 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
497 nvidia,open-dr 497 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
498 nvidia,io-hv = 498 nvidia,io-hv = <TEGRA_PIN_DISABLE>;
499 }; 499 };
500 gen1_i2c_scl_pj1 { 500 gen1_i2c_scl_pj1 {
501 nvidia,pins = 501 nvidia,pins = "gen1_i2c_scl_pj1";
502 nvidia,functio 502 nvidia,function = "i2c1";
503 nvidia,pull = 503 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
504 nvidia,tristat 504 nvidia,tristate = <TEGRA_PIN_DISABLE>;
505 nvidia,enable- 505 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
506 nvidia,open-dr 506 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
507 nvidia,io-hv = 507 nvidia,io-hv = <TEGRA_PIN_DISABLE>;
508 }; 508 };
509 gen2_i2c_scl_pj2 { 509 gen2_i2c_scl_pj2 {
510 nvidia,pins = 510 nvidia,pins = "gen2_i2c_scl_pj2";
511 nvidia,functio 511 nvidia,function = "i2c2";
512 nvidia,pull = 512 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
513 nvidia,tristat 513 nvidia,tristate = <TEGRA_PIN_DISABLE>;
514 nvidia,enable- 514 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
515 nvidia,open-dr 515 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
516 nvidia,io-hv = 516 nvidia,io-hv = <TEGRA_PIN_ENABLE>;
517 }; 517 };
518 gen2_i2c_sda_pj3 { 518 gen2_i2c_sda_pj3 {
519 nvidia,pins = 519 nvidia,pins = "gen2_i2c_sda_pj3";
520 nvidia,functio 520 nvidia,function = "i2c2";
521 nvidia,pull = 521 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
522 nvidia,tristat 522 nvidia,tristate = <TEGRA_PIN_DISABLE>;
523 nvidia,enable- 523 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
524 nvidia,open-dr 524 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
525 nvidia,io-hv = 525 nvidia,io-hv = <TEGRA_PIN_ENABLE>;
526 }; 526 };
527 dap4_fs_pj4 { 527 dap4_fs_pj4 {
528 nvidia,pins = 528 nvidia,pins = "dap4_fs_pj4";
529 nvidia,functio 529 nvidia,function = "rsvd1";
530 nvidia,pull = 530 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
531 nvidia,tristat 531 nvidia,tristate = <TEGRA_PIN_ENABLE>;
532 nvidia,enable- 532 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
533 nvidia,open-dr 533 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
534 }; 534 };
535 dap4_din_pj5 { 535 dap4_din_pj5 {
536 nvidia,pins = 536 nvidia,pins = "dap4_din_pj5";
537 nvidia,functio 537 nvidia,function = "rsvd1";
538 nvidia,pull = 538 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
539 nvidia,tristat 539 nvidia,tristate = <TEGRA_PIN_ENABLE>;
540 nvidia,enable- 540 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
541 nvidia,open-dr 541 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
542 }; 542 };
543 dap4_dout_pj6 { 543 dap4_dout_pj6 {
544 nvidia,pins = 544 nvidia,pins = "dap4_dout_pj6";
545 nvidia,functio 545 nvidia,function = "rsvd1";
546 nvidia,pull = 546 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
547 nvidia,tristat 547 nvidia,tristate = <TEGRA_PIN_ENABLE>;
548 nvidia,enable- 548 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
549 nvidia,open-dr 549 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
550 }; 550 };
551 dap4_sclk_pj7 { 551 dap4_sclk_pj7 {
552 nvidia,pins = 552 nvidia,pins = "dap4_sclk_pj7";
553 nvidia,functio 553 nvidia,function = "rsvd1";
554 nvidia,pull = 554 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
555 nvidia,tristat 555 nvidia,tristate = <TEGRA_PIN_ENABLE>;
556 nvidia,enable- 556 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
557 nvidia,open-dr 557 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
558 }; 558 };
559 pk0 { 559 pk0 {
560 nvidia,pins = 560 nvidia,pins = "pk0";
561 nvidia,functio 561 nvidia,function = "rsvd2";
562 nvidia,pull = 562 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
563 nvidia,tristat 563 nvidia,tristate = <TEGRA_PIN_ENABLE>;
564 nvidia,enable- 564 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
565 nvidia,open-dr 565 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
566 }; 566 };
567 pk1 { 567 pk1 {
568 nvidia,pins = 568 nvidia,pins = "pk1";
569 nvidia,functio 569 nvidia,function = "rsvd2";
570 nvidia,pull = 570 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
571 nvidia,tristat 571 nvidia,tristate = <TEGRA_PIN_ENABLE>;
572 nvidia,enable- 572 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
573 nvidia,open-dr 573 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
574 }; 574 };
575 pk2 { 575 pk2 {
576 nvidia,pins = 576 nvidia,pins = "pk2";
577 nvidia,functio 577 nvidia,function = "rsvd2";
578 nvidia,pull = 578 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
579 nvidia,tristat 579 nvidia,tristate = <TEGRA_PIN_ENABLE>;
580 nvidia,enable- 580 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
581 nvidia,open-dr 581 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
582 }; 582 };
583 pk3 { 583 pk3 {
584 nvidia,pins = 584 nvidia,pins = "pk3";
585 nvidia,functio 585 nvidia,function = "rsvd2";
586 nvidia,pull = 586 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
587 nvidia,tristat 587 nvidia,tristate = <TEGRA_PIN_ENABLE>;
588 nvidia,enable- 588 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
589 nvidia,open-dr 589 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
590 }; 590 };
591 pk4 { 591 pk4 {
592 nvidia,pins = 592 nvidia,pins = "pk4";
593 nvidia,functio 593 nvidia,function = "rsvd1";
594 nvidia,pull = 594 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
595 nvidia,tristat 595 nvidia,tristate = <TEGRA_PIN_ENABLE>;
596 nvidia,enable- 596 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
597 nvidia,open-dr 597 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
598 }; 598 };
599 pk5 { 599 pk5 {
600 nvidia,pins = 600 nvidia,pins = "pk5";
601 nvidia,functio 601 nvidia,function = "rsvd1";
602 nvidia,pull = 602 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
603 nvidia,tristat 603 nvidia,tristate = <TEGRA_PIN_ENABLE>;
604 nvidia,enable- 604 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
605 nvidia,open-dr 605 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
606 }; 606 };
607 pk6 { 607 pk6 {
608 nvidia,pins = 608 nvidia,pins = "pk6";
609 nvidia,functio 609 nvidia,function = "rsvd1";
610 nvidia,pull = 610 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
611 nvidia,tristat 611 nvidia,tristate = <TEGRA_PIN_ENABLE>;
612 nvidia,enable- 612 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
613 nvidia,open-dr 613 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
614 }; 614 };
615 pk7 { 615 pk7 {
616 nvidia,pins = 616 nvidia,pins = "pk7";
617 nvidia,functio 617 nvidia,function = "rsvd1";
618 nvidia,pull = 618 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
619 nvidia,tristat 619 nvidia,tristate = <TEGRA_PIN_ENABLE>;
620 nvidia,enable- 620 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
621 nvidia,open-dr 621 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
622 }; 622 };
623 pl0 { 623 pl0 {
624 nvidia,pins = 624 nvidia,pins = "pl0";
625 nvidia,functio 625 nvidia,function = "rsvd0";
626 nvidia,pull = 626 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
627 nvidia,tristat 627 nvidia,tristate = <TEGRA_PIN_ENABLE>;
628 nvidia,enable- 628 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
629 nvidia,open-dr 629 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
630 }; 630 };
631 pl1 { 631 pl1 {
632 nvidia,pins = 632 nvidia,pins = "pl1";
633 nvidia,functio 633 nvidia,function = "rsvd1";
634 nvidia,pull = 634 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
635 nvidia,tristat 635 nvidia,tristate = <TEGRA_PIN_ENABLE>;
636 nvidia,enable- 636 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
637 nvidia,open-dr 637 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
638 }; 638 };
639 sdmmc1_clk_pm0 { 639 sdmmc1_clk_pm0 {
640 nvidia,pins = 640 nvidia,pins = "sdmmc1_clk_pm0";
641 nvidia,functio 641 nvidia,function = "rsvd1";
642 nvidia,pull = 642 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
643 nvidia,tristat 643 nvidia,tristate = <TEGRA_PIN_ENABLE>;
644 nvidia,enable- 644 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
645 nvidia,open-dr 645 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
646 }; 646 };
647 sdmmc1_cmd_pm1 { 647 sdmmc1_cmd_pm1 {
648 nvidia,pins = 648 nvidia,pins = "sdmmc1_cmd_pm1";
649 nvidia,functio 649 nvidia,function = "rsvd2";
650 nvidia,pull = 650 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
651 nvidia,tristat 651 nvidia,tristate = <TEGRA_PIN_ENABLE>;
652 nvidia,enable- 652 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
653 nvidia,open-dr 653 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
654 }; 654 };
655 sdmmc1_dat3_pm2 { 655 sdmmc1_dat3_pm2 {
656 nvidia,pins = 656 nvidia,pins = "sdmmc1_dat3_pm2";
657 nvidia,functio 657 nvidia,function = "rsvd2";
658 nvidia,pull = 658 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
659 nvidia,tristat 659 nvidia,tristate = <TEGRA_PIN_ENABLE>;
660 nvidia,enable- 660 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
661 nvidia,open-dr 661 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
662 }; 662 };
663 sdmmc1_dat2_pm3 { 663 sdmmc1_dat2_pm3 {
664 nvidia,pins = 664 nvidia,pins = "sdmmc1_dat2_pm3";
665 nvidia,functio 665 nvidia,function = "rsvd2";
666 nvidia,pull = 666 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
667 nvidia,tristat 667 nvidia,tristate = <TEGRA_PIN_ENABLE>;
668 nvidia,enable- 668 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
669 nvidia,open-dr 669 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
670 }; 670 };
671 sdmmc1_dat1_pm4 { 671 sdmmc1_dat1_pm4 {
672 nvidia,pins = 672 nvidia,pins = "sdmmc1_dat1_pm4";
673 nvidia,functio 673 nvidia,function = "rsvd2";
674 nvidia,pull = 674 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
675 nvidia,tristat 675 nvidia,tristate = <TEGRA_PIN_ENABLE>;
676 nvidia,enable- 676 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
677 nvidia,open-dr 677 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
678 }; 678 };
679 sdmmc1_dat0_pm5 { 679 sdmmc1_dat0_pm5 {
680 nvidia,pins = 680 nvidia,pins = "sdmmc1_dat0_pm5";
681 nvidia,functio 681 nvidia,function = "rsvd1";
682 nvidia,pull = 682 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
683 nvidia,tristat 683 nvidia,tristate = <TEGRA_PIN_ENABLE>;
684 nvidia,enable- 684 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
685 nvidia,open-dr 685 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
686 }; 686 };
687 sdmmc3_clk_pp0 { 687 sdmmc3_clk_pp0 {
688 nvidia,pins = 688 nvidia,pins = "sdmmc3_clk_pp0";
689 nvidia,functio 689 nvidia,function = "rsvd1";
690 nvidia,pull = 690 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
691 nvidia,tristat 691 nvidia,tristate = <TEGRA_PIN_ENABLE>;
692 nvidia,enable- 692 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
693 nvidia,open-dr 693 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
694 }; 694 };
695 sdmmc3_cmd_pp1 { 695 sdmmc3_cmd_pp1 {
696 nvidia,pins = 696 nvidia,pins = "sdmmc3_cmd_pp1";
697 nvidia,functio 697 nvidia,function = "rsvd1";
698 nvidia,pull = 698 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
699 nvidia,tristat 699 nvidia,tristate = <TEGRA_PIN_ENABLE>;
700 nvidia,enable- 700 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
701 nvidia,open-dr 701 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
702 }; 702 };
703 sdmmc3_dat3_pp2 { 703 sdmmc3_dat3_pp2 {
704 nvidia,pins = 704 nvidia,pins = "sdmmc3_dat3_pp2";
705 nvidia,functio 705 nvidia,function = "rsvd1";
706 nvidia,pull = 706 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
707 nvidia,tristat 707 nvidia,tristate = <TEGRA_PIN_ENABLE>;
708 nvidia,enable- 708 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
709 nvidia,open-dr 709 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
710 }; 710 };
711 sdmmc3_dat2_pp3 { 711 sdmmc3_dat2_pp3 {
712 nvidia,pins = 712 nvidia,pins = "sdmmc3_dat2_pp3";
713 nvidia,functio 713 nvidia,function = "rsvd1";
714 nvidia,pull = 714 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
715 nvidia,tristat 715 nvidia,tristate = <TEGRA_PIN_ENABLE>;
716 nvidia,enable- 716 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
717 nvidia,open-dr 717 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
718 }; 718 };
719 sdmmc3_dat1_pp4 { 719 sdmmc3_dat1_pp4 {
720 nvidia,pins = 720 nvidia,pins = "sdmmc3_dat1_pp4";
721 nvidia,functio 721 nvidia,function = "rsvd1";
722 nvidia,pull = 722 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
723 nvidia,tristat 723 nvidia,tristate = <TEGRA_PIN_ENABLE>;
724 nvidia,enable- 724 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
725 nvidia,open-dr 725 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
726 }; 726 };
727 sdmmc3_dat0_pp5 { 727 sdmmc3_dat0_pp5 {
728 nvidia,pins = 728 nvidia,pins = "sdmmc3_dat0_pp5";
729 nvidia,functio 729 nvidia,function = "rsvd1";
730 nvidia,pull = 730 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
731 nvidia,tristat 731 nvidia,tristate = <TEGRA_PIN_ENABLE>;
732 nvidia,enable- 732 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
733 nvidia,open-dr 733 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
734 }; 734 };
735 cam1_mclk_ps0 { 735 cam1_mclk_ps0 {
736 nvidia,pins = 736 nvidia,pins = "cam1_mclk_ps0";
737 nvidia,functio 737 nvidia,function = "rsvd1";
738 nvidia,pull = 738 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
739 nvidia,tristat 739 nvidia,tristate = <TEGRA_PIN_ENABLE>;
740 nvidia,enable- 740 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
741 nvidia,open-dr 741 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
742 }; 742 };
743 cam2_mclk_ps1 { 743 cam2_mclk_ps1 {
744 nvidia,pins = 744 nvidia,pins = "cam2_mclk_ps1";
745 nvidia,functio 745 nvidia,function = "rsvd1";
746 nvidia,pull = 746 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
747 nvidia,tristat 747 nvidia,tristate = <TEGRA_PIN_ENABLE>;
748 nvidia,enable- 748 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
749 nvidia,open-dr 749 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
750 }; 750 };
751 cam_i2c_scl_ps2 { 751 cam_i2c_scl_ps2 {
752 nvidia,pins = 752 nvidia,pins = "cam_i2c_scl_ps2";
753 nvidia,functio 753 nvidia,function = "rsvd2";
754 nvidia,pull = 754 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
755 nvidia,tristat 755 nvidia,tristate = <TEGRA_PIN_ENABLE>;
756 nvidia,enable- 756 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
757 nvidia,open-dr 757 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
758 nvidia,io-hv = 758 nvidia,io-hv = <TEGRA_PIN_DISABLE>;
759 }; 759 };
760 cam_i2c_sda_ps3 { 760 cam_i2c_sda_ps3 {
761 nvidia,pins = 761 nvidia,pins = "cam_i2c_sda_ps3";
762 nvidia,functio 762 nvidia,function = "rsvd2";
763 nvidia,pull = 763 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
764 nvidia,tristat 764 nvidia,tristate = <TEGRA_PIN_ENABLE>;
765 nvidia,enable- 765 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
766 nvidia,open-dr 766 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
767 nvidia,io-hv = 767 nvidia,io-hv = <TEGRA_PIN_DISABLE>;
768 }; 768 };
769 cam_rst_ps4 { 769 cam_rst_ps4 {
770 nvidia,pins = 770 nvidia,pins = "cam_rst_ps4";
771 nvidia,functio 771 nvidia,function = "rsvd1";
772 nvidia,pull = 772 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
773 nvidia,tristat 773 nvidia,tristate = <TEGRA_PIN_ENABLE>;
774 nvidia,enable- 774 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
775 nvidia,open-dr 775 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
776 }; 776 };
777 cam_af_en_ps5 { 777 cam_af_en_ps5 {
778 nvidia,pins = 778 nvidia,pins = "cam_af_en_ps5";
779 nvidia,functio 779 nvidia,function = "rsvd2";
780 nvidia,pull = 780 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
781 nvidia,tristat 781 nvidia,tristate = <TEGRA_PIN_ENABLE>;
782 nvidia,enable- 782 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
783 nvidia,open-dr 783 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
784 }; 784 };
785 cam_flash_en_ps6 { 785 cam_flash_en_ps6 {
786 nvidia,pins = 786 nvidia,pins = "cam_flash_en_ps6";
787 nvidia,functio 787 nvidia,function = "rsvd2";
788 nvidia,pull = 788 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
789 nvidia,tristat 789 nvidia,tristate = <TEGRA_PIN_ENABLE>;
790 nvidia,enable- 790 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
791 nvidia,open-dr 791 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
792 }; 792 };
793 cam1_pwdn_ps7 { 793 cam1_pwdn_ps7 {
794 nvidia,pins = 794 nvidia,pins = "cam1_pwdn_ps7";
795 nvidia,functio 795 nvidia,function = "rsvd1";
796 nvidia,pull = 796 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
797 nvidia,tristat 797 nvidia,tristate = <TEGRA_PIN_ENABLE>;
798 nvidia,enable- 798 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
799 nvidia,open-dr 799 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
800 }; 800 };
801 cam2_pwdn_pt0 { 801 cam2_pwdn_pt0 {
802 nvidia,pins = 802 nvidia,pins = "cam2_pwdn_pt0";
803 nvidia,functio 803 nvidia,function = "rsvd1";
804 nvidia,pull = 804 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
805 nvidia,tristat 805 nvidia,tristate = <TEGRA_PIN_ENABLE>;
806 nvidia,enable- 806 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
807 nvidia,open-dr 807 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
808 }; 808 };
809 cam1_strobe_pt1 { 809 cam1_strobe_pt1 {
810 nvidia,pins = 810 nvidia,pins = "cam1_strobe_pt1";
811 nvidia,functio 811 nvidia,function = "rsvd1";
812 nvidia,pull = 812 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
813 nvidia,tristat 813 nvidia,tristate = <TEGRA_PIN_ENABLE>;
814 nvidia,enable- 814 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
815 nvidia,open-dr 815 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
816 }; 816 };
817 uart1_tx_pu0 { 817 uart1_tx_pu0 {
818 nvidia,pins = 818 nvidia,pins = "uart1_tx_pu0";
819 nvidia,functio 819 nvidia,function = "uarta";
820 nvidia,pull = 820 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
821 nvidia,tristat 821 nvidia,tristate = <TEGRA_PIN_DISABLE>;
822 nvidia,enable- 822 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
823 nvidia,open-dr 823 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
824 }; 824 };
825 uart1_rx_pu1 { 825 uart1_rx_pu1 {
826 nvidia,pins = 826 nvidia,pins = "uart1_rx_pu1";
827 nvidia,functio 827 nvidia,function = "uarta";
828 nvidia,pull = 828 nvidia,pull = <TEGRA_PIN_PULL_UP>;
829 nvidia,tristat 829 nvidia,tristate = <TEGRA_PIN_DISABLE>;
830 nvidia,enable- 830 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
831 nvidia,open-dr 831 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
832 }; 832 };
833 uart1_rts_pu2 { 833 uart1_rts_pu2 {
834 nvidia,pins = 834 nvidia,pins = "uart1_rts_pu2";
835 nvidia,functio 835 nvidia,function = "uarta";
836 nvidia,pull = 836 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
837 nvidia,tristat 837 nvidia,tristate = <TEGRA_PIN_DISABLE>;
838 nvidia,enable- 838 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
839 nvidia,open-dr 839 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
840 }; 840 };
841 uart1_cts_pu3 { 841 uart1_cts_pu3 {
842 nvidia,pins = 842 nvidia,pins = "uart1_cts_pu3";
843 nvidia,functio 843 nvidia,function = "uarta";
844 nvidia,pull = 844 nvidia,pull = <TEGRA_PIN_PULL_UP>;
845 nvidia,tristat 845 nvidia,tristate = <TEGRA_PIN_DISABLE>;
846 nvidia,enable- 846 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
847 nvidia,open-dr 847 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
848 }; 848 };
849 lcd_bl_pwm_pv0 { 849 lcd_bl_pwm_pv0 {
850 nvidia,pins = 850 nvidia,pins = "lcd_bl_pwm_pv0";
851 nvidia,functio 851 nvidia,function = "pwm0";
852 nvidia,pull = 852 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
853 nvidia,tristat 853 nvidia,tristate = <TEGRA_PIN_DISABLE>;
854 nvidia,enable- 854 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
855 nvidia,open-dr 855 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
856 }; 856 };
857 lcd_bl_en_pv1 { 857 lcd_bl_en_pv1 {
858 nvidia,pins = 858 nvidia,pins = "lcd_bl_en_pv1";
859 nvidia,functio 859 nvidia,function = "rsvd0";
860 nvidia,pull = 860 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
861 nvidia,tristat 861 nvidia,tristate = <TEGRA_PIN_ENABLE>;
862 nvidia,enable- 862 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
863 nvidia,open-dr 863 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
864 }; 864 };
865 lcd_rst_pv2 { 865 lcd_rst_pv2 {
866 nvidia,pins = 866 nvidia,pins = "lcd_rst_pv2";
867 nvidia,functio 867 nvidia,function = "rsvd0";
868 nvidia,pull = 868 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
869 nvidia,tristat 869 nvidia,tristate = <TEGRA_PIN_ENABLE>;
870 nvidia,enable- 870 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
871 nvidia,open-dr 871 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
872 }; 872 };
873 lcd_gpio1_pv3 { 873 lcd_gpio1_pv3 {
874 nvidia,pins = 874 nvidia,pins = "lcd_gpio1_pv3";
875 nvidia,functio 875 nvidia,function = "rsvd1";
876 nvidia,pull = 876 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
877 nvidia,tristat 877 nvidia,tristate = <TEGRA_PIN_ENABLE>;
878 nvidia,enable- 878 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
879 nvidia,open-dr 879 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
880 }; 880 };
881 lcd_gpio2_pv4 { 881 lcd_gpio2_pv4 {
882 nvidia,pins = 882 nvidia,pins = "lcd_gpio2_pv4";
883 nvidia,functio 883 nvidia,function = "pwm1";
884 nvidia,pull = 884 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
885 nvidia,tristat 885 nvidia,tristate = <TEGRA_PIN_DISABLE>;
886 nvidia,enable- 886 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
887 nvidia,open-dr 887 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
888 }; 888 };
889 ap_ready_pv5 { 889 ap_ready_pv5 {
890 nvidia,pins = 890 nvidia,pins = "ap_ready_pv5";
891 nvidia,functio 891 nvidia,function = "rsvd0";
892 nvidia,pull = 892 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
893 nvidia,tristat 893 nvidia,tristate = <TEGRA_PIN_ENABLE>;
894 nvidia,enable- 894 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
895 nvidia,open-dr 895 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
896 }; 896 };
897 touch_rst_pv6 { 897 touch_rst_pv6 {
898 nvidia,pins = 898 nvidia,pins = "touch_rst_pv6";
899 nvidia,functio 899 nvidia,function = "rsvd0";
900 nvidia,pull = 900 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
901 nvidia,tristat 901 nvidia,tristate = <TEGRA_PIN_ENABLE>;
902 nvidia,enable- 902 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
903 nvidia,open-dr 903 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
904 }; 904 };
905 touch_clk_pv7 { 905 touch_clk_pv7 {
906 nvidia,pins = 906 nvidia,pins = "touch_clk_pv7";
907 nvidia,functio 907 nvidia,function = "rsvd1";
908 nvidia,pull = 908 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
909 nvidia,tristat 909 nvidia,tristate = <TEGRA_PIN_ENABLE>;
910 nvidia,enable- 910 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
911 nvidia,open-dr 911 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
912 }; 912 };
913 modem_wake_ap_px0 { 913 modem_wake_ap_px0 {
914 nvidia,pins = 914 nvidia,pins = "modem_wake_ap_px0";
915 nvidia,functio 915 nvidia,function = "rsvd0";
916 nvidia,pull = 916 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
917 nvidia,tristat 917 nvidia,tristate = <TEGRA_PIN_ENABLE>;
918 nvidia,enable- 918 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
919 nvidia,open-dr 919 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
920 }; 920 };
921 touch_int_px1 { 921 touch_int_px1 {
922 nvidia,pins = 922 nvidia,pins = "touch_int_px1";
923 nvidia,functio 923 nvidia,function = "rsvd0";
924 nvidia,pull = 924 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
925 nvidia,tristat 925 nvidia,tristate = <TEGRA_PIN_ENABLE>;
926 nvidia,enable- 926 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
927 nvidia,open-dr 927 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
928 }; 928 };
929 motion_int_px2 { 929 motion_int_px2 {
930 nvidia,pins = 930 nvidia,pins = "motion_int_px2";
931 nvidia,functio 931 nvidia,function = "rsvd0";
932 nvidia,pull = 932 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
933 nvidia,tristat 933 nvidia,tristate = <TEGRA_PIN_ENABLE>;
934 nvidia,enable- 934 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
935 nvidia,open-dr 935 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
936 }; 936 };
937 als_prox_int_px3 { 937 als_prox_int_px3 {
938 nvidia,pins = 938 nvidia,pins = "als_prox_int_px3";
939 nvidia,functio 939 nvidia,function = "rsvd0";
940 nvidia,pull = 940 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
941 nvidia,tristat 941 nvidia,tristate = <TEGRA_PIN_ENABLE>;
942 nvidia,enable- 942 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
943 nvidia,open-dr 943 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
944 }; 944 };
945 temp_alert_px4 { 945 temp_alert_px4 {
946 nvidia,pins = 946 nvidia,pins = "temp_alert_px4";
947 nvidia,pull = 947 nvidia,pull = <TEGRA_PIN_PULL_UP>;
948 nvidia,tristat 948 nvidia,tristate = <TEGRA_PIN_DISABLE>;
949 nvidia,enable- 949 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
950 nvidia,open-dr 950 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
951 }; 951 };
952 button_power_on_px5 { 952 button_power_on_px5 {
953 nvidia,pins = 953 nvidia,pins = "button_power_on_px5";
954 nvidia,functio 954 nvidia,function = "rsvd0";
955 nvidia,pull = 955 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
956 nvidia,tristat 956 nvidia,tristate = <TEGRA_PIN_ENABLE>;
957 nvidia,enable- 957 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
958 nvidia,open-dr 958 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
959 }; 959 };
960 button_vol_up_px6 { 960 button_vol_up_px6 {
961 nvidia,pins = 961 nvidia,pins = "button_vol_up_px6";
962 nvidia,pull = 962 nvidia,pull = <TEGRA_PIN_PULL_UP>;
963 nvidia,tristat 963 nvidia,tristate = <TEGRA_PIN_DISABLE>;
964 nvidia,enable- 964 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
965 nvidia,open-dr 965 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
966 }; 966 };
967 button_vol_down_px7 { 967 button_vol_down_px7 {
968 nvidia,pins = 968 nvidia,pins = "button_vol_down_px7";
969 nvidia,pull = 969 nvidia,pull = <TEGRA_PIN_PULL_UP>;
970 nvidia,tristat 970 nvidia,tristate = <TEGRA_PIN_DISABLE>;
971 nvidia,enable- 971 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
972 nvidia,open-dr 972 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
973 }; 973 };
974 button_slide_sw_py0 { 974 button_slide_sw_py0 {
975 nvidia,pins = 975 nvidia,pins = "button_slide_sw_py0";
976 nvidia,functio 976 nvidia,function = "rsvd0";
977 nvidia,pull = 977 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
978 nvidia,tristat 978 nvidia,tristate = <TEGRA_PIN_ENABLE>;
979 nvidia,enable- 979 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
980 nvidia,open-dr 980 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
981 }; 981 };
982 button_home_py1 { 982 button_home_py1 {
983 nvidia,pins = 983 nvidia,pins = "button_home_py1";
984 nvidia,pull = 984 nvidia,pull = <TEGRA_PIN_PULL_UP>;
985 nvidia,tristat 985 nvidia,tristate = <TEGRA_PIN_DISABLE>;
986 nvidia,enable- 986 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
987 nvidia,open-dr 987 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
988 }; 988 };
989 lcd_te_py2 { 989 lcd_te_py2 {
990 nvidia,pins = 990 nvidia,pins = "lcd_te_py2";
991 nvidia,functio 991 nvidia,function = "rsvd1";
992 nvidia,pull = 992 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
993 nvidia,tristat 993 nvidia,tristate = <TEGRA_PIN_ENABLE>;
994 nvidia,enable- 994 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
995 nvidia,open-dr 995 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
996 }; 996 };
997 pwr_i2c_scl_py3 { 997 pwr_i2c_scl_py3 {
998 nvidia,pins = 998 nvidia,pins = "pwr_i2c_scl_py3";
999 nvidia,functio 999 nvidia,function = "i2cpmu";
1000 nvidia,pull = 1000 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1001 nvidia,trista 1001 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1002 nvidia,enable 1002 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1003 nvidia,open-d 1003 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1004 nvidia,io-hv 1004 nvidia,io-hv = <TEGRA_PIN_DISABLE>;
1005 }; 1005 };
1006 pwr_i2c_sda_py4 { 1006 pwr_i2c_sda_py4 {
1007 nvidia,pins = 1007 nvidia,pins = "pwr_i2c_sda_py4";
1008 nvidia,functi 1008 nvidia,function = "i2cpmu";
1009 nvidia,pull = 1009 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1010 nvidia,trista 1010 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1011 nvidia,enable 1011 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1012 nvidia,open-d 1012 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1013 nvidia,io-hv 1013 nvidia,io-hv = <TEGRA_PIN_DISABLE>;
1014 }; 1014 };
1015 clk_32k_out_py5 { 1015 clk_32k_out_py5 {
1016 nvidia,pins = 1016 nvidia,pins = "clk_32k_out_py5";
1017 nvidia,functi 1017 nvidia,function = "rsvd2";
1018 nvidia,pull = 1018 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1019 nvidia,trista 1019 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1020 nvidia,enable 1020 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1021 nvidia,open-d 1021 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1022 }; 1022 };
1023 pz0 { 1023 pz0 {
1024 nvidia,pins = 1024 nvidia,pins = "pz0";
1025 nvidia,pull = 1025 nvidia,pull = <TEGRA_PIN_PULL_UP>;
1026 nvidia,trista 1026 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1027 nvidia,enable 1027 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1028 nvidia,open-d 1028 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1029 }; 1029 };
1030 pz1 { 1030 pz1 {
1031 nvidia,pins = 1031 nvidia,pins = "pz1";
1032 nvidia,functi 1032 nvidia,function = "rsvd2";
1033 nvidia,pull = 1033 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1034 nvidia,trista 1034 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1035 nvidia,enable 1035 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1036 nvidia,open-d 1036 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1037 }; 1037 };
1038 pz2 { 1038 pz2 {
1039 nvidia,pins = 1039 nvidia,pins = "pz2";
1040 nvidia,functi 1040 nvidia,function = "rsvd2";
1041 nvidia,pull = 1041 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1042 nvidia,trista 1042 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1043 nvidia,enable 1043 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1044 nvidia,open-d 1044 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1045 }; 1045 };
1046 pz3 { 1046 pz3 {
1047 nvidia,pins = 1047 nvidia,pins = "pz3";
1048 nvidia,functi 1048 nvidia,function = "rsvd1";
1049 nvidia,pull = 1049 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1050 nvidia,trista 1050 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1051 nvidia,enable 1051 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1052 nvidia,open-d 1052 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1053 }; 1053 };
1054 pz4 { 1054 pz4 {
1055 nvidia,pins = 1055 nvidia,pins = "pz4";
1056 nvidia,functi 1056 nvidia,function = "rsvd1";
1057 nvidia,pull = 1057 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1058 nvidia,trista 1058 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1059 nvidia,enable 1059 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1060 nvidia,open-d 1060 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1061 }; 1061 };
1062 pz5 { 1062 pz5 {
1063 nvidia,pins = 1063 nvidia,pins = "pz5";
1064 nvidia,functi 1064 nvidia,function = "soc";
1065 nvidia,pull = 1065 nvidia,pull = <TEGRA_PIN_PULL_UP>;
1066 nvidia,trista 1066 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1067 nvidia,enable 1067 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1068 nvidia,open-d 1068 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1069 }; 1069 };
1070 dap2_fs_paa0 { 1070 dap2_fs_paa0 {
1071 nvidia,pins = 1071 nvidia,pins = "dap2_fs_paa0";
1072 nvidia,functi 1072 nvidia,function = "i2s2";
1073 nvidia,pull = 1073 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1074 nvidia,trista 1074 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1075 nvidia,enable 1075 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1076 nvidia,open-d 1076 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1077 }; 1077 };
1078 dap2_sclk_paa1 { 1078 dap2_sclk_paa1 {
1079 nvidia,pins = 1079 nvidia,pins = "dap2_sclk_paa1";
1080 nvidia,functi 1080 nvidia,function = "i2s2";
1081 nvidia,pull = 1081 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1082 nvidia,trista 1082 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1083 nvidia,enable 1083 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1084 nvidia,open-d 1084 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1085 }; 1085 };
1086 dap2_din_paa2 { 1086 dap2_din_paa2 {
1087 nvidia,pins = 1087 nvidia,pins = "dap2_din_paa2";
1088 nvidia,functi 1088 nvidia,function = "i2s2";
1089 nvidia,pull = 1089 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1090 nvidia,trista 1090 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1091 nvidia,enable 1091 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1092 nvidia,open-d 1092 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1093 }; 1093 };
1094 dap2_dout_paa3 { 1094 dap2_dout_paa3 {
1095 nvidia,pins = 1095 nvidia,pins = "dap2_dout_paa3";
1096 nvidia,functi 1096 nvidia,function = "i2s2";
1097 nvidia,pull = 1097 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1098 nvidia,trista 1098 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1099 nvidia,enable 1099 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1100 nvidia,open-d 1100 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1101 }; 1101 };
1102 aud_mclk_pbb0 { 1102 aud_mclk_pbb0 {
1103 nvidia,pins = 1103 nvidia,pins = "aud_mclk_pbb0";
1104 nvidia,functi 1104 nvidia,function = "rsvd1";
1105 nvidia,pull = 1105 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1106 nvidia,trista 1106 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1107 nvidia,enable 1107 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1108 nvidia,open-d 1108 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1109 }; 1109 };
1110 dvfs_pwm_pbb1 { 1110 dvfs_pwm_pbb1 {
1111 nvidia,pins = 1111 nvidia,pins = "dvfs_pwm_pbb1";
1112 nvidia,functi 1112 nvidia,function = "cldvfs";
1113 nvidia,pull = 1113 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1114 nvidia,trista 1114 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1115 nvidia,enable 1115 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1116 nvidia,open-d 1116 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1117 }; 1117 };
1118 dvfs_clk_pbb2 { 1118 dvfs_clk_pbb2 {
1119 nvidia,pins = 1119 nvidia,pins = "dvfs_clk_pbb2";
1120 nvidia,pull = 1120 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1121 nvidia,trista 1121 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1122 nvidia,enable 1122 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1123 nvidia,open-d 1123 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1124 }; 1124 };
1125 gpio_x1_aud_pbb3 { 1125 gpio_x1_aud_pbb3 {
1126 nvidia,pins = 1126 nvidia,pins = "gpio_x1_aud_pbb3";
1127 nvidia,functi 1127 nvidia,function = "rsvd0";
1128 nvidia,pull = 1128 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1129 nvidia,trista 1129 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1130 nvidia,enable 1130 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1131 nvidia,open-d 1131 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1132 }; 1132 };
1133 gpio_x3_aud_pbb4 { 1133 gpio_x3_aud_pbb4 {
1134 nvidia,pins = 1134 nvidia,pins = "gpio_x3_aud_pbb4";
1135 nvidia,functi 1135 nvidia,function = "rsvd0";
1136 nvidia,pull = 1136 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1137 nvidia,trista 1137 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1138 nvidia,enable 1138 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1139 nvidia,open-d 1139 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1140 }; 1140 };
1141 hdmi_cec_pcc0 { 1141 hdmi_cec_pcc0 {
1142 nvidia,pins = 1142 nvidia,pins = "hdmi_cec_pcc0";
1143 nvidia,functi 1143 nvidia,function = "cec";
1144 nvidia,pull = 1144 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1145 nvidia,trista 1145 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1146 nvidia,enable 1146 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1147 nvidia,open-d 1147 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1148 nvidia,io-hv 1148 nvidia,io-hv = <TEGRA_PIN_ENABLE>;
1149 }; 1149 };
1150 hdmi_int_dp_hpd_pcc1 1150 hdmi_int_dp_hpd_pcc1 {
1151 nvidia,pins = 1151 nvidia,pins = "hdmi_int_dp_hpd_pcc1";
1152 nvidia,pull = 1152 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1153 nvidia,trista 1153 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1154 nvidia,enable 1154 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1155 nvidia,open-d 1155 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1156 nvidia,io-hv 1156 nvidia,io-hv = <TEGRA_PIN_DISABLE>;
1157 }; 1157 };
1158 spdif_out_pcc2 { 1158 spdif_out_pcc2 {
1159 nvidia,pins = 1159 nvidia,pins = "spdif_out_pcc2";
1160 nvidia,functi 1160 nvidia,function = "rsvd1";
1161 nvidia,pull = 1161 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1162 nvidia,trista 1162 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1163 nvidia,enable 1163 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1164 nvidia,open-d 1164 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1165 }; 1165 };
1166 spdif_in_pcc3 { 1166 spdif_in_pcc3 {
1167 nvidia,pins = 1167 nvidia,pins = "spdif_in_pcc3";
1168 nvidia,functi 1168 nvidia,function = "rsvd1";
1169 nvidia,pull = 1169 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1170 nvidia,trista 1170 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1171 nvidia,enable 1171 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1172 nvidia,open-d 1172 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1173 }; 1173 };
1174 usb_vbus_en0_pcc4 { 1174 usb_vbus_en0_pcc4 {
1175 nvidia,pins = 1175 nvidia,pins = "usb_vbus_en0_pcc4";
1176 nvidia,functi 1176 nvidia,function = "usb";
1177 nvidia,pull = 1177 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1178 nvidia,trista 1178 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1179 nvidia,enable 1179 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1180 nvidia,open-d 1180 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1181 nvidia,io-hv 1181 nvidia,io-hv = <TEGRA_PIN_ENABLE>;
1182 }; 1182 };
1183 usb_vbus_en1_pcc5 { 1183 usb_vbus_en1_pcc5 {
1184 nvidia,pins = 1184 nvidia,pins = "usb_vbus_en1_pcc5";
1185 nvidia,functi 1185 nvidia,function = "usb";
1186 nvidia,pull = 1186 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1187 nvidia,trista 1187 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1188 nvidia,enable 1188 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1189 nvidia,open-d 1189 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1190 nvidia,io-hv 1190 nvidia,io-hv = <TEGRA_PIN_ENABLE>;
1191 }; 1191 };
1192 dp_hpd0_pcc6 { 1192 dp_hpd0_pcc6 {
1193 nvidia,pins = 1193 nvidia,pins = "dp_hpd0_pcc6";
1194 nvidia,functi 1194 nvidia,function = "rsvd1";
1195 nvidia,pull = 1195 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1196 nvidia,trista 1196 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1197 nvidia,enable 1197 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1198 nvidia,open-d 1198 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1199 }; 1199 };
1200 pcc7 { 1200 pcc7 {
1201 nvidia,pins = 1201 nvidia,pins = "pcc7";
1202 nvidia,pull = 1202 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1203 nvidia,trista 1203 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1204 nvidia,enable 1204 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1205 nvidia,open-d 1205 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1206 nvidia,io-hv 1206 nvidia,io-hv = <TEGRA_PIN_DISABLE>;
1207 }; 1207 };
1208 spi2_cs1_pdd0 { 1208 spi2_cs1_pdd0 {
1209 nvidia,pins = 1209 nvidia,pins = "spi2_cs1_pdd0";
1210 nvidia,functi 1210 nvidia,function = "rsvd1";
1211 nvidia,pull = 1211 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1212 nvidia,trista 1212 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1213 nvidia,enable 1213 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1214 nvidia,open-d 1214 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1215 }; 1215 };
1216 qspi_sck_pee0 { 1216 qspi_sck_pee0 {
1217 nvidia,pins = 1217 nvidia,pins = "qspi_sck_pee0";
1218 nvidia,functi 1218 nvidia,function = "rsvd1";
1219 nvidia,pull = 1219 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1220 nvidia,trista 1220 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1221 nvidia,enable 1221 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1222 nvidia,open-d 1222 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1223 }; 1223 };
1224 qspi_cs_n_pee1 { 1224 qspi_cs_n_pee1 {
1225 nvidia,pins = 1225 nvidia,pins = "qspi_cs_n_pee1";
1226 nvidia,functi 1226 nvidia,function = "rsvd1";
1227 nvidia,pull = 1227 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1228 nvidia,trista 1228 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1229 nvidia,enable 1229 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1230 nvidia,open-d 1230 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1231 }; 1231 };
1232 qspi_io0_pee2 { 1232 qspi_io0_pee2 {
1233 nvidia,pins = 1233 nvidia,pins = "qspi_io0_pee2";
1234 nvidia,functi 1234 nvidia,function = "rsvd1";
1235 nvidia,pull = 1235 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1236 nvidia,trista 1236 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1237 nvidia,enable 1237 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1238 nvidia,open-d 1238 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1239 }; 1239 };
1240 qspi_io1_pee3 { 1240 qspi_io1_pee3 {
1241 nvidia,pins = 1241 nvidia,pins = "qspi_io1_pee3";
1242 nvidia,functi 1242 nvidia,function = "rsvd1";
1243 nvidia,pull = 1243 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1244 nvidia,trista 1244 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1245 nvidia,enable 1245 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1246 nvidia,open-d 1246 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1247 }; 1247 };
1248 qspi_io2_pee4 { 1248 qspi_io2_pee4 {
1249 nvidia,pins = 1249 nvidia,pins = "qspi_io2_pee4";
1250 nvidia,functi 1250 nvidia,function = "rsvd1";
1251 nvidia,pull = 1251 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1252 nvidia,trista 1252 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1253 nvidia,enable 1253 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1254 nvidia,open-d 1254 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1255 }; 1255 };
1256 qspi_io3_pee5 { 1256 qspi_io3_pee5 {
1257 nvidia,pins = 1257 nvidia,pins = "qspi_io3_pee5";
1258 nvidia,functi 1258 nvidia,function = "rsvd1";
1259 nvidia,pull = 1259 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1260 nvidia,trista 1260 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1261 nvidia,enable 1261 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1262 nvidia,open-d 1262 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1263 }; 1263 };
1264 core_pwr_req { 1264 core_pwr_req {
1265 nvidia,pins = 1265 nvidia,pins = "core_pwr_req";
1266 nvidia,functi 1266 nvidia,function = "core";
1267 nvidia,pull = 1267 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1268 nvidia,trista 1268 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1269 nvidia,enable 1269 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1270 nvidia,open-d 1270 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1271 }; 1271 };
1272 cpu_pwr_req { 1272 cpu_pwr_req {
1273 nvidia,pins = 1273 nvidia,pins = "cpu_pwr_req";
1274 nvidia,functi 1274 nvidia,function = "rsvd1";
1275 nvidia,pull = 1275 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1276 nvidia,trista 1276 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1277 nvidia,enable 1277 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1278 nvidia,open-d 1278 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1279 }; 1279 };
1280 pwr_int_n { 1280 pwr_int_n {
1281 nvidia,pins = 1281 nvidia,pins = "pwr_int_n";
1282 nvidia,functi 1282 nvidia,function = "pmi";
1283 nvidia,pull = 1283 nvidia,pull = <TEGRA_PIN_PULL_UP>;
1284 nvidia,trista 1284 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1285 nvidia,enable 1285 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1286 nvidia,open-d 1286 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1287 }; 1287 };
1288 clk_32k_in { 1288 clk_32k_in {
1289 nvidia,pins = 1289 nvidia,pins = "clk_32k_in";
1290 nvidia,functi 1290 nvidia,function = "clk";
1291 nvidia,pull = 1291 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1292 nvidia,trista 1292 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1293 nvidia,enable 1293 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1294 nvidia,open-d 1294 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1295 }; 1295 };
1296 jtag_rtck { 1296 jtag_rtck {
1297 nvidia,pins = 1297 nvidia,pins = "jtag_rtck";
1298 nvidia,functi 1298 nvidia,function = "jtag";
1299 nvidia,pull = 1299 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1300 nvidia,trista 1300 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1301 nvidia,enable 1301 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1302 nvidia,open-d 1302 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1303 }; 1303 };
1304 clk_req { 1304 clk_req {
1305 nvidia,pins = 1305 nvidia,pins = "clk_req";
1306 nvidia,functi 1306 nvidia,function = "rsvd1";
1307 nvidia,pull = 1307 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1308 nvidia,trista 1308 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1309 nvidia,enable 1309 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1310 nvidia,open-d 1310 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1311 }; 1311 };
1312 shutdown { 1312 shutdown {
1313 nvidia,pins = 1313 nvidia,pins = "shutdown";
1314 nvidia,functi 1314 nvidia,function = "shutdown";
1315 nvidia,pull = 1315 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1316 nvidia,trista 1316 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1317 nvidia,enable 1317 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1318 nvidia,open-d 1318 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
1319 }; 1319 };
1320 }; 1320 };
1321 }; 1321 };
1322 1322
1323 serial@70006000 { 1323 serial@70006000 {
1324 /delete-property/ dmas; <<
1325 /delete-property/ dma-names; <<
1326 status = "okay"; 1324 status = "okay";
1327 }; 1325 };
1328 1326
1329 i2c@7000d000 { 1327 i2c@7000d000 {
1330 status = "okay"; 1328 status = "okay";
1331 clock-frequency = <400000>; 1329 clock-frequency = <400000>;
1332 1330
1333 pmic: pmic@3c { !! 1331 max77620: max77620@3c {
1334 compatible = "maxim,m 1332 compatible = "maxim,max77620";
1335 reg = <0x3c>; 1333 reg = <0x3c>;
1336 interrupts = <GIC_SPI 1334 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1337 1335
1338 #interrupt-cells = <2 1336 #interrupt-cells = <2>;
1339 interrupt-controller; 1337 interrupt-controller;
1340 1338
1341 gpio-controller; 1339 gpio-controller;
1342 #gpio-cells = <2>; 1340 #gpio-cells = <2>;
1343 1341
1344 pinctrl-names = "defa 1342 pinctrl-names = "default";
1345 pinctrl-0 = <&max7762 1343 pinctrl-0 = <&max77620_default>;
1346 1344
1347 fps { !! 1345 max77620_default: pinmux@0 {
1348 #address-cell !! 1346 pin_gpio0 {
1349 #size-cells = <<
1350 <<
1351 fps0 { <<
1352 reg = <<
1353 maxim <<
1354 }; <<
1355 <<
1356 fps1 { <<
1357 reg = <<
1358 maxim <<
1359 maxim <<
1360 }; <<
1361 <<
1362 fps2 { <<
1363 reg = <<
1364 maxim <<
1365 }; <<
1366 }; <<
1367 <<
1368 hog-0 { <<
1369 gpio-hog; <<
1370 output-high; <<
1371 gpios = <2 GP <<
1372 <7 GP <<
1373 }; <<
1374 <<
1375 max77620_default: pin <<
1376 gpio0 { <<
1377 pins 1347 pins = "gpio0";
1378 funct 1348 function = "gpio";
1379 }; 1349 };
1380 1350
1381 gpio1 { !! 1351 pin_gpio1 {
1382 pins 1352 pins = "gpio1";
1383 funct 1353 function = "fps-out";
1384 drive 1354 drive-push-pull = <1>;
1385 maxim 1355 maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
1386 maxim 1356 maxim,active-fps-power-up-slot = <7>;
1387 maxim 1357 maxim,active-fps-power-down-slot = <0>;
1388 }; 1358 };
1389 1359
1390 gpio2 { !! 1360 pin_gpio2_3 {
1391 pins !! 1361 pins = "gpio2", "gpio3";
1392 funct <<
1393 drive <<
1394 maxim <<
1395 }; <<
1396 <<
1397 gpio3 { <<
1398 pins <<
1399 funct 1362 function = "fps-out";
1400 drive 1363 drive-open-drain = <1>;
1401 maxim 1364 maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
1402 }; 1365 };
1403 1366
1404 gpio4 { !! 1367 pin_gpio4 {
1405 pins 1368 pins = "gpio4";
1406 funct 1369 function = "32k-out1";
1407 }; 1370 };
1408 1371
1409 gpio5_6_7 { !! 1372 pin_gpio5_6_7 {
1410 pins 1373 pins = "gpio5", "gpio6", "gpio7";
1411 funct 1374 function = "gpio";
1412 drive 1375 drive-push-pull = <1>;
1413 }; 1376 };
>> 1377
>> 1378 pin_gpio2 {
>> 1379 maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
>> 1380 };
>> 1381
>> 1382 pin_gpio3 {
>> 1383 maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
>> 1384 };
>> 1385 };
>> 1386
>> 1387 spmic-default-output-high {
>> 1388 gpio-hog;
>> 1389 output-high;
>> 1390 gpios = <2 GPIO_ACTIVE_HIGH 7 GPIO_ACTIVE_HIGH>;
>> 1391 };
>> 1392
>> 1393 fps {
>> 1394 #address-cells = <1>;
>> 1395 #size-cells = <0>;
>> 1396
>> 1397 fps0 {
>> 1398 reg = <0>;
>> 1399 maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>;
>> 1400 };
>> 1401
>> 1402 fps1 {
>> 1403 reg = <1>;
>> 1404 maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>;
>> 1405 maxim,device-state-on-disabled-event = <MAX77620_FPS_INACTIVE_STATE_SLEEP>;
>> 1406 };
>> 1407
>> 1408 fps2 {
>> 1409 reg = <2>;
>> 1410 maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>;
>> 1411 };
1414 }; 1412 };
1415 1413
1416 regulators { 1414 regulators {
1417 in-ldo0-1-sup 1415 in-ldo0-1-supply = <&max77620_sd2>;
1418 in-ldo7-8-sup 1416 in-ldo7-8-supply = <&max77620_sd2>;
1419 1417
1420 max77620_sd0: 1418 max77620_sd0: sd0 {
1421 regul 1419 regulator-name = "vdd-core";
1422 regul 1420 regulator-enable-ramp-delay = <146>;
1423 regul 1421 regulator-min-microvolt = <600000>;
1424 regul 1422 regulator-max-microvolt = <1400000>;
1425 regul 1423 regulator-ramp-delay = <27500>;
1426 regul 1424 regulator-always-on;
1427 regul 1425 regulator-boot-on;
1428 1426
1429 maxim 1427 maxim,active-fps-power-up-slot = <0>;
1430 maxim 1428 maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
1431 }; 1429 };
1432 1430
1433 max77620_sd1: 1431 max77620_sd1: sd1 {
1434 regul 1432 regulator-name = "vddio-ddr";
1435 regul 1433 regulator-enable-ramp-delay = <130>;
1436 regul 1434 regulator-ramp-delay = <27500>;
1437 regul 1435 regulator-always-on;
1438 regul 1436 regulator-boot-on;
1439 1437
1440 maxim 1438 maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
1441 }; 1439 };
1442 1440
1443 max77620_sd2: 1441 max77620_sd2: sd2 {
1444 regul 1442 regulator-name = "vdd-pre-reg";
1445 regul 1443 regulator-enable-ramp-delay = <176>;
1446 regul 1444 regulator-min-microvolt = <3000000>;
1447 regul 1445 regulator-max-microvolt = <3000000>;
1448 regul 1446 regulator-ramp-delay = <27500>;
1449 regul 1447 regulator-always-on;
1450 regul 1448 regulator-boot-on;
1451 1449
1452 maxim 1450 maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
1453 maxim 1451 maxim,suspend-fps-source = <MAX77620_FPS_SRC_NONE>;
1454 }; 1452 };
1455 1453
1456 max77620_sd3: 1454 max77620_sd3: sd3 {
1457 regul 1455 regulator-name = "vdd-1v8";
1458 regul 1456 regulator-enable-ramp-delay = <242>;
1459 regul 1457 regulator-min-microvolt = <1800000>;
1460 regul 1458 regulator-max-microvolt = <1800000>;
1461 regul 1459 regulator-ramp-delay = <27500>;
1462 regul 1460 regulator-always-on;
1463 regul 1461 regulator-boot-on;
1464 1462
1465 maxim 1463 maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
1466 }; 1464 };
1467 1465
1468 max77620_ldo0 1466 max77620_ldo0: ldo0 {
1469 regul 1467 regulator-name = "avdd-sys";
1470 regul 1468 regulator-enable-ramp-delay = <26>;
1471 regul 1469 regulator-min-microvolt = <1200000>;
1472 regul 1470 regulator-max-microvolt = <1200000>;
1473 regul 1471 regulator-ramp-delay = <100000>;
1474 regul 1472 regulator-boot-on;
1475 1473
1476 maxim 1474 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
1477 }; 1475 };
1478 1476
1479 max77620_ldo1 1477 max77620_ldo1: ldo1 {
1480 regul 1478 regulator-name = "vdd-pex";
1481 regul 1479 regulator-enable-ramp-delay = <22>;
1482 regul 1480 regulator-min-microvolt = <1075000>;
1483 regul 1481 regulator-max-microvolt = <1075000>;
1484 regul 1482 regulator-ramp-delay = <100000>;
1485 regul 1483 regulator-always-on;
1486 1484
1487 maxim 1485 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
1488 }; 1486 };
1489 1487
1490 max77620_ldo2 1488 max77620_ldo2: ldo2 {
1491 regul 1489 regulator-name = "vddio-sdmmc3";
1492 regul 1490 regulator-enable-ramp-delay = <62>;
1493 regul 1491 regulator-min-microvolt = <1800000>;
1494 regul 1492 regulator-max-microvolt = <3300000>;
1495 regul 1493 regulator-ramp-delay = <100000>;
1496 1494
1497 maxim 1495 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
1498 }; 1496 };
1499 1497
1500 max77620_ldo3 1498 max77620_ldo3: ldo3 {
1501 regul 1499 regulator-name = "vdd-3v3-eth";
1502 regul 1500 regulator-enable-ramp-delay = <50>;
1503 regul 1501 regulator-min-microvolt = <3300000>;
1504 regul 1502 regulator-max-microvolt = <3300000>;
1505 regul 1503 regulator-ramp-delay = <100000>;
1506 regul 1504 regulator-always-on;
1507 regul 1505 regulator-boot-on;
1508 1506
1509 maxim 1507 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
1510 }; 1508 };
1511 1509
1512 max77620_ldo4 1510 max77620_ldo4: ldo4 {
1513 regul 1511 regulator-name = "vdd-rtc";
1514 regul 1512 regulator-enable-ramp-delay = <22>;
1515 regul 1513 regulator-min-microvolt = <850000>;
1516 regul 1514 regulator-max-microvolt = <850000>;
1517 regul 1515 regulator-ramp-delay = <100000>;
1518 regul 1516 regulator-always-on;
1519 regul 1517 regulator-boot-on;
1520 1518
1521 maxim 1519 maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
1522 }; 1520 };
1523 1521
1524 max77620_ldo5 1522 max77620_ldo5: ldo5 {
1525 regul 1523 regulator-name = "avdd-ts-hv";
1526 regul 1524 regulator-enable-ramp-delay = <62>;
1527 regul 1525 regulator-min-microvolt = <3300000>;
1528 regul 1526 regulator-max-microvolt = <3300000>;
1529 regul 1527 regulator-ramp-delay = <100000>;
1530 1528
1531 maxim 1529 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
1532 }; 1530 };
1533 1531
1534 max77620_ldo6 1532 max77620_ldo6: ldo6 {
1535 regul 1533 regulator-name = "vdd-ts";
1536 regul 1534 regulator-enable-ramp-delay = <36>;
1537 regul 1535 regulator-min-microvolt = <1800000>;
1538 regul 1536 regulator-max-microvolt = <1800000>;
1539 regul 1537 regulator-ramp-delay = <100000>;
1540 regul 1538 regulator-boot-on;
1541 1539
1542 maxim 1540 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
1543 }; 1541 };
1544 1542
1545 max77620_ldo7 1543 max77620_ldo7: ldo7 {
1546 regul 1544 regulator-name = "vdd-gen-pll-edp";
1547 regul 1545 regulator-enable-ramp-delay = <24>;
1548 regul 1546 regulator-min-microvolt = <1050000>;
1549 regul 1547 regulator-max-microvolt = <1050000>;
1550 regul 1548 regulator-ramp-delay = <100000>;
1551 regul 1549 regulator-always-on;
1552 regul 1550 regulator-boot-on;
1553 1551
1554 maxim 1552 maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
1555 maxim 1553 maxim,suspend-fps-source = <MAX77620_FPS_SRC_NONE>;
1556 }; 1554 };
1557 1555
1558 max77620_ldo8 1556 max77620_ldo8: ldo8 {
1559 regul 1557 regulator-name = "vdd-hdmi-dp";
1560 regul 1558 regulator-enable-ramp-delay = <22>;
1561 regul 1559 regulator-min-microvolt = <1050000>;
1562 regul 1560 regulator-max-microvolt = <1050000>;
1563 regul 1561 regulator-ramp-delay = <100000>;
1564 regul 1562 regulator-always-on;
1565 regul 1563 regulator-boot-on;
1566 1564
1567 maxim 1565 maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
1568 }; 1566 };
1569 }; 1567 };
1570 }; 1568 };
1571 }; 1569 };
1572 1570
1573 pmc@7000e400 { 1571 pmc@7000e400 {
1574 nvidia,invert-interrupt; 1572 nvidia,invert-interrupt;
1575 nvidia,suspend-mode = <0>; 1573 nvidia,suspend-mode = <0>;
1576 nvidia,cpu-pwr-good-time = <0 1574 nvidia,cpu-pwr-good-time = <0>;
1577 nvidia,cpu-pwr-off-time = <0> 1575 nvidia,cpu-pwr-off-time = <0>;
1578 nvidia,core-pwr-good-time = < 1576 nvidia,core-pwr-good-time = <4587 3876>;
1579 nvidia,core-pwr-off-time = <3 1577 nvidia,core-pwr-off-time = <39065>;
1580 nvidia,core-power-req-active- 1578 nvidia,core-power-req-active-high;
1581 nvidia,sys-clock-req-active-h 1579 nvidia,sys-clock-req-active-high;
1582 status = "okay"; 1580 status = "okay";
1583 }; 1581 };
1584 1582
1585 mmc@700b0600 { !! 1583 sdhci@700b0600 {
1586 bus-width = <8>; 1584 bus-width = <8>;
1587 non-removable; 1585 non-removable;
1588 status = "okay"; 1586 status = "okay";
1589 }; 1587 };
1590 1588
1591 clk32k_in: clock-32k { !! 1589 clocks {
1592 compatible = "fixed-clock"; !! 1590 compatible = "simple-bus";
1593 clock-frequency = <32768>; !! 1591 #address-cells = <1>;
1594 #clock-cells = <0>; !! 1592 #size-cells = <0>;
>> 1593
>> 1594 clk32k_in: clock@0 {
>> 1595 compatible = "fixed-clock";
>> 1596 reg = <0>;
>> 1597 #clock-cells = <0>;
>> 1598 clock-frequency = <32768>;
>> 1599 };
>> 1600 };
>> 1601
>> 1602 gpio-keys {
>> 1603 compatible = "gpio-keys";
>> 1604 status = "okay";
>> 1605
>> 1606 power {
>> 1607 debounce-interval = <30>;
>> 1608 gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW>;
>> 1609 label = "Power";
>> 1610 linux,code = <KEY_POWER>;
>> 1611 wakeup-event-action = <EV_ACT_ASSERTED>;
>> 1612 wakeup-source;
>> 1613 };
1595 }; 1614 };
1596 1615
1597 cpus { 1616 cpus {
1598 cpu@0 { 1617 cpu@0 {
1599 enable-method = "psci 1618 enable-method = "psci";
1600 }; 1619 };
1601 1620
1602 cpu@1 { 1621 cpu@1 {
1603 enable-method = "psci 1622 enable-method = "psci";
1604 }; 1623 };
1605 1624
1606 cpu@2 { 1625 cpu@2 {
1607 enable-method = "psci 1626 enable-method = "psci";
1608 }; 1627 };
1609 1628
1610 cpu@3 { 1629 cpu@3 {
1611 enable-method = "psci 1630 enable-method = "psci";
1612 }; 1631 };
1613 <<
1614 idle-states { <<
1615 cpu-sleep { <<
1616 status = "oka <<
1617 }; <<
1618 }; <<
1619 }; <<
1620 <<
1621 gpio-keys { <<
1622 compatible = "gpio-keys"; <<
1623 status = "okay"; <<
1624 <<
1625 key-power { <<
1626 debounce-interval = < <<
1627 gpios = <&gpio TEGRA_ <<
1628 label = "Power"; <<
1629 linux,code = <KEY_POW <<
1630 wakeup-event-action = <<
1631 wakeup-source; <<
1632 }; <<
1633 }; 1632 };
1634 1633
1635 psci { 1634 psci {
1636 compatible = "arm,psci-1.0"; 1635 compatible = "arm,psci-1.0";
1637 method = "smc"; 1636 method = "smc";
1638 }; 1637 };
1639 1638
1640 battery_reg: regulator-vdd-ac-bat { !! 1639 regulators {
1641 compatible = "regulator-fixed !! 1640 compatible = "simple-bus";
1642 regulator-name = "vdd-ac-bat" !! 1641 device_type = "fixed-regulators";
1643 regulator-min-microvolt = <50 !! 1642 #address-cells = <1>;
1644 regulator-max-microvolt = <50 !! 1643 #size-cells = <0>;
1645 regulator-always-on; !! 1644
1646 }; !! 1645 battery_reg: regulator@0 {
>> 1646 compatible = "regulator-fixed";
>> 1647 reg = <0>;
>> 1648 regulator-name = "vdd-ac-bat";
>> 1649 regulator-min-microvolt = <5000000>;
>> 1650 regulator-max-microvolt = <5000000>;
>> 1651 regulator-always-on;
>> 1652 };
1647 1653
1648 vdd_3v3: regulator-vdd-3v3 { !! 1654 vdd_3v3: regulator@1 {
1649 compatible = "regulator-fixed !! 1655 compatible = "regulator-fixed";
1650 regulator-name = "vdd-3v3"; !! 1656 reg = <1>;
1651 regulator-enable-ramp-delay = !! 1657 regulator-name = "vdd-3v3";
1652 regulator-min-microvolt = <33 !! 1658 regulator-enable-ramp-delay = <160>;
1653 regulator-max-microvolt = <33 !! 1659 regulator-min-microvolt = <3300000>;
1654 regulator-always-on; !! 1660 regulator-max-microvolt = <3300000>;
>> 1661 regulator-always-on;
1655 1662
1656 gpio = <&pmic 3 GPIO_ACTIVE_H !! 1663 gpio = <&max77620 3 GPIO_ACTIVE_HIGH>;
1657 enable-active-high; !! 1664 enable-active-high;
1658 }; !! 1665 };
1659 1666
1660 max77620_gpio7: regulator-max77620-gp !! 1667 max77620_gpio7: regulator@2 {
1661 compatible = "regulator-fixed !! 1668 compatible = "regulator-fixed";
1662 regulator-name = "max77620-gp !! 1669 reg = <2>;
1663 regulator-enable-ramp-delay = !! 1670 regulator-name = "max77620-gpio7";
1664 regulator-min-microvolt = <12 !! 1671 regulator-enable-ramp-delay = <240>;
1665 regulator-max-microvolt = <12 !! 1672 regulator-min-microvolt = <1200000>;
1666 vin-supply = <&max77620_ldo0> !! 1673 regulator-max-microvolt = <1200000>;
1667 regulator-always-on; !! 1674 vin-supply = <&max77620_ldo0>;
1668 regulator-boot-on; !! 1675 regulator-always-on;
>> 1676 regulator-boot-on;
1669 1677
1670 gpio = <&pmic 7 GPIO_ACTIVE_H !! 1678 gpio = <&max77620 7 GPIO_ACTIVE_HIGH>;
1671 enable-active-high; !! 1679 enable-active-high;
1672 }; !! 1680 };
1673 1681
1674 lcd_bl_en: regulator-lcd-bl-en { !! 1682 lcd_bl_en: regulator@3 {
1675 compatible = "regulator-fixed !! 1683 compatible = "regulator-fixed";
1676 regulator-name = "lcd-bl-en"; !! 1684 reg = <3>;
1677 regulator-min-microvolt = <18 !! 1685 regulator-name = "lcd-bl-en";
1678 regulator-max-microvolt = <18 !! 1686 regulator-min-microvolt = <1800000>;
1679 regulator-boot-on; !! 1687 regulator-max-microvolt = <1800000>;
>> 1688 regulator-boot-on;
1680 1689
1681 gpio = <&gpio TEGRA_GPIO(V, 1 !! 1690 gpio = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>;
1682 enable-active-high; !! 1691 enable-active-high;
1683 }; !! 1692 };
1684 1693
1685 en_vdd_sd: regulator-vdd-sd { !! 1694 en_vdd_sd: regulator@4 {
1686 compatible = "regulator-fixed !! 1695 compatible = "regulator-fixed";
1687 regulator-name = "en-vdd-sd"; !! 1696 reg = <4>;
1688 regulator-enable-ramp-delay = !! 1697 regulator-name = "en-vdd-sd";
1689 regulator-min-microvolt = <33 !! 1698 regulator-enable-ramp-delay = <472>;
1690 regulator-max-microvolt = <33 !! 1699 regulator-min-microvolt = <3300000>;
1691 vin-supply = <&vdd_3v3>; !! 1700 regulator-max-microvolt = <3300000>;
>> 1701 vin-supply = <&vdd_3v3>;
1692 1702
1693 gpio = <&gpio TEGRA_GPIO(Z, 4 !! 1703 gpio = <&gpio TEGRA_GPIO(Z, 4) GPIO_ACTIVE_HIGH>;
1694 enable-active-high; !! 1704 enable-active-high;
1695 }; !! 1705 };
1696 1706
1697 en_vdd_cam: regulator-vdd-cam { !! 1707 en_vdd_cam: regulator@5 {
1698 compatible = "regulator-fixed !! 1708 compatible = "regulator-fixed";
1699 regulator-name = "en-vdd-cam" !! 1709 reg = <5>;
1700 regulator-min-microvolt = <18 !! 1710 regulator-name = "en-vdd-cam";
1701 regulator-max-microvolt = <18 !! 1711 regulator-min-microvolt = <1800000>;
>> 1712 regulator-max-microvolt = <1800000>;
1702 1713
1703 gpio = <&gpio TEGRA_GPIO(S, 4 !! 1714 gpio = <&gpio TEGRA_GPIO(S, 4) GPIO_ACTIVE_HIGH>;
1704 enable-active-high; !! 1715 enable-active-high;
1705 }; !! 1716 };
1706 1717
1707 vdd_sys_boost: regulator-vdd-sys-boos !! 1718 vdd_sys_boost: regulator@6 {
1708 compatible = "regulator-fixed !! 1719 compatible = "regulator-fixed";
1709 regulator-name = "vdd-sys-boo !! 1720 reg = <6>;
1710 regulator-enable-ramp-delay = !! 1721 regulator-name = "vdd-sys-boost";
1711 regulator-min-microvolt = <50 !! 1722 regulator-enable-ramp-delay = <3090>;
1712 regulator-max-microvolt = <50 !! 1723 regulator-min-microvolt = <5000000>;
1713 regulator-always-on; !! 1724 regulator-max-microvolt = <5000000>;
>> 1725 regulator-always-on;
1714 1726
1715 gpio = <&pmic 1 GPIO_ACTIVE_H !! 1727 gpio = <&max77620 1 GPIO_ACTIVE_HIGH>;
1716 enable-active-high; !! 1728 enable-active-high;
1717 }; !! 1729 };
1718 1730
1719 vdd_hdmi: regulator-vdd-hdmi { !! 1731 vdd_hdmi: regulator@7 {
1720 compatible = "regulator-fixed !! 1732 compatible = "regulator-fixed";
1721 regulator-name = "vdd-hdmi"; !! 1733 reg = <7>;
1722 regulator-enable-ramp-delay = !! 1734 regulator-name = "vdd-hdmi";
1723 regulator-min-microvolt = <50 !! 1735 regulator-enable-ramp-delay = <468>;
1724 regulator-max-microvolt = <50 !! 1736 regulator-min-microvolt = <5000000>;
1725 vin-supply = <&vdd_sys_boost> !! 1737 regulator-max-microvolt = <5000000>;
1726 regulator-boot-on; !! 1738 vin-supply = <&vdd_sys_boost>;
>> 1739 regulator-boot-on;
1727 1740
1728 gpio = <&gpio TEGRA_GPIO(CC, !! 1741 gpio = <&gpio TEGRA_GPIO(CC, 7) GPIO_ACTIVE_HIGH>;
1729 enable-active-high; !! 1742 enable-active-high;
1730 }; !! 1743 };
1731 1744
1732 en_vdd_cpu_fixed: regulator-vdd-cpu-f !! 1745 en_vdd_cpu_fixed: regulator@8 {
1733 compatible = "regulator-fixed !! 1746 compatible = "regulator-fixed";
1734 regulator-name = "vdd-cpu-fix !! 1747 reg = <8>;
1735 regulator-min-microvolt = <10 !! 1748 regulator-name = "vdd-cpu-fixed";
1736 regulator-max-microvolt = <10 !! 1749 regulator-min-microvolt = <1000000>;
1737 }; !! 1750 regulator-max-microvolt = <1000000>;
>> 1751 };
1738 1752
1739 vdd_aux_3v3: regulator-vdd-aux-3v3 { !! 1753 vdd_aux_3v3: regulator@9 {
1740 compatible = "regulator-fixed !! 1754 compatible = "regulator-fixed";
1741 regulator-name = "aux-3v3"; !! 1755 reg = <9>;
1742 regulator-min-microvolt = <33 !! 1756 regulator-name = "aux-3v3";
1743 regulator-max-microvolt = <33 !! 1757 regulator-min-microvolt = <3300000>;
1744 }; !! 1758 regulator-max-microvolt = <3300000>;
>> 1759 };
1745 1760
1746 vdd_snsr_pm: regulator-vdd-snsr-pm { !! 1761 vdd_snsr_pm: regulator@10 {
1747 compatible = "regulator-fixed !! 1762 compatible = "regulator-fixed";
1748 regulator-name = "snsr_pm"; !! 1763 reg = <10>;
1749 regulator-min-microvolt = <33 !! 1764 regulator-name = "snsr_pm";
1750 regulator-max-microvolt = <33 !! 1765 regulator-min-microvolt = <3300000>;
>> 1766 regulator-max-microvolt = <3300000>;
1751 1767
1752 enable-active-high; !! 1768 enable-active-high;
1753 }; !! 1769 };
1754 1770
1755 vdd_usb_5v0: regulator-vdd-usb-5v0 { !! 1771 vdd_usb_5v0: regulator@11 {
1756 compatible = "regulator-fixed !! 1772 compatible = "regulator-fixed";
1757 status = "disabled"; !! 1773 reg = <11>;
1758 regulator-name = "vdd-usb-5v0 !! 1774 status = "disabled";
1759 regulator-min-microvolt = <50 !! 1775 regulator-name = "vdd-usb-5v0";
1760 regulator-max-microvolt = <50 !! 1776 regulator-min-microvolt = <5000000>;
1761 vin-supply = <&vdd_3v3>; !! 1777 regulator-max-microvolt = <5000000>;
>> 1778 vin-supply = <&vdd_3v3>;
1762 1779
1763 enable-active-high; !! 1780 enable-active-high;
1764 }; !! 1781 };
1765 1782
1766 vdd_cdc_1v2_aud: regulator-vdd-cdc-1v !! 1783 vdd_cdc_1v2_aud: regulator@101 {
1767 compatible = "regulator-fixed !! 1784 compatible = "regulator-fixed";
1768 status = "disabled"; !! 1785 reg = <101>;
1769 regulator-name = "vdd_cdc_1v2 !! 1786 status = "disabled";
1770 regulator-min-microvolt = <12 !! 1787 regulator-name = "vdd_cdc_1v2_aud";
1771 regulator-max-microvolt = <12 !! 1788 regulator-min-microvolt = <1200000>;
1772 startup-delay-us = <250000>; !! 1789 regulator-max-microvolt = <1200000>;
>> 1790 startup-delay-us = <250000>;
1773 1791
1774 enable-active-high; !! 1792 enable-active-high;
1775 }; !! 1793 };
1776 1794
1777 vdd_disp_3v0: regulator-vdd-disp-3v0 !! 1795 vdd_disp_3v0: regulator@12 {
1778 compatible = "regulator-fixed !! 1796 compatible = "regulator-fixed";
1779 regulator-name = "vdd-disp-3v !! 1797 reg = <12>;
1780 regulator-enable-ramp-delay = !! 1798 regulator-name = "vdd-disp-3v0";
1781 regulator-min-microvolt = <30 !! 1799 regulator-enable-ramp-delay = <232>;
1782 regulator-max-microvolt = <30 !! 1800 regulator-min-microvolt = <3000000>;
1783 regulator-always-on; !! 1801 regulator-max-microvolt = <3000000>;
>> 1802 regulator-always-on;
1784 1803
1785 gpio = <&gpio TEGRA_GPIO(I, 3 !! 1804 gpio = <&gpio TEGRA_GPIO(I, 3) GPIO_ACTIVE_HIGH>;
1786 enable-active-high; !! 1805 enable-active-high;
1787 }; !! 1806 };
1788 1807
1789 vdd_fan: regulator-vdd-fan { !! 1808 vdd_fan: regulator@13 {
1790 compatible = "regulator-fixed !! 1809 compatible = "regulator-fixed";
1791 regulator-name = "vdd-fan"; !! 1810 reg = <13>;
1792 regulator-enable-ramp-delay = !! 1811 regulator-name = "vdd-fan";
1793 regulator-min-microvolt = <50 !! 1812 regulator-enable-ramp-delay = <284>;
1794 regulator-max-microvolt = <50 !! 1813 regulator-min-microvolt = <5000000>;
>> 1814 regulator-max-microvolt = <5000000>;
1795 1815
1796 gpio = <&gpio TEGRA_GPIO(E, 4 !! 1816 gpio = <&gpio TEGRA_GPIO(E, 4) GPIO_ACTIVE_HIGH>;
1797 enable-active-high; !! 1817 enable-active-high;
1798 }; !! 1818 };
1799 1819
1800 usb_vbus1: regulator-usb-vbus1 { !! 1820 usb_vbus1: regulator@14 {
1801 compatible = "regulator-fixed !! 1821 compatible = "regulator-fixed";
1802 regulator-name = "usb-vbus1"; !! 1822 reg = <14>;
1803 regulator-min-microvolt = <50 !! 1823 regulator-name = "usb-vbus1";
1804 regulator-max-microvolt = <50 !! 1824 regulator-min-microvolt = <5000000>;
1805 !! 1825 regulator-max-microvolt = <5000000>;
1806 gpio = <&gpio TEGRA_GPIO(CC, !! 1826
1807 enable-active-high; !! 1827 gpio = <&gpio TEGRA_GPIO(CC, 5) GPIO_ACTIVE_HIGH>;
1808 gpio-open-drain; !! 1828 enable-active-high;
1809 }; !! 1829 gpio-open-drain;
>> 1830 };
1810 1831
1811 usb_vbus2: regulator-usb-vbus2 { !! 1832 usb_vbus2: regulator@15 {
1812 compatible = "regulator-fixed !! 1833 compatible = "regulator-fixed";
1813 regulator-name = "usb-vbus2"; !! 1834 reg = <15>;
1814 regulator-min-microvolt = <50 !! 1835 regulator-name = "usb-vbus2";
1815 regulator-max-microvolt = <50 !! 1836 regulator-min-microvolt = <5000000>;
1816 !! 1837 regulator-max-microvolt = <5000000>;
1817 gpio = <&gpio TEGRA_GPIO(CC, !! 1838
1818 enable-active-high; !! 1839 gpio = <&gpio TEGRA_GPIO(CC, 4) GPIO_ACTIVE_HIGH>;
1819 gpio-open-drain; !! 1840 enable-active-high;
1820 }; !! 1841 gpio-open-drain;
>> 1842 };
1821 1843
1822 vdd_3v3_eth: regulator-vdd-3v3-eth { !! 1844 vdd_3v3_eth: regulator@16 {
1823 compatible = "regulator-fixed !! 1845 compatible = "regulator-fixed";
1824 regulator-name = "vdd-3v3-eth !! 1846 reg = <16>;
1825 regulator-min-microvolt = <33 !! 1847 regulator-name = "vdd-3v3-eth-a02";
1826 regulator-max-microvolt = <33 !! 1848 regulator-min-microvolt = <3300000>;
1827 regulator-always-on; !! 1849 regulator-max-microvolt = <3300000>;
1828 regulator-boot-on; !! 1850 regulator-always-on;
1829 !! 1851 regulator-boot-on;
1830 gpio = <&gpio TEGRA_GPIO(D, 4 !! 1852
1831 enable-active-high; !! 1853 gpio = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>;
1832 gpio-open-drain; !! 1854 enable-active-high;
>> 1855 gpio-open-drain;
>> 1856 };
1833 }; 1857 };
1834 }; 1858 };
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