1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/; 2 /dts-v1/;
3 3
4 #include <dt-bindings/input/gpio-keys.h> 4 #include <dt-bindings/input/gpio-keys.h>
5 #include <dt-bindings/input/linux-event-codes. 5 #include <dt-bindings/input/linux-event-codes.h>
6 #include <dt-bindings/mfd/max77620.h> 6 #include <dt-bindings/mfd/max77620.h>
7 7
8 #include "tegra210.dtsi" 8 #include "tegra210.dtsi"
9 9
10 / { 10 / {
11 model = "NVIDIA Jetson Nano Developer 11 model = "NVIDIA Jetson Nano Developer Kit";
12 compatible = "nvidia,p3450-0000", "nvi 12 compatible = "nvidia,p3450-0000", "nvidia,tegra210";
13 13
14 aliases { 14 aliases {
15 ethernet = "/pcie@1003000/pci@ 15 ethernet = "/pcie@1003000/pci@2,0/ethernet@0,0";
16 rtc0 = "/i2c@7000d000/pmic@3c" 16 rtc0 = "/i2c@7000d000/pmic@3c";
17 rtc1 = "/rtc@7000e000"; 17 rtc1 = "/rtc@7000e000";
18 serial0 = &uarta; 18 serial0 = &uarta;
19 }; 19 };
20 20
21 chosen { 21 chosen {
22 stdout-path = "serial0:115200n 22 stdout-path = "serial0:115200n8";
23 }; 23 };
24 24
25 memory@80000000 { 25 memory@80000000 {
26 device_type = "memory"; 26 device_type = "memory";
27 reg = <0x0 0x80000000 0x1 0x0> 27 reg = <0x0 0x80000000 0x1 0x0>;
28 }; 28 };
29 29
30 pcie@1003000 { 30 pcie@1003000 {
31 status = "okay"; 31 status = "okay";
32 32
>> 33 avdd-pll-uerefe-supply = <&vdd_pex_1v05>;
33 hvddio-pex-supply = <&vdd_1v8> 34 hvddio-pex-supply = <&vdd_1v8>;
34 dvddio-pex-supply = <&vdd_pex_ 35 dvddio-pex-supply = <&vdd_pex_1v05>;
>> 36 dvdd-pex-pll-supply = <&vdd_pex_1v05>;
>> 37 hvdd-pex-pll-e-supply = <&vdd_1v8>;
35 vddio-pex-ctl-supply = <&vdd_1 38 vddio-pex-ctl-supply = <&vdd_1v8>;
36 39
37 pci@1,0 { 40 pci@1,0 {
38 phys = <&{/padctl@7009f 41 phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>,
39 <&{/padctl@7009f 42 <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>,
40 <&{/padctl@7009f 43 <&{/padctl@7009f000/pads/pcie/lanes/pcie-3}>,
41 <&{/padctl@7009f 44 <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>;
42 phy-names = "pcie-0", 45 phy-names = "pcie-0", "pcie-1", "pcie-2", "pcie-3";
43 nvidia,num-lanes = <4> 46 nvidia,num-lanes = <4>;
44 status = "okay"; 47 status = "okay";
45 }; 48 };
46 49
47 pci@2,0 { 50 pci@2,0 {
48 phys = <&{/padctl@7009f 51 phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>;
49 phy-names = "pcie-0"; 52 phy-names = "pcie-0";
50 status = "okay"; 53 status = "okay";
51 54
52 ethernet@0,0 { 55 ethernet@0,0 {
53 reg = <0x00000 56 reg = <0x000000 0 0 0 0>;
54 local-mac-addr 57 local-mac-address = [ 00 00 00 00 00 00 ];
55 }; 58 };
56 }; 59 };
57 }; 60 };
58 61
59 host1x@50000000 { 62 host1x@50000000 {
60 dpaux@54040000 { 63 dpaux@54040000 {
61 status = "okay"; 64 status = "okay";
62 }; 65 };
63 66
64 vi@54080000 { 67 vi@54080000 {
65 status = "okay"; 68 status = "okay";
66 69
67 avdd-dsi-csi-supply = 70 avdd-dsi-csi-supply = <&vdd_sys_1v2>;
68 71
69 csi@838 { 72 csi@838 {
70 status = "okay 73 status = "okay";
71 }; 74 };
72 }; 75 };
73 76
74 sor@54540000 { 77 sor@54540000 {
75 status = "okay"; 78 status = "okay";
76 79
77 avdd-io-hdmi-dp-supply 80 avdd-io-hdmi-dp-supply = <&avdd_io_edp_1v05>;
78 vdd-hdmi-dp-pll-supply 81 vdd-hdmi-dp-pll-supply = <&vdd_1v8>;
79 82
80 nvidia,xbar-cfg = <2 1 83 nvidia,xbar-cfg = <2 1 0 3 4>;
81 nvidia,dpaux = <&dpaux 84 nvidia,dpaux = <&dpaux>;
82 }; 85 };
83 86
84 sor@54580000 { 87 sor@54580000 {
85 status = "okay"; 88 status = "okay";
86 89
87 avdd-io-hdmi-dp-supply 90 avdd-io-hdmi-dp-supply = <&avdd_1v05>;
88 vdd-hdmi-dp-pll-supply 91 vdd-hdmi-dp-pll-supply = <&vdd_1v8>;
89 hdmi-supply = <&vdd_hd 92 hdmi-supply = <&vdd_hdmi>;
90 93
91 nvidia,ddc-i2c-bus = < 94 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
92 nvidia,hpd-gpio = <&gp 95 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(CC, 1)
93 GPI 96 GPIO_ACTIVE_LOW>;
94 nvidia,xbar-cfg = <0 1 97 nvidia,xbar-cfg = <0 1 2 3 4>;
95 }; 98 };
96 99
97 dpaux@545c0000 { 100 dpaux@545c0000 {
98 status = "okay"; 101 status = "okay";
99 }; 102 };
100 103
101 i2c@546c0000 { 104 i2c@546c0000 {
102 status = "okay"; 105 status = "okay";
103 }; 106 };
104 }; 107 };
105 108
106 gpu@57000000 { 109 gpu@57000000 {
107 vdd-supply = <&vdd_gpu>; 110 vdd-supply = <&vdd_gpu>;
108 status = "okay"; 111 status = "okay";
109 }; 112 };
110 113
111 pinmux@700008d4 { 114 pinmux@700008d4 {
112 dvfs_pwm_active_state: pinmux- !! 115 dvfs_pwm_active_state: dvfs_pwm_active {
113 dvfs_pwm_pbb1 { 116 dvfs_pwm_pbb1 {
114 nvidia,pins = 117 nvidia,pins = "dvfs_pwm_pbb1";
115 nvidia,tristat 118 nvidia,tristate = <TEGRA_PIN_DISABLE>;
116 }; 119 };
117 }; 120 };
118 121
119 dvfs_pwm_inactive_state: pinmu !! 122 dvfs_pwm_inactive_state: dvfs_pwm_inactive {
120 dvfs_pwm_pbb1 { 123 dvfs_pwm_pbb1 {
121 nvidia,pins = 124 nvidia,pins = "dvfs_pwm_pbb1";
122 nvidia,tristat 125 nvidia,tristate = <TEGRA_PIN_ENABLE>;
123 }; 126 };
124 }; 127 };
125 }; 128 };
126 129
127 /* debug port */ 130 /* debug port */
128 serial@70006000 { 131 serial@70006000 {
129 /delete-property/ dmas; <<
130 /delete-property/ dma-names; <<
131 status = "okay"; 132 status = "okay";
132 }; 133 };
133 134
134 pwm@7000a000 { 135 pwm@7000a000 {
135 status = "okay"; 136 status = "okay";
136 }; 137 };
137 138
138 i2c@7000c500 { 139 i2c@7000c500 {
139 status = "okay"; 140 status = "okay";
140 clock-frequency = <100000>; 141 clock-frequency = <100000>;
141 142
142 eeprom@50 { 143 eeprom@50 {
143 compatible = "atmel,24 144 compatible = "atmel,24c02";
144 reg = <0x50>; 145 reg = <0x50>;
145 146
146 label = "module"; 147 label = "module";
147 vcc-supply = <&vdd_1v8 148 vcc-supply = <&vdd_1v8>;
148 address-width = <8>; 149 address-width = <8>;
149 pagesize = <8>; 150 pagesize = <8>;
150 size = <256>; 151 size = <256>;
151 read-only; 152 read-only;
152 }; 153 };
153 154
154 eeprom@57 { 155 eeprom@57 {
155 compatible = "atmel,24 156 compatible = "atmel,24c02";
156 reg = <0x57>; 157 reg = <0x57>;
157 158
158 label = "system"; 159 label = "system";
159 vcc-supply = <&vdd_1v8 160 vcc-supply = <&vdd_1v8>;
160 address-width = <8>; 161 address-width = <8>;
161 pagesize = <8>; 162 pagesize = <8>;
162 size = <256>; 163 size = <256>;
163 read-only; 164 read-only;
164 }; 165 };
165 }; 166 };
166 167
167 hdmi_ddc: i2c@7000c700 { 168 hdmi_ddc: i2c@7000c700 {
168 status = "okay"; 169 status = "okay";
169 clock-frequency = <100000>; 170 clock-frequency = <100000>;
170 }; 171 };
171 172
172 i2c@7000d000 { 173 i2c@7000d000 {
173 status = "okay"; 174 status = "okay";
174 clock-frequency = <400000>; 175 clock-frequency = <400000>;
175 176
176 pmic: pmic@3c { 177 pmic: pmic@3c {
177 compatible = "maxim,ma 178 compatible = "maxim,max77620";
178 reg = <0x3c>; 179 reg = <0x3c>;
179 interrupt-parent = <&t 180 interrupt-parent = <&tegra_pmc>;
180 interrupts = <51 IRQ_T 181 interrupts = <51 IRQ_TYPE_LEVEL_LOW>;
181 182
182 #interrupt-cells = <2> 183 #interrupt-cells = <2>;
183 interrupt-controller; 184 interrupt-controller;
184 185
185 #gpio-cells = <2>; 186 #gpio-cells = <2>;
186 gpio-controller; 187 gpio-controller;
187 188
188 pinctrl-names = "defau 189 pinctrl-names = "default";
189 pinctrl-0 = <&max77620 190 pinctrl-0 = <&max77620_default>;
190 191
191 fps { <<
192 fps0 { <<
193 maxim, <<
194 maxim, <<
195 }; <<
196 <<
197 fps1 { <<
198 maxim, <<
199 maxim, <<
200 }; <<
201 <<
202 fps2 { <<
203 maxim, <<
204 }; <<
205 }; <<
206 <<
207 max77620_default: pinm 192 max77620_default: pinmux {
208 gpio0 { 193 gpio0 {
209 pins = 194 pins = "gpio0";
210 functi 195 function = "gpio";
211 }; 196 };
212 197
213 gpio1 { 198 gpio1 {
214 pins = 199 pins = "gpio1";
215 functi 200 function = "fps-out";
216 drive- 201 drive-push-pull = <1>;
217 maxim, 202 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
218 maxim, 203 maxim,active-fps-power-up-slot = <0>;
219 maxim, 204 maxim,active-fps-power-down-slot = <7>;
220 }; 205 };
221 206
222 gpio2 { 207 gpio2 {
223 pins = 208 pins = "gpio2";
224 functi 209 function = "fps-out";
225 drive- 210 drive-open-drain = <1>;
226 maxim, 211 maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
227 maxim, 212 maxim,active-fps-power-up-slot = <0>;
228 maxim, 213 maxim,active-fps-power-down-slot = <7>;
229 }; 214 };
230 215
231 gpio3 { 216 gpio3 {
232 pins = 217 pins = "gpio3";
233 functi 218 function = "fps-out";
234 drive- 219 drive-open-drain = <1>;
235 maxim, 220 maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
236 maxim, 221 maxim,active-fps-power-up-slot = <4>;
237 maxim, 222 maxim,active-fps-power-down-slot = <3>;
238 }; 223 };
239 224
240 gpio4 { 225 gpio4 {
241 pins = 226 pins = "gpio4";
242 functi 227 function = "32k-out1";
243 }; 228 };
244 229
245 gpio5_6_7 { 230 gpio5_6_7 {
246 pins = 231 pins = "gpio5", "gpio6", "gpio7";
247 functi 232 function = "gpio";
248 drive- 233 drive-push-pull = <1>;
249 }; 234 };
250 }; 235 };
251 236
>> 237 fps {
>> 238 fps0 {
>> 239 maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>;
>> 240 maxim,suspend-fps-time-period-us = <5120>;
>> 241 };
>> 242
>> 243 fps1 {
>> 244 maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>;
>> 245 maxim,suspend-fps-time-period-us = <5120>;
>> 246 };
>> 247
>> 248 fps2 {
>> 249 maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>;
>> 250 };
>> 251 };
>> 252
252 regulators { 253 regulators {
253 in-ldo0-1-supp 254 in-ldo0-1-supply = <&vdd_pre>;
254 in-ldo2-supply 255 in-ldo2-supply = <&vdd_3v3_sys>;
255 in-ldo3-5-supp 256 in-ldo3-5-supply = <&vdd_1v8>;
256 in-ldo4-6-supp 257 in-ldo4-6-supply = <&vdd_5v0_sys>;
257 in-ldo7-8-supp 258 in-ldo7-8-supply = <&vdd_pre>;
258 in-sd0-supply 259 in-sd0-supply = <&vdd_5v0_sys>;
259 in-sd1-supply 260 in-sd1-supply = <&vdd_5v0_sys>;
260 in-sd2-supply 261 in-sd2-supply = <&vdd_5v0_sys>;
261 in-sd3-supply 262 in-sd3-supply = <&vdd_5v0_sys>;
262 263
263 vdd_soc: sd0 { 264 vdd_soc: sd0 {
264 regula 265 regulator-name = "VDD_SOC";
265 regula 266 regulator-min-microvolt = <1000000>;
266 regula 267 regulator-max-microvolt = <1170000>;
267 regula 268 regulator-enable-ramp-delay = <146>;
>> 269 regulator-disable-ramp-delay = <4080>;
268 regula 270 regulator-ramp-delay = <27500>;
269 regula 271 regulator-ramp-delay-scale = <300>;
270 regula 272 regulator-always-on;
271 regula 273 regulator-boot-on;
272 274
273 maxim, 275 maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
274 maxim, 276 maxim,active-fps-power-up-slot = <1>;
275 maxim, 277 maxim,active-fps-power-down-slot = <6>;
276 }; 278 };
277 279
278 vdd_ddr: sd1 { 280 vdd_ddr: sd1 {
279 regula 281 regulator-name = "VDD_DDR_1V1_PMIC";
280 regula 282 regulator-min-microvolt = <1150000>;
281 regula 283 regulator-max-microvolt = <1150000>;
282 regula 284 regulator-enable-ramp-delay = <176>;
>> 285 regulator-disable-ramp-delay = <145800>;
283 regula 286 regulator-ramp-delay = <27500>;
284 regula 287 regulator-ramp-delay-scale = <300>;
285 regula 288 regulator-always-on;
286 regula 289 regulator-boot-on;
287 290
288 maxim, 291 maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
289 maxim, 292 maxim,active-fps-power-up-slot = <5>;
290 maxim, 293 maxim,active-fps-power-down-slot = <2>;
291 }; 294 };
292 295
293 vdd_pre: sd2 { 296 vdd_pre: sd2 {
294 regula 297 regulator-name = "VDD_PRE_REG_1V35";
295 regula 298 regulator-min-microvolt = <1350000>;
296 regula 299 regulator-max-microvolt = <1350000>;
297 regula 300 regulator-enable-ramp-delay = <176>;
>> 301 regulator-disable-ramp-delay = <32000>;
298 regula 302 regulator-ramp-delay = <27500>;
299 regula 303 regulator-ramp-delay-scale = <350>;
300 regula 304 regulator-always-on;
301 regula 305 regulator-boot-on;
302 306
303 maxim, 307 maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
304 maxim, 308 maxim,active-fps-power-up-slot = <2>;
305 maxim, 309 maxim,active-fps-power-down-slot = <5>;
306 }; 310 };
307 311
308 vdd_1v8: sd3 { 312 vdd_1v8: sd3 {
309 regula 313 regulator-name = "VDD_1V8";
310 regula 314 regulator-min-microvolt = <1800000>;
311 regula 315 regulator-max-microvolt = <1800000>;
312 regula 316 regulator-enable-ramp-delay = <242>;
>> 317 regulator-disable-ramp-delay = <118000>;
313 regula 318 regulator-ramp-delay = <27500>;
314 regula 319 regulator-ramp-delay-scale = <360>;
315 regula 320 regulator-always-on;
316 regula 321 regulator-boot-on;
317 322
318 maxim, 323 maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
319 maxim, 324 maxim,active-fps-power-up-slot = <3>;
320 maxim, 325 maxim,active-fps-power-down-slot = <4>;
321 }; 326 };
322 327
323 vdd_sys_1v2: l 328 vdd_sys_1v2: ldo0 {
324 regula 329 regulator-name = "AVDD_SYS_1V2";
325 regula 330 regulator-min-microvolt = <1200000>;
326 regula 331 regulator-max-microvolt = <1200000>;
327 regula 332 regulator-enable-ramp-delay = <26>;
>> 333 regulator-disable-ramp-delay = <626>;
328 regula 334 regulator-ramp-delay = <100000>;
329 regula 335 regulator-ramp-delay-scale = <200>;
330 regula 336 regulator-always-on;
331 regula 337 regulator-boot-on;
332 338
333 maxim, 339 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
334 maxim, 340 maxim,active-fps-power-up-slot = <0>;
335 maxim, 341 maxim,active-fps-power-down-slot = <7>;
336 }; 342 };
337 343
338 vdd_pex_1v05: 344 vdd_pex_1v05: ldo1 {
339 regula 345 regulator-name = "VDD_PEX_1V05";
340 regula 346 regulator-min-microvolt = <1050000>;
341 regula 347 regulator-max-microvolt = <1050000>;
342 regula 348 regulator-enable-ramp-delay = <22>;
>> 349 regulator-disable-ramp-delay = <650>;
343 regula 350 regulator-ramp-delay = <100000>;
344 regula 351 regulator-ramp-delay-scale = <200>;
345 352
346 maxim, 353 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
347 maxim, 354 maxim,active-fps-power-up-slot = <0>;
348 maxim, 355 maxim,active-fps-power-down-slot = <7>;
349 }; 356 };
350 357
351 vddio_sdmmc: l 358 vddio_sdmmc: ldo2 {
352 regula 359 regulator-name = "VDDIO_SDMMC";
353 regula 360 regulator-min-microvolt = <1800000>;
354 regula 361 regulator-max-microvolt = <3300000>;
355 regula 362 regulator-enable-ramp-delay = <62>;
>> 363 regulator-disable-ramp-delay = <650>;
356 regula 364 regulator-ramp-delay = <100000>;
357 regula 365 regulator-ramp-delay-scale = <200>;
358 366
359 maxim, 367 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
360 maxim, 368 maxim,active-fps-power-up-slot = <0>;
361 maxim, 369 maxim,active-fps-power-down-slot = <7>;
362 }; 370 };
363 371
364 ldo3 { 372 ldo3 {
365 status 373 status = "disabled";
366 }; 374 };
367 375
368 vdd_rtc: ldo4 376 vdd_rtc: ldo4 {
369 regula 377 regulator-name = "VDD_RTC";
370 regula 378 regulator-min-microvolt = <850000>;
371 regula 379 regulator-max-microvolt = <1100000>;
372 regula 380 regulator-enable-ramp-delay = <22>;
>> 381 regulator-disable-ramp-delay = <610>;
373 regula 382 regulator-ramp-delay = <100000>;
374 regula 383 regulator-ramp-delay-scale = <200>;
375 regula 384 regulator-disable-active-discharge;
376 regula 385 regulator-always-on;
377 regula 386 regulator-boot-on;
378 387
379 maxim, 388 maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
380 maxim, 389 maxim,active-fps-power-up-slot = <1>;
381 maxim, 390 maxim,active-fps-power-down-slot = <6>;
382 }; 391 };
383 392
384 ldo5 { 393 ldo5 {
385 status 394 status = "disabled";
386 }; 395 };
387 396
388 ldo6 { 397 ldo6 {
389 status 398 status = "disabled";
390 }; 399 };
391 400
392 avdd_1v05_pll: 401 avdd_1v05_pll: ldo7 {
393 regula 402 regulator-name = "AVDD_1V05_PLL";
394 regula 403 regulator-min-microvolt = <1050000>;
395 regula 404 regulator-max-microvolt = <1050000>;
396 regula 405 regulator-enable-ramp-delay = <24>;
>> 406 regulator-disable-ramp-delay = <2768>;
397 regula 407 regulator-ramp-delay = <100000>;
398 regula 408 regulator-ramp-delay-scale = <200>;
399 409
400 maxim, 410 maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
401 maxim, 411 maxim,active-fps-power-up-slot = <3>;
402 maxim, 412 maxim,active-fps-power-down-slot = <4>;
403 }; 413 };
404 414
405 avdd_1v05: ldo 415 avdd_1v05: ldo8 {
406 regula 416 regulator-name = "AVDD_SATA_HDMI_DP_1V05";
407 regula 417 regulator-min-microvolt = <1050000>;
408 regula 418 regulator-max-microvolt = <1050000>;
409 regula 419 regulator-enable-ramp-delay = <22>;
>> 420 regulator-disable-ramp-delay = <1160>;
410 regula 421 regulator-ramp-delay = <100000>;
411 regula 422 regulator-ramp-delay-scale = <200>;
412 423
413 maxim, 424 maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
414 maxim, 425 maxim,active-fps-power-up-slot = <6>;
415 maxim, 426 maxim,active-fps-power-down-slot = <1>;
416 }; 427 };
417 }; 428 };
418 }; 429 };
419 }; 430 };
420 431
421 pmc@7000e400 { 432 pmc@7000e400 {
422 nvidia,invert-interrupt; 433 nvidia,invert-interrupt;
423 nvidia,suspend-mode = <0>; 434 nvidia,suspend-mode = <0>;
424 nvidia,cpu-pwr-good-time = <0> 435 nvidia,cpu-pwr-good-time = <0>;
425 nvidia,cpu-pwr-off-time = <0>; 436 nvidia,cpu-pwr-off-time = <0>;
426 nvidia,core-pwr-good-time = <4 437 nvidia,core-pwr-good-time = <4587 3876>;
427 nvidia,core-pwr-off-time = <39 438 nvidia,core-pwr-off-time = <39065>;
428 nvidia,core-power-req-active-h 439 nvidia,core-power-req-active-high;
429 nvidia,sys-clock-req-active-hi 440 nvidia,sys-clock-req-active-high;
430 }; 441 };
431 442
432 hda@70030000 { 443 hda@70030000 {
433 nvidia,model = "NVIDIA Jetson 444 nvidia,model = "NVIDIA Jetson Nano HDA";
434 445
435 status = "okay"; 446 status = "okay";
436 }; 447 };
437 448
438 usb@70090000 { 449 usb@70090000 {
439 phys = <&{/padctl@7009f000/pads 450 phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>,
440 <&{/padctl@7009f000/pads 451 <&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>,
441 <&{/padctl@7009f000/pads 452 <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>,
442 <&{/padctl@7009f000/pads 453 <&{/padctl@7009f000/pads/pcie/lanes/pcie-6}>;
443 phy-names = "usb2-0", "usb2-1" 454 phy-names = "usb2-0", "usb2-1", "usb2-2", "usb3-0";
444 455
445 avdd-usb-supply = <&vdd_3v3_sy 456 avdd-usb-supply = <&vdd_3v3_sys>;
446 dvddio-pex-supply = <&vdd_pex_ 457 dvddio-pex-supply = <&vdd_pex_1v05>;
447 hvddio-pex-supply = <&vdd_1v8> 458 hvddio-pex-supply = <&vdd_1v8>;
>> 459 /* these really belong to the XUSB pad controller */
>> 460 avdd-pll-utmip-supply = <&vdd_1v8>;
>> 461 avdd-pll-uerefe-supply = <&vdd_pex_1v05>;
>> 462 dvdd-usb-ss-pll-supply = <&vdd_pex_1v05>;
>> 463 hvdd-usb-ss-pll-e-supply = <&vdd_1v8>;
448 464
449 status = "okay"; 465 status = "okay";
450 }; 466 };
451 467
452 padctl@7009f000 { 468 padctl@7009f000 {
453 status = "okay"; 469 status = "okay";
454 470
455 avdd-pll-utmip-supply = <&vdd_ 471 avdd-pll-utmip-supply = <&vdd_1v8>;
456 avdd-pll-uerefe-supply = <&vdd 472 avdd-pll-uerefe-supply = <&vdd_pex_1v05>;
457 dvdd-pex-pll-supply = <&vdd_pe 473 dvdd-pex-pll-supply = <&vdd_pex_1v05>;
458 hvdd-pex-pll-e-supply = <&vdd_ 474 hvdd-pex-pll-e-supply = <&vdd_1v8>;
459 475
460 pads { 476 pads {
461 usb2 { 477 usb2 {
462 status = "okay 478 status = "okay";
463 479
464 lanes { 480 lanes {
465 micro_ 481 micro_b: usb2-0 {
466 482 nvidia,function = "xusb";
467 483 status = "okay";
468 }; 484 };
469 485
470 usb2-1 486 usb2-1 {
471 487 nvidia,function = "xusb";
472 488 status = "okay";
473 }; 489 };
474 490
475 usb2-2 491 usb2-2 {
476 492 nvidia,function = "xusb";
477 493 status = "okay";
478 }; 494 };
479 }; 495 };
480 }; 496 };
481 497
482 pcie { 498 pcie {
483 status = "okay 499 status = "okay";
484 500
485 lanes { 501 lanes {
486 pcie-0 502 pcie-0 {
487 503 nvidia,function = "pcie-x1";
488 504 status = "okay";
489 }; 505 };
490 506
491 pcie-1 507 pcie-1 {
492 508 nvidia,function = "pcie-x4";
493 509 status = "okay";
494 }; 510 };
495 511
496 pcie-2 512 pcie-2 {
497 513 nvidia,function = "pcie-x4";
498 514 status = "okay";
499 }; 515 };
500 516
501 pcie-3 517 pcie-3 {
502 518 nvidia,function = "pcie-x4";
503 519 status = "okay";
504 }; 520 };
505 521
506 pcie-4 522 pcie-4 {
507 523 nvidia,function = "pcie-x4";
508 524 status = "okay";
509 }; 525 };
510 526
511 pcie-5 527 pcie-5 {
512 528 nvidia,function = "usb3-ss";
513 529 status = "okay";
514 }; 530 };
515 531
516 pcie-6 532 pcie-6 {
517 533 nvidia,function = "usb3-ss";
518 534 status = "okay";
519 }; 535 };
520 }; 536 };
521 }; 537 };
522 }; 538 };
523 539
524 ports { 540 ports {
525 usb2-0 { 541 usb2-0 {
526 status = "okay 542 status = "okay";
527 mode = "periph 543 mode = "peripheral";
528 usb-role-switc 544 usb-role-switch;
529 545
530 vbus-supply = 546 vbus-supply = <&vdd_5v0_usb>;
531 547
532 connector { 548 connector {
533 compat 549 compatible = "gpio-usb-b-connector",
534 550 "usb-b-connector";
535 label 551 label = "micro-USB";
536 type = 552 type = "micro";
537 vbus-g 553 vbus-gpios = <&gpio TEGRA_GPIO(CC, 4)
538 554 GPIO_ACTIVE_LOW>;
539 }; 555 };
540 }; 556 };
541 557
542 usb2-1 { 558 usb2-1 {
543 status = "okay 559 status = "okay";
544 mode = "host"; 560 mode = "host";
545 }; 561 };
546 562
547 usb2-2 { 563 usb2-2 {
548 status = "okay 564 status = "okay";
549 mode = "host"; 565 mode = "host";
550 }; 566 };
551 567
552 usb3-0 { 568 usb3-0 {
553 status = "okay 569 status = "okay";
554 nvidia,usb2-co 570 nvidia,usb2-companion = <1>;
555 vbus-supply = 571 vbus-supply = <&vdd_hub_3v3>;
556 }; 572 };
557 }; 573 };
558 }; 574 };
559 575
560 mmc@700b0000 { 576 mmc@700b0000 {
561 status = "okay"; 577 status = "okay";
562 bus-width = <4>; 578 bus-width = <4>;
563 579
564 cd-gpios = <&gpio TEGRA_GPIO(Z 580 cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>;
565 disable-wp; 581 disable-wp;
566 582
567 vqmmc-supply = <&vddio_sdmmc>; 583 vqmmc-supply = <&vddio_sdmmc>;
568 vmmc-supply = <&vdd_3v3_sd>; 584 vmmc-supply = <&vdd_3v3_sd>;
569 }; 585 };
570 586
571 mmc@700b0400 { 587 mmc@700b0400 {
572 status = "okay"; 588 status = "okay";
573 bus-width = <4>; 589 bus-width = <4>;
574 590
575 vqmmc-supply = <&vdd_1v8>; 591 vqmmc-supply = <&vdd_1v8>;
576 vmmc-supply = <&vdd_3v3_sys>; 592 vmmc-supply = <&vdd_3v3_sys>;
577 593
578 non-removable; 594 non-removable;
579 cap-sdio-irq; 595 cap-sdio-irq;
580 keep-power-in-suspend; 596 keep-power-in-suspend;
581 wakeup-source; 597 wakeup-source;
582 }; 598 };
583 599
584 usb@700d0000 { 600 usb@700d0000 {
585 status = "okay"; 601 status = "okay";
586 phys = <µ_b>; 602 phys = <µ_b>;
587 phy-names = "usb2-0"; 603 phy-names = "usb2-0";
588 avddio-usb-supply = <&vdd_3v3_ 604 avddio-usb-supply = <&vdd_3v3_sys>;
589 hvdd-usb-supply = <&vdd_1v8>; 605 hvdd-usb-supply = <&vdd_1v8>;
590 }; 606 };
591 607
592 clock@70110000 { 608 clock@70110000 {
593 status = "okay"; 609 status = "okay";
594 610
595 nvidia,cf = <6>; 611 nvidia,cf = <6>;
596 nvidia,ci = <0>; 612 nvidia,ci = <0>;
597 nvidia,cg = <2>; 613 nvidia,cg = <2>;
598 nvidia,droop-ctrl = <0x00000f0 614 nvidia,droop-ctrl = <0x00000f00>;
599 nvidia,force-mode = <1>; 615 nvidia,force-mode = <1>;
600 nvidia,sample-rate = <25000>; 616 nvidia,sample-rate = <25000>;
601 617
602 nvidia,pwm-min-microvolts = <7 618 nvidia,pwm-min-microvolts = <708000>;
603 nvidia,pwm-period-nanoseconds 619 nvidia,pwm-period-nanoseconds = <2500>; /* 2.5us */
604 nvidia,pwm-to-pmic; 620 nvidia,pwm-to-pmic;
605 nvidia,pwm-tristate-microvolts 621 nvidia,pwm-tristate-microvolts = <1000000>;
606 nvidia,pwm-voltage-step-microv 622 nvidia,pwm-voltage-step-microvolts = <19200>;
607 623
608 pinctrl-names = "dvfs_pwm_enab 624 pinctrl-names = "dvfs_pwm_enable", "dvfs_pwm_disable";
609 pinctrl-0 = <&dvfs_pwm_active_ 625 pinctrl-0 = <&dvfs_pwm_active_state>;
610 pinctrl-1 = <&dvfs_pwm_inactiv 626 pinctrl-1 = <&dvfs_pwm_inactive_state>;
611 }; 627 };
612 628
613 aconnect@702c0000 { 629 aconnect@702c0000 {
614 status = "okay"; 630 status = "okay";
615 631
>> 632 dma-controller@702e2000 {
>> 633 status = "okay";
>> 634 };
>> 635
>> 636 interrupt-controller@702f9000 {
>> 637 status = "okay";
>> 638 };
>> 639
616 ahub@702d0800 { 640 ahub@702d0800 {
617 status = "okay"; 641 status = "okay";
618 642
619 admaif@702d0000 { 643 admaif@702d0000 {
620 status = "okay 644 status = "okay";
621 }; 645 };
622 646
623 i2s@702d1200 { 647 i2s@702d1200 {
624 status = "okay 648 status = "okay";
625 649
626 ports { 650 ports {
627 #addre 651 #address-cells = <1>;
628 #size- 652 #size-cells = <0>;
629 653
630 port@0 654 port@0 {
631 655 reg = <0>;
632 656
633 657 i2s3_cif_ep: endpoint {
634 658 remote-endpoint = <&xbar_i2s3_ep>;
635 659 };
636 }; 660 };
637 661
638 i2s3_p 662 i2s3_port: port@1 {
639 663 reg = <1>;
640 664
641 665 i2s3_dap_ep: endpoint {
642 666 dai-format = "i2s";
643 667 /* Placeholder for external Codec */
644 668 };
645 }; 669 };
646 }; 670 };
647 }; 671 };
648 672
649 i2s@702d1300 { 673 i2s@702d1300 {
650 status = "okay 674 status = "okay";
651 675
652 ports { 676 ports {
653 #addre 677 #address-cells = <1>;
654 #size- 678 #size-cells = <0>;
655 679
656 port@0 680 port@0 {
657 681 reg = <0>;
658 682
659 683 i2s4_cif_ep: endpoint {
660 684 remote-endpoint = <&xbar_i2s4_ep>;
661 685 };
662 }; 686 };
663 687
664 i2s4_p 688 i2s4_port: port@1 {
665 689 reg = <1>;
666 690
667 !! 691 i2s4_dap_ep: endpoint@0 {
668 692 dai-format = "i2s";
669 693 /* Placeholder for external Codec */
670 694 };
671 }; 695 };
672 }; 696 };
673 }; 697 };
674 698
675 sfc@702d2000 { <<
676 status = "okay <<
677 <<
678 ports { <<
679 #addre <<
680 #size- <<
681 <<
682 port@0 <<
683 <<
684 <<
685 <<
686 <<
687 <<
688 }; <<
689 <<
690 sfc1_o <<
691 <<
692 <<
693 <<
694 <<
695 <<
696 }; <<
697 }; <<
698 }; <<
699 <<
700 sfc@702d2200 { <<
701 status = "okay <<
702 <<
703 ports { <<
704 #addre <<
705 #size- <<
706 <<
707 port@0 <<
708 <<
709 <<
710 <<
711 <<
712 <<
713 }; <<
714 <<
715 sfc2_o <<
716 <<
717 <<
718 <<
719 <<
720 <<
721 }; <<
722 }; <<
723 }; <<
724 <<
725 sfc@702d2400 { <<
726 status = "okay <<
727 <<
728 ports { <<
729 #addre <<
730 #size- <<
731 <<
732 port@0 <<
733 <<
734 <<
735 <<
736 <<
737 <<
738 }; <<
739 <<
740 sfc3_o <<
741 <<
742 <<
743 <<
744 <<
745 <<
746 }; <<
747 }; <<
748 }; <<
749 <<
750 sfc@702d2600 { <<
751 status = "okay <<
752 <<
753 ports { <<
754 #addre <<
755 #size- <<
756 <<
757 port@0 <<
758 <<
759 <<
760 <<
761 <<
762 <<
763 }; <<
764 <<
765 sfc4_o <<
766 <<
767 <<
768 <<
769 <<
770 <<
771 }; <<
772 }; <<
773 }; <<
774 <<
775 amx@702d3000 { <<
776 status = "okay <<
777 <<
778 ports { <<
779 #addre <<
780 #size- <<
781 <<
782 port@0 <<
783 <<
784 <<
785 <<
786 <<
787 <<
788 }; <<
789 <<
790 port@1 <<
791 <<
792 <<
793 <<
794 <<
795 <<
796 }; <<
797 <<
798 port@2 <<
799 <<
800 <<
801 <<
802 <<
803 <<
804 }; <<
805 <<
806 port@3 <<
807 <<
808 <<
809 <<
810 <<
811 <<
812 }; <<
813 <<
814 amx1_o <<
815 <<
816 <<
817 <<
818 <<
819 <<
820 }; <<
821 }; <<
822 }; <<
823 <<
824 amx@702d3100 { <<
825 status = "okay <<
826 <<
827 ports { <<
828 #addre <<
829 #size- <<
830 <<
831 port@0 <<
832 <<
833 <<
834 <<
835 <<
836 <<
837 }; <<
838 <<
839 port@1 <<
840 <<
841 <<
842 <<
843 <<
844 <<
845 }; <<
846 <<
847 amx2_i <<
848 <<
849 <<
850 <<
851 <<
852 <<
853 }; <<
854 <<
855 amx2_i <<
856 <<
857 <<
858 <<
859 <<
860 <<
861 }; <<
862 <<
863 amx2_o <<
864 <<
865 <<
866 <<
867 <<
868 <<
869 }; <<
870 }; <<
871 }; <<
872 <<
873 adx@702d3800 { <<
874 status = "okay <<
875 <<
876 ports { <<
877 #addre <<
878 #size- <<
879 <<
880 port@0 <<
881 <<
882 <<
883 <<
884 <<
885 <<
886 }; <<
887 <<
888 adx1_o <<
889 <<
890 <<
891 <<
892 <<
893 <<
894 }; <<
895 <<
896 adx1_o <<
897 <<
898 <<
899 <<
900 <<
901 <<
902 }; <<
903 <<
904 adx1_o <<
905 <<
906 <<
907 <<
908 <<
909 <<
910 }; <<
911 <<
912 adx1_o <<
913 <<
914 <<
915 <<
916 <<
917 <<
918 }; <<
919 }; <<
920 }; <<
921 <<
922 adx@702d3900 { <<
923 status = "okay <<
924 <<
925 ports { <<
926 #addre <<
927 #size- <<
928 <<
929 port@0 <<
930 <<
931 <<
932 <<
933 <<
934 <<
935 }; <<
936 <<
937 adx2_o <<
938 <<
939 <<
940 <<
941 <<
942 <<
943 }; <<
944 <<
945 adx2_o <<
946 <<
947 <<
948 <<
949 <<
950 <<
951 }; <<
952 <<
953 adx2_o <<
954 <<
955 <<
956 <<
957 <<
958 <<
959 }; <<
960 <<
961 adx2_o <<
962 <<
963 <<
964 <<
965 <<
966 <<
967 }; <<
968 }; <<
969 }; <<
970 <<
971 dmic@702d4000 { 699 dmic@702d4000 {
972 status = "okay 700 status = "okay";
973 701
974 ports { 702 ports {
975 #addre 703 #address-cells = <1>;
976 #size- 704 #size-cells = <0>;
977 705
978 port@0 706 port@0 {
979 707 reg = <0>;
980 708
981 !! 709 dmic1_cif_ep: endpoint@0 {
982 710 remote-endpoint = <&xbar_dmic1_ep>;
983 711 };
984 }; 712 };
985 713
986 dmic1_ 714 dmic1_port: port@1 {
987 715 reg = <1>;
988 716
989 !! 717 dmic1_dap_ep: endpoint@0 {
990 718 /* Placeholder for external Codec */
991 719 };
992 }; 720 };
993 }; 721 };
994 }; 722 };
995 723
996 dmic@702d4100 { 724 dmic@702d4100 {
997 status = "okay 725 status = "okay";
998 726
999 ports { 727 ports {
1000 #addr 728 #address-cells = <1>;
1001 #size 729 #size-cells = <0>;
1002 730
1003 port@ 731 port@0 {
1004 732 reg = <0>;
1005 733
1006 !! 734 dmic2_cif_ep: endpoint@0 {
1007 735 remote-endpoint = <&xbar_dmic2_ep>;
1008 736 };
1009 }; 737 };
1010 738
1011 dmic2 739 dmic2_port: port@1 {
1012 740 reg = <1>;
1013 741
1014 !! 742 dmic2_dap_ep: endpoint@0 {
1015 743 /* Placeholder for external Codec */
1016 744 };
1017 }; 745 };
1018 }; 746 };
1019 }; 747 };
1020 748
1021 processing-engine@702 <<
1022 status = "oka <<
1023 <<
1024 ports { <<
1025 #addr <<
1026 #size <<
1027 <<
1028 port@ <<
1029 <<
1030 <<
1031 <<
1032 <<
1033 <<
1034 }; <<
1035 <<
1036 ope1_ <<
1037 <<
1038 <<
1039 <<
1040 <<
1041 <<
1042 }; <<
1043 }; <<
1044 }; <<
1045 <<
1046 processing-engine@702 <<
1047 status = "oka <<
1048 <<
1049 ports { <<
1050 #addr <<
1051 #size <<
1052 <<
1053 port@ <<
1054 <<
1055 <<
1056 <<
1057 <<
1058 <<
1059 }; <<
1060 <<
1061 ope2_ <<
1062 <<
1063 <<
1064 <<
1065 <<
1066 <<
1067 }; <<
1068 }; <<
1069 }; <<
1070 <<
1071 mvc@702da000 { <<
1072 status = "oka <<
1073 <<
1074 ports { <<
1075 #addr <<
1076 #size <<
1077 <<
1078 port@ <<
1079 <<
1080 <<
1081 <<
1082 <<
1083 <<
1084 }; <<
1085 <<
1086 mvc1_ <<
1087 <<
1088 <<
1089 <<
1090 <<
1091 <<
1092 }; <<
1093 }; <<
1094 }; <<
1095 <<
1096 mvc@702da200 { <<
1097 status = "oka <<
1098 <<
1099 ports { <<
1100 #addr <<
1101 #size <<
1102 <<
1103 port@ <<
1104 <<
1105 <<
1106 <<
1107 <<
1108 <<
1109 }; <<
1110 <<
1111 mvc2_ <<
1112 <<
1113 <<
1114 <<
1115 <<
1116 <<
1117 }; <<
1118 }; <<
1119 }; <<
1120 <<
1121 amixer@702dbb00 { <<
1122 status = "oka <<
1123 <<
1124 ports { <<
1125 #addr <<
1126 #size <<
1127 <<
1128 port@ <<
1129 <<
1130 <<
1131 <<
1132 <<
1133 <<
1134 }; <<
1135 <<
1136 port@ <<
1137 <<
1138 <<
1139 <<
1140 <<
1141 <<
1142 }; <<
1143 <<
1144 port@ <<
1145 <<
1146 <<
1147 <<
1148 <<
1149 <<
1150 }; <<
1151 <<
1152 port@ <<
1153 <<
1154 <<
1155 <<
1156 <<
1157 <<
1158 }; <<
1159 <<
1160 port@ <<
1161 <<
1162 <<
1163 <<
1164 <<
1165 <<
1166 }; <<
1167 <<
1168 port@ <<
1169 <<
1170 <<
1171 <<
1172 <<
1173 <<
1174 }; <<
1175 <<
1176 port@ <<
1177 <<
1178 <<
1179 <<
1180 <<
1181 <<
1182 }; <<
1183 <<
1184 port@ <<
1185 <<
1186 <<
1187 <<
1188 <<
1189 <<
1190 }; <<
1191 <<
1192 port@ <<
1193 <<
1194 <<
1195 <<
1196 <<
1197 <<
1198 }; <<
1199 <<
1200 port@ <<
1201 <<
1202 <<
1203 <<
1204 <<
1205 <<
1206 }; <<
1207 <<
1208 mixer <<
1209 <<
1210 <<
1211 <<
1212 <<
1213 <<
1214 }; <<
1215 <<
1216 mixer <<
1217 <<
1218 <<
1219 <<
1220 <<
1221 <<
1222 }; <<
1223 <<
1224 mixer <<
1225 <<
1226 <<
1227 <<
1228 <<
1229 <<
1230 }; <<
1231 <<
1232 mixer <<
1233 <<
1234 <<
1235 <<
1236 <<
1237 <<
1238 }; <<
1239 <<
1240 mixer <<
1241 <<
1242 <<
1243 <<
1244 <<
1245 <<
1246 }; <<
1247 }; <<
1248 }; <<
1249 <<
1250 ports { 749 ports {
1251 xbar_i2s3_por 750 xbar_i2s3_port: port@c {
1252 reg = 751 reg = <0xc>;
1253 752
1254 xbar_ 753 xbar_i2s3_ep: endpoint {
1255 754 remote-endpoint = <&i2s3_cif_ep>;
1256 }; 755 };
1257 }; 756 };
1258 757
1259 xbar_i2s4_por 758 xbar_i2s4_port: port@d {
1260 reg = 759 reg = <0xd>;
1261 760
1262 xbar_ 761 xbar_i2s4_ep: endpoint {
1263 762 remote-endpoint = <&i2s4_cif_ep>;
1264 }; 763 };
1265 }; 764 };
1266 765
1267 xbar_dmic1_po 766 xbar_dmic1_port: port@f {
1268 reg = 767 reg = <0xf>;
1269 768
1270 xbar_ 769 xbar_dmic1_ep: endpoint {
1271 770 remote-endpoint = <&dmic1_cif_ep>;
1272 }; 771 };
1273 }; 772 };
1274 773
1275 xbar_dmic2_po 774 xbar_dmic2_port: port@10 {
1276 reg = 775 reg = <0x10>;
1277 776
1278 xbar_ 777 xbar_dmic2_ep: endpoint {
1279 778 remote-endpoint = <&dmic2_cif_ep>;
1280 }; 779 };
1281 }; 780 };
1282 <<
1283 xbar_sfc1_in_ <<
1284 reg = <<
1285 <<
1286 xbar_ <<
1287 <<
1288 }; <<
1289 }; <<
1290 <<
1291 port@13 { <<
1292 reg = <<
1293 <<
1294 xbar_ <<
1295 <<
1296 }; <<
1297 }; <<
1298 <<
1299 xbar_sfc2_in_ <<
1300 reg = <<
1301 <<
1302 xbar_ <<
1303 <<
1304 }; <<
1305 }; <<
1306 <<
1307 port@15 { <<
1308 reg = <<
1309 <<
1310 xbar_ <<
1311 <<
1312 }; <<
1313 }; <<
1314 <<
1315 xbar_sfc3_in_ <<
1316 reg = <<
1317 <<
1318 xbar_ <<
1319 <<
1320 }; <<
1321 }; <<
1322 <<
1323 port@17 { <<
1324 reg = <<
1325 <<
1326 xbar_ <<
1327 <<
1328 }; <<
1329 }; <<
1330 <<
1331 xbar_sfc4_in_ <<
1332 reg = <<
1333 <<
1334 xbar_ <<
1335 <<
1336 }; <<
1337 }; <<
1338 <<
1339 port@19 { <<
1340 reg = <<
1341 <<
1342 xbar_ <<
1343 <<
1344 }; <<
1345 }; <<
1346 <<
1347 xbar_mvc1_in_ <<
1348 reg = <<
1349 <<
1350 xbar_ <<
1351 <<
1352 }; <<
1353 }; <<
1354 <<
1355 port@1b { <<
1356 reg = <<
1357 <<
1358 xbar_ <<
1359 <<
1360 }; <<
1361 }; <<
1362 <<
1363 xbar_mvc2_in_ <<
1364 reg = <<
1365 <<
1366 xbar_ <<
1367 <<
1368 }; <<
1369 }; <<
1370 <<
1371 port@1d { <<
1372 reg = <<
1373 <<
1374 xbar_ <<
1375 <<
1376 }; <<
1377 }; <<
1378 <<
1379 xbar_amx1_in1 <<
1380 reg = <<
1381 <<
1382 xbar_ <<
1383 <<
1384 }; <<
1385 }; <<
1386 <<
1387 xbar_amx1_in2 <<
1388 reg = <<
1389 <<
1390 xbar_ <<
1391 <<
1392 }; <<
1393 }; <<
1394 <<
1395 xbar_amx1_in3 <<
1396 reg = <<
1397 <<
1398 xbar_ <<
1399 <<
1400 }; <<
1401 }; <<
1402 <<
1403 xbar_amx1_in4 <<
1404 reg = <<
1405 <<
1406 xbar_ <<
1407 <<
1408 }; <<
1409 }; <<
1410 <<
1411 port@22 { <<
1412 reg = <<
1413 <<
1414 xbar_ <<
1415 <<
1416 }; <<
1417 }; <<
1418 <<
1419 xbar_amx2_in1 <<
1420 reg = <<
1421 <<
1422 xbar_ <<
1423 <<
1424 }; <<
1425 }; <<
1426 <<
1427 xbar_amx2_in2 <<
1428 reg = <<
1429 <<
1430 xbar_ <<
1431 <<
1432 }; <<
1433 }; <<
1434 <<
1435 xbar_amx2_in3 <<
1436 reg = <<
1437 <<
1438 xbar_ <<
1439 <<
1440 }; <<
1441 }; <<
1442 <<
1443 xbar_amx2_in4 <<
1444 reg = <<
1445 <<
1446 xbar_ <<
1447 <<
1448 }; <<
1449 }; <<
1450 <<
1451 port@27 { <<
1452 reg = <<
1453 <<
1454 xbar_ <<
1455 <<
1456 }; <<
1457 }; <<
1458 <<
1459 xbar_adx1_in_ <<
1460 reg = <<
1461 <<
1462 xbar_ <<
1463 <<
1464 }; <<
1465 }; <<
1466 <<
1467 port@29 { <<
1468 reg = <<
1469 <<
1470 xbar_ <<
1471 <<
1472 }; <<
1473 }; <<
1474 <<
1475 port@2a { <<
1476 reg = <<
1477 <<
1478 xbar_ <<
1479 <<
1480 }; <<
1481 }; <<
1482 <<
1483 port@2b { <<
1484 reg = <<
1485 <<
1486 xbar_ <<
1487 <<
1488 }; <<
1489 }; <<
1490 <<
1491 port@2c { <<
1492 reg = <<
1493 <<
1494 xbar_ <<
1495 <<
1496 }; <<
1497 }; <<
1498 <<
1499 xbar_adx2_in_ <<
1500 reg = <<
1501 <<
1502 xbar_ <<
1503 <<
1504 }; <<
1505 }; <<
1506 <<
1507 port@2e { <<
1508 reg = <<
1509 <<
1510 xbar_ <<
1511 <<
1512 }; <<
1513 }; <<
1514 <<
1515 port@2f { <<
1516 reg = <<
1517 <<
1518 xbar_ <<
1519 <<
1520 }; <<
1521 }; <<
1522 <<
1523 port@30 { <<
1524 reg = <<
1525 <<
1526 xbar_ <<
1527 <<
1528 }; <<
1529 }; <<
1530 <<
1531 port@31 { <<
1532 reg = <<
1533 <<
1534 xbar_ <<
1535 <<
1536 }; <<
1537 }; <<
1538 <<
1539 xbar_mixer_in <<
1540 reg = <<
1541 <<
1542 xbar_ <<
1543 <<
1544 }; <<
1545 }; <<
1546 <<
1547 xbar_mixer_in <<
1548 reg = <<
1549 <<
1550 xbar_ <<
1551 <<
1552 }; <<
1553 }; <<
1554 <<
1555 xbar_mixer_in <<
1556 reg = <<
1557 <<
1558 xbar_ <<
1559 <<
1560 }; <<
1561 }; <<
1562 <<
1563 xbar_mixer_in <<
1564 reg = <<
1565 <<
1566 xbar_ <<
1567 <<
1568 }; <<
1569 }; <<
1570 <<
1571 xbar_mixer_in <<
1572 reg = <<
1573 <<
1574 xbar_ <<
1575 <<
1576 }; <<
1577 }; <<
1578 <<
1579 xbar_mixer_in <<
1580 reg = <<
1581 <<
1582 xbar_ <<
1583 <<
1584 }; <<
1585 }; <<
1586 <<
1587 xbar_mixer_in <<
1588 reg = <<
1589 <<
1590 xbar_ <<
1591 <<
1592 }; <<
1593 }; <<
1594 <<
1595 xbar_mixer_in <<
1596 reg = <<
1597 <<
1598 xbar_ <<
1599 <<
1600 }; <<
1601 }; <<
1602 <<
1603 xbar_mixer_in <<
1604 reg = <<
1605 <<
1606 xbar_ <<
1607 <<
1608 }; <<
1609 }; <<
1610 <<
1611 xbar_mixer_in <<
1612 reg = <<
1613 <<
1614 xbar_ <<
1615 <<
1616 }; <<
1617 }; <<
1618 <<
1619 port@3c { <<
1620 reg = <<
1621 <<
1622 xbar_ <<
1623 <<
1624 }; <<
1625 }; <<
1626 <<
1627 port@3d { <<
1628 reg = <<
1629 <<
1630 xbar_ <<
1631 <<
1632 }; <<
1633 }; <<
1634 <<
1635 port@3e { <<
1636 reg = <<
1637 <<
1638 xbar_ <<
1639 <<
1640 }; <<
1641 }; <<
1642 <<
1643 port@3f { <<
1644 reg = <<
1645 <<
1646 xbar_ <<
1647 <<
1648 }; <<
1649 }; <<
1650 <<
1651 port@40 { <<
1652 reg = <<
1653 <<
1654 xbar_ <<
1655 <<
1656 }; <<
1657 }; <<
1658 <<
1659 xbar_ope1_in_ <<
1660 reg = <<
1661 <<
1662 xbar_ <<
1663 <<
1664 }; <<
1665 }; <<
1666 <<
1667 port@42 { <<
1668 reg = <<
1669 <<
1670 xbar_ <<
1671 <<
1672 }; <<
1673 }; <<
1674 <<
1675 xbar_ope2_in_ <<
1676 reg = <<
1677 <<
1678 xbar_ <<
1679 <<
1680 }; <<
1681 }; <<
1682 <<
1683 port@44 { <<
1684 reg = <<
1685 <<
1686 xbar_ <<
1687 <<
1688 }; <<
1689 }; <<
1690 }; 781 };
1691 }; 782 };
1692 <<
1693 dma-controller@702e2000 { <<
1694 status = "okay"; <<
1695 }; <<
1696 <<
1697 interrupt-controller@702f9000 <<
1698 status = "okay"; <<
1699 }; <<
1700 }; 783 };
1701 784
1702 spi@70410000 { 785 spi@70410000 {
1703 status = "okay"; 786 status = "okay";
1704 787
1705 flash@0 { 788 flash@0 {
1706 compatible = "jedec,s !! 789 compatible = "spi-nor";
1707 reg = <0>; 790 reg = <0>;
1708 spi-max-frequency = < 791 spi-max-frequency = <104000000>;
1709 spi-tx-bus-width = <2 792 spi-tx-bus-width = <2>;
1710 spi-rx-bus-width = <2 793 spi-rx-bus-width = <2>;
1711 }; 794 };
1712 }; 795 };
1713 796
1714 clk32k_in: clock-32k { !! 797 clk32k_in: clock@0 {
1715 compatible = "fixed-clock"; 798 compatible = "fixed-clock";
1716 clock-frequency = <32768>; 799 clock-frequency = <32768>;
1717 #clock-cells = <0>; 800 #clock-cells = <0>;
1718 }; 801 };
1719 802
1720 cpus { 803 cpus {
1721 cpu@0 { 804 cpu@0 {
1722 enable-method = "psci 805 enable-method = "psci";
1723 }; 806 };
1724 807
1725 cpu@1 { 808 cpu@1 {
1726 enable-method = "psci 809 enable-method = "psci";
1727 }; 810 };
1728 811
1729 cpu@2 { 812 cpu@2 {
1730 enable-method = "psci 813 enable-method = "psci";
1731 }; 814 };
1732 815
1733 cpu@3 { 816 cpu@3 {
1734 enable-method = "psci 817 enable-method = "psci";
1735 }; 818 };
1736 819
1737 idle-states { 820 idle-states {
1738 cpu-sleep { 821 cpu-sleep {
1739 status = "oka 822 status = "okay";
1740 }; 823 };
1741 }; 824 };
1742 }; 825 };
1743 826
1744 gpio-keys { !! 827 fan: fan {
1745 compatible = "gpio-keys"; !! 828 compatible = "pwm-fan";
>> 829 pwms = <&pwm 3 45334>;
1746 830
1747 key-force-recovery { !! 831 cooling-levels = <0 64 128 255>;
1748 label = "Force Recove !! 832 #cooling-cells = <2>;
1749 gpios = <&gpio TEGRA_ !! 833 };
1750 linux,input-type = <E !! 834
1751 linux,code = <BTN_1>; !! 835 thermal-zones {
1752 debounce-interval = < !! 836 cpu {
>> 837 trips {
>> 838 cpu_trip_critical: critical {
>> 839 temperature = <96500>;
>> 840 hysteresis = <0>;
>> 841 type = "critical";
>> 842 };
>> 843
>> 844 cpu_trip_hot: hot {
>> 845 temperature = <70000>;
>> 846 hysteresis = <2000>;
>> 847 type = "hot";
>> 848 };
>> 849
>> 850 cpu_trip_active: active {
>> 851 temperature = <50000>;
>> 852 hysteresis = <2000>;
>> 853 type = "active";
>> 854 };
>> 855
>> 856 cpu_trip_passive: passive {
>> 857 temperature = <30000>;
>> 858 hysteresis = <2000>;
>> 859 type = "passive";
>> 860 };
>> 861 };
>> 862
>> 863 cooling-maps {
>> 864 cpu-critical {
>> 865 cooling-device = <&fan 3 3>;
>> 866 trip = <&cpu_trip_critical>;
>> 867 };
>> 868
>> 869 cpu-hot {
>> 870 cooling-device = <&fan 2 2>;
>> 871 trip = <&cpu_trip_hot>;
>> 872 };
>> 873
>> 874 cpu-active {
>> 875 cooling-device = <&fan 1 1>;
>> 876 trip = <&cpu_trip_active>;
>> 877 };
>> 878
>> 879 cpu-passive {
>> 880 cooling-device = <&fan 0 0>;
>> 881 trip = <&cpu_trip_passive>;
>> 882 };
>> 883 };
1753 }; 884 };
>> 885 };
1754 886
1755 key-power { !! 887 gpio-keys {
>> 888 compatible = "gpio-keys";
>> 889
>> 890 power {
1756 label = "Power"; 891 label = "Power";
1757 gpios = <&gpio TEGRA_ 892 gpios = <&gpio TEGRA_GPIO(X, 5) GPIO_ACTIVE_LOW>;
1758 linux,input-type = <E 893 linux,input-type = <EV_KEY>;
1759 linux,code = <KEY_POW 894 linux,code = <KEY_POWER>;
1760 debounce-interval = < 895 debounce-interval = <30>;
1761 wakeup-event-action = 896 wakeup-event-action = <EV_ACT_ASSERTED>;
1762 wakeup-source; 897 wakeup-source;
1763 }; 898 };
>> 899
>> 900 force-recovery {
>> 901 label = "Force Recovery";
>> 902 gpios = <&gpio TEGRA_GPIO(X, 6) GPIO_ACTIVE_LOW>;
>> 903 linux,input-type = <EV_KEY>;
>> 904 linux,code = <BTN_1>;
>> 905 debounce-interval = <30>;
>> 906 };
1764 }; 907 };
1765 908
1766 psci { 909 psci {
1767 compatible = "arm,psci-1.0"; 910 compatible = "arm,psci-1.0";
1768 method = "smc"; 911 method = "smc";
1769 }; 912 };
1770 913
1771 fan: pwm-fan { !! 914 vdd_5v0_sys: regulator@0 {
1772 compatible = "pwm-fan"; <<
1773 pwms = <&pwm 3 45334>; <<
1774 <<
1775 cooling-levels = <0 64 128 25 <<
1776 #cooling-cells = <2>; <<
1777 }; <<
1778 <<
1779 vdd_5v0_sys: regulator-vdd-5v0-sys { <<
1780 compatible = "regulator-fixed 915 compatible = "regulator-fixed";
1781 916
1782 regulator-name = "VDD_5V0_SYS 917 regulator-name = "VDD_5V0_SYS";
1783 regulator-min-microvolt = <50 918 regulator-min-microvolt = <5000000>;
1784 regulator-max-microvolt = <50 919 regulator-max-microvolt = <5000000>;
1785 regulator-always-on; 920 regulator-always-on;
1786 regulator-boot-on; 921 regulator-boot-on;
1787 }; 922 };
1788 923
1789 vdd_3v3_sys: regulator-vdd-3v3-sys { !! 924 vdd_3v3_sys: regulator@1 {
1790 compatible = "regulator-fixed 925 compatible = "regulator-fixed";
1791 926
1792 regulator-name = "VDD_3V3_SYS 927 regulator-name = "VDD_3V3_SYS";
1793 regulator-min-microvolt = <33 928 regulator-min-microvolt = <3300000>;
1794 regulator-max-microvolt = <33 929 regulator-max-microvolt = <3300000>;
1795 regulator-enable-ramp-delay = 930 regulator-enable-ramp-delay = <240>;
>> 931 regulator-disable-ramp-delay = <11340>;
1796 regulator-always-on; 932 regulator-always-on;
1797 regulator-boot-on; 933 regulator-boot-on;
1798 934
1799 gpio = <&pmic 3 GPIO_ACTIVE_H 935 gpio = <&pmic 3 GPIO_ACTIVE_HIGH>;
1800 enable-active-high; 936 enable-active-high;
1801 937
1802 vin-supply = <&vdd_5v0_sys>; 938 vin-supply = <&vdd_5v0_sys>;
1803 }; 939 };
1804 940
1805 vdd_3v3_sd: regulator-vdd-3v3-sd { !! 941 vdd_3v3_sd: regulator@2 {
1806 compatible = "regulator-fixed 942 compatible = "regulator-fixed";
1807 943
1808 regulator-name = "VDD_3V3_SD" 944 regulator-name = "VDD_3V3_SD";
1809 regulator-min-microvolt = <33 945 regulator-min-microvolt = <3300000>;
1810 regulator-max-microvolt = <33 946 regulator-max-microvolt = <3300000>;
1811 947
1812 gpio = <&gpio TEGRA_GPIO(Z, 3 948 gpio = <&gpio TEGRA_GPIO(Z, 3) GPIO_ACTIVE_HIGH>;
1813 enable-active-high; 949 enable-active-high;
1814 950
1815 vin-supply = <&vdd_3v3_sys>; 951 vin-supply = <&vdd_3v3_sys>;
1816 }; 952 };
1817 953
1818 vdd_hdmi: regulator-vdd-hdmi-5v0 { !! 954 vdd_hdmi: regulator@3 {
1819 compatible = "regulator-fixed 955 compatible = "regulator-fixed";
1820 956
1821 regulator-name = "VDD_HDMI_5V 957 regulator-name = "VDD_HDMI_5V0";
1822 regulator-min-microvolt = <50 958 regulator-min-microvolt = <5000000>;
1823 regulator-max-microvolt = <50 959 regulator-max-microvolt = <5000000>;
1824 960
1825 vin-supply = <&vdd_5v0_sys>; 961 vin-supply = <&vdd_5v0_sys>;
1826 }; 962 };
1827 963
1828 vdd_hub_3v3: regulator-vdd-hub-3v3 { !! 964 vdd_hub_3v3: regulator@4 {
1829 compatible = "regulator-fixed 965 compatible = "regulator-fixed";
1830 966
1831 regulator-name = "VDD_HUB_3V3 967 regulator-name = "VDD_HUB_3V3";
1832 regulator-min-microvolt = <33 968 regulator-min-microvolt = <3300000>;
1833 regulator-max-microvolt = <33 969 regulator-max-microvolt = <3300000>;
1834 970
1835 gpio = <&gpio TEGRA_GPIO(A, 6 971 gpio = <&gpio TEGRA_GPIO(A, 6) GPIO_ACTIVE_HIGH>;
1836 enable-active-high; 972 enable-active-high;
1837 973
1838 vin-supply = <&vdd_5v0_sys>; 974 vin-supply = <&vdd_5v0_sys>;
1839 }; 975 };
1840 976
1841 vdd_cpu: regulator-vdd-cpu { !! 977 vdd_cpu: regulator@5 {
1842 compatible = "regulator-fixed 978 compatible = "regulator-fixed";
1843 979
1844 regulator-name = "VDD_CPU"; 980 regulator-name = "VDD_CPU";
1845 regulator-min-microvolt = <50 981 regulator-min-microvolt = <5000000>;
1846 regulator-max-microvolt = <50 982 regulator-max-microvolt = <5000000>;
1847 regulator-always-on; 983 regulator-always-on;
1848 regulator-boot-on; 984 regulator-boot-on;
1849 985
1850 gpio = <&pmic 5 GPIO_ACTIVE_H 986 gpio = <&pmic 5 GPIO_ACTIVE_HIGH>;
1851 enable-active-high; 987 enable-active-high;
1852 988
1853 vin-supply = <&vdd_5v0_sys>; 989 vin-supply = <&vdd_5v0_sys>;
1854 }; 990 };
1855 991
1856 vdd_gpu: regulator-vdd-gpu { !! 992 vdd_gpu: regulator@6 {
1857 compatible = "pwm-regulator"; 993 compatible = "pwm-regulator";
1858 pwms = <&pwm 1 8000>; 994 pwms = <&pwm 1 8000>;
1859 995
1860 regulator-name = "VDD_GPU"; 996 regulator-name = "VDD_GPU";
1861 regulator-min-microvolt = <71 997 regulator-min-microvolt = <710000>;
1862 regulator-max-microvolt = <13 998 regulator-max-microvolt = <1320000>;
1863 regulator-ramp-delay = <80>; 999 regulator-ramp-delay = <80>;
1864 regulator-enable-ramp-delay = 1000 regulator-enable-ramp-delay = <2000>;
1865 regulator-settling-time-us = 1001 regulator-settling-time-us = <160>;
1866 1002
1867 enable-gpios = <&pmic 6 GPIO_ 1003 enable-gpios = <&pmic 6 GPIO_ACTIVE_HIGH>;
1868 vin-supply = <&vdd_5v0_sys>; 1004 vin-supply = <&vdd_5v0_sys>;
1869 }; 1005 };
1870 1006
1871 avdd_io_edp_1v05: regulator-avdd-io-e !! 1007 avdd_io_edp_1v05: regulator@7 {
1872 compatible = "regulator-fixed 1008 compatible = "regulator-fixed";
1873 1009
1874 regulator-name = "AVDD_IO_EDP 1010 regulator-name = "AVDD_IO_EDP_1V05";
1875 regulator-min-microvolt = <10 1011 regulator-min-microvolt = <1050000>;
1876 regulator-max-microvolt = <10 1012 regulator-max-microvolt = <1050000>;
1877 1013
1878 gpio = <&pmic 7 GPIO_ACTIVE_H 1014 gpio = <&pmic 7 GPIO_ACTIVE_HIGH>;
1879 enable-active-high; 1015 enable-active-high;
1880 1016
1881 vin-supply = <&avdd_1v05_pll> 1017 vin-supply = <&avdd_1v05_pll>;
1882 }; 1018 };
1883 1019
1884 vdd_5v0_usb: regulator-vdd-5v-usb { !! 1020 vdd_5v0_usb: regulator@8 {
1885 compatible = "regulator-fixed 1021 compatible = "regulator-fixed";
1886 1022
1887 regulator-name = "VDD_5V_USB" 1023 regulator-name = "VDD_5V_USB";
1888 regulator-min-microvolt = <50 1024 regulator-min-microvolt = <50000000>;
1889 regulator-max-microvolt = <50 1025 regulator-max-microvolt = <50000000>;
1890 1026
1891 vin-supply = <&vdd_5v0_sys>; 1027 vin-supply = <&vdd_5v0_sys>;
1892 }; 1028 };
1893 1029
1894 sound { 1030 sound {
1895 compatible = "nvidia,tegra210 1031 compatible = "nvidia,tegra210-audio-graph-card";
1896 status = "okay"; 1032 status = "okay";
1897 1033
1898 dais = /* FE */ 1034 dais = /* FE */
1899 <&admaif1_port>, <&adm 1035 <&admaif1_port>, <&admaif2_port>, <&admaif3_port>,
1900 <&admaif4_port>, <&adm 1036 <&admaif4_port>, <&admaif5_port>, <&admaif6_port>,
1901 <&admaif7_port>, <&adm 1037 <&admaif7_port>, <&admaif8_port>, <&admaif9_port>,
1902 <&admaif10_port>, 1038 <&admaif10_port>,
1903 /* Router */ 1039 /* Router */
1904 <&xbar_i2s3_port>, <&x 1040 <&xbar_i2s3_port>, <&xbar_i2s4_port>,
1905 <&xbar_dmic1_port>, <& 1041 <&xbar_dmic1_port>, <&xbar_dmic2_port>,
1906 <&xbar_sfc1_in_port>, <<
1907 <&xbar_sfc3_in_port>, <<
1908 <&xbar_mvc1_in_port>, <<
1909 <&xbar_amx1_in1_port>, <<
1910 <&xbar_amx1_in3_port>, <<
1911 <&xbar_amx2_in1_port>, <<
1912 <&xbar_amx2_in3_port>, <<
1913 <&xbar_adx1_in_port>, <<
1914 <&xbar_mixer_in1_port> <<
1915 <&xbar_mixer_in3_port> <<
1916 <&xbar_mixer_in5_port> <<
1917 <&xbar_mixer_in7_port> <<
1918 <&xbar_mixer_in9_port> <<
1919 <&xbar_ope1_in_port>, <<
1920 /* HW accelerators */ <<
1921 <&sfc1_out_port>, <&sf <<
1922 <&sfc3_out_port>, <&sf <<
1923 <&mvc1_out_port>, <&mv <<
1924 <&amx1_out_port>, <&am <<
1925 <&adx1_out1_port>, <&a <<
1926 <&adx1_out3_port>, <&a <<
1927 <&adx2_out1_port>, <&a <<
1928 <&adx2_out3_port>, <&a <<
1929 <&mixer_out1_port>, <& <<
1930 <&mixer_out3_port>, <& <<
1931 <&mixer_out5_port>, <<
1932 <&ope1_out_port>, <&op <<
1933 /* I/O DAP Ports */ 1042 /* I/O DAP Ports */
1934 <&i2s3_port>, <&i2s4_p 1043 <&i2s3_port>, <&i2s4_port>,
1935 <&dmic1_port>, <&dmic2 1044 <&dmic1_port>, <&dmic2_port>;
1936 1045
1937 label = "NVIDIA Jetson Nano A 1046 label = "NVIDIA Jetson Nano APE";
1938 }; <<
1939 <<
1940 thermal-zones { <<
1941 cpu-thermal { <<
1942 trips { <<
1943 cpu_trip_crit <<
1944 tempe <<
1945 hyste <<
1946 type <<
1947 }; <<
1948 <<
1949 cpu_trip_hot: <<
1950 tempe <<
1951 hyste <<
1952 type <<
1953 }; <<
1954 <<
1955 cpu_trip_acti <<
1956 tempe <<
1957 hyste <<
1958 type <<
1959 }; <<
1960 <<
1961 cpu_trip_pass <<
1962 tempe <<
1963 hyste <<
1964 type <<
1965 }; <<
1966 }; <<
1967 <<
1968 cooling-maps { <<
1969 cpu-critical <<
1970 cooli <<
1971 trip <<
1972 }; <<
1973 <<
1974 cpu-hot { <<
1975 cooli <<
1976 trip <<
1977 }; <<
1978 <<
1979 cpu-active { <<
1980 cooli <<
1981 trip <<
1982 }; <<
1983 <<
1984 cpu-passive { <<
1985 cooli <<
1986 trip <<
1987 }; <<
1988 }; <<
1989 }; <<
1990 }; 1047 };
1991 }; 1048 };
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