1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/; 2 /dts-v1/;
3 3
4 #include <dt-bindings/input/gpio-keys.h> 4 #include <dt-bindings/input/gpio-keys.h>
5 #include <dt-bindings/input/linux-event-codes. 5 #include <dt-bindings/input/linux-event-codes.h>
6 #include <dt-bindings/mfd/max77620.h> 6 #include <dt-bindings/mfd/max77620.h>
7 7
8 #include "tegra210.dtsi" 8 #include "tegra210.dtsi"
9 9
10 / { 10 / {
11 model = "NVIDIA Jetson Nano Developer 11 model = "NVIDIA Jetson Nano Developer Kit";
12 compatible = "nvidia,p3450-0000", "nvi 12 compatible = "nvidia,p3450-0000", "nvidia,tegra210";
13 13
14 aliases { 14 aliases {
15 ethernet = "/pcie@1003000/pci@ 15 ethernet = "/pcie@1003000/pci@2,0/ethernet@0,0";
16 rtc0 = "/i2c@7000d000/pmic@3c" 16 rtc0 = "/i2c@7000d000/pmic@3c";
17 rtc1 = "/rtc@7000e000"; 17 rtc1 = "/rtc@7000e000";
18 serial0 = &uarta; 18 serial0 = &uarta;
19 }; 19 };
20 20
21 chosen { 21 chosen {
22 stdout-path = "serial0:115200n 22 stdout-path = "serial0:115200n8";
23 }; 23 };
24 24
25 memory@80000000 { 25 memory@80000000 {
26 device_type = "memory"; 26 device_type = "memory";
27 reg = <0x0 0x80000000 0x1 0x0> 27 reg = <0x0 0x80000000 0x1 0x0>;
28 }; 28 };
29 29
30 pcie@1003000 { 30 pcie@1003000 {
31 status = "okay"; 31 status = "okay";
32 32
>> 33 avdd-pll-uerefe-supply = <&vdd_pex_1v05>;
33 hvddio-pex-supply = <&vdd_1v8> 34 hvddio-pex-supply = <&vdd_1v8>;
34 dvddio-pex-supply = <&vdd_pex_ 35 dvddio-pex-supply = <&vdd_pex_1v05>;
>> 36 dvdd-pex-pll-supply = <&vdd_pex_1v05>;
>> 37 hvdd-pex-pll-e-supply = <&vdd_1v8>;
35 vddio-pex-ctl-supply = <&vdd_1 38 vddio-pex-ctl-supply = <&vdd_1v8>;
36 39
37 pci@1,0 { 40 pci@1,0 {
38 phys = <&{/padctl@7009f 41 phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>,
39 <&{/padctl@7009f 42 <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>,
40 <&{/padctl@7009f 43 <&{/padctl@7009f000/pads/pcie/lanes/pcie-3}>,
41 <&{/padctl@7009f 44 <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>;
42 phy-names = "pcie-0", 45 phy-names = "pcie-0", "pcie-1", "pcie-2", "pcie-3";
43 nvidia,num-lanes = <4> 46 nvidia,num-lanes = <4>;
44 status = "okay"; 47 status = "okay";
45 }; 48 };
46 49
47 pci@2,0 { 50 pci@2,0 {
48 phys = <&{/padctl@7009f 51 phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>;
49 phy-names = "pcie-0"; 52 phy-names = "pcie-0";
50 status = "okay"; 53 status = "okay";
51 54
52 ethernet@0,0 { 55 ethernet@0,0 {
53 reg = <0x00000 56 reg = <0x000000 0 0 0 0>;
54 local-mac-addr 57 local-mac-address = [ 00 00 00 00 00 00 ];
55 }; 58 };
56 }; 59 };
57 }; 60 };
58 61
59 host1x@50000000 { 62 host1x@50000000 {
60 dpaux@54040000 { 63 dpaux@54040000 {
61 status = "okay"; 64 status = "okay";
62 }; 65 };
63 66
64 vi@54080000 { 67 vi@54080000 {
65 status = "okay"; 68 status = "okay";
66 69
67 avdd-dsi-csi-supply = 70 avdd-dsi-csi-supply = <&vdd_sys_1v2>;
68 71
69 csi@838 { 72 csi@838 {
70 status = "okay 73 status = "okay";
71 }; 74 };
72 }; 75 };
73 76
74 sor@54540000 { 77 sor@54540000 {
75 status = "okay"; 78 status = "okay";
76 79
77 avdd-io-hdmi-dp-supply 80 avdd-io-hdmi-dp-supply = <&avdd_io_edp_1v05>;
78 vdd-hdmi-dp-pll-supply 81 vdd-hdmi-dp-pll-supply = <&vdd_1v8>;
79 82
80 nvidia,xbar-cfg = <2 1 83 nvidia,xbar-cfg = <2 1 0 3 4>;
81 nvidia,dpaux = <&dpaux 84 nvidia,dpaux = <&dpaux>;
82 }; 85 };
83 86
84 sor@54580000 { 87 sor@54580000 {
85 status = "okay"; 88 status = "okay";
86 89
87 avdd-io-hdmi-dp-supply 90 avdd-io-hdmi-dp-supply = <&avdd_1v05>;
88 vdd-hdmi-dp-pll-supply 91 vdd-hdmi-dp-pll-supply = <&vdd_1v8>;
89 hdmi-supply = <&vdd_hd 92 hdmi-supply = <&vdd_hdmi>;
90 93
91 nvidia,ddc-i2c-bus = < 94 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
92 nvidia,hpd-gpio = <&gp 95 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(CC, 1)
93 GPI 96 GPIO_ACTIVE_LOW>;
94 nvidia,xbar-cfg = <0 1 97 nvidia,xbar-cfg = <0 1 2 3 4>;
95 }; 98 };
96 99
97 dpaux@545c0000 { 100 dpaux@545c0000 {
98 status = "okay"; 101 status = "okay";
99 }; 102 };
100 103
101 i2c@546c0000 { 104 i2c@546c0000 {
102 status = "okay"; 105 status = "okay";
103 }; 106 };
104 }; 107 };
105 108
106 gpu@57000000 { 109 gpu@57000000 {
107 vdd-supply = <&vdd_gpu>; 110 vdd-supply = <&vdd_gpu>;
108 status = "okay"; 111 status = "okay";
109 }; 112 };
110 113
111 pinmux@700008d4 { 114 pinmux@700008d4 {
112 dvfs_pwm_active_state: pinmux- !! 115 dvfs_pwm_active_state: dvfs_pwm_active {
113 dvfs_pwm_pbb1 { 116 dvfs_pwm_pbb1 {
114 nvidia,pins = 117 nvidia,pins = "dvfs_pwm_pbb1";
115 nvidia,tristat 118 nvidia,tristate = <TEGRA_PIN_DISABLE>;
116 }; 119 };
117 }; 120 };
118 121
119 dvfs_pwm_inactive_state: pinmu !! 122 dvfs_pwm_inactive_state: dvfs_pwm_inactive {
120 dvfs_pwm_pbb1 { 123 dvfs_pwm_pbb1 {
121 nvidia,pins = 124 nvidia,pins = "dvfs_pwm_pbb1";
122 nvidia,tristat 125 nvidia,tristate = <TEGRA_PIN_ENABLE>;
123 }; 126 };
124 }; 127 };
125 }; 128 };
126 129
127 /* debug port */ 130 /* debug port */
128 serial@70006000 { 131 serial@70006000 {
129 /delete-property/ dmas; <<
130 /delete-property/ dma-names; <<
131 status = "okay"; 132 status = "okay";
132 }; 133 };
133 134
134 pwm@7000a000 { 135 pwm@7000a000 {
135 status = "okay"; 136 status = "okay";
136 }; 137 };
137 138
138 i2c@7000c500 { 139 i2c@7000c500 {
139 status = "okay"; 140 status = "okay";
140 clock-frequency = <100000>; 141 clock-frequency = <100000>;
141 142
142 eeprom@50 { 143 eeprom@50 {
143 compatible = "atmel,24 144 compatible = "atmel,24c02";
144 reg = <0x50>; 145 reg = <0x50>;
145 146
146 label = "module"; 147 label = "module";
147 vcc-supply = <&vdd_1v8 148 vcc-supply = <&vdd_1v8>;
148 address-width = <8>; 149 address-width = <8>;
149 pagesize = <8>; 150 pagesize = <8>;
150 size = <256>; 151 size = <256>;
151 read-only; 152 read-only;
152 }; 153 };
153 154
154 eeprom@57 { 155 eeprom@57 {
155 compatible = "atmel,24 156 compatible = "atmel,24c02";
156 reg = <0x57>; 157 reg = <0x57>;
157 158
158 label = "system"; 159 label = "system";
159 vcc-supply = <&vdd_1v8 160 vcc-supply = <&vdd_1v8>;
160 address-width = <8>; 161 address-width = <8>;
161 pagesize = <8>; 162 pagesize = <8>;
162 size = <256>; 163 size = <256>;
163 read-only; 164 read-only;
164 }; 165 };
165 }; 166 };
166 167
167 hdmi_ddc: i2c@7000c700 { 168 hdmi_ddc: i2c@7000c700 {
168 status = "okay"; 169 status = "okay";
169 clock-frequency = <100000>; 170 clock-frequency = <100000>;
170 }; 171 };
171 172
172 i2c@7000d000 { 173 i2c@7000d000 {
173 status = "okay"; 174 status = "okay";
174 clock-frequency = <400000>; 175 clock-frequency = <400000>;
175 176
176 pmic: pmic@3c { 177 pmic: pmic@3c {
177 compatible = "maxim,ma 178 compatible = "maxim,max77620";
178 reg = <0x3c>; 179 reg = <0x3c>;
179 interrupt-parent = <&t 180 interrupt-parent = <&tegra_pmc>;
180 interrupts = <51 IRQ_T 181 interrupts = <51 IRQ_TYPE_LEVEL_LOW>;
181 182
182 #interrupt-cells = <2> 183 #interrupt-cells = <2>;
183 interrupt-controller; 184 interrupt-controller;
184 185
185 #gpio-cells = <2>; 186 #gpio-cells = <2>;
186 gpio-controller; 187 gpio-controller;
187 188
188 pinctrl-names = "defau 189 pinctrl-names = "default";
189 pinctrl-0 = <&max77620 190 pinctrl-0 = <&max77620_default>;
190 191
191 fps { <<
192 fps0 { <<
193 maxim, <<
194 maxim, <<
195 }; <<
196 <<
197 fps1 { <<
198 maxim, <<
199 maxim, <<
200 }; <<
201 <<
202 fps2 { <<
203 maxim, <<
204 }; <<
205 }; <<
206 <<
207 max77620_default: pinm 192 max77620_default: pinmux {
208 gpio0 { 193 gpio0 {
209 pins = 194 pins = "gpio0";
210 functi 195 function = "gpio";
211 }; 196 };
212 197
213 gpio1 { 198 gpio1 {
214 pins = 199 pins = "gpio1";
215 functi 200 function = "fps-out";
216 drive- 201 drive-push-pull = <1>;
217 maxim, 202 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
218 maxim, 203 maxim,active-fps-power-up-slot = <0>;
219 maxim, 204 maxim,active-fps-power-down-slot = <7>;
220 }; 205 };
221 206
222 gpio2 { 207 gpio2 {
223 pins = 208 pins = "gpio2";
224 functi 209 function = "fps-out";
225 drive- 210 drive-open-drain = <1>;
226 maxim, 211 maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
227 maxim, 212 maxim,active-fps-power-up-slot = <0>;
228 maxim, 213 maxim,active-fps-power-down-slot = <7>;
229 }; 214 };
230 215
231 gpio3 { 216 gpio3 {
232 pins = 217 pins = "gpio3";
233 functi 218 function = "fps-out";
234 drive- 219 drive-open-drain = <1>;
235 maxim, 220 maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
236 maxim, 221 maxim,active-fps-power-up-slot = <4>;
237 maxim, 222 maxim,active-fps-power-down-slot = <3>;
238 }; 223 };
239 224
240 gpio4 { 225 gpio4 {
241 pins = 226 pins = "gpio4";
242 functi 227 function = "32k-out1";
243 }; 228 };
244 229
245 gpio5_6_7 { 230 gpio5_6_7 {
246 pins = 231 pins = "gpio5", "gpio6", "gpio7";
247 functi 232 function = "gpio";
248 drive- 233 drive-push-pull = <1>;
249 }; 234 };
250 }; 235 };
251 236
>> 237 fps {
>> 238 fps0 {
>> 239 maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>;
>> 240 maxim,suspend-fps-time-period-us = <5120>;
>> 241 };
>> 242
>> 243 fps1 {
>> 244 maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>;
>> 245 maxim,suspend-fps-time-period-us = <5120>;
>> 246 };
>> 247
>> 248 fps2 {
>> 249 maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>;
>> 250 };
>> 251 };
>> 252
252 regulators { 253 regulators {
253 in-ldo0-1-supp 254 in-ldo0-1-supply = <&vdd_pre>;
254 in-ldo2-supply 255 in-ldo2-supply = <&vdd_3v3_sys>;
255 in-ldo3-5-supp 256 in-ldo3-5-supply = <&vdd_1v8>;
256 in-ldo4-6-supp 257 in-ldo4-6-supply = <&vdd_5v0_sys>;
257 in-ldo7-8-supp 258 in-ldo7-8-supply = <&vdd_pre>;
258 in-sd0-supply 259 in-sd0-supply = <&vdd_5v0_sys>;
259 in-sd1-supply 260 in-sd1-supply = <&vdd_5v0_sys>;
260 in-sd2-supply 261 in-sd2-supply = <&vdd_5v0_sys>;
261 in-sd3-supply 262 in-sd3-supply = <&vdd_5v0_sys>;
262 263
263 vdd_soc: sd0 { 264 vdd_soc: sd0 {
264 regula 265 regulator-name = "VDD_SOC";
265 regula 266 regulator-min-microvolt = <1000000>;
266 regula 267 regulator-max-microvolt = <1170000>;
267 regula 268 regulator-enable-ramp-delay = <146>;
>> 269 regulator-disable-ramp-delay = <4080>;
268 regula 270 regulator-ramp-delay = <27500>;
269 regula 271 regulator-ramp-delay-scale = <300>;
270 regula 272 regulator-always-on;
271 regula 273 regulator-boot-on;
272 274
273 maxim, 275 maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
274 maxim, 276 maxim,active-fps-power-up-slot = <1>;
275 maxim, 277 maxim,active-fps-power-down-slot = <6>;
276 }; 278 };
277 279
278 vdd_ddr: sd1 { 280 vdd_ddr: sd1 {
279 regula 281 regulator-name = "VDD_DDR_1V1_PMIC";
280 regula 282 regulator-min-microvolt = <1150000>;
281 regula 283 regulator-max-microvolt = <1150000>;
282 regula 284 regulator-enable-ramp-delay = <176>;
>> 285 regulator-disable-ramp-delay = <145800>;
283 regula 286 regulator-ramp-delay = <27500>;
284 regula 287 regulator-ramp-delay-scale = <300>;
285 regula 288 regulator-always-on;
286 regula 289 regulator-boot-on;
287 290
288 maxim, 291 maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
289 maxim, 292 maxim,active-fps-power-up-slot = <5>;
290 maxim, 293 maxim,active-fps-power-down-slot = <2>;
291 }; 294 };
292 295
293 vdd_pre: sd2 { 296 vdd_pre: sd2 {
294 regula 297 regulator-name = "VDD_PRE_REG_1V35";
295 regula 298 regulator-min-microvolt = <1350000>;
296 regula 299 regulator-max-microvolt = <1350000>;
297 regula 300 regulator-enable-ramp-delay = <176>;
>> 301 regulator-disable-ramp-delay = <32000>;
298 regula 302 regulator-ramp-delay = <27500>;
299 regula 303 regulator-ramp-delay-scale = <350>;
300 regula 304 regulator-always-on;
301 regula 305 regulator-boot-on;
302 306
303 maxim, 307 maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
304 maxim, 308 maxim,active-fps-power-up-slot = <2>;
305 maxim, 309 maxim,active-fps-power-down-slot = <5>;
306 }; 310 };
307 311
308 vdd_1v8: sd3 { 312 vdd_1v8: sd3 {
309 regula 313 regulator-name = "VDD_1V8";
310 regula 314 regulator-min-microvolt = <1800000>;
311 regula 315 regulator-max-microvolt = <1800000>;
312 regula 316 regulator-enable-ramp-delay = <242>;
>> 317 regulator-disable-ramp-delay = <118000>;
313 regula 318 regulator-ramp-delay = <27500>;
314 regula 319 regulator-ramp-delay-scale = <360>;
315 regula 320 regulator-always-on;
316 regula 321 regulator-boot-on;
317 322
318 maxim, 323 maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
319 maxim, 324 maxim,active-fps-power-up-slot = <3>;
320 maxim, 325 maxim,active-fps-power-down-slot = <4>;
321 }; 326 };
322 327
323 vdd_sys_1v2: l 328 vdd_sys_1v2: ldo0 {
324 regula 329 regulator-name = "AVDD_SYS_1V2";
325 regula 330 regulator-min-microvolt = <1200000>;
326 regula 331 regulator-max-microvolt = <1200000>;
327 regula 332 regulator-enable-ramp-delay = <26>;
>> 333 regulator-disable-ramp-delay = <626>;
328 regula 334 regulator-ramp-delay = <100000>;
329 regula 335 regulator-ramp-delay-scale = <200>;
330 regula 336 regulator-always-on;
331 regula 337 regulator-boot-on;
332 338
333 maxim, 339 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
334 maxim, 340 maxim,active-fps-power-up-slot = <0>;
335 maxim, 341 maxim,active-fps-power-down-slot = <7>;
336 }; 342 };
337 343
338 vdd_pex_1v05: 344 vdd_pex_1v05: ldo1 {
339 regula 345 regulator-name = "VDD_PEX_1V05";
340 regula 346 regulator-min-microvolt = <1050000>;
341 regula 347 regulator-max-microvolt = <1050000>;
342 regula 348 regulator-enable-ramp-delay = <22>;
>> 349 regulator-disable-ramp-delay = <650>;
343 regula 350 regulator-ramp-delay = <100000>;
344 regula 351 regulator-ramp-delay-scale = <200>;
345 352
346 maxim, 353 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
347 maxim, 354 maxim,active-fps-power-up-slot = <0>;
348 maxim, 355 maxim,active-fps-power-down-slot = <7>;
349 }; 356 };
350 357
351 vddio_sdmmc: l 358 vddio_sdmmc: ldo2 {
352 regula 359 regulator-name = "VDDIO_SDMMC";
353 regula 360 regulator-min-microvolt = <1800000>;
354 regula 361 regulator-max-microvolt = <3300000>;
355 regula 362 regulator-enable-ramp-delay = <62>;
>> 363 regulator-disable-ramp-delay = <650>;
356 regula 364 regulator-ramp-delay = <100000>;
357 regula 365 regulator-ramp-delay-scale = <200>;
358 366
359 maxim, 367 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
360 maxim, 368 maxim,active-fps-power-up-slot = <0>;
361 maxim, 369 maxim,active-fps-power-down-slot = <7>;
362 }; 370 };
363 371
364 ldo3 { 372 ldo3 {
365 status 373 status = "disabled";
366 }; 374 };
367 375
368 vdd_rtc: ldo4 376 vdd_rtc: ldo4 {
369 regula 377 regulator-name = "VDD_RTC";
370 regula 378 regulator-min-microvolt = <850000>;
371 regula 379 regulator-max-microvolt = <1100000>;
372 regula 380 regulator-enable-ramp-delay = <22>;
>> 381 regulator-disable-ramp-delay = <610>;
373 regula 382 regulator-ramp-delay = <100000>;
374 regula 383 regulator-ramp-delay-scale = <200>;
375 regula 384 regulator-disable-active-discharge;
376 regula 385 regulator-always-on;
377 regula 386 regulator-boot-on;
378 387
379 maxim, 388 maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
380 maxim, 389 maxim,active-fps-power-up-slot = <1>;
381 maxim, 390 maxim,active-fps-power-down-slot = <6>;
382 }; 391 };
383 392
384 ldo5 { 393 ldo5 {
385 status 394 status = "disabled";
386 }; 395 };
387 396
388 ldo6 { 397 ldo6 {
389 status 398 status = "disabled";
390 }; 399 };
391 400
392 avdd_1v05_pll: 401 avdd_1v05_pll: ldo7 {
393 regula 402 regulator-name = "AVDD_1V05_PLL";
394 regula 403 regulator-min-microvolt = <1050000>;
395 regula 404 regulator-max-microvolt = <1050000>;
396 regula 405 regulator-enable-ramp-delay = <24>;
>> 406 regulator-disable-ramp-delay = <2768>;
397 regula 407 regulator-ramp-delay = <100000>;
398 regula 408 regulator-ramp-delay-scale = <200>;
399 409
400 maxim, 410 maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
401 maxim, 411 maxim,active-fps-power-up-slot = <3>;
402 maxim, 412 maxim,active-fps-power-down-slot = <4>;
403 }; 413 };
404 414
405 avdd_1v05: ldo 415 avdd_1v05: ldo8 {
406 regula 416 regulator-name = "AVDD_SATA_HDMI_DP_1V05";
407 regula 417 regulator-min-microvolt = <1050000>;
408 regula 418 regulator-max-microvolt = <1050000>;
409 regula 419 regulator-enable-ramp-delay = <22>;
>> 420 regulator-disable-ramp-delay = <1160>;
410 regula 421 regulator-ramp-delay = <100000>;
411 regula 422 regulator-ramp-delay-scale = <200>;
412 423
413 maxim, 424 maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
414 maxim, 425 maxim,active-fps-power-up-slot = <6>;
415 maxim, 426 maxim,active-fps-power-down-slot = <1>;
416 }; 427 };
417 }; 428 };
418 }; 429 };
419 }; 430 };
420 431
421 pmc@7000e400 { 432 pmc@7000e400 {
422 nvidia,invert-interrupt; 433 nvidia,invert-interrupt;
423 nvidia,suspend-mode = <0>; 434 nvidia,suspend-mode = <0>;
424 nvidia,cpu-pwr-good-time = <0> 435 nvidia,cpu-pwr-good-time = <0>;
425 nvidia,cpu-pwr-off-time = <0>; 436 nvidia,cpu-pwr-off-time = <0>;
426 nvidia,core-pwr-good-time = <4 437 nvidia,core-pwr-good-time = <4587 3876>;
427 nvidia,core-pwr-off-time = <39 438 nvidia,core-pwr-off-time = <39065>;
428 nvidia,core-power-req-active-h 439 nvidia,core-power-req-active-high;
429 nvidia,sys-clock-req-active-hi 440 nvidia,sys-clock-req-active-high;
430 }; 441 };
431 442
432 hda@70030000 { 443 hda@70030000 {
433 nvidia,model = "NVIDIA Jetson 444 nvidia,model = "NVIDIA Jetson Nano HDA";
434 445
435 status = "okay"; 446 status = "okay";
436 }; 447 };
437 448
438 usb@70090000 { 449 usb@70090000 {
439 phys = <&{/padctl@7009f000/pads 450 phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>,
440 <&{/padctl@7009f000/pads 451 <&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>,
441 <&{/padctl@7009f000/pads 452 <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>,
442 <&{/padctl@7009f000/pads 453 <&{/padctl@7009f000/pads/pcie/lanes/pcie-6}>;
443 phy-names = "usb2-0", "usb2-1" 454 phy-names = "usb2-0", "usb2-1", "usb2-2", "usb3-0";
444 455
445 avdd-usb-supply = <&vdd_3v3_sy 456 avdd-usb-supply = <&vdd_3v3_sys>;
446 dvddio-pex-supply = <&vdd_pex_ 457 dvddio-pex-supply = <&vdd_pex_1v05>;
447 hvddio-pex-supply = <&vdd_1v8> 458 hvddio-pex-supply = <&vdd_1v8>;
>> 459 /* these really belong to the XUSB pad controller */
>> 460 avdd-pll-utmip-supply = <&vdd_1v8>;
>> 461 avdd-pll-uerefe-supply = <&vdd_pex_1v05>;
>> 462 dvdd-usb-ss-pll-supply = <&vdd_pex_1v05>;
>> 463 hvdd-usb-ss-pll-e-supply = <&vdd_1v8>;
448 464
449 status = "okay"; 465 status = "okay";
450 }; 466 };
451 467
452 padctl@7009f000 { 468 padctl@7009f000 {
453 status = "okay"; 469 status = "okay";
454 470
455 avdd-pll-utmip-supply = <&vdd_ 471 avdd-pll-utmip-supply = <&vdd_1v8>;
456 avdd-pll-uerefe-supply = <&vdd 472 avdd-pll-uerefe-supply = <&vdd_pex_1v05>;
457 dvdd-pex-pll-supply = <&vdd_pe 473 dvdd-pex-pll-supply = <&vdd_pex_1v05>;
458 hvdd-pex-pll-e-supply = <&vdd_ 474 hvdd-pex-pll-e-supply = <&vdd_1v8>;
459 475
460 pads { 476 pads {
461 usb2 { 477 usb2 {
462 status = "okay 478 status = "okay";
463 479
464 lanes { 480 lanes {
465 micro_ 481 micro_b: usb2-0 {
466 482 nvidia,function = "xusb";
467 483 status = "okay";
468 }; 484 };
469 485
470 usb2-1 486 usb2-1 {
471 487 nvidia,function = "xusb";
472 488 status = "okay";
473 }; 489 };
474 490
475 usb2-2 491 usb2-2 {
476 492 nvidia,function = "xusb";
477 493 status = "okay";
478 }; 494 };
479 }; 495 };
480 }; 496 };
481 497
482 pcie { 498 pcie {
483 status = "okay 499 status = "okay";
484 500
485 lanes { 501 lanes {
486 pcie-0 502 pcie-0 {
487 503 nvidia,function = "pcie-x1";
488 504 status = "okay";
489 }; 505 };
490 506
491 pcie-1 507 pcie-1 {
492 508 nvidia,function = "pcie-x4";
493 509 status = "okay";
494 }; 510 };
495 511
496 pcie-2 512 pcie-2 {
497 513 nvidia,function = "pcie-x4";
498 514 status = "okay";
499 }; 515 };
500 516
501 pcie-3 517 pcie-3 {
502 518 nvidia,function = "pcie-x4";
503 519 status = "okay";
504 }; 520 };
505 521
506 pcie-4 522 pcie-4 {
507 523 nvidia,function = "pcie-x4";
508 524 status = "okay";
509 }; 525 };
510 526
511 pcie-5 527 pcie-5 {
512 528 nvidia,function = "usb3-ss";
513 529 status = "okay";
514 }; 530 };
515 531
516 pcie-6 532 pcie-6 {
517 533 nvidia,function = "usb3-ss";
518 534 status = "okay";
519 }; 535 };
520 }; 536 };
521 }; 537 };
522 }; 538 };
523 539
524 ports { 540 ports {
525 usb2-0 { 541 usb2-0 {
526 status = "okay 542 status = "okay";
527 mode = "periph 543 mode = "peripheral";
528 usb-role-switc 544 usb-role-switch;
529 545
530 vbus-supply = 546 vbus-supply = <&vdd_5v0_usb>;
531 547
532 connector { 548 connector {
533 compat 549 compatible = "gpio-usb-b-connector",
534 550 "usb-b-connector";
535 label 551 label = "micro-USB";
536 type = 552 type = "micro";
537 vbus-g 553 vbus-gpios = <&gpio TEGRA_GPIO(CC, 4)
538 554 GPIO_ACTIVE_LOW>;
539 }; 555 };
540 }; 556 };
541 557
542 usb2-1 { 558 usb2-1 {
543 status = "okay 559 status = "okay";
544 mode = "host"; 560 mode = "host";
545 }; 561 };
546 562
547 usb2-2 { 563 usb2-2 {
548 status = "okay 564 status = "okay";
549 mode = "host"; 565 mode = "host";
550 }; 566 };
551 567
552 usb3-0 { 568 usb3-0 {
553 status = "okay 569 status = "okay";
554 nvidia,usb2-co 570 nvidia,usb2-companion = <1>;
555 vbus-supply = 571 vbus-supply = <&vdd_hub_3v3>;
556 }; 572 };
557 }; 573 };
558 }; 574 };
559 575
560 mmc@700b0000 { 576 mmc@700b0000 {
561 status = "okay"; 577 status = "okay";
562 bus-width = <4>; 578 bus-width = <4>;
563 579
564 cd-gpios = <&gpio TEGRA_GPIO(Z 580 cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>;
565 disable-wp; 581 disable-wp;
566 582
567 vqmmc-supply = <&vddio_sdmmc>; 583 vqmmc-supply = <&vddio_sdmmc>;
568 vmmc-supply = <&vdd_3v3_sd>; 584 vmmc-supply = <&vdd_3v3_sd>;
569 }; 585 };
570 586
571 mmc@700b0400 { 587 mmc@700b0400 {
572 status = "okay"; 588 status = "okay";
573 bus-width = <4>; 589 bus-width = <4>;
574 590
575 vqmmc-supply = <&vdd_1v8>; 591 vqmmc-supply = <&vdd_1v8>;
576 vmmc-supply = <&vdd_3v3_sys>; 592 vmmc-supply = <&vdd_3v3_sys>;
577 593
578 non-removable; 594 non-removable;
579 cap-sdio-irq; 595 cap-sdio-irq;
580 keep-power-in-suspend; 596 keep-power-in-suspend;
581 wakeup-source; 597 wakeup-source;
582 }; 598 };
583 599
584 usb@700d0000 { 600 usb@700d0000 {
585 status = "okay"; 601 status = "okay";
586 phys = <µ_b>; 602 phys = <µ_b>;
587 phy-names = "usb2-0"; 603 phy-names = "usb2-0";
588 avddio-usb-supply = <&vdd_3v3_ 604 avddio-usb-supply = <&vdd_3v3_sys>;
589 hvdd-usb-supply = <&vdd_1v8>; 605 hvdd-usb-supply = <&vdd_1v8>;
590 }; 606 };
591 607
592 clock@70110000 { 608 clock@70110000 {
593 status = "okay"; 609 status = "okay";
594 610
595 nvidia,cf = <6>; 611 nvidia,cf = <6>;
596 nvidia,ci = <0>; 612 nvidia,ci = <0>;
597 nvidia,cg = <2>; 613 nvidia,cg = <2>;
598 nvidia,droop-ctrl = <0x00000f0 614 nvidia,droop-ctrl = <0x00000f00>;
599 nvidia,force-mode = <1>; 615 nvidia,force-mode = <1>;
600 nvidia,sample-rate = <25000>; 616 nvidia,sample-rate = <25000>;
601 617
602 nvidia,pwm-min-microvolts = <7 618 nvidia,pwm-min-microvolts = <708000>;
603 nvidia,pwm-period-nanoseconds 619 nvidia,pwm-period-nanoseconds = <2500>; /* 2.5us */
604 nvidia,pwm-to-pmic; 620 nvidia,pwm-to-pmic;
605 nvidia,pwm-tristate-microvolts 621 nvidia,pwm-tristate-microvolts = <1000000>;
606 nvidia,pwm-voltage-step-microv 622 nvidia,pwm-voltage-step-microvolts = <19200>;
607 623
608 pinctrl-names = "dvfs_pwm_enab 624 pinctrl-names = "dvfs_pwm_enable", "dvfs_pwm_disable";
609 pinctrl-0 = <&dvfs_pwm_active_ 625 pinctrl-0 = <&dvfs_pwm_active_state>;
610 pinctrl-1 = <&dvfs_pwm_inactiv 626 pinctrl-1 = <&dvfs_pwm_inactive_state>;
611 }; 627 };
612 628
613 aconnect@702c0000 { 629 aconnect@702c0000 {
614 status = "okay"; 630 status = "okay";
615 631
>> 632 dma-controller@702e2000 {
>> 633 status = "okay";
>> 634 };
>> 635
>> 636 interrupt-controller@702f9000 {
>> 637 status = "okay";
>> 638 };
>> 639
616 ahub@702d0800 { 640 ahub@702d0800 {
617 status = "okay"; 641 status = "okay";
618 642
619 admaif@702d0000 { 643 admaif@702d0000 {
620 status = "okay 644 status = "okay";
621 }; 645 };
622 646
623 i2s@702d1200 { 647 i2s@702d1200 {
624 status = "okay 648 status = "okay";
625 649
626 ports { 650 ports {
627 #addre 651 #address-cells = <1>;
628 #size- 652 #size-cells = <0>;
629 653
630 port@0 654 port@0 {
631 655 reg = <0>;
632 656
633 657 i2s3_cif_ep: endpoint {
634 658 remote-endpoint = <&xbar_i2s3_ep>;
635 659 };
636 }; 660 };
637 661
638 i2s3_p 662 i2s3_port: port@1 {
639 663 reg = <1>;
640 664
641 665 i2s3_dap_ep: endpoint {
642 666 dai-format = "i2s";
643 667 /* Placeholder for external Codec */
644 668 };
645 }; 669 };
646 }; 670 };
647 }; 671 };
648 672
649 i2s@702d1300 { 673 i2s@702d1300 {
650 status = "okay 674 status = "okay";
651 675
652 ports { 676 ports {
653 #addre 677 #address-cells = <1>;
654 #size- 678 #size-cells = <0>;
655 679
656 port@0 680 port@0 {
657 681 reg = <0>;
658 682
659 683 i2s4_cif_ep: endpoint {
660 684 remote-endpoint = <&xbar_i2s4_ep>;
661 685 };
662 }; 686 };
663 687
664 i2s4_p 688 i2s4_port: port@1 {
665 689 reg = <1>;
666 690
667 !! 691 i2s4_dap_ep: endpoint@0 {
668 692 dai-format = "i2s";
669 693 /* Placeholder for external Codec */
670 694 };
671 }; 695 };
672 }; 696 };
673 }; 697 };
674 698
>> 699 dmic@702d4000 {
>> 700 status = "okay";
>> 701
>> 702 ports {
>> 703 #address-cells = <1>;
>> 704 #size-cells = <0>;
>> 705
>> 706 port@0 {
>> 707 reg = <0>;
>> 708
>> 709 dmic1_cif_ep: endpoint@0 {
>> 710 remote-endpoint = <&xbar_dmic1_ep>;
>> 711 };
>> 712 };
>> 713
>> 714 dmic1_port: port@1 {
>> 715 reg = <1>;
>> 716
>> 717 dmic1_dap_ep: endpoint@0 {
>> 718 /* Placeholder for external Codec */
>> 719 };
>> 720 };
>> 721 };
>> 722 };
>> 723
>> 724 dmic@702d4100 {
>> 725 status = "okay";
>> 726
>> 727 ports {
>> 728 #address-cells = <1>;
>> 729 #size-cells = <0>;
>> 730
>> 731 port@0 {
>> 732 reg = <0>;
>> 733
>> 734 dmic2_cif_ep: endpoint@0 {
>> 735 remote-endpoint = <&xbar_dmic2_ep>;
>> 736 };
>> 737 };
>> 738
>> 739 dmic2_port: port@1 {
>> 740 reg = <1>;
>> 741
>> 742 dmic2_dap_ep: endpoint@0 {
>> 743 /* Placeholder for external Codec */
>> 744 };
>> 745 };
>> 746 };
>> 747 };
>> 748
675 sfc@702d2000 { 749 sfc@702d2000 {
676 status = "okay 750 status = "okay";
677 751
678 ports { 752 ports {
679 #addre 753 #address-cells = <1>;
680 #size- 754 #size-cells = <0>;
681 755
682 port@0 756 port@0 {
683 757 reg = <0>;
684 758
685 759 sfc1_cif_in_ep: endpoint {
686 760 remote-endpoint = <&xbar_sfc1_in_ep>;
687 761 };
688 }; 762 };
689 763
690 sfc1_o 764 sfc1_out_port: port@1 {
691 765 reg = <1>;
692 766
693 767 sfc1_cif_out_ep: endpoint {
694 768 remote-endpoint = <&xbar_sfc1_out_ep>;
695 769 };
696 }; 770 };
697 }; 771 };
698 }; 772 };
699 773
700 sfc@702d2200 { 774 sfc@702d2200 {
701 status = "okay 775 status = "okay";
702 776
703 ports { 777 ports {
704 #addre 778 #address-cells = <1>;
705 #size- 779 #size-cells = <0>;
706 780
707 port@0 781 port@0 {
708 782 reg = <0>;
709 783
710 784 sfc2_cif_in_ep: endpoint {
711 785 remote-endpoint = <&xbar_sfc2_in_ep>;
712 786 };
713 }; 787 };
714 788
715 sfc2_o 789 sfc2_out_port: port@1 {
716 790 reg = <1>;
717 791
718 792 sfc2_cif_out_ep: endpoint {
719 793 remote-endpoint = <&xbar_sfc2_out_ep>;
720 794 };
721 }; 795 };
722 }; 796 };
723 }; 797 };
724 798
725 sfc@702d2400 { 799 sfc@702d2400 {
726 status = "okay 800 status = "okay";
727 801
728 ports { 802 ports {
729 #addre 803 #address-cells = <1>;
730 #size- 804 #size-cells = <0>;
731 805
732 port@0 806 port@0 {
733 807 reg = <0>;
734 808
735 809 sfc3_cif_in_ep: endpoint {
736 810 remote-endpoint = <&xbar_sfc3_in_ep>;
737 811 };
738 }; 812 };
739 813
740 sfc3_o 814 sfc3_out_port: port@1 {
741 815 reg = <1>;
742 816
743 817 sfc3_cif_out_ep: endpoint {
744 818 remote-endpoint = <&xbar_sfc3_out_ep>;
745 819 };
746 }; 820 };
747 }; 821 };
748 }; 822 };
749 823
750 sfc@702d2600 { 824 sfc@702d2600 {
751 status = "okay 825 status = "okay";
752 826
753 ports { 827 ports {
754 #addre 828 #address-cells = <1>;
755 #size- 829 #size-cells = <0>;
756 830
757 port@0 831 port@0 {
758 832 reg = <0>;
759 833
760 834 sfc4_cif_in_ep: endpoint {
761 835 remote-endpoint = <&xbar_sfc4_in_ep>;
762 836 };
763 }; 837 };
764 838
765 sfc4_o 839 sfc4_out_port: port@1 {
766 840 reg = <1>;
767 841
768 842 sfc4_cif_out_ep: endpoint {
769 843 remote-endpoint = <&xbar_sfc4_out_ep>;
770 844 };
771 }; 845 };
772 }; 846 };
773 }; 847 };
774 848
>> 849 mvc@702da000 {
>> 850 status = "okay";
>> 851
>> 852 ports {
>> 853 #address-cells = <1>;
>> 854 #size-cells = <0>;
>> 855
>> 856 port@0 {
>> 857 reg = <0>;
>> 858
>> 859 mvc1_cif_in_ep: endpoint {
>> 860 remote-endpoint = <&xbar_mvc1_in_ep>;
>> 861 };
>> 862 };
>> 863
>> 864 mvc1_out_port: port@1 {
>> 865 reg = <1>;
>> 866
>> 867 mvc1_cif_out_ep: endpoint {
>> 868 remote-endpoint = <&xbar_mvc1_out_ep>;
>> 869 };
>> 870 };
>> 871 };
>> 872 };
>> 873
>> 874 mvc@702da200 {
>> 875 status = "okay";
>> 876
>> 877 ports {
>> 878 #address-cells = <1>;
>> 879 #size-cells = <0>;
>> 880
>> 881 port@0 {
>> 882 reg = <0>;
>> 883
>> 884 mvc2_cif_in_ep: endpoint {
>> 885 remote-endpoint = <&xbar_mvc2_in_ep>;
>> 886 };
>> 887 };
>> 888
>> 889 mvc2_out_port: port@1 {
>> 890 reg = <1>;
>> 891
>> 892 mvc2_cif_out_ep: endpoint {
>> 893 remote-endpoint = <&xbar_mvc2_out_ep>;
>> 894 };
>> 895 };
>> 896 };
>> 897 };
>> 898
775 amx@702d3000 { 899 amx@702d3000 {
776 status = "okay 900 status = "okay";
777 901
778 ports { 902 ports {
779 #addre 903 #address-cells = <1>;
780 #size- 904 #size-cells = <0>;
781 905
782 port@0 906 port@0 {
783 907 reg = <0>;
784 908
785 909 amx1_in1_ep: endpoint {
786 910 remote-endpoint = <&xbar_amx1_in1_ep>;
787 911 };
788 }; 912 };
789 913
790 port@1 914 port@1 {
791 915 reg = <1>;
792 916
793 917 amx1_in2_ep: endpoint {
794 918 remote-endpoint = <&xbar_amx1_in2_ep>;
795 919 };
796 }; 920 };
797 921
798 port@2 922 port@2 {
799 923 reg = <2>;
800 924
801 925 amx1_in3_ep: endpoint {
802 926 remote-endpoint = <&xbar_amx1_in3_ep>;
803 927 };
804 }; 928 };
805 929
806 port@3 930 port@3 {
807 931 reg = <3>;
808 932
809 933 amx1_in4_ep: endpoint {
810 934 remote-endpoint = <&xbar_amx1_in4_ep>;
811 935 };
812 }; 936 };
813 937
814 amx1_o 938 amx1_out_port: port@4 {
815 939 reg = <4>;
816 940
817 941 amx1_out_ep: endpoint {
818 942 remote-endpoint = <&xbar_amx1_out_ep>;
819 943 };
820 }; 944 };
821 }; 945 };
822 }; 946 };
823 947
824 amx@702d3100 { 948 amx@702d3100 {
825 status = "okay 949 status = "okay";
826 950
827 ports { 951 ports {
828 #addre 952 #address-cells = <1>;
829 #size- 953 #size-cells = <0>;
830 954
831 port@0 955 port@0 {
832 956 reg = <0>;
833 957
834 958 amx2_in1_ep: endpoint {
835 959 remote-endpoint = <&xbar_amx2_in1_ep>;
836 960 };
837 }; 961 };
838 962
839 port@1 963 port@1 {
840 964 reg = <1>;
841 965
842 966 amx2_in2_ep: endpoint {
843 967 remote-endpoint = <&xbar_amx2_in2_ep>;
844 968 };
845 }; 969 };
846 970
847 amx2_i 971 amx2_in3_port: port@2 {
848 972 reg = <2>;
849 973
850 974 amx2_in3_ep: endpoint {
851 975 remote-endpoint = <&xbar_amx2_in3_ep>;
852 976 };
853 }; 977 };
854 978
855 amx2_i 979 amx2_in4_port: port@3 {
856 980 reg = <3>;
857 981
858 982 amx2_in4_ep: endpoint {
859 983 remote-endpoint = <&xbar_amx2_in4_ep>;
860 984 };
861 }; 985 };
862 986
863 amx2_o 987 amx2_out_port: port@4 {
864 988 reg = <4>;
865 989
866 990 amx2_out_ep: endpoint {
867 991 remote-endpoint = <&xbar_amx2_out_ep>;
868 992 };
869 }; 993 };
870 }; 994 };
871 }; 995 };
872 996
873 adx@702d3800 { 997 adx@702d3800 {
874 status = "okay 998 status = "okay";
875 999
876 ports { 1000 ports {
877 #addre 1001 #address-cells = <1>;
878 #size- 1002 #size-cells = <0>;
879 1003
880 port@0 1004 port@0 {
881 1005 reg = <0>;
882 1006
883 1007 adx1_in_ep: endpoint {
884 1008 remote-endpoint = <&xbar_adx1_in_ep>;
885 1009 };
886 }; 1010 };
887 1011
888 adx1_o 1012 adx1_out1_port: port@1 {
889 1013 reg = <1>;
890 1014
891 1015 adx1_out1_ep: endpoint {
892 1016 remote-endpoint = <&xbar_adx1_out1_ep>;
893 1017 };
894 }; 1018 };
895 1019
896 adx1_o 1020 adx1_out2_port: port@2 {
897 1021 reg = <2>;
898 1022
899 1023 adx1_out2_ep: endpoint {
900 1024 remote-endpoint = <&xbar_adx1_out2_ep>;
901 1025 };
902 }; 1026 };
903 1027
904 adx1_o 1028 adx1_out3_port: port@3 {
905 1029 reg = <3>;
906 1030
907 1031 adx1_out3_ep: endpoint {
908 1032 remote-endpoint = <&xbar_adx1_out3_ep>;
909 1033 };
910 }; 1034 };
911 1035
912 adx1_o 1036 adx1_out4_port: port@4 {
913 1037 reg = <4>;
914 1038
915 1039 adx1_out4_ep: endpoint {
916 1040 remote-endpoint = <&xbar_adx1_out4_ep>;
917 1041 };
918 }; 1042 };
919 }; 1043 };
920 }; 1044 };
921 1045
922 adx@702d3900 { 1046 adx@702d3900 {
923 status = "okay 1047 status = "okay";
924 1048
925 ports { 1049 ports {
926 #addre 1050 #address-cells = <1>;
927 #size- 1051 #size-cells = <0>;
928 1052
929 port@0 1053 port@0 {
930 1054 reg = <0>;
931 1055
932 1056 adx2_in_ep: endpoint {
933 1057 remote-endpoint = <&xbar_adx2_in_ep>;
934 1058 };
935 }; 1059 };
936 1060
937 adx2_o 1061 adx2_out1_port: port@1 {
938 1062 reg = <1>;
939 1063
940 1064 adx2_out1_ep: endpoint {
941 1065 remote-endpoint = <&xbar_adx2_out1_ep>;
942 1066 };
943 }; 1067 };
944 1068
945 adx2_o 1069 adx2_out2_port: port@2 {
946 1070 reg = <2>;
947 1071
948 1072 adx2_out2_ep: endpoint {
949 1073 remote-endpoint = <&xbar_adx2_out2_ep>;
950 1074 };
951 }; 1075 };
952 1076
953 adx2_o 1077 adx2_out3_port: port@3 {
954 1078 reg = <3>;
955 1079
956 1080 adx2_out3_ep: endpoint {
957 1081 remote-endpoint = <&xbar_adx2_out3_ep>;
958 1082 };
959 }; 1083 };
960 1084
961 adx2_o 1085 adx2_out4_port: port@4 {
962 1086 reg = <4>;
963 1087
964 1088 adx2_out4_ep: endpoint {
965 1089 remote-endpoint = <&xbar_adx2_out4_ep>;
966 1090 };
967 }; 1091 };
968 }; 1092 };
969 }; 1093 };
970 1094
971 dmic@702d4000 { <<
972 status = "okay <<
973 <<
974 ports { <<
975 #addre <<
976 #size- <<
977 <<
978 port@0 <<
979 <<
980 <<
981 <<
982 <<
983 <<
984 }; <<
985 <<
986 dmic1_ <<
987 <<
988 <<
989 <<
990 <<
991 <<
992 }; <<
993 }; <<
994 }; <<
995 <<
996 dmic@702d4100 { <<
997 status = "okay <<
998 <<
999 ports { <<
1000 #addr <<
1001 #size <<
1002 <<
1003 port@ <<
1004 <<
1005 <<
1006 <<
1007 <<
1008 <<
1009 }; <<
1010 <<
1011 dmic2 <<
1012 <<
1013 <<
1014 <<
1015 <<
1016 <<
1017 }; <<
1018 }; <<
1019 }; <<
1020 <<
1021 processing-engine@702 <<
1022 status = "oka <<
1023 <<
1024 ports { <<
1025 #addr <<
1026 #size <<
1027 <<
1028 port@ <<
1029 <<
1030 <<
1031 <<
1032 <<
1033 <<
1034 }; <<
1035 <<
1036 ope1_ <<
1037 <<
1038 <<
1039 <<
1040 <<
1041 <<
1042 }; <<
1043 }; <<
1044 }; <<
1045 <<
1046 processing-engine@702 <<
1047 status = "oka <<
1048 <<
1049 ports { <<
1050 #addr <<
1051 #size <<
1052 <<
1053 port@ <<
1054 <<
1055 <<
1056 <<
1057 <<
1058 <<
1059 }; <<
1060 <<
1061 ope2_ <<
1062 <<
1063 <<
1064 <<
1065 <<
1066 <<
1067 }; <<
1068 }; <<
1069 }; <<
1070 <<
1071 mvc@702da000 { <<
1072 status = "oka <<
1073 <<
1074 ports { <<
1075 #addr <<
1076 #size <<
1077 <<
1078 port@ <<
1079 <<
1080 <<
1081 <<
1082 <<
1083 <<
1084 }; <<
1085 <<
1086 mvc1_ <<
1087 <<
1088 <<
1089 <<
1090 <<
1091 <<
1092 }; <<
1093 }; <<
1094 }; <<
1095 <<
1096 mvc@702da200 { <<
1097 status = "oka <<
1098 <<
1099 ports { <<
1100 #addr <<
1101 #size <<
1102 <<
1103 port@ <<
1104 <<
1105 <<
1106 <<
1107 <<
1108 <<
1109 }; <<
1110 <<
1111 mvc2_ <<
1112 <<
1113 <<
1114 <<
1115 <<
1116 <<
1117 }; <<
1118 }; <<
1119 }; <<
1120 <<
1121 amixer@702dbb00 { 1095 amixer@702dbb00 {
1122 status = "oka 1096 status = "okay";
1123 1097
1124 ports { 1098 ports {
1125 #addr 1099 #address-cells = <1>;
1126 #size 1100 #size-cells = <0>;
1127 1101
1128 port@ 1102 port@0 {
1129 1103 reg = <0x0>;
1130 1104
1131 1105 mixer_in1_ep: endpoint {
1132 1106 remote-endpoint = <&xbar_mixer_in1_ep>;
1133 1107 };
1134 }; 1108 };
1135 1109
1136 port@ 1110 port@1 {
1137 1111 reg = <0x1>;
1138 1112
1139 1113 mixer_in2_ep: endpoint {
1140 1114 remote-endpoint = <&xbar_mixer_in2_ep>;
1141 1115 };
1142 }; 1116 };
1143 1117
1144 port@ 1118 port@2 {
1145 1119 reg = <0x2>;
1146 1120
1147 1121 mixer_in3_ep: endpoint {
1148 1122 remote-endpoint = <&xbar_mixer_in3_ep>;
1149 1123 };
1150 }; 1124 };
1151 1125
1152 port@ 1126 port@3 {
1153 1127 reg = <0x3>;
1154 1128
1155 1129 mixer_in4_ep: endpoint {
1156 1130 remote-endpoint = <&xbar_mixer_in4_ep>;
1157 1131 };
1158 }; 1132 };
1159 1133
1160 port@ 1134 port@4 {
1161 1135 reg = <0x4>;
1162 1136
1163 1137 mixer_in5_ep: endpoint {
1164 1138 remote-endpoint = <&xbar_mixer_in5_ep>;
1165 1139 };
1166 }; 1140 };
1167 1141
1168 port@ 1142 port@5 {
1169 1143 reg = <0x5>;
1170 1144
1171 1145 mixer_in6_ep: endpoint {
1172 1146 remote-endpoint = <&xbar_mixer_in6_ep>;
1173 1147 };
1174 }; 1148 };
1175 1149
1176 port@ 1150 port@6 {
1177 1151 reg = <0x6>;
1178 1152
1179 1153 mixer_in7_ep: endpoint {
1180 1154 remote-endpoint = <&xbar_mixer_in7_ep>;
1181 1155 };
1182 }; 1156 };
1183 1157
1184 port@ 1158 port@7 {
1185 1159 reg = <0x7>;
1186 1160
1187 1161 mixer_in8_ep: endpoint {
1188 1162 remote-endpoint = <&xbar_mixer_in8_ep>;
1189 1163 };
1190 }; 1164 };
1191 1165
1192 port@ 1166 port@8 {
1193 1167 reg = <0x8>;
1194 1168
1195 1169 mixer_in9_ep: endpoint {
1196 1170 remote-endpoint = <&xbar_mixer_in9_ep>;
1197 1171 };
1198 }; 1172 };
1199 1173
1200 port@ 1174 port@9 {
1201 1175 reg = <0x9>;
1202 1176
1203 1177 mixer_in10_ep: endpoint {
1204 1178 remote-endpoint = <&xbar_mixer_in10_ep>;
1205 1179 };
1206 }; 1180 };
1207 1181
1208 mixer 1182 mixer_out1_port: port@a {
1209 1183 reg = <0xa>;
1210 1184
1211 1185 mixer_out1_ep: endpoint {
1212 1186 remote-endpoint = <&xbar_mixer_out1_ep>;
1213 1187 };
1214 }; 1188 };
1215 1189
1216 mixer 1190 mixer_out2_port: port@b {
1217 1191 reg = <0xb>;
1218 1192
1219 1193 mixer_out2_ep: endpoint {
1220 1194 remote-endpoint = <&xbar_mixer_out2_ep>;
1221 1195 };
1222 }; 1196 };
1223 1197
1224 mixer 1198 mixer_out3_port: port@c {
1225 1199 reg = <0xc>;
1226 1200
1227 1201 mixer_out3_ep: endpoint {
1228 1202 remote-endpoint = <&xbar_mixer_out3_ep>;
1229 1203 };
1230 }; 1204 };
1231 1205
1232 mixer 1206 mixer_out4_port: port@d {
1233 1207 reg = <0xd>;
1234 1208
1235 1209 mixer_out4_ep: endpoint {
1236 1210 remote-endpoint = <&xbar_mixer_out4_ep>;
1237 1211 };
1238 }; 1212 };
1239 1213
1240 mixer 1214 mixer_out5_port: port@e {
1241 1215 reg = <0xe>;
1242 1216
1243 1217 mixer_out5_ep: endpoint {
1244 1218 remote-endpoint = <&xbar_mixer_out5_ep>;
1245 1219 };
1246 }; 1220 };
1247 }; 1221 };
1248 }; 1222 };
1249 1223
1250 ports { 1224 ports {
1251 xbar_i2s3_por 1225 xbar_i2s3_port: port@c {
1252 reg = 1226 reg = <0xc>;
1253 1227
1254 xbar_ 1228 xbar_i2s3_ep: endpoint {
1255 1229 remote-endpoint = <&i2s3_cif_ep>;
1256 }; 1230 };
1257 }; 1231 };
1258 1232
1259 xbar_i2s4_por 1233 xbar_i2s4_port: port@d {
1260 reg = 1234 reg = <0xd>;
1261 1235
1262 xbar_ 1236 xbar_i2s4_ep: endpoint {
1263 1237 remote-endpoint = <&i2s4_cif_ep>;
1264 }; 1238 };
1265 }; 1239 };
1266 1240
1267 xbar_dmic1_po 1241 xbar_dmic1_port: port@f {
1268 reg = 1242 reg = <0xf>;
1269 1243
1270 xbar_ 1244 xbar_dmic1_ep: endpoint {
1271 1245 remote-endpoint = <&dmic1_cif_ep>;
1272 }; 1246 };
1273 }; 1247 };
1274 1248
1275 xbar_dmic2_po 1249 xbar_dmic2_port: port@10 {
1276 reg = 1250 reg = <0x10>;
1277 1251
1278 xbar_ 1252 xbar_dmic2_ep: endpoint {
1279 1253 remote-endpoint = <&dmic2_cif_ep>;
1280 }; 1254 };
1281 }; 1255 };
1282 1256
1283 xbar_sfc1_in_ 1257 xbar_sfc1_in_port: port@12 {
1284 reg = 1258 reg = <0x12>;
1285 1259
1286 xbar_ 1260 xbar_sfc1_in_ep: endpoint {
1287 1261 remote-endpoint = <&sfc1_cif_in_ep>;
1288 }; 1262 };
1289 }; 1263 };
1290 1264
1291 port@13 { 1265 port@13 {
1292 reg = 1266 reg = <0x13>;
1293 1267
1294 xbar_ 1268 xbar_sfc1_out_ep: endpoint {
1295 1269 remote-endpoint = <&sfc1_cif_out_ep>;
1296 }; 1270 };
1297 }; 1271 };
1298 1272
1299 xbar_sfc2_in_ 1273 xbar_sfc2_in_port: port@14 {
1300 reg = 1274 reg = <0x14>;
1301 1275
1302 xbar_ 1276 xbar_sfc2_in_ep: endpoint {
1303 1277 remote-endpoint = <&sfc2_cif_in_ep>;
1304 }; 1278 };
1305 }; 1279 };
1306 1280
1307 port@15 { 1281 port@15 {
1308 reg = 1282 reg = <0x15>;
1309 1283
1310 xbar_ 1284 xbar_sfc2_out_ep: endpoint {
1311 1285 remote-endpoint = <&sfc2_cif_out_ep>;
1312 }; 1286 };
1313 }; 1287 };
1314 1288
1315 xbar_sfc3_in_ 1289 xbar_sfc3_in_port: port@16 {
1316 reg = 1290 reg = <0x16>;
1317 1291
1318 xbar_ 1292 xbar_sfc3_in_ep: endpoint {
1319 1293 remote-endpoint = <&sfc3_cif_in_ep>;
1320 }; 1294 };
1321 }; 1295 };
1322 1296
1323 port@17 { 1297 port@17 {
1324 reg = 1298 reg = <0x17>;
1325 1299
1326 xbar_ 1300 xbar_sfc3_out_ep: endpoint {
1327 1301 remote-endpoint = <&sfc3_cif_out_ep>;
1328 }; 1302 };
1329 }; 1303 };
1330 1304
1331 xbar_sfc4_in_ 1305 xbar_sfc4_in_port: port@18 {
1332 reg = 1306 reg = <0x18>;
1333 1307
1334 xbar_ 1308 xbar_sfc4_in_ep: endpoint {
1335 1309 remote-endpoint = <&sfc4_cif_in_ep>;
1336 }; 1310 };
1337 }; 1311 };
1338 1312
1339 port@19 { 1313 port@19 {
1340 reg = 1314 reg = <0x19>;
1341 1315
1342 xbar_ 1316 xbar_sfc4_out_ep: endpoint {
1343 1317 remote-endpoint = <&sfc4_cif_out_ep>;
1344 }; 1318 };
1345 }; 1319 };
1346 1320
1347 xbar_mvc1_in_ 1321 xbar_mvc1_in_port: port@1a {
1348 reg = 1322 reg = <0x1a>;
1349 1323
1350 xbar_ 1324 xbar_mvc1_in_ep: endpoint {
1351 1325 remote-endpoint = <&mvc1_cif_in_ep>;
1352 }; 1326 };
1353 }; 1327 };
1354 1328
1355 port@1b { 1329 port@1b {
1356 reg = 1330 reg = <0x1b>;
1357 1331
1358 xbar_ 1332 xbar_mvc1_out_ep: endpoint {
1359 1333 remote-endpoint = <&mvc1_cif_out_ep>;
1360 }; 1334 };
1361 }; 1335 };
1362 1336
1363 xbar_mvc2_in_ 1337 xbar_mvc2_in_port: port@1c {
1364 reg = 1338 reg = <0x1c>;
1365 1339
1366 xbar_ 1340 xbar_mvc2_in_ep: endpoint {
1367 1341 remote-endpoint = <&mvc2_cif_in_ep>;
1368 }; 1342 };
1369 }; 1343 };
1370 1344
1371 port@1d { 1345 port@1d {
1372 reg = 1346 reg = <0x1d>;
1373 1347
1374 xbar_ 1348 xbar_mvc2_out_ep: endpoint {
1375 1349 remote-endpoint = <&mvc2_cif_out_ep>;
1376 }; 1350 };
1377 }; 1351 };
1378 1352
1379 xbar_amx1_in1 1353 xbar_amx1_in1_port: port@1e {
1380 reg = 1354 reg = <0x1e>;
1381 1355
1382 xbar_ 1356 xbar_amx1_in1_ep: endpoint {
1383 1357 remote-endpoint = <&amx1_in1_ep>;
1384 }; 1358 };
1385 }; 1359 };
1386 1360
1387 xbar_amx1_in2 1361 xbar_amx1_in2_port: port@1f {
1388 reg = 1362 reg = <0x1f>;
1389 1363
1390 xbar_ 1364 xbar_amx1_in2_ep: endpoint {
1391 1365 remote-endpoint = <&amx1_in2_ep>;
1392 }; 1366 };
1393 }; 1367 };
1394 1368
1395 xbar_amx1_in3 1369 xbar_amx1_in3_port: port@20 {
1396 reg = 1370 reg = <0x20>;
1397 1371
1398 xbar_ 1372 xbar_amx1_in3_ep: endpoint {
1399 1373 remote-endpoint = <&amx1_in3_ep>;
1400 }; 1374 };
1401 }; 1375 };
1402 1376
1403 xbar_amx1_in4 1377 xbar_amx1_in4_port: port@21 {
1404 reg = 1378 reg = <0x21>;
1405 1379
1406 xbar_ 1380 xbar_amx1_in4_ep: endpoint {
1407 1381 remote-endpoint = <&amx1_in4_ep>;
1408 }; 1382 };
1409 }; 1383 };
1410 1384
1411 port@22 { 1385 port@22 {
1412 reg = 1386 reg = <0x22>;
1413 1387
1414 xbar_ 1388 xbar_amx1_out_ep: endpoint {
1415 1389 remote-endpoint = <&amx1_out_ep>;
1416 }; 1390 };
1417 }; 1391 };
1418 1392
1419 xbar_amx2_in1 1393 xbar_amx2_in1_port: port@23 {
1420 reg = 1394 reg = <0x23>;
1421 1395
1422 xbar_ 1396 xbar_amx2_in1_ep: endpoint {
1423 1397 remote-endpoint = <&amx2_in1_ep>;
1424 }; 1398 };
1425 }; 1399 };
1426 1400
1427 xbar_amx2_in2 1401 xbar_amx2_in2_port: port@24 {
1428 reg = 1402 reg = <0x24>;
1429 1403
1430 xbar_ 1404 xbar_amx2_in2_ep: endpoint {
1431 1405 remote-endpoint = <&amx2_in2_ep>;
1432 }; 1406 };
1433 }; 1407 };
1434 1408
1435 xbar_amx2_in3 1409 xbar_amx2_in3_port: port@25 {
1436 reg = 1410 reg = <0x25>;
1437 1411
1438 xbar_ 1412 xbar_amx2_in3_ep: endpoint {
1439 1413 remote-endpoint = <&amx2_in3_ep>;
1440 }; 1414 };
1441 }; 1415 };
1442 1416
1443 xbar_amx2_in4 1417 xbar_amx2_in4_port: port@26 {
1444 reg = 1418 reg = <0x26>;
1445 1419
1446 xbar_ 1420 xbar_amx2_in4_ep: endpoint {
1447 1421 remote-endpoint = <&amx2_in4_ep>;
1448 }; 1422 };
1449 }; 1423 };
1450 1424
1451 port@27 { 1425 port@27 {
1452 reg = 1426 reg = <0x27>;
1453 1427
1454 xbar_ 1428 xbar_amx2_out_ep: endpoint {
1455 1429 remote-endpoint = <&amx2_out_ep>;
1456 }; 1430 };
1457 }; 1431 };
1458 1432
1459 xbar_adx1_in_ 1433 xbar_adx1_in_port: port@28 {
1460 reg = 1434 reg = <0x28>;
1461 1435
1462 xbar_ 1436 xbar_adx1_in_ep: endpoint {
1463 1437 remote-endpoint = <&adx1_in_ep>;
1464 }; 1438 };
1465 }; 1439 };
1466 1440
1467 port@29 { 1441 port@29 {
1468 reg = 1442 reg = <0x29>;
1469 1443
1470 xbar_ 1444 xbar_adx1_out1_ep: endpoint {
1471 1445 remote-endpoint = <&adx1_out1_ep>;
1472 }; 1446 };
1473 }; 1447 };
1474 1448
1475 port@2a { 1449 port@2a {
1476 reg = 1450 reg = <0x2a>;
1477 1451
1478 xbar_ 1452 xbar_adx1_out2_ep: endpoint {
1479 1453 remote-endpoint = <&adx1_out2_ep>;
1480 }; 1454 };
1481 }; 1455 };
1482 1456
1483 port@2b { 1457 port@2b {
1484 reg = 1458 reg = <0x2b>;
1485 1459
1486 xbar_ 1460 xbar_adx1_out3_ep: endpoint {
1487 1461 remote-endpoint = <&adx1_out3_ep>;
1488 }; 1462 };
1489 }; 1463 };
1490 1464
1491 port@2c { 1465 port@2c {
1492 reg = 1466 reg = <0x2c>;
1493 1467
1494 xbar_ 1468 xbar_adx1_out4_ep: endpoint {
1495 1469 remote-endpoint = <&adx1_out4_ep>;
1496 }; 1470 };
1497 }; 1471 };
1498 1472
1499 xbar_adx2_in_ 1473 xbar_adx2_in_port: port@2d {
1500 reg = 1474 reg = <0x2d>;
1501 1475
1502 xbar_ 1476 xbar_adx2_in_ep: endpoint {
1503 1477 remote-endpoint = <&adx2_in_ep>;
1504 }; 1478 };
1505 }; 1479 };
1506 1480
1507 port@2e { 1481 port@2e {
1508 reg = 1482 reg = <0x2e>;
1509 1483
1510 xbar_ 1484 xbar_adx2_out1_ep: endpoint {
1511 1485 remote-endpoint = <&adx2_out1_ep>;
1512 }; 1486 };
1513 }; 1487 };
1514 1488
1515 port@2f { 1489 port@2f {
1516 reg = 1490 reg = <0x2f>;
1517 1491
1518 xbar_ 1492 xbar_adx2_out2_ep: endpoint {
1519 1493 remote-endpoint = <&adx2_out2_ep>;
1520 }; 1494 };
1521 }; 1495 };
1522 1496
1523 port@30 { 1497 port@30 {
1524 reg = 1498 reg = <0x30>;
1525 1499
1526 xbar_ 1500 xbar_adx2_out3_ep: endpoint {
1527 1501 remote-endpoint = <&adx2_out3_ep>;
1528 }; 1502 };
1529 }; 1503 };
1530 1504
1531 port@31 { 1505 port@31 {
1532 reg = 1506 reg = <0x31>;
1533 1507
1534 xbar_ 1508 xbar_adx2_out4_ep: endpoint {
1535 1509 remote-endpoint = <&adx2_out4_ep>;
1536 }; 1510 };
1537 }; 1511 };
1538 1512
1539 xbar_mixer_in 1513 xbar_mixer_in1_port: port@32 {
1540 reg = 1514 reg = <0x32>;
1541 1515
1542 xbar_ 1516 xbar_mixer_in1_ep: endpoint {
1543 1517 remote-endpoint = <&mixer_in1_ep>;
1544 }; 1518 };
1545 }; 1519 };
1546 1520
1547 xbar_mixer_in 1521 xbar_mixer_in2_port: port@33 {
1548 reg = 1522 reg = <0x33>;
1549 1523
1550 xbar_ 1524 xbar_mixer_in2_ep: endpoint {
1551 1525 remote-endpoint = <&mixer_in2_ep>;
1552 }; 1526 };
1553 }; 1527 };
1554 1528
1555 xbar_mixer_in 1529 xbar_mixer_in3_port: port@34 {
1556 reg = 1530 reg = <0x34>;
1557 1531
1558 xbar_ 1532 xbar_mixer_in3_ep: endpoint {
1559 1533 remote-endpoint = <&mixer_in3_ep>;
1560 }; 1534 };
1561 }; 1535 };
1562 1536
1563 xbar_mixer_in 1537 xbar_mixer_in4_port: port@35 {
1564 reg = 1538 reg = <0x35>;
1565 1539
1566 xbar_ 1540 xbar_mixer_in4_ep: endpoint {
1567 1541 remote-endpoint = <&mixer_in4_ep>;
1568 }; 1542 };
1569 }; 1543 };
1570 1544
1571 xbar_mixer_in 1545 xbar_mixer_in5_port: port@36 {
1572 reg = 1546 reg = <0x36>;
1573 1547
1574 xbar_ 1548 xbar_mixer_in5_ep: endpoint {
1575 1549 remote-endpoint = <&mixer_in5_ep>;
1576 }; 1550 };
1577 }; 1551 };
1578 1552
1579 xbar_mixer_in 1553 xbar_mixer_in6_port: port@37 {
1580 reg = 1554 reg = <0x37>;
1581 1555
1582 xbar_ 1556 xbar_mixer_in6_ep: endpoint {
1583 1557 remote-endpoint = <&mixer_in6_ep>;
1584 }; 1558 };
1585 }; 1559 };
1586 1560
1587 xbar_mixer_in 1561 xbar_mixer_in7_port: port@38 {
1588 reg = 1562 reg = <0x38>;
1589 1563
1590 xbar_ 1564 xbar_mixer_in7_ep: endpoint {
1591 1565 remote-endpoint = <&mixer_in7_ep>;
1592 }; 1566 };
1593 }; 1567 };
1594 1568
1595 xbar_mixer_in 1569 xbar_mixer_in8_port: port@39 {
1596 reg = 1570 reg = <0x39>;
1597 1571
1598 xbar_ 1572 xbar_mixer_in8_ep: endpoint {
1599 1573 remote-endpoint = <&mixer_in8_ep>;
1600 }; 1574 };
1601 }; 1575 };
1602 1576
1603 xbar_mixer_in 1577 xbar_mixer_in9_port: port@3a {
1604 reg = 1578 reg = <0x3a>;
1605 1579
1606 xbar_ 1580 xbar_mixer_in9_ep: endpoint {
1607 1581 remote-endpoint = <&mixer_in9_ep>;
1608 }; 1582 };
1609 }; 1583 };
1610 1584
1611 xbar_mixer_in 1585 xbar_mixer_in10_port: port@3b {
1612 reg = 1586 reg = <0x3b>;
1613 1587
1614 xbar_ 1588 xbar_mixer_in10_ep: endpoint {
1615 1589 remote-endpoint = <&mixer_in10_ep>;
1616 }; 1590 };
1617 }; 1591 };
1618 1592
1619 port@3c { 1593 port@3c {
1620 reg = 1594 reg = <0x3c>;
1621 1595
1622 xbar_ 1596 xbar_mixer_out1_ep: endpoint {
1623 1597 remote-endpoint = <&mixer_out1_ep>;
1624 }; 1598 };
1625 }; 1599 };
1626 1600
1627 port@3d { 1601 port@3d {
1628 reg = 1602 reg = <0x3d>;
1629 1603
1630 xbar_ 1604 xbar_mixer_out2_ep: endpoint {
1631 1605 remote-endpoint = <&mixer_out2_ep>;
1632 }; 1606 };
1633 }; 1607 };
1634 1608
1635 port@3e { 1609 port@3e {
1636 reg = 1610 reg = <0x3e>;
1637 1611
1638 xbar_ 1612 xbar_mixer_out3_ep: endpoint {
1639 1613 remote-endpoint = <&mixer_out3_ep>;
1640 }; 1614 };
1641 }; 1615 };
1642 1616
1643 port@3f { 1617 port@3f {
1644 reg = 1618 reg = <0x3f>;
1645 1619
1646 xbar_ 1620 xbar_mixer_out4_ep: endpoint {
1647 1621 remote-endpoint = <&mixer_out4_ep>;
1648 }; 1622 };
1649 }; 1623 };
1650 1624
1651 port@40 { 1625 port@40 {
1652 reg = 1626 reg = <0x40>;
1653 1627
1654 xbar_ 1628 xbar_mixer_out5_ep: endpoint {
1655 1629 remote-endpoint = <&mixer_out5_ep>;
1656 }; 1630 };
1657 }; 1631 };
1658 <<
1659 xbar_ope1_in_ <<
1660 reg = <<
1661 <<
1662 xbar_ <<
1663 <<
1664 }; <<
1665 }; <<
1666 <<
1667 port@42 { <<
1668 reg = <<
1669 <<
1670 xbar_ <<
1671 <<
1672 }; <<
1673 }; <<
1674 <<
1675 xbar_ope2_in_ <<
1676 reg = <<
1677 <<
1678 xbar_ <<
1679 <<
1680 }; <<
1681 }; <<
1682 <<
1683 port@44 { <<
1684 reg = <<
1685 <<
1686 xbar_ <<
1687 <<
1688 }; <<
1689 }; <<
1690 }; 1632 };
1691 }; 1633 };
1692 <<
1693 dma-controller@702e2000 { <<
1694 status = "okay"; <<
1695 }; <<
1696 <<
1697 interrupt-controller@702f9000 <<
1698 status = "okay"; <<
1699 }; <<
1700 }; 1634 };
1701 1635
1702 spi@70410000 { 1636 spi@70410000 {
1703 status = "okay"; 1637 status = "okay";
1704 1638
1705 flash@0 { 1639 flash@0 {
1706 compatible = "jedec,s !! 1640 compatible = "spi-nor";
1707 reg = <0>; 1641 reg = <0>;
1708 spi-max-frequency = < 1642 spi-max-frequency = <104000000>;
1709 spi-tx-bus-width = <2 1643 spi-tx-bus-width = <2>;
1710 spi-rx-bus-width = <2 1644 spi-rx-bus-width = <2>;
1711 }; 1645 };
1712 }; 1646 };
1713 1647
1714 clk32k_in: clock-32k { !! 1648 clk32k_in: clock@0 {
1715 compatible = "fixed-clock"; 1649 compatible = "fixed-clock";
1716 clock-frequency = <32768>; 1650 clock-frequency = <32768>;
1717 #clock-cells = <0>; 1651 #clock-cells = <0>;
1718 }; 1652 };
1719 1653
1720 cpus { 1654 cpus {
1721 cpu@0 { 1655 cpu@0 {
1722 enable-method = "psci 1656 enable-method = "psci";
1723 }; 1657 };
1724 1658
1725 cpu@1 { 1659 cpu@1 {
1726 enable-method = "psci 1660 enable-method = "psci";
1727 }; 1661 };
1728 1662
1729 cpu@2 { 1663 cpu@2 {
1730 enable-method = "psci 1664 enable-method = "psci";
1731 }; 1665 };
1732 1666
1733 cpu@3 { 1667 cpu@3 {
1734 enable-method = "psci 1668 enable-method = "psci";
1735 }; 1669 };
1736 1670
1737 idle-states { 1671 idle-states {
1738 cpu-sleep { 1672 cpu-sleep {
1739 status = "oka 1673 status = "okay";
1740 }; 1674 };
1741 }; 1675 };
1742 }; 1676 };
1743 1677
1744 gpio-keys { !! 1678 fan: fan {
1745 compatible = "gpio-keys"; !! 1679 compatible = "pwm-fan";
>> 1680 pwms = <&pwm 3 45334>;
1746 1681
1747 key-force-recovery { !! 1682 cooling-levels = <0 64 128 255>;
1748 label = "Force Recove !! 1683 #cooling-cells = <2>;
1749 gpios = <&gpio TEGRA_ !! 1684 };
1750 linux,input-type = <E !! 1685
1751 linux,code = <BTN_1>; !! 1686 thermal-zones {
1752 debounce-interval = < !! 1687 cpu {
>> 1688 trips {
>> 1689 cpu_trip_critical: critical {
>> 1690 temperature = <96500>;
>> 1691 hysteresis = <0>;
>> 1692 type = "critical";
>> 1693 };
>> 1694
>> 1695 cpu_trip_hot: hot {
>> 1696 temperature = <70000>;
>> 1697 hysteresis = <2000>;
>> 1698 type = "hot";
>> 1699 };
>> 1700
>> 1701 cpu_trip_active: active {
>> 1702 temperature = <50000>;
>> 1703 hysteresis = <2000>;
>> 1704 type = "active";
>> 1705 };
>> 1706
>> 1707 cpu_trip_passive: passive {
>> 1708 temperature = <30000>;
>> 1709 hysteresis = <2000>;
>> 1710 type = "passive";
>> 1711 };
>> 1712 };
>> 1713
>> 1714 cooling-maps {
>> 1715 cpu-critical {
>> 1716 cooling-device = <&fan 3 3>;
>> 1717 trip = <&cpu_trip_critical>;
>> 1718 };
>> 1719
>> 1720 cpu-hot {
>> 1721 cooling-device = <&fan 2 2>;
>> 1722 trip = <&cpu_trip_hot>;
>> 1723 };
>> 1724
>> 1725 cpu-active {
>> 1726 cooling-device = <&fan 1 1>;
>> 1727 trip = <&cpu_trip_active>;
>> 1728 };
>> 1729
>> 1730 cpu-passive {
>> 1731 cooling-device = <&fan 0 0>;
>> 1732 trip = <&cpu_trip_passive>;
>> 1733 };
>> 1734 };
1753 }; 1735 };
>> 1736 };
1754 1737
1755 key-power { !! 1738 gpio-keys {
>> 1739 compatible = "gpio-keys";
>> 1740
>> 1741 power {
1756 label = "Power"; 1742 label = "Power";
1757 gpios = <&gpio TEGRA_ 1743 gpios = <&gpio TEGRA_GPIO(X, 5) GPIO_ACTIVE_LOW>;
1758 linux,input-type = <E 1744 linux,input-type = <EV_KEY>;
1759 linux,code = <KEY_POW 1745 linux,code = <KEY_POWER>;
1760 debounce-interval = < 1746 debounce-interval = <30>;
1761 wakeup-event-action = 1747 wakeup-event-action = <EV_ACT_ASSERTED>;
1762 wakeup-source; 1748 wakeup-source;
1763 }; 1749 };
>> 1750
>> 1751 force-recovery {
>> 1752 label = "Force Recovery";
>> 1753 gpios = <&gpio TEGRA_GPIO(X, 6) GPIO_ACTIVE_LOW>;
>> 1754 linux,input-type = <EV_KEY>;
>> 1755 linux,code = <BTN_1>;
>> 1756 debounce-interval = <30>;
>> 1757 };
1764 }; 1758 };
1765 1759
1766 psci { 1760 psci {
1767 compatible = "arm,psci-1.0"; 1761 compatible = "arm,psci-1.0";
1768 method = "smc"; 1762 method = "smc";
1769 }; 1763 };
1770 1764
1771 fan: pwm-fan { !! 1765 vdd_5v0_sys: regulator@0 {
1772 compatible = "pwm-fan"; <<
1773 pwms = <&pwm 3 45334>; <<
1774 <<
1775 cooling-levels = <0 64 128 25 <<
1776 #cooling-cells = <2>; <<
1777 }; <<
1778 <<
1779 vdd_5v0_sys: regulator-vdd-5v0-sys { <<
1780 compatible = "regulator-fixed 1766 compatible = "regulator-fixed";
1781 1767
1782 regulator-name = "VDD_5V0_SYS 1768 regulator-name = "VDD_5V0_SYS";
1783 regulator-min-microvolt = <50 1769 regulator-min-microvolt = <5000000>;
1784 regulator-max-microvolt = <50 1770 regulator-max-microvolt = <5000000>;
1785 regulator-always-on; 1771 regulator-always-on;
1786 regulator-boot-on; 1772 regulator-boot-on;
1787 }; 1773 };
1788 1774
1789 vdd_3v3_sys: regulator-vdd-3v3-sys { !! 1775 vdd_3v3_sys: regulator@1 {
1790 compatible = "regulator-fixed 1776 compatible = "regulator-fixed";
1791 1777
1792 regulator-name = "VDD_3V3_SYS 1778 regulator-name = "VDD_3V3_SYS";
1793 regulator-min-microvolt = <33 1779 regulator-min-microvolt = <3300000>;
1794 regulator-max-microvolt = <33 1780 regulator-max-microvolt = <3300000>;
1795 regulator-enable-ramp-delay = 1781 regulator-enable-ramp-delay = <240>;
>> 1782 regulator-disable-ramp-delay = <11340>;
1796 regulator-always-on; 1783 regulator-always-on;
1797 regulator-boot-on; 1784 regulator-boot-on;
1798 1785
1799 gpio = <&pmic 3 GPIO_ACTIVE_H 1786 gpio = <&pmic 3 GPIO_ACTIVE_HIGH>;
1800 enable-active-high; 1787 enable-active-high;
1801 1788
1802 vin-supply = <&vdd_5v0_sys>; 1789 vin-supply = <&vdd_5v0_sys>;
1803 }; 1790 };
1804 1791
1805 vdd_3v3_sd: regulator-vdd-3v3-sd { !! 1792 vdd_3v3_sd: regulator@2 {
1806 compatible = "regulator-fixed 1793 compatible = "regulator-fixed";
1807 1794
1808 regulator-name = "VDD_3V3_SD" 1795 regulator-name = "VDD_3V3_SD";
1809 regulator-min-microvolt = <33 1796 regulator-min-microvolt = <3300000>;
1810 regulator-max-microvolt = <33 1797 regulator-max-microvolt = <3300000>;
1811 1798
1812 gpio = <&gpio TEGRA_GPIO(Z, 3 1799 gpio = <&gpio TEGRA_GPIO(Z, 3) GPIO_ACTIVE_HIGH>;
1813 enable-active-high; 1800 enable-active-high;
1814 1801
1815 vin-supply = <&vdd_3v3_sys>; 1802 vin-supply = <&vdd_3v3_sys>;
1816 }; 1803 };
1817 1804
1818 vdd_hdmi: regulator-vdd-hdmi-5v0 { !! 1805 vdd_hdmi: regulator@3 {
1819 compatible = "regulator-fixed 1806 compatible = "regulator-fixed";
1820 1807
1821 regulator-name = "VDD_HDMI_5V 1808 regulator-name = "VDD_HDMI_5V0";
1822 regulator-min-microvolt = <50 1809 regulator-min-microvolt = <5000000>;
1823 regulator-max-microvolt = <50 1810 regulator-max-microvolt = <5000000>;
1824 1811
1825 vin-supply = <&vdd_5v0_sys>; 1812 vin-supply = <&vdd_5v0_sys>;
1826 }; 1813 };
1827 1814
1828 vdd_hub_3v3: regulator-vdd-hub-3v3 { !! 1815 vdd_hub_3v3: regulator@4 {
1829 compatible = "regulator-fixed 1816 compatible = "regulator-fixed";
1830 1817
1831 regulator-name = "VDD_HUB_3V3 1818 regulator-name = "VDD_HUB_3V3";
1832 regulator-min-microvolt = <33 1819 regulator-min-microvolt = <3300000>;
1833 regulator-max-microvolt = <33 1820 regulator-max-microvolt = <3300000>;
1834 1821
1835 gpio = <&gpio TEGRA_GPIO(A, 6 1822 gpio = <&gpio TEGRA_GPIO(A, 6) GPIO_ACTIVE_HIGH>;
1836 enable-active-high; 1823 enable-active-high;
1837 1824
1838 vin-supply = <&vdd_5v0_sys>; 1825 vin-supply = <&vdd_5v0_sys>;
1839 }; 1826 };
1840 1827
1841 vdd_cpu: regulator-vdd-cpu { !! 1828 vdd_cpu: regulator@5 {
1842 compatible = "regulator-fixed 1829 compatible = "regulator-fixed";
1843 1830
1844 regulator-name = "VDD_CPU"; 1831 regulator-name = "VDD_CPU";
1845 regulator-min-microvolt = <50 1832 regulator-min-microvolt = <5000000>;
1846 regulator-max-microvolt = <50 1833 regulator-max-microvolt = <5000000>;
1847 regulator-always-on; 1834 regulator-always-on;
1848 regulator-boot-on; 1835 regulator-boot-on;
1849 1836
1850 gpio = <&pmic 5 GPIO_ACTIVE_H 1837 gpio = <&pmic 5 GPIO_ACTIVE_HIGH>;
1851 enable-active-high; 1838 enable-active-high;
1852 1839
1853 vin-supply = <&vdd_5v0_sys>; 1840 vin-supply = <&vdd_5v0_sys>;
1854 }; 1841 };
1855 1842
1856 vdd_gpu: regulator-vdd-gpu { !! 1843 vdd_gpu: regulator@6 {
1857 compatible = "pwm-regulator"; 1844 compatible = "pwm-regulator";
1858 pwms = <&pwm 1 8000>; 1845 pwms = <&pwm 1 8000>;
1859 1846
1860 regulator-name = "VDD_GPU"; 1847 regulator-name = "VDD_GPU";
1861 regulator-min-microvolt = <71 1848 regulator-min-microvolt = <710000>;
1862 regulator-max-microvolt = <13 1849 regulator-max-microvolt = <1320000>;
1863 regulator-ramp-delay = <80>; 1850 regulator-ramp-delay = <80>;
1864 regulator-enable-ramp-delay = 1851 regulator-enable-ramp-delay = <2000>;
1865 regulator-settling-time-us = 1852 regulator-settling-time-us = <160>;
1866 1853
1867 enable-gpios = <&pmic 6 GPIO_ 1854 enable-gpios = <&pmic 6 GPIO_ACTIVE_HIGH>;
1868 vin-supply = <&vdd_5v0_sys>; 1855 vin-supply = <&vdd_5v0_sys>;
1869 }; 1856 };
1870 1857
1871 avdd_io_edp_1v05: regulator-avdd-io-e !! 1858 avdd_io_edp_1v05: regulator@7 {
1872 compatible = "regulator-fixed 1859 compatible = "regulator-fixed";
1873 1860
1874 regulator-name = "AVDD_IO_EDP 1861 regulator-name = "AVDD_IO_EDP_1V05";
1875 regulator-min-microvolt = <10 1862 regulator-min-microvolt = <1050000>;
1876 regulator-max-microvolt = <10 1863 regulator-max-microvolt = <1050000>;
1877 1864
1878 gpio = <&pmic 7 GPIO_ACTIVE_H 1865 gpio = <&pmic 7 GPIO_ACTIVE_HIGH>;
1879 enable-active-high; 1866 enable-active-high;
1880 1867
1881 vin-supply = <&avdd_1v05_pll> 1868 vin-supply = <&avdd_1v05_pll>;
1882 }; 1869 };
1883 1870
1884 vdd_5v0_usb: regulator-vdd-5v-usb { !! 1871 vdd_5v0_usb: regulator@8 {
1885 compatible = "regulator-fixed 1872 compatible = "regulator-fixed";
1886 1873
1887 regulator-name = "VDD_5V_USB" 1874 regulator-name = "VDD_5V_USB";
1888 regulator-min-microvolt = <50 1875 regulator-min-microvolt = <50000000>;
1889 regulator-max-microvolt = <50 1876 regulator-max-microvolt = <50000000>;
1890 1877
1891 vin-supply = <&vdd_5v0_sys>; 1878 vin-supply = <&vdd_5v0_sys>;
1892 }; 1879 };
1893 1880
1894 sound { 1881 sound {
1895 compatible = "nvidia,tegra210 1882 compatible = "nvidia,tegra210-audio-graph-card";
1896 status = "okay"; 1883 status = "okay";
1897 1884
1898 dais = /* FE */ 1885 dais = /* FE */
1899 <&admaif1_port>, <&adm 1886 <&admaif1_port>, <&admaif2_port>, <&admaif3_port>,
1900 <&admaif4_port>, <&adm 1887 <&admaif4_port>, <&admaif5_port>, <&admaif6_port>,
1901 <&admaif7_port>, <&adm 1888 <&admaif7_port>, <&admaif8_port>, <&admaif9_port>,
1902 <&admaif10_port>, 1889 <&admaif10_port>,
1903 /* Router */ 1890 /* Router */
1904 <&xbar_i2s3_port>, <&x 1891 <&xbar_i2s3_port>, <&xbar_i2s4_port>,
1905 <&xbar_dmic1_port>, <& 1892 <&xbar_dmic1_port>, <&xbar_dmic2_port>,
1906 <&xbar_sfc1_in_port>, 1893 <&xbar_sfc1_in_port>, <&xbar_sfc2_in_port>,
1907 <&xbar_sfc3_in_port>, 1894 <&xbar_sfc3_in_port>, <&xbar_sfc4_in_port>,
1908 <&xbar_mvc1_in_port>, 1895 <&xbar_mvc1_in_port>, <&xbar_mvc2_in_port>,
1909 <&xbar_amx1_in1_port>, 1896 <&xbar_amx1_in1_port>, <&xbar_amx1_in2_port>,
1910 <&xbar_amx1_in3_port>, 1897 <&xbar_amx1_in3_port>, <&xbar_amx1_in4_port>,
1911 <&xbar_amx2_in1_port>, 1898 <&xbar_amx2_in1_port>, <&xbar_amx2_in2_port>,
1912 <&xbar_amx2_in3_port>, 1899 <&xbar_amx2_in3_port>, <&xbar_amx2_in4_port>,
1913 <&xbar_adx1_in_port>, 1900 <&xbar_adx1_in_port>, <&xbar_adx2_in_port>,
1914 <&xbar_mixer_in1_port> 1901 <&xbar_mixer_in1_port>, <&xbar_mixer_in2_port>,
1915 <&xbar_mixer_in3_port> 1902 <&xbar_mixer_in3_port>, <&xbar_mixer_in4_port>,
1916 <&xbar_mixer_in5_port> 1903 <&xbar_mixer_in5_port>, <&xbar_mixer_in6_port>,
1917 <&xbar_mixer_in7_port> 1904 <&xbar_mixer_in7_port>, <&xbar_mixer_in8_port>,
1918 <&xbar_mixer_in9_port> 1905 <&xbar_mixer_in9_port>, <&xbar_mixer_in10_port>,
1919 <&xbar_ope1_in_port>, <<
1920 /* HW accelerators */ 1906 /* HW accelerators */
1921 <&sfc1_out_port>, <&sf 1907 <&sfc1_out_port>, <&sfc2_out_port>,
1922 <&sfc3_out_port>, <&sf 1908 <&sfc3_out_port>, <&sfc4_out_port>,
1923 <&mvc1_out_port>, <&mv 1909 <&mvc1_out_port>, <&mvc2_out_port>,
1924 <&amx1_out_port>, <&am 1910 <&amx1_out_port>, <&amx2_out_port>,
1925 <&adx1_out1_port>, <&a 1911 <&adx1_out1_port>, <&adx1_out2_port>,
1926 <&adx1_out3_port>, <&a 1912 <&adx1_out3_port>, <&adx1_out4_port>,
1927 <&adx2_out1_port>, <&a 1913 <&adx2_out1_port>, <&adx2_out2_port>,
1928 <&adx2_out3_port>, <&a 1914 <&adx2_out3_port>, <&adx2_out4_port>,
1929 <&mixer_out1_port>, <& 1915 <&mixer_out1_port>, <&mixer_out2_port>,
1930 <&mixer_out3_port>, <& 1916 <&mixer_out3_port>, <&mixer_out4_port>,
1931 <&mixer_out5_port>, 1917 <&mixer_out5_port>,
1932 <&ope1_out_port>, <&op <<
1933 /* I/O DAP Ports */ 1918 /* I/O DAP Ports */
1934 <&i2s3_port>, <&i2s4_p 1919 <&i2s3_port>, <&i2s4_port>,
1935 <&dmic1_port>, <&dmic2 1920 <&dmic1_port>, <&dmic2_port>;
1936 1921
1937 label = "NVIDIA Jetson Nano A 1922 label = "NVIDIA Jetson Nano APE";
1938 }; <<
1939 <<
1940 thermal-zones { <<
1941 cpu-thermal { <<
1942 trips { <<
1943 cpu_trip_crit <<
1944 tempe <<
1945 hyste <<
1946 type <<
1947 }; <<
1948 <<
1949 cpu_trip_hot: <<
1950 tempe <<
1951 hyste <<
1952 type <<
1953 }; <<
1954 <<
1955 cpu_trip_acti <<
1956 tempe <<
1957 hyste <<
1958 type <<
1959 }; <<
1960 <<
1961 cpu_trip_pass <<
1962 tempe <<
1963 hyste <<
1964 type <<
1965 }; <<
1966 }; <<
1967 <<
1968 cooling-maps { <<
1969 cpu-critical <<
1970 cooli <<
1971 trip <<
1972 }; <<
1973 <<
1974 cpu-hot { <<
1975 cooli <<
1976 trip <<
1977 }; <<
1978 <<
1979 cpu-active { <<
1980 cooli <<
1981 trip <<
1982 }; <<
1983 <<
1984 cpu-passive { <<
1985 cooli <<
1986 trip <<
1987 }; <<
1988 }; <<
1989 }; <<
1990 }; 1923 };
1991 }; 1924 };
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