1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/; 2 /dts-v1/;
3 3
4 #include <dt-bindings/input/gpio-keys.h> 4 #include <dt-bindings/input/gpio-keys.h>
5 #include <dt-bindings/input/linux-event-codes. 5 #include <dt-bindings/input/linux-event-codes.h>
6 #include <dt-bindings/mfd/max77620.h> 6 #include <dt-bindings/mfd/max77620.h>
7 7
8 #include "tegra210.dtsi" 8 #include "tegra210.dtsi"
9 9
10 / { 10 / {
11 model = "NVIDIA Jetson Nano Developer 11 model = "NVIDIA Jetson Nano Developer Kit";
12 compatible = "nvidia,p3450-0000", "nvi 12 compatible = "nvidia,p3450-0000", "nvidia,tegra210";
13 13
14 aliases { 14 aliases {
15 ethernet = "/pcie@1003000/pci@ 15 ethernet = "/pcie@1003000/pci@2,0/ethernet@0,0";
16 rtc0 = "/i2c@7000d000/pmic@3c" 16 rtc0 = "/i2c@7000d000/pmic@3c";
17 rtc1 = "/rtc@7000e000"; 17 rtc1 = "/rtc@7000e000";
18 serial0 = &uarta; 18 serial0 = &uarta;
19 }; 19 };
20 20
21 chosen { 21 chosen {
22 stdout-path = "serial0:115200n 22 stdout-path = "serial0:115200n8";
23 }; 23 };
24 24
25 memory@80000000 { 25 memory@80000000 {
26 device_type = "memory"; 26 device_type = "memory";
27 reg = <0x0 0x80000000 0x1 0x0> 27 reg = <0x0 0x80000000 0x1 0x0>;
28 }; 28 };
29 29
30 pcie@1003000 { 30 pcie@1003000 {
31 status = "okay"; 31 status = "okay";
32 32
33 hvddio-pex-supply = <&vdd_1v8> 33 hvddio-pex-supply = <&vdd_1v8>;
34 dvddio-pex-supply = <&vdd_pex_ 34 dvddio-pex-supply = <&vdd_pex_1v05>;
35 vddio-pex-ctl-supply = <&vdd_1 35 vddio-pex-ctl-supply = <&vdd_1v8>;
36 36
37 pci@1,0 { 37 pci@1,0 {
38 phys = <&{/padctl@7009f 38 phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>,
39 <&{/padctl@7009f 39 <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>,
40 <&{/padctl@7009f 40 <&{/padctl@7009f000/pads/pcie/lanes/pcie-3}>,
41 <&{/padctl@7009f 41 <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>;
42 phy-names = "pcie-0", 42 phy-names = "pcie-0", "pcie-1", "pcie-2", "pcie-3";
43 nvidia,num-lanes = <4> 43 nvidia,num-lanes = <4>;
44 status = "okay"; 44 status = "okay";
45 }; 45 };
46 46
47 pci@2,0 { 47 pci@2,0 {
48 phys = <&{/padctl@7009f 48 phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>;
49 phy-names = "pcie-0"; 49 phy-names = "pcie-0";
50 status = "okay"; 50 status = "okay";
51 51
52 ethernet@0,0 { 52 ethernet@0,0 {
53 reg = <0x00000 53 reg = <0x000000 0 0 0 0>;
54 local-mac-addr 54 local-mac-address = [ 00 00 00 00 00 00 ];
55 }; 55 };
56 }; 56 };
57 }; 57 };
58 58
59 host1x@50000000 { 59 host1x@50000000 {
60 dpaux@54040000 { 60 dpaux@54040000 {
61 status = "okay"; 61 status = "okay";
62 }; 62 };
63 63
64 vi@54080000 { 64 vi@54080000 {
65 status = "okay"; 65 status = "okay";
66 66
67 avdd-dsi-csi-supply = 67 avdd-dsi-csi-supply = <&vdd_sys_1v2>;
68 68
69 csi@838 { 69 csi@838 {
70 status = "okay 70 status = "okay";
71 }; 71 };
72 }; 72 };
73 73
74 sor@54540000 { 74 sor@54540000 {
75 status = "okay"; 75 status = "okay";
76 76
77 avdd-io-hdmi-dp-supply 77 avdd-io-hdmi-dp-supply = <&avdd_io_edp_1v05>;
78 vdd-hdmi-dp-pll-supply 78 vdd-hdmi-dp-pll-supply = <&vdd_1v8>;
79 79
80 nvidia,xbar-cfg = <2 1 80 nvidia,xbar-cfg = <2 1 0 3 4>;
81 nvidia,dpaux = <&dpaux 81 nvidia,dpaux = <&dpaux>;
82 }; 82 };
83 83
84 sor@54580000 { 84 sor@54580000 {
85 status = "okay"; 85 status = "okay";
86 86
87 avdd-io-hdmi-dp-supply 87 avdd-io-hdmi-dp-supply = <&avdd_1v05>;
88 vdd-hdmi-dp-pll-supply 88 vdd-hdmi-dp-pll-supply = <&vdd_1v8>;
89 hdmi-supply = <&vdd_hd 89 hdmi-supply = <&vdd_hdmi>;
90 90
91 nvidia,ddc-i2c-bus = < 91 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
92 nvidia,hpd-gpio = <&gp 92 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(CC, 1)
93 GPI 93 GPIO_ACTIVE_LOW>;
94 nvidia,xbar-cfg = <0 1 94 nvidia,xbar-cfg = <0 1 2 3 4>;
95 }; 95 };
96 96
97 dpaux@545c0000 { 97 dpaux@545c0000 {
98 status = "okay"; 98 status = "okay";
99 }; 99 };
100 100
101 i2c@546c0000 { 101 i2c@546c0000 {
102 status = "okay"; 102 status = "okay";
103 }; 103 };
104 }; 104 };
105 105
106 gpu@57000000 { 106 gpu@57000000 {
107 vdd-supply = <&vdd_gpu>; 107 vdd-supply = <&vdd_gpu>;
108 status = "okay"; 108 status = "okay";
109 }; 109 };
110 110
111 pinmux@700008d4 { 111 pinmux@700008d4 {
112 dvfs_pwm_active_state: pinmux- !! 112 dvfs_pwm_active_state: dvfs_pwm_active {
113 dvfs_pwm_pbb1 { 113 dvfs_pwm_pbb1 {
114 nvidia,pins = 114 nvidia,pins = "dvfs_pwm_pbb1";
115 nvidia,tristat 115 nvidia,tristate = <TEGRA_PIN_DISABLE>;
116 }; 116 };
117 }; 117 };
118 118
119 dvfs_pwm_inactive_state: pinmu !! 119 dvfs_pwm_inactive_state: dvfs_pwm_inactive {
120 dvfs_pwm_pbb1 { 120 dvfs_pwm_pbb1 {
121 nvidia,pins = 121 nvidia,pins = "dvfs_pwm_pbb1";
122 nvidia,tristat 122 nvidia,tristate = <TEGRA_PIN_ENABLE>;
123 }; 123 };
124 }; 124 };
125 }; 125 };
126 126
127 /* debug port */ 127 /* debug port */
128 serial@70006000 { 128 serial@70006000 {
129 /delete-property/ dmas; <<
130 /delete-property/ dma-names; <<
131 status = "okay"; 129 status = "okay";
132 }; 130 };
133 131
134 pwm@7000a000 { 132 pwm@7000a000 {
135 status = "okay"; 133 status = "okay";
136 }; 134 };
137 135
138 i2c@7000c500 { 136 i2c@7000c500 {
139 status = "okay"; 137 status = "okay";
140 clock-frequency = <100000>; 138 clock-frequency = <100000>;
141 139
142 eeprom@50 { 140 eeprom@50 {
143 compatible = "atmel,24 141 compatible = "atmel,24c02";
144 reg = <0x50>; 142 reg = <0x50>;
145 143
146 label = "module"; 144 label = "module";
147 vcc-supply = <&vdd_1v8 145 vcc-supply = <&vdd_1v8>;
148 address-width = <8>; 146 address-width = <8>;
149 pagesize = <8>; 147 pagesize = <8>;
150 size = <256>; 148 size = <256>;
151 read-only; 149 read-only;
152 }; 150 };
153 151
154 eeprom@57 { 152 eeprom@57 {
155 compatible = "atmel,24 153 compatible = "atmel,24c02";
156 reg = <0x57>; 154 reg = <0x57>;
157 155
158 label = "system"; 156 label = "system";
159 vcc-supply = <&vdd_1v8 157 vcc-supply = <&vdd_1v8>;
160 address-width = <8>; 158 address-width = <8>;
161 pagesize = <8>; 159 pagesize = <8>;
162 size = <256>; 160 size = <256>;
163 read-only; 161 read-only;
164 }; 162 };
165 }; 163 };
166 164
167 hdmi_ddc: i2c@7000c700 { 165 hdmi_ddc: i2c@7000c700 {
168 status = "okay"; 166 status = "okay";
169 clock-frequency = <100000>; 167 clock-frequency = <100000>;
170 }; 168 };
171 169
172 i2c@7000d000 { 170 i2c@7000d000 {
173 status = "okay"; 171 status = "okay";
174 clock-frequency = <400000>; 172 clock-frequency = <400000>;
175 173
176 pmic: pmic@3c { 174 pmic: pmic@3c {
177 compatible = "maxim,ma 175 compatible = "maxim,max77620";
178 reg = <0x3c>; 176 reg = <0x3c>;
179 interrupt-parent = <&t 177 interrupt-parent = <&tegra_pmc>;
180 interrupts = <51 IRQ_T 178 interrupts = <51 IRQ_TYPE_LEVEL_LOW>;
181 179
182 #interrupt-cells = <2> 180 #interrupt-cells = <2>;
183 interrupt-controller; 181 interrupt-controller;
184 182
185 #gpio-cells = <2>; 183 #gpio-cells = <2>;
186 gpio-controller; 184 gpio-controller;
187 185
188 pinctrl-names = "defau 186 pinctrl-names = "default";
189 pinctrl-0 = <&max77620 187 pinctrl-0 = <&max77620_default>;
190 188
191 fps { <<
192 fps0 { <<
193 maxim, <<
194 maxim, <<
195 }; <<
196 <<
197 fps1 { <<
198 maxim, <<
199 maxim, <<
200 }; <<
201 <<
202 fps2 { <<
203 maxim, <<
204 }; <<
205 }; <<
206 <<
207 max77620_default: pinm 189 max77620_default: pinmux {
208 gpio0 { 190 gpio0 {
209 pins = 191 pins = "gpio0";
210 functi 192 function = "gpio";
211 }; 193 };
212 194
213 gpio1 { 195 gpio1 {
214 pins = 196 pins = "gpio1";
215 functi 197 function = "fps-out";
216 drive- 198 drive-push-pull = <1>;
217 maxim, 199 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
218 maxim, 200 maxim,active-fps-power-up-slot = <0>;
219 maxim, 201 maxim,active-fps-power-down-slot = <7>;
220 }; 202 };
221 203
222 gpio2 { 204 gpio2 {
223 pins = 205 pins = "gpio2";
224 functi 206 function = "fps-out";
225 drive- 207 drive-open-drain = <1>;
226 maxim, 208 maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
227 maxim, 209 maxim,active-fps-power-up-slot = <0>;
228 maxim, 210 maxim,active-fps-power-down-slot = <7>;
229 }; 211 };
230 212
231 gpio3 { 213 gpio3 {
232 pins = 214 pins = "gpio3";
233 functi 215 function = "fps-out";
234 drive- 216 drive-open-drain = <1>;
235 maxim, 217 maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
236 maxim, 218 maxim,active-fps-power-up-slot = <4>;
237 maxim, 219 maxim,active-fps-power-down-slot = <3>;
238 }; 220 };
239 221
240 gpio4 { 222 gpio4 {
241 pins = 223 pins = "gpio4";
242 functi 224 function = "32k-out1";
243 }; 225 };
244 226
245 gpio5_6_7 { 227 gpio5_6_7 {
246 pins = 228 pins = "gpio5", "gpio6", "gpio7";
247 functi 229 function = "gpio";
248 drive- 230 drive-push-pull = <1>;
249 }; 231 };
250 }; 232 };
251 233
>> 234 fps {
>> 235 fps0 {
>> 236 maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>;
>> 237 maxim,suspend-fps-time-period-us = <5120>;
>> 238 };
>> 239
>> 240 fps1 {
>> 241 maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>;
>> 242 maxim,suspend-fps-time-period-us = <5120>;
>> 243 };
>> 244
>> 245 fps2 {
>> 246 maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>;
>> 247 };
>> 248 };
>> 249
252 regulators { 250 regulators {
253 in-ldo0-1-supp 251 in-ldo0-1-supply = <&vdd_pre>;
254 in-ldo2-supply 252 in-ldo2-supply = <&vdd_3v3_sys>;
255 in-ldo3-5-supp 253 in-ldo3-5-supply = <&vdd_1v8>;
256 in-ldo4-6-supp 254 in-ldo4-6-supply = <&vdd_5v0_sys>;
257 in-ldo7-8-supp 255 in-ldo7-8-supply = <&vdd_pre>;
258 in-sd0-supply 256 in-sd0-supply = <&vdd_5v0_sys>;
259 in-sd1-supply 257 in-sd1-supply = <&vdd_5v0_sys>;
260 in-sd2-supply 258 in-sd2-supply = <&vdd_5v0_sys>;
261 in-sd3-supply 259 in-sd3-supply = <&vdd_5v0_sys>;
262 260
263 vdd_soc: sd0 { 261 vdd_soc: sd0 {
264 regula 262 regulator-name = "VDD_SOC";
265 regula 263 regulator-min-microvolt = <1000000>;
266 regula 264 regulator-max-microvolt = <1170000>;
267 regula 265 regulator-enable-ramp-delay = <146>;
268 regula 266 regulator-ramp-delay = <27500>;
269 regula 267 regulator-ramp-delay-scale = <300>;
270 regula 268 regulator-always-on;
271 regula 269 regulator-boot-on;
272 270
273 maxim, 271 maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
274 maxim, 272 maxim,active-fps-power-up-slot = <1>;
275 maxim, 273 maxim,active-fps-power-down-slot = <6>;
276 }; 274 };
277 275
278 vdd_ddr: sd1 { 276 vdd_ddr: sd1 {
279 regula 277 regulator-name = "VDD_DDR_1V1_PMIC";
280 regula 278 regulator-min-microvolt = <1150000>;
281 regula 279 regulator-max-microvolt = <1150000>;
282 regula 280 regulator-enable-ramp-delay = <176>;
283 regula 281 regulator-ramp-delay = <27500>;
284 regula 282 regulator-ramp-delay-scale = <300>;
285 regula 283 regulator-always-on;
286 regula 284 regulator-boot-on;
287 285
288 maxim, 286 maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
289 maxim, 287 maxim,active-fps-power-up-slot = <5>;
290 maxim, 288 maxim,active-fps-power-down-slot = <2>;
291 }; 289 };
292 290
293 vdd_pre: sd2 { 291 vdd_pre: sd2 {
294 regula 292 regulator-name = "VDD_PRE_REG_1V35";
295 regula 293 regulator-min-microvolt = <1350000>;
296 regula 294 regulator-max-microvolt = <1350000>;
297 regula 295 regulator-enable-ramp-delay = <176>;
298 regula 296 regulator-ramp-delay = <27500>;
299 regula 297 regulator-ramp-delay-scale = <350>;
300 regula 298 regulator-always-on;
301 regula 299 regulator-boot-on;
302 300
303 maxim, 301 maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
304 maxim, 302 maxim,active-fps-power-up-slot = <2>;
305 maxim, 303 maxim,active-fps-power-down-slot = <5>;
306 }; 304 };
307 305
308 vdd_1v8: sd3 { 306 vdd_1v8: sd3 {
309 regula 307 regulator-name = "VDD_1V8";
310 regula 308 regulator-min-microvolt = <1800000>;
311 regula 309 regulator-max-microvolt = <1800000>;
312 regula 310 regulator-enable-ramp-delay = <242>;
313 regula 311 regulator-ramp-delay = <27500>;
314 regula 312 regulator-ramp-delay-scale = <360>;
315 regula 313 regulator-always-on;
316 regula 314 regulator-boot-on;
317 315
318 maxim, 316 maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
319 maxim, 317 maxim,active-fps-power-up-slot = <3>;
320 maxim, 318 maxim,active-fps-power-down-slot = <4>;
321 }; 319 };
322 320
323 vdd_sys_1v2: l 321 vdd_sys_1v2: ldo0 {
324 regula 322 regulator-name = "AVDD_SYS_1V2";
325 regula 323 regulator-min-microvolt = <1200000>;
326 regula 324 regulator-max-microvolt = <1200000>;
327 regula 325 regulator-enable-ramp-delay = <26>;
328 regula 326 regulator-ramp-delay = <100000>;
329 regula 327 regulator-ramp-delay-scale = <200>;
330 regula 328 regulator-always-on;
331 regula 329 regulator-boot-on;
332 330
333 maxim, 331 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
334 maxim, 332 maxim,active-fps-power-up-slot = <0>;
335 maxim, 333 maxim,active-fps-power-down-slot = <7>;
336 }; 334 };
337 335
338 vdd_pex_1v05: 336 vdd_pex_1v05: ldo1 {
339 regula 337 regulator-name = "VDD_PEX_1V05";
340 regula 338 regulator-min-microvolt = <1050000>;
341 regula 339 regulator-max-microvolt = <1050000>;
342 regula 340 regulator-enable-ramp-delay = <22>;
343 regula 341 regulator-ramp-delay = <100000>;
344 regula 342 regulator-ramp-delay-scale = <200>;
345 343
346 maxim, 344 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
347 maxim, 345 maxim,active-fps-power-up-slot = <0>;
348 maxim, 346 maxim,active-fps-power-down-slot = <7>;
349 }; 347 };
350 348
351 vddio_sdmmc: l 349 vddio_sdmmc: ldo2 {
352 regula 350 regulator-name = "VDDIO_SDMMC";
353 regula 351 regulator-min-microvolt = <1800000>;
354 regula 352 regulator-max-microvolt = <3300000>;
355 regula 353 regulator-enable-ramp-delay = <62>;
356 regula 354 regulator-ramp-delay = <100000>;
357 regula 355 regulator-ramp-delay-scale = <200>;
358 356
359 maxim, 357 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
360 maxim, 358 maxim,active-fps-power-up-slot = <0>;
361 maxim, 359 maxim,active-fps-power-down-slot = <7>;
362 }; 360 };
363 361
364 ldo3 { 362 ldo3 {
365 status 363 status = "disabled";
366 }; 364 };
367 365
368 vdd_rtc: ldo4 366 vdd_rtc: ldo4 {
369 regula 367 regulator-name = "VDD_RTC";
370 regula 368 regulator-min-microvolt = <850000>;
371 regula 369 regulator-max-microvolt = <1100000>;
372 regula 370 regulator-enable-ramp-delay = <22>;
373 regula 371 regulator-ramp-delay = <100000>;
374 regula 372 regulator-ramp-delay-scale = <200>;
375 regula 373 regulator-disable-active-discharge;
376 regula 374 regulator-always-on;
377 regula 375 regulator-boot-on;
378 376
379 maxim, 377 maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
380 maxim, 378 maxim,active-fps-power-up-slot = <1>;
381 maxim, 379 maxim,active-fps-power-down-slot = <6>;
382 }; 380 };
383 381
384 ldo5 { 382 ldo5 {
385 status 383 status = "disabled";
386 }; 384 };
387 385
388 ldo6 { 386 ldo6 {
389 status 387 status = "disabled";
390 }; 388 };
391 389
392 avdd_1v05_pll: 390 avdd_1v05_pll: ldo7 {
393 regula 391 regulator-name = "AVDD_1V05_PLL";
394 regula 392 regulator-min-microvolt = <1050000>;
395 regula 393 regulator-max-microvolt = <1050000>;
396 regula 394 regulator-enable-ramp-delay = <24>;
397 regula 395 regulator-ramp-delay = <100000>;
398 regula 396 regulator-ramp-delay-scale = <200>;
399 397
400 maxim, 398 maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
401 maxim, 399 maxim,active-fps-power-up-slot = <3>;
402 maxim, 400 maxim,active-fps-power-down-slot = <4>;
403 }; 401 };
404 402
405 avdd_1v05: ldo 403 avdd_1v05: ldo8 {
406 regula 404 regulator-name = "AVDD_SATA_HDMI_DP_1V05";
407 regula 405 regulator-min-microvolt = <1050000>;
408 regula 406 regulator-max-microvolt = <1050000>;
409 regula 407 regulator-enable-ramp-delay = <22>;
410 regula 408 regulator-ramp-delay = <100000>;
411 regula 409 regulator-ramp-delay-scale = <200>;
412 410
413 maxim, 411 maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
414 maxim, 412 maxim,active-fps-power-up-slot = <6>;
415 maxim, 413 maxim,active-fps-power-down-slot = <1>;
416 }; 414 };
417 }; 415 };
418 }; 416 };
419 }; 417 };
420 418
421 pmc@7000e400 { 419 pmc@7000e400 {
422 nvidia,invert-interrupt; 420 nvidia,invert-interrupt;
423 nvidia,suspend-mode = <0>; 421 nvidia,suspend-mode = <0>;
424 nvidia,cpu-pwr-good-time = <0> 422 nvidia,cpu-pwr-good-time = <0>;
425 nvidia,cpu-pwr-off-time = <0>; 423 nvidia,cpu-pwr-off-time = <0>;
426 nvidia,core-pwr-good-time = <4 424 nvidia,core-pwr-good-time = <4587 3876>;
427 nvidia,core-pwr-off-time = <39 425 nvidia,core-pwr-off-time = <39065>;
428 nvidia,core-power-req-active-h 426 nvidia,core-power-req-active-high;
429 nvidia,sys-clock-req-active-hi 427 nvidia,sys-clock-req-active-high;
430 }; 428 };
431 429
432 hda@70030000 { 430 hda@70030000 {
433 nvidia,model = "NVIDIA Jetson 431 nvidia,model = "NVIDIA Jetson Nano HDA";
434 432
435 status = "okay"; 433 status = "okay";
436 }; 434 };
437 435
438 usb@70090000 { 436 usb@70090000 {
439 phys = <&{/padctl@7009f000/pads 437 phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>,
440 <&{/padctl@7009f000/pads 438 <&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>,
441 <&{/padctl@7009f000/pads 439 <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>,
442 <&{/padctl@7009f000/pads 440 <&{/padctl@7009f000/pads/pcie/lanes/pcie-6}>;
443 phy-names = "usb2-0", "usb2-1" 441 phy-names = "usb2-0", "usb2-1", "usb2-2", "usb3-0";
444 442
445 avdd-usb-supply = <&vdd_3v3_sy 443 avdd-usb-supply = <&vdd_3v3_sys>;
446 dvddio-pex-supply = <&vdd_pex_ 444 dvddio-pex-supply = <&vdd_pex_1v05>;
447 hvddio-pex-supply = <&vdd_1v8> 445 hvddio-pex-supply = <&vdd_1v8>;
448 446
449 status = "okay"; 447 status = "okay";
450 }; 448 };
451 449
452 padctl@7009f000 { 450 padctl@7009f000 {
453 status = "okay"; 451 status = "okay";
454 452
455 avdd-pll-utmip-supply = <&vdd_ 453 avdd-pll-utmip-supply = <&vdd_1v8>;
456 avdd-pll-uerefe-supply = <&vdd 454 avdd-pll-uerefe-supply = <&vdd_pex_1v05>;
457 dvdd-pex-pll-supply = <&vdd_pe 455 dvdd-pex-pll-supply = <&vdd_pex_1v05>;
458 hvdd-pex-pll-e-supply = <&vdd_ 456 hvdd-pex-pll-e-supply = <&vdd_1v8>;
459 457
460 pads { 458 pads {
461 usb2 { 459 usb2 {
462 status = "okay 460 status = "okay";
463 461
464 lanes { 462 lanes {
465 micro_ 463 micro_b: usb2-0 {
466 464 nvidia,function = "xusb";
467 465 status = "okay";
468 }; 466 };
469 467
470 usb2-1 468 usb2-1 {
471 469 nvidia,function = "xusb";
472 470 status = "okay";
473 }; 471 };
474 472
475 usb2-2 473 usb2-2 {
476 474 nvidia,function = "xusb";
477 475 status = "okay";
478 }; 476 };
479 }; 477 };
480 }; 478 };
481 479
482 pcie { 480 pcie {
483 status = "okay 481 status = "okay";
484 482
485 lanes { 483 lanes {
486 pcie-0 484 pcie-0 {
487 485 nvidia,function = "pcie-x1";
488 486 status = "okay";
489 }; 487 };
490 488
491 pcie-1 489 pcie-1 {
492 490 nvidia,function = "pcie-x4";
493 491 status = "okay";
494 }; 492 };
495 493
496 pcie-2 494 pcie-2 {
497 495 nvidia,function = "pcie-x4";
498 496 status = "okay";
499 }; 497 };
500 498
501 pcie-3 499 pcie-3 {
502 500 nvidia,function = "pcie-x4";
503 501 status = "okay";
504 }; 502 };
505 503
506 pcie-4 504 pcie-4 {
507 505 nvidia,function = "pcie-x4";
508 506 status = "okay";
509 }; 507 };
510 508
511 pcie-5 509 pcie-5 {
512 510 nvidia,function = "usb3-ss";
513 511 status = "okay";
514 }; 512 };
515 513
516 pcie-6 514 pcie-6 {
517 515 nvidia,function = "usb3-ss";
518 516 status = "okay";
519 }; 517 };
520 }; 518 };
521 }; 519 };
522 }; 520 };
523 521
524 ports { 522 ports {
525 usb2-0 { 523 usb2-0 {
526 status = "okay 524 status = "okay";
527 mode = "periph 525 mode = "peripheral";
528 usb-role-switc 526 usb-role-switch;
529 527
530 vbus-supply = 528 vbus-supply = <&vdd_5v0_usb>;
531 529
532 connector { 530 connector {
533 compat 531 compatible = "gpio-usb-b-connector",
534 532 "usb-b-connector";
535 label 533 label = "micro-USB";
536 type = 534 type = "micro";
537 vbus-g 535 vbus-gpios = <&gpio TEGRA_GPIO(CC, 4)
538 536 GPIO_ACTIVE_LOW>;
539 }; 537 };
540 }; 538 };
541 539
542 usb2-1 { 540 usb2-1 {
543 status = "okay 541 status = "okay";
544 mode = "host"; 542 mode = "host";
545 }; 543 };
546 544
547 usb2-2 { 545 usb2-2 {
548 status = "okay 546 status = "okay";
549 mode = "host"; 547 mode = "host";
550 }; 548 };
551 549
552 usb3-0 { 550 usb3-0 {
553 status = "okay 551 status = "okay";
554 nvidia,usb2-co 552 nvidia,usb2-companion = <1>;
555 vbus-supply = 553 vbus-supply = <&vdd_hub_3v3>;
556 }; 554 };
557 }; 555 };
558 }; 556 };
559 557
560 mmc@700b0000 { 558 mmc@700b0000 {
561 status = "okay"; 559 status = "okay";
562 bus-width = <4>; 560 bus-width = <4>;
563 561
564 cd-gpios = <&gpio TEGRA_GPIO(Z 562 cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>;
565 disable-wp; 563 disable-wp;
566 564
567 vqmmc-supply = <&vddio_sdmmc>; 565 vqmmc-supply = <&vddio_sdmmc>;
568 vmmc-supply = <&vdd_3v3_sd>; 566 vmmc-supply = <&vdd_3v3_sd>;
569 }; 567 };
570 568
571 mmc@700b0400 { 569 mmc@700b0400 {
572 status = "okay"; 570 status = "okay";
573 bus-width = <4>; 571 bus-width = <4>;
574 572
575 vqmmc-supply = <&vdd_1v8>; 573 vqmmc-supply = <&vdd_1v8>;
576 vmmc-supply = <&vdd_3v3_sys>; 574 vmmc-supply = <&vdd_3v3_sys>;
577 575
578 non-removable; 576 non-removable;
579 cap-sdio-irq; 577 cap-sdio-irq;
580 keep-power-in-suspend; 578 keep-power-in-suspend;
581 wakeup-source; 579 wakeup-source;
582 }; 580 };
583 581
584 usb@700d0000 { 582 usb@700d0000 {
585 status = "okay"; 583 status = "okay";
586 phys = <µ_b>; 584 phys = <µ_b>;
587 phy-names = "usb2-0"; 585 phy-names = "usb2-0";
588 avddio-usb-supply = <&vdd_3v3_ 586 avddio-usb-supply = <&vdd_3v3_sys>;
589 hvdd-usb-supply = <&vdd_1v8>; 587 hvdd-usb-supply = <&vdd_1v8>;
590 }; 588 };
591 589
592 clock@70110000 { 590 clock@70110000 {
593 status = "okay"; 591 status = "okay";
594 592
595 nvidia,cf = <6>; 593 nvidia,cf = <6>;
596 nvidia,ci = <0>; 594 nvidia,ci = <0>;
597 nvidia,cg = <2>; 595 nvidia,cg = <2>;
598 nvidia,droop-ctrl = <0x00000f0 596 nvidia,droop-ctrl = <0x00000f00>;
599 nvidia,force-mode = <1>; 597 nvidia,force-mode = <1>;
600 nvidia,sample-rate = <25000>; 598 nvidia,sample-rate = <25000>;
601 599
602 nvidia,pwm-min-microvolts = <7 600 nvidia,pwm-min-microvolts = <708000>;
603 nvidia,pwm-period-nanoseconds 601 nvidia,pwm-period-nanoseconds = <2500>; /* 2.5us */
604 nvidia,pwm-to-pmic; 602 nvidia,pwm-to-pmic;
605 nvidia,pwm-tristate-microvolts 603 nvidia,pwm-tristate-microvolts = <1000000>;
606 nvidia,pwm-voltage-step-microv 604 nvidia,pwm-voltage-step-microvolts = <19200>;
607 605
608 pinctrl-names = "dvfs_pwm_enab 606 pinctrl-names = "dvfs_pwm_enable", "dvfs_pwm_disable";
609 pinctrl-0 = <&dvfs_pwm_active_ 607 pinctrl-0 = <&dvfs_pwm_active_state>;
610 pinctrl-1 = <&dvfs_pwm_inactiv 608 pinctrl-1 = <&dvfs_pwm_inactive_state>;
611 }; 609 };
612 610
613 aconnect@702c0000 { 611 aconnect@702c0000 {
614 status = "okay"; 612 status = "okay";
615 613
>> 614 dma-controller@702e2000 {
>> 615 status = "okay";
>> 616 };
>> 617
>> 618 interrupt-controller@702f9000 {
>> 619 status = "okay";
>> 620 };
>> 621
616 ahub@702d0800 { 622 ahub@702d0800 {
617 status = "okay"; 623 status = "okay";
618 624
619 admaif@702d0000 { 625 admaif@702d0000 {
620 status = "okay 626 status = "okay";
621 }; 627 };
622 628
623 i2s@702d1200 { 629 i2s@702d1200 {
624 status = "okay 630 status = "okay";
625 631
626 ports { 632 ports {
627 #addre 633 #address-cells = <1>;
628 #size- 634 #size-cells = <0>;
629 635
630 port@0 636 port@0 {
631 637 reg = <0>;
632 638
633 639 i2s3_cif_ep: endpoint {
634 640 remote-endpoint = <&xbar_i2s3_ep>;
635 641 };
636 }; 642 };
637 643
638 i2s3_p 644 i2s3_port: port@1 {
639 645 reg = <1>;
640 646
641 647 i2s3_dap_ep: endpoint {
642 648 dai-format = "i2s";
643 649 /* Placeholder for external Codec */
644 650 };
645 }; 651 };
646 }; 652 };
647 }; 653 };
648 654
649 i2s@702d1300 { 655 i2s@702d1300 {
650 status = "okay 656 status = "okay";
651 657
652 ports { 658 ports {
653 #addre 659 #address-cells = <1>;
654 #size- 660 #size-cells = <0>;
655 661
656 port@0 662 port@0 {
657 663 reg = <0>;
658 664
659 665 i2s4_cif_ep: endpoint {
660 666 remote-endpoint = <&xbar_i2s4_ep>;
661 667 };
662 }; 668 };
663 669
664 i2s4_p 670 i2s4_port: port@1 {
665 671 reg = <1>;
666 672
667 673 i2s4_dap_ep: endpoint {
668 674 dai-format = "i2s";
669 675 /* Placeholder for external Codec */
670 676 };
671 }; 677 };
672 }; 678 };
673 }; 679 };
674 680
>> 681 dmic@702d4000 {
>> 682 status = "okay";
>> 683
>> 684 ports {
>> 685 #address-cells = <1>;
>> 686 #size-cells = <0>;
>> 687
>> 688 port@0 {
>> 689 reg = <0>;
>> 690
>> 691 dmic1_cif_ep: endpoint {
>> 692 remote-endpoint = <&xbar_dmic1_ep>;
>> 693 };
>> 694 };
>> 695
>> 696 dmic1_port: port@1 {
>> 697 reg = <1>;
>> 698
>> 699 dmic1_dap_ep: endpoint {
>> 700 /* Placeholder for external Codec */
>> 701 };
>> 702 };
>> 703 };
>> 704 };
>> 705
>> 706 dmic@702d4100 {
>> 707 status = "okay";
>> 708
>> 709 ports {
>> 710 #address-cells = <1>;
>> 711 #size-cells = <0>;
>> 712
>> 713 port@0 {
>> 714 reg = <0>;
>> 715
>> 716 dmic2_cif_ep: endpoint {
>> 717 remote-endpoint = <&xbar_dmic2_ep>;
>> 718 };
>> 719 };
>> 720
>> 721 dmic2_port: port@1 {
>> 722 reg = <1>;
>> 723
>> 724 dmic2_dap_ep: endpoint {
>> 725 /* Placeholder for external Codec */
>> 726 };
>> 727 };
>> 728 };
>> 729 };
>> 730
675 sfc@702d2000 { 731 sfc@702d2000 {
676 status = "okay 732 status = "okay";
677 733
678 ports { 734 ports {
679 #addre 735 #address-cells = <1>;
680 #size- 736 #size-cells = <0>;
681 737
682 port@0 738 port@0 {
683 739 reg = <0>;
684 740
685 741 sfc1_cif_in_ep: endpoint {
686 742 remote-endpoint = <&xbar_sfc1_in_ep>;
687 743 };
688 }; 744 };
689 745
690 sfc1_o 746 sfc1_out_port: port@1 {
691 747 reg = <1>;
692 748
693 749 sfc1_cif_out_ep: endpoint {
694 750 remote-endpoint = <&xbar_sfc1_out_ep>;
695 751 };
696 }; 752 };
697 }; 753 };
698 }; 754 };
699 755
700 sfc@702d2200 { 756 sfc@702d2200 {
701 status = "okay 757 status = "okay";
702 758
703 ports { 759 ports {
704 #addre 760 #address-cells = <1>;
705 #size- 761 #size-cells = <0>;
706 762
707 port@0 763 port@0 {
708 764 reg = <0>;
709 765
710 766 sfc2_cif_in_ep: endpoint {
711 767 remote-endpoint = <&xbar_sfc2_in_ep>;
712 768 };
713 }; 769 };
714 770
715 sfc2_o 771 sfc2_out_port: port@1 {
716 772 reg = <1>;
717 773
718 774 sfc2_cif_out_ep: endpoint {
719 775 remote-endpoint = <&xbar_sfc2_out_ep>;
720 776 };
721 }; 777 };
722 }; 778 };
723 }; 779 };
724 780
725 sfc@702d2400 { 781 sfc@702d2400 {
726 status = "okay 782 status = "okay";
727 783
728 ports { 784 ports {
729 #addre 785 #address-cells = <1>;
730 #size- 786 #size-cells = <0>;
731 787
732 port@0 788 port@0 {
733 789 reg = <0>;
734 790
735 791 sfc3_cif_in_ep: endpoint {
736 792 remote-endpoint = <&xbar_sfc3_in_ep>;
737 793 };
738 }; 794 };
739 795
740 sfc3_o 796 sfc3_out_port: port@1 {
741 797 reg = <1>;
742 798
743 799 sfc3_cif_out_ep: endpoint {
744 800 remote-endpoint = <&xbar_sfc3_out_ep>;
745 801 };
746 }; 802 };
747 }; 803 };
748 }; 804 };
749 805
750 sfc@702d2600 { 806 sfc@702d2600 {
751 status = "okay 807 status = "okay";
752 808
753 ports { 809 ports {
754 #addre 810 #address-cells = <1>;
755 #size- 811 #size-cells = <0>;
756 812
757 port@0 813 port@0 {
758 814 reg = <0>;
759 815
760 816 sfc4_cif_in_ep: endpoint {
761 817 remote-endpoint = <&xbar_sfc4_in_ep>;
762 818 };
763 }; 819 };
764 820
765 sfc4_o 821 sfc4_out_port: port@1 {
766 822 reg = <1>;
767 823
768 824 sfc4_cif_out_ep: endpoint {
769 825 remote-endpoint = <&xbar_sfc4_out_ep>;
770 826 };
771 }; 827 };
772 }; 828 };
773 }; 829 };
774 830
>> 831 mvc@702da000 {
>> 832 status = "okay";
>> 833
>> 834 ports {
>> 835 #address-cells = <1>;
>> 836 #size-cells = <0>;
>> 837
>> 838 port@0 {
>> 839 reg = <0>;
>> 840
>> 841 mvc1_cif_in_ep: endpoint {
>> 842 remote-endpoint = <&xbar_mvc1_in_ep>;
>> 843 };
>> 844 };
>> 845
>> 846 mvc1_out_port: port@1 {
>> 847 reg = <1>;
>> 848
>> 849 mvc1_cif_out_ep: endpoint {
>> 850 remote-endpoint = <&xbar_mvc1_out_ep>;
>> 851 };
>> 852 };
>> 853 };
>> 854 };
>> 855
>> 856 mvc@702da200 {
>> 857 status = "okay";
>> 858
>> 859 ports {
>> 860 #address-cells = <1>;
>> 861 #size-cells = <0>;
>> 862
>> 863 port@0 {
>> 864 reg = <0>;
>> 865
>> 866 mvc2_cif_in_ep: endpoint {
>> 867 remote-endpoint = <&xbar_mvc2_in_ep>;
>> 868 };
>> 869 };
>> 870
>> 871 mvc2_out_port: port@1 {
>> 872 reg = <1>;
>> 873
>> 874 mvc2_cif_out_ep: endpoint {
>> 875 remote-endpoint = <&xbar_mvc2_out_ep>;
>> 876 };
>> 877 };
>> 878 };
>> 879 };
>> 880
775 amx@702d3000 { 881 amx@702d3000 {
776 status = "okay 882 status = "okay";
777 883
778 ports { 884 ports {
779 #addre 885 #address-cells = <1>;
780 #size- 886 #size-cells = <0>;
781 887
782 port@0 888 port@0 {
783 889 reg = <0>;
784 890
785 891 amx1_in1_ep: endpoint {
786 892 remote-endpoint = <&xbar_amx1_in1_ep>;
787 893 };
788 }; 894 };
789 895
790 port@1 896 port@1 {
791 897 reg = <1>;
792 898
793 899 amx1_in2_ep: endpoint {
794 900 remote-endpoint = <&xbar_amx1_in2_ep>;
795 901 };
796 }; 902 };
797 903
798 port@2 904 port@2 {
799 905 reg = <2>;
800 906
801 907 amx1_in3_ep: endpoint {
802 908 remote-endpoint = <&xbar_amx1_in3_ep>;
803 909 };
804 }; 910 };
805 911
806 port@3 912 port@3 {
807 913 reg = <3>;
808 914
809 915 amx1_in4_ep: endpoint {
810 916 remote-endpoint = <&xbar_amx1_in4_ep>;
811 917 };
812 }; 918 };
813 919
814 amx1_o 920 amx1_out_port: port@4 {
815 921 reg = <4>;
816 922
817 923 amx1_out_ep: endpoint {
818 924 remote-endpoint = <&xbar_amx1_out_ep>;
819 925 };
820 }; 926 };
821 }; 927 };
822 }; 928 };
823 929
824 amx@702d3100 { 930 amx@702d3100 {
825 status = "okay 931 status = "okay";
826 932
827 ports { 933 ports {
828 #addre 934 #address-cells = <1>;
829 #size- 935 #size-cells = <0>;
830 936
831 port@0 937 port@0 {
832 938 reg = <0>;
833 939
834 940 amx2_in1_ep: endpoint {
835 941 remote-endpoint = <&xbar_amx2_in1_ep>;
836 942 };
837 }; 943 };
838 944
839 port@1 945 port@1 {
840 946 reg = <1>;
841 947
842 948 amx2_in2_ep: endpoint {
843 949 remote-endpoint = <&xbar_amx2_in2_ep>;
844 950 };
845 }; 951 };
846 952
847 amx2_i 953 amx2_in3_port: port@2 {
848 954 reg = <2>;
849 955
850 956 amx2_in3_ep: endpoint {
851 957 remote-endpoint = <&xbar_amx2_in3_ep>;
852 958 };
853 }; 959 };
854 960
855 amx2_i 961 amx2_in4_port: port@3 {
856 962 reg = <3>;
857 963
858 964 amx2_in4_ep: endpoint {
859 965 remote-endpoint = <&xbar_amx2_in4_ep>;
860 966 };
861 }; 967 };
862 968
863 amx2_o 969 amx2_out_port: port@4 {
864 970 reg = <4>;
865 971
866 972 amx2_out_ep: endpoint {
867 973 remote-endpoint = <&xbar_amx2_out_ep>;
868 974 };
869 }; 975 };
870 }; 976 };
871 }; 977 };
872 978
873 adx@702d3800 { 979 adx@702d3800 {
874 status = "okay 980 status = "okay";
875 981
876 ports { 982 ports {
877 #addre 983 #address-cells = <1>;
878 #size- 984 #size-cells = <0>;
879 985
880 port@0 986 port@0 {
881 987 reg = <0>;
882 988
883 989 adx1_in_ep: endpoint {
884 990 remote-endpoint = <&xbar_adx1_in_ep>;
885 991 };
886 }; 992 };
887 993
888 adx1_o 994 adx1_out1_port: port@1 {
889 995 reg = <1>;
890 996
891 997 adx1_out1_ep: endpoint {
892 998 remote-endpoint = <&xbar_adx1_out1_ep>;
893 999 };
894 }; 1000 };
895 1001
896 adx1_o 1002 adx1_out2_port: port@2 {
897 1003 reg = <2>;
898 1004
899 1005 adx1_out2_ep: endpoint {
900 1006 remote-endpoint = <&xbar_adx1_out2_ep>;
901 1007 };
902 }; 1008 };
903 1009
904 adx1_o 1010 adx1_out3_port: port@3 {
905 1011 reg = <3>;
906 1012
907 1013 adx1_out3_ep: endpoint {
908 1014 remote-endpoint = <&xbar_adx1_out3_ep>;
909 1015 };
910 }; 1016 };
911 1017
912 adx1_o 1018 adx1_out4_port: port@4 {
913 1019 reg = <4>;
914 1020
915 1021 adx1_out4_ep: endpoint {
916 1022 remote-endpoint = <&xbar_adx1_out4_ep>;
917 1023 };
918 }; 1024 };
919 }; 1025 };
920 }; 1026 };
921 1027
922 adx@702d3900 { 1028 adx@702d3900 {
923 status = "okay 1029 status = "okay";
924 1030
925 ports { 1031 ports {
926 #addre 1032 #address-cells = <1>;
927 #size- 1033 #size-cells = <0>;
928 1034
929 port@0 1035 port@0 {
930 1036 reg = <0>;
931 1037
932 1038 adx2_in_ep: endpoint {
933 1039 remote-endpoint = <&xbar_adx2_in_ep>;
934 1040 };
935 }; 1041 };
936 1042
937 adx2_o 1043 adx2_out1_port: port@1 {
938 1044 reg = <1>;
939 1045
940 1046 adx2_out1_ep: endpoint {
941 1047 remote-endpoint = <&xbar_adx2_out1_ep>;
942 1048 };
943 }; 1049 };
944 1050
945 adx2_o 1051 adx2_out2_port: port@2 {
946 1052 reg = <2>;
947 1053
948 1054 adx2_out2_ep: endpoint {
949 1055 remote-endpoint = <&xbar_adx2_out2_ep>;
950 1056 };
951 }; 1057 };
952 1058
953 adx2_o 1059 adx2_out3_port: port@3 {
954 1060 reg = <3>;
955 1061
956 1062 adx2_out3_ep: endpoint {
957 1063 remote-endpoint = <&xbar_adx2_out3_ep>;
958 1064 };
959 }; 1065 };
960 1066
961 adx2_o 1067 adx2_out4_port: port@4 {
962 1068 reg = <4>;
963 1069
964 1070 adx2_out4_ep: endpoint {
965 1071 remote-endpoint = <&xbar_adx2_out4_ep>;
966 1072 };
967 }; 1073 };
968 }; 1074 };
969 }; 1075 };
970 1076
971 dmic@702d4000 { <<
972 status = "okay <<
973 <<
974 ports { <<
975 #addre <<
976 #size- <<
977 <<
978 port@0 <<
979 <<
980 <<
981 <<
982 <<
983 <<
984 }; <<
985 <<
986 dmic1_ <<
987 <<
988 <<
989 <<
990 <<
991 <<
992 }; <<
993 }; <<
994 }; <<
995 <<
996 dmic@702d4100 { <<
997 status = "okay <<
998 <<
999 ports { <<
1000 #addr <<
1001 #size <<
1002 <<
1003 port@ <<
1004 <<
1005 <<
1006 <<
1007 <<
1008 <<
1009 }; <<
1010 <<
1011 dmic2 <<
1012 <<
1013 <<
1014 <<
1015 <<
1016 <<
1017 }; <<
1018 }; <<
1019 }; <<
1020 <<
1021 processing-engine@702 <<
1022 status = "oka <<
1023 <<
1024 ports { <<
1025 #addr <<
1026 #size <<
1027 <<
1028 port@ <<
1029 <<
1030 <<
1031 <<
1032 <<
1033 <<
1034 }; <<
1035 <<
1036 ope1_ <<
1037 <<
1038 <<
1039 <<
1040 <<
1041 <<
1042 }; <<
1043 }; <<
1044 }; <<
1045 <<
1046 processing-engine@702 <<
1047 status = "oka <<
1048 <<
1049 ports { <<
1050 #addr <<
1051 #size <<
1052 <<
1053 port@ <<
1054 <<
1055 <<
1056 <<
1057 <<
1058 <<
1059 }; <<
1060 <<
1061 ope2_ <<
1062 <<
1063 <<
1064 <<
1065 <<
1066 <<
1067 }; <<
1068 }; <<
1069 }; <<
1070 <<
1071 mvc@702da000 { <<
1072 status = "oka <<
1073 <<
1074 ports { <<
1075 #addr <<
1076 #size <<
1077 <<
1078 port@ <<
1079 <<
1080 <<
1081 <<
1082 <<
1083 <<
1084 }; <<
1085 <<
1086 mvc1_ <<
1087 <<
1088 <<
1089 <<
1090 <<
1091 <<
1092 }; <<
1093 }; <<
1094 }; <<
1095 <<
1096 mvc@702da200 { <<
1097 status = "oka <<
1098 <<
1099 ports { <<
1100 #addr <<
1101 #size <<
1102 <<
1103 port@ <<
1104 <<
1105 <<
1106 <<
1107 <<
1108 <<
1109 }; <<
1110 <<
1111 mvc2_ <<
1112 <<
1113 <<
1114 <<
1115 <<
1116 <<
1117 }; <<
1118 }; <<
1119 }; <<
1120 <<
1121 amixer@702dbb00 { 1077 amixer@702dbb00 {
1122 status = "oka 1078 status = "okay";
1123 1079
1124 ports { 1080 ports {
1125 #addr 1081 #address-cells = <1>;
1126 #size 1082 #size-cells = <0>;
1127 1083
1128 port@ 1084 port@0 {
1129 1085 reg = <0x0>;
1130 1086
1131 1087 mixer_in1_ep: endpoint {
1132 1088 remote-endpoint = <&xbar_mixer_in1_ep>;
1133 1089 };
1134 }; 1090 };
1135 1091
1136 port@ 1092 port@1 {
1137 1093 reg = <0x1>;
1138 1094
1139 1095 mixer_in2_ep: endpoint {
1140 1096 remote-endpoint = <&xbar_mixer_in2_ep>;
1141 1097 };
1142 }; 1098 };
1143 1099
1144 port@ 1100 port@2 {
1145 1101 reg = <0x2>;
1146 1102
1147 1103 mixer_in3_ep: endpoint {
1148 1104 remote-endpoint = <&xbar_mixer_in3_ep>;
1149 1105 };
1150 }; 1106 };
1151 1107
1152 port@ 1108 port@3 {
1153 1109 reg = <0x3>;
1154 1110
1155 1111 mixer_in4_ep: endpoint {
1156 1112 remote-endpoint = <&xbar_mixer_in4_ep>;
1157 1113 };
1158 }; 1114 };
1159 1115
1160 port@ 1116 port@4 {
1161 1117 reg = <0x4>;
1162 1118
1163 1119 mixer_in5_ep: endpoint {
1164 1120 remote-endpoint = <&xbar_mixer_in5_ep>;
1165 1121 };
1166 }; 1122 };
1167 1123
1168 port@ 1124 port@5 {
1169 1125 reg = <0x5>;
1170 1126
1171 1127 mixer_in6_ep: endpoint {
1172 1128 remote-endpoint = <&xbar_mixer_in6_ep>;
1173 1129 };
1174 }; 1130 };
1175 1131
1176 port@ 1132 port@6 {
1177 1133 reg = <0x6>;
1178 1134
1179 1135 mixer_in7_ep: endpoint {
1180 1136 remote-endpoint = <&xbar_mixer_in7_ep>;
1181 1137 };
1182 }; 1138 };
1183 1139
1184 port@ 1140 port@7 {
1185 1141 reg = <0x7>;
1186 1142
1187 1143 mixer_in8_ep: endpoint {
1188 1144 remote-endpoint = <&xbar_mixer_in8_ep>;
1189 1145 };
1190 }; 1146 };
1191 1147
1192 port@ 1148 port@8 {
1193 1149 reg = <0x8>;
1194 1150
1195 1151 mixer_in9_ep: endpoint {
1196 1152 remote-endpoint = <&xbar_mixer_in9_ep>;
1197 1153 };
1198 }; 1154 };
1199 1155
1200 port@ 1156 port@9 {
1201 1157 reg = <0x9>;
1202 1158
1203 1159 mixer_in10_ep: endpoint {
1204 1160 remote-endpoint = <&xbar_mixer_in10_ep>;
1205 1161 };
1206 }; 1162 };
1207 1163
1208 mixer 1164 mixer_out1_port: port@a {
1209 1165 reg = <0xa>;
1210 1166
1211 1167 mixer_out1_ep: endpoint {
1212 1168 remote-endpoint = <&xbar_mixer_out1_ep>;
1213 1169 };
1214 }; 1170 };
1215 1171
1216 mixer 1172 mixer_out2_port: port@b {
1217 1173 reg = <0xb>;
1218 1174
1219 1175 mixer_out2_ep: endpoint {
1220 1176 remote-endpoint = <&xbar_mixer_out2_ep>;
1221 1177 };
1222 }; 1178 };
1223 1179
1224 mixer 1180 mixer_out3_port: port@c {
1225 1181 reg = <0xc>;
1226 1182
1227 1183 mixer_out3_ep: endpoint {
1228 1184 remote-endpoint = <&xbar_mixer_out3_ep>;
1229 1185 };
1230 }; 1186 };
1231 1187
1232 mixer 1188 mixer_out4_port: port@d {
1233 1189 reg = <0xd>;
1234 1190
1235 1191 mixer_out4_ep: endpoint {
1236 1192 remote-endpoint = <&xbar_mixer_out4_ep>;
1237 1193 };
1238 }; 1194 };
1239 1195
1240 mixer 1196 mixer_out5_port: port@e {
1241 1197 reg = <0xe>;
1242 1198
1243 1199 mixer_out5_ep: endpoint {
1244 1200 remote-endpoint = <&xbar_mixer_out5_ep>;
1245 1201 };
1246 }; 1202 };
1247 }; 1203 };
1248 }; 1204 };
1249 1205
1250 ports { 1206 ports {
1251 xbar_i2s3_por 1207 xbar_i2s3_port: port@c {
1252 reg = 1208 reg = <0xc>;
1253 1209
1254 xbar_ 1210 xbar_i2s3_ep: endpoint {
1255 1211 remote-endpoint = <&i2s3_cif_ep>;
1256 }; 1212 };
1257 }; 1213 };
1258 1214
1259 xbar_i2s4_por 1215 xbar_i2s4_port: port@d {
1260 reg = 1216 reg = <0xd>;
1261 1217
1262 xbar_ 1218 xbar_i2s4_ep: endpoint {
1263 1219 remote-endpoint = <&i2s4_cif_ep>;
1264 }; 1220 };
1265 }; 1221 };
1266 1222
1267 xbar_dmic1_po 1223 xbar_dmic1_port: port@f {
1268 reg = 1224 reg = <0xf>;
1269 1225
1270 xbar_ 1226 xbar_dmic1_ep: endpoint {
1271 1227 remote-endpoint = <&dmic1_cif_ep>;
1272 }; 1228 };
1273 }; 1229 };
1274 1230
1275 xbar_dmic2_po 1231 xbar_dmic2_port: port@10 {
1276 reg = 1232 reg = <0x10>;
1277 1233
1278 xbar_ 1234 xbar_dmic2_ep: endpoint {
1279 1235 remote-endpoint = <&dmic2_cif_ep>;
1280 }; 1236 };
1281 }; 1237 };
1282 1238
1283 xbar_sfc1_in_ 1239 xbar_sfc1_in_port: port@12 {
1284 reg = 1240 reg = <0x12>;
1285 1241
1286 xbar_ 1242 xbar_sfc1_in_ep: endpoint {
1287 1243 remote-endpoint = <&sfc1_cif_in_ep>;
1288 }; 1244 };
1289 }; 1245 };
1290 1246
1291 port@13 { 1247 port@13 {
1292 reg = 1248 reg = <0x13>;
1293 1249
1294 xbar_ 1250 xbar_sfc1_out_ep: endpoint {
1295 1251 remote-endpoint = <&sfc1_cif_out_ep>;
1296 }; 1252 };
1297 }; 1253 };
1298 1254
1299 xbar_sfc2_in_ 1255 xbar_sfc2_in_port: port@14 {
1300 reg = 1256 reg = <0x14>;
1301 1257
1302 xbar_ 1258 xbar_sfc2_in_ep: endpoint {
1303 1259 remote-endpoint = <&sfc2_cif_in_ep>;
1304 }; 1260 };
1305 }; 1261 };
1306 1262
1307 port@15 { 1263 port@15 {
1308 reg = 1264 reg = <0x15>;
1309 1265
1310 xbar_ 1266 xbar_sfc2_out_ep: endpoint {
1311 1267 remote-endpoint = <&sfc2_cif_out_ep>;
1312 }; 1268 };
1313 }; 1269 };
1314 1270
1315 xbar_sfc3_in_ 1271 xbar_sfc3_in_port: port@16 {
1316 reg = 1272 reg = <0x16>;
1317 1273
1318 xbar_ 1274 xbar_sfc3_in_ep: endpoint {
1319 1275 remote-endpoint = <&sfc3_cif_in_ep>;
1320 }; 1276 };
1321 }; 1277 };
1322 1278
1323 port@17 { 1279 port@17 {
1324 reg = 1280 reg = <0x17>;
1325 1281
1326 xbar_ 1282 xbar_sfc3_out_ep: endpoint {
1327 1283 remote-endpoint = <&sfc3_cif_out_ep>;
1328 }; 1284 };
1329 }; 1285 };
1330 1286
1331 xbar_sfc4_in_ 1287 xbar_sfc4_in_port: port@18 {
1332 reg = 1288 reg = <0x18>;
1333 1289
1334 xbar_ 1290 xbar_sfc4_in_ep: endpoint {
1335 1291 remote-endpoint = <&sfc4_cif_in_ep>;
1336 }; 1292 };
1337 }; 1293 };
1338 1294
1339 port@19 { 1295 port@19 {
1340 reg = 1296 reg = <0x19>;
1341 1297
1342 xbar_ 1298 xbar_sfc4_out_ep: endpoint {
1343 1299 remote-endpoint = <&sfc4_cif_out_ep>;
1344 }; 1300 };
1345 }; 1301 };
1346 1302
1347 xbar_mvc1_in_ 1303 xbar_mvc1_in_port: port@1a {
1348 reg = 1304 reg = <0x1a>;
1349 1305
1350 xbar_ 1306 xbar_mvc1_in_ep: endpoint {
1351 1307 remote-endpoint = <&mvc1_cif_in_ep>;
1352 }; 1308 };
1353 }; 1309 };
1354 1310
1355 port@1b { 1311 port@1b {
1356 reg = 1312 reg = <0x1b>;
1357 1313
1358 xbar_ 1314 xbar_mvc1_out_ep: endpoint {
1359 1315 remote-endpoint = <&mvc1_cif_out_ep>;
1360 }; 1316 };
1361 }; 1317 };
1362 1318
1363 xbar_mvc2_in_ 1319 xbar_mvc2_in_port: port@1c {
1364 reg = 1320 reg = <0x1c>;
1365 1321
1366 xbar_ 1322 xbar_mvc2_in_ep: endpoint {
1367 1323 remote-endpoint = <&mvc2_cif_in_ep>;
1368 }; 1324 };
1369 }; 1325 };
1370 1326
1371 port@1d { 1327 port@1d {
1372 reg = 1328 reg = <0x1d>;
1373 1329
1374 xbar_ 1330 xbar_mvc2_out_ep: endpoint {
1375 1331 remote-endpoint = <&mvc2_cif_out_ep>;
1376 }; 1332 };
1377 }; 1333 };
1378 1334
1379 xbar_amx1_in1 1335 xbar_amx1_in1_port: port@1e {
1380 reg = 1336 reg = <0x1e>;
1381 1337
1382 xbar_ 1338 xbar_amx1_in1_ep: endpoint {
1383 1339 remote-endpoint = <&amx1_in1_ep>;
1384 }; 1340 };
1385 }; 1341 };
1386 1342
1387 xbar_amx1_in2 1343 xbar_amx1_in2_port: port@1f {
1388 reg = 1344 reg = <0x1f>;
1389 1345
1390 xbar_ 1346 xbar_amx1_in2_ep: endpoint {
1391 1347 remote-endpoint = <&amx1_in2_ep>;
1392 }; 1348 };
1393 }; 1349 };
1394 1350
1395 xbar_amx1_in3 1351 xbar_amx1_in3_port: port@20 {
1396 reg = 1352 reg = <0x20>;
1397 1353
1398 xbar_ 1354 xbar_amx1_in3_ep: endpoint {
1399 1355 remote-endpoint = <&amx1_in3_ep>;
1400 }; 1356 };
1401 }; 1357 };
1402 1358
1403 xbar_amx1_in4 1359 xbar_amx1_in4_port: port@21 {
1404 reg = 1360 reg = <0x21>;
1405 1361
1406 xbar_ 1362 xbar_amx1_in4_ep: endpoint {
1407 1363 remote-endpoint = <&amx1_in4_ep>;
1408 }; 1364 };
1409 }; 1365 };
1410 1366
1411 port@22 { 1367 port@22 {
1412 reg = 1368 reg = <0x22>;
1413 1369
1414 xbar_ 1370 xbar_amx1_out_ep: endpoint {
1415 1371 remote-endpoint = <&amx1_out_ep>;
1416 }; 1372 };
1417 }; 1373 };
1418 1374
1419 xbar_amx2_in1 1375 xbar_amx2_in1_port: port@23 {
1420 reg = 1376 reg = <0x23>;
1421 1377
1422 xbar_ 1378 xbar_amx2_in1_ep: endpoint {
1423 1379 remote-endpoint = <&amx2_in1_ep>;
1424 }; 1380 };
1425 }; 1381 };
1426 1382
1427 xbar_amx2_in2 1383 xbar_amx2_in2_port: port@24 {
1428 reg = 1384 reg = <0x24>;
1429 1385
1430 xbar_ 1386 xbar_amx2_in2_ep: endpoint {
1431 1387 remote-endpoint = <&amx2_in2_ep>;
1432 }; 1388 };
1433 }; 1389 };
1434 1390
1435 xbar_amx2_in3 1391 xbar_amx2_in3_port: port@25 {
1436 reg = 1392 reg = <0x25>;
1437 1393
1438 xbar_ 1394 xbar_amx2_in3_ep: endpoint {
1439 1395 remote-endpoint = <&amx2_in3_ep>;
1440 }; 1396 };
1441 }; 1397 };
1442 1398
1443 xbar_amx2_in4 1399 xbar_amx2_in4_port: port@26 {
1444 reg = 1400 reg = <0x26>;
1445 1401
1446 xbar_ 1402 xbar_amx2_in4_ep: endpoint {
1447 1403 remote-endpoint = <&amx2_in4_ep>;
1448 }; 1404 };
1449 }; 1405 };
1450 1406
1451 port@27 { 1407 port@27 {
1452 reg = 1408 reg = <0x27>;
1453 1409
1454 xbar_ 1410 xbar_amx2_out_ep: endpoint {
1455 1411 remote-endpoint = <&amx2_out_ep>;
1456 }; 1412 };
1457 }; 1413 };
1458 1414
1459 xbar_adx1_in_ 1415 xbar_adx1_in_port: port@28 {
1460 reg = 1416 reg = <0x28>;
1461 1417
1462 xbar_ 1418 xbar_adx1_in_ep: endpoint {
1463 1419 remote-endpoint = <&adx1_in_ep>;
1464 }; 1420 };
1465 }; 1421 };
1466 1422
1467 port@29 { 1423 port@29 {
1468 reg = 1424 reg = <0x29>;
1469 1425
1470 xbar_ 1426 xbar_adx1_out1_ep: endpoint {
1471 1427 remote-endpoint = <&adx1_out1_ep>;
1472 }; 1428 };
1473 }; 1429 };
1474 1430
1475 port@2a { 1431 port@2a {
1476 reg = 1432 reg = <0x2a>;
1477 1433
1478 xbar_ 1434 xbar_adx1_out2_ep: endpoint {
1479 1435 remote-endpoint = <&adx1_out2_ep>;
1480 }; 1436 };
1481 }; 1437 };
1482 1438
1483 port@2b { 1439 port@2b {
1484 reg = 1440 reg = <0x2b>;
1485 1441
1486 xbar_ 1442 xbar_adx1_out3_ep: endpoint {
1487 1443 remote-endpoint = <&adx1_out3_ep>;
1488 }; 1444 };
1489 }; 1445 };
1490 1446
1491 port@2c { 1447 port@2c {
1492 reg = 1448 reg = <0x2c>;
1493 1449
1494 xbar_ 1450 xbar_adx1_out4_ep: endpoint {
1495 1451 remote-endpoint = <&adx1_out4_ep>;
1496 }; 1452 };
1497 }; 1453 };
1498 1454
1499 xbar_adx2_in_ 1455 xbar_adx2_in_port: port@2d {
1500 reg = 1456 reg = <0x2d>;
1501 1457
1502 xbar_ 1458 xbar_adx2_in_ep: endpoint {
1503 1459 remote-endpoint = <&adx2_in_ep>;
1504 }; 1460 };
1505 }; 1461 };
1506 1462
1507 port@2e { 1463 port@2e {
1508 reg = 1464 reg = <0x2e>;
1509 1465
1510 xbar_ 1466 xbar_adx2_out1_ep: endpoint {
1511 1467 remote-endpoint = <&adx2_out1_ep>;
1512 }; 1468 };
1513 }; 1469 };
1514 1470
1515 port@2f { 1471 port@2f {
1516 reg = 1472 reg = <0x2f>;
1517 1473
1518 xbar_ 1474 xbar_adx2_out2_ep: endpoint {
1519 1475 remote-endpoint = <&adx2_out2_ep>;
1520 }; 1476 };
1521 }; 1477 };
1522 1478
1523 port@30 { 1479 port@30 {
1524 reg = 1480 reg = <0x30>;
1525 1481
1526 xbar_ 1482 xbar_adx2_out3_ep: endpoint {
1527 1483 remote-endpoint = <&adx2_out3_ep>;
1528 }; 1484 };
1529 }; 1485 };
1530 1486
1531 port@31 { 1487 port@31 {
1532 reg = 1488 reg = <0x31>;
1533 1489
1534 xbar_ 1490 xbar_adx2_out4_ep: endpoint {
1535 1491 remote-endpoint = <&adx2_out4_ep>;
1536 }; 1492 };
1537 }; 1493 };
1538 1494
1539 xbar_mixer_in 1495 xbar_mixer_in1_port: port@32 {
1540 reg = 1496 reg = <0x32>;
1541 1497
1542 xbar_ 1498 xbar_mixer_in1_ep: endpoint {
1543 1499 remote-endpoint = <&mixer_in1_ep>;
1544 }; 1500 };
1545 }; 1501 };
1546 1502
1547 xbar_mixer_in 1503 xbar_mixer_in2_port: port@33 {
1548 reg = 1504 reg = <0x33>;
1549 1505
1550 xbar_ 1506 xbar_mixer_in2_ep: endpoint {
1551 1507 remote-endpoint = <&mixer_in2_ep>;
1552 }; 1508 };
1553 }; 1509 };
1554 1510
1555 xbar_mixer_in 1511 xbar_mixer_in3_port: port@34 {
1556 reg = 1512 reg = <0x34>;
1557 1513
1558 xbar_ 1514 xbar_mixer_in3_ep: endpoint {
1559 1515 remote-endpoint = <&mixer_in3_ep>;
1560 }; 1516 };
1561 }; 1517 };
1562 1518
1563 xbar_mixer_in 1519 xbar_mixer_in4_port: port@35 {
1564 reg = 1520 reg = <0x35>;
1565 1521
1566 xbar_ 1522 xbar_mixer_in4_ep: endpoint {
1567 1523 remote-endpoint = <&mixer_in4_ep>;
1568 }; 1524 };
1569 }; 1525 };
1570 1526
1571 xbar_mixer_in 1527 xbar_mixer_in5_port: port@36 {
1572 reg = 1528 reg = <0x36>;
1573 1529
1574 xbar_ 1530 xbar_mixer_in5_ep: endpoint {
1575 1531 remote-endpoint = <&mixer_in5_ep>;
1576 }; 1532 };
1577 }; 1533 };
1578 1534
1579 xbar_mixer_in 1535 xbar_mixer_in6_port: port@37 {
1580 reg = 1536 reg = <0x37>;
1581 1537
1582 xbar_ 1538 xbar_mixer_in6_ep: endpoint {
1583 1539 remote-endpoint = <&mixer_in6_ep>;
1584 }; 1540 };
1585 }; 1541 };
1586 1542
1587 xbar_mixer_in 1543 xbar_mixer_in7_port: port@38 {
1588 reg = 1544 reg = <0x38>;
1589 1545
1590 xbar_ 1546 xbar_mixer_in7_ep: endpoint {
1591 1547 remote-endpoint = <&mixer_in7_ep>;
1592 }; 1548 };
1593 }; 1549 };
1594 1550
1595 xbar_mixer_in 1551 xbar_mixer_in8_port: port@39 {
1596 reg = 1552 reg = <0x39>;
1597 1553
1598 xbar_ 1554 xbar_mixer_in8_ep: endpoint {
1599 1555 remote-endpoint = <&mixer_in8_ep>;
1600 }; 1556 };
1601 }; 1557 };
1602 1558
1603 xbar_mixer_in 1559 xbar_mixer_in9_port: port@3a {
1604 reg = 1560 reg = <0x3a>;
1605 1561
1606 xbar_ 1562 xbar_mixer_in9_ep: endpoint {
1607 1563 remote-endpoint = <&mixer_in9_ep>;
1608 }; 1564 };
1609 }; 1565 };
1610 1566
1611 xbar_mixer_in 1567 xbar_mixer_in10_port: port@3b {
1612 reg = 1568 reg = <0x3b>;
1613 1569
1614 xbar_ 1570 xbar_mixer_in10_ep: endpoint {
1615 1571 remote-endpoint = <&mixer_in10_ep>;
1616 }; 1572 };
1617 }; 1573 };
1618 1574
1619 port@3c { 1575 port@3c {
1620 reg = 1576 reg = <0x3c>;
1621 1577
1622 xbar_ 1578 xbar_mixer_out1_ep: endpoint {
1623 1579 remote-endpoint = <&mixer_out1_ep>;
1624 }; 1580 };
1625 }; 1581 };
1626 1582
1627 port@3d { 1583 port@3d {
1628 reg = 1584 reg = <0x3d>;
1629 1585
1630 xbar_ 1586 xbar_mixer_out2_ep: endpoint {
1631 1587 remote-endpoint = <&mixer_out2_ep>;
1632 }; 1588 };
1633 }; 1589 };
1634 1590
1635 port@3e { 1591 port@3e {
1636 reg = 1592 reg = <0x3e>;
1637 1593
1638 xbar_ 1594 xbar_mixer_out3_ep: endpoint {
1639 1595 remote-endpoint = <&mixer_out3_ep>;
1640 }; 1596 };
1641 }; 1597 };
1642 1598
1643 port@3f { 1599 port@3f {
1644 reg = 1600 reg = <0x3f>;
1645 1601
1646 xbar_ 1602 xbar_mixer_out4_ep: endpoint {
1647 1603 remote-endpoint = <&mixer_out4_ep>;
1648 }; 1604 };
1649 }; 1605 };
1650 1606
1651 port@40 { 1607 port@40 {
1652 reg = 1608 reg = <0x40>;
1653 1609
1654 xbar_ 1610 xbar_mixer_out5_ep: endpoint {
1655 1611 remote-endpoint = <&mixer_out5_ep>;
1656 }; 1612 };
1657 }; 1613 };
1658 <<
1659 xbar_ope1_in_ <<
1660 reg = <<
1661 <<
1662 xbar_ <<
1663 <<
1664 }; <<
1665 }; <<
1666 <<
1667 port@42 { <<
1668 reg = <<
1669 <<
1670 xbar_ <<
1671 <<
1672 }; <<
1673 }; <<
1674 <<
1675 xbar_ope2_in_ <<
1676 reg = <<
1677 <<
1678 xbar_ <<
1679 <<
1680 }; <<
1681 }; <<
1682 <<
1683 port@44 { <<
1684 reg = <<
1685 <<
1686 xbar_ <<
1687 <<
1688 }; <<
1689 }; <<
1690 }; 1614 };
1691 }; 1615 };
1692 <<
1693 dma-controller@702e2000 { <<
1694 status = "okay"; <<
1695 }; <<
1696 <<
1697 interrupt-controller@702f9000 <<
1698 status = "okay"; <<
1699 }; <<
1700 }; 1616 };
1701 1617
1702 spi@70410000 { 1618 spi@70410000 {
1703 status = "okay"; 1619 status = "okay";
1704 1620
1705 flash@0 { 1621 flash@0 {
1706 compatible = "jedec,s 1622 compatible = "jedec,spi-nor";
1707 reg = <0>; 1623 reg = <0>;
1708 spi-max-frequency = < 1624 spi-max-frequency = <104000000>;
1709 spi-tx-bus-width = <2 1625 spi-tx-bus-width = <2>;
1710 spi-rx-bus-width = <2 1626 spi-rx-bus-width = <2>;
1711 }; 1627 };
1712 }; 1628 };
1713 1629
1714 clk32k_in: clock-32k { 1630 clk32k_in: clock-32k {
1715 compatible = "fixed-clock"; 1631 compatible = "fixed-clock";
1716 clock-frequency = <32768>; 1632 clock-frequency = <32768>;
1717 #clock-cells = <0>; 1633 #clock-cells = <0>;
1718 }; 1634 };
1719 1635
1720 cpus { 1636 cpus {
1721 cpu@0 { 1637 cpu@0 {
1722 enable-method = "psci 1638 enable-method = "psci";
1723 }; 1639 };
1724 1640
1725 cpu@1 { 1641 cpu@1 {
1726 enable-method = "psci 1642 enable-method = "psci";
1727 }; 1643 };
1728 1644
1729 cpu@2 { 1645 cpu@2 {
1730 enable-method = "psci 1646 enable-method = "psci";
1731 }; 1647 };
1732 1648
1733 cpu@3 { 1649 cpu@3 {
1734 enable-method = "psci 1650 enable-method = "psci";
1735 }; 1651 };
1736 1652
1737 idle-states { 1653 idle-states {
1738 cpu-sleep { 1654 cpu-sleep {
1739 status = "oka 1655 status = "okay";
1740 }; 1656 };
1741 }; 1657 };
1742 }; 1658 };
1743 1659
1744 gpio-keys { !! 1660 fan: fan {
1745 compatible = "gpio-keys"; !! 1661 compatible = "pwm-fan";
>> 1662 pwms = <&pwm 3 45334>;
1746 1663
1747 key-force-recovery { !! 1664 cooling-levels = <0 64 128 255>;
1748 label = "Force Recove !! 1665 #cooling-cells = <2>;
1749 gpios = <&gpio TEGRA_ !! 1666 };
1750 linux,input-type = <E !! 1667
1751 linux,code = <BTN_1>; !! 1668 thermal-zones {
1752 debounce-interval = < !! 1669 cpu-thermal {
>> 1670 trips {
>> 1671 cpu_trip_critical: critical {
>> 1672 temperature = <96500>;
>> 1673 hysteresis = <0>;
>> 1674 type = "critical";
>> 1675 };
>> 1676
>> 1677 cpu_trip_hot: hot {
>> 1678 temperature = <70000>;
>> 1679 hysteresis = <2000>;
>> 1680 type = "hot";
>> 1681 };
>> 1682
>> 1683 cpu_trip_active: active {
>> 1684 temperature = <50000>;
>> 1685 hysteresis = <2000>;
>> 1686 type = "active";
>> 1687 };
>> 1688
>> 1689 cpu_trip_passive: passive {
>> 1690 temperature = <30000>;
>> 1691 hysteresis = <2000>;
>> 1692 type = "passive";
>> 1693 };
>> 1694 };
>> 1695
>> 1696 cooling-maps {
>> 1697 cpu-critical {
>> 1698 cooling-device = <&fan 3 3>;
>> 1699 trip = <&cpu_trip_critical>;
>> 1700 };
>> 1701
>> 1702 cpu-hot {
>> 1703 cooling-device = <&fan 2 2>;
>> 1704 trip = <&cpu_trip_hot>;
>> 1705 };
>> 1706
>> 1707 cpu-active {
>> 1708 cooling-device = <&fan 1 1>;
>> 1709 trip = <&cpu_trip_active>;
>> 1710 };
>> 1711
>> 1712 cpu-passive {
>> 1713 cooling-device = <&fan 0 0>;
>> 1714 trip = <&cpu_trip_passive>;
>> 1715 };
>> 1716 };
1753 }; 1717 };
>> 1718 };
1754 1719
1755 key-power { !! 1720 gpio-keys {
>> 1721 compatible = "gpio-keys";
>> 1722
>> 1723 power {
1756 label = "Power"; 1724 label = "Power";
1757 gpios = <&gpio TEGRA_ 1725 gpios = <&gpio TEGRA_GPIO(X, 5) GPIO_ACTIVE_LOW>;
1758 linux,input-type = <E 1726 linux,input-type = <EV_KEY>;
1759 linux,code = <KEY_POW 1727 linux,code = <KEY_POWER>;
1760 debounce-interval = < 1728 debounce-interval = <30>;
1761 wakeup-event-action = 1729 wakeup-event-action = <EV_ACT_ASSERTED>;
1762 wakeup-source; 1730 wakeup-source;
1763 }; 1731 };
>> 1732
>> 1733 force-recovery {
>> 1734 label = "Force Recovery";
>> 1735 gpios = <&gpio TEGRA_GPIO(X, 6) GPIO_ACTIVE_LOW>;
>> 1736 linux,input-type = <EV_KEY>;
>> 1737 linux,code = <BTN_1>;
>> 1738 debounce-interval = <30>;
>> 1739 };
1764 }; 1740 };
1765 1741
1766 psci { 1742 psci {
1767 compatible = "arm,psci-1.0"; 1743 compatible = "arm,psci-1.0";
1768 method = "smc"; 1744 method = "smc";
1769 }; 1745 };
1770 1746
1771 fan: pwm-fan { <<
1772 compatible = "pwm-fan"; <<
1773 pwms = <&pwm 3 45334>; <<
1774 <<
1775 cooling-levels = <0 64 128 25 <<
1776 #cooling-cells = <2>; <<
1777 }; <<
1778 <<
1779 vdd_5v0_sys: regulator-vdd-5v0-sys { 1747 vdd_5v0_sys: regulator-vdd-5v0-sys {
1780 compatible = "regulator-fixed 1748 compatible = "regulator-fixed";
1781 1749
1782 regulator-name = "VDD_5V0_SYS 1750 regulator-name = "VDD_5V0_SYS";
1783 regulator-min-microvolt = <50 1751 regulator-min-microvolt = <5000000>;
1784 regulator-max-microvolt = <50 1752 regulator-max-microvolt = <5000000>;
1785 regulator-always-on; 1753 regulator-always-on;
1786 regulator-boot-on; 1754 regulator-boot-on;
1787 }; 1755 };
1788 1756
1789 vdd_3v3_sys: regulator-vdd-3v3-sys { 1757 vdd_3v3_sys: regulator-vdd-3v3-sys {
1790 compatible = "regulator-fixed 1758 compatible = "regulator-fixed";
1791 1759
1792 regulator-name = "VDD_3V3_SYS 1760 regulator-name = "VDD_3V3_SYS";
1793 regulator-min-microvolt = <33 1761 regulator-min-microvolt = <3300000>;
1794 regulator-max-microvolt = <33 1762 regulator-max-microvolt = <3300000>;
1795 regulator-enable-ramp-delay = 1763 regulator-enable-ramp-delay = <240>;
1796 regulator-always-on; 1764 regulator-always-on;
1797 regulator-boot-on; 1765 regulator-boot-on;
1798 1766
1799 gpio = <&pmic 3 GPIO_ACTIVE_H 1767 gpio = <&pmic 3 GPIO_ACTIVE_HIGH>;
1800 enable-active-high; 1768 enable-active-high;
1801 1769
1802 vin-supply = <&vdd_5v0_sys>; 1770 vin-supply = <&vdd_5v0_sys>;
1803 }; 1771 };
1804 1772
1805 vdd_3v3_sd: regulator-vdd-3v3-sd { 1773 vdd_3v3_sd: regulator-vdd-3v3-sd {
1806 compatible = "regulator-fixed 1774 compatible = "regulator-fixed";
1807 1775
1808 regulator-name = "VDD_3V3_SD" 1776 regulator-name = "VDD_3V3_SD";
1809 regulator-min-microvolt = <33 1777 regulator-min-microvolt = <3300000>;
1810 regulator-max-microvolt = <33 1778 regulator-max-microvolt = <3300000>;
1811 1779
1812 gpio = <&gpio TEGRA_GPIO(Z, 3 1780 gpio = <&gpio TEGRA_GPIO(Z, 3) GPIO_ACTIVE_HIGH>;
1813 enable-active-high; 1781 enable-active-high;
1814 1782
1815 vin-supply = <&vdd_3v3_sys>; 1783 vin-supply = <&vdd_3v3_sys>;
1816 }; 1784 };
1817 1785
1818 vdd_hdmi: regulator-vdd-hdmi-5v0 { 1786 vdd_hdmi: regulator-vdd-hdmi-5v0 {
1819 compatible = "regulator-fixed 1787 compatible = "regulator-fixed";
1820 1788
1821 regulator-name = "VDD_HDMI_5V 1789 regulator-name = "VDD_HDMI_5V0";
1822 regulator-min-microvolt = <50 1790 regulator-min-microvolt = <5000000>;
1823 regulator-max-microvolt = <50 1791 regulator-max-microvolt = <5000000>;
1824 1792
1825 vin-supply = <&vdd_5v0_sys>; 1793 vin-supply = <&vdd_5v0_sys>;
1826 }; 1794 };
1827 1795
1828 vdd_hub_3v3: regulator-vdd-hub-3v3 { 1796 vdd_hub_3v3: regulator-vdd-hub-3v3 {
1829 compatible = "regulator-fixed 1797 compatible = "regulator-fixed";
1830 1798
1831 regulator-name = "VDD_HUB_3V3 1799 regulator-name = "VDD_HUB_3V3";
1832 regulator-min-microvolt = <33 1800 regulator-min-microvolt = <3300000>;
1833 regulator-max-microvolt = <33 1801 regulator-max-microvolt = <3300000>;
1834 1802
1835 gpio = <&gpio TEGRA_GPIO(A, 6 1803 gpio = <&gpio TEGRA_GPIO(A, 6) GPIO_ACTIVE_HIGH>;
1836 enable-active-high; 1804 enable-active-high;
1837 1805
1838 vin-supply = <&vdd_5v0_sys>; 1806 vin-supply = <&vdd_5v0_sys>;
1839 }; 1807 };
1840 1808
1841 vdd_cpu: regulator-vdd-cpu { 1809 vdd_cpu: regulator-vdd-cpu {
1842 compatible = "regulator-fixed 1810 compatible = "regulator-fixed";
1843 1811
1844 regulator-name = "VDD_CPU"; 1812 regulator-name = "VDD_CPU";
1845 regulator-min-microvolt = <50 1813 regulator-min-microvolt = <5000000>;
1846 regulator-max-microvolt = <50 1814 regulator-max-microvolt = <5000000>;
1847 regulator-always-on; 1815 regulator-always-on;
1848 regulator-boot-on; 1816 regulator-boot-on;
1849 1817
1850 gpio = <&pmic 5 GPIO_ACTIVE_H 1818 gpio = <&pmic 5 GPIO_ACTIVE_HIGH>;
1851 enable-active-high; 1819 enable-active-high;
1852 1820
1853 vin-supply = <&vdd_5v0_sys>; 1821 vin-supply = <&vdd_5v0_sys>;
1854 }; 1822 };
1855 1823
1856 vdd_gpu: regulator-vdd-gpu { 1824 vdd_gpu: regulator-vdd-gpu {
1857 compatible = "pwm-regulator"; 1825 compatible = "pwm-regulator";
1858 pwms = <&pwm 1 8000>; 1826 pwms = <&pwm 1 8000>;
1859 1827
1860 regulator-name = "VDD_GPU"; 1828 regulator-name = "VDD_GPU";
1861 regulator-min-microvolt = <71 1829 regulator-min-microvolt = <710000>;
1862 regulator-max-microvolt = <13 1830 regulator-max-microvolt = <1320000>;
1863 regulator-ramp-delay = <80>; 1831 regulator-ramp-delay = <80>;
1864 regulator-enable-ramp-delay = 1832 regulator-enable-ramp-delay = <2000>;
1865 regulator-settling-time-us = 1833 regulator-settling-time-us = <160>;
1866 1834
1867 enable-gpios = <&pmic 6 GPIO_ 1835 enable-gpios = <&pmic 6 GPIO_ACTIVE_HIGH>;
1868 vin-supply = <&vdd_5v0_sys>; 1836 vin-supply = <&vdd_5v0_sys>;
1869 }; 1837 };
1870 1838
1871 avdd_io_edp_1v05: regulator-avdd-io-e 1839 avdd_io_edp_1v05: regulator-avdd-io-epd-1v05 {
1872 compatible = "regulator-fixed 1840 compatible = "regulator-fixed";
1873 1841
1874 regulator-name = "AVDD_IO_EDP 1842 regulator-name = "AVDD_IO_EDP_1V05";
1875 regulator-min-microvolt = <10 1843 regulator-min-microvolt = <1050000>;
1876 regulator-max-microvolt = <10 1844 regulator-max-microvolt = <1050000>;
1877 1845
1878 gpio = <&pmic 7 GPIO_ACTIVE_H 1846 gpio = <&pmic 7 GPIO_ACTIVE_HIGH>;
1879 enable-active-high; 1847 enable-active-high;
1880 1848
1881 vin-supply = <&avdd_1v05_pll> 1849 vin-supply = <&avdd_1v05_pll>;
1882 }; 1850 };
1883 1851
1884 vdd_5v0_usb: regulator-vdd-5v-usb { 1852 vdd_5v0_usb: regulator-vdd-5v-usb {
1885 compatible = "regulator-fixed 1853 compatible = "regulator-fixed";
1886 1854
1887 regulator-name = "VDD_5V_USB" 1855 regulator-name = "VDD_5V_USB";
1888 regulator-min-microvolt = <50 1856 regulator-min-microvolt = <50000000>;
1889 regulator-max-microvolt = <50 1857 regulator-max-microvolt = <50000000>;
1890 1858
1891 vin-supply = <&vdd_5v0_sys>; 1859 vin-supply = <&vdd_5v0_sys>;
1892 }; 1860 };
1893 1861
1894 sound { 1862 sound {
1895 compatible = "nvidia,tegra210 1863 compatible = "nvidia,tegra210-audio-graph-card";
1896 status = "okay"; 1864 status = "okay";
1897 1865
1898 dais = /* FE */ 1866 dais = /* FE */
1899 <&admaif1_port>, <&adm 1867 <&admaif1_port>, <&admaif2_port>, <&admaif3_port>,
1900 <&admaif4_port>, <&adm 1868 <&admaif4_port>, <&admaif5_port>, <&admaif6_port>,
1901 <&admaif7_port>, <&adm 1869 <&admaif7_port>, <&admaif8_port>, <&admaif9_port>,
1902 <&admaif10_port>, 1870 <&admaif10_port>,
1903 /* Router */ 1871 /* Router */
1904 <&xbar_i2s3_port>, <&x 1872 <&xbar_i2s3_port>, <&xbar_i2s4_port>,
1905 <&xbar_dmic1_port>, <& 1873 <&xbar_dmic1_port>, <&xbar_dmic2_port>,
1906 <&xbar_sfc1_in_port>, 1874 <&xbar_sfc1_in_port>, <&xbar_sfc2_in_port>,
1907 <&xbar_sfc3_in_port>, 1875 <&xbar_sfc3_in_port>, <&xbar_sfc4_in_port>,
1908 <&xbar_mvc1_in_port>, 1876 <&xbar_mvc1_in_port>, <&xbar_mvc2_in_port>,
1909 <&xbar_amx1_in1_port>, 1877 <&xbar_amx1_in1_port>, <&xbar_amx1_in2_port>,
1910 <&xbar_amx1_in3_port>, 1878 <&xbar_amx1_in3_port>, <&xbar_amx1_in4_port>,
1911 <&xbar_amx2_in1_port>, 1879 <&xbar_amx2_in1_port>, <&xbar_amx2_in2_port>,
1912 <&xbar_amx2_in3_port>, 1880 <&xbar_amx2_in3_port>, <&xbar_amx2_in4_port>,
1913 <&xbar_adx1_in_port>, 1881 <&xbar_adx1_in_port>, <&xbar_adx2_in_port>,
1914 <&xbar_mixer_in1_port> 1882 <&xbar_mixer_in1_port>, <&xbar_mixer_in2_port>,
1915 <&xbar_mixer_in3_port> 1883 <&xbar_mixer_in3_port>, <&xbar_mixer_in4_port>,
1916 <&xbar_mixer_in5_port> 1884 <&xbar_mixer_in5_port>, <&xbar_mixer_in6_port>,
1917 <&xbar_mixer_in7_port> 1885 <&xbar_mixer_in7_port>, <&xbar_mixer_in8_port>,
1918 <&xbar_mixer_in9_port> 1886 <&xbar_mixer_in9_port>, <&xbar_mixer_in10_port>,
1919 <&xbar_ope1_in_port>, <<
1920 /* HW accelerators */ 1887 /* HW accelerators */
1921 <&sfc1_out_port>, <&sf 1888 <&sfc1_out_port>, <&sfc2_out_port>,
1922 <&sfc3_out_port>, <&sf 1889 <&sfc3_out_port>, <&sfc4_out_port>,
1923 <&mvc1_out_port>, <&mv 1890 <&mvc1_out_port>, <&mvc2_out_port>,
1924 <&amx1_out_port>, <&am 1891 <&amx1_out_port>, <&amx2_out_port>,
1925 <&adx1_out1_port>, <&a 1892 <&adx1_out1_port>, <&adx1_out2_port>,
1926 <&adx1_out3_port>, <&a 1893 <&adx1_out3_port>, <&adx1_out4_port>,
1927 <&adx2_out1_port>, <&a 1894 <&adx2_out1_port>, <&adx2_out2_port>,
1928 <&adx2_out3_port>, <&a 1895 <&adx2_out3_port>, <&adx2_out4_port>,
1929 <&mixer_out1_port>, <& 1896 <&mixer_out1_port>, <&mixer_out2_port>,
1930 <&mixer_out3_port>, <& 1897 <&mixer_out3_port>, <&mixer_out4_port>,
1931 <&mixer_out5_port>, 1898 <&mixer_out5_port>,
1932 <&ope1_out_port>, <&op <<
1933 /* I/O DAP Ports */ 1899 /* I/O DAP Ports */
1934 <&i2s3_port>, <&i2s4_p 1900 <&i2s3_port>, <&i2s4_port>,
1935 <&dmic1_port>, <&dmic2 1901 <&dmic1_port>, <&dmic2_port>;
1936 1902
1937 label = "NVIDIA Jetson Nano A 1903 label = "NVIDIA Jetson Nano APE";
1938 }; <<
1939 <<
1940 thermal-zones { <<
1941 cpu-thermal { <<
1942 trips { <<
1943 cpu_trip_crit <<
1944 tempe <<
1945 hyste <<
1946 type <<
1947 }; <<
1948 <<
1949 cpu_trip_hot: <<
1950 tempe <<
1951 hyste <<
1952 type <<
1953 }; <<
1954 <<
1955 cpu_trip_acti <<
1956 tempe <<
1957 hyste <<
1958 type <<
1959 }; <<
1960 <<
1961 cpu_trip_pass <<
1962 tempe <<
1963 hyste <<
1964 type <<
1965 }; <<
1966 }; <<
1967 <<
1968 cooling-maps { <<
1969 cpu-critical <<
1970 cooli <<
1971 trip <<
1972 }; <<
1973 <<
1974 cpu-hot { <<
1975 cooli <<
1976 trip <<
1977 }; <<
1978 <<
1979 cpu-active { <<
1980 cooli <<
1981 trip <<
1982 }; <<
1983 <<
1984 cpu-passive { <<
1985 cooli <<
1986 trip <<
1987 }; <<
1988 }; <<
1989 }; <<
1990 }; 1904 };
1991 }; 1905 };
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