1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/; 2 /dts-v1/;
3 3
4 #include <dt-bindings/input/gpio-keys.h> 4 #include <dt-bindings/input/gpio-keys.h>
5 #include <dt-bindings/input/linux-event-codes. 5 #include <dt-bindings/input/linux-event-codes.h>
6 #include <dt-bindings/mfd/max77620.h> 6 #include <dt-bindings/mfd/max77620.h>
7 7
8 #include "tegra210.dtsi" 8 #include "tegra210.dtsi"
9 9
10 / { 10 / {
11 model = "NVIDIA Jetson Nano Developer 11 model = "NVIDIA Jetson Nano Developer Kit";
12 compatible = "nvidia,p3450-0000", "nvi 12 compatible = "nvidia,p3450-0000", "nvidia,tegra210";
13 13
14 aliases { 14 aliases {
15 ethernet = "/pcie@1003000/pci@ 15 ethernet = "/pcie@1003000/pci@2,0/ethernet@0,0";
16 rtc0 = "/i2c@7000d000/pmic@3c" 16 rtc0 = "/i2c@7000d000/pmic@3c";
17 rtc1 = "/rtc@7000e000"; 17 rtc1 = "/rtc@7000e000";
18 serial0 = &uarta; 18 serial0 = &uarta;
19 }; 19 };
20 20
21 chosen { 21 chosen {
22 stdout-path = "serial0:115200n 22 stdout-path = "serial0:115200n8";
23 }; 23 };
24 24
25 memory@80000000 { !! 25 memory {
26 device_type = "memory"; 26 device_type = "memory";
27 reg = <0x0 0x80000000 0x1 0x0> 27 reg = <0x0 0x80000000 0x1 0x0>;
28 }; 28 };
29 29
30 pcie@1003000 { 30 pcie@1003000 {
31 status = "okay"; 31 status = "okay";
32 32
>> 33 avdd-pll-uerefe-supply = <&vdd_pex_1v05>;
33 hvddio-pex-supply = <&vdd_1v8> 34 hvddio-pex-supply = <&vdd_1v8>;
34 dvddio-pex-supply = <&vdd_pex_ 35 dvddio-pex-supply = <&vdd_pex_1v05>;
>> 36 dvdd-pex-pll-supply = <&vdd_pex_1v05>;
>> 37 hvdd-pex-pll-e-supply = <&vdd_1v8>;
35 vddio-pex-ctl-supply = <&vdd_1 38 vddio-pex-ctl-supply = <&vdd_1v8>;
36 39
37 pci@1,0 { 40 pci@1,0 {
38 phys = <&{/padctl@7009f 41 phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>,
39 <&{/padctl@7009f 42 <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>,
40 <&{/padctl@7009f 43 <&{/padctl@7009f000/pads/pcie/lanes/pcie-3}>,
41 <&{/padctl@7009f 44 <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>;
42 phy-names = "pcie-0", 45 phy-names = "pcie-0", "pcie-1", "pcie-2", "pcie-3";
43 nvidia,num-lanes = <4> 46 nvidia,num-lanes = <4>;
44 status = "okay"; 47 status = "okay";
45 }; 48 };
46 49
47 pci@2,0 { 50 pci@2,0 {
48 phys = <&{/padctl@7009f 51 phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>;
49 phy-names = "pcie-0"; 52 phy-names = "pcie-0";
50 status = "okay"; 53 status = "okay";
51 54
52 ethernet@0,0 { 55 ethernet@0,0 {
53 reg = <0x00000 56 reg = <0x000000 0 0 0 0>;
54 local-mac-addr 57 local-mac-address = [ 00 00 00 00 00 00 ];
55 }; 58 };
56 }; 59 };
57 }; 60 };
58 61
59 host1x@50000000 { 62 host1x@50000000 {
60 dpaux@54040000 { 63 dpaux@54040000 {
61 status = "okay"; 64 status = "okay";
62 }; 65 };
63 66
64 vi@54080000 { <<
65 status = "okay"; <<
66 <<
67 avdd-dsi-csi-supply = <<
68 <<
69 csi@838 { <<
70 status = "okay <<
71 }; <<
72 }; <<
73 <<
74 sor@54540000 { <<
75 status = "okay"; <<
76 <<
77 avdd-io-hdmi-dp-supply <<
78 vdd-hdmi-dp-pll-supply <<
79 <<
80 nvidia,xbar-cfg = <2 1 <<
81 nvidia,dpaux = <&dpaux <<
82 }; <<
83 <<
84 sor@54580000 { 67 sor@54580000 {
85 status = "okay"; 68 status = "okay";
86 69
87 avdd-io-hdmi-dp-supply !! 70 avdd-io-supply = <&avdd_1v05>;
88 vdd-hdmi-dp-pll-supply !! 71 vdd-pll-supply = <&vdd_1v8>;
89 hdmi-supply = <&vdd_hd 72 hdmi-supply = <&vdd_hdmi>;
90 73
91 nvidia,ddc-i2c-bus = < 74 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
92 nvidia,hpd-gpio = <&gp 75 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(CC, 1)
93 GPI 76 GPIO_ACTIVE_LOW>;
94 nvidia,xbar-cfg = <0 1 77 nvidia,xbar-cfg = <0 1 2 3 4>;
95 }; 78 };
96 <<
97 dpaux@545c0000 { <<
98 status = "okay"; <<
99 }; <<
100 <<
101 i2c@546c0000 { <<
102 status = "okay"; <<
103 }; <<
104 }; 79 };
105 80
106 gpu@57000000 { 81 gpu@57000000 {
107 vdd-supply = <&vdd_gpu>; 82 vdd-supply = <&vdd_gpu>;
108 status = "okay"; 83 status = "okay";
109 }; 84 };
110 85
111 pinmux@700008d4 { <<
112 dvfs_pwm_active_state: pinmux- <<
113 dvfs_pwm_pbb1 { <<
114 nvidia,pins = <<
115 nvidia,tristat <<
116 }; <<
117 }; <<
118 <<
119 dvfs_pwm_inactive_state: pinmu <<
120 dvfs_pwm_pbb1 { <<
121 nvidia,pins = <<
122 nvidia,tristat <<
123 }; <<
124 }; <<
125 }; <<
126 <<
127 /* debug port */ 86 /* debug port */
128 serial@70006000 { 87 serial@70006000 {
129 /delete-property/ dmas; <<
130 /delete-property/ dma-names; <<
131 status = "okay"; 88 status = "okay";
132 }; 89 };
133 90
134 pwm@7000a000 { <<
135 status = "okay"; <<
136 }; <<
137 <<
138 i2c@7000c500 { <<
139 status = "okay"; <<
140 clock-frequency = <100000>; <<
141 <<
142 eeprom@50 { <<
143 compatible = "atmel,24 <<
144 reg = <0x50>; <<
145 <<
146 label = "module"; <<
147 vcc-supply = <&vdd_1v8 <<
148 address-width = <8>; <<
149 pagesize = <8>; <<
150 size = <256>; <<
151 read-only; <<
152 }; <<
153 <<
154 eeprom@57 { <<
155 compatible = "atmel,24 <<
156 reg = <0x57>; <<
157 <<
158 label = "system"; <<
159 vcc-supply = <&vdd_1v8 <<
160 address-width = <8>; <<
161 pagesize = <8>; <<
162 size = <256>; <<
163 read-only; <<
164 }; <<
165 }; <<
166 <<
167 hdmi_ddc: i2c@7000c700 { 91 hdmi_ddc: i2c@7000c700 {
168 status = "okay"; 92 status = "okay";
169 clock-frequency = <100000>; 93 clock-frequency = <100000>;
170 }; 94 };
171 95
172 i2c@7000d000 { 96 i2c@7000d000 {
173 status = "okay"; 97 status = "okay";
174 clock-frequency = <400000>; 98 clock-frequency = <400000>;
175 99
176 pmic: pmic@3c { 100 pmic: pmic@3c {
177 compatible = "maxim,ma 101 compatible = "maxim,max77620";
178 reg = <0x3c>; 102 reg = <0x3c>;
179 interrupt-parent = <&t !! 103 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
180 interrupts = <51 IRQ_T <<
181 104
182 #interrupt-cells = <2> 105 #interrupt-cells = <2>;
183 interrupt-controller; 106 interrupt-controller;
184 107
185 #gpio-cells = <2>; 108 #gpio-cells = <2>;
186 gpio-controller; 109 gpio-controller;
187 110
188 pinctrl-names = "defau 111 pinctrl-names = "default";
189 pinctrl-0 = <&max77620 112 pinctrl-0 = <&max77620_default>;
190 113
191 fps { <<
192 fps0 { <<
193 maxim, <<
194 maxim, <<
195 }; <<
196 <<
197 fps1 { <<
198 maxim, <<
199 maxim, <<
200 }; <<
201 <<
202 fps2 { <<
203 maxim, <<
204 }; <<
205 }; <<
206 <<
207 max77620_default: pinm 114 max77620_default: pinmux {
208 gpio0 { 115 gpio0 {
209 pins = 116 pins = "gpio0";
210 functi 117 function = "gpio";
211 }; 118 };
212 119
213 gpio1 { 120 gpio1 {
214 pins = 121 pins = "gpio1";
215 functi 122 function = "fps-out";
216 drive- 123 drive-push-pull = <1>;
217 maxim, 124 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
218 maxim, 125 maxim,active-fps-power-up-slot = <0>;
219 maxim, 126 maxim,active-fps-power-down-slot = <7>;
220 }; 127 };
221 128
222 gpio2 { 129 gpio2 {
223 pins = 130 pins = "gpio2";
224 functi 131 function = "fps-out";
225 drive- 132 drive-open-drain = <1>;
226 maxim, 133 maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
227 maxim, 134 maxim,active-fps-power-up-slot = <0>;
228 maxim, 135 maxim,active-fps-power-down-slot = <7>;
229 }; 136 };
230 137
231 gpio3 { 138 gpio3 {
232 pins = 139 pins = "gpio3";
233 functi 140 function = "fps-out";
234 drive- 141 drive-open-drain = <1>;
235 maxim, 142 maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
236 maxim, 143 maxim,active-fps-power-up-slot = <4>;
237 maxim, 144 maxim,active-fps-power-down-slot = <3>;
238 }; 145 };
239 146
240 gpio4 { 147 gpio4 {
241 pins = 148 pins = "gpio4";
242 functi 149 function = "32k-out1";
243 }; 150 };
244 151
245 gpio5_6_7 { 152 gpio5_6_7 {
246 pins = 153 pins = "gpio5", "gpio6", "gpio7";
247 functi 154 function = "gpio";
248 drive- 155 drive-push-pull = <1>;
249 }; 156 };
250 }; 157 };
251 158
>> 159 fps {
>> 160 fps0 {
>> 161 maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>;
>> 162 maxim,suspend-fps-time-period-us = <5120>;
>> 163 };
>> 164
>> 165 fps1 {
>> 166 maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>;
>> 167 maxim,suspend-fps-time-period-us = <5120>;
>> 168 };
>> 169
>> 170 fps2 {
>> 171 maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>;
>> 172 };
>> 173 };
>> 174
252 regulators { 175 regulators {
253 in-ldo0-1-supp 176 in-ldo0-1-supply = <&vdd_pre>;
254 in-ldo2-supply 177 in-ldo2-supply = <&vdd_3v3_sys>;
255 in-ldo3-5-supp 178 in-ldo3-5-supply = <&vdd_1v8>;
256 in-ldo4-6-supp 179 in-ldo4-6-supply = <&vdd_5v0_sys>;
257 in-ldo7-8-supp 180 in-ldo7-8-supply = <&vdd_pre>;
258 in-sd0-supply 181 in-sd0-supply = <&vdd_5v0_sys>;
259 in-sd1-supply 182 in-sd1-supply = <&vdd_5v0_sys>;
260 in-sd2-supply 183 in-sd2-supply = <&vdd_5v0_sys>;
261 in-sd3-supply 184 in-sd3-supply = <&vdd_5v0_sys>;
262 185
263 vdd_soc: sd0 { 186 vdd_soc: sd0 {
264 regula 187 regulator-name = "VDD_SOC";
265 regula 188 regulator-min-microvolt = <1000000>;
266 regula 189 regulator-max-microvolt = <1170000>;
267 regula 190 regulator-enable-ramp-delay = <146>;
>> 191 regulator-disable-ramp-delay = <4080>;
268 regula 192 regulator-ramp-delay = <27500>;
269 regula 193 regulator-ramp-delay-scale = <300>;
270 regula 194 regulator-always-on;
271 regula 195 regulator-boot-on;
272 196
273 maxim, 197 maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
274 maxim, 198 maxim,active-fps-power-up-slot = <1>;
275 maxim, 199 maxim,active-fps-power-down-slot = <6>;
276 }; 200 };
277 201
278 vdd_ddr: sd1 { 202 vdd_ddr: sd1 {
279 regula 203 regulator-name = "VDD_DDR_1V1_PMIC";
280 regula 204 regulator-min-microvolt = <1150000>;
281 regula 205 regulator-max-microvolt = <1150000>;
282 regula 206 regulator-enable-ramp-delay = <176>;
>> 207 regulator-disable-ramp-delay = <145800>;
283 regula 208 regulator-ramp-delay = <27500>;
284 regula 209 regulator-ramp-delay-scale = <300>;
285 regula 210 regulator-always-on;
286 regula 211 regulator-boot-on;
287 212
288 maxim, 213 maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
289 maxim, 214 maxim,active-fps-power-up-slot = <5>;
290 maxim, 215 maxim,active-fps-power-down-slot = <2>;
291 }; 216 };
292 217
293 vdd_pre: sd2 { 218 vdd_pre: sd2 {
294 regula 219 regulator-name = "VDD_PRE_REG_1V35";
295 regula 220 regulator-min-microvolt = <1350000>;
296 regula 221 regulator-max-microvolt = <1350000>;
297 regula 222 regulator-enable-ramp-delay = <176>;
>> 223 regulator-disable-ramp-delay = <32000>;
298 regula 224 regulator-ramp-delay = <27500>;
299 regula 225 regulator-ramp-delay-scale = <350>;
300 regula 226 regulator-always-on;
301 regula 227 regulator-boot-on;
302 228
303 maxim, 229 maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
304 maxim, 230 maxim,active-fps-power-up-slot = <2>;
305 maxim, 231 maxim,active-fps-power-down-slot = <5>;
306 }; 232 };
307 233
308 vdd_1v8: sd3 { 234 vdd_1v8: sd3 {
309 regula 235 regulator-name = "VDD_1V8";
310 regula 236 regulator-min-microvolt = <1800000>;
311 regula 237 regulator-max-microvolt = <1800000>;
312 regula 238 regulator-enable-ramp-delay = <242>;
>> 239 regulator-disable-ramp-delay = <118000>;
313 regula 240 regulator-ramp-delay = <27500>;
314 regula 241 regulator-ramp-delay-scale = <360>;
315 regula 242 regulator-always-on;
316 regula 243 regulator-boot-on;
317 244
318 maxim, 245 maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
319 maxim, 246 maxim,active-fps-power-up-slot = <3>;
320 maxim, 247 maxim,active-fps-power-down-slot = <4>;
321 }; 248 };
322 249
323 vdd_sys_1v2: l 250 vdd_sys_1v2: ldo0 {
324 regula 251 regulator-name = "AVDD_SYS_1V2";
325 regula 252 regulator-min-microvolt = <1200000>;
326 regula 253 regulator-max-microvolt = <1200000>;
327 regula 254 regulator-enable-ramp-delay = <26>;
>> 255 regulator-disable-ramp-delay = <626>;
328 regula 256 regulator-ramp-delay = <100000>;
329 regula 257 regulator-ramp-delay-scale = <200>;
330 regula 258 regulator-always-on;
331 regula 259 regulator-boot-on;
332 260
333 maxim, 261 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
334 maxim, 262 maxim,active-fps-power-up-slot = <0>;
335 maxim, 263 maxim,active-fps-power-down-slot = <7>;
336 }; 264 };
337 265
338 vdd_pex_1v05: 266 vdd_pex_1v05: ldo1 {
339 regula 267 regulator-name = "VDD_PEX_1V05";
340 regula 268 regulator-min-microvolt = <1050000>;
341 regula 269 regulator-max-microvolt = <1050000>;
342 regula 270 regulator-enable-ramp-delay = <22>;
>> 271 regulator-disable-ramp-delay = <650>;
343 regula 272 regulator-ramp-delay = <100000>;
344 regula 273 regulator-ramp-delay-scale = <200>;
345 274
346 maxim, 275 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
347 maxim, 276 maxim,active-fps-power-up-slot = <0>;
348 maxim, 277 maxim,active-fps-power-down-slot = <7>;
349 }; 278 };
350 279
351 vddio_sdmmc: l 280 vddio_sdmmc: ldo2 {
352 regula 281 regulator-name = "VDDIO_SDMMC";
353 regula 282 regulator-min-microvolt = <1800000>;
354 regula 283 regulator-max-microvolt = <3300000>;
355 regula 284 regulator-enable-ramp-delay = <62>;
>> 285 regulator-disable-ramp-delay = <650>;
356 regula 286 regulator-ramp-delay = <100000>;
357 regula 287 regulator-ramp-delay-scale = <200>;
358 288
359 maxim, 289 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
360 maxim, 290 maxim,active-fps-power-up-slot = <0>;
361 maxim, 291 maxim,active-fps-power-down-slot = <7>;
362 }; 292 };
363 293
364 ldo3 { 294 ldo3 {
365 status 295 status = "disabled";
366 }; 296 };
367 297
368 vdd_rtc: ldo4 298 vdd_rtc: ldo4 {
369 regula 299 regulator-name = "VDD_RTC";
370 regula 300 regulator-min-microvolt = <850000>;
371 regula 301 regulator-max-microvolt = <1100000>;
372 regula 302 regulator-enable-ramp-delay = <22>;
>> 303 regulator-disable-ramp-delay = <610>;
373 regula 304 regulator-ramp-delay = <100000>;
374 regula 305 regulator-ramp-delay-scale = <200>;
375 regula 306 regulator-disable-active-discharge;
376 regula 307 regulator-always-on;
377 regula 308 regulator-boot-on;
378 309
379 maxim, 310 maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
380 maxim, 311 maxim,active-fps-power-up-slot = <1>;
381 maxim, 312 maxim,active-fps-power-down-slot = <6>;
382 }; 313 };
383 314
384 ldo5 { 315 ldo5 {
385 status 316 status = "disabled";
386 }; 317 };
387 318
388 ldo6 { 319 ldo6 {
389 status 320 status = "disabled";
390 }; 321 };
391 322
392 avdd_1v05_pll: 323 avdd_1v05_pll: ldo7 {
393 regula 324 regulator-name = "AVDD_1V05_PLL";
394 regula 325 regulator-min-microvolt = <1050000>;
395 regula 326 regulator-max-microvolt = <1050000>;
396 regula 327 regulator-enable-ramp-delay = <24>;
>> 328 regulator-disable-ramp-delay = <2768>;
397 regula 329 regulator-ramp-delay = <100000>;
398 regula 330 regulator-ramp-delay-scale = <200>;
399 331
400 maxim, 332 maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
401 maxim, 333 maxim,active-fps-power-up-slot = <3>;
402 maxim, 334 maxim,active-fps-power-down-slot = <4>;
403 }; 335 };
404 336
405 avdd_1v05: ldo 337 avdd_1v05: ldo8 {
406 regula 338 regulator-name = "AVDD_SATA_HDMI_DP_1V05";
407 regula 339 regulator-min-microvolt = <1050000>;
408 regula 340 regulator-max-microvolt = <1050000>;
409 regula 341 regulator-enable-ramp-delay = <22>;
>> 342 regulator-disable-ramp-delay = <1160>;
410 regula 343 regulator-ramp-delay = <100000>;
411 regula 344 regulator-ramp-delay-scale = <200>;
412 345
413 maxim, 346 maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
414 maxim, 347 maxim,active-fps-power-up-slot = <6>;
415 maxim, 348 maxim,active-fps-power-down-slot = <1>;
416 }; 349 };
417 }; 350 };
418 }; 351 };
419 }; 352 };
420 353
421 pmc@7000e400 { 354 pmc@7000e400 {
422 nvidia,invert-interrupt; 355 nvidia,invert-interrupt;
423 nvidia,suspend-mode = <0>; <<
424 nvidia,cpu-pwr-good-time = <0> <<
425 nvidia,cpu-pwr-off-time = <0>; <<
426 nvidia,core-pwr-good-time = <4 <<
427 nvidia,core-pwr-off-time = <39 <<
428 nvidia,core-power-req-active-h <<
429 nvidia,sys-clock-req-active-hi <<
430 }; 356 };
431 357
432 hda@70030000 { 358 hda@70030000 {
433 nvidia,model = "NVIDIA Jetson !! 359 nvidia,model = "jetson-nano-hda";
434 360
435 status = "okay"; 361 status = "okay";
436 }; 362 };
437 363
438 usb@70090000 { 364 usb@70090000 {
439 phys = <&{/padctl@7009f000/pads 365 phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>,
440 <&{/padctl@7009f000/pads 366 <&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>,
441 <&{/padctl@7009f000/pads 367 <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>,
442 <&{/padctl@7009f000/pads 368 <&{/padctl@7009f000/pads/pcie/lanes/pcie-6}>;
443 phy-names = "usb2-0", "usb2-1" 369 phy-names = "usb2-0", "usb2-1", "usb2-2", "usb3-0";
444 370
445 avdd-usb-supply = <&vdd_3v3_sy 371 avdd-usb-supply = <&vdd_3v3_sys>;
446 dvddio-pex-supply = <&vdd_pex_ 372 dvddio-pex-supply = <&vdd_pex_1v05>;
447 hvddio-pex-supply = <&vdd_1v8> 373 hvddio-pex-supply = <&vdd_1v8>;
>> 374 /* these really belong to the XUSB pad controller */
>> 375 avdd-pll-utmip-supply = <&vdd_1v8>;
>> 376 avdd-pll-uerefe-supply = <&vdd_pex_1v05>;
>> 377 dvdd-usb-ss-pll-supply = <&vdd_pex_1v05>;
>> 378 hvdd-usb-ss-pll-e-supply = <&vdd_1v8>;
448 379
449 status = "okay"; 380 status = "okay";
450 }; 381 };
451 382
452 padctl@7009f000 { 383 padctl@7009f000 {
453 status = "okay"; 384 status = "okay";
454 385
455 avdd-pll-utmip-supply = <&vdd_ 386 avdd-pll-utmip-supply = <&vdd_1v8>;
456 avdd-pll-uerefe-supply = <&vdd 387 avdd-pll-uerefe-supply = <&vdd_pex_1v05>;
457 dvdd-pex-pll-supply = <&vdd_pe 388 dvdd-pex-pll-supply = <&vdd_pex_1v05>;
458 hvdd-pex-pll-e-supply = <&vdd_ 389 hvdd-pex-pll-e-supply = <&vdd_1v8>;
459 390
460 pads { 391 pads {
461 usb2 { 392 usb2 {
462 status = "okay 393 status = "okay";
463 394
464 lanes { 395 lanes {
465 micro_ !! 396 usb2-0 {
466 397 nvidia,function = "xusb";
467 398 status = "okay";
468 }; 399 };
469 400
470 usb2-1 401 usb2-1 {
471 402 nvidia,function = "xusb";
472 403 status = "okay";
473 }; 404 };
474 405
475 usb2-2 406 usb2-2 {
476 407 nvidia,function = "xusb";
477 408 status = "okay";
478 }; 409 };
479 }; 410 };
480 }; 411 };
481 412
482 pcie { 413 pcie {
483 status = "okay 414 status = "okay";
484 415
485 lanes { 416 lanes {
486 pcie-0 417 pcie-0 {
487 418 nvidia,function = "pcie-x1";
488 419 status = "okay";
489 }; 420 };
490 421
491 pcie-1 422 pcie-1 {
492 423 nvidia,function = "pcie-x4";
493 424 status = "okay";
494 }; 425 };
495 426
496 pcie-2 427 pcie-2 {
497 428 nvidia,function = "pcie-x4";
498 429 status = "okay";
499 }; 430 };
500 431
501 pcie-3 432 pcie-3 {
502 433 nvidia,function = "pcie-x4";
503 434 status = "okay";
504 }; 435 };
505 436
506 pcie-4 437 pcie-4 {
507 438 nvidia,function = "pcie-x4";
508 439 status = "okay";
509 }; 440 };
510 441
511 pcie-5 442 pcie-5 {
512 443 nvidia,function = "usb3-ss";
513 444 status = "okay";
514 }; 445 };
515 446
516 pcie-6 447 pcie-6 {
517 448 nvidia,function = "usb3-ss";
518 449 status = "okay";
519 }; 450 };
520 }; 451 };
521 }; 452 };
522 }; 453 };
523 454
524 ports { 455 ports {
525 usb2-0 { 456 usb2-0 {
526 status = "okay 457 status = "okay";
527 mode = "periph !! 458 mode = "otg";
528 usb-role-switc <<
529 <<
530 vbus-supply = <<
531 <<
532 connector { <<
533 compat <<
534 <<
535 label <<
536 type = <<
537 vbus-g <<
538 <<
539 }; <<
540 }; 459 };
541 460
542 usb2-1 { 461 usb2-1 {
543 status = "okay 462 status = "okay";
544 mode = "host"; 463 mode = "host";
545 }; 464 };
546 465
547 usb2-2 { 466 usb2-2 {
548 status = "okay 467 status = "okay";
549 mode = "host"; 468 mode = "host";
550 }; 469 };
551 470
552 usb3-0 { 471 usb3-0 {
553 status = "okay 472 status = "okay";
554 nvidia,usb2-co 473 nvidia,usb2-companion = <1>;
555 vbus-supply = 474 vbus-supply = <&vdd_hub_3v3>;
556 }; 475 };
557 }; 476 };
558 }; 477 };
559 478
560 mmc@700b0000 { !! 479 sdhci@700b0000 {
561 status = "okay"; 480 status = "okay";
562 bus-width = <4>; 481 bus-width = <4>;
563 482
564 cd-gpios = <&gpio TEGRA_GPIO(Z 483 cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>;
565 disable-wp; <<
566 484
567 vqmmc-supply = <&vddio_sdmmc>; 485 vqmmc-supply = <&vddio_sdmmc>;
568 vmmc-supply = <&vdd_3v3_sd>; 486 vmmc-supply = <&vdd_3v3_sd>;
569 }; 487 };
570 488
571 mmc@700b0400 { !! 489 clocks {
572 status = "okay"; !! 490 compatible = "simple-bus";
573 bus-width = <4>; !! 491 #address-cells = <1>;
574 !! 492 #size-cells = <0>;
575 vqmmc-supply = <&vdd_1v8>; <<
576 vmmc-supply = <&vdd_3v3_sys>; <<
577 <<
578 non-removable; <<
579 cap-sdio-irq; <<
580 keep-power-in-suspend; <<
581 wakeup-source; <<
582 }; <<
583 <<
584 usb@700d0000 { <<
585 status = "okay"; <<
586 phys = <µ_b>; <<
587 phy-names = "usb2-0"; <<
588 avddio-usb-supply = <&vdd_3v3_ <<
589 hvdd-usb-supply = <&vdd_1v8>; <<
590 }; <<
591 <<
592 clock@70110000 { <<
593 status = "okay"; <<
594 <<
595 nvidia,cf = <6>; <<
596 nvidia,ci = <0>; <<
597 nvidia,cg = <2>; <<
598 nvidia,droop-ctrl = <0x00000f0 <<
599 nvidia,force-mode = <1>; <<
600 nvidia,sample-rate = <25000>; <<
601 <<
602 nvidia,pwm-min-microvolts = <7 <<
603 nvidia,pwm-period-nanoseconds <<
604 nvidia,pwm-to-pmic; <<
605 nvidia,pwm-tristate-microvolts <<
606 nvidia,pwm-voltage-step-microv <<
607 <<
608 pinctrl-names = "dvfs_pwm_enab <<
609 pinctrl-0 = <&dvfs_pwm_active_ <<
610 pinctrl-1 = <&dvfs_pwm_inactiv <<
611 }; <<
612 <<
613 aconnect@702c0000 { <<
614 status = "okay"; <<
615 <<
616 ahub@702d0800 { <<
617 status = "okay"; <<
618 <<
619 admaif@702d0000 { <<
620 status = "okay <<
621 }; <<
622 <<
623 i2s@702d1200 { <<
624 status = "okay <<
625 <<
626 ports { <<
627 #addre <<
628 #size- <<
629 <<
630 port@0 <<
631 <<
632 <<
633 <<
634 <<
635 <<
636 }; <<
637 <<
638 i2s3_p <<
639 <<
640 <<
641 <<
642 <<
643 <<
644 <<
645 }; <<
646 }; <<
647 }; <<
648 <<
649 i2s@702d1300 { <<
650 status = "okay <<
651 <<
652 ports { <<
653 #addre <<
654 #size- <<
655 <<
656 port@0 <<
657 <<
658 <<
659 <<
660 <<
661 <<
662 }; <<
663 <<
664 i2s4_p <<
665 <<
666 <<
667 <<
668 <<
669 <<
670 <<
671 }; <<
672 }; <<
673 }; <<
674 <<
675 sfc@702d2000 { <<
676 status = "okay <<
677 <<
678 ports { <<
679 #addre <<
680 #size- <<
681 <<
682 port@0 <<
683 <<
684 <<
685 <<
686 <<
687 <<
688 }; <<
689 <<
690 sfc1_o <<
691 <<
692 <<
693 <<
694 <<
695 <<
696 }; <<
697 }; <<
698 }; <<
699 <<
700 sfc@702d2200 { <<
701 status = "okay <<
702 <<
703 ports { <<
704 #addre <<
705 #size- <<
706 <<
707 port@0 <<
708 <<
709 <<
710 <<
711 <<
712 <<
713 }; <<
714 <<
715 sfc2_o <<
716 <<
717 <<
718 <<
719 <<
720 <<
721 }; <<
722 }; <<
723 }; <<
724 <<
725 sfc@702d2400 { <<
726 status = "okay <<
727 <<
728 ports { <<
729 #addre <<
730 #size- <<
731 <<
732 port@0 <<
733 <<
734 <<
735 <<
736 <<
737 <<
738 }; <<
739 <<
740 sfc3_o <<
741 <<
742 <<
743 <<
744 <<
745 <<
746 }; <<
747 }; <<
748 }; <<
749 <<
750 sfc@702d2600 { <<
751 status = "okay <<
752 <<
753 ports { <<
754 #addre <<
755 #size- <<
756 <<
757 port@0 <<
758 <<
759 <<
760 <<
761 <<
762 <<
763 }; <<
764 <<
765 sfc4_o <<
766 <<
767 <<
768 <<
769 <<
770 <<
771 }; <<
772 }; <<
773 }; <<
774 <<
775 amx@702d3000 { <<
776 status = "okay <<
777 <<
778 ports { <<
779 #addre <<
780 #size- <<
781 <<
782 port@0 <<
783 <<
784 <<
785 <<
786 <<
787 <<
788 }; <<
789 <<
790 port@1 <<
791 <<
792 <<
793 <<
794 <<
795 <<
796 }; <<
797 <<
798 port@2 <<
799 <<
800 <<
801 <<
802 <<
803 <<
804 }; <<
805 <<
806 port@3 <<
807 <<
808 <<
809 <<
810 <<
811 <<
812 }; <<
813 <<
814 amx1_o <<
815 <<
816 <<
817 <<
818 <<
819 <<
820 }; <<
821 }; <<
822 }; <<
823 <<
824 amx@702d3100 { <<
825 status = "okay <<
826 <<
827 ports { <<
828 #addre <<
829 #size- <<
830 <<
831 port@0 <<
832 <<
833 <<
834 <<
835 <<
836 <<
837 }; <<
838 <<
839 port@1 <<
840 <<
841 <<
842 <<
843 <<
844 <<
845 }; <<
846 <<
847 amx2_i <<
848 <<
849 <<
850 <<
851 <<
852 <<
853 }; <<
854 <<
855 amx2_i <<
856 <<
857 <<
858 <<
859 <<
860 <<
861 }; <<
862 <<
863 amx2_o <<
864 <<
865 <<
866 <<
867 <<
868 <<
869 }; <<
870 }; <<
871 }; <<
872 <<
873 adx@702d3800 { <<
874 status = "okay <<
875 <<
876 ports { <<
877 #addre <<
878 #size- <<
879 <<
880 port@0 <<
881 <<
882 <<
883 <<
884 <<
885 <<
886 }; <<
887 <<
888 adx1_o <<
889 <<
890 <<
891 <<
892 <<
893 <<
894 }; <<
895 <<
896 adx1_o <<
897 <<
898 <<
899 <<
900 <<
901 <<
902 }; <<
903 <<
904 adx1_o <<
905 <<
906 <<
907 <<
908 <<
909 <<
910 }; <<
911 <<
912 adx1_o <<
913 <<
914 <<
915 <<
916 <<
917 <<
918 }; <<
919 }; <<
920 }; <<
921 <<
922 adx@702d3900 { <<
923 status = "okay <<
924 <<
925 ports { <<
926 #addre <<
927 #size- <<
928 <<
929 port@0 <<
930 <<
931 <<
932 <<
933 <<
934 <<
935 }; <<
936 <<
937 adx2_o <<
938 <<
939 <<
940 <<
941 <<
942 <<
943 }; <<
944 <<
945 adx2_o <<
946 <<
947 <<
948 <<
949 <<
950 <<
951 }; <<
952 <<
953 adx2_o <<
954 <<
955 <<
956 <<
957 <<
958 <<
959 }; <<
960 <<
961 adx2_o <<
962 <<
963 <<
964 <<
965 <<
966 <<
967 }; <<
968 }; <<
969 }; <<
970 <<
971 dmic@702d4000 { <<
972 status = "okay <<
973 <<
974 ports { <<
975 #addre <<
976 #size- <<
977 <<
978 port@0 <<
979 <<
980 <<
981 <<
982 <<
983 <<
984 }; <<
985 <<
986 dmic1_ <<
987 <<
988 <<
989 <<
990 <<
991 <<
992 }; <<
993 }; <<
994 }; <<
995 <<
996 dmic@702d4100 { <<
997 status = "okay <<
998 <<
999 ports { <<
1000 #addr <<
1001 #size <<
1002 <<
1003 port@ <<
1004 <<
1005 <<
1006 <<
1007 <<
1008 <<
1009 }; <<
1010 <<
1011 dmic2 <<
1012 <<
1013 <<
1014 <<
1015 <<
1016 <<
1017 }; <<
1018 }; <<
1019 }; <<
1020 <<
1021 processing-engine@702 <<
1022 status = "oka <<
1023 <<
1024 ports { <<
1025 #addr <<
1026 #size <<
1027 <<
1028 port@ <<
1029 <<
1030 <<
1031 <<
1032 <<
1033 <<
1034 }; <<
1035 <<
1036 ope1_ <<
1037 <<
1038 <<
1039 <<
1040 <<
1041 <<
1042 }; <<
1043 }; <<
1044 }; <<
1045 <<
1046 processing-engine@702 <<
1047 status = "oka <<
1048 <<
1049 ports { <<
1050 #addr <<
1051 #size <<
1052 <<
1053 port@ <<
1054 <<
1055 <<
1056 <<
1057 <<
1058 <<
1059 }; <<
1060 <<
1061 ope2_ <<
1062 <<
1063 <<
1064 <<
1065 <<
1066 <<
1067 }; <<
1068 }; <<
1069 }; <<
1070 <<
1071 mvc@702da000 { <<
1072 status = "oka <<
1073 <<
1074 ports { <<
1075 #addr <<
1076 #size <<
1077 <<
1078 port@ <<
1079 <<
1080 <<
1081 <<
1082 <<
1083 <<
1084 }; <<
1085 <<
1086 mvc1_ <<
1087 <<
1088 <<
1089 <<
1090 <<
1091 <<
1092 }; <<
1093 }; <<
1094 }; <<
1095 <<
1096 mvc@702da200 { <<
1097 status = "oka <<
1098 <<
1099 ports { <<
1100 #addr <<
1101 #size <<
1102 <<
1103 port@ <<
1104 <<
1105 <<
1106 <<
1107 <<
1108 <<
1109 }; <<
1110 <<
1111 mvc2_ <<
1112 <<
1113 <<
1114 <<
1115 <<
1116 <<
1117 }; <<
1118 }; <<
1119 }; <<
1120 <<
1121 amixer@702dbb00 { <<
1122 status = "oka <<
1123 <<
1124 ports { <<
1125 #addr <<
1126 #size <<
1127 <<
1128 port@ <<
1129 <<
1130 <<
1131 <<
1132 <<
1133 <<
1134 }; <<
1135 <<
1136 port@ <<
1137 <<
1138 <<
1139 <<
1140 <<
1141 <<
1142 }; <<
1143 <<
1144 port@ <<
1145 <<
1146 <<
1147 <<
1148 <<
1149 <<
1150 }; <<
1151 <<
1152 port@ <<
1153 <<
1154 <<
1155 <<
1156 <<
1157 <<
1158 }; <<
1159 <<
1160 port@ <<
1161 <<
1162 <<
1163 <<
1164 <<
1165 <<
1166 }; <<
1167 <<
1168 port@ <<
1169 <<
1170 <<
1171 <<
1172 <<
1173 <<
1174 }; <<
1175 <<
1176 port@ <<
1177 <<
1178 <<
1179 <<
1180 <<
1181 <<
1182 }; <<
1183 <<
1184 port@ <<
1185 <<
1186 <<
1187 <<
1188 <<
1189 <<
1190 }; <<
1191 <<
1192 port@ <<
1193 <<
1194 <<
1195 <<
1196 <<
1197 <<
1198 }; <<
1199 <<
1200 port@ <<
1201 <<
1202 <<
1203 <<
1204 <<
1205 <<
1206 }; <<
1207 <<
1208 mixer <<
1209 <<
1210 <<
1211 <<
1212 <<
1213 <<
1214 }; <<
1215 <<
1216 mixer <<
1217 <<
1218 <<
1219 <<
1220 <<
1221 <<
1222 }; <<
1223 <<
1224 mixer <<
1225 <<
1226 <<
1227 <<
1228 <<
1229 <<
1230 }; <<
1231 <<
1232 mixer <<
1233 <<
1234 <<
1235 <<
1236 <<
1237 <<
1238 }; <<
1239 <<
1240 mixer <<
1241 <<
1242 <<
1243 <<
1244 <<
1245 <<
1246 }; <<
1247 }; <<
1248 }; <<
1249 <<
1250 ports { <<
1251 xbar_i2s3_por <<
1252 reg = <<
1253 <<
1254 xbar_ <<
1255 <<
1256 }; <<
1257 }; <<
1258 <<
1259 xbar_i2s4_por <<
1260 reg = <<
1261 <<
1262 xbar_ <<
1263 <<
1264 }; <<
1265 }; <<
1266 <<
1267 xbar_dmic1_po <<
1268 reg = <<
1269 <<
1270 xbar_ <<
1271 <<
1272 }; <<
1273 }; <<
1274 <<
1275 xbar_dmic2_po <<
1276 reg = <<
1277 <<
1278 xbar_ <<
1279 <<
1280 }; <<
1281 }; <<
1282 <<
1283 xbar_sfc1_in_ <<
1284 reg = <<
1285 <<
1286 xbar_ <<
1287 <<
1288 }; <<
1289 }; <<
1290 <<
1291 port@13 { <<
1292 reg = <<
1293 <<
1294 xbar_ <<
1295 <<
1296 }; <<
1297 }; <<
1298 <<
1299 xbar_sfc2_in_ <<
1300 reg = <<
1301 <<
1302 xbar_ <<
1303 <<
1304 }; <<
1305 }; <<
1306 <<
1307 port@15 { <<
1308 reg = <<
1309 <<
1310 xbar_ <<
1311 <<
1312 }; <<
1313 }; <<
1314 <<
1315 xbar_sfc3_in_ <<
1316 reg = <<
1317 <<
1318 xbar_ <<
1319 <<
1320 }; <<
1321 }; <<
1322 <<
1323 port@17 { <<
1324 reg = <<
1325 <<
1326 xbar_ <<
1327 <<
1328 }; <<
1329 }; <<
1330 <<
1331 xbar_sfc4_in_ <<
1332 reg = <<
1333 <<
1334 xbar_ <<
1335 <<
1336 }; <<
1337 }; <<
1338 <<
1339 port@19 { <<
1340 reg = <<
1341 <<
1342 xbar_ <<
1343 <<
1344 }; <<
1345 }; <<
1346 <<
1347 xbar_mvc1_in_ <<
1348 reg = <<
1349 <<
1350 xbar_ <<
1351 <<
1352 }; <<
1353 }; <<
1354 <<
1355 port@1b { <<
1356 reg = <<
1357 <<
1358 xbar_ <<
1359 <<
1360 }; <<
1361 }; <<
1362 <<
1363 xbar_mvc2_in_ <<
1364 reg = <<
1365 <<
1366 xbar_ <<
1367 <<
1368 }; <<
1369 }; <<
1370 <<
1371 port@1d { <<
1372 reg = <<
1373 <<
1374 xbar_ <<
1375 <<
1376 }; <<
1377 }; <<
1378 <<
1379 xbar_amx1_in1 <<
1380 reg = <<
1381 <<
1382 xbar_ <<
1383 <<
1384 }; <<
1385 }; <<
1386 <<
1387 xbar_amx1_in2 <<
1388 reg = <<
1389 <<
1390 xbar_ <<
1391 <<
1392 }; <<
1393 }; <<
1394 <<
1395 xbar_amx1_in3 <<
1396 reg = <<
1397 <<
1398 xbar_ <<
1399 <<
1400 }; <<
1401 }; <<
1402 <<
1403 xbar_amx1_in4 <<
1404 reg = <<
1405 <<
1406 xbar_ <<
1407 <<
1408 }; <<
1409 }; <<
1410 <<
1411 port@22 { <<
1412 reg = <<
1413 <<
1414 xbar_ <<
1415 <<
1416 }; <<
1417 }; <<
1418 <<
1419 xbar_amx2_in1 <<
1420 reg = <<
1421 <<
1422 xbar_ <<
1423 <<
1424 }; <<
1425 }; <<
1426 <<
1427 xbar_amx2_in2 <<
1428 reg = <<
1429 <<
1430 xbar_ <<
1431 <<
1432 }; <<
1433 }; <<
1434 <<
1435 xbar_amx2_in3 <<
1436 reg = <<
1437 <<
1438 xbar_ <<
1439 <<
1440 }; <<
1441 }; <<
1442 <<
1443 xbar_amx2_in4 <<
1444 reg = <<
1445 <<
1446 xbar_ <<
1447 <<
1448 }; <<
1449 }; <<
1450 <<
1451 port@27 { <<
1452 reg = <<
1453 <<
1454 xbar_ <<
1455 <<
1456 }; <<
1457 }; <<
1458 <<
1459 xbar_adx1_in_ <<
1460 reg = <<
1461 <<
1462 xbar_ <<
1463 <<
1464 }; <<
1465 }; <<
1466 <<
1467 port@29 { <<
1468 reg = <<
1469 <<
1470 xbar_ <<
1471 <<
1472 }; <<
1473 }; <<
1474 <<
1475 port@2a { <<
1476 reg = <<
1477 <<
1478 xbar_ <<
1479 <<
1480 }; <<
1481 }; <<
1482 <<
1483 port@2b { <<
1484 reg = <<
1485 <<
1486 xbar_ <<
1487 <<
1488 }; <<
1489 }; <<
1490 <<
1491 port@2c { <<
1492 reg = <<
1493 <<
1494 xbar_ <<
1495 <<
1496 }; <<
1497 }; <<
1498 <<
1499 xbar_adx2_in_ <<
1500 reg = <<
1501 <<
1502 xbar_ <<
1503 <<
1504 }; <<
1505 }; <<
1506 <<
1507 port@2e { <<
1508 reg = <<
1509 <<
1510 xbar_ <<
1511 <<
1512 }; <<
1513 }; <<
1514 <<
1515 port@2f { <<
1516 reg = <<
1517 <<
1518 xbar_ <<
1519 <<
1520 }; <<
1521 }; <<
1522 <<
1523 port@30 { <<
1524 reg = <<
1525 <<
1526 xbar_ <<
1527 <<
1528 }; <<
1529 }; <<
1530 <<
1531 port@31 { <<
1532 reg = <<
1533 <<
1534 xbar_ <<
1535 <<
1536 }; <<
1537 }; <<
1538 <<
1539 xbar_mixer_in <<
1540 reg = <<
1541 <<
1542 xbar_ <<
1543 <<
1544 }; <<
1545 }; <<
1546 <<
1547 xbar_mixer_in <<
1548 reg = <<
1549 <<
1550 xbar_ <<
1551 <<
1552 }; <<
1553 }; <<
1554 <<
1555 xbar_mixer_in <<
1556 reg = <<
1557 <<
1558 xbar_ <<
1559 <<
1560 }; <<
1561 }; <<
1562 <<
1563 xbar_mixer_in <<
1564 reg = <<
1565 <<
1566 xbar_ <<
1567 <<
1568 }; <<
1569 }; <<
1570 <<
1571 xbar_mixer_in <<
1572 reg = <<
1573 <<
1574 xbar_ <<
1575 <<
1576 }; <<
1577 }; <<
1578 <<
1579 xbar_mixer_in <<
1580 reg = <<
1581 <<
1582 xbar_ <<
1583 <<
1584 }; <<
1585 }; <<
1586 <<
1587 xbar_mixer_in <<
1588 reg = <<
1589 <<
1590 xbar_ <<
1591 <<
1592 }; <<
1593 }; <<
1594 <<
1595 xbar_mixer_in <<
1596 reg = <<
1597 <<
1598 xbar_ <<
1599 <<
1600 }; <<
1601 }; <<
1602 <<
1603 xbar_mixer_in <<
1604 reg = <<
1605 <<
1606 xbar_ <<
1607 <<
1608 }; <<
1609 }; <<
1610 <<
1611 xbar_mixer_in <<
1612 reg = <<
1613 <<
1614 xbar_ <<
1615 <<
1616 }; <<
1617 }; <<
1618 <<
1619 port@3c { <<
1620 reg = <<
1621 <<
1622 xbar_ <<
1623 <<
1624 }; <<
1625 }; <<
1626 <<
1627 port@3d { <<
1628 reg = <<
1629 <<
1630 xbar_ <<
1631 <<
1632 }; <<
1633 }; <<
1634 <<
1635 port@3e { <<
1636 reg = <<
1637 <<
1638 xbar_ <<
1639 <<
1640 }; <<
1641 }; <<
1642 <<
1643 port@3f { <<
1644 reg = <<
1645 <<
1646 xbar_ <<
1647 <<
1648 }; <<
1649 }; <<
1650 <<
1651 port@40 { <<
1652 reg = <<
1653 <<
1654 xbar_ <<
1655 <<
1656 }; <<
1657 }; <<
1658 <<
1659 xbar_ope1_in_ <<
1660 reg = <<
1661 <<
1662 xbar_ <<
1663 <<
1664 }; <<
1665 }; <<
1666 <<
1667 port@42 { <<
1668 reg = <<
1669 <<
1670 xbar_ <<
1671 <<
1672 }; <<
1673 }; <<
1674 <<
1675 xbar_ope2_in_ <<
1676 reg = <<
1677 <<
1678 xbar_ <<
1679 <<
1680 }; <<
1681 }; <<
1682 <<
1683 port@44 { <<
1684 reg = <<
1685 <<
1686 xbar_ <<
1687 <<
1688 }; <<
1689 }; <<
1690 }; <<
1691 }; <<
1692 <<
1693 dma-controller@702e2000 { <<
1694 status = "okay"; <<
1695 }; <<
1696 <<
1697 interrupt-controller@702f9000 <<
1698 status = "okay"; <<
1699 }; <<
1700 }; <<
1701 <<
1702 spi@70410000 { <<
1703 status = "okay"; <<
1704 493
1705 flash@0 { !! 494 clk32k_in: clock@0 {
1706 compatible = "jedec,s !! 495 compatible = "fixed-clock";
1707 reg = <0>; 496 reg = <0>;
1708 spi-max-frequency = < !! 497 #clock-cells = <0>;
1709 spi-tx-bus-width = <2 !! 498 clock-frequency = <32768>;
1710 spi-rx-bus-width = <2 <<
1711 }; 499 };
1712 }; 500 };
1713 501
1714 clk32k_in: clock-32k { <<
1715 compatible = "fixed-clock"; <<
1716 clock-frequency = <32768>; <<
1717 #clock-cells = <0>; <<
1718 }; <<
1719 <<
1720 cpus { 502 cpus {
1721 cpu@0 { 503 cpu@0 {
1722 enable-method = "psci 504 enable-method = "psci";
1723 }; 505 };
1724 506
1725 cpu@1 { 507 cpu@1 {
1726 enable-method = "psci 508 enable-method = "psci";
1727 }; 509 };
1728 510
1729 cpu@2 { 511 cpu@2 {
1730 enable-method = "psci 512 enable-method = "psci";
1731 }; 513 };
1732 514
1733 cpu@3 { 515 cpu@3 {
1734 enable-method = "psci 516 enable-method = "psci";
1735 }; 517 };
1736 <<
1737 idle-states { <<
1738 cpu-sleep { <<
1739 status = "oka <<
1740 }; <<
1741 }; <<
1742 }; 518 };
1743 519
1744 gpio-keys { 520 gpio-keys {
1745 compatible = "gpio-keys"; 521 compatible = "gpio-keys";
1746 522
1747 key-force-recovery { !! 523 power {
1748 label = "Force Recove <<
1749 gpios = <&gpio TEGRA_ <<
1750 linux,input-type = <E <<
1751 linux,code = <BTN_1>; <<
1752 debounce-interval = < <<
1753 }; <<
1754 <<
1755 key-power { <<
1756 label = "Power"; 524 label = "Power";
1757 gpios = <&gpio TEGRA_ 525 gpios = <&gpio TEGRA_GPIO(X, 5) GPIO_ACTIVE_LOW>;
1758 linux,input-type = <E 526 linux,input-type = <EV_KEY>;
1759 linux,code = <KEY_POW 527 linux,code = <KEY_POWER>;
1760 debounce-interval = < 528 debounce-interval = <30>;
1761 wakeup-event-action = 529 wakeup-event-action = <EV_ACT_ASSERTED>;
1762 wakeup-source; 530 wakeup-source;
1763 }; 531 };
>> 532
>> 533 force-recovery {
>> 534 label = "Force Recovery";
>> 535 gpios = <&gpio TEGRA_GPIO(X, 6) GPIO_ACTIVE_LOW>;
>> 536 linux,input-type = <EV_KEY>;
>> 537 linux,code = <BTN_1>;
>> 538 debounce-interval = <30>;
>> 539 };
1764 }; 540 };
1765 541
1766 psci { 542 psci {
1767 compatible = "arm,psci-1.0"; 543 compatible = "arm,psci-1.0";
1768 method = "smc"; 544 method = "smc";
1769 }; 545 };
1770 546
1771 fan: pwm-fan { !! 547 regulators {
1772 compatible = "pwm-fan"; !! 548 compatible = "simple-bus";
1773 pwms = <&pwm 3 45334>; !! 549 #address-cells = <1>;
1774 !! 550 #size-cells = <0>;
1775 cooling-levels = <0 64 128 25 <<
1776 #cooling-cells = <2>; <<
1777 }; <<
1778 <<
1779 vdd_5v0_sys: regulator-vdd-5v0-sys { <<
1780 compatible = "regulator-fixed <<
1781 <<
1782 regulator-name = "VDD_5V0_SYS <<
1783 regulator-min-microvolt = <50 <<
1784 regulator-max-microvolt = <50 <<
1785 regulator-always-on; <<
1786 regulator-boot-on; <<
1787 }; <<
1788 <<
1789 vdd_3v3_sys: regulator-vdd-3v3-sys { <<
1790 compatible = "regulator-fixed <<
1791 551
1792 regulator-name = "VDD_3V3_SYS !! 552 vdd_5v0_sys: regulator@0 {
1793 regulator-min-microvolt = <33 !! 553 compatible = "regulator-fixed";
1794 regulator-max-microvolt = <33 !! 554 reg = <0>;
1795 regulator-enable-ramp-delay = <<
1796 regulator-always-on; <<
1797 regulator-boot-on; <<
1798 <<
1799 gpio = <&pmic 3 GPIO_ACTIVE_H <<
1800 enable-active-high; <<
1801 <<
1802 vin-supply = <&vdd_5v0_sys>; <<
1803 }; <<
1804 <<
1805 vdd_3v3_sd: regulator-vdd-3v3-sd { <<
1806 compatible = "regulator-fixed <<
1807 <<
1808 regulator-name = "VDD_3V3_SD" <<
1809 regulator-min-microvolt = <33 <<
1810 regulator-max-microvolt = <33 <<
1811 <<
1812 gpio = <&gpio TEGRA_GPIO(Z, 3 <<
1813 enable-active-high; <<
1814 <<
1815 vin-supply = <&vdd_3v3_sys>; <<
1816 }; <<
1817 <<
1818 vdd_hdmi: regulator-vdd-hdmi-5v0 { <<
1819 compatible = "regulator-fixed <<
1820 <<
1821 regulator-name = "VDD_HDMI_5V <<
1822 regulator-min-microvolt = <50 <<
1823 regulator-max-microvolt = <50 <<
1824 <<
1825 vin-supply = <&vdd_5v0_sys>; <<
1826 }; <<
1827 <<
1828 vdd_hub_3v3: regulator-vdd-hub-3v3 { <<
1829 compatible = "regulator-fixed <<
1830 <<
1831 regulator-name = "VDD_HUB_3V3 <<
1832 regulator-min-microvolt = <33 <<
1833 regulator-max-microvolt = <33 <<
1834 <<
1835 gpio = <&gpio TEGRA_GPIO(A, 6 <<
1836 enable-active-high; <<
1837 <<
1838 vin-supply = <&vdd_5v0_sys>; <<
1839 }; <<
1840 <<
1841 vdd_cpu: regulator-vdd-cpu { <<
1842 compatible = "regulator-fixed <<
1843 555
1844 regulator-name = "VDD_CPU"; !! 556 regulator-name = "VDD_5V0_SYS";
1845 regulator-min-microvolt = <50 !! 557 regulator-min-microvolt = <5000000>;
1846 regulator-max-microvolt = <50 !! 558 regulator-max-microvolt = <5000000>;
1847 regulator-always-on; !! 559 regulator-always-on;
1848 regulator-boot-on; !! 560 regulator-boot-on;
>> 561 };
1849 562
1850 gpio = <&pmic 5 GPIO_ACTIVE_H !! 563 vdd_3v3_sys: regulator@1 {
1851 enable-active-high; !! 564 compatible = "regulator-fixed";
>> 565 reg = <1>;
>> 566 regulator-name = "VDD_3V3_SYS";
>> 567 regulator-min-microvolt = <3300000>;
>> 568 regulator-max-microvolt = <3300000>;
>> 569 regulator-enable-ramp-delay = <240>;
>> 570 regulator-disable-ramp-delay = <11340>;
>> 571 regulator-always-on;
>> 572 regulator-boot-on;
1852 573
1853 vin-supply = <&vdd_5v0_sys>; !! 574 gpio = <&pmic 3 GPIO_ACTIVE_HIGH>;
1854 }; !! 575 enable-active-high;
1855 576
1856 vdd_gpu: regulator-vdd-gpu { !! 577 vin-supply = <&vdd_5v0_sys>;
1857 compatible = "pwm-regulator"; !! 578 };
1858 pwms = <&pwm 1 8000>; <<
1859 <<
1860 regulator-name = "VDD_GPU"; <<
1861 regulator-min-microvolt = <71 <<
1862 regulator-max-microvolt = <13 <<
1863 regulator-ramp-delay = <80>; <<
1864 regulator-enable-ramp-delay = <<
1865 regulator-settling-time-us = <<
1866 579
1867 enable-gpios = <&pmic 6 GPIO_ !! 580 vdd_3v3_sd: regulator@2 {
1868 vin-supply = <&vdd_5v0_sys>; !! 581 compatible = "regulator-fixed";
1869 }; !! 582 reg = <2>;
1870 583
1871 avdd_io_edp_1v05: regulator-avdd-io-e !! 584 regulator-name = "VDD_3V3_SD";
1872 compatible = "regulator-fixed !! 585 regulator-min-microvolt = <3300000>;
>> 586 regulator-max-microvolt = <3300000>;
1873 587
1874 regulator-name = "AVDD_IO_EDP !! 588 gpio = <&gpio TEGRA_GPIO(Z, 3) GPIO_ACTIVE_HIGH>;
1875 regulator-min-microvolt = <10 !! 589 enable-active-high;
1876 regulator-max-microvolt = <10 <<
1877 590
1878 gpio = <&pmic 7 GPIO_ACTIVE_H !! 591 vin-supply = <&vdd_3v3_sys>;
1879 enable-active-high; !! 592 };
1880 593
1881 vin-supply = <&avdd_1v05_pll> !! 594 vdd_hdmi: regulator@3 {
1882 }; !! 595 compatible = "regulator-fixed";
>> 596 reg = <3>;
1883 597
1884 vdd_5v0_usb: regulator-vdd-5v-usb { !! 598 regulator-name = "VDD_HDMI_5V0";
1885 compatible = "regulator-fixed !! 599 regulator-min-microvolt = <5000000>;
>> 600 regulator-max-microvolt = <5000000>;
1886 601
1887 regulator-name = "VDD_5V_USB" !! 602 vin-supply = <&vdd_5v0_sys>;
1888 regulator-min-microvolt = <50 !! 603 };
1889 regulator-max-microvolt = <50 <<
1890 604
1891 vin-supply = <&vdd_5v0_sys>; !! 605 vdd_hub_3v3: regulator@4 {
1892 }; !! 606 compatible = "regulator-fixed";
>> 607 reg = <4>;
1893 608
1894 sound { !! 609 regulator-name = "VDD_HUB_3V3";
1895 compatible = "nvidia,tegra210 !! 610 regulator-min-microvolt = <3300000>;
1896 status = "okay"; !! 611 regulator-max-microvolt = <3300000>;
1897 612
1898 dais = /* FE */ !! 613 gpio = <&gpio TEGRA_GPIO(A, 6) GPIO_ACTIVE_HIGH>;
1899 <&admaif1_port>, <&adm !! 614 enable-active-high;
1900 <&admaif4_port>, <&adm <<
1901 <&admaif7_port>, <&adm <<
1902 <&admaif10_port>, <<
1903 /* Router */ <<
1904 <&xbar_i2s3_port>, <&x <<
1905 <&xbar_dmic1_port>, <& <<
1906 <&xbar_sfc1_in_port>, <<
1907 <&xbar_sfc3_in_port>, <<
1908 <&xbar_mvc1_in_port>, <<
1909 <&xbar_amx1_in1_port>, <<
1910 <&xbar_amx1_in3_port>, <<
1911 <&xbar_amx2_in1_port>, <<
1912 <&xbar_amx2_in3_port>, <<
1913 <&xbar_adx1_in_port>, <<
1914 <&xbar_mixer_in1_port> <<
1915 <&xbar_mixer_in3_port> <<
1916 <&xbar_mixer_in5_port> <<
1917 <&xbar_mixer_in7_port> <<
1918 <&xbar_mixer_in9_port> <<
1919 <&xbar_ope1_in_port>, <<
1920 /* HW accelerators */ <<
1921 <&sfc1_out_port>, <&sf <<
1922 <&sfc3_out_port>, <&sf <<
1923 <&mvc1_out_port>, <&mv <<
1924 <&amx1_out_port>, <&am <<
1925 <&adx1_out1_port>, <&a <<
1926 <&adx1_out3_port>, <&a <<
1927 <&adx2_out1_port>, <&a <<
1928 <&adx2_out3_port>, <&a <<
1929 <&mixer_out1_port>, <& <<
1930 <&mixer_out3_port>, <& <<
1931 <&mixer_out5_port>, <<
1932 <&ope1_out_port>, <&op <<
1933 /* I/O DAP Ports */ <<
1934 <&i2s3_port>, <&i2s4_p <<
1935 <&dmic1_port>, <&dmic2 <<
1936 615
1937 label = "NVIDIA Jetson Nano A !! 616 vin-supply = <&vdd_5v0_sys>;
1938 }; !! 617 };
1939 618
1940 thermal-zones { !! 619 vdd_cpu: regulator@5 {
1941 cpu-thermal { !! 620 compatible = "regulator-fixed";
1942 trips { !! 621 reg = <5>;
1943 cpu_trip_crit <<
1944 tempe <<
1945 hyste <<
1946 type <<
1947 }; <<
1948 <<
1949 cpu_trip_hot: <<
1950 tempe <<
1951 hyste <<
1952 type <<
1953 }; <<
1954 <<
1955 cpu_trip_acti <<
1956 tempe <<
1957 hyste <<
1958 type <<
1959 }; <<
1960 <<
1961 cpu_trip_pass <<
1962 tempe <<
1963 hyste <<
1964 type <<
1965 }; <<
1966 }; <<
1967 622
1968 cooling-maps { !! 623 regulator-name = "VDD_CPU";
1969 cpu-critical !! 624 regulator-min-microvolt = <5000000>;
1970 cooli !! 625 regulator-max-microvolt = <5000000>;
1971 trip !! 626 regulator-always-on;
1972 }; !! 627 regulator-boot-on;
1973 628
1974 cpu-hot { !! 629 gpio = <&pmic 5 GPIO_ACTIVE_HIGH>;
1975 cooli !! 630 enable-active-high;
1976 trip <<
1977 }; <<
1978 631
1979 cpu-active { !! 632 vin-supply = <&vdd_5v0_sys>;
1980 cooli !! 633 };
1981 trip <<
1982 }; <<
1983 634
1984 cpu-passive { !! 635 vdd_gpu: regulator@6 {
1985 cooli !! 636 compatible = "pwm-regulator";
1986 trip !! 637 reg = <6>;
1987 }; !! 638 pwms = <&pwm 1 4880>;
1988 }; !! 639 regulator-name = "VDD_GPU";
>> 640 regulator-min-microvolt = <710000>;
>> 641 regulator-max-microvolt = <1320000>;
>> 642 regulator-ramp-delay = <80>;
>> 643 regulator-enable-ramp-delay = <2000>;
>> 644 regulator-settling-time-us = <160>;
>> 645 enable-gpios = <&pmic 6 GPIO_ACTIVE_HIGH>;
>> 646 vin-supply = <&vdd_5v0_sys>;
1989 }; 647 };
1990 }; 648 };
1991 }; 649 };
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