1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra210-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra210-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra-io
7 #include <dt-bindings/reset/tegra210-car.h>
8 #include <dt-bindings/interrupt-controller/arm
9 #include <dt-bindings/thermal/tegra124-socther
10 #include <dt-bindings/soc/tegra-pmc.h>
11
12 / {
13 compatible = "nvidia,tegra210";
14 interrupt-parent = <&lic>;
15 #address-cells = <2>;
16 #size-cells = <2>;
17
18 pcie@1003000 {
19 compatible = "nvidia,tegra210-
20 device_type = "pci";
21 reg = <0x0 0x01003000 0x0 0x00
22 <0x0 0x01003800 0x0 0x00
23 <0x0 0x02000000 0x0 0x10
24 reg-names = "pads", "afi", "cs
25 interrupts = <GIC_SPI 98 IRQ_T
26 <GIC_SPI 99 IRQ_T
27 interrupt-names = "intr", "msi
28
29 #interrupt-cells = <1>;
30 interrupt-map-mask = <0 0 0 0>
31 interrupt-map = <0 0 0 0 &gic
32
33 bus-range = <0x00 0xff>;
34 #address-cells = <3>;
35 #size-cells = <2>;
36
37 ranges = <0x02000000 0 0x01000
38 <0x02000000 0 0x01001
39 <0x01000000 0 0x0
40 <0x02000000 0 0x13000
41 <0x42000000 0 0x20000
42
43 clocks = <&tegra_car TEGRA210_
44 <&tegra_car TEGRA210_
45 <&tegra_car TEGRA210_
46 <&tegra_car TEGRA210_
47 clock-names = "pex", "afi", "p
48 resets = <&tegra_car 70>,
49 <&tegra_car 72>,
50 <&tegra_car 74>;
51 reset-names = "pex", "afi", "p
52
53 pinctrl-names = "default", "id
54 pinctrl-0 = <&pex_dpd_disable>
55 pinctrl-1 = <&pex_dpd_enable>;
56
57 status = "disabled";
58
59 pci@1,0 {
60 device_type = "pci";
61 assigned-addresses = <
62 reg = <0x000800 0 0 0
63 bus-range = <0x00 0xff
64 status = "disabled";
65
66 #address-cells = <3>;
67 #size-cells = <2>;
68 ranges;
69
70 nvidia,num-lanes = <4>
71 };
72
73 pci@2,0 {
74 device_type = "pci";
75 assigned-addresses = <
76 reg = <0x001000 0 0 0
77 bus-range = <0x00 0xff
78 status = "disabled";
79
80 #address-cells = <3>;
81 #size-cells = <2>;
82 ranges;
83
84 nvidia,num-lanes = <1>
85 };
86 };
87
88 host1x@50000000 {
89 compatible = "nvidia,tegra210-
90 reg = <0x0 0x50000000 0x0 0x00
91 interrupts = <GIC_SPI 65 IRQ_T
92 <GIC_SPI 67 IRQ_T
93 interrupt-names = "syncpt", "h
94 clocks = <&tegra_car TEGRA210_
95 clock-names = "host1x";
96 resets = <&tegra_car 28>, <&mc
97 reset-names = "host1x", "mc";
98
99 #address-cells = <2>;
100 #size-cells = <2>;
101
102 ranges = <0x0 0x54000000 0x0 0
103
104 iommus = <&mc TEGRA_SWGROUP_HC
105
106 dpaux1: dpaux@54040000 {
107 compatible = "nvidia,t
108 reg = <0x0 0x54040000
109 interrupts = <GIC_SPI
110 clocks = <&tegra_car T
111 <&tegra_car T
112 clock-names = "dpaux",
113 resets = <&tegra_car 2
114 reset-names = "dpaux";
115 power-domains = <&pd_s
116 status = "disabled";
117
118 state_dpaux1_aux: pinm
119 groups = "dpau
120 function = "au
121 };
122
123 state_dpaux1_i2c: pinm
124 groups = "dpau
125 function = "i2
126 };
127
128 state_dpaux1_off: pinm
129 groups = "dpau
130 function = "of
131 };
132
133 i2c-bus {
134 #address-cells
135 #size-cells =
136 };
137 };
138
139 vi@54080000 {
140 compatible = "nvidia,t
141 reg = <0x0 0x54080000
142 interrupts = <GIC_SPI
143 status = "disabled";
144 assigned-clocks = <&te
145 assigned-clock-parents
146
147 clocks = <&tegra_car T
148 power-domains = <&pd_v
149
150 #address-cells = <1>;
151 #size-cells = <1>;
152
153 ranges = <0x0 0x0 0x54
154
155 csi@838 {
156 compatible = "
157 reg = <0x838 0
158 status = "disa
159 assigned-clock
160
161
162
163 assigned-clock
164
165
166 assigned-clock
167
168
169
170
171 clocks = <&teg
172 <&teg
173 <&teg
174 <&teg
175 <&teg
176 clock-names =
177 power-domains
178 };
179 };
180
181 tsec@54100000 {
182 compatible = "nvidia,t
183 reg = <0x0 0x54100000
184 interrupts = <GIC_SPI
185 clocks = <&tegra_car T
186 clock-names = "tsec";
187 resets = <&tegra_car 8
188 reset-names = "tsec";
189 status = "disabled";
190 };
191
192 dc@54200000 {
193 compatible = "nvidia,t
194 reg = <0x0 0x54200000
195 interrupts = <GIC_SPI
196 clocks = <&tegra_car T
197 clock-names = "dc";
198 resets = <&tegra_car 2
199 reset-names = "dc";
200
201 iommus = <&mc TEGRA_SW
202
203 nvidia,outputs = <&dsi
204 nvidia,head = <0>;
205 };
206
207 dc@54240000 {
208 compatible = "nvidia,t
209 reg = <0x0 0x54240000
210 interrupts = <GIC_SPI
211 clocks = <&tegra_car T
212 clock-names = "dc";
213 resets = <&tegra_car 2
214 reset-names = "dc";
215
216 iommus = <&mc TEGRA_SW
217
218 nvidia,outputs = <&dsi
219 nvidia,head = <1>;
220 };
221
222 dsia: dsi@54300000 {
223 compatible = "nvidia,t
224 reg = <0x0 0x54300000
225 clocks = <&tegra_car T
226 <&tegra_car T
227 <&tegra_car T
228 clock-names = "dsi", "
229 resets = <&tegra_car 4
230 reset-names = "dsi";
231 power-domains = <&pd_s
232 nvidia,mipi-calibrate
233
234 status = "disabled";
235
236 #address-cells = <1>;
237 #size-cells = <0>;
238 };
239
240 vic@54340000 {
241 compatible = "nvidia,t
242 reg = <0x0 0x54340000
243 interrupts = <GIC_SPI
244 clocks = <&tegra_car T
245 clock-names = "vic";
246 resets = <&tegra_car 1
247 reset-names = "vic";
248
249 iommus = <&mc TEGRA_SW
250 power-domains = <&pd_v
251 };
252
253 nvjpg@54380000 {
254 compatible = "nvidia,t
255 reg = <0x0 0x54380000
256 status = "disabled";
257 };
258
259 dsib: dsi@54400000 {
260 compatible = "nvidia,t
261 reg = <0x0 0x54400000
262 clocks = <&tegra_car T
263 <&tegra_car T
264 <&tegra_car T
265 clock-names = "dsi", "
266 resets = <&tegra_car 8
267 reset-names = "dsi";
268 power-domains = <&pd_s
269 nvidia,mipi-calibrate
270
271 status = "disabled";
272
273 #address-cells = <1>;
274 #size-cells = <0>;
275 };
276
277 nvdec@54480000 {
278 compatible = "nvidia,t
279 reg = <0x0 0x54480000
280 status = "disabled";
281 };
282
283 nvenc@544c0000 {
284 compatible = "nvidia,t
285 reg = <0x0 0x544c0000
286 status = "disabled";
287 };
288
289 tsec@54500000 {
290 compatible = "nvidia,t
291 reg = <0x0 0x54500000
292 interrupts = <GIC_SPI
293 clocks = <&tegra_car T
294 clock-names = "tsec";
295 resets = <&tegra_car 2
296 reset-names = "tsec";
297 status = "disabled";
298 };
299
300 sor0: sor@54540000 {
301 compatible = "nvidia,t
302 reg = <0x0 0x54540000
303 interrupts = <GIC_SPI
304 clocks = <&tegra_car T
305 <&tegra_car T
306 <&tegra_car T
307 <&tegra_car T
308 <&tegra_car T
309 clock-names = "sor", "
310 resets = <&tegra_car 1
311 reset-names = "sor";
312 pinctrl-0 = <&state_dp
313 pinctrl-1 = <&state_dp
314 pinctrl-2 = <&state_dp
315 pinctrl-names = "aux",
316 power-domains = <&pd_s
317 status = "disabled";
318 };
319
320 sor1: sor@54580000 {
321 compatible = "nvidia,t
322 reg = <0x0 0x54580000
323 interrupts = <GIC_SPI
324 clocks = <&tegra_car T
325 <&tegra_car T
326 <&tegra_car T
327 <&tegra_car T
328 <&tegra_car T
329 clock-names = "sor", "
330 resets = <&tegra_car 1
331 reset-names = "sor";
332 pinctrl-0 = <&state_dp
333 pinctrl-1 = <&state_dp
334 pinctrl-2 = <&state_dp
335 pinctrl-names = "aux",
336 power-domains = <&pd_s
337 status = "disabled";
338 };
339
340 dpaux: dpaux@545c0000 {
341 compatible = "nvidia,t
342 reg = <0x0 0x545c0000
343 interrupts = <GIC_SPI
344 clocks = <&tegra_car T
345 <&tegra_car T
346 clock-names = "dpaux",
347 resets = <&tegra_car 1
348 reset-names = "dpaux";
349 power-domains = <&pd_s
350 status = "disabled";
351
352 state_dpaux_aux: pinmu
353 groups = "dpau
354 function = "au
355 };
356
357 state_dpaux_i2c: pinmu
358 groups = "dpau
359 function = "i2
360 };
361
362 state_dpaux_off: pinmu
363 groups = "dpau
364 function = "of
365 };
366
367 i2c-bus {
368 #address-cells
369 #size-cells =
370 };
371 };
372
373 isp@54600000 {
374 compatible = "nvidia,t
375 reg = <0x0 0x54600000
376 interrupts = <GIC_SPI
377 clocks = <&tegra_car T
378 resets = <&tegra_car 2
379 reset-names = "isp";
380 status = "disabled";
381 };
382
383 isp@54680000 {
384 compatible = "nvidia,t
385 reg = <0x0 0x54680000
386 interrupts = <GIC_SPI
387 clocks = <&tegra_car T
388 resets = <&tegra_car 3
389 reset-names = "isp";
390 status = "disabled";
391 };
392
393 i2c@546c0000 {
394 compatible = "nvidia,t
395 reg = <0x0 0x546c0000
396 interrupts = <GIC_SPI
397 clocks = <&tegra_car T
398 <&tegra_car T
399 clock-names = "div-clk
400 resets = <&tegra_car 2
401 reset-names = "i2c";
402 power-domains = <&pd_v
403 status = "disabled";
404
405 #address-cells = <1>;
406 #size-cells = <0>;
407 };
408 };
409
410 gic: interrupt-controller@50041000 {
411 compatible = "arm,gic-400";
412 #interrupt-cells = <3>;
413 interrupt-controller;
414 reg = <0x0 0x50041000 0x0 0x10
415 <0x0 0x50042000 0x0 0x20
416 <0x0 0x50044000 0x0 0x20
417 <0x0 0x50046000 0x0 0x20
418 interrupts = <GIC_PPI 9
419 (GIC_CPU_MASK_SIMPLE(4
420 interrupt-parent = <&gic>;
421 };
422
423 gpu@57000000 {
424 compatible = "nvidia,gm20b";
425 reg = <0x0 0x57000000 0x0 0x01
426 <0x0 0x58000000 0x0 0x01
427 interrupts = <GIC_SPI 157 IRQ_
428 <GIC_SPI 158 IRQ_
429 interrupt-names = "stall", "no
430 clocks = <&tegra_car TEGRA210_
431 <&tegra_car TEGRA210_
432 <&tegra_car TEGRA210_
433 clock-names = "gpu", "pwr", "r
434 resets = <&tegra_car 184>;
435 reset-names = "gpu";
436
437 iommus = <&mc TEGRA_SWGROUP_GP
438
439 status = "disabled";
440 };
441
442 lic: interrupt-controller@60004000 {
443 compatible = "nvidia,tegra210-
444 reg = <0x0 0x60004000 0x0 0x40
445 <0x0 0x60004100 0x0 0x40
446 <0x0 0x60004200 0x0 0x40
447 <0x0 0x60004300 0x0 0x40
448 <0x0 0x60004400 0x0 0x40
449 <0x0 0x60004500 0x0 0x40
450 interrupt-controller;
451 #interrupt-cells = <3>;
452 interrupt-parent = <&gic>;
453 };
454
455 timer@60005000 {
456 compatible = "nvidia,tegra210-
457 reg = <0x0 0x60005000 0x0 0x40
458 interrupts = <GIC_SPI 156 IRQ_
459 <GIC_SPI 0 IRQ_TY
460 <GIC_SPI 1 IRQ_TY
461 <GIC_SPI 41 IRQ_T
462 <GIC_SPI 42 IRQ_T
463 <GIC_SPI 121 IRQ_
464 <GIC_SPI 152 IRQ_
465 <GIC_SPI 153 IRQ_
466 <GIC_SPI 154 IRQ_
467 <GIC_SPI 155 IRQ_
468 <GIC_SPI 176 IRQ_
469 <GIC_SPI 177 IRQ_
470 <GIC_SPI 178 IRQ_
471 <GIC_SPI 179 IRQ_
472 clocks = <&tegra_car TEGRA210_
473 clock-names = "timer";
474 };
475
476 tegra_car: clock@60006000 {
477 compatible = "nvidia,tegra210-
478 reg = <0x0 0x60006000 0x0 0x10
479 #clock-cells = <1>;
480 #reset-cells = <1>;
481 };
482
483 flow-controller@60007000 {
484 compatible = "nvidia,tegra210-
485 reg = <0x0 0x60007000 0x0 0x10
486 };
487
488 gpio: gpio@6000d000 {
489 compatible = "nvidia,tegra210-
490 reg = <0x0 0x6000d000 0x0 0x10
491 interrupts = <GIC_SPI 32 IRQ_T
492 <GIC_SPI 33 IRQ_T
493 <GIC_SPI 34 IRQ_T
494 <GIC_SPI 35 IRQ_T
495 <GIC_SPI 55 IRQ_T
496 <GIC_SPI 87 IRQ_T
497 <GIC_SPI 89 IRQ_T
498 <GIC_SPI 125 IRQ_
499 #gpio-cells = <2>;
500 gpio-controller;
501 #interrupt-cells = <2>;
502 interrupt-controller;
503 };
504
505 apbdma: dma@60020000 {
506 compatible = "nvidia,tegra210-
507 reg = <0x0 0x60020000 0x0 0x14
508 interrupts = <GIC_SPI 104 IRQ_
509 <GIC_SPI 105 IRQ_
510 <GIC_SPI 106 IRQ_
511 <GIC_SPI 107 IRQ_
512 <GIC_SPI 108 IRQ_
513 <GIC_SPI 109 IRQ_
514 <GIC_SPI 110 IRQ_
515 <GIC_SPI 111 IRQ_
516 <GIC_SPI 112 IRQ_
517 <GIC_SPI 113 IRQ_
518 <GIC_SPI 114 IRQ_
519 <GIC_SPI 115 IRQ_
520 <GIC_SPI 116 IRQ_
521 <GIC_SPI 117 IRQ_
522 <GIC_SPI 118 IRQ_
523 <GIC_SPI 119 IRQ_
524 <GIC_SPI 128 IRQ_
525 <GIC_SPI 129 IRQ_
526 <GIC_SPI 130 IRQ_
527 <GIC_SPI 131 IRQ_
528 <GIC_SPI 132 IRQ_
529 <GIC_SPI 133 IRQ_
530 <GIC_SPI 134 IRQ_
531 <GIC_SPI 135 IRQ_
532 <GIC_SPI 136 IRQ_
533 <GIC_SPI 137 IRQ_
534 <GIC_SPI 138 IRQ_
535 <GIC_SPI 139 IRQ_
536 <GIC_SPI 140 IRQ_
537 <GIC_SPI 141 IRQ_
538 <GIC_SPI 142 IRQ_
539 <GIC_SPI 143 IRQ_
540 clocks = <&tegra_car TEGRA210_
541 clock-names = "dma";
542 resets = <&tegra_car 34>;
543 reset-names = "dma";
544 #dma-cells = <1>;
545 };
546
547 apbmisc@70000800 {
548 compatible = "nvidia,tegra210-
549 reg = <0x0 0x70000800 0x0 0x64
550 <0x0 0x70000008 0x0 0x04
551 };
552
553 pinmux: pinmux@700008d4 {
554 compatible = "nvidia,tegra210-
555 reg = <0x0 0x700008d4 0x0 0x29
556 <0x0 0x70003000 0x0 0x29
557
558 sdmmc1_1v8_drv: pinmux-sdmmc1-
559 sdmmc1 {
560 nvidia,pins =
561 nvidia,pull-do
562 nvidia,pull-up
563 };
564 };
565
566 sdmmc1_3v3_drv: pinmux-sdmmc1-
567 sdmmc1 {
568 nvidia,pins =
569 nvidia,pull-do
570 nvidia,pull-up
571 };
572 };
573
574 sdmmc2_1v8_drv: pinmux-sdmmc2-
575 sdmmc2 {
576 nvidia,pins =
577 nvidia,pull-do
578 nvidia,pull-up
579 };
580 };
581
582 sdmmc3_1v8_drv: pinmux-sdmmc3-
583 sdmmc3 {
584 nvidia,pins =
585 nvidia,pull-do
586 nvidia,pull-up
587 };
588 };
589
590 sdmmc3_3v3_drv: pinmux-sdmmc3-
591 sdmmc3 {
592 nvidia,pins =
593 nvidia,pull-do
594 nvidia,pull-up
595 };
596 };
597
598 sdmmc4_1v8_drv: pinmux-sdmmc4-
599 sdmmc4 {
600 nvidia,pins =
601 nvidia,pull-do
602 nvidia,pull-up
603 };
604 };
605 };
606
607 /*
608 * There are two serial driver i.e. 82
609 * driver and APB DMA based serial dri
610 * and performance. To enable the 8250
611 * is "nvidia,tegra124-uart", "nvidia,
612 * the APB DMA based serial driver, th
613 * "nvidia,tegra124-hsuart", "nvidia,t
614 */
615 uarta: serial@70006000 {
616 compatible = "nvidia,tegra210-
617 reg = <0x0 0x70006000 0x0 0x40
618 reg-shift = <2>;
619 interrupts = <GIC_SPI 36 IRQ_T
620 clocks = <&tegra_car TEGRA210_
621 resets = <&tegra_car 6>;
622 dmas = <&apbdma 8>, <&apbdma 8
623 dma-names = "rx", "tx";
624 status = "disabled";
625 };
626
627 uartb: serial@70006040 {
628 compatible = "nvidia,tegra210-
629 reg = <0x0 0x70006040 0x0 0x40
630 reg-shift = <2>;
631 interrupts = <GIC_SPI 37 IRQ_T
632 clocks = <&tegra_car TEGRA210_
633 resets = <&tegra_car 7>;
634 dmas = <&apbdma 9>, <&apbdma 9
635 dma-names = "rx", "tx";
636 status = "disabled";
637 };
638
639 uartc: serial@70006200 {
640 compatible = "nvidia,tegra210-
641 reg = <0x0 0x70006200 0x0 0x40
642 reg-shift = <2>;
643 interrupts = <GIC_SPI 46 IRQ_T
644 clocks = <&tegra_car TEGRA210_
645 resets = <&tegra_car 55>;
646 dmas = <&apbdma 10>, <&apbdma
647 dma-names = "rx", "tx";
648 status = "disabled";
649 };
650
651 uartd: serial@70006300 {
652 compatible = "nvidia,tegra210-
653 reg = <0x0 0x70006300 0x0 0x40
654 reg-shift = <2>;
655 interrupts = <GIC_SPI 90 IRQ_T
656 clocks = <&tegra_car TEGRA210_
657 resets = <&tegra_car 65>;
658 dmas = <&apbdma 19>, <&apbdma
659 dma-names = "rx", "tx";
660 status = "disabled";
661 };
662
663 pwm: pwm@7000a000 {
664 compatible = "nvidia,tegra210-
665 reg = <0x0 0x7000a000 0x0 0x10
666 #pwm-cells = <2>;
667 clocks = <&tegra_car TEGRA210_
668 resets = <&tegra_car 17>;
669 reset-names = "pwm";
670 status = "disabled";
671 };
672
673 i2c@7000c000 {
674 compatible = "nvidia,tegra210-
675 reg = <0x0 0x7000c000 0x0 0x10
676 interrupts = <GIC_SPI 38 IRQ_T
677 #address-cells = <1>;
678 #size-cells = <0>;
679 clocks = <&tegra_car TEGRA210_
680 clock-names = "div-clk";
681 resets = <&tegra_car 12>;
682 reset-names = "i2c";
683 dmas = <&apbdma 21>, <&apbdma
684 dma-names = "rx", "tx";
685 status = "disabled";
686 };
687
688 i2c@7000c400 {
689 compatible = "nvidia,tegra210-
690 reg = <0x0 0x7000c400 0x0 0x10
691 interrupts = <GIC_SPI 84 IRQ_T
692 #address-cells = <1>;
693 #size-cells = <0>;
694 clocks = <&tegra_car TEGRA210_
695 clock-names = "div-clk";
696 resets = <&tegra_car 54>;
697 reset-names = "i2c";
698 dmas = <&apbdma 22>, <&apbdma
699 dma-names = "rx", "tx";
700 status = "disabled";
701 };
702
703 i2c@7000c500 {
704 compatible = "nvidia,tegra210-
705 reg = <0x0 0x7000c500 0x0 0x10
706 interrupts = <GIC_SPI 92 IRQ_T
707 #address-cells = <1>;
708 #size-cells = <0>;
709 clocks = <&tegra_car TEGRA210_
710 clock-names = "div-clk";
711 resets = <&tegra_car 67>;
712 reset-names = "i2c";
713 dmas = <&apbdma 23>, <&apbdma
714 dma-names = "rx", "tx";
715 status = "disabled";
716 };
717
718 i2c@7000c700 {
719 compatible = "nvidia,tegra210-
720 reg = <0x0 0x7000c700 0x0 0x10
721 interrupts = <GIC_SPI 120 IRQ_
722 #address-cells = <1>;
723 #size-cells = <0>;
724 clocks = <&tegra_car TEGRA210_
725 clock-names = "div-clk";
726 resets = <&tegra_car 103>;
727 reset-names = "i2c";
728 dmas = <&apbdma 26>, <&apbdma
729 dma-names = "rx", "tx";
730 pinctrl-0 = <&state_dpaux1_i2c
731 pinctrl-1 = <&state_dpaux1_off
732 pinctrl-names = "default", "id
733 status = "disabled";
734 };
735
736 i2c@7000d000 {
737 compatible = "nvidia,tegra210-
738 reg = <0x0 0x7000d000 0x0 0x10
739 interrupts = <GIC_SPI 53 IRQ_T
740 #address-cells = <1>;
741 #size-cells = <0>;
742 clocks = <&tegra_car TEGRA210_
743 clock-names = "div-clk";
744 resets = <&tegra_car 47>;
745 reset-names = "i2c";
746 dmas = <&apbdma 24>, <&apbdma
747 dma-names = "rx", "tx";
748 status = "disabled";
749 };
750
751 i2c@7000d100 {
752 compatible = "nvidia,tegra210-
753 reg = <0x0 0x7000d100 0x0 0x10
754 interrupts = <GIC_SPI 63 IRQ_T
755 #address-cells = <1>;
756 #size-cells = <0>;
757 clocks = <&tegra_car TEGRA210_
758 clock-names = "div-clk";
759 resets = <&tegra_car 166>;
760 reset-names = "i2c";
761 dmas = <&apbdma 30>, <&apbdma
762 dma-names = "rx", "tx";
763 pinctrl-0 = <&state_dpaux_i2c>
764 pinctrl-1 = <&state_dpaux_off>
765 pinctrl-names = "default", "id
766 status = "disabled";
767 };
768
769 spi@7000d400 {
770 compatible = "nvidia,tegra210-
771 reg = <0x0 0x7000d400 0x0 0x20
772 interrupts = <GIC_SPI 59 IRQ_T
773 #address-cells = <1>;
774 #size-cells = <0>;
775 clocks = <&tegra_car TEGRA210_
776 clock-names = "spi";
777 resets = <&tegra_car 41>;
778 reset-names = "spi";
779 dmas = <&apbdma 15>, <&apbdma
780 dma-names = "rx", "tx";
781 status = "disabled";
782 };
783
784 spi@7000d600 {
785 compatible = "nvidia,tegra210-
786 reg = <0x0 0x7000d600 0x0 0x20
787 interrupts = <GIC_SPI 82 IRQ_T
788 #address-cells = <1>;
789 #size-cells = <0>;
790 clocks = <&tegra_car TEGRA210_
791 clock-names = "spi";
792 resets = <&tegra_car 44>;
793 reset-names = "spi";
794 dmas = <&apbdma 16>, <&apbdma
795 dma-names = "rx", "tx";
796 status = "disabled";
797 };
798
799 spi@7000d800 {
800 compatible = "nvidia,tegra210-
801 reg = <0x0 0x7000d800 0x0 0x20
802 interrupts = <GIC_SPI 83 IRQ_T
803 #address-cells = <1>;
804 #size-cells = <0>;
805 clocks = <&tegra_car TEGRA210_
806 clock-names = "spi";
807 resets = <&tegra_car 46>;
808 reset-names = "spi";
809 dmas = <&apbdma 17>, <&apbdma
810 dma-names = "rx", "tx";
811 status = "disabled";
812 };
813
814 spi@7000da00 {
815 compatible = "nvidia,tegra210-
816 reg = <0x0 0x7000da00 0x0 0x20
817 interrupts = <GIC_SPI 93 IRQ_T
818 #address-cells = <1>;
819 #size-cells = <0>;
820 clocks = <&tegra_car TEGRA210_
821 clock-names = "spi";
822 resets = <&tegra_car 68>;
823 reset-names = "spi";
824 dmas = <&apbdma 18>, <&apbdma
825 dma-names = "rx", "tx";
826 status = "disabled";
827 };
828
829 rtc@7000e000 {
830 compatible = "nvidia,tegra210-
831 reg = <0x0 0x7000e000 0x0 0x10
832 interrupts = <16 IRQ_TYPE_LEVE
833 interrupt-parent = <&tegra_pmc
834 clocks = <&tegra_car TEGRA210_
835 clock-names = "rtc";
836 };
837
838 tegra_pmc: pmc@7000e400 {
839 compatible = "nvidia,tegra210-
840 reg = <0x0 0x7000e400 0x0 0x40
841 clocks = <&tegra_car TEGRA210_
842 clock-names = "pclk", "clk32k_
843 #clock-cells = <1>;
844 #interrupt-cells = <2>;
845 interrupt-controller;
846
847 pinmux {
848 pex_dpd_disable: pex-d
849 pins = "pex-bi
850 low-power-disa
851 };
852
853 pex_dpd_enable: pex-dp
854 pins = "pex-bi
855 low-power-enab
856 };
857
858 sdmmc1_1v8: sdmmc1-1v8
859 pins = "sdmmc1
860 power-source =
861 };
862
863 sdmmc1_3v3: sdmmc1-3v3
864 pins = "sdmmc1
865 power-source =
866 };
867
868 sdmmc3_1v8: sdmmc3-1v8
869 pins = "sdmmc3
870 power-source =
871 };
872
873 sdmmc3_3v3: sdmmc3-3v3
874 pins = "sdmmc3
875 power-source =
876 };
877 };
878
879 powergates {
880 pd_audio: aud {
881 clocks = <&teg
882 <&teg
883 resets = <&teg
884 #power-domain-
885 };
886
887 pd_sor: sor {
888 clocks = <&teg
889 <&teg
890 <&teg
891 <&teg
892 <&teg
893 <&teg
894 <&teg
895 <&teg
896 <&teg
897 <&teg
898 resets = <&teg
899 <&teg
900 <&teg
901 <&teg
902 <&teg
903 <&teg
904 <&teg
905 #power-domain-
906 };
907
908 pd_venc: venc {
909 clocks = <&teg
910 <&teg
911 resets = <&mc
912 <&teg
913 <&teg
914 #power-domain-
915 };
916
917 pd_vic: vic {
918 clocks = <&teg
919 resets = <&teg
920 #power-domain-
921 };
922
923 pd_xusbss: xusba {
924 clocks = <&teg
925 resets = <&teg
926 #power-domain-
927 };
928
929 pd_xusbdev: xusbb {
930 clocks = <&teg
931 resets = <&teg
932 #power-domain-
933 };
934
935 pd_xusbhost: xusbc {
936 clocks = <&teg
937 resets = <&teg
938 #power-domain-
939 };
940 };
941 };
942
943 fuse@7000f800 {
944 compatible = "nvidia,tegra210-
945 reg = <0x0 0x7000f800 0x0 0x40
946 clocks = <&tegra_car TEGRA210_
947 clock-names = "fuse";
948 resets = <&tegra_car 39>;
949 reset-names = "fuse";
950 };
951
952 mc: memory-controller@70019000 {
953 compatible = "nvidia,tegra210-
954 reg = <0x0 0x70019000 0x0 0x10
955 clocks = <&tegra_car TEGRA210_
956 clock-names = "mc";
957
958 interrupts = <GIC_SPI 77 IRQ_T
959
960 #iommu-cells = <1>;
961 #reset-cells = <1>;
962 };
963
964 emc: external-memory-controller@7001b0
965 compatible = "nvidia,tegra210-
966 reg = <0x0 0x7001b000 0x0 0x10
967 <0x0 0x7001e000 0x0 0x10
968 <0x0 0x7001f000 0x0 0x10
969 clocks = <&tegra_car TEGRA210_
970 clock-names = "emc";
971 interrupts = <GIC_SPI 78 IRQ_T
972 nvidia,memory-controller = <&m
973 #cooling-cells = <2>;
974 };
975
976 sata@70020000 {
977 compatible = "nvidia,tegra210-
978 reg = <0x0 0x70027000 0x0 0x20
979 <0x0 0x70020000 0x0 0x70
980 <0x0 0x70001100 0x0 0x10
981 interrupts = <GIC_SPI 23 IRQ_T
982 clocks = <&tegra_car TEGRA210_
983 <&tegra_car TEGRA210_
984 clock-names = "sata", "sata-oo
985 resets = <&tegra_car 124>,
986 <&tegra_car 129>,
987 <&tegra_car 123>;
988 reset-names = "sata", "sata-co
989 status = "disabled";
990 };
991
992 hda@70030000 {
993 compatible = "nvidia,tegra210-
994 reg = <0x0 0x70030000 0x0 0x10
995 interrupts = <GIC_SPI 81 IRQ_T
996 clocks = <&tegra_car TEGRA210_
997 <&tegra_car TEGRA210_
998 <&tegra_car TEGRA210_
999 clock-names = "hda", "hda2hdmi
1000 resets = <&tegra_car 125>, /*
1001 <&tegra_car 128>, /*
1002 <&tegra_car 111>; /*
1003 reset-names = "hda", "hda2hdm
1004 power-domains = <&pd_sor>;
1005 status = "disabled";
1006 };
1007
1008 usb@70090000 {
1009 compatible = "nvidia,tegra210
1010 reg = <0x0 0x70090000 0x0 0x8
1011 <0x0 0x70098000 0x0 0x1
1012 <0x0 0x70099000 0x0 0x1
1013 reg-names = "hcd", "fpci", "i
1014
1015 interrupts = <GIC_SPI 39 IRQ_
1016 <GIC_SPI 40 IRQ_
1017
1018 clocks = <&tegra_car TEGRA210
1019 <&tegra_car TEGRA210
1020 <&tegra_car TEGRA210
1021 <&tegra_car TEGRA210
1022 <&tegra_car TEGRA210
1023 <&tegra_car TEGRA210
1024 <&tegra_car TEGRA210
1025 <&tegra_car TEGRA210
1026 <&tegra_car TEGRA210
1027 <&tegra_car TEGRA210
1028 <&tegra_car TEGRA210
1029 clock-names = "xusb_host", "x
1030 "xusb_falcon_sr
1031 "xusb_ss_div2",
1032 "xusb_hs_src",
1033 "pll_u_480m", "
1034 resets = <&tegra_car 89>, <&t
1035 <&tegra_car 143>;
1036 reset-names = "xusb_host", "x
1037 power-domains = <&pd_xusbhost
1038 power-domain-names = "xusb_ho
1039
1040 nvidia,xusb-padctl = <&padctl
1041
1042 status = "disabled";
1043 };
1044
1045 padctl: padctl@7009f000 {
1046 compatible = "nvidia,tegra210
1047 reg = <0x0 0x7009f000 0x0 0x1
1048 interrupts = <GIC_SPI 49 IRQ_
1049 resets = <&tegra_car 142>;
1050 reset-names = "padctl";
1051 nvidia,pmc = <&tegra_pmc>;
1052
1053 status = "disabled";
1054
1055 pads {
1056 usb2 {
1057 clocks = <&te
1058 clock-names =
1059 status = "dis
1060
1061 lanes {
1062 usb2-
1063
1064
1065 };
1066
1067 usb2-
1068
1069
1070 };
1071
1072 usb2-
1073
1074
1075 };
1076
1077 usb2-
1078
1079
1080 };
1081 };
1082 };
1083
1084 hsic {
1085 clocks = <&te
1086 clock-names =
1087 status = "dis
1088
1089 lanes {
1090 hsic-
1091
1092
1093 };
1094
1095 hsic-
1096
1097
1098 };
1099 };
1100 };
1101
1102 pcie {
1103 clocks = <&te
1104 clock-names =
1105 resets = <&te
1106 reset-names =
1107 status = "dis
1108
1109 lanes {
1110 pcie-
1111
1112
1113 };
1114
1115 pcie-
1116
1117
1118 };
1119
1120 pcie-
1121
1122
1123 };
1124
1125 pcie-
1126
1127
1128 };
1129
1130 pcie-
1131
1132
1133 };
1134
1135 pcie-
1136
1137
1138 };
1139
1140 pcie-
1141
1142
1143 };
1144 };
1145 };
1146
1147 sata {
1148 clocks = <&te
1149 clock-names =
1150 resets = <&te
1151 reset-names =
1152 status = "dis
1153
1154 lanes {
1155 sata-
1156
1157
1158 };
1159 };
1160 };
1161 };
1162
1163 ports {
1164 usb2-0 {
1165 status = "dis
1166 };
1167
1168 usb2-1 {
1169 status = "dis
1170 };
1171
1172 usb2-2 {
1173 status = "dis
1174 };
1175
1176 usb2-3 {
1177 status = "dis
1178 };
1179
1180 hsic-0 {
1181 status = "dis
1182 };
1183
1184 usb3-0 {
1185 status = "dis
1186 };
1187
1188 usb3-1 {
1189 status = "dis
1190 };
1191
1192 usb3-2 {
1193 status = "dis
1194 };
1195
1196 usb3-3 {
1197 status = "dis
1198 };
1199 };
1200 };
1201
1202 mmc@700b0000 {
1203 compatible = "nvidia,tegra210
1204 reg = <0x0 0x700b0000 0x0 0x2
1205 interrupts = <GIC_SPI 14 IRQ_
1206 clocks = <&tegra_car TEGRA210
1207 <&tegra_car TEGRA210
1208 clock-names = "sdhci", "tmclk
1209 resets = <&tegra_car 14>;
1210 reset-names = "sdhci";
1211 pinctrl-names = "sdmmc-3v3",
1212 "sdmmc-3v3-dr
1213 pinctrl-0 = <&sdmmc1_3v3>;
1214 pinctrl-1 = <&sdmmc1_1v8>;
1215 pinctrl-2 = <&sdmmc1_3v3_drv>
1216 pinctrl-3 = <&sdmmc1_1v8_drv>
1217 nvidia,pad-autocal-pull-up-of
1218 nvidia,pad-autocal-pull-down-
1219 nvidia,pad-autocal-pull-up-of
1220 nvidia,pad-autocal-pull-down-
1221 nvidia,default-tap = <0x2>;
1222 nvidia,default-trim = <0x4>;
1223 assigned-clocks = <&tegra_car
1224 <&tegra_car
1225 <&tegra_car
1226 assigned-clock-parents = <&te
1227 assigned-clock-rates = <20000
1228 status = "disabled";
1229 };
1230
1231 mmc@700b0200 {
1232 compatible = "nvidia,tegra210
1233 reg = <0x0 0x700b0200 0x0 0x2
1234 interrupts = <GIC_SPI 15 IRQ_
1235 clocks = <&tegra_car TEGRA210
1236 <&tegra_car TEGRA210
1237 clock-names = "sdhci", "tmclk
1238 resets = <&tegra_car 9>;
1239 reset-names = "sdhci";
1240 pinctrl-names = "sdmmc-1v8-dr
1241 pinctrl-0 = <&sdmmc2_1v8_drv>
1242 nvidia,pad-autocal-pull-up-of
1243 nvidia,pad-autocal-pull-down-
1244 nvidia,default-tap = <0x8>;
1245 nvidia,default-trim = <0x0>;
1246 status = "disabled";
1247 };
1248
1249 mmc@700b0400 {
1250 compatible = "nvidia,tegra210
1251 reg = <0x0 0x700b0400 0x0 0x2
1252 interrupts = <GIC_SPI 19 IRQ_
1253 clocks = <&tegra_car TEGRA210
1254 <&tegra_car TEGRA210
1255 clock-names = "sdhci", "tmclk
1256 resets = <&tegra_car 69>;
1257 reset-names = "sdhci";
1258 pinctrl-names = "sdmmc-3v3",
1259 "sdmmc-3v3-dr
1260 pinctrl-0 = <&sdmmc3_3v3>;
1261 pinctrl-1 = <&sdmmc3_1v8>;
1262 pinctrl-2 = <&sdmmc3_3v3_drv>
1263 pinctrl-3 = <&sdmmc3_1v8_drv>
1264 nvidia,pad-autocal-pull-up-of
1265 nvidia,pad-autocal-pull-down-
1266 nvidia,pad-autocal-pull-up-of
1267 nvidia,pad-autocal-pull-down-
1268 nvidia,default-tap = <0x3>;
1269 nvidia,default-trim = <0x3>;
1270 status = "disabled";
1271 };
1272
1273 mmc@700b0600 {
1274 compatible = "nvidia,tegra210
1275 reg = <0x0 0x700b0600 0x0 0x2
1276 interrupts = <GIC_SPI 31 IRQ_
1277 clocks = <&tegra_car TEGRA210
1278 <&tegra_car TEGRA210
1279 clock-names = "sdhci", "tmclk
1280 resets = <&tegra_car 15>;
1281 reset-names = "sdhci";
1282 pinctrl-names = "sdmmc-3v3-dr
1283 pinctrl-0 = <&sdmmc4_1v8_drv>
1284 pinctrl-1 = <&sdmmc4_1v8_drv>
1285 nvidia,pad-autocal-pull-up-of
1286 nvidia,pad-autocal-pull-down-
1287 nvidia,default-tap = <0x8>;
1288 nvidia,default-trim = <0x0>;
1289 assigned-clocks = <&tegra_car
1290 <&tegra_car
1291 assigned-clock-parents = <&te
1292 nvidia,dqs-trim = <40>;
1293 mmc-hs400-1_8v;
1294 status = "disabled";
1295 };
1296
1297 usb@700d0000 {
1298 compatible = "nvidia,tegra210
1299 reg = <0x0 0x700d0000 0x0 0x8
1300 <0x0 0x700d8000 0x0 0x1
1301 <0x0 0x700d9000 0x0 0x1
1302 reg-names = "base", "fpci", "
1303 interrupts = <GIC_SPI 44 IRQ_
1304 clocks = <&tegra_car TEGRA210
1305 <&tegra_car TEGRA210
1306 <&tegra_car TEGRA210
1307 <&tegra_car TEGRA210
1308 <&tegra_car TEGRA210
1309 clock-names = "dev", "ss", "s
1310 power-domains = <&pd_xusbdev>
1311 power-domain-names = "dev", "
1312 nvidia,xusb-padctl = <&padctl
1313 status = "disabled";
1314 };
1315
1316 soctherm: thermal-sensor@700e2000 {
1317 compatible = "nvidia,tegra210
1318 reg = <0x0 0x700e2000 0x0 0x6
1319 <0x0 0x60006000 0x0 0x4
1320 reg-names = "soctherm-reg", "
1321 interrupts = <GIC_SPI 48 IRQ_
1322 <GIC_SPI 51 IRQ_
1323 interrupt-names = "thermal",
1324 clocks = <&tegra_car TEGRA210
1325 <&tegra_car TEGRA210_
1326 clock-names = "tsensor", "soc
1327 resets = <&tegra_car 78>;
1328 reset-names = "soctherm";
1329 #thermal-sensor-cells = <1>;
1330
1331 throttle-cfgs {
1332 throttle_heavy: heavy
1333 nvidia,priori
1334 nvidia,cpu-th
1335 nvidia,gpu-th
1336
1337 #cooling-cell
1338 };
1339 };
1340 };
1341
1342 mipi: mipi@700e3000 {
1343 compatible = "nvidia,tegra210
1344 reg = <0x0 0x700e3000 0x0 0x1
1345 clocks = <&tegra_car TEGRA210
1346 clock-names = "mipi-cal";
1347 power-domains = <&pd_sor>;
1348 #nvidia,mipi-calibrate-cells
1349 };
1350
1351 dfll: clock@70110000 {
1352 compatible = "nvidia,tegra210
1353 reg = <0 0x70110000 0 0x100>,
1354 <0 0x70110000 0 0x100>,
1355 <0 0x70110100 0 0x100>,
1356 <0 0x70110200 0 0x100>;
1357 interrupts = <GIC_SPI 62 IRQ_
1358 clocks = <&tegra_car TEGRA210
1359 <&tegra_car TEGRA210
1360 <&tegra_car TEGRA210
1361 clock-names = "soc", "ref", "
1362 resets = <&tegra_car TEGRA210
1363 <&tegra_car 155>;
1364 reset-names = "dvco", "dfll";
1365 #clock-cells = <0>;
1366 clock-output-names = "dfllCPU
1367 status = "disabled";
1368 };
1369
1370 aconnect@702c0000 {
1371 compatible = "nvidia,tegra210
1372 clocks = <&tegra_car TEGRA210
1373 <&tegra_car TEGRA210
1374 clock-names = "ape", "apb2ape
1375 power-domains = <&pd_audio>;
1376 #address-cells = <1>;
1377 #size-cells = <1>;
1378 ranges = <0x702c0000 0x0 0x70
1379 status = "disabled";
1380
1381 tegra_ahub: ahub@702d0800 {
1382 compatible = "nvidia,
1383 reg = <0x702d0800 0x8
1384 clocks = <&tegra_car
1385 clock-names = "ahub";
1386 assigned-clocks = <&t
1387 assigned-clock-parent
1388 assigned-clock-rates
1389 #address-cells = <1>;
1390 #size-cells = <1>;
1391 ranges = <0x702d0000
1392 status = "disabled";
1393
1394 tegra_admaif: admaif@
1395 compatible =
1396 reg = <0x702d
1397 dmas = <&adma
1398 <&adma
1399 <&adma
1400 <&adma
1401 <&adma
1402 <&adma
1403 <&adma
1404 <&adma
1405 <&adma
1406 <&adma
1407 dma-names = "
1408 "
1409 "
1410 "
1411 "
1412 "
1413 "
1414 "
1415 "
1416 "
1417 status = "dis
1418
1419 ports {
1420 #addr
1421 #size
1422
1423 admai
1424
1425
1426
1427
1428
1429 };
1430
1431 admai
1432
1433
1434
1435
1436
1437 };
1438
1439 admai
1440
1441
1442
1443
1444
1445 };
1446
1447 admai
1448
1449
1450
1451
1452
1453 };
1454
1455 admai
1456
1457
1458
1459
1460
1461 };
1462
1463 admai
1464
1465
1466
1467
1468
1469 };
1470
1471 admai
1472
1473
1474
1475
1476
1477 };
1478
1479 admai
1480
1481
1482
1483
1484
1485 };
1486
1487 admai
1488
1489
1490
1491
1492
1493 };
1494
1495 admai
1496
1497
1498
1499
1500
1501 };
1502 };
1503 };
1504
1505 tegra_i2s1: i2s@702d1
1506 compatible =
1507 reg = <0x702d
1508 clocks = <&te
1509 <&te
1510 clock-names =
1511 assigned-cloc
1512 assigned-cloc
1513 assigned-cloc
1514 sound-name-pr
1515 status = "dis
1516 };
1517
1518 tegra_i2s2: i2s@702d1
1519 compatible =
1520 reg = <0x702d
1521 clocks = <&te
1522 <&te
1523 clock-names =
1524 assigned-cloc
1525 assigned-cloc
1526 assigned-cloc
1527 sound-name-pr
1528 status = "dis
1529 };
1530
1531 tegra_i2s3: i2s@702d1
1532 compatible =
1533 reg = <0x702d
1534 clocks = <&te
1535 <&te
1536 clock-names =
1537 assigned-cloc
1538 assigned-cloc
1539 assigned-cloc
1540 sound-name-pr
1541 status = "dis
1542 };
1543
1544 tegra_i2s4: i2s@702d1
1545 compatible =
1546 reg = <0x702d
1547 clocks = <&te
1548 <&te
1549 clock-names =
1550 assigned-cloc
1551 assigned-cloc
1552 assigned-cloc
1553 sound-name-pr
1554 status = "dis
1555 };
1556
1557 tegra_i2s5: i2s@702d1
1558 compatible =
1559 reg = <0x702d
1560 clocks = <&te
1561 <&te
1562 clock-names =
1563 assigned-cloc
1564 assigned-cloc
1565 assigned-cloc
1566 sound-name-pr
1567 status = "dis
1568 };
1569
1570 tegra_sfc1: sfc@702d2
1571 compatible =
1572 reg = <0x702d
1573 sound-name-pr
1574 status = "dis
1575 };
1576
1577 tegra_sfc2: sfc@702d2
1578 compatible =
1579 reg = <0x702d
1580 sound-name-pr
1581 status = "dis
1582 };
1583
1584 tegra_sfc3: sfc@702d2
1585 compatible =
1586 reg = <0x702d
1587 sound-name-pr
1588 status = "dis
1589 };
1590
1591 tegra_sfc4: sfc@702d2
1592 compatible =
1593 reg = <0x702d
1594 sound-name-pr
1595 status = "dis
1596 };
1597
1598 tegra_amx1: amx@702d3
1599 compatible =
1600 reg = <0x702d
1601 sound-name-pr
1602 status = "dis
1603 };
1604
1605 tegra_amx2: amx@702d3
1606 compatible =
1607 reg = <0x702d
1608 sound-name-pr
1609 status = "dis
1610 };
1611
1612 tegra_adx1: adx@702d3
1613 compatible =
1614 reg = <0x702d
1615 sound-name-pr
1616 status = "dis
1617 };
1618
1619 tegra_adx2: adx@702d3
1620 compatible =
1621 reg = <0x702d
1622 sound-name-pr
1623 status = "dis
1624 };
1625
1626 tegra_dmic1: dmic@702
1627 compatible =
1628 reg = <0x702d
1629 clocks = <&te
1630 clock-names =
1631 assigned-cloc
1632 assigned-cloc
1633 assigned-cloc
1634 sound-name-pr
1635 status = "dis
1636 };
1637
1638 tegra_dmic2: dmic@702
1639 compatible =
1640 reg = <0x702d
1641 clocks = <&te
1642 clock-names =
1643 assigned-cloc
1644 assigned-cloc
1645 assigned-cloc
1646 sound-name-pr
1647 status = "dis
1648 };
1649
1650 tegra_dmic3: dmic@702
1651 compatible =
1652 reg = <0x702d
1653 clocks = <&te
1654 clock-names =
1655 assigned-cloc
1656 assigned-cloc
1657 assigned-cloc
1658 sound-name-pr
1659 status = "dis
1660 };
1661
1662 tegra_ope1: processin
1663 compatible =
1664 reg = <0x702d
1665 #address-cell
1666 #size-cells =
1667 ranges;
1668 sound-name-pr
1669 status = "dis
1670
1671 equalizer@702
1672 compa
1673 reg =
1674 };
1675
1676 dynamic-range
1677 compa
1678 reg =
1679 };
1680 };
1681
1682 tegra_ope2: processin
1683 compatible =
1684 reg = <0x702d
1685 #address-cell
1686 #size-cells =
1687 ranges;
1688 sound-name-pr
1689 status = "dis
1690
1691 equalizer@702
1692 compa
1693 reg =
1694 };
1695
1696 dynamic-range
1697 compa
1698 reg =
1699 };
1700 };
1701
1702 tegra_mvc1: mvc@702da
1703 compatible =
1704 reg = <0x702d
1705 sound-name-pr
1706 status = "dis
1707 };
1708
1709 tegra_mvc2: mvc@702da
1710 compatible =
1711 reg = <0x702d
1712 sound-name-pr
1713 status = "dis
1714 };
1715
1716 tegra_amixer: amixer@
1717 compatible =
1718 reg = <0x702d
1719 sound-name-pr
1720 status = "dis
1721 };
1722
1723 ports {
1724 #address-cell
1725 #size-cells =
1726
1727 port@0 {
1728 reg =
1729
1730 xbar_
1731
1732 };
1733 };
1734
1735 port@1 {
1736 reg =
1737
1738 xbar_
1739
1740 };
1741 };
1742
1743 port@2 {
1744 reg =
1745
1746 xbar_
1747
1748 };
1749 };
1750
1751 port@3 {
1752 reg =
1753
1754 xbar_
1755
1756 };
1757 };
1758
1759 port@4 {
1760 reg =
1761 xbar_
1762
1763 };
1764 };
1765 port@5 {
1766 reg =
1767
1768 xbar_
1769
1770 };
1771 };
1772
1773 port@6 {
1774 reg =
1775
1776 xbar_
1777
1778 };
1779 };
1780
1781 port@7 {
1782 reg =
1783
1784 xbar_
1785
1786 };
1787 };
1788
1789 port@8 {
1790 reg =
1791
1792 xbar_
1793
1794 };
1795 };
1796
1797 port@9 {
1798 reg =
1799
1800 xbar_
1801
1802 };
1803 };
1804 };
1805 };
1806
1807 adma: dma-controller@702e2000
1808 compatible = "nvidia,
1809 reg = <0x702e2000 0x2
1810 interrupt-parent = <&
1811 interrupts = <GIC_SPI
1812 <GIC_SPI
1813 <GIC_SPI
1814 <GIC_SPI
1815 <GIC_SPI
1816 <GIC_SPI
1817 <GIC_SPI
1818 <GIC_SPI
1819 <GIC_SPI
1820 <GIC_SPI
1821 <GIC_SPI
1822 <GIC_SPI
1823 <GIC_SPI
1824 <GIC_SPI
1825 <GIC_SPI
1826 <GIC_SPI
1827 <GIC_SPI
1828 <GIC_SPI
1829 <GIC_SPI
1830 <GIC_SPI
1831 <GIC_SPI
1832 <GIC_SPI
1833 #dma-cells = <1>;
1834 clocks = <&tegra_car
1835 clock-names = "d_audi
1836 status = "disabled";
1837 };
1838
1839 agic: interrupt-controller@70
1840 compatible = "nvidia,
1841 #interrupt-cells = <3
1842 interrupt-controller;
1843 reg = <0x702f9000 0x1
1844 <0x702fa000 0x2
1845 interrupts = <GIC_SPI
1846 clocks = <&tegra_car
1847 clock-names = "clk";
1848 status = "disabled";
1849 };
1850 };
1851
1852 spi@70410000 {
1853 compatible = "nvidia,tegra210
1854 reg = <0x0 0x70410000 0x0 0x1
1855 interrupts = <GIC_SPI 10 IRQ_
1856 #address-cells = <1>;
1857 #size-cells = <0>;
1858 clocks = <&tegra_car TEGRA210
1859 <&tegra_car TEGRA210
1860 clock-names = "qspi", "qspi_o
1861 resets = <&tegra_car 211>;
1862 dmas = <&apbdma 5>, <&apbdma
1863 dma-names = "rx", "tx";
1864 status = "disabled";
1865 };
1866
1867 usb@7d000000 {
1868 compatible = "nvidia,tegra210
1869 reg = <0x0 0x7d000000 0x0 0x4
1870 interrupts = <GIC_SPI 20 IRQ_
1871 phy_type = "utmi";
1872 clocks = <&tegra_car TEGRA210
1873 clock-names = "usb";
1874 resets = <&tegra_car 22>;
1875 reset-names = "usb";
1876 nvidia,phy = <&phy1>;
1877 status = "disabled";
1878 };
1879
1880 phy1: usb-phy@7d000000 {
1881 compatible = "nvidia,tegra210
1882 reg = <0x0 0x7d000000 0x0 0x4
1883 <0x0 0x7d000000 0x0 0x4
1884 phy_type = "utmi";
1885 clocks = <&tegra_car TEGRA210
1886 <&tegra_car TEGRA210
1887 <&tegra_car TEGRA210
1888 clock-names = "reg", "pll_u",
1889 resets = <&tegra_car 22>, <&t
1890 reset-names = "usb", "utmi-pa
1891 nvidia,hssync-start-delay = <
1892 nvidia,idle-wait-delay = <17>
1893 nvidia,elastic-limit = <16>;
1894 nvidia,term-range-adj = <6>;
1895 nvidia,xcvr-setup = <9>;
1896 nvidia,xcvr-lsfslew = <0>;
1897 nvidia,xcvr-lsrslew = <3>;
1898 nvidia,hssquelch-level = <2>;
1899 nvidia,hsdiscon-level = <5>;
1900 nvidia,xcvr-hsslew = <12>;
1901 nvidia,has-utmi-pad-registers
1902 status = "disabled";
1903 };
1904
1905 usb@7d004000 {
1906 compatible = "nvidia,tegra210
1907 reg = <0x0 0x7d004000 0x0 0x4
1908 interrupts = <GIC_SPI 21 IRQ_
1909 phy_type = "utmi";
1910 clocks = <&tegra_car TEGRA210
1911 clock-names = "usb";
1912 resets = <&tegra_car 58>;
1913 reset-names = "usb";
1914 nvidia,phy = <&phy2>;
1915 status = "disabled";
1916 };
1917
1918 phy2: usb-phy@7d004000 {
1919 compatible = "nvidia,tegra210
1920 reg = <0x0 0x7d004000 0x0 0x4
1921 <0x0 0x7d000000 0x0 0x4
1922 phy_type = "utmi";
1923 clocks = <&tegra_car TEGRA210
1924 <&tegra_car TEGRA210
1925 <&tegra_car TEGRA210
1926 clock-names = "reg", "pll_u",
1927 resets = <&tegra_car 58>, <&t
1928 reset-names = "usb", "utmi-pa
1929 nvidia,hssync-start-delay = <
1930 nvidia,idle-wait-delay = <17>
1931 nvidia,elastic-limit = <16>;
1932 nvidia,term-range-adj = <6>;
1933 nvidia,xcvr-setup = <9>;
1934 nvidia,xcvr-lsfslew = <0>;
1935 nvidia,xcvr-lsrslew = <3>;
1936 nvidia,hssquelch-level = <2>;
1937 nvidia,hsdiscon-level = <5>;
1938 nvidia,xcvr-hsslew = <12>;
1939 status = "disabled";
1940 };
1941
1942 cpus {
1943 #address-cells = <1>;
1944 #size-cells = <0>;
1945
1946 cpu@0 {
1947 device_type = "cpu";
1948 compatible = "arm,cor
1949 reg = <0>;
1950 clocks = <&tegra_car
1951 <&tegra_car
1952 <&tegra_car
1953 <&dfll>;
1954 clock-names = "cpu_g"
1955 clock-latency = <3000
1956 cpu-idle-states = <&C
1957 next-level-cache = <&
1958 };
1959
1960 cpu@1 {
1961 device_type = "cpu";
1962 compatible = "arm,cor
1963 reg = <1>;
1964 cpu-idle-states = <&C
1965 next-level-cache = <&
1966 };
1967
1968 cpu@2 {
1969 device_type = "cpu";
1970 compatible = "arm,cor
1971 reg = <2>;
1972 cpu-idle-states = <&C
1973 next-level-cache = <&
1974 };
1975
1976 cpu@3 {
1977 device_type = "cpu";
1978 compatible = "arm,cor
1979 reg = <3>;
1980 cpu-idle-states = <&C
1981 next-level-cache = <&
1982 };
1983
1984 idle-states {
1985 entry-method = "psci"
1986
1987 CPU_SLEEP: cpu-sleep
1988 compatible =
1989 arm,psci-susp
1990 entry-latency
1991 exit-latency-
1992 min-residency
1993 wakeup-latenc
1994 idle-state-na
1995 status = "dis
1996 };
1997 };
1998
1999 L2: l2-cache {
2000 compatible = "cache";
2001 cache-level = <2>;
2002 cache-unified;
2003 };
2004 };
2005
2006 pmu {
2007 compatible = "arm,cortex-a57-
2008 interrupts = <GIC_SPI 144 IRQ
2009 <GIC_SPI 145 IRQ
2010 <GIC_SPI 146 IRQ
2011 <GIC_SPI 147 IRQ
2012 interrupt-affinity = <&{/cpus
2013 &{/cpus
2014 };
2015
2016 sound {
2017 status = "disabled";
2018
2019 clocks = <&tegra_car TEGRA210
2020 <&tegra_car TEGRA210
2021 clock-names = "pll_a", "plla_
2022
2023 assigned-clocks = <&tegra_car
2024 <&tegra_car
2025 <&tegra_car
2026 assigned-clock-parents = <0>,
2027 assigned-clock-rates = <36864
2028 };
2029
2030 thermal-zones {
2031 cpu-thermal {
2032 polling-delay-passive
2033 polling-delay = <0>;
2034
2035 thermal-sensors =
2036 <&soctherm TE
2037
2038 trips {
2039 cpu-shutdown-
2040 tempe
2041 hyste
2042 type
2043 };
2044
2045 cpu_throttle_
2046 tempe
2047 hyste
2048 type
2049 };
2050 };
2051
2052 cooling-maps {
2053 map0 {
2054 trip
2055 cooli
2056 };
2057 };
2058 };
2059
2060 mem-thermal {
2061 polling-delay-passive
2062 polling-delay = <0>;
2063
2064 thermal-sensors =
2065 <&soctherm TE
2066
2067 trips {
2068 dram_nominal:
2069 tempe
2070 hyste
2071 type
2072 };
2073
2074 dram_throttle
2075 tempe
2076 hyste
2077 type
2078 };
2079
2080 mem-hot-trip
2081 tempe
2082 hyste
2083 type
2084 };
2085
2086 mem-shutdown-
2087 tempe
2088 hyste
2089 type
2090 };
2091 };
2092
2093 cooling-maps {
2094 dram-passive
2095 cooli
2096 trip
2097 };
2098
2099 dram-active {
2100 cooli
2101 trip
2102 };
2103 };
2104 };
2105
2106 gpu-thermal {
2107 polling-delay-passive
2108 polling-delay = <0>;
2109
2110 thermal-sensors =
2111 <&soctherm TE
2112
2113 trips {
2114 gpu-shutdown-
2115 tempe
2116 hyste
2117 type
2118 };
2119
2120 gpu_throttle_
2121 tempe
2122 hyste
2123 type
2124 };
2125 };
2126
2127 cooling-maps {
2128 map0 {
2129 trip
2130 cooli
2131 };
2132 };
2133 };
2134
2135 pllx-thermal {
2136 polling-delay-passive
2137 polling-delay = <0>;
2138
2139 thermal-sensors =
2140 <&soctherm TE
2141
2142 trips {
2143 pllx-shutdown
2144 tempe
2145 hyste
2146 type
2147 };
2148
2149 pllx-throttle
2150 tempe
2151 hyste
2152 type
2153 };
2154 };
2155
2156 cooling-maps {
2157 /*
2158 * There are
2159 * because th
2160 */
2161 };
2162 };
2163 };
2164
2165 timer {
2166 compatible = "arm,armv8-timer
2167 interrupts = <GIC_PPI 13
2168 (GIC_CPU_MASK
2169 <GIC_PPI 14
2170 (GIC_CPU_MASK
2171 <GIC_PPI 11
2172 (GIC_CPU_MASK
2173 <GIC_PPI 10
2174 (GIC_CPU_MASK
2175 interrupt-parent = <&gic>;
2176 arm,no-tick-in-suspend;
2177 };
2178 };
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