1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra210-car.h> 2 #include <dt-bindings/clock/tegra210-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h> 3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra210-mc.h> 4 #include <dt-bindings/memory/tegra210-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h> 5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra-io <<
7 #include <dt-bindings/reset/tegra210-car.h> <<
8 #include <dt-bindings/interrupt-controller/arm 6 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/thermal/tegra124-socther 7 #include <dt-bindings/thermal/tegra124-soctherm.h>
10 #include <dt-bindings/soc/tegra-pmc.h> <<
11 8
12 / { 9 / {
13 compatible = "nvidia,tegra210"; 10 compatible = "nvidia,tegra210";
14 interrupt-parent = <&lic>; 11 interrupt-parent = <&lic>;
15 #address-cells = <2>; 12 #address-cells = <2>;
16 #size-cells = <2>; 13 #size-cells = <2>;
17 14
18 pcie@1003000 { 15 pcie@1003000 {
19 compatible = "nvidia,tegra210- 16 compatible = "nvidia,tegra210-pcie";
20 device_type = "pci"; 17 device_type = "pci";
21 reg = <0x0 0x01003000 0x0 0x00 !! 18 reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */
22 <0x0 0x01003800 0x0 0x00 !! 19 0x0 0x01003800 0x0 0x00000800 /* AFI registers */
23 <0x0 0x02000000 0x0 0x10 !! 20 0x0 0x02000000 0x0 0x10000000>; /* configuration space */
24 reg-names = "pads", "afi", "cs 21 reg-names = "pads", "afi", "cs";
25 interrupts = <GIC_SPI 98 IRQ_T 22 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
26 <GIC_SPI 99 IRQ_T 23 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
27 interrupt-names = "intr", "msi 24 interrupt-names = "intr", "msi";
28 25
29 #interrupt-cells = <1>; 26 #interrupt-cells = <1>;
30 interrupt-map-mask = <0 0 0 0> 27 interrupt-map-mask = <0 0 0 0>;
31 interrupt-map = <0 0 0 0 &gic 28 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
32 29
33 bus-range = <0x00 0xff>; 30 bus-range = <0x00 0xff>;
34 #address-cells = <3>; 31 #address-cells = <3>;
35 #size-cells = <2>; 32 #size-cells = <2>;
36 33
37 ranges = <0x02000000 0 0x01000 !! 34 ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000 /* port 0 configuration space */
38 <0x02000000 0 0x01001 !! 35 0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000 /* port 1 configuration space */
39 <0x01000000 0 0x0 !! 36 0x81000000 0 0x0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */
40 <0x02000000 0 0x13000 !! 37 0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */
41 <0x42000000 0 0x20000 !! 38 0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
42 39
43 clocks = <&tegra_car TEGRA210_ 40 clocks = <&tegra_car TEGRA210_CLK_PCIE>,
44 <&tegra_car TEGRA210_ 41 <&tegra_car TEGRA210_CLK_AFI>,
45 <&tegra_car TEGRA210_ 42 <&tegra_car TEGRA210_CLK_PLL_E>,
46 <&tegra_car TEGRA210_ 43 <&tegra_car TEGRA210_CLK_CML0>;
47 clock-names = "pex", "afi", "p 44 clock-names = "pex", "afi", "pll_e", "cml";
48 resets = <&tegra_car 70>, 45 resets = <&tegra_car 70>,
49 <&tegra_car 72>, 46 <&tegra_car 72>,
50 <&tegra_car 74>; 47 <&tegra_car 74>;
51 reset-names = "pex", "afi", "p 48 reset-names = "pex", "afi", "pcie_x";
52 <<
53 pinctrl-names = "default", "id <<
54 pinctrl-0 = <&pex_dpd_disable> <<
55 pinctrl-1 = <&pex_dpd_enable>; <<
56 <<
57 status = "disabled"; 49 status = "disabled";
58 50
59 pci@1,0 { 51 pci@1,0 {
60 device_type = "pci"; 52 device_type = "pci";
61 assigned-addresses = < 53 assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
62 reg = <0x000800 0 0 0 54 reg = <0x000800 0 0 0 0>;
63 bus-range = <0x00 0xff 55 bus-range = <0x00 0xff>;
64 status = "disabled"; 56 status = "disabled";
65 57
66 #address-cells = <3>; 58 #address-cells = <3>;
67 #size-cells = <2>; 59 #size-cells = <2>;
68 ranges; 60 ranges;
69 61
70 nvidia,num-lanes = <4> 62 nvidia,num-lanes = <4>;
71 }; 63 };
72 64
73 pci@2,0 { 65 pci@2,0 {
74 device_type = "pci"; 66 device_type = "pci";
75 assigned-addresses = < 67 assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
76 reg = <0x001000 0 0 0 68 reg = <0x001000 0 0 0 0>;
77 bus-range = <0x00 0xff 69 bus-range = <0x00 0xff>;
78 status = "disabled"; 70 status = "disabled";
79 71
80 #address-cells = <3>; 72 #address-cells = <3>;
81 #size-cells = <2>; 73 #size-cells = <2>;
82 ranges; 74 ranges;
83 75
84 nvidia,num-lanes = <1> 76 nvidia,num-lanes = <1>;
85 }; 77 };
86 }; 78 };
87 79
88 host1x@50000000 { 80 host1x@50000000 {
89 compatible = "nvidia,tegra210- !! 81 compatible = "nvidia,tegra210-host1x", "simple-bus";
90 reg = <0x0 0x50000000 0x0 0x00 82 reg = <0x0 0x50000000 0x0 0x00034000>;
91 interrupts = <GIC_SPI 65 IRQ_T 83 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
92 <GIC_SPI 67 IRQ_T 84 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
93 interrupt-names = "syncpt", "h <<
94 clocks = <&tegra_car TEGRA210_ 85 clocks = <&tegra_car TEGRA210_CLK_HOST1X>;
95 clock-names = "host1x"; 86 clock-names = "host1x";
96 resets = <&tegra_car 28>, <&mc !! 87 resets = <&tegra_car 28>;
97 reset-names = "host1x", "mc"; !! 88 reset-names = "host1x";
98 89
99 #address-cells = <2>; 90 #address-cells = <2>;
100 #size-cells = <2>; 91 #size-cells = <2>;
101 92
102 ranges = <0x0 0x54000000 0x0 0 93 ranges = <0x0 0x54000000 0x0 0x54000000 0x0 0x01000000>;
103 94
104 iommus = <&mc TEGRA_SWGROUP_HC 95 iommus = <&mc TEGRA_SWGROUP_HC>;
105 96
106 dpaux1: dpaux@54040000 { 97 dpaux1: dpaux@54040000 {
107 compatible = "nvidia,t 98 compatible = "nvidia,tegra210-dpaux";
108 reg = <0x0 0x54040000 99 reg = <0x0 0x54040000 0x0 0x00040000>;
109 interrupts = <GIC_SPI 100 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
110 clocks = <&tegra_car T 101 clocks = <&tegra_car TEGRA210_CLK_DPAUX1>,
111 <&tegra_car T 102 <&tegra_car TEGRA210_CLK_PLL_DP>;
112 clock-names = "dpaux", 103 clock-names = "dpaux", "parent";
113 resets = <&tegra_car 2 104 resets = <&tegra_car 207>;
114 reset-names = "dpaux"; 105 reset-names = "dpaux";
115 power-domains = <&pd_s 106 power-domains = <&pd_sor>;
116 status = "disabled"; 107 status = "disabled";
117 108
118 state_dpaux1_aux: pinm 109 state_dpaux1_aux: pinmux-aux {
119 groups = "dpau 110 groups = "dpaux-io";
120 function = "au 111 function = "aux";
121 }; 112 };
122 113
123 state_dpaux1_i2c: pinm 114 state_dpaux1_i2c: pinmux-i2c {
124 groups = "dpau 115 groups = "dpaux-io";
125 function = "i2 116 function = "i2c";
126 }; 117 };
127 118
128 state_dpaux1_off: pinm 119 state_dpaux1_off: pinmux-off {
129 groups = "dpau 120 groups = "dpaux-io";
130 function = "of 121 function = "off";
131 }; 122 };
132 123
133 i2c-bus { 124 i2c-bus {
134 #address-cells 125 #address-cells = <1>;
135 #size-cells = 126 #size-cells = <0>;
136 }; 127 };
137 }; 128 };
138 129
139 vi@54080000 { 130 vi@54080000 {
140 compatible = "nvidia,t 131 compatible = "nvidia,tegra210-vi";
141 reg = <0x0 0x54080000 !! 132 reg = <0x0 0x54080000 0x0 0x00040000>;
142 interrupts = <GIC_SPI 133 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
143 status = "disabled"; 134 status = "disabled";
144 assigned-clocks = <&te <<
145 assigned-clock-parents <<
146 <<
147 clocks = <&tegra_car T <<
148 power-domains = <&pd_v <<
149 <<
150 #address-cells = <1>; <<
151 #size-cells = <1>; <<
152 <<
153 ranges = <0x0 0x0 0x54 <<
154 <<
155 csi@838 { <<
156 compatible = " <<
157 reg = <0x838 0 <<
158 status = "disa <<
159 assigned-clock <<
160 <<
161 <<
162 <<
163 assigned-clock <<
164 <<
165 <<
166 assigned-clock <<
167 <<
168 <<
169 <<
170 <<
171 clocks = <&teg <<
172 <&teg <<
173 <&teg <<
174 <&teg <<
175 <&teg <<
176 clock-names = <<
177 power-domains <<
178 }; <<
179 }; 135 };
180 136
181 tsec@54100000 { 137 tsec@54100000 {
182 compatible = "nvidia,t 138 compatible = "nvidia,tegra210-tsec";
183 reg = <0x0 0x54100000 139 reg = <0x0 0x54100000 0x0 0x00040000>;
184 interrupts = <GIC_SPI <<
185 clocks = <&tegra_car T <<
186 clock-names = "tsec"; <<
187 resets = <&tegra_car 8 <<
188 reset-names = "tsec"; <<
189 status = "disabled"; <<
190 }; 140 };
191 141
192 dc@54200000 { 142 dc@54200000 {
193 compatible = "nvidia,t 143 compatible = "nvidia,tegra210-dc";
194 reg = <0x0 0x54200000 144 reg = <0x0 0x54200000 0x0 0x00040000>;
195 interrupts = <GIC_SPI 145 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
196 clocks = <&tegra_car T !! 146 clocks = <&tegra_car TEGRA210_CLK_DISP1>,
197 clock-names = "dc"; !! 147 <&tegra_car TEGRA210_CLK_PLL_P>;
>> 148 clock-names = "dc", "parent";
198 resets = <&tegra_car 2 149 resets = <&tegra_car 27>;
199 reset-names = "dc"; 150 reset-names = "dc";
200 151
201 iommus = <&mc TEGRA_SW 152 iommus = <&mc TEGRA_SWGROUP_DC>;
202 153
203 nvidia,outputs = <&dsi <<
204 nvidia,head = <0>; 154 nvidia,head = <0>;
205 }; 155 };
206 156
207 dc@54240000 { 157 dc@54240000 {
208 compatible = "nvidia,t 158 compatible = "nvidia,tegra210-dc";
209 reg = <0x0 0x54240000 159 reg = <0x0 0x54240000 0x0 0x00040000>;
210 interrupts = <GIC_SPI 160 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
211 clocks = <&tegra_car T !! 161 clocks = <&tegra_car TEGRA210_CLK_DISP2>,
212 clock-names = "dc"; !! 162 <&tegra_car TEGRA210_CLK_PLL_P>;
>> 163 clock-names = "dc", "parent";
213 resets = <&tegra_car 2 164 resets = <&tegra_car 26>;
214 reset-names = "dc"; 165 reset-names = "dc";
215 166
216 iommus = <&mc TEGRA_SW 167 iommus = <&mc TEGRA_SWGROUP_DCB>;
217 168
218 nvidia,outputs = <&dsi <<
219 nvidia,head = <1>; 169 nvidia,head = <1>;
220 }; 170 };
221 171
222 dsia: dsi@54300000 { !! 172 dsi@54300000 {
223 compatible = "nvidia,t 173 compatible = "nvidia,tegra210-dsi";
224 reg = <0x0 0x54300000 174 reg = <0x0 0x54300000 0x0 0x00040000>;
225 clocks = <&tegra_car T 175 clocks = <&tegra_car TEGRA210_CLK_DSIA>,
226 <&tegra_car T 176 <&tegra_car TEGRA210_CLK_DSIALP>,
227 <&tegra_car T 177 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>;
228 clock-names = "dsi", " 178 clock-names = "dsi", "lp", "parent";
229 resets = <&tegra_car 4 179 resets = <&tegra_car 48>;
230 reset-names = "dsi"; 180 reset-names = "dsi";
231 power-domains = <&pd_s 181 power-domains = <&pd_sor>;
232 nvidia,mipi-calibrate 182 nvidia,mipi-calibrate = <&mipi 0x0c0>; /* DSIA & DSIB pads */
233 183
234 status = "disabled"; 184 status = "disabled";
235 185
236 #address-cells = <1>; 186 #address-cells = <1>;
237 #size-cells = <0>; 187 #size-cells = <0>;
238 }; 188 };
239 189
240 vic@54340000 { 190 vic@54340000 {
241 compatible = "nvidia,t 191 compatible = "nvidia,tegra210-vic";
242 reg = <0x0 0x54340000 192 reg = <0x0 0x54340000 0x0 0x00040000>;
243 interrupts = <GIC_SPI 193 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
244 clocks = <&tegra_car T 194 clocks = <&tegra_car TEGRA210_CLK_VIC03>;
245 clock-names = "vic"; 195 clock-names = "vic";
246 resets = <&tegra_car 1 196 resets = <&tegra_car 178>;
247 reset-names = "vic"; 197 reset-names = "vic";
248 198
249 iommus = <&mc TEGRA_SW 199 iommus = <&mc TEGRA_SWGROUP_VIC>;
250 power-domains = <&pd_v 200 power-domains = <&pd_vic>;
251 }; 201 };
252 202
253 nvjpg@54380000 { 203 nvjpg@54380000 {
254 compatible = "nvidia,t 204 compatible = "nvidia,tegra210-nvjpg";
255 reg = <0x0 0x54380000 205 reg = <0x0 0x54380000 0x0 0x00040000>;
256 status = "disabled"; 206 status = "disabled";
257 }; 207 };
258 208
259 dsib: dsi@54400000 { !! 209 dsi@54400000 {
260 compatible = "nvidia,t 210 compatible = "nvidia,tegra210-dsi";
261 reg = <0x0 0x54400000 211 reg = <0x0 0x54400000 0x0 0x00040000>;
262 clocks = <&tegra_car T 212 clocks = <&tegra_car TEGRA210_CLK_DSIB>,
263 <&tegra_car T 213 <&tegra_car TEGRA210_CLK_DSIBLP>,
264 <&tegra_car T 214 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>;
265 clock-names = "dsi", " 215 clock-names = "dsi", "lp", "parent";
266 resets = <&tegra_car 8 216 resets = <&tegra_car 82>;
267 reset-names = "dsi"; 217 reset-names = "dsi";
268 power-domains = <&pd_s 218 power-domains = <&pd_sor>;
269 nvidia,mipi-calibrate 219 nvidia,mipi-calibrate = <&mipi 0x300>; /* DSIC & DSID pads */
270 220
271 status = "disabled"; 221 status = "disabled";
272 222
273 #address-cells = <1>; 223 #address-cells = <1>;
274 #size-cells = <0>; 224 #size-cells = <0>;
275 }; 225 };
276 226
277 nvdec@54480000 { 227 nvdec@54480000 {
278 compatible = "nvidia,t 228 compatible = "nvidia,tegra210-nvdec";
279 reg = <0x0 0x54480000 229 reg = <0x0 0x54480000 0x0 0x00040000>;
280 status = "disabled"; 230 status = "disabled";
281 }; 231 };
282 232
283 nvenc@544c0000 { 233 nvenc@544c0000 {
284 compatible = "nvidia,t 234 compatible = "nvidia,tegra210-nvenc";
285 reg = <0x0 0x544c0000 235 reg = <0x0 0x544c0000 0x0 0x00040000>;
286 status = "disabled"; 236 status = "disabled";
287 }; 237 };
288 238
289 tsec@54500000 { 239 tsec@54500000 {
290 compatible = "nvidia,t 240 compatible = "nvidia,tegra210-tsec";
291 reg = <0x0 0x54500000 241 reg = <0x0 0x54500000 0x0 0x00040000>;
292 interrupts = <GIC_SPI <<
293 clocks = <&tegra_car T <<
294 clock-names = "tsec"; <<
295 resets = <&tegra_car 2 <<
296 reset-names = "tsec"; <<
297 status = "disabled"; 242 status = "disabled";
298 }; 243 };
299 244
300 sor0: sor@54540000 { !! 245 sor@54540000 {
301 compatible = "nvidia,t 246 compatible = "nvidia,tegra210-sor";
302 reg = <0x0 0x54540000 247 reg = <0x0 0x54540000 0x0 0x00040000>;
303 interrupts = <GIC_SPI 248 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
304 clocks = <&tegra_car T 249 clocks = <&tegra_car TEGRA210_CLK_SOR0>,
305 <&tegra_car T <<
306 <&tegra_car T 250 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>,
307 <&tegra_car T 251 <&tegra_car TEGRA210_CLK_PLL_DP>,
308 <&tegra_car T 252 <&tegra_car TEGRA210_CLK_SOR_SAFE>;
309 clock-names = "sor", " !! 253 clock-names = "sor", "parent", "dp", "safe";
310 resets = <&tegra_car 1 254 resets = <&tegra_car 182>;
311 reset-names = "sor"; 255 reset-names = "sor";
312 pinctrl-0 = <&state_dp 256 pinctrl-0 = <&state_dpaux_aux>;
313 pinctrl-1 = <&state_dp 257 pinctrl-1 = <&state_dpaux_i2c>;
314 pinctrl-2 = <&state_dp 258 pinctrl-2 = <&state_dpaux_off>;
315 pinctrl-names = "aux", 259 pinctrl-names = "aux", "i2c", "off";
316 power-domains = <&pd_s 260 power-domains = <&pd_sor>;
317 status = "disabled"; 261 status = "disabled";
318 }; 262 };
319 263
320 sor1: sor@54580000 { !! 264 sor@54580000 {
321 compatible = "nvidia,t 265 compatible = "nvidia,tegra210-sor1";
322 reg = <0x0 0x54580000 266 reg = <0x0 0x54580000 0x0 0x00040000>;
323 interrupts = <GIC_SPI 267 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
324 clocks = <&tegra_car T 268 clocks = <&tegra_car TEGRA210_CLK_SOR1>,
325 <&tegra_car T !! 269 <&tegra_car TEGRA210_CLK_SOR1_SRC>,
326 <&tegra_car T 270 <&tegra_car TEGRA210_CLK_PLL_D2_OUT0>,
327 <&tegra_car T 271 <&tegra_car TEGRA210_CLK_PLL_DP>,
328 <&tegra_car T 272 <&tegra_car TEGRA210_CLK_SOR_SAFE>;
329 clock-names = "sor", " !! 273 clock-names = "sor", "source", "parent", "dp", "safe";
330 resets = <&tegra_car 1 274 resets = <&tegra_car 183>;
331 reset-names = "sor"; 275 reset-names = "sor";
332 pinctrl-0 = <&state_dp 276 pinctrl-0 = <&state_dpaux1_aux>;
333 pinctrl-1 = <&state_dp 277 pinctrl-1 = <&state_dpaux1_i2c>;
334 pinctrl-2 = <&state_dp 278 pinctrl-2 = <&state_dpaux1_off>;
335 pinctrl-names = "aux", 279 pinctrl-names = "aux", "i2c", "off";
336 power-domains = <&pd_s 280 power-domains = <&pd_sor>;
337 status = "disabled"; 281 status = "disabled";
338 }; 282 };
339 283
340 dpaux: dpaux@545c0000 { 284 dpaux: dpaux@545c0000 {
341 compatible = "nvidia,t !! 285 compatible = "nvidia,tegra124-dpaux";
342 reg = <0x0 0x545c0000 286 reg = <0x0 0x545c0000 0x0 0x00040000>;
343 interrupts = <GIC_SPI 287 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
344 clocks = <&tegra_car T 288 clocks = <&tegra_car TEGRA210_CLK_DPAUX>,
345 <&tegra_car T 289 <&tegra_car TEGRA210_CLK_PLL_DP>;
346 clock-names = "dpaux", 290 clock-names = "dpaux", "parent";
347 resets = <&tegra_car 1 291 resets = <&tegra_car 181>;
348 reset-names = "dpaux"; 292 reset-names = "dpaux";
349 power-domains = <&pd_s 293 power-domains = <&pd_sor>;
350 status = "disabled"; 294 status = "disabled";
351 295
352 state_dpaux_aux: pinmu 296 state_dpaux_aux: pinmux-aux {
353 groups = "dpau 297 groups = "dpaux-io";
354 function = "au 298 function = "aux";
355 }; 299 };
356 300
357 state_dpaux_i2c: pinmu 301 state_dpaux_i2c: pinmux-i2c {
358 groups = "dpau 302 groups = "dpaux-io";
359 function = "i2 303 function = "i2c";
360 }; 304 };
361 305
362 state_dpaux_off: pinmu 306 state_dpaux_off: pinmux-off {
363 groups = "dpau 307 groups = "dpaux-io";
364 function = "of 308 function = "off";
365 }; 309 };
366 310
367 i2c-bus { 311 i2c-bus {
368 #address-cells 312 #address-cells = <1>;
369 #size-cells = 313 #size-cells = <0>;
370 }; 314 };
371 }; 315 };
372 316
373 isp@54600000 { 317 isp@54600000 {
374 compatible = "nvidia,t 318 compatible = "nvidia,tegra210-isp";
375 reg = <0x0 0x54600000 319 reg = <0x0 0x54600000 0x0 0x00040000>;
376 interrupts = <GIC_SPI 320 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
377 clocks = <&tegra_car T <<
378 resets = <&tegra_car 2 <<
379 reset-names = "isp"; <<
380 status = "disabled"; 321 status = "disabled";
381 }; 322 };
382 323
383 isp@54680000 { 324 isp@54680000 {
384 compatible = "nvidia,t 325 compatible = "nvidia,tegra210-isp";
385 reg = <0x0 0x54680000 326 reg = <0x0 0x54680000 0x0 0x00040000>;
386 interrupts = <GIC_SPI 327 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
387 clocks = <&tegra_car T <<
388 resets = <&tegra_car 3 <<
389 reset-names = "isp"; <<
390 status = "disabled"; 328 status = "disabled";
391 }; 329 };
392 330
393 i2c@546c0000 { 331 i2c@546c0000 {
394 compatible = "nvidia,t 332 compatible = "nvidia,tegra210-i2c-vi";
395 reg = <0x0 0x546c0000 333 reg = <0x0 0x546c0000 0x0 0x00040000>;
396 interrupts = <GIC_SPI 334 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
397 clocks = <&tegra_car T <<
398 <&tegra_car T <<
399 clock-names = "div-clk <<
400 resets = <&tegra_car 2 <<
401 reset-names = "i2c"; <<
402 power-domains = <&pd_v <<
403 status = "disabled"; 335 status = "disabled";
404 <<
405 #address-cells = <1>; <<
406 #size-cells = <0>; <<
407 }; 336 };
408 }; 337 };
409 338
410 gic: interrupt-controller@50041000 { 339 gic: interrupt-controller@50041000 {
411 compatible = "arm,gic-400"; 340 compatible = "arm,gic-400";
412 #interrupt-cells = <3>; 341 #interrupt-cells = <3>;
413 interrupt-controller; 342 interrupt-controller;
414 reg = <0x0 0x50041000 0x0 0x10 343 reg = <0x0 0x50041000 0x0 0x1000>,
415 <0x0 0x50042000 0x0 0x20 344 <0x0 0x50042000 0x0 0x2000>,
416 <0x0 0x50044000 0x0 0x20 345 <0x0 0x50044000 0x0 0x2000>,
417 <0x0 0x50046000 0x0 0x20 346 <0x0 0x50046000 0x0 0x2000>;
418 interrupts = <GIC_PPI 9 347 interrupts = <GIC_PPI 9
419 (GIC_CPU_MASK_SIMPLE(4 348 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
420 interrupt-parent = <&gic>; 349 interrupt-parent = <&gic>;
421 }; 350 };
422 351
423 gpu@57000000 { 352 gpu@57000000 {
424 compatible = "nvidia,gm20b"; 353 compatible = "nvidia,gm20b";
425 reg = <0x0 0x57000000 0x0 0x01 354 reg = <0x0 0x57000000 0x0 0x01000000>,
426 <0x0 0x58000000 0x0 0x01 355 <0x0 0x58000000 0x0 0x01000000>;
427 interrupts = <GIC_SPI 157 IRQ_ 356 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
428 <GIC_SPI 158 IRQ_ 357 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
429 interrupt-names = "stall", "no 358 interrupt-names = "stall", "nonstall";
430 clocks = <&tegra_car TEGRA210_ 359 clocks = <&tegra_car TEGRA210_CLK_GPU>,
431 <&tegra_car TEGRA210_ 360 <&tegra_car TEGRA210_CLK_PLL_P_OUT5>,
432 <&tegra_car TEGRA210_ 361 <&tegra_car TEGRA210_CLK_PLL_G_REF>;
433 clock-names = "gpu", "pwr", "r 362 clock-names = "gpu", "pwr", "ref";
434 resets = <&tegra_car 184>; 363 resets = <&tegra_car 184>;
435 reset-names = "gpu"; 364 reset-names = "gpu";
436 365
437 iommus = <&mc TEGRA_SWGROUP_GP 366 iommus = <&mc TEGRA_SWGROUP_GPU>;
438 367
439 status = "disabled"; 368 status = "disabled";
440 }; 369 };
441 370
442 lic: interrupt-controller@60004000 { 371 lic: interrupt-controller@60004000 {
443 compatible = "nvidia,tegra210- 372 compatible = "nvidia,tegra210-ictlr";
444 reg = <0x0 0x60004000 0x0 0x40 373 reg = <0x0 0x60004000 0x0 0x40>, /* primary controller */
445 <0x0 0x60004100 0x0 0x40 374 <0x0 0x60004100 0x0 0x40>, /* secondary controller */
446 <0x0 0x60004200 0x0 0x40 375 <0x0 0x60004200 0x0 0x40>, /* tertiary controller */
447 <0x0 0x60004300 0x0 0x40 376 <0x0 0x60004300 0x0 0x40>, /* quaternary controller */
448 <0x0 0x60004400 0x0 0x40 377 <0x0 0x60004400 0x0 0x40>, /* quinary controller */
449 <0x0 0x60004500 0x0 0x40 378 <0x0 0x60004500 0x0 0x40>; /* senary controller */
450 interrupt-controller; 379 interrupt-controller;
451 #interrupt-cells = <3>; 380 #interrupt-cells = <3>;
452 interrupt-parent = <&gic>; 381 interrupt-parent = <&gic>;
453 }; 382 };
454 383
455 timer@60005000 { 384 timer@60005000 {
456 compatible = "nvidia,tegra210- !! 385 compatible = "nvidia,tegra210-timer", "nvidia,tegra20-timer";
457 reg = <0x0 0x60005000 0x0 0x40 386 reg = <0x0 0x60005000 0x0 0x400>;
458 interrupts = <GIC_SPI 156 IRQ_ !! 387 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
459 <GIC_SPI 0 IRQ_TY <<
460 <GIC_SPI 1 IRQ_TY 388 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
461 <GIC_SPI 41 IRQ_T 389 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
462 <GIC_SPI 42 IRQ_T 390 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
463 <GIC_SPI 121 IRQ_ 391 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
464 <GIC_SPI 152 IRQ_ !! 392 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
465 <GIC_SPI 153 IRQ_ <<
466 <GIC_SPI 154 IRQ_ <<
467 <GIC_SPI 155 IRQ_ <<
468 <GIC_SPI 176 IRQ_ <<
469 <GIC_SPI 177 IRQ_ <<
470 <GIC_SPI 178 IRQ_ <<
471 <GIC_SPI 179 IRQ_ <<
472 clocks = <&tegra_car TEGRA210_ 393 clocks = <&tegra_car TEGRA210_CLK_TIMER>;
473 clock-names = "timer"; 394 clock-names = "timer";
474 }; 395 };
475 396
476 tegra_car: clock@60006000 { 397 tegra_car: clock@60006000 {
477 compatible = "nvidia,tegra210- 398 compatible = "nvidia,tegra210-car";
478 reg = <0x0 0x60006000 0x0 0x10 399 reg = <0x0 0x60006000 0x0 0x1000>;
479 #clock-cells = <1>; 400 #clock-cells = <1>;
480 #reset-cells = <1>; 401 #reset-cells = <1>;
481 }; 402 };
482 403
483 flow-controller@60007000 { 404 flow-controller@60007000 {
484 compatible = "nvidia,tegra210- 405 compatible = "nvidia,tegra210-flowctrl";
485 reg = <0x0 0x60007000 0x0 0x10 406 reg = <0x0 0x60007000 0x0 0x1000>;
486 }; 407 };
487 408
488 gpio: gpio@6000d000 { 409 gpio: gpio@6000d000 {
489 compatible = "nvidia,tegra210- 410 compatible = "nvidia,tegra210-gpio", "nvidia,tegra30-gpio";
490 reg = <0x0 0x6000d000 0x0 0x10 411 reg = <0x0 0x6000d000 0x0 0x1000>;
491 interrupts = <GIC_SPI 32 IRQ_T 412 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
492 <GIC_SPI 33 IRQ_T 413 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
493 <GIC_SPI 34 IRQ_T 414 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
494 <GIC_SPI 35 IRQ_T 415 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
495 <GIC_SPI 55 IRQ_T 416 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
496 <GIC_SPI 87 IRQ_T 417 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
497 <GIC_SPI 89 IRQ_T 418 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
498 <GIC_SPI 125 IRQ_ 419 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
499 #gpio-cells = <2>; 420 #gpio-cells = <2>;
500 gpio-controller; 421 gpio-controller;
501 #interrupt-cells = <2>; 422 #interrupt-cells = <2>;
502 interrupt-controller; 423 interrupt-controller;
503 }; 424 };
504 425
505 apbdma: dma@60020000 { 426 apbdma: dma@60020000 {
506 compatible = "nvidia,tegra210- 427 compatible = "nvidia,tegra210-apbdma", "nvidia,tegra148-apbdma";
507 reg = <0x0 0x60020000 0x0 0x14 428 reg = <0x0 0x60020000 0x0 0x1400>;
508 interrupts = <GIC_SPI 104 IRQ_ 429 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
509 <GIC_SPI 105 IRQ_ 430 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
510 <GIC_SPI 106 IRQ_ 431 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
511 <GIC_SPI 107 IRQ_ 432 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
512 <GIC_SPI 108 IRQ_ 433 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
513 <GIC_SPI 109 IRQ_ 434 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
514 <GIC_SPI 110 IRQ_ 435 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
515 <GIC_SPI 111 IRQ_ 436 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
516 <GIC_SPI 112 IRQ_ 437 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
517 <GIC_SPI 113 IRQ_ 438 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
518 <GIC_SPI 114 IRQ_ 439 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
519 <GIC_SPI 115 IRQ_ 440 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
520 <GIC_SPI 116 IRQ_ 441 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
521 <GIC_SPI 117 IRQ_ 442 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
522 <GIC_SPI 118 IRQ_ 443 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
523 <GIC_SPI 119 IRQ_ 444 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
524 <GIC_SPI 128 IRQ_ 445 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
525 <GIC_SPI 129 IRQ_ 446 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
526 <GIC_SPI 130 IRQ_ 447 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
527 <GIC_SPI 131 IRQ_ 448 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
528 <GIC_SPI 132 IRQ_ 449 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
529 <GIC_SPI 133 IRQ_ 450 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
530 <GIC_SPI 134 IRQ_ 451 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
531 <GIC_SPI 135 IRQ_ 452 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
532 <GIC_SPI 136 IRQ_ 453 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
533 <GIC_SPI 137 IRQ_ 454 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
534 <GIC_SPI 138 IRQ_ 455 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
535 <GIC_SPI 139 IRQ_ 456 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
536 <GIC_SPI 140 IRQ_ 457 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
537 <GIC_SPI 141 IRQ_ 458 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
538 <GIC_SPI 142 IRQ_ 459 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
539 <GIC_SPI 143 IRQ_ 460 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
540 clocks = <&tegra_car TEGRA210_ 461 clocks = <&tegra_car TEGRA210_CLK_APBDMA>;
541 clock-names = "dma"; 462 clock-names = "dma";
542 resets = <&tegra_car 34>; 463 resets = <&tegra_car 34>;
543 reset-names = "dma"; 464 reset-names = "dma";
544 #dma-cells = <1>; 465 #dma-cells = <1>;
545 }; 466 };
546 467
547 apbmisc@70000800 { 468 apbmisc@70000800 {
548 compatible = "nvidia,tegra210- 469 compatible = "nvidia,tegra210-apbmisc", "nvidia,tegra20-apbmisc";
549 reg = <0x0 0x70000800 0x0 0x64 470 reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */
550 <0x0 0x70000008 0x0 0x04 !! 471 <0x0 0x7000e864 0x0 0x04>; /* Strapping options */
551 }; 472 };
552 473
553 pinmux: pinmux@700008d4 { 474 pinmux: pinmux@700008d4 {
554 compatible = "nvidia,tegra210- 475 compatible = "nvidia,tegra210-pinmux";
555 reg = <0x0 0x700008d4 0x0 0x29 476 reg = <0x0 0x700008d4 0x0 0x29c>, /* Pad control registers */
556 <0x0 0x70003000 0x0 0x29 477 <0x0 0x70003000 0x0 0x294>; /* Mux registers */
557 <<
558 sdmmc1_1v8_drv: pinmux-sdmmc1- <<
559 sdmmc1 { <<
560 nvidia,pins = <<
561 nvidia,pull-do <<
562 nvidia,pull-up <<
563 }; <<
564 }; <<
565 <<
566 sdmmc1_3v3_drv: pinmux-sdmmc1- <<
567 sdmmc1 { <<
568 nvidia,pins = <<
569 nvidia,pull-do <<
570 nvidia,pull-up <<
571 }; <<
572 }; <<
573 <<
574 sdmmc2_1v8_drv: pinmux-sdmmc2- <<
575 sdmmc2 { <<
576 nvidia,pins = <<
577 nvidia,pull-do <<
578 nvidia,pull-up <<
579 }; <<
580 }; <<
581 <<
582 sdmmc3_1v8_drv: pinmux-sdmmc3- <<
583 sdmmc3 { <<
584 nvidia,pins = <<
585 nvidia,pull-do <<
586 nvidia,pull-up <<
587 }; <<
588 }; <<
589 <<
590 sdmmc3_3v3_drv: pinmux-sdmmc3- <<
591 sdmmc3 { <<
592 nvidia,pins = <<
593 nvidia,pull-do <<
594 nvidia,pull-up <<
595 }; <<
596 }; <<
597 <<
598 sdmmc4_1v8_drv: pinmux-sdmmc4- <<
599 sdmmc4 { <<
600 nvidia,pins = <<
601 nvidia,pull-do <<
602 nvidia,pull-up <<
603 }; <<
604 }; <<
605 }; 478 };
606 479
607 /* 480 /*
608 * There are two serial driver i.e. 82 481 * There are two serial driver i.e. 8250 based simple serial
609 * driver and APB DMA based serial dri 482 * driver and APB DMA based serial driver for higher baudrate
610 * and performance. To enable the 8250 483 * and performance. To enable the 8250 based driver, the compatible
611 * is "nvidia,tegra124-uart", "nvidia, 484 * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable
612 * the APB DMA based serial driver, th 485 * the APB DMA based serial driver, the compatible is
613 * "nvidia,tegra124-hsuart", "nvidia,t 486 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart".
614 */ 487 */
615 uarta: serial@70006000 { 488 uarta: serial@70006000 {
616 compatible = "nvidia,tegra210- 489 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
617 reg = <0x0 0x70006000 0x0 0x40 490 reg = <0x0 0x70006000 0x0 0x40>;
618 reg-shift = <2>; 491 reg-shift = <2>;
619 interrupts = <GIC_SPI 36 IRQ_T 492 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
620 clocks = <&tegra_car TEGRA210_ 493 clocks = <&tegra_car TEGRA210_CLK_UARTA>;
>> 494 clock-names = "serial";
621 resets = <&tegra_car 6>; 495 resets = <&tegra_car 6>;
>> 496 reset-names = "serial";
622 dmas = <&apbdma 8>, <&apbdma 8 497 dmas = <&apbdma 8>, <&apbdma 8>;
623 dma-names = "rx", "tx"; 498 dma-names = "rx", "tx";
624 status = "disabled"; 499 status = "disabled";
625 }; 500 };
626 501
627 uartb: serial@70006040 { 502 uartb: serial@70006040 {
628 compatible = "nvidia,tegra210- 503 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
629 reg = <0x0 0x70006040 0x0 0x40 504 reg = <0x0 0x70006040 0x0 0x40>;
630 reg-shift = <2>; 505 reg-shift = <2>;
631 interrupts = <GIC_SPI 37 IRQ_T 506 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
632 clocks = <&tegra_car TEGRA210_ 507 clocks = <&tegra_car TEGRA210_CLK_UARTB>;
>> 508 clock-names = "serial";
633 resets = <&tegra_car 7>; 509 resets = <&tegra_car 7>;
>> 510 reset-names = "serial";
634 dmas = <&apbdma 9>, <&apbdma 9 511 dmas = <&apbdma 9>, <&apbdma 9>;
635 dma-names = "rx", "tx"; 512 dma-names = "rx", "tx";
636 status = "disabled"; 513 status = "disabled";
637 }; 514 };
638 515
639 uartc: serial@70006200 { 516 uartc: serial@70006200 {
640 compatible = "nvidia,tegra210- 517 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
641 reg = <0x0 0x70006200 0x0 0x40 518 reg = <0x0 0x70006200 0x0 0x40>;
642 reg-shift = <2>; 519 reg-shift = <2>;
643 interrupts = <GIC_SPI 46 IRQ_T 520 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
644 clocks = <&tegra_car TEGRA210_ 521 clocks = <&tegra_car TEGRA210_CLK_UARTC>;
>> 522 clock-names = "serial";
645 resets = <&tegra_car 55>; 523 resets = <&tegra_car 55>;
>> 524 reset-names = "serial";
646 dmas = <&apbdma 10>, <&apbdma 525 dmas = <&apbdma 10>, <&apbdma 10>;
647 dma-names = "rx", "tx"; 526 dma-names = "rx", "tx";
648 status = "disabled"; 527 status = "disabled";
649 }; 528 };
650 529
651 uartd: serial@70006300 { 530 uartd: serial@70006300 {
652 compatible = "nvidia,tegra210- 531 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
653 reg = <0x0 0x70006300 0x0 0x40 532 reg = <0x0 0x70006300 0x0 0x40>;
654 reg-shift = <2>; 533 reg-shift = <2>;
655 interrupts = <GIC_SPI 90 IRQ_T 534 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
656 clocks = <&tegra_car TEGRA210_ 535 clocks = <&tegra_car TEGRA210_CLK_UARTD>;
>> 536 clock-names = "serial";
657 resets = <&tegra_car 65>; 537 resets = <&tegra_car 65>;
>> 538 reset-names = "serial";
658 dmas = <&apbdma 19>, <&apbdma 539 dmas = <&apbdma 19>, <&apbdma 19>;
659 dma-names = "rx", "tx"; 540 dma-names = "rx", "tx";
660 status = "disabled"; 541 status = "disabled";
661 }; 542 };
662 543
663 pwm: pwm@7000a000 { 544 pwm: pwm@7000a000 {
664 compatible = "nvidia,tegra210- 545 compatible = "nvidia,tegra210-pwm", "nvidia,tegra20-pwm";
665 reg = <0x0 0x7000a000 0x0 0x10 546 reg = <0x0 0x7000a000 0x0 0x100>;
666 #pwm-cells = <2>; 547 #pwm-cells = <2>;
667 clocks = <&tegra_car TEGRA210_ 548 clocks = <&tegra_car TEGRA210_CLK_PWM>;
>> 549 clock-names = "pwm";
668 resets = <&tegra_car 17>; 550 resets = <&tegra_car 17>;
669 reset-names = "pwm"; 551 reset-names = "pwm";
670 status = "disabled"; 552 status = "disabled";
671 }; 553 };
672 554
673 i2c@7000c000 { 555 i2c@7000c000 {
674 compatible = "nvidia,tegra210- !! 556 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
675 reg = <0x0 0x7000c000 0x0 0x10 557 reg = <0x0 0x7000c000 0x0 0x100>;
676 interrupts = <GIC_SPI 38 IRQ_T 558 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
677 #address-cells = <1>; 559 #address-cells = <1>;
678 #size-cells = <0>; 560 #size-cells = <0>;
679 clocks = <&tegra_car TEGRA210_ 561 clocks = <&tegra_car TEGRA210_CLK_I2C1>;
680 clock-names = "div-clk"; 562 clock-names = "div-clk";
681 resets = <&tegra_car 12>; 563 resets = <&tegra_car 12>;
682 reset-names = "i2c"; 564 reset-names = "i2c";
683 dmas = <&apbdma 21>, <&apbdma 565 dmas = <&apbdma 21>, <&apbdma 21>;
684 dma-names = "rx", "tx"; 566 dma-names = "rx", "tx";
685 status = "disabled"; 567 status = "disabled";
686 }; 568 };
687 569
688 i2c@7000c400 { 570 i2c@7000c400 {
689 compatible = "nvidia,tegra210- !! 571 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
690 reg = <0x0 0x7000c400 0x0 0x10 572 reg = <0x0 0x7000c400 0x0 0x100>;
691 interrupts = <GIC_SPI 84 IRQ_T 573 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
692 #address-cells = <1>; 574 #address-cells = <1>;
693 #size-cells = <0>; 575 #size-cells = <0>;
694 clocks = <&tegra_car TEGRA210_ 576 clocks = <&tegra_car TEGRA210_CLK_I2C2>;
695 clock-names = "div-clk"; 577 clock-names = "div-clk";
696 resets = <&tegra_car 54>; 578 resets = <&tegra_car 54>;
697 reset-names = "i2c"; 579 reset-names = "i2c";
698 dmas = <&apbdma 22>, <&apbdma 580 dmas = <&apbdma 22>, <&apbdma 22>;
699 dma-names = "rx", "tx"; 581 dma-names = "rx", "tx";
700 status = "disabled"; 582 status = "disabled";
701 }; 583 };
702 584
703 i2c@7000c500 { 585 i2c@7000c500 {
704 compatible = "nvidia,tegra210- !! 586 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
705 reg = <0x0 0x7000c500 0x0 0x10 587 reg = <0x0 0x7000c500 0x0 0x100>;
706 interrupts = <GIC_SPI 92 IRQ_T 588 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
707 #address-cells = <1>; 589 #address-cells = <1>;
708 #size-cells = <0>; 590 #size-cells = <0>;
709 clocks = <&tegra_car TEGRA210_ 591 clocks = <&tegra_car TEGRA210_CLK_I2C3>;
710 clock-names = "div-clk"; 592 clock-names = "div-clk";
711 resets = <&tegra_car 67>; 593 resets = <&tegra_car 67>;
712 reset-names = "i2c"; 594 reset-names = "i2c";
713 dmas = <&apbdma 23>, <&apbdma 595 dmas = <&apbdma 23>, <&apbdma 23>;
714 dma-names = "rx", "tx"; 596 dma-names = "rx", "tx";
715 status = "disabled"; 597 status = "disabled";
716 }; 598 };
717 599
718 i2c@7000c700 { 600 i2c@7000c700 {
719 compatible = "nvidia,tegra210- !! 601 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
720 reg = <0x0 0x7000c700 0x0 0x10 602 reg = <0x0 0x7000c700 0x0 0x100>;
721 interrupts = <GIC_SPI 120 IRQ_ 603 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
722 #address-cells = <1>; 604 #address-cells = <1>;
723 #size-cells = <0>; 605 #size-cells = <0>;
724 clocks = <&tegra_car TEGRA210_ 606 clocks = <&tegra_car TEGRA210_CLK_I2C4>;
725 clock-names = "div-clk"; 607 clock-names = "div-clk";
726 resets = <&tegra_car 103>; 608 resets = <&tegra_car 103>;
727 reset-names = "i2c"; 609 reset-names = "i2c";
728 dmas = <&apbdma 26>, <&apbdma 610 dmas = <&apbdma 26>, <&apbdma 26>;
729 dma-names = "rx", "tx"; 611 dma-names = "rx", "tx";
730 pinctrl-0 = <&state_dpaux1_i2c 612 pinctrl-0 = <&state_dpaux1_i2c>;
731 pinctrl-1 = <&state_dpaux1_off 613 pinctrl-1 = <&state_dpaux1_off>;
732 pinctrl-names = "default", "id 614 pinctrl-names = "default", "idle";
733 status = "disabled"; 615 status = "disabled";
734 }; 616 };
735 617
736 i2c@7000d000 { 618 i2c@7000d000 {
737 compatible = "nvidia,tegra210- !! 619 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
738 reg = <0x0 0x7000d000 0x0 0x10 620 reg = <0x0 0x7000d000 0x0 0x100>;
739 interrupts = <GIC_SPI 53 IRQ_T 621 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
740 #address-cells = <1>; 622 #address-cells = <1>;
741 #size-cells = <0>; 623 #size-cells = <0>;
742 clocks = <&tegra_car TEGRA210_ 624 clocks = <&tegra_car TEGRA210_CLK_I2C5>;
743 clock-names = "div-clk"; 625 clock-names = "div-clk";
744 resets = <&tegra_car 47>; 626 resets = <&tegra_car 47>;
745 reset-names = "i2c"; 627 reset-names = "i2c";
746 dmas = <&apbdma 24>, <&apbdma 628 dmas = <&apbdma 24>, <&apbdma 24>;
747 dma-names = "rx", "tx"; 629 dma-names = "rx", "tx";
748 status = "disabled"; 630 status = "disabled";
749 }; 631 };
750 632
751 i2c@7000d100 { 633 i2c@7000d100 {
752 compatible = "nvidia,tegra210- !! 634 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
753 reg = <0x0 0x7000d100 0x0 0x10 635 reg = <0x0 0x7000d100 0x0 0x100>;
754 interrupts = <GIC_SPI 63 IRQ_T 636 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
755 #address-cells = <1>; 637 #address-cells = <1>;
756 #size-cells = <0>; 638 #size-cells = <0>;
757 clocks = <&tegra_car TEGRA210_ 639 clocks = <&tegra_car TEGRA210_CLK_I2C6>;
758 clock-names = "div-clk"; 640 clock-names = "div-clk";
759 resets = <&tegra_car 166>; 641 resets = <&tegra_car 166>;
760 reset-names = "i2c"; 642 reset-names = "i2c";
761 dmas = <&apbdma 30>, <&apbdma 643 dmas = <&apbdma 30>, <&apbdma 30>;
762 dma-names = "rx", "tx"; 644 dma-names = "rx", "tx";
763 pinctrl-0 = <&state_dpaux_i2c> 645 pinctrl-0 = <&state_dpaux_i2c>;
764 pinctrl-1 = <&state_dpaux_off> 646 pinctrl-1 = <&state_dpaux_off>;
765 pinctrl-names = "default", "id 647 pinctrl-names = "default", "idle";
766 status = "disabled"; 648 status = "disabled";
767 }; 649 };
768 650
769 spi@7000d400 { 651 spi@7000d400 {
770 compatible = "nvidia,tegra210- 652 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
771 reg = <0x0 0x7000d400 0x0 0x20 653 reg = <0x0 0x7000d400 0x0 0x200>;
772 interrupts = <GIC_SPI 59 IRQ_T 654 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
773 #address-cells = <1>; 655 #address-cells = <1>;
774 #size-cells = <0>; 656 #size-cells = <0>;
775 clocks = <&tegra_car TEGRA210_ 657 clocks = <&tegra_car TEGRA210_CLK_SBC1>;
776 clock-names = "spi"; 658 clock-names = "spi";
777 resets = <&tegra_car 41>; 659 resets = <&tegra_car 41>;
778 reset-names = "spi"; 660 reset-names = "spi";
779 dmas = <&apbdma 15>, <&apbdma 661 dmas = <&apbdma 15>, <&apbdma 15>;
780 dma-names = "rx", "tx"; 662 dma-names = "rx", "tx";
781 status = "disabled"; 663 status = "disabled";
782 }; 664 };
783 665
784 spi@7000d600 { 666 spi@7000d600 {
785 compatible = "nvidia,tegra210- 667 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
786 reg = <0x0 0x7000d600 0x0 0x20 668 reg = <0x0 0x7000d600 0x0 0x200>;
787 interrupts = <GIC_SPI 82 IRQ_T 669 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
788 #address-cells = <1>; 670 #address-cells = <1>;
789 #size-cells = <0>; 671 #size-cells = <0>;
790 clocks = <&tegra_car TEGRA210_ 672 clocks = <&tegra_car TEGRA210_CLK_SBC2>;
791 clock-names = "spi"; 673 clock-names = "spi";
792 resets = <&tegra_car 44>; 674 resets = <&tegra_car 44>;
793 reset-names = "spi"; 675 reset-names = "spi";
794 dmas = <&apbdma 16>, <&apbdma 676 dmas = <&apbdma 16>, <&apbdma 16>;
795 dma-names = "rx", "tx"; 677 dma-names = "rx", "tx";
796 status = "disabled"; 678 status = "disabled";
797 }; 679 };
798 680
799 spi@7000d800 { 681 spi@7000d800 {
800 compatible = "nvidia,tegra210- 682 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
801 reg = <0x0 0x7000d800 0x0 0x20 683 reg = <0x0 0x7000d800 0x0 0x200>;
802 interrupts = <GIC_SPI 83 IRQ_T 684 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
803 #address-cells = <1>; 685 #address-cells = <1>;
804 #size-cells = <0>; 686 #size-cells = <0>;
805 clocks = <&tegra_car TEGRA210_ 687 clocks = <&tegra_car TEGRA210_CLK_SBC3>;
806 clock-names = "spi"; 688 clock-names = "spi";
807 resets = <&tegra_car 46>; 689 resets = <&tegra_car 46>;
808 reset-names = "spi"; 690 reset-names = "spi";
809 dmas = <&apbdma 17>, <&apbdma 691 dmas = <&apbdma 17>, <&apbdma 17>;
810 dma-names = "rx", "tx"; 692 dma-names = "rx", "tx";
811 status = "disabled"; 693 status = "disabled";
812 }; 694 };
813 695
814 spi@7000da00 { 696 spi@7000da00 {
815 compatible = "nvidia,tegra210- 697 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
816 reg = <0x0 0x7000da00 0x0 0x20 698 reg = <0x0 0x7000da00 0x0 0x200>;
817 interrupts = <GIC_SPI 93 IRQ_T 699 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
818 #address-cells = <1>; 700 #address-cells = <1>;
819 #size-cells = <0>; 701 #size-cells = <0>;
820 clocks = <&tegra_car TEGRA210_ 702 clocks = <&tegra_car TEGRA210_CLK_SBC4>;
821 clock-names = "spi"; 703 clock-names = "spi";
822 resets = <&tegra_car 68>; 704 resets = <&tegra_car 68>;
823 reset-names = "spi"; 705 reset-names = "spi";
824 dmas = <&apbdma 18>, <&apbdma 706 dmas = <&apbdma 18>, <&apbdma 18>;
825 dma-names = "rx", "tx"; 707 dma-names = "rx", "tx";
826 status = "disabled"; 708 status = "disabled";
827 }; 709 };
828 710
829 rtc@7000e000 { 711 rtc@7000e000 {
830 compatible = "nvidia,tegra210- 712 compatible = "nvidia,tegra210-rtc", "nvidia,tegra20-rtc";
831 reg = <0x0 0x7000e000 0x0 0x10 713 reg = <0x0 0x7000e000 0x0 0x100>;
832 interrupts = <16 IRQ_TYPE_LEVE !! 714 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
833 interrupt-parent = <&tegra_pmc <<
834 clocks = <&tegra_car TEGRA210_ 715 clocks = <&tegra_car TEGRA210_CLK_RTC>;
835 clock-names = "rtc"; 716 clock-names = "rtc";
836 }; 717 };
837 718
838 tegra_pmc: pmc@7000e400 { !! 719 pmc: pmc@7000e400 {
839 compatible = "nvidia,tegra210- 720 compatible = "nvidia,tegra210-pmc";
840 reg = <0x0 0x7000e400 0x0 0x40 721 reg = <0x0 0x7000e400 0x0 0x400>;
841 clocks = <&tegra_car TEGRA210_ 722 clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>;
842 clock-names = "pclk", "clk32k_ 723 clock-names = "pclk", "clk32k_in";
843 #clock-cells = <1>; <<
844 #interrupt-cells = <2>; <<
845 interrupt-controller; <<
846 <<
847 pinmux { <<
848 pex_dpd_disable: pex-d <<
849 pins = "pex-bi <<
850 low-power-disa <<
851 }; <<
852 <<
853 pex_dpd_enable: pex-dp <<
854 pins = "pex-bi <<
855 low-power-enab <<
856 }; <<
857 <<
858 sdmmc1_1v8: sdmmc1-1v8 <<
859 pins = "sdmmc1 <<
860 power-source = <<
861 }; <<
862 <<
863 sdmmc1_3v3: sdmmc1-3v3 <<
864 pins = "sdmmc1 <<
865 power-source = <<
866 }; <<
867 <<
868 sdmmc3_1v8: sdmmc3-1v8 <<
869 pins = "sdmmc3 <<
870 power-source = <<
871 }; <<
872 <<
873 sdmmc3_3v3: sdmmc3-3v3 <<
874 pins = "sdmmc3 <<
875 power-source = <<
876 }; <<
877 }; <<
878 724
879 powergates { 725 powergates {
880 pd_audio: aud { 726 pd_audio: aud {
881 clocks = <&teg 727 clocks = <&tegra_car TEGRA210_CLK_APE>,
882 <&teg 728 <&tegra_car TEGRA210_CLK_APB2APE>;
883 resets = <&teg 729 resets = <&tegra_car 198>;
884 #power-domain- 730 #power-domain-cells = <0>;
885 }; 731 };
886 732
887 pd_sor: sor { 733 pd_sor: sor {
888 clocks = <&teg 734 clocks = <&tegra_car TEGRA210_CLK_SOR0>,
889 <&teg 735 <&tegra_car TEGRA210_CLK_SOR1>,
890 <&teg !! 736 <&tegra_car TEGRA210_CLK_CSI>,
891 <&teg <<
892 <&teg <<
893 <&teg 737 <&tegra_car TEGRA210_CLK_DSIA>,
894 <&teg 738 <&tegra_car TEGRA210_CLK_DSIB>,
895 <&teg 739 <&tegra_car TEGRA210_CLK_DPAUX>,
896 <&teg 740 <&tegra_car TEGRA210_CLK_DPAUX1>,
897 <&teg 741 <&tegra_car TEGRA210_CLK_MIPI_CAL>;
898 resets = <&teg 742 resets = <&tegra_car TEGRA210_CLK_SOR0>,
899 <&teg 743 <&tegra_car TEGRA210_CLK_SOR1>,
>> 744 <&tegra_car TEGRA210_CLK_CSI>,
900 <&teg 745 <&tegra_car TEGRA210_CLK_DSIA>,
901 <&teg 746 <&tegra_car TEGRA210_CLK_DSIB>,
902 <&teg 747 <&tegra_car TEGRA210_CLK_DPAUX>,
903 <&teg 748 <&tegra_car TEGRA210_CLK_DPAUX1>,
904 <&teg 749 <&tegra_car TEGRA210_CLK_MIPI_CAL>;
905 #power-domain- 750 #power-domain-cells = <0>;
906 }; 751 };
907 752
908 pd_venc: venc { <<
909 clocks = <&teg <<
910 <&teg <<
911 resets = <&mc <<
912 <&teg <<
913 <&teg <<
914 #power-domain- <<
915 }; <<
916 <<
917 pd_vic: vic { <<
918 clocks = <&teg <<
919 resets = <&teg <<
920 #power-domain- <<
921 }; <<
922 <<
923 pd_xusbss: xusba { 753 pd_xusbss: xusba {
924 clocks = <&teg 754 clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>;
925 resets = <&teg 755 resets = <&tegra_car TEGRA210_CLK_XUSB_SS>;
926 #power-domain- 756 #power-domain-cells = <0>;
927 }; 757 };
928 758
929 pd_xusbdev: xusbb { 759 pd_xusbdev: xusbb {
930 clocks = <&teg 760 clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>;
931 resets = <&teg 761 resets = <&tegra_car 95>;
932 #power-domain- 762 #power-domain-cells = <0>;
933 }; 763 };
934 764
935 pd_xusbhost: xusbc { 765 pd_xusbhost: xusbc {
936 clocks = <&teg 766 clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>;
937 resets = <&teg 767 resets = <&tegra_car TEGRA210_CLK_XUSB_HOST>;
938 #power-domain- 768 #power-domain-cells = <0>;
939 }; 769 };
>> 770
>> 771 pd_vic: vic {
>> 772 clocks = <&tegra_car TEGRA210_CLK_VIC03>;
>> 773 clock-names = "vic";
>> 774 resets = <&tegra_car 178>;
>> 775 reset-names = "vic";
>> 776 #power-domain-cells = <0>;
>> 777 };
940 }; 778 };
941 }; 779 };
942 780
943 fuse@7000f800 { 781 fuse@7000f800 {
944 compatible = "nvidia,tegra210- 782 compatible = "nvidia,tegra210-efuse";
945 reg = <0x0 0x7000f800 0x0 0x40 783 reg = <0x0 0x7000f800 0x0 0x400>;
946 clocks = <&tegra_car TEGRA210_ 784 clocks = <&tegra_car TEGRA210_CLK_FUSE>;
947 clock-names = "fuse"; 785 clock-names = "fuse";
948 resets = <&tegra_car 39>; 786 resets = <&tegra_car 39>;
949 reset-names = "fuse"; 787 reset-names = "fuse";
950 }; 788 };
951 789
952 mc: memory-controller@70019000 { 790 mc: memory-controller@70019000 {
953 compatible = "nvidia,tegra210- 791 compatible = "nvidia,tegra210-mc";
954 reg = <0x0 0x70019000 0x0 0x10 792 reg = <0x0 0x70019000 0x0 0x1000>;
955 clocks = <&tegra_car TEGRA210_ 793 clocks = <&tegra_car TEGRA210_CLK_MC>;
956 clock-names = "mc"; 794 clock-names = "mc";
957 795
958 interrupts = <GIC_SPI 77 IRQ_T 796 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
959 797
960 #iommu-cells = <1>; 798 #iommu-cells = <1>;
961 #reset-cells = <1>; <<
962 }; <<
963 <<
964 emc: external-memory-controller@7001b0 <<
965 compatible = "nvidia,tegra210- <<
966 reg = <0x0 0x7001b000 0x0 0x10 <<
967 <0x0 0x7001e000 0x0 0x10 <<
968 <0x0 0x7001f000 0x0 0x10 <<
969 clocks = <&tegra_car TEGRA210_ <<
970 clock-names = "emc"; <<
971 interrupts = <GIC_SPI 78 IRQ_T <<
972 nvidia,memory-controller = <&m <<
973 #cooling-cells = <2>; <<
974 }; <<
975 <<
976 sata@70020000 { <<
977 compatible = "nvidia,tegra210- <<
978 reg = <0x0 0x70027000 0x0 0x20 <<
979 <0x0 0x70020000 0x0 0x70 <<
980 <0x0 0x70001100 0x0 0x10 <<
981 interrupts = <GIC_SPI 23 IRQ_T <<
982 clocks = <&tegra_car TEGRA210_ <<
983 <&tegra_car TEGRA210_ <<
984 clock-names = "sata", "sata-oo <<
985 resets = <&tegra_car 124>, <<
986 <&tegra_car 129>, <<
987 <&tegra_car 123>; <<
988 reset-names = "sata", "sata-co <<
989 status = "disabled"; <<
990 }; 799 };
991 800
992 hda@70030000 { 801 hda@70030000 {
993 compatible = "nvidia,tegra210- 802 compatible = "nvidia,tegra210-hda", "nvidia,tegra30-hda";
994 reg = <0x0 0x70030000 0x0 0x10 803 reg = <0x0 0x70030000 0x0 0x10000>;
995 interrupts = <GIC_SPI 81 IRQ_T 804 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
996 clocks = <&tegra_car TEGRA210_ 805 clocks = <&tegra_car TEGRA210_CLK_HDA>,
997 <&tegra_car TEGRA210_ 806 <&tegra_car TEGRA210_CLK_HDA2HDMI>,
998 <&tegra_car TEGRA210_ 807 <&tegra_car TEGRA210_CLK_HDA2CODEC_2X>;
999 clock-names = "hda", "hda2hdmi 808 clock-names = "hda", "hda2hdmi", "hda2codec_2x";
1000 resets = <&tegra_car 125>, /* 809 resets = <&tegra_car 125>, /* hda */
1001 <&tegra_car 128>, /* 810 <&tegra_car 128>, /* hda2hdmi */
1002 <&tegra_car 111>; /* 811 <&tegra_car 111>; /* hda2codec_2x */
1003 reset-names = "hda", "hda2hdm 812 reset-names = "hda", "hda2hdmi", "hda2codec_2x";
1004 power-domains = <&pd_sor>; <<
1005 status = "disabled"; 813 status = "disabled";
1006 }; 814 };
1007 815
1008 usb@70090000 { 816 usb@70090000 {
1009 compatible = "nvidia,tegra210 817 compatible = "nvidia,tegra210-xusb";
1010 reg = <0x0 0x70090000 0x0 0x8 818 reg = <0x0 0x70090000 0x0 0x8000>,
1011 <0x0 0x70098000 0x0 0x1 819 <0x0 0x70098000 0x0 0x1000>,
1012 <0x0 0x70099000 0x0 0x1 820 <0x0 0x70099000 0x0 0x1000>;
1013 reg-names = "hcd", "fpci", "i 821 reg-names = "hcd", "fpci", "ipfs";
1014 822
1015 interrupts = <GIC_SPI 39 IRQ_ 823 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
1016 <GIC_SPI 40 IRQ_ 824 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1017 825
1018 clocks = <&tegra_car TEGRA210 826 clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>,
1019 <&tegra_car TEGRA210 827 <&tegra_car TEGRA210_CLK_XUSB_HOST_SRC>,
1020 <&tegra_car TEGRA210 828 <&tegra_car TEGRA210_CLK_XUSB_FALCON_SRC>,
1021 <&tegra_car TEGRA210 829 <&tegra_car TEGRA210_CLK_XUSB_SS>,
1022 <&tegra_car TEGRA210 830 <&tegra_car TEGRA210_CLK_XUSB_SS_DIV2>,
1023 <&tegra_car TEGRA210 831 <&tegra_car TEGRA210_CLK_XUSB_SS_SRC>,
1024 <&tegra_car TEGRA210 832 <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>,
1025 <&tegra_car TEGRA210 833 <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>,
1026 <&tegra_car TEGRA210 834 <&tegra_car TEGRA210_CLK_PLL_U_480M>,
1027 <&tegra_car TEGRA210 835 <&tegra_car TEGRA210_CLK_CLK_M>,
1028 <&tegra_car TEGRA210 836 <&tegra_car TEGRA210_CLK_PLL_E>;
1029 clock-names = "xusb_host", "x 837 clock-names = "xusb_host", "xusb_host_src",
1030 "xusb_falcon_sr 838 "xusb_falcon_src", "xusb_ss",
1031 "xusb_ss_div2", 839 "xusb_ss_div2", "xusb_ss_src",
1032 "xusb_hs_src", 840 "xusb_hs_src", "xusb_fs_src",
1033 "pll_u_480m", " 841 "pll_u_480m", "clk_m", "pll_e";
1034 resets = <&tegra_car 89>, <&t 842 resets = <&tegra_car 89>, <&tegra_car 156>,
1035 <&tegra_car 143>; 843 <&tegra_car 143>;
1036 reset-names = "xusb_host", "x 844 reset-names = "xusb_host", "xusb_ss", "xusb_src";
1037 power-domains = <&pd_xusbhost <<
1038 power-domain-names = "xusb_ho <<
1039 845
1040 nvidia,xusb-padctl = <&padctl 846 nvidia,xusb-padctl = <&padctl>;
1041 847
1042 status = "disabled"; 848 status = "disabled";
1043 }; 849 };
1044 850
1045 padctl: padctl@7009f000 { 851 padctl: padctl@7009f000 {
1046 compatible = "nvidia,tegra210 852 compatible = "nvidia,tegra210-xusb-padctl";
1047 reg = <0x0 0x7009f000 0x0 0x1 853 reg = <0x0 0x7009f000 0x0 0x1000>;
1048 interrupts = <GIC_SPI 49 IRQ_ <<
1049 resets = <&tegra_car 142>; 854 resets = <&tegra_car 142>;
1050 reset-names = "padctl"; 855 reset-names = "padctl";
1051 nvidia,pmc = <&tegra_pmc>; <<
1052 856
1053 status = "disabled"; 857 status = "disabled";
1054 858
1055 pads { 859 pads {
1056 usb2 { 860 usb2 {
1057 clocks = <&te 861 clocks = <&tegra_car TEGRA210_CLK_USB2_TRK>;
1058 clock-names = 862 clock-names = "trk";
1059 status = "dis 863 status = "disabled";
1060 864
1061 lanes { 865 lanes {
1062 usb2- 866 usb2-0 {
1063 867 status = "disabled";
1064 868 #phy-cells = <0>;
1065 }; 869 };
1066 870
1067 usb2- 871 usb2-1 {
1068 872 status = "disabled";
1069 873 #phy-cells = <0>;
1070 }; 874 };
1071 875
1072 usb2- 876 usb2-2 {
1073 877 status = "disabled";
1074 878 #phy-cells = <0>;
1075 }; 879 };
1076 880
1077 usb2- 881 usb2-3 {
1078 882 status = "disabled";
1079 883 #phy-cells = <0>;
1080 }; 884 };
1081 }; 885 };
1082 }; 886 };
1083 887
1084 hsic { 888 hsic {
1085 clocks = <&te 889 clocks = <&tegra_car TEGRA210_CLK_HSIC_TRK>;
1086 clock-names = 890 clock-names = "trk";
1087 status = "dis 891 status = "disabled";
1088 892
1089 lanes { 893 lanes {
1090 hsic- 894 hsic-0 {
1091 895 status = "disabled";
1092 896 #phy-cells = <0>;
1093 }; 897 };
1094 898
1095 hsic- 899 hsic-1 {
1096 900 status = "disabled";
1097 901 #phy-cells = <0>;
1098 }; 902 };
1099 }; 903 };
1100 }; 904 };
1101 905
1102 pcie { 906 pcie {
1103 clocks = <&te 907 clocks = <&tegra_car TEGRA210_CLK_PLL_E>;
1104 clock-names = 908 clock-names = "pll";
1105 resets = <&te 909 resets = <&tegra_car 205>;
1106 reset-names = 910 reset-names = "phy";
1107 status = "dis 911 status = "disabled";
1108 912
1109 lanes { 913 lanes {
1110 pcie- 914 pcie-0 {
1111 915 status = "disabled";
1112 916 #phy-cells = <0>;
1113 }; 917 };
1114 918
1115 pcie- 919 pcie-1 {
1116 920 status = "disabled";
1117 921 #phy-cells = <0>;
1118 }; 922 };
1119 923
1120 pcie- 924 pcie-2 {
1121 925 status = "disabled";
1122 926 #phy-cells = <0>;
1123 }; 927 };
1124 928
1125 pcie- 929 pcie-3 {
1126 930 status = "disabled";
1127 931 #phy-cells = <0>;
1128 }; 932 };
1129 933
1130 pcie- 934 pcie-4 {
1131 935 status = "disabled";
1132 936 #phy-cells = <0>;
1133 }; 937 };
1134 938
1135 pcie- 939 pcie-5 {
1136 940 status = "disabled";
1137 941 #phy-cells = <0>;
1138 }; 942 };
1139 943
1140 pcie- 944 pcie-6 {
1141 945 status = "disabled";
1142 946 #phy-cells = <0>;
1143 }; 947 };
1144 }; 948 };
1145 }; 949 };
1146 950
1147 sata { 951 sata {
1148 clocks = <&te 952 clocks = <&tegra_car TEGRA210_CLK_PLL_E>;
1149 clock-names = 953 clock-names = "pll";
1150 resets = <&te 954 resets = <&tegra_car 204>;
1151 reset-names = 955 reset-names = "phy";
1152 status = "dis 956 status = "disabled";
1153 957
1154 lanes { 958 lanes {
1155 sata- 959 sata-0 {
1156 960 status = "disabled";
1157 961 #phy-cells = <0>;
1158 }; 962 };
1159 }; 963 };
1160 }; 964 };
1161 }; 965 };
1162 966
1163 ports { 967 ports {
1164 usb2-0 { 968 usb2-0 {
1165 status = "dis 969 status = "disabled";
1166 }; 970 };
1167 971
1168 usb2-1 { 972 usb2-1 {
1169 status = "dis 973 status = "disabled";
1170 }; 974 };
1171 975
1172 usb2-2 { 976 usb2-2 {
1173 status = "dis 977 status = "disabled";
1174 }; 978 };
1175 979
1176 usb2-3 { 980 usb2-3 {
1177 status = "dis 981 status = "disabled";
1178 }; 982 };
1179 983
1180 hsic-0 { 984 hsic-0 {
1181 status = "dis 985 status = "disabled";
1182 }; 986 };
1183 987
1184 usb3-0 { 988 usb3-0 {
1185 status = "dis 989 status = "disabled";
1186 }; 990 };
1187 991
1188 usb3-1 { 992 usb3-1 {
1189 status = "dis 993 status = "disabled";
1190 }; 994 };
1191 995
1192 usb3-2 { 996 usb3-2 {
1193 status = "dis 997 status = "disabled";
1194 }; 998 };
1195 999
1196 usb3-3 { 1000 usb3-3 {
1197 status = "dis 1001 status = "disabled";
1198 }; 1002 };
1199 }; 1003 };
1200 }; 1004 };
1201 1005
1202 mmc@700b0000 { !! 1006 sdhci@700b0000 {
1203 compatible = "nvidia,tegra210 !! 1007 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";
1204 reg = <0x0 0x700b0000 0x0 0x2 1008 reg = <0x0 0x700b0000 0x0 0x200>;
1205 interrupts = <GIC_SPI 14 IRQ_ 1009 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1206 clocks = <&tegra_car TEGRA210 !! 1010 clocks = <&tegra_car TEGRA210_CLK_SDMMC1>;
1207 <&tegra_car TEGRA210 !! 1011 clock-names = "sdhci";
1208 clock-names = "sdhci", "tmclk <<
1209 resets = <&tegra_car 14>; 1012 resets = <&tegra_car 14>;
1210 reset-names = "sdhci"; 1013 reset-names = "sdhci";
1211 pinctrl-names = "sdmmc-3v3", <<
1212 "sdmmc-3v3-dr <<
1213 pinctrl-0 = <&sdmmc1_3v3>; <<
1214 pinctrl-1 = <&sdmmc1_1v8>; <<
1215 pinctrl-2 = <&sdmmc1_3v3_drv> <<
1216 pinctrl-3 = <&sdmmc1_1v8_drv> <<
1217 nvidia,pad-autocal-pull-up-of <<
1218 nvidia,pad-autocal-pull-down- <<
1219 nvidia,pad-autocal-pull-up-of <<
1220 nvidia,pad-autocal-pull-down- <<
1221 nvidia,default-tap = <0x2>; <<
1222 nvidia,default-trim = <0x4>; <<
1223 assigned-clocks = <&tegra_car <<
1224 <&tegra_car <<
1225 <&tegra_car <<
1226 assigned-clock-parents = <&te <<
1227 assigned-clock-rates = <20000 <<
1228 status = "disabled"; 1014 status = "disabled";
1229 }; 1015 };
1230 1016
1231 mmc@700b0200 { !! 1017 sdhci@700b0200 {
1232 compatible = "nvidia,tegra210 !! 1018 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";
1233 reg = <0x0 0x700b0200 0x0 0x2 1019 reg = <0x0 0x700b0200 0x0 0x200>;
1234 interrupts = <GIC_SPI 15 IRQ_ 1020 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1235 clocks = <&tegra_car TEGRA210 !! 1021 clocks = <&tegra_car TEGRA210_CLK_SDMMC2>;
1236 <&tegra_car TEGRA210 !! 1022 clock-names = "sdhci";
1237 clock-names = "sdhci", "tmclk <<
1238 resets = <&tegra_car 9>; 1023 resets = <&tegra_car 9>;
1239 reset-names = "sdhci"; 1024 reset-names = "sdhci";
1240 pinctrl-names = "sdmmc-1v8-dr <<
1241 pinctrl-0 = <&sdmmc2_1v8_drv> <<
1242 nvidia,pad-autocal-pull-up-of <<
1243 nvidia,pad-autocal-pull-down- <<
1244 nvidia,default-tap = <0x8>; <<
1245 nvidia,default-trim = <0x0>; <<
1246 status = "disabled"; 1025 status = "disabled";
1247 }; 1026 };
1248 1027
1249 mmc@700b0400 { !! 1028 sdhci@700b0400 {
1250 compatible = "nvidia,tegra210 !! 1029 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";
1251 reg = <0x0 0x700b0400 0x0 0x2 1030 reg = <0x0 0x700b0400 0x0 0x200>;
1252 interrupts = <GIC_SPI 19 IRQ_ 1031 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1253 clocks = <&tegra_car TEGRA210 !! 1032 clocks = <&tegra_car TEGRA210_CLK_SDMMC3>;
1254 <&tegra_car TEGRA210 !! 1033 clock-names = "sdhci";
1255 clock-names = "sdhci", "tmclk <<
1256 resets = <&tegra_car 69>; 1034 resets = <&tegra_car 69>;
1257 reset-names = "sdhci"; 1035 reset-names = "sdhci";
1258 pinctrl-names = "sdmmc-3v3", <<
1259 "sdmmc-3v3-dr <<
1260 pinctrl-0 = <&sdmmc3_3v3>; <<
1261 pinctrl-1 = <&sdmmc3_1v8>; <<
1262 pinctrl-2 = <&sdmmc3_3v3_drv> <<
1263 pinctrl-3 = <&sdmmc3_1v8_drv> <<
1264 nvidia,pad-autocal-pull-up-of <<
1265 nvidia,pad-autocal-pull-down- <<
1266 nvidia,pad-autocal-pull-up-of <<
1267 nvidia,pad-autocal-pull-down- <<
1268 nvidia,default-tap = <0x3>; <<
1269 nvidia,default-trim = <0x3>; <<
1270 status = "disabled"; 1036 status = "disabled";
1271 }; 1037 };
1272 1038
1273 mmc@700b0600 { !! 1039 sdhci@700b0600 {
1274 compatible = "nvidia,tegra210 !! 1040 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";
1275 reg = <0x0 0x700b0600 0x0 0x2 1041 reg = <0x0 0x700b0600 0x0 0x200>;
1276 interrupts = <GIC_SPI 31 IRQ_ 1042 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
1277 clocks = <&tegra_car TEGRA210 !! 1043 clocks = <&tegra_car TEGRA210_CLK_SDMMC4>;
1278 <&tegra_car TEGRA210 !! 1044 clock-names = "sdhci";
1279 clock-names = "sdhci", "tmclk <<
1280 resets = <&tegra_car 15>; 1045 resets = <&tegra_car 15>;
1281 reset-names = "sdhci"; 1046 reset-names = "sdhci";
1282 pinctrl-names = "sdmmc-3v3-dr <<
1283 pinctrl-0 = <&sdmmc4_1v8_drv> <<
1284 pinctrl-1 = <&sdmmc4_1v8_drv> <<
1285 nvidia,pad-autocal-pull-up-of <<
1286 nvidia,pad-autocal-pull-down- <<
1287 nvidia,default-tap = <0x8>; <<
1288 nvidia,default-trim = <0x0>; <<
1289 assigned-clocks = <&tegra_car <<
1290 <&tegra_car <<
1291 assigned-clock-parents = <&te <<
1292 nvidia,dqs-trim = <40>; <<
1293 mmc-hs400-1_8v; <<
1294 status = "disabled"; <<
1295 }; <<
1296 <<
1297 usb@700d0000 { <<
1298 compatible = "nvidia,tegra210 <<
1299 reg = <0x0 0x700d0000 0x0 0x8 <<
1300 <0x0 0x700d8000 0x0 0x1 <<
1301 <0x0 0x700d9000 0x0 0x1 <<
1302 reg-names = "base", "fpci", " <<
1303 interrupts = <GIC_SPI 44 IRQ_ <<
1304 clocks = <&tegra_car TEGRA210 <<
1305 <&tegra_car TEGRA210 <<
1306 <&tegra_car TEGRA210 <<
1307 <&tegra_car TEGRA210 <<
1308 <&tegra_car TEGRA210 <<
1309 clock-names = "dev", "ss", "s <<
1310 power-domains = <&pd_xusbdev> <<
1311 power-domain-names = "dev", " <<
1312 nvidia,xusb-padctl = <&padctl <<
1313 status = "disabled"; 1047 status = "disabled";
1314 }; 1048 };
1315 1049
1316 soctherm: thermal-sensor@700e2000 { <<
1317 compatible = "nvidia,tegra210 <<
1318 reg = <0x0 0x700e2000 0x0 0x6 <<
1319 <0x0 0x60006000 0x0 0x4 <<
1320 reg-names = "soctherm-reg", " <<
1321 interrupts = <GIC_SPI 48 IRQ_ <<
1322 <GIC_SPI 51 IRQ_ <<
1323 interrupt-names = "thermal", <<
1324 clocks = <&tegra_car TEGRA210 <<
1325 <&tegra_car TEGRA210_ <<
1326 clock-names = "tsensor", "soc <<
1327 resets = <&tegra_car 78>; <<
1328 reset-names = "soctherm"; <<
1329 #thermal-sensor-cells = <1>; <<
1330 <<
1331 throttle-cfgs { <<
1332 throttle_heavy: heavy <<
1333 nvidia,priori <<
1334 nvidia,cpu-th <<
1335 nvidia,gpu-th <<
1336 <<
1337 #cooling-cell <<
1338 }; <<
1339 }; <<
1340 }; <<
1341 <<
1342 mipi: mipi@700e3000 { 1050 mipi: mipi@700e3000 {
1343 compatible = "nvidia,tegra210 1051 compatible = "nvidia,tegra210-mipi";
1344 reg = <0x0 0x700e3000 0x0 0x1 1052 reg = <0x0 0x700e3000 0x0 0x100>;
1345 clocks = <&tegra_car TEGRA210 1053 clocks = <&tegra_car TEGRA210_CLK_MIPI_CAL>;
1346 clock-names = "mipi-cal"; 1054 clock-names = "mipi-cal";
1347 power-domains = <&pd_sor>; 1055 power-domains = <&pd_sor>;
1348 #nvidia,mipi-calibrate-cells 1056 #nvidia,mipi-calibrate-cells = <1>;
1349 }; 1057 };
1350 1058
1351 dfll: clock@70110000 { <<
1352 compatible = "nvidia,tegra210 <<
1353 reg = <0 0x70110000 0 0x100>, <<
1354 <0 0x70110000 0 0x100>, <<
1355 <0 0x70110100 0 0x100>, <<
1356 <0 0x70110200 0 0x100>; <<
1357 interrupts = <GIC_SPI 62 IRQ_ <<
1358 clocks = <&tegra_car TEGRA210 <<
1359 <&tegra_car TEGRA210 <<
1360 <&tegra_car TEGRA210 <<
1361 clock-names = "soc", "ref", " <<
1362 resets = <&tegra_car TEGRA210 <<
1363 <&tegra_car 155>; <<
1364 reset-names = "dvco", "dfll"; <<
1365 #clock-cells = <0>; <<
1366 clock-output-names = "dfllCPU <<
1367 status = "disabled"; <<
1368 }; <<
1369 <<
1370 aconnect@702c0000 { 1059 aconnect@702c0000 {
1371 compatible = "nvidia,tegra210 1060 compatible = "nvidia,tegra210-aconnect";
1372 clocks = <&tegra_car TEGRA210 1061 clocks = <&tegra_car TEGRA210_CLK_APE>,
1373 <&tegra_car TEGRA210 1062 <&tegra_car TEGRA210_CLK_APB2APE>;
1374 clock-names = "ape", "apb2ape 1063 clock-names = "ape", "apb2ape";
1375 power-domains = <&pd_audio>; 1064 power-domains = <&pd_audio>;
1376 #address-cells = <1>; 1065 #address-cells = <1>;
1377 #size-cells = <1>; 1066 #size-cells = <1>;
1378 ranges = <0x702c0000 0x0 0x70 1067 ranges = <0x702c0000 0x0 0x702c0000 0x00040000>;
1379 status = "disabled"; 1068 status = "disabled";
1380 1069
1381 tegra_ahub: ahub@702d0800 { !! 1070 adma: dma@702e2000 {
1382 compatible = "nvidia, <<
1383 reg = <0x702d0800 0x8 <<
1384 clocks = <&tegra_car <<
1385 clock-names = "ahub"; <<
1386 assigned-clocks = <&t <<
1387 assigned-clock-parent <<
1388 assigned-clock-rates <<
1389 #address-cells = <1>; <<
1390 #size-cells = <1>; <<
1391 ranges = <0x702d0000 <<
1392 status = "disabled"; <<
1393 <<
1394 tegra_admaif: admaif@ <<
1395 compatible = <<
1396 reg = <0x702d <<
1397 dmas = <&adma <<
1398 <&adma <<
1399 <&adma <<
1400 <&adma <<
1401 <&adma <<
1402 <&adma <<
1403 <&adma <<
1404 <&adma <<
1405 <&adma <<
1406 <&adma <<
1407 dma-names = " <<
1408 " <<
1409 " <<
1410 " <<
1411 " <<
1412 " <<
1413 " <<
1414 " <<
1415 " <<
1416 " <<
1417 status = "dis <<
1418 <<
1419 ports { <<
1420 #addr <<
1421 #size <<
1422 <<
1423 admai <<
1424 <<
1425 <<
1426 <<
1427 <<
1428 <<
1429 }; <<
1430 <<
1431 admai <<
1432 <<
1433 <<
1434 <<
1435 <<
1436 <<
1437 }; <<
1438 <<
1439 admai <<
1440 <<
1441 <<
1442 <<
1443 <<
1444 <<
1445 }; <<
1446 <<
1447 admai <<
1448 <<
1449 <<
1450 <<
1451 <<
1452 <<
1453 }; <<
1454 <<
1455 admai <<
1456 <<
1457 <<
1458 <<
1459 <<
1460 <<
1461 }; <<
1462 <<
1463 admai <<
1464 <<
1465 <<
1466 <<
1467 <<
1468 <<
1469 }; <<
1470 <<
1471 admai <<
1472 <<
1473 <<
1474 <<
1475 <<
1476 <<
1477 }; <<
1478 <<
1479 admai <<
1480 <<
1481 <<
1482 <<
1483 <<
1484 <<
1485 }; <<
1486 <<
1487 admai <<
1488 <<
1489 <<
1490 <<
1491 <<
1492 <<
1493 }; <<
1494 <<
1495 admai <<
1496 <<
1497 <<
1498 <<
1499 <<
1500 <<
1501 }; <<
1502 }; <<
1503 }; <<
1504 <<
1505 tegra_i2s1: i2s@702d1 <<
1506 compatible = <<
1507 reg = <0x702d <<
1508 clocks = <&te <<
1509 <&te <<
1510 clock-names = <<
1511 assigned-cloc <<
1512 assigned-cloc <<
1513 assigned-cloc <<
1514 sound-name-pr <<
1515 status = "dis <<
1516 }; <<
1517 <<
1518 tegra_i2s2: i2s@702d1 <<
1519 compatible = <<
1520 reg = <0x702d <<
1521 clocks = <&te <<
1522 <&te <<
1523 clock-names = <<
1524 assigned-cloc <<
1525 assigned-cloc <<
1526 assigned-cloc <<
1527 sound-name-pr <<
1528 status = "dis <<
1529 }; <<
1530 <<
1531 tegra_i2s3: i2s@702d1 <<
1532 compatible = <<
1533 reg = <0x702d <<
1534 clocks = <&te <<
1535 <&te <<
1536 clock-names = <<
1537 assigned-cloc <<
1538 assigned-cloc <<
1539 assigned-cloc <<
1540 sound-name-pr <<
1541 status = "dis <<
1542 }; <<
1543 <<
1544 tegra_i2s4: i2s@702d1 <<
1545 compatible = <<
1546 reg = <0x702d <<
1547 clocks = <&te <<
1548 <&te <<
1549 clock-names = <<
1550 assigned-cloc <<
1551 assigned-cloc <<
1552 assigned-cloc <<
1553 sound-name-pr <<
1554 status = "dis <<
1555 }; <<
1556 <<
1557 tegra_i2s5: i2s@702d1 <<
1558 compatible = <<
1559 reg = <0x702d <<
1560 clocks = <&te <<
1561 <&te <<
1562 clock-names = <<
1563 assigned-cloc <<
1564 assigned-cloc <<
1565 assigned-cloc <<
1566 sound-name-pr <<
1567 status = "dis <<
1568 }; <<
1569 <<
1570 tegra_sfc1: sfc@702d2 <<
1571 compatible = <<
1572 reg = <0x702d <<
1573 sound-name-pr <<
1574 status = "dis <<
1575 }; <<
1576 <<
1577 tegra_sfc2: sfc@702d2 <<
1578 compatible = <<
1579 reg = <0x702d <<
1580 sound-name-pr <<
1581 status = "dis <<
1582 }; <<
1583 <<
1584 tegra_sfc3: sfc@702d2 <<
1585 compatible = <<
1586 reg = <0x702d <<
1587 sound-name-pr <<
1588 status = "dis <<
1589 }; <<
1590 <<
1591 tegra_sfc4: sfc@702d2 <<
1592 compatible = <<
1593 reg = <0x702d <<
1594 sound-name-pr <<
1595 status = "dis <<
1596 }; <<
1597 <<
1598 tegra_amx1: amx@702d3 <<
1599 compatible = <<
1600 reg = <0x702d <<
1601 sound-name-pr <<
1602 status = "dis <<
1603 }; <<
1604 <<
1605 tegra_amx2: amx@702d3 <<
1606 compatible = <<
1607 reg = <0x702d <<
1608 sound-name-pr <<
1609 status = "dis <<
1610 }; <<
1611 <<
1612 tegra_adx1: adx@702d3 <<
1613 compatible = <<
1614 reg = <0x702d <<
1615 sound-name-pr <<
1616 status = "dis <<
1617 }; <<
1618 <<
1619 tegra_adx2: adx@702d3 <<
1620 compatible = <<
1621 reg = <0x702d <<
1622 sound-name-pr <<
1623 status = "dis <<
1624 }; <<
1625 <<
1626 tegra_dmic1: dmic@702 <<
1627 compatible = <<
1628 reg = <0x702d <<
1629 clocks = <&te <<
1630 clock-names = <<
1631 assigned-cloc <<
1632 assigned-cloc <<
1633 assigned-cloc <<
1634 sound-name-pr <<
1635 status = "dis <<
1636 }; <<
1637 <<
1638 tegra_dmic2: dmic@702 <<
1639 compatible = <<
1640 reg = <0x702d <<
1641 clocks = <&te <<
1642 clock-names = <<
1643 assigned-cloc <<
1644 assigned-cloc <<
1645 assigned-cloc <<
1646 sound-name-pr <<
1647 status = "dis <<
1648 }; <<
1649 <<
1650 tegra_dmic3: dmic@702 <<
1651 compatible = <<
1652 reg = <0x702d <<
1653 clocks = <&te <<
1654 clock-names = <<
1655 assigned-cloc <<
1656 assigned-cloc <<
1657 assigned-cloc <<
1658 sound-name-pr <<
1659 status = "dis <<
1660 }; <<
1661 <<
1662 tegra_ope1: processin <<
1663 compatible = <<
1664 reg = <0x702d <<
1665 #address-cell <<
1666 #size-cells = <<
1667 ranges; <<
1668 sound-name-pr <<
1669 status = "dis <<
1670 <<
1671 equalizer@702 <<
1672 compa <<
1673 reg = <<
1674 }; <<
1675 <<
1676 dynamic-range <<
1677 compa <<
1678 reg = <<
1679 }; <<
1680 }; <<
1681 <<
1682 tegra_ope2: processin <<
1683 compatible = <<
1684 reg = <0x702d <<
1685 #address-cell <<
1686 #size-cells = <<
1687 ranges; <<
1688 sound-name-pr <<
1689 status = "dis <<
1690 <<
1691 equalizer@702 <<
1692 compa <<
1693 reg = <<
1694 }; <<
1695 <<
1696 dynamic-range <<
1697 compa <<
1698 reg = <<
1699 }; <<
1700 }; <<
1701 <<
1702 tegra_mvc1: mvc@702da <<
1703 compatible = <<
1704 reg = <0x702d <<
1705 sound-name-pr <<
1706 status = "dis <<
1707 }; <<
1708 <<
1709 tegra_mvc2: mvc@702da <<
1710 compatible = <<
1711 reg = <0x702d <<
1712 sound-name-pr <<
1713 status = "dis <<
1714 }; <<
1715 <<
1716 tegra_amixer: amixer@ <<
1717 compatible = <<
1718 reg = <0x702d <<
1719 sound-name-pr <<
1720 status = "dis <<
1721 }; <<
1722 <<
1723 ports { <<
1724 #address-cell <<
1725 #size-cells = <<
1726 <<
1727 port@0 { <<
1728 reg = <<
1729 <<
1730 xbar_ <<
1731 <<
1732 }; <<
1733 }; <<
1734 <<
1735 port@1 { <<
1736 reg = <<
1737 <<
1738 xbar_ <<
1739 <<
1740 }; <<
1741 }; <<
1742 <<
1743 port@2 { <<
1744 reg = <<
1745 <<
1746 xbar_ <<
1747 <<
1748 }; <<
1749 }; <<
1750 <<
1751 port@3 { <<
1752 reg = <<
1753 <<
1754 xbar_ <<
1755 <<
1756 }; <<
1757 }; <<
1758 <<
1759 port@4 { <<
1760 reg = <<
1761 xbar_ <<
1762 <<
1763 }; <<
1764 }; <<
1765 port@5 { <<
1766 reg = <<
1767 <<
1768 xbar_ <<
1769 <<
1770 }; <<
1771 }; <<
1772 <<
1773 port@6 { <<
1774 reg = <<
1775 <<
1776 xbar_ <<
1777 <<
1778 }; <<
1779 }; <<
1780 <<
1781 port@7 { <<
1782 reg = <<
1783 <<
1784 xbar_ <<
1785 <<
1786 }; <<
1787 }; <<
1788 <<
1789 port@8 { <<
1790 reg = <<
1791 <<
1792 xbar_ <<
1793 <<
1794 }; <<
1795 }; <<
1796 <<
1797 port@9 { <<
1798 reg = <<
1799 <<
1800 xbar_ <<
1801 <<
1802 }; <<
1803 }; <<
1804 }; <<
1805 }; <<
1806 <<
1807 adma: dma-controller@702e2000 <<
1808 compatible = "nvidia, 1071 compatible = "nvidia,tegra210-adma";
1809 reg = <0x702e2000 0x2 1072 reg = <0x702e2000 0x2000>;
1810 interrupt-parent = <& 1073 interrupt-parent = <&agic>;
1811 interrupts = <GIC_SPI 1074 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
1812 <GIC_SPI 1075 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
1813 <GIC_SPI 1076 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
1814 <GIC_SPI 1077 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
1815 <GIC_SPI 1078 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
1816 <GIC_SPI 1079 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
1817 <GIC_SPI 1080 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
1818 <GIC_SPI 1081 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
1819 <GIC_SPI 1082 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
1820 <GIC_SPI 1083 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
1821 <GIC_SPI 1084 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
1822 <GIC_SPI 1085 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
1823 <GIC_SPI 1086 <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
1824 <GIC_SPI 1087 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
1825 <GIC_SPI 1088 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
1826 <GIC_SPI 1089 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
1827 <GIC_SPI 1090 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
1828 <GIC_SPI 1091 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
1829 <GIC_SPI 1092 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
1830 <GIC_SPI 1093 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
1831 <GIC_SPI 1094 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
1832 <GIC_SPI 1095 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1833 #dma-cells = <1>; 1096 #dma-cells = <1>;
1834 clocks = <&tegra_car 1097 clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>;
1835 clock-names = "d_audi 1098 clock-names = "d_audio";
1836 status = "disabled"; 1099 status = "disabled";
1837 }; 1100 };
1838 1101
1839 agic: interrupt-controller@70 !! 1102 agic: agic@702f9000 {
1840 compatible = "nvidia, 1103 compatible = "nvidia,tegra210-agic";
1841 #interrupt-cells = <3 1104 #interrupt-cells = <3>;
1842 interrupt-controller; 1105 interrupt-controller;
1843 reg = <0x702f9000 0x1 !! 1106 reg = <0x702f9000 0x2000>,
1844 <0x702fa000 0x2 1107 <0x702fa000 0x2000>;
1845 interrupts = <GIC_SPI 1108 interrupts = <GIC_SPI 102 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1846 clocks = <&tegra_car 1109 clocks = <&tegra_car TEGRA210_CLK_APE>;
1847 clock-names = "clk"; 1110 clock-names = "clk";
1848 status = "disabled"; 1111 status = "disabled";
1849 }; 1112 };
1850 }; 1113 };
1851 1114
1852 spi@70410000 { 1115 spi@70410000 {
1853 compatible = "nvidia,tegra210 1116 compatible = "nvidia,tegra210-qspi";
1854 reg = <0x0 0x70410000 0x0 0x1 1117 reg = <0x0 0x70410000 0x0 0x1000>;
1855 interrupts = <GIC_SPI 10 IRQ_ 1118 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1856 #address-cells = <1>; 1119 #address-cells = <1>;
1857 #size-cells = <0>; 1120 #size-cells = <0>;
1858 clocks = <&tegra_car TEGRA210 !! 1121 clocks = <&tegra_car TEGRA210_CLK_QSPI>;
1859 <&tegra_car TEGRA210 !! 1122 clock-names = "qspi";
1860 clock-names = "qspi", "qspi_o <<
1861 resets = <&tegra_car 211>; 1123 resets = <&tegra_car 211>;
>> 1124 reset-names = "qspi";
1862 dmas = <&apbdma 5>, <&apbdma 1125 dmas = <&apbdma 5>, <&apbdma 5>;
1863 dma-names = "rx", "tx"; 1126 dma-names = "rx", "tx";
1864 status = "disabled"; 1127 status = "disabled";
1865 }; 1128 };
1866 1129
1867 usb@7d000000 { 1130 usb@7d000000 {
1868 compatible = "nvidia,tegra210 !! 1131 compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci";
1869 reg = <0x0 0x7d000000 0x0 0x4 1132 reg = <0x0 0x7d000000 0x0 0x4000>;
1870 interrupts = <GIC_SPI 20 IRQ_ 1133 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1871 phy_type = "utmi"; 1134 phy_type = "utmi";
1872 clocks = <&tegra_car TEGRA210 1135 clocks = <&tegra_car TEGRA210_CLK_USBD>;
1873 clock-names = "usb"; 1136 clock-names = "usb";
1874 resets = <&tegra_car 22>; 1137 resets = <&tegra_car 22>;
1875 reset-names = "usb"; 1138 reset-names = "usb";
1876 nvidia,phy = <&phy1>; 1139 nvidia,phy = <&phy1>;
1877 status = "disabled"; 1140 status = "disabled";
1878 }; 1141 };
1879 1142
1880 phy1: usb-phy@7d000000 { 1143 phy1: usb-phy@7d000000 {
1881 compatible = "nvidia,tegra210 1144 compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy";
1882 reg = <0x0 0x7d000000 0x0 0x4 1145 reg = <0x0 0x7d000000 0x0 0x4000>,
1883 <0x0 0x7d000000 0x0 0x4 1146 <0x0 0x7d000000 0x0 0x4000>;
1884 phy_type = "utmi"; 1147 phy_type = "utmi";
1885 clocks = <&tegra_car TEGRA210 1148 clocks = <&tegra_car TEGRA210_CLK_USBD>,
1886 <&tegra_car TEGRA210 1149 <&tegra_car TEGRA210_CLK_PLL_U>,
1887 <&tegra_car TEGRA210 1150 <&tegra_car TEGRA210_CLK_USBD>;
1888 clock-names = "reg", "pll_u", 1151 clock-names = "reg", "pll_u", "utmi-pads";
1889 resets = <&tegra_car 22>, <&t 1152 resets = <&tegra_car 22>, <&tegra_car 22>;
1890 reset-names = "usb", "utmi-pa 1153 reset-names = "usb", "utmi-pads";
1891 nvidia,hssync-start-delay = < 1154 nvidia,hssync-start-delay = <0>;
1892 nvidia,idle-wait-delay = <17> 1155 nvidia,idle-wait-delay = <17>;
1893 nvidia,elastic-limit = <16>; 1156 nvidia,elastic-limit = <16>;
1894 nvidia,term-range-adj = <6>; 1157 nvidia,term-range-adj = <6>;
1895 nvidia,xcvr-setup = <9>; 1158 nvidia,xcvr-setup = <9>;
1896 nvidia,xcvr-lsfslew = <0>; 1159 nvidia,xcvr-lsfslew = <0>;
1897 nvidia,xcvr-lsrslew = <3>; 1160 nvidia,xcvr-lsrslew = <3>;
1898 nvidia,hssquelch-level = <2>; 1161 nvidia,hssquelch-level = <2>;
1899 nvidia,hsdiscon-level = <5>; 1162 nvidia,hsdiscon-level = <5>;
1900 nvidia,xcvr-hsslew = <12>; 1163 nvidia,xcvr-hsslew = <12>;
1901 nvidia,has-utmi-pad-registers 1164 nvidia,has-utmi-pad-registers;
1902 status = "disabled"; 1165 status = "disabled";
1903 }; 1166 };
1904 1167
1905 usb@7d004000 { 1168 usb@7d004000 {
1906 compatible = "nvidia,tegra210 !! 1169 compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci";
1907 reg = <0x0 0x7d004000 0x0 0x4 1170 reg = <0x0 0x7d004000 0x0 0x4000>;
1908 interrupts = <GIC_SPI 21 IRQ_ 1171 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
1909 phy_type = "utmi"; 1172 phy_type = "utmi";
1910 clocks = <&tegra_car TEGRA210 1173 clocks = <&tegra_car TEGRA210_CLK_USB2>;
1911 clock-names = "usb"; 1174 clock-names = "usb";
1912 resets = <&tegra_car 58>; 1175 resets = <&tegra_car 58>;
1913 reset-names = "usb"; 1176 reset-names = "usb";
1914 nvidia,phy = <&phy2>; 1177 nvidia,phy = <&phy2>;
1915 status = "disabled"; 1178 status = "disabled";
1916 }; 1179 };
1917 1180
1918 phy2: usb-phy@7d004000 { 1181 phy2: usb-phy@7d004000 {
1919 compatible = "nvidia,tegra210 1182 compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy";
1920 reg = <0x0 0x7d004000 0x0 0x4 1183 reg = <0x0 0x7d004000 0x0 0x4000>,
1921 <0x0 0x7d000000 0x0 0x4 1184 <0x0 0x7d000000 0x0 0x4000>;
1922 phy_type = "utmi"; 1185 phy_type = "utmi";
1923 clocks = <&tegra_car TEGRA210 1186 clocks = <&tegra_car TEGRA210_CLK_USB2>,
1924 <&tegra_car TEGRA210 1187 <&tegra_car TEGRA210_CLK_PLL_U>,
1925 <&tegra_car TEGRA210 1188 <&tegra_car TEGRA210_CLK_USBD>;
1926 clock-names = "reg", "pll_u", 1189 clock-names = "reg", "pll_u", "utmi-pads";
1927 resets = <&tegra_car 58>, <&t 1190 resets = <&tegra_car 58>, <&tegra_car 22>;
1928 reset-names = "usb", "utmi-pa 1191 reset-names = "usb", "utmi-pads";
1929 nvidia,hssync-start-delay = < 1192 nvidia,hssync-start-delay = <0>;
1930 nvidia,idle-wait-delay = <17> 1193 nvidia,idle-wait-delay = <17>;
1931 nvidia,elastic-limit = <16>; 1194 nvidia,elastic-limit = <16>;
1932 nvidia,term-range-adj = <6>; 1195 nvidia,term-range-adj = <6>;
1933 nvidia,xcvr-setup = <9>; 1196 nvidia,xcvr-setup = <9>;
1934 nvidia,xcvr-lsfslew = <0>; 1197 nvidia,xcvr-lsfslew = <0>;
1935 nvidia,xcvr-lsrslew = <3>; 1198 nvidia,xcvr-lsrslew = <3>;
1936 nvidia,hssquelch-level = <2>; 1199 nvidia,hssquelch-level = <2>;
1937 nvidia,hsdiscon-level = <5>; 1200 nvidia,hsdiscon-level = <5>;
1938 nvidia,xcvr-hsslew = <12>; 1201 nvidia,xcvr-hsslew = <12>;
1939 status = "disabled"; 1202 status = "disabled";
1940 }; 1203 };
1941 1204
1942 cpus { 1205 cpus {
1943 #address-cells = <1>; 1206 #address-cells = <1>;
1944 #size-cells = <0>; 1207 #size-cells = <0>;
1945 1208
1946 cpu@0 { 1209 cpu@0 {
1947 device_type = "cpu"; 1210 device_type = "cpu";
1948 compatible = "arm,cor 1211 compatible = "arm,cortex-a57";
1949 reg = <0>; 1212 reg = <0>;
1950 clocks = <&tegra_car <<
1951 <&tegra_car <<
1952 <&tegra_car <<
1953 <&dfll>; <<
1954 clock-names = "cpu_g" <<
1955 clock-latency = <3000 <<
1956 cpu-idle-states = <&C <<
1957 next-level-cache = <& <<
1958 }; 1213 };
1959 1214
1960 cpu@1 { 1215 cpu@1 {
1961 device_type = "cpu"; 1216 device_type = "cpu";
1962 compatible = "arm,cor 1217 compatible = "arm,cortex-a57";
1963 reg = <1>; 1218 reg = <1>;
1964 cpu-idle-states = <&C <<
1965 next-level-cache = <& <<
1966 }; 1219 };
1967 1220
1968 cpu@2 { 1221 cpu@2 {
1969 device_type = "cpu"; 1222 device_type = "cpu";
1970 compatible = "arm,cor 1223 compatible = "arm,cortex-a57";
1971 reg = <2>; 1224 reg = <2>;
1972 cpu-idle-states = <&C <<
1973 next-level-cache = <& <<
1974 }; 1225 };
1975 1226
1976 cpu@3 { 1227 cpu@3 {
1977 device_type = "cpu"; 1228 device_type = "cpu";
1978 compatible = "arm,cor 1229 compatible = "arm,cortex-a57";
1979 reg = <3>; 1230 reg = <3>;
1980 cpu-idle-states = <&C <<
1981 next-level-cache = <& <<
1982 }; <<
1983 <<
1984 idle-states { <<
1985 entry-method = "psci" <<
1986 <<
1987 CPU_SLEEP: cpu-sleep <<
1988 compatible = <<
1989 arm,psci-susp <<
1990 entry-latency <<
1991 exit-latency- <<
1992 min-residency <<
1993 wakeup-latenc <<
1994 idle-state-na <<
1995 status = "dis <<
1996 }; <<
1997 }; <<
1998 <<
1999 L2: l2-cache { <<
2000 compatible = "cache"; <<
2001 cache-level = <2>; <<
2002 cache-unified; <<
2003 }; 1231 };
2004 }; 1232 };
2005 1233
2006 pmu { !! 1234 timer {
2007 compatible = "arm,cortex-a57- !! 1235 compatible = "arm,armv8-timer";
2008 interrupts = <GIC_SPI 144 IRQ !! 1236 interrupts = <GIC_PPI 13
2009 <GIC_SPI 145 IRQ !! 1237 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2010 <GIC_SPI 146 IRQ !! 1238 <GIC_PPI 14
2011 <GIC_SPI 147 IRQ !! 1239 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2012 interrupt-affinity = <&{/cpus !! 1240 <GIC_PPI 11
2013 &{/cpus !! 1241 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
>> 1242 <GIC_PPI 10
>> 1243 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
>> 1244 interrupt-parent = <&gic>;
2014 }; 1245 };
2015 1246
2016 sound { !! 1247 soctherm: thermal-sensor@700e2000 {
2017 status = "disabled"; !! 1248 compatible = "nvidia,tegra210-soctherm";
>> 1249 reg = <0x0 0x700e2000 0x0 0x600 /* SOC_THERM reg_base */
>> 1250 0x0 0x60006000 0x0 0x400>; /* CAR reg_base */
>> 1251 reg-names = "soctherm-reg", "car-reg";
>> 1252 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
>> 1253 clocks = <&tegra_car TEGRA210_CLK_TSENSOR>,
>> 1254 <&tegra_car TEGRA210_CLK_SOC_THERM>;
>> 1255 clock-names = "tsensor", "soctherm";
>> 1256 resets = <&tegra_car 78>;
>> 1257 reset-names = "soctherm";
>> 1258 #thermal-sensor-cells = <1>;
2018 1259
2019 clocks = <&tegra_car TEGRA210 !! 1260 throttle-cfgs {
2020 <&tegra_car TEGRA210 !! 1261 throttle_heavy: heavy {
2021 clock-names = "pll_a", "plla_ !! 1262 nvidia,priority = <100>;
>> 1263 nvidia,cpu-throt-percent = <85>;
2022 1264
2023 assigned-clocks = <&tegra_car !! 1265 #cooling-cells = <2>;
2024 <&tegra_car !! 1266 };
2025 <&tegra_car !! 1267 };
2026 assigned-clock-parents = <0>, <<
2027 assigned-clock-rates = <36864 <<
2028 }; 1268 };
2029 1269
2030 thermal-zones { 1270 thermal-zones {
2031 cpu-thermal { !! 1271 cpu {
2032 polling-delay-passive 1272 polling-delay-passive = <1000>;
2033 polling-delay = <0>; 1273 polling-delay = <0>;
2034 1274
2035 thermal-sensors = 1275 thermal-sensors =
2036 <&soctherm TE 1276 <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>;
2037 1277
2038 trips { 1278 trips {
2039 cpu-shutdown- 1279 cpu-shutdown-trip {
2040 tempe 1280 temperature = <102500>;
2041 hyste 1281 hysteresis = <0>;
2042 type 1282 type = "critical";
2043 }; 1283 };
2044 1284
2045 cpu_throttle_ 1285 cpu_throttle_trip: throttle-trip {
2046 tempe 1286 temperature = <98500>;
2047 hyste 1287 hysteresis = <1000>;
2048 type 1288 type = "hot";
2049 }; 1289 };
2050 }; 1290 };
2051 1291
2052 cooling-maps { 1292 cooling-maps {
2053 map0 { 1293 map0 {
2054 trip 1294 trip = <&cpu_throttle_trip>;
2055 cooli 1295 cooling-device = <&throttle_heavy 1 1>;
2056 }; 1296 };
2057 }; 1297 };
2058 }; 1298 };
2059 !! 1299 mem {
2060 mem-thermal { <<
2061 polling-delay-passive 1300 polling-delay-passive = <0>;
2062 polling-delay = <0>; 1301 polling-delay = <0>;
2063 1302
2064 thermal-sensors = 1303 thermal-sensors =
2065 <&soctherm TE 1304 <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>;
2066 1305
2067 trips { 1306 trips {
2068 dram_nominal: <<
2069 tempe <<
2070 hyste <<
2071 type <<
2072 }; <<
2073 <<
2074 dram_throttle <<
2075 tempe <<
2076 hyste <<
2077 type <<
2078 }; <<
2079 <<
2080 mem-hot-trip <<
2081 tempe <<
2082 hyste <<
2083 type <<
2084 }; <<
2085 <<
2086 mem-shutdown- 1307 mem-shutdown-trip {
2087 tempe 1308 temperature = <103000>;
2088 hyste 1309 hysteresis = <0>;
2089 type 1310 type = "critical";
2090 }; 1311 };
2091 }; 1312 };
2092 1313
2093 cooling-maps { 1314 cooling-maps {
2094 dram-passive !! 1315 /*
2095 cooli !! 1316 * There are currently no cooling maps,
2096 trip !! 1317 * because there are no cooling devices.
2097 }; !! 1318 */
2098 <<
2099 dram-active { <<
2100 cooli <<
2101 trip <<
2102 }; <<
2103 }; 1319 };
2104 }; 1320 };
2105 !! 1321 gpu {
2106 gpu-thermal { <<
2107 polling-delay-passive 1322 polling-delay-passive = <1000>;
2108 polling-delay = <0>; 1323 polling-delay = <0>;
2109 1324
2110 thermal-sensors = 1325 thermal-sensors =
2111 <&soctherm TE 1326 <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>;
2112 1327
2113 trips { 1328 trips {
2114 gpu-shutdown- 1329 gpu-shutdown-trip {
2115 tempe 1330 temperature = <103000>;
2116 hyste 1331 hysteresis = <0>;
2117 type 1332 type = "critical";
2118 }; 1333 };
2119 1334
2120 gpu_throttle_ 1335 gpu_throttle_trip: throttle-trip {
2121 tempe 1336 temperature = <100000>;
2122 hyste 1337 hysteresis = <1000>;
2123 type 1338 type = "hot";
2124 }; 1339 };
2125 }; 1340 };
2126 1341
2127 cooling-maps { 1342 cooling-maps {
2128 map0 { 1343 map0 {
2129 trip 1344 trip = <&gpu_throttle_trip>;
2130 cooli 1345 cooling-device = <&throttle_heavy 1 1>;
2131 }; 1346 };
2132 }; 1347 };
2133 }; 1348 };
2134 !! 1349 pllx {
2135 pllx-thermal { <<
2136 polling-delay-passive 1350 polling-delay-passive = <0>;
2137 polling-delay = <0>; 1351 polling-delay = <0>;
2138 1352
2139 thermal-sensors = 1353 thermal-sensors =
2140 <&soctherm TE 1354 <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>;
2141 1355
2142 trips { 1356 trips {
2143 pllx-shutdown 1357 pllx-shutdown-trip {
2144 tempe 1358 temperature = <103000>;
2145 hyste 1359 hysteresis = <0>;
2146 type 1360 type = "critical";
2147 }; 1361 };
2148 <<
2149 pllx-throttle <<
2150 tempe <<
2151 hyste <<
2152 type <<
2153 }; <<
2154 }; 1362 };
2155 1363
2156 cooling-maps { 1364 cooling-maps {
2157 /* 1365 /*
2158 * There are 1366 * There are currently no cooling maps,
2159 * because th 1367 * because there are no cooling devices.
2160 */ 1368 */
2161 }; 1369 };
2162 }; 1370 };
2163 }; <<
2164 <<
2165 timer { <<
2166 compatible = "arm,armv8-timer <<
2167 interrupts = <GIC_PPI 13 <<
2168 (GIC_CPU_MASK <<
2169 <GIC_PPI 14 <<
2170 (GIC_CPU_MASK <<
2171 <GIC_PPI 11 <<
2172 (GIC_CPU_MASK <<
2173 <GIC_PPI 10 <<
2174 (GIC_CPU_MASK <<
2175 interrupt-parent = <&gic>; <<
2176 arm,no-tick-in-suspend; <<
2177 }; 1371 };
2178 }; 1372 };
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