1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra210-car.h> 2 #include <dt-bindings/clock/tegra210-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h> 3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra210-mc.h> 4 #include <dt-bindings/memory/tegra210-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h> 5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra-io 6 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
7 #include <dt-bindings/reset/tegra210-car.h> <<
8 #include <dt-bindings/interrupt-controller/arm 7 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/thermal/tegra124-socther 8 #include <dt-bindings/thermal/tegra124-soctherm.h>
10 #include <dt-bindings/soc/tegra-pmc.h> <<
11 9
12 / { 10 / {
13 compatible = "nvidia,tegra210"; 11 compatible = "nvidia,tegra210";
14 interrupt-parent = <&lic>; 12 interrupt-parent = <&lic>;
15 #address-cells = <2>; 13 #address-cells = <2>;
16 #size-cells = <2>; 14 #size-cells = <2>;
17 15
18 pcie@1003000 { 16 pcie@1003000 {
19 compatible = "nvidia,tegra210- 17 compatible = "nvidia,tegra210-pcie";
20 device_type = "pci"; 18 device_type = "pci";
21 reg = <0x0 0x01003000 0x0 0x00 !! 19 reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */
22 <0x0 0x01003800 0x0 0x00 !! 20 0x0 0x01003800 0x0 0x00000800 /* AFI registers */
23 <0x0 0x02000000 0x0 0x10 !! 21 0x0 0x02000000 0x0 0x10000000>; /* configuration space */
24 reg-names = "pads", "afi", "cs 22 reg-names = "pads", "afi", "cs";
25 interrupts = <GIC_SPI 98 IRQ_T 23 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
26 <GIC_SPI 99 IRQ_T 24 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
27 interrupt-names = "intr", "msi 25 interrupt-names = "intr", "msi";
28 26
29 #interrupt-cells = <1>; 27 #interrupt-cells = <1>;
30 interrupt-map-mask = <0 0 0 0> 28 interrupt-map-mask = <0 0 0 0>;
31 interrupt-map = <0 0 0 0 &gic 29 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
32 30
33 bus-range = <0x00 0xff>; 31 bus-range = <0x00 0xff>;
34 #address-cells = <3>; 32 #address-cells = <3>;
35 #size-cells = <2>; 33 #size-cells = <2>;
36 34
37 ranges = <0x02000000 0 0x01000 !! 35 ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000 /* port 0 configuration space */
38 <0x02000000 0 0x01001 !! 36 0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000 /* port 1 configuration space */
39 <0x01000000 0 0x0 !! 37 0x81000000 0 0x0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */
40 <0x02000000 0 0x13000 !! 38 0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */
41 <0x42000000 0 0x20000 !! 39 0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
42 40
43 clocks = <&tegra_car TEGRA210_ 41 clocks = <&tegra_car TEGRA210_CLK_PCIE>,
44 <&tegra_car TEGRA210_ 42 <&tegra_car TEGRA210_CLK_AFI>,
45 <&tegra_car TEGRA210_ 43 <&tegra_car TEGRA210_CLK_PLL_E>,
46 <&tegra_car TEGRA210_ 44 <&tegra_car TEGRA210_CLK_CML0>;
47 clock-names = "pex", "afi", "p 45 clock-names = "pex", "afi", "pll_e", "cml";
48 resets = <&tegra_car 70>, 46 resets = <&tegra_car 70>,
49 <&tegra_car 72>, 47 <&tegra_car 72>,
50 <&tegra_car 74>; 48 <&tegra_car 74>;
51 reset-names = "pex", "afi", "p 49 reset-names = "pex", "afi", "pcie_x";
52 <<
53 pinctrl-names = "default", "id <<
54 pinctrl-0 = <&pex_dpd_disable> <<
55 pinctrl-1 = <&pex_dpd_enable>; <<
56 <<
57 status = "disabled"; 50 status = "disabled";
58 51
59 pci@1,0 { 52 pci@1,0 {
60 device_type = "pci"; 53 device_type = "pci";
61 assigned-addresses = < 54 assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
62 reg = <0x000800 0 0 0 55 reg = <0x000800 0 0 0 0>;
63 bus-range = <0x00 0xff 56 bus-range = <0x00 0xff>;
64 status = "disabled"; 57 status = "disabled";
65 58
66 #address-cells = <3>; 59 #address-cells = <3>;
67 #size-cells = <2>; 60 #size-cells = <2>;
68 ranges; 61 ranges;
69 62
70 nvidia,num-lanes = <4> 63 nvidia,num-lanes = <4>;
71 }; 64 };
72 65
73 pci@2,0 { 66 pci@2,0 {
74 device_type = "pci"; 67 device_type = "pci";
75 assigned-addresses = < 68 assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
76 reg = <0x001000 0 0 0 69 reg = <0x001000 0 0 0 0>;
77 bus-range = <0x00 0xff 70 bus-range = <0x00 0xff>;
78 status = "disabled"; 71 status = "disabled";
79 72
80 #address-cells = <3>; 73 #address-cells = <3>;
81 #size-cells = <2>; 74 #size-cells = <2>;
82 ranges; 75 ranges;
83 76
84 nvidia,num-lanes = <1> 77 nvidia,num-lanes = <1>;
85 }; 78 };
86 }; 79 };
87 80
88 host1x@50000000 { 81 host1x@50000000 {
89 compatible = "nvidia,tegra210- !! 82 compatible = "nvidia,tegra210-host1x", "simple-bus";
90 reg = <0x0 0x50000000 0x0 0x00 83 reg = <0x0 0x50000000 0x0 0x00034000>;
91 interrupts = <GIC_SPI 65 IRQ_T 84 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
92 <GIC_SPI 67 IRQ_T 85 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
93 interrupt-names = "syncpt", "h <<
94 clocks = <&tegra_car TEGRA210_ 86 clocks = <&tegra_car TEGRA210_CLK_HOST1X>;
95 clock-names = "host1x"; 87 clock-names = "host1x";
96 resets = <&tegra_car 28>, <&mc !! 88 resets = <&tegra_car 28>;
97 reset-names = "host1x", "mc"; !! 89 reset-names = "host1x";
98 90
99 #address-cells = <2>; 91 #address-cells = <2>;
100 #size-cells = <2>; 92 #size-cells = <2>;
101 93
102 ranges = <0x0 0x54000000 0x0 0 94 ranges = <0x0 0x54000000 0x0 0x54000000 0x0 0x01000000>;
103 95
104 iommus = <&mc TEGRA_SWGROUP_HC 96 iommus = <&mc TEGRA_SWGROUP_HC>;
105 97
106 dpaux1: dpaux@54040000 { 98 dpaux1: dpaux@54040000 {
107 compatible = "nvidia,t 99 compatible = "nvidia,tegra210-dpaux";
108 reg = <0x0 0x54040000 100 reg = <0x0 0x54040000 0x0 0x00040000>;
109 interrupts = <GIC_SPI 101 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
110 clocks = <&tegra_car T 102 clocks = <&tegra_car TEGRA210_CLK_DPAUX1>,
111 <&tegra_car T 103 <&tegra_car TEGRA210_CLK_PLL_DP>;
112 clock-names = "dpaux", 104 clock-names = "dpaux", "parent";
113 resets = <&tegra_car 2 105 resets = <&tegra_car 207>;
114 reset-names = "dpaux"; 106 reset-names = "dpaux";
115 power-domains = <&pd_s 107 power-domains = <&pd_sor>;
116 status = "disabled"; 108 status = "disabled";
117 109
118 state_dpaux1_aux: pinm 110 state_dpaux1_aux: pinmux-aux {
119 groups = "dpau 111 groups = "dpaux-io";
120 function = "au 112 function = "aux";
121 }; 113 };
122 114
123 state_dpaux1_i2c: pinm 115 state_dpaux1_i2c: pinmux-i2c {
124 groups = "dpau 116 groups = "dpaux-io";
125 function = "i2 117 function = "i2c";
126 }; 118 };
127 119
128 state_dpaux1_off: pinm 120 state_dpaux1_off: pinmux-off {
129 groups = "dpau 121 groups = "dpaux-io";
130 function = "of 122 function = "off";
131 }; 123 };
132 124
133 i2c-bus { 125 i2c-bus {
134 #address-cells 126 #address-cells = <1>;
135 #size-cells = 127 #size-cells = <0>;
136 }; 128 };
137 }; 129 };
138 130
139 vi@54080000 { 131 vi@54080000 {
140 compatible = "nvidia,t 132 compatible = "nvidia,tegra210-vi";
141 reg = <0x0 0x54080000 !! 133 reg = <0x0 0x54080000 0x0 0x00040000>;
142 interrupts = <GIC_SPI 134 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
143 status = "disabled"; 135 status = "disabled";
144 assigned-clocks = <&te <<
145 assigned-clock-parents <<
146 <<
147 clocks = <&tegra_car T <<
148 power-domains = <&pd_v <<
149 <<
150 #address-cells = <1>; <<
151 #size-cells = <1>; <<
152 <<
153 ranges = <0x0 0x0 0x54 <<
154 <<
155 csi@838 { <<
156 compatible = " <<
157 reg = <0x838 0 <<
158 status = "disa <<
159 assigned-clock <<
160 <<
161 <<
162 <<
163 assigned-clock <<
164 <<
165 <<
166 assigned-clock <<
167 <<
168 <<
169 <<
170 <<
171 clocks = <&teg <<
172 <&teg <<
173 <&teg <<
174 <&teg <<
175 <&teg <<
176 clock-names = <<
177 power-domains <<
178 }; <<
179 }; 136 };
180 137
181 tsec@54100000 { 138 tsec@54100000 {
182 compatible = "nvidia,t 139 compatible = "nvidia,tegra210-tsec";
183 reg = <0x0 0x54100000 140 reg = <0x0 0x54100000 0x0 0x00040000>;
184 interrupts = <GIC_SPI <<
185 clocks = <&tegra_car T <<
186 clock-names = "tsec"; <<
187 resets = <&tegra_car 8 <<
188 reset-names = "tsec"; <<
189 status = "disabled"; <<
190 }; 141 };
191 142
192 dc@54200000 { 143 dc@54200000 {
193 compatible = "nvidia,t 144 compatible = "nvidia,tegra210-dc";
194 reg = <0x0 0x54200000 145 reg = <0x0 0x54200000 0x0 0x00040000>;
195 interrupts = <GIC_SPI 146 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
196 clocks = <&tegra_car T !! 147 clocks = <&tegra_car TEGRA210_CLK_DISP1>,
197 clock-names = "dc"; !! 148 <&tegra_car TEGRA210_CLK_PLL_P>;
>> 149 clock-names = "dc", "parent";
198 resets = <&tegra_car 2 150 resets = <&tegra_car 27>;
199 reset-names = "dc"; 151 reset-names = "dc";
200 152
201 iommus = <&mc TEGRA_SW 153 iommus = <&mc TEGRA_SWGROUP_DC>;
202 154
203 nvidia,outputs = <&dsi <<
204 nvidia,head = <0>; 155 nvidia,head = <0>;
205 }; 156 };
206 157
207 dc@54240000 { 158 dc@54240000 {
208 compatible = "nvidia,t 159 compatible = "nvidia,tegra210-dc";
209 reg = <0x0 0x54240000 160 reg = <0x0 0x54240000 0x0 0x00040000>;
210 interrupts = <GIC_SPI 161 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
211 clocks = <&tegra_car T !! 162 clocks = <&tegra_car TEGRA210_CLK_DISP2>,
212 clock-names = "dc"; !! 163 <&tegra_car TEGRA210_CLK_PLL_P>;
>> 164 clock-names = "dc", "parent";
213 resets = <&tegra_car 2 165 resets = <&tegra_car 26>;
214 reset-names = "dc"; 166 reset-names = "dc";
215 167
216 iommus = <&mc TEGRA_SW 168 iommus = <&mc TEGRA_SWGROUP_DCB>;
217 169
218 nvidia,outputs = <&dsi <<
219 nvidia,head = <1>; 170 nvidia,head = <1>;
220 }; 171 };
221 172
222 dsia: dsi@54300000 { !! 173 dsi@54300000 {
223 compatible = "nvidia,t 174 compatible = "nvidia,tegra210-dsi";
224 reg = <0x0 0x54300000 175 reg = <0x0 0x54300000 0x0 0x00040000>;
225 clocks = <&tegra_car T 176 clocks = <&tegra_car TEGRA210_CLK_DSIA>,
226 <&tegra_car T 177 <&tegra_car TEGRA210_CLK_DSIALP>,
227 <&tegra_car T 178 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>;
228 clock-names = "dsi", " 179 clock-names = "dsi", "lp", "parent";
229 resets = <&tegra_car 4 180 resets = <&tegra_car 48>;
230 reset-names = "dsi"; 181 reset-names = "dsi";
231 power-domains = <&pd_s 182 power-domains = <&pd_sor>;
232 nvidia,mipi-calibrate 183 nvidia,mipi-calibrate = <&mipi 0x0c0>; /* DSIA & DSIB pads */
233 184
234 status = "disabled"; 185 status = "disabled";
235 186
236 #address-cells = <1>; 187 #address-cells = <1>;
237 #size-cells = <0>; 188 #size-cells = <0>;
238 }; 189 };
239 190
240 vic@54340000 { 191 vic@54340000 {
241 compatible = "nvidia,t 192 compatible = "nvidia,tegra210-vic";
242 reg = <0x0 0x54340000 193 reg = <0x0 0x54340000 0x0 0x00040000>;
243 interrupts = <GIC_SPI 194 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
244 clocks = <&tegra_car T 195 clocks = <&tegra_car TEGRA210_CLK_VIC03>;
245 clock-names = "vic"; 196 clock-names = "vic";
246 resets = <&tegra_car 1 197 resets = <&tegra_car 178>;
247 reset-names = "vic"; 198 reset-names = "vic";
248 199
249 iommus = <&mc TEGRA_SW 200 iommus = <&mc TEGRA_SWGROUP_VIC>;
250 power-domains = <&pd_v 201 power-domains = <&pd_vic>;
251 }; 202 };
252 203
253 nvjpg@54380000 { 204 nvjpg@54380000 {
254 compatible = "nvidia,t 205 compatible = "nvidia,tegra210-nvjpg";
255 reg = <0x0 0x54380000 206 reg = <0x0 0x54380000 0x0 0x00040000>;
256 status = "disabled"; 207 status = "disabled";
257 }; 208 };
258 209
259 dsib: dsi@54400000 { !! 210 dsi@54400000 {
260 compatible = "nvidia,t 211 compatible = "nvidia,tegra210-dsi";
261 reg = <0x0 0x54400000 212 reg = <0x0 0x54400000 0x0 0x00040000>;
262 clocks = <&tegra_car T 213 clocks = <&tegra_car TEGRA210_CLK_DSIB>,
263 <&tegra_car T 214 <&tegra_car TEGRA210_CLK_DSIBLP>,
264 <&tegra_car T 215 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>;
265 clock-names = "dsi", " 216 clock-names = "dsi", "lp", "parent";
266 resets = <&tegra_car 8 217 resets = <&tegra_car 82>;
267 reset-names = "dsi"; 218 reset-names = "dsi";
268 power-domains = <&pd_s 219 power-domains = <&pd_sor>;
269 nvidia,mipi-calibrate 220 nvidia,mipi-calibrate = <&mipi 0x300>; /* DSIC & DSID pads */
270 221
271 status = "disabled"; 222 status = "disabled";
272 223
273 #address-cells = <1>; 224 #address-cells = <1>;
274 #size-cells = <0>; 225 #size-cells = <0>;
275 }; 226 };
276 227
277 nvdec@54480000 { 228 nvdec@54480000 {
278 compatible = "nvidia,t 229 compatible = "nvidia,tegra210-nvdec";
279 reg = <0x0 0x54480000 230 reg = <0x0 0x54480000 0x0 0x00040000>;
280 status = "disabled"; 231 status = "disabled";
281 }; 232 };
282 233
283 nvenc@544c0000 { 234 nvenc@544c0000 {
284 compatible = "nvidia,t 235 compatible = "nvidia,tegra210-nvenc";
285 reg = <0x0 0x544c0000 236 reg = <0x0 0x544c0000 0x0 0x00040000>;
286 status = "disabled"; 237 status = "disabled";
287 }; 238 };
288 239
289 tsec@54500000 { 240 tsec@54500000 {
290 compatible = "nvidia,t 241 compatible = "nvidia,tegra210-tsec";
291 reg = <0x0 0x54500000 242 reg = <0x0 0x54500000 0x0 0x00040000>;
292 interrupts = <GIC_SPI <<
293 clocks = <&tegra_car T <<
294 clock-names = "tsec"; <<
295 resets = <&tegra_car 2 <<
296 reset-names = "tsec"; <<
297 status = "disabled"; 243 status = "disabled";
298 }; 244 };
299 245
300 sor0: sor@54540000 { !! 246 sor@54540000 {
301 compatible = "nvidia,t 247 compatible = "nvidia,tegra210-sor";
302 reg = <0x0 0x54540000 248 reg = <0x0 0x54540000 0x0 0x00040000>;
303 interrupts = <GIC_SPI 249 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
304 clocks = <&tegra_car T 250 clocks = <&tegra_car TEGRA210_CLK_SOR0>,
305 <&tegra_car T <<
306 <&tegra_car T 251 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>,
307 <&tegra_car T 252 <&tegra_car TEGRA210_CLK_PLL_DP>,
308 <&tegra_car T 253 <&tegra_car TEGRA210_CLK_SOR_SAFE>;
309 clock-names = "sor", " !! 254 clock-names = "sor", "parent", "dp", "safe";
310 resets = <&tegra_car 1 255 resets = <&tegra_car 182>;
311 reset-names = "sor"; 256 reset-names = "sor";
312 pinctrl-0 = <&state_dp 257 pinctrl-0 = <&state_dpaux_aux>;
313 pinctrl-1 = <&state_dp 258 pinctrl-1 = <&state_dpaux_i2c>;
314 pinctrl-2 = <&state_dp 259 pinctrl-2 = <&state_dpaux_off>;
315 pinctrl-names = "aux", 260 pinctrl-names = "aux", "i2c", "off";
316 power-domains = <&pd_s 261 power-domains = <&pd_sor>;
317 status = "disabled"; 262 status = "disabled";
318 }; 263 };
319 264
320 sor1: sor@54580000 { !! 265 sor@54580000 {
321 compatible = "nvidia,t 266 compatible = "nvidia,tegra210-sor1";
322 reg = <0x0 0x54580000 267 reg = <0x0 0x54580000 0x0 0x00040000>;
323 interrupts = <GIC_SPI 268 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
324 clocks = <&tegra_car T 269 clocks = <&tegra_car TEGRA210_CLK_SOR1>,
325 <&tegra_car T 270 <&tegra_car TEGRA210_CLK_SOR1_OUT>,
326 <&tegra_car T 271 <&tegra_car TEGRA210_CLK_PLL_D2_OUT0>,
327 <&tegra_car T 272 <&tegra_car TEGRA210_CLK_PLL_DP>,
328 <&tegra_car T 273 <&tegra_car TEGRA210_CLK_SOR_SAFE>;
329 clock-names = "sor", " 274 clock-names = "sor", "out", "parent", "dp", "safe";
330 resets = <&tegra_car 1 275 resets = <&tegra_car 183>;
331 reset-names = "sor"; 276 reset-names = "sor";
332 pinctrl-0 = <&state_dp 277 pinctrl-0 = <&state_dpaux1_aux>;
333 pinctrl-1 = <&state_dp 278 pinctrl-1 = <&state_dpaux1_i2c>;
334 pinctrl-2 = <&state_dp 279 pinctrl-2 = <&state_dpaux1_off>;
335 pinctrl-names = "aux", 280 pinctrl-names = "aux", "i2c", "off";
336 power-domains = <&pd_s 281 power-domains = <&pd_sor>;
337 status = "disabled"; 282 status = "disabled";
338 }; 283 };
339 284
340 dpaux: dpaux@545c0000 { 285 dpaux: dpaux@545c0000 {
341 compatible = "nvidia,t !! 286 compatible = "nvidia,tegra124-dpaux";
342 reg = <0x0 0x545c0000 287 reg = <0x0 0x545c0000 0x0 0x00040000>;
343 interrupts = <GIC_SPI 288 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
344 clocks = <&tegra_car T 289 clocks = <&tegra_car TEGRA210_CLK_DPAUX>,
345 <&tegra_car T 290 <&tegra_car TEGRA210_CLK_PLL_DP>;
346 clock-names = "dpaux", 291 clock-names = "dpaux", "parent";
347 resets = <&tegra_car 1 292 resets = <&tegra_car 181>;
348 reset-names = "dpaux"; 293 reset-names = "dpaux";
349 power-domains = <&pd_s 294 power-domains = <&pd_sor>;
350 status = "disabled"; 295 status = "disabled";
351 296
352 state_dpaux_aux: pinmu 297 state_dpaux_aux: pinmux-aux {
353 groups = "dpau 298 groups = "dpaux-io";
354 function = "au 299 function = "aux";
355 }; 300 };
356 301
357 state_dpaux_i2c: pinmu 302 state_dpaux_i2c: pinmux-i2c {
358 groups = "dpau 303 groups = "dpaux-io";
359 function = "i2 304 function = "i2c";
360 }; 305 };
361 306
362 state_dpaux_off: pinmu 307 state_dpaux_off: pinmux-off {
363 groups = "dpau 308 groups = "dpaux-io";
364 function = "of 309 function = "off";
365 }; 310 };
366 311
367 i2c-bus { 312 i2c-bus {
368 #address-cells 313 #address-cells = <1>;
369 #size-cells = 314 #size-cells = <0>;
370 }; 315 };
371 }; 316 };
372 317
373 isp@54600000 { 318 isp@54600000 {
374 compatible = "nvidia,t 319 compatible = "nvidia,tegra210-isp";
375 reg = <0x0 0x54600000 320 reg = <0x0 0x54600000 0x0 0x00040000>;
376 interrupts = <GIC_SPI 321 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
377 clocks = <&tegra_car T <<
378 resets = <&tegra_car 2 <<
379 reset-names = "isp"; <<
380 status = "disabled"; 322 status = "disabled";
381 }; 323 };
382 324
383 isp@54680000 { 325 isp@54680000 {
384 compatible = "nvidia,t 326 compatible = "nvidia,tegra210-isp";
385 reg = <0x0 0x54680000 327 reg = <0x0 0x54680000 0x0 0x00040000>;
386 interrupts = <GIC_SPI 328 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
387 clocks = <&tegra_car T <<
388 resets = <&tegra_car 3 <<
389 reset-names = "isp"; <<
390 status = "disabled"; 329 status = "disabled";
391 }; 330 };
392 331
393 i2c@546c0000 { 332 i2c@546c0000 {
394 compatible = "nvidia,t 333 compatible = "nvidia,tegra210-i2c-vi";
395 reg = <0x0 0x546c0000 334 reg = <0x0 0x546c0000 0x0 0x00040000>;
396 interrupts = <GIC_SPI 335 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
397 clocks = <&tegra_car T <<
398 <&tegra_car T <<
399 clock-names = "div-clk <<
400 resets = <&tegra_car 2 <<
401 reset-names = "i2c"; <<
402 power-domains = <&pd_v <<
403 status = "disabled"; 336 status = "disabled";
404 <<
405 #address-cells = <1>; <<
406 #size-cells = <0>; <<
407 }; 337 };
408 }; 338 };
409 339
410 gic: interrupt-controller@50041000 { 340 gic: interrupt-controller@50041000 {
411 compatible = "arm,gic-400"; 341 compatible = "arm,gic-400";
412 #interrupt-cells = <3>; 342 #interrupt-cells = <3>;
413 interrupt-controller; 343 interrupt-controller;
414 reg = <0x0 0x50041000 0x0 0x10 344 reg = <0x0 0x50041000 0x0 0x1000>,
415 <0x0 0x50042000 0x0 0x20 345 <0x0 0x50042000 0x0 0x2000>,
416 <0x0 0x50044000 0x0 0x20 346 <0x0 0x50044000 0x0 0x2000>,
417 <0x0 0x50046000 0x0 0x20 347 <0x0 0x50046000 0x0 0x2000>;
418 interrupts = <GIC_PPI 9 348 interrupts = <GIC_PPI 9
419 (GIC_CPU_MASK_SIMPLE(4 349 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
420 interrupt-parent = <&gic>; 350 interrupt-parent = <&gic>;
421 }; 351 };
422 352
423 gpu@57000000 { 353 gpu@57000000 {
424 compatible = "nvidia,gm20b"; 354 compatible = "nvidia,gm20b";
425 reg = <0x0 0x57000000 0x0 0x01 355 reg = <0x0 0x57000000 0x0 0x01000000>,
426 <0x0 0x58000000 0x0 0x01 356 <0x0 0x58000000 0x0 0x01000000>;
427 interrupts = <GIC_SPI 157 IRQ_ 357 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
428 <GIC_SPI 158 IRQ_ 358 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
429 interrupt-names = "stall", "no 359 interrupt-names = "stall", "nonstall";
430 clocks = <&tegra_car TEGRA210_ 360 clocks = <&tegra_car TEGRA210_CLK_GPU>,
431 <&tegra_car TEGRA210_ 361 <&tegra_car TEGRA210_CLK_PLL_P_OUT5>,
432 <&tegra_car TEGRA210_ 362 <&tegra_car TEGRA210_CLK_PLL_G_REF>;
433 clock-names = "gpu", "pwr", "r 363 clock-names = "gpu", "pwr", "ref";
434 resets = <&tegra_car 184>; 364 resets = <&tegra_car 184>;
435 reset-names = "gpu"; 365 reset-names = "gpu";
436 366
437 iommus = <&mc TEGRA_SWGROUP_GP 367 iommus = <&mc TEGRA_SWGROUP_GPU>;
438 368
439 status = "disabled"; 369 status = "disabled";
440 }; 370 };
441 371
442 lic: interrupt-controller@60004000 { 372 lic: interrupt-controller@60004000 {
443 compatible = "nvidia,tegra210- 373 compatible = "nvidia,tegra210-ictlr";
444 reg = <0x0 0x60004000 0x0 0x40 374 reg = <0x0 0x60004000 0x0 0x40>, /* primary controller */
445 <0x0 0x60004100 0x0 0x40 375 <0x0 0x60004100 0x0 0x40>, /* secondary controller */
446 <0x0 0x60004200 0x0 0x40 376 <0x0 0x60004200 0x0 0x40>, /* tertiary controller */
447 <0x0 0x60004300 0x0 0x40 377 <0x0 0x60004300 0x0 0x40>, /* quaternary controller */
448 <0x0 0x60004400 0x0 0x40 378 <0x0 0x60004400 0x0 0x40>, /* quinary controller */
449 <0x0 0x60004500 0x0 0x40 379 <0x0 0x60004500 0x0 0x40>; /* senary controller */
450 interrupt-controller; 380 interrupt-controller;
451 #interrupt-cells = <3>; 381 #interrupt-cells = <3>;
452 interrupt-parent = <&gic>; 382 interrupt-parent = <&gic>;
453 }; 383 };
454 384
455 timer@60005000 { 385 timer@60005000 {
456 compatible = "nvidia,tegra210- !! 386 compatible = "nvidia,tegra210-timer", "nvidia,tegra20-timer";
457 reg = <0x0 0x60005000 0x0 0x40 387 reg = <0x0 0x60005000 0x0 0x400>;
458 interrupts = <GIC_SPI 156 IRQ_ !! 388 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
459 <GIC_SPI 0 IRQ_TY <<
460 <GIC_SPI 1 IRQ_TY 389 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
461 <GIC_SPI 41 IRQ_T 390 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
462 <GIC_SPI 42 IRQ_T 391 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
463 <GIC_SPI 121 IRQ_ 392 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
464 <GIC_SPI 152 IRQ_ !! 393 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
465 <GIC_SPI 153 IRQ_ <<
466 <GIC_SPI 154 IRQ_ <<
467 <GIC_SPI 155 IRQ_ <<
468 <GIC_SPI 176 IRQ_ <<
469 <GIC_SPI 177 IRQ_ <<
470 <GIC_SPI 178 IRQ_ <<
471 <GIC_SPI 179 IRQ_ <<
472 clocks = <&tegra_car TEGRA210_ 394 clocks = <&tegra_car TEGRA210_CLK_TIMER>;
473 clock-names = "timer"; 395 clock-names = "timer";
474 }; 396 };
475 397
476 tegra_car: clock@60006000 { 398 tegra_car: clock@60006000 {
477 compatible = "nvidia,tegra210- 399 compatible = "nvidia,tegra210-car";
478 reg = <0x0 0x60006000 0x0 0x10 400 reg = <0x0 0x60006000 0x0 0x1000>;
479 #clock-cells = <1>; 401 #clock-cells = <1>;
480 #reset-cells = <1>; 402 #reset-cells = <1>;
481 }; 403 };
482 404
483 flow-controller@60007000 { 405 flow-controller@60007000 {
484 compatible = "nvidia,tegra210- 406 compatible = "nvidia,tegra210-flowctrl";
485 reg = <0x0 0x60007000 0x0 0x10 407 reg = <0x0 0x60007000 0x0 0x1000>;
486 }; 408 };
487 409
488 gpio: gpio@6000d000 { 410 gpio: gpio@6000d000 {
489 compatible = "nvidia,tegra210- 411 compatible = "nvidia,tegra210-gpio", "nvidia,tegra30-gpio";
490 reg = <0x0 0x6000d000 0x0 0x10 412 reg = <0x0 0x6000d000 0x0 0x1000>;
491 interrupts = <GIC_SPI 32 IRQ_T 413 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
492 <GIC_SPI 33 IRQ_T 414 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
493 <GIC_SPI 34 IRQ_T 415 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
494 <GIC_SPI 35 IRQ_T 416 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
495 <GIC_SPI 55 IRQ_T 417 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
496 <GIC_SPI 87 IRQ_T 418 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
497 <GIC_SPI 89 IRQ_T 419 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
498 <GIC_SPI 125 IRQ_ 420 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
499 #gpio-cells = <2>; 421 #gpio-cells = <2>;
500 gpio-controller; 422 gpio-controller;
501 #interrupt-cells = <2>; 423 #interrupt-cells = <2>;
502 interrupt-controller; 424 interrupt-controller;
503 }; 425 };
504 426
505 apbdma: dma@60020000 { 427 apbdma: dma@60020000 {
506 compatible = "nvidia,tegra210- 428 compatible = "nvidia,tegra210-apbdma", "nvidia,tegra148-apbdma";
507 reg = <0x0 0x60020000 0x0 0x14 429 reg = <0x0 0x60020000 0x0 0x1400>;
508 interrupts = <GIC_SPI 104 IRQ_ 430 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
509 <GIC_SPI 105 IRQ_ 431 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
510 <GIC_SPI 106 IRQ_ 432 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
511 <GIC_SPI 107 IRQ_ 433 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
512 <GIC_SPI 108 IRQ_ 434 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
513 <GIC_SPI 109 IRQ_ 435 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
514 <GIC_SPI 110 IRQ_ 436 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
515 <GIC_SPI 111 IRQ_ 437 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
516 <GIC_SPI 112 IRQ_ 438 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
517 <GIC_SPI 113 IRQ_ 439 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
518 <GIC_SPI 114 IRQ_ 440 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
519 <GIC_SPI 115 IRQ_ 441 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
520 <GIC_SPI 116 IRQ_ 442 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
521 <GIC_SPI 117 IRQ_ 443 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
522 <GIC_SPI 118 IRQ_ 444 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
523 <GIC_SPI 119 IRQ_ 445 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
524 <GIC_SPI 128 IRQ_ 446 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
525 <GIC_SPI 129 IRQ_ 447 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
526 <GIC_SPI 130 IRQ_ 448 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
527 <GIC_SPI 131 IRQ_ 449 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
528 <GIC_SPI 132 IRQ_ 450 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
529 <GIC_SPI 133 IRQ_ 451 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
530 <GIC_SPI 134 IRQ_ 452 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
531 <GIC_SPI 135 IRQ_ 453 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
532 <GIC_SPI 136 IRQ_ 454 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
533 <GIC_SPI 137 IRQ_ 455 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
534 <GIC_SPI 138 IRQ_ 456 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
535 <GIC_SPI 139 IRQ_ 457 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
536 <GIC_SPI 140 IRQ_ 458 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
537 <GIC_SPI 141 IRQ_ 459 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
538 <GIC_SPI 142 IRQ_ 460 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
539 <GIC_SPI 143 IRQ_ 461 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
540 clocks = <&tegra_car TEGRA210_ 462 clocks = <&tegra_car TEGRA210_CLK_APBDMA>;
541 clock-names = "dma"; 463 clock-names = "dma";
542 resets = <&tegra_car 34>; 464 resets = <&tegra_car 34>;
543 reset-names = "dma"; 465 reset-names = "dma";
544 #dma-cells = <1>; 466 #dma-cells = <1>;
545 }; 467 };
546 468
547 apbmisc@70000800 { 469 apbmisc@70000800 {
548 compatible = "nvidia,tegra210- 470 compatible = "nvidia,tegra210-apbmisc", "nvidia,tegra20-apbmisc";
549 reg = <0x0 0x70000800 0x0 0x64 471 reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */
550 <0x0 0x70000008 0x0 0x04 !! 472 <0x0 0x7000e864 0x0 0x04>; /* Strapping options */
551 }; 473 };
552 474
553 pinmux: pinmux@700008d4 { 475 pinmux: pinmux@700008d4 {
554 compatible = "nvidia,tegra210- 476 compatible = "nvidia,tegra210-pinmux";
555 reg = <0x0 0x700008d4 0x0 0x29 477 reg = <0x0 0x700008d4 0x0 0x29c>, /* Pad control registers */
556 <0x0 0x70003000 0x0 0x29 478 <0x0 0x70003000 0x0 0x294>; /* Mux registers */
557 <<
558 sdmmc1_1v8_drv: pinmux-sdmmc1- <<
559 sdmmc1 { <<
560 nvidia,pins = <<
561 nvidia,pull-do <<
562 nvidia,pull-up <<
563 }; <<
564 }; <<
565 <<
566 sdmmc1_3v3_drv: pinmux-sdmmc1- <<
567 sdmmc1 { <<
568 nvidia,pins = <<
569 nvidia,pull-do <<
570 nvidia,pull-up <<
571 }; <<
572 }; <<
573 <<
574 sdmmc2_1v8_drv: pinmux-sdmmc2- <<
575 sdmmc2 { <<
576 nvidia,pins = <<
577 nvidia,pull-do <<
578 nvidia,pull-up <<
579 }; <<
580 }; <<
581 <<
582 sdmmc3_1v8_drv: pinmux-sdmmc3- <<
583 sdmmc3 { <<
584 nvidia,pins = <<
585 nvidia,pull-do <<
586 nvidia,pull-up <<
587 }; <<
588 }; <<
589 <<
590 sdmmc3_3v3_drv: pinmux-sdmmc3- <<
591 sdmmc3 { <<
592 nvidia,pins = <<
593 nvidia,pull-do <<
594 nvidia,pull-up <<
595 }; <<
596 }; <<
597 <<
598 sdmmc4_1v8_drv: pinmux-sdmmc4- <<
599 sdmmc4 { <<
600 nvidia,pins = <<
601 nvidia,pull-do <<
602 nvidia,pull-up <<
603 }; <<
604 }; <<
605 }; 479 };
606 480
607 /* 481 /*
608 * There are two serial driver i.e. 82 482 * There are two serial driver i.e. 8250 based simple serial
609 * driver and APB DMA based serial dri 483 * driver and APB DMA based serial driver for higher baudrate
610 * and performance. To enable the 8250 484 * and performance. To enable the 8250 based driver, the compatible
611 * is "nvidia,tegra124-uart", "nvidia, 485 * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable
612 * the APB DMA based serial driver, th 486 * the APB DMA based serial driver, the compatible is
613 * "nvidia,tegra124-hsuart", "nvidia,t 487 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart".
614 */ 488 */
615 uarta: serial@70006000 { 489 uarta: serial@70006000 {
616 compatible = "nvidia,tegra210- 490 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
617 reg = <0x0 0x70006000 0x0 0x40 491 reg = <0x0 0x70006000 0x0 0x40>;
618 reg-shift = <2>; 492 reg-shift = <2>;
619 interrupts = <GIC_SPI 36 IRQ_T 493 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
620 clocks = <&tegra_car TEGRA210_ 494 clocks = <&tegra_car TEGRA210_CLK_UARTA>;
>> 495 clock-names = "serial";
621 resets = <&tegra_car 6>; 496 resets = <&tegra_car 6>;
>> 497 reset-names = "serial";
622 dmas = <&apbdma 8>, <&apbdma 8 498 dmas = <&apbdma 8>, <&apbdma 8>;
623 dma-names = "rx", "tx"; 499 dma-names = "rx", "tx";
624 status = "disabled"; 500 status = "disabled";
625 }; 501 };
626 502
627 uartb: serial@70006040 { 503 uartb: serial@70006040 {
628 compatible = "nvidia,tegra210- 504 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
629 reg = <0x0 0x70006040 0x0 0x40 505 reg = <0x0 0x70006040 0x0 0x40>;
630 reg-shift = <2>; 506 reg-shift = <2>;
631 interrupts = <GIC_SPI 37 IRQ_T 507 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
632 clocks = <&tegra_car TEGRA210_ 508 clocks = <&tegra_car TEGRA210_CLK_UARTB>;
>> 509 clock-names = "serial";
633 resets = <&tegra_car 7>; 510 resets = <&tegra_car 7>;
>> 511 reset-names = "serial";
634 dmas = <&apbdma 9>, <&apbdma 9 512 dmas = <&apbdma 9>, <&apbdma 9>;
635 dma-names = "rx", "tx"; 513 dma-names = "rx", "tx";
636 status = "disabled"; 514 status = "disabled";
637 }; 515 };
638 516
639 uartc: serial@70006200 { 517 uartc: serial@70006200 {
640 compatible = "nvidia,tegra210- 518 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
641 reg = <0x0 0x70006200 0x0 0x40 519 reg = <0x0 0x70006200 0x0 0x40>;
642 reg-shift = <2>; 520 reg-shift = <2>;
643 interrupts = <GIC_SPI 46 IRQ_T 521 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
644 clocks = <&tegra_car TEGRA210_ 522 clocks = <&tegra_car TEGRA210_CLK_UARTC>;
>> 523 clock-names = "serial";
645 resets = <&tegra_car 55>; 524 resets = <&tegra_car 55>;
>> 525 reset-names = "serial";
646 dmas = <&apbdma 10>, <&apbdma 526 dmas = <&apbdma 10>, <&apbdma 10>;
647 dma-names = "rx", "tx"; 527 dma-names = "rx", "tx";
648 status = "disabled"; 528 status = "disabled";
649 }; 529 };
650 530
651 uartd: serial@70006300 { 531 uartd: serial@70006300 {
652 compatible = "nvidia,tegra210- 532 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
653 reg = <0x0 0x70006300 0x0 0x40 533 reg = <0x0 0x70006300 0x0 0x40>;
654 reg-shift = <2>; 534 reg-shift = <2>;
655 interrupts = <GIC_SPI 90 IRQ_T 535 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
656 clocks = <&tegra_car TEGRA210_ 536 clocks = <&tegra_car TEGRA210_CLK_UARTD>;
>> 537 clock-names = "serial";
657 resets = <&tegra_car 65>; 538 resets = <&tegra_car 65>;
>> 539 reset-names = "serial";
658 dmas = <&apbdma 19>, <&apbdma 540 dmas = <&apbdma 19>, <&apbdma 19>;
659 dma-names = "rx", "tx"; 541 dma-names = "rx", "tx";
660 status = "disabled"; 542 status = "disabled";
661 }; 543 };
662 544
663 pwm: pwm@7000a000 { 545 pwm: pwm@7000a000 {
664 compatible = "nvidia,tegra210- 546 compatible = "nvidia,tegra210-pwm", "nvidia,tegra20-pwm";
665 reg = <0x0 0x7000a000 0x0 0x10 547 reg = <0x0 0x7000a000 0x0 0x100>;
666 #pwm-cells = <2>; 548 #pwm-cells = <2>;
667 clocks = <&tegra_car TEGRA210_ 549 clocks = <&tegra_car TEGRA210_CLK_PWM>;
>> 550 clock-names = "pwm";
668 resets = <&tegra_car 17>; 551 resets = <&tegra_car 17>;
669 reset-names = "pwm"; 552 reset-names = "pwm";
670 status = "disabled"; 553 status = "disabled";
671 }; 554 };
672 555
673 i2c@7000c000 { 556 i2c@7000c000 {
674 compatible = "nvidia,tegra210- !! 557 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
675 reg = <0x0 0x7000c000 0x0 0x10 558 reg = <0x0 0x7000c000 0x0 0x100>;
676 interrupts = <GIC_SPI 38 IRQ_T 559 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
677 #address-cells = <1>; 560 #address-cells = <1>;
678 #size-cells = <0>; 561 #size-cells = <0>;
679 clocks = <&tegra_car TEGRA210_ 562 clocks = <&tegra_car TEGRA210_CLK_I2C1>;
680 clock-names = "div-clk"; 563 clock-names = "div-clk";
681 resets = <&tegra_car 12>; 564 resets = <&tegra_car 12>;
682 reset-names = "i2c"; 565 reset-names = "i2c";
683 dmas = <&apbdma 21>, <&apbdma 566 dmas = <&apbdma 21>, <&apbdma 21>;
684 dma-names = "rx", "tx"; 567 dma-names = "rx", "tx";
685 status = "disabled"; 568 status = "disabled";
686 }; 569 };
687 570
688 i2c@7000c400 { 571 i2c@7000c400 {
689 compatible = "nvidia,tegra210- !! 572 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
690 reg = <0x0 0x7000c400 0x0 0x10 573 reg = <0x0 0x7000c400 0x0 0x100>;
691 interrupts = <GIC_SPI 84 IRQ_T 574 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
692 #address-cells = <1>; 575 #address-cells = <1>;
693 #size-cells = <0>; 576 #size-cells = <0>;
694 clocks = <&tegra_car TEGRA210_ 577 clocks = <&tegra_car TEGRA210_CLK_I2C2>;
695 clock-names = "div-clk"; 578 clock-names = "div-clk";
696 resets = <&tegra_car 54>; 579 resets = <&tegra_car 54>;
697 reset-names = "i2c"; 580 reset-names = "i2c";
698 dmas = <&apbdma 22>, <&apbdma 581 dmas = <&apbdma 22>, <&apbdma 22>;
699 dma-names = "rx", "tx"; 582 dma-names = "rx", "tx";
700 status = "disabled"; 583 status = "disabled";
701 }; 584 };
702 585
703 i2c@7000c500 { 586 i2c@7000c500 {
704 compatible = "nvidia,tegra210- !! 587 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
705 reg = <0x0 0x7000c500 0x0 0x10 588 reg = <0x0 0x7000c500 0x0 0x100>;
706 interrupts = <GIC_SPI 92 IRQ_T 589 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
707 #address-cells = <1>; 590 #address-cells = <1>;
708 #size-cells = <0>; 591 #size-cells = <0>;
709 clocks = <&tegra_car TEGRA210_ 592 clocks = <&tegra_car TEGRA210_CLK_I2C3>;
710 clock-names = "div-clk"; 593 clock-names = "div-clk";
711 resets = <&tegra_car 67>; 594 resets = <&tegra_car 67>;
712 reset-names = "i2c"; 595 reset-names = "i2c";
713 dmas = <&apbdma 23>, <&apbdma 596 dmas = <&apbdma 23>, <&apbdma 23>;
714 dma-names = "rx", "tx"; 597 dma-names = "rx", "tx";
715 status = "disabled"; 598 status = "disabled";
716 }; 599 };
717 600
718 i2c@7000c700 { 601 i2c@7000c700 {
719 compatible = "nvidia,tegra210- !! 602 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
720 reg = <0x0 0x7000c700 0x0 0x10 603 reg = <0x0 0x7000c700 0x0 0x100>;
721 interrupts = <GIC_SPI 120 IRQ_ 604 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
722 #address-cells = <1>; 605 #address-cells = <1>;
723 #size-cells = <0>; 606 #size-cells = <0>;
724 clocks = <&tegra_car TEGRA210_ 607 clocks = <&tegra_car TEGRA210_CLK_I2C4>;
725 clock-names = "div-clk"; 608 clock-names = "div-clk";
726 resets = <&tegra_car 103>; 609 resets = <&tegra_car 103>;
727 reset-names = "i2c"; 610 reset-names = "i2c";
728 dmas = <&apbdma 26>, <&apbdma 611 dmas = <&apbdma 26>, <&apbdma 26>;
729 dma-names = "rx", "tx"; 612 dma-names = "rx", "tx";
730 pinctrl-0 = <&state_dpaux1_i2c 613 pinctrl-0 = <&state_dpaux1_i2c>;
731 pinctrl-1 = <&state_dpaux1_off 614 pinctrl-1 = <&state_dpaux1_off>;
732 pinctrl-names = "default", "id 615 pinctrl-names = "default", "idle";
733 status = "disabled"; 616 status = "disabled";
734 }; 617 };
735 618
736 i2c@7000d000 { 619 i2c@7000d000 {
737 compatible = "nvidia,tegra210- !! 620 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
738 reg = <0x0 0x7000d000 0x0 0x10 621 reg = <0x0 0x7000d000 0x0 0x100>;
739 interrupts = <GIC_SPI 53 IRQ_T 622 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
740 #address-cells = <1>; 623 #address-cells = <1>;
741 #size-cells = <0>; 624 #size-cells = <0>;
742 clocks = <&tegra_car TEGRA210_ 625 clocks = <&tegra_car TEGRA210_CLK_I2C5>;
743 clock-names = "div-clk"; 626 clock-names = "div-clk";
744 resets = <&tegra_car 47>; 627 resets = <&tegra_car 47>;
745 reset-names = "i2c"; 628 reset-names = "i2c";
746 dmas = <&apbdma 24>, <&apbdma 629 dmas = <&apbdma 24>, <&apbdma 24>;
747 dma-names = "rx", "tx"; 630 dma-names = "rx", "tx";
748 status = "disabled"; 631 status = "disabled";
749 }; 632 };
750 633
751 i2c@7000d100 { 634 i2c@7000d100 {
752 compatible = "nvidia,tegra210- !! 635 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
753 reg = <0x0 0x7000d100 0x0 0x10 636 reg = <0x0 0x7000d100 0x0 0x100>;
754 interrupts = <GIC_SPI 63 IRQ_T 637 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
755 #address-cells = <1>; 638 #address-cells = <1>;
756 #size-cells = <0>; 639 #size-cells = <0>;
757 clocks = <&tegra_car TEGRA210_ 640 clocks = <&tegra_car TEGRA210_CLK_I2C6>;
758 clock-names = "div-clk"; 641 clock-names = "div-clk";
759 resets = <&tegra_car 166>; 642 resets = <&tegra_car 166>;
760 reset-names = "i2c"; 643 reset-names = "i2c";
761 dmas = <&apbdma 30>, <&apbdma 644 dmas = <&apbdma 30>, <&apbdma 30>;
762 dma-names = "rx", "tx"; 645 dma-names = "rx", "tx";
763 pinctrl-0 = <&state_dpaux_i2c> 646 pinctrl-0 = <&state_dpaux_i2c>;
764 pinctrl-1 = <&state_dpaux_off> 647 pinctrl-1 = <&state_dpaux_off>;
765 pinctrl-names = "default", "id 648 pinctrl-names = "default", "idle";
766 status = "disabled"; 649 status = "disabled";
767 }; 650 };
768 651
769 spi@7000d400 { 652 spi@7000d400 {
770 compatible = "nvidia,tegra210- 653 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
771 reg = <0x0 0x7000d400 0x0 0x20 654 reg = <0x0 0x7000d400 0x0 0x200>;
772 interrupts = <GIC_SPI 59 IRQ_T 655 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
773 #address-cells = <1>; 656 #address-cells = <1>;
774 #size-cells = <0>; 657 #size-cells = <0>;
775 clocks = <&tegra_car TEGRA210_ 658 clocks = <&tegra_car TEGRA210_CLK_SBC1>;
776 clock-names = "spi"; 659 clock-names = "spi";
777 resets = <&tegra_car 41>; 660 resets = <&tegra_car 41>;
778 reset-names = "spi"; 661 reset-names = "spi";
779 dmas = <&apbdma 15>, <&apbdma 662 dmas = <&apbdma 15>, <&apbdma 15>;
780 dma-names = "rx", "tx"; 663 dma-names = "rx", "tx";
781 status = "disabled"; 664 status = "disabled";
782 }; 665 };
783 666
784 spi@7000d600 { 667 spi@7000d600 {
785 compatible = "nvidia,tegra210- 668 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
786 reg = <0x0 0x7000d600 0x0 0x20 669 reg = <0x0 0x7000d600 0x0 0x200>;
787 interrupts = <GIC_SPI 82 IRQ_T 670 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
788 #address-cells = <1>; 671 #address-cells = <1>;
789 #size-cells = <0>; 672 #size-cells = <0>;
790 clocks = <&tegra_car TEGRA210_ 673 clocks = <&tegra_car TEGRA210_CLK_SBC2>;
791 clock-names = "spi"; 674 clock-names = "spi";
792 resets = <&tegra_car 44>; 675 resets = <&tegra_car 44>;
793 reset-names = "spi"; 676 reset-names = "spi";
794 dmas = <&apbdma 16>, <&apbdma 677 dmas = <&apbdma 16>, <&apbdma 16>;
795 dma-names = "rx", "tx"; 678 dma-names = "rx", "tx";
796 status = "disabled"; 679 status = "disabled";
797 }; 680 };
798 681
799 spi@7000d800 { 682 spi@7000d800 {
800 compatible = "nvidia,tegra210- 683 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
801 reg = <0x0 0x7000d800 0x0 0x20 684 reg = <0x0 0x7000d800 0x0 0x200>;
802 interrupts = <GIC_SPI 83 IRQ_T 685 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
803 #address-cells = <1>; 686 #address-cells = <1>;
804 #size-cells = <0>; 687 #size-cells = <0>;
805 clocks = <&tegra_car TEGRA210_ 688 clocks = <&tegra_car TEGRA210_CLK_SBC3>;
806 clock-names = "spi"; 689 clock-names = "spi";
807 resets = <&tegra_car 46>; 690 resets = <&tegra_car 46>;
808 reset-names = "spi"; 691 reset-names = "spi";
809 dmas = <&apbdma 17>, <&apbdma 692 dmas = <&apbdma 17>, <&apbdma 17>;
810 dma-names = "rx", "tx"; 693 dma-names = "rx", "tx";
811 status = "disabled"; 694 status = "disabled";
812 }; 695 };
813 696
814 spi@7000da00 { 697 spi@7000da00 {
815 compatible = "nvidia,tegra210- 698 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
816 reg = <0x0 0x7000da00 0x0 0x20 699 reg = <0x0 0x7000da00 0x0 0x200>;
817 interrupts = <GIC_SPI 93 IRQ_T 700 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
818 #address-cells = <1>; 701 #address-cells = <1>;
819 #size-cells = <0>; 702 #size-cells = <0>;
820 clocks = <&tegra_car TEGRA210_ 703 clocks = <&tegra_car TEGRA210_CLK_SBC4>;
821 clock-names = "spi"; 704 clock-names = "spi";
822 resets = <&tegra_car 68>; 705 resets = <&tegra_car 68>;
823 reset-names = "spi"; 706 reset-names = "spi";
824 dmas = <&apbdma 18>, <&apbdma 707 dmas = <&apbdma 18>, <&apbdma 18>;
825 dma-names = "rx", "tx"; 708 dma-names = "rx", "tx";
826 status = "disabled"; 709 status = "disabled";
827 }; 710 };
828 711
829 rtc@7000e000 { 712 rtc@7000e000 {
830 compatible = "nvidia,tegra210- 713 compatible = "nvidia,tegra210-rtc", "nvidia,tegra20-rtc";
831 reg = <0x0 0x7000e000 0x0 0x10 714 reg = <0x0 0x7000e000 0x0 0x100>;
832 interrupts = <16 IRQ_TYPE_LEVE !! 715 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
833 interrupt-parent = <&tegra_pmc <<
834 clocks = <&tegra_car TEGRA210_ 716 clocks = <&tegra_car TEGRA210_CLK_RTC>;
835 clock-names = "rtc"; 717 clock-names = "rtc";
836 }; 718 };
837 719
838 tegra_pmc: pmc@7000e400 { !! 720 pmc: pmc@7000e400 {
839 compatible = "nvidia,tegra210- 721 compatible = "nvidia,tegra210-pmc";
840 reg = <0x0 0x7000e400 0x0 0x40 722 reg = <0x0 0x7000e400 0x0 0x400>;
841 clocks = <&tegra_car TEGRA210_ 723 clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>;
842 clock-names = "pclk", "clk32k_ 724 clock-names = "pclk", "clk32k_in";
843 #clock-cells = <1>; <<
844 #interrupt-cells = <2>; <<
845 interrupt-controller; <<
846 <<
847 pinmux { <<
848 pex_dpd_disable: pex-d <<
849 pins = "pex-bi <<
850 low-power-disa <<
851 }; <<
852 <<
853 pex_dpd_enable: pex-dp <<
854 pins = "pex-bi <<
855 low-power-enab <<
856 }; <<
857 <<
858 sdmmc1_1v8: sdmmc1-1v8 <<
859 pins = "sdmmc1 <<
860 power-source = <<
861 }; <<
862 <<
863 sdmmc1_3v3: sdmmc1-3v3 <<
864 pins = "sdmmc1 <<
865 power-source = <<
866 }; <<
867 <<
868 sdmmc3_1v8: sdmmc3-1v8 <<
869 pins = "sdmmc3 <<
870 power-source = <<
871 }; <<
872 <<
873 sdmmc3_3v3: sdmmc3-3v3 <<
874 pins = "sdmmc3 <<
875 power-source = <<
876 }; <<
877 }; <<
878 725
879 powergates { 726 powergates {
880 pd_audio: aud { 727 pd_audio: aud {
881 clocks = <&teg 728 clocks = <&tegra_car TEGRA210_CLK_APE>,
882 <&teg 729 <&tegra_car TEGRA210_CLK_APB2APE>;
883 resets = <&teg 730 resets = <&tegra_car 198>;
884 #power-domain- 731 #power-domain-cells = <0>;
885 }; 732 };
886 733
887 pd_sor: sor { 734 pd_sor: sor {
888 clocks = <&teg 735 clocks = <&tegra_car TEGRA210_CLK_SOR0>,
889 <&teg 736 <&tegra_car TEGRA210_CLK_SOR1>,
890 <&teg !! 737 <&tegra_car TEGRA210_CLK_CSI>,
891 <&teg <<
892 <&teg <<
893 <&teg 738 <&tegra_car TEGRA210_CLK_DSIA>,
894 <&teg 739 <&tegra_car TEGRA210_CLK_DSIB>,
895 <&teg 740 <&tegra_car TEGRA210_CLK_DPAUX>,
896 <&teg 741 <&tegra_car TEGRA210_CLK_DPAUX1>,
897 <&teg 742 <&tegra_car TEGRA210_CLK_MIPI_CAL>;
898 resets = <&teg 743 resets = <&tegra_car TEGRA210_CLK_SOR0>,
899 <&teg 744 <&tegra_car TEGRA210_CLK_SOR1>,
>> 745 <&tegra_car TEGRA210_CLK_CSI>,
900 <&teg 746 <&tegra_car TEGRA210_CLK_DSIA>,
901 <&teg 747 <&tegra_car TEGRA210_CLK_DSIB>,
902 <&teg 748 <&tegra_car TEGRA210_CLK_DPAUX>,
903 <&teg 749 <&tegra_car TEGRA210_CLK_DPAUX1>,
904 <&teg 750 <&tegra_car TEGRA210_CLK_MIPI_CAL>;
905 #power-domain- 751 #power-domain-cells = <0>;
906 }; 752 };
907 753
908 pd_venc: venc { <<
909 clocks = <&teg <<
910 <&teg <<
911 resets = <&mc <<
912 <&teg <<
913 <&teg <<
914 #power-domain- <<
915 }; <<
916 <<
917 pd_vic: vic { <<
918 clocks = <&teg <<
919 resets = <&teg <<
920 #power-domain- <<
921 }; <<
922 <<
923 pd_xusbss: xusba { 754 pd_xusbss: xusba {
924 clocks = <&teg 755 clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>;
925 resets = <&teg 756 resets = <&tegra_car TEGRA210_CLK_XUSB_SS>;
926 #power-domain- 757 #power-domain-cells = <0>;
927 }; 758 };
928 759
929 pd_xusbdev: xusbb { 760 pd_xusbdev: xusbb {
930 clocks = <&teg 761 clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>;
931 resets = <&teg 762 resets = <&tegra_car 95>;
932 #power-domain- 763 #power-domain-cells = <0>;
933 }; 764 };
934 765
935 pd_xusbhost: xusbc { 766 pd_xusbhost: xusbc {
936 clocks = <&teg 767 clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>;
937 resets = <&teg 768 resets = <&tegra_car TEGRA210_CLK_XUSB_HOST>;
938 #power-domain- 769 #power-domain-cells = <0>;
939 }; 770 };
>> 771
>> 772 pd_vic: vic {
>> 773 clocks = <&tegra_car TEGRA210_CLK_VIC03>;
>> 774 clock-names = "vic";
>> 775 resets = <&tegra_car 178>;
>> 776 reset-names = "vic";
>> 777 #power-domain-cells = <0>;
>> 778 };
>> 779 };
>> 780
>> 781 sdmmc1_3v3: sdmmc1-3v3 {
>> 782 pins = "sdmmc1";
>> 783 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
>> 784 };
>> 785
>> 786 sdmmc1_1v8: sdmmc1-1v8 {
>> 787 pins = "sdmmc1";
>> 788 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
>> 789 };
>> 790
>> 791 sdmmc3_3v3: sdmmc3-3v3 {
>> 792 pins = "sdmmc3";
>> 793 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
>> 794 };
>> 795
>> 796 sdmmc3_1v8: sdmmc3-1v8 {
>> 797 pins = "sdmmc3";
>> 798 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
940 }; 799 };
941 }; 800 };
942 801
943 fuse@7000f800 { 802 fuse@7000f800 {
944 compatible = "nvidia,tegra210- 803 compatible = "nvidia,tegra210-efuse";
945 reg = <0x0 0x7000f800 0x0 0x40 804 reg = <0x0 0x7000f800 0x0 0x400>;
946 clocks = <&tegra_car TEGRA210_ 805 clocks = <&tegra_car TEGRA210_CLK_FUSE>;
947 clock-names = "fuse"; 806 clock-names = "fuse";
948 resets = <&tegra_car 39>; 807 resets = <&tegra_car 39>;
949 reset-names = "fuse"; 808 reset-names = "fuse";
950 }; 809 };
951 810
952 mc: memory-controller@70019000 { 811 mc: memory-controller@70019000 {
953 compatible = "nvidia,tegra210- 812 compatible = "nvidia,tegra210-mc";
954 reg = <0x0 0x70019000 0x0 0x10 813 reg = <0x0 0x70019000 0x0 0x1000>;
955 clocks = <&tegra_car TEGRA210_ 814 clocks = <&tegra_car TEGRA210_CLK_MC>;
956 clock-names = "mc"; 815 clock-names = "mc";
957 816
958 interrupts = <GIC_SPI 77 IRQ_T 817 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
959 818
960 #iommu-cells = <1>; 819 #iommu-cells = <1>;
961 #reset-cells = <1>; <<
962 }; <<
963 <<
964 emc: external-memory-controller@7001b0 <<
965 compatible = "nvidia,tegra210- <<
966 reg = <0x0 0x7001b000 0x0 0x10 <<
967 <0x0 0x7001e000 0x0 0x10 <<
968 <0x0 0x7001f000 0x0 0x10 <<
969 clocks = <&tegra_car TEGRA210_ <<
970 clock-names = "emc"; <<
971 interrupts = <GIC_SPI 78 IRQ_T <<
972 nvidia,memory-controller = <&m <<
973 #cooling-cells = <2>; <<
974 }; 820 };
975 821
976 sata@70020000 { 822 sata@70020000 {
977 compatible = "nvidia,tegra210- 823 compatible = "nvidia,tegra210-ahci";
978 reg = <0x0 0x70027000 0x0 0x20 824 reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */
979 <0x0 0x70020000 0x0 0x70 825 <0x0 0x70020000 0x0 0x7000>, /* SATA */
980 <0x0 0x70001100 0x0 0x10 826 <0x0 0x70001100 0x0 0x1000>; /* SATA AUX */
981 interrupts = <GIC_SPI 23 IRQ_T 827 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
982 clocks = <&tegra_car TEGRA210_ 828 clocks = <&tegra_car TEGRA210_CLK_SATA>,
983 <&tegra_car TEGRA210_ 829 <&tegra_car TEGRA210_CLK_SATA_OOB>;
984 clock-names = "sata", "sata-oo 830 clock-names = "sata", "sata-oob";
985 resets = <&tegra_car 124>, 831 resets = <&tegra_car 124>,
986 <&tegra_car 129>, !! 832 <&tegra_car 123>,
987 <&tegra_car 123>; !! 833 <&tegra_car 129>;
988 reset-names = "sata", "sata-co !! 834 reset-names = "sata", "sata-oob", "sata-cold";
989 status = "disabled"; 835 status = "disabled";
990 }; 836 };
991 837
992 hda@70030000 { 838 hda@70030000 {
993 compatible = "nvidia,tegra210- 839 compatible = "nvidia,tegra210-hda", "nvidia,tegra30-hda";
994 reg = <0x0 0x70030000 0x0 0x10 840 reg = <0x0 0x70030000 0x0 0x10000>;
995 interrupts = <GIC_SPI 81 IRQ_T 841 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
996 clocks = <&tegra_car TEGRA210_ 842 clocks = <&tegra_car TEGRA210_CLK_HDA>,
997 <&tegra_car TEGRA210_ 843 <&tegra_car TEGRA210_CLK_HDA2HDMI>,
998 <&tegra_car TEGRA210_ 844 <&tegra_car TEGRA210_CLK_HDA2CODEC_2X>;
999 clock-names = "hda", "hda2hdmi 845 clock-names = "hda", "hda2hdmi", "hda2codec_2x";
1000 resets = <&tegra_car 125>, /* 846 resets = <&tegra_car 125>, /* hda */
1001 <&tegra_car 128>, /* 847 <&tegra_car 128>, /* hda2hdmi */
1002 <&tegra_car 111>; /* 848 <&tegra_car 111>; /* hda2codec_2x */
1003 reset-names = "hda", "hda2hdm 849 reset-names = "hda", "hda2hdmi", "hda2codec_2x";
1004 power-domains = <&pd_sor>; <<
1005 status = "disabled"; 850 status = "disabled";
1006 }; 851 };
1007 852
1008 usb@70090000 { 853 usb@70090000 {
1009 compatible = "nvidia,tegra210 854 compatible = "nvidia,tegra210-xusb";
1010 reg = <0x0 0x70090000 0x0 0x8 855 reg = <0x0 0x70090000 0x0 0x8000>,
1011 <0x0 0x70098000 0x0 0x1 856 <0x0 0x70098000 0x0 0x1000>,
1012 <0x0 0x70099000 0x0 0x1 857 <0x0 0x70099000 0x0 0x1000>;
1013 reg-names = "hcd", "fpci", "i 858 reg-names = "hcd", "fpci", "ipfs";
1014 859
1015 interrupts = <GIC_SPI 39 IRQ_ 860 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
1016 <GIC_SPI 40 IRQ_ 861 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1017 862
1018 clocks = <&tegra_car TEGRA210 863 clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>,
1019 <&tegra_car TEGRA210 864 <&tegra_car TEGRA210_CLK_XUSB_HOST_SRC>,
1020 <&tegra_car TEGRA210 865 <&tegra_car TEGRA210_CLK_XUSB_FALCON_SRC>,
1021 <&tegra_car TEGRA210 866 <&tegra_car TEGRA210_CLK_XUSB_SS>,
1022 <&tegra_car TEGRA210 867 <&tegra_car TEGRA210_CLK_XUSB_SS_DIV2>,
1023 <&tegra_car TEGRA210 868 <&tegra_car TEGRA210_CLK_XUSB_SS_SRC>,
1024 <&tegra_car TEGRA210 869 <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>,
1025 <&tegra_car TEGRA210 870 <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>,
1026 <&tegra_car TEGRA210 871 <&tegra_car TEGRA210_CLK_PLL_U_480M>,
1027 <&tegra_car TEGRA210 872 <&tegra_car TEGRA210_CLK_CLK_M>,
1028 <&tegra_car TEGRA210 873 <&tegra_car TEGRA210_CLK_PLL_E>;
1029 clock-names = "xusb_host", "x 874 clock-names = "xusb_host", "xusb_host_src",
1030 "xusb_falcon_sr 875 "xusb_falcon_src", "xusb_ss",
1031 "xusb_ss_div2", 876 "xusb_ss_div2", "xusb_ss_src",
1032 "xusb_hs_src", 877 "xusb_hs_src", "xusb_fs_src",
1033 "pll_u_480m", " 878 "pll_u_480m", "clk_m", "pll_e";
1034 resets = <&tegra_car 89>, <&t 879 resets = <&tegra_car 89>, <&tegra_car 156>,
1035 <&tegra_car 143>; 880 <&tegra_car 143>;
1036 reset-names = "xusb_host", "x 881 reset-names = "xusb_host", "xusb_ss", "xusb_src";
1037 power-domains = <&pd_xusbhost 882 power-domains = <&pd_xusbhost>, <&pd_xusbss>;
1038 power-domain-names = "xusb_ho 883 power-domain-names = "xusb_host", "xusb_ss";
1039 884
1040 nvidia,xusb-padctl = <&padctl 885 nvidia,xusb-padctl = <&padctl>;
1041 886
1042 status = "disabled"; 887 status = "disabled";
1043 }; 888 };
1044 889
1045 padctl: padctl@7009f000 { 890 padctl: padctl@7009f000 {
1046 compatible = "nvidia,tegra210 891 compatible = "nvidia,tegra210-xusb-padctl";
1047 reg = <0x0 0x7009f000 0x0 0x1 892 reg = <0x0 0x7009f000 0x0 0x1000>;
1048 interrupts = <GIC_SPI 49 IRQ_ <<
1049 resets = <&tegra_car 142>; 893 resets = <&tegra_car 142>;
1050 reset-names = "padctl"; 894 reset-names = "padctl";
1051 nvidia,pmc = <&tegra_pmc>; <<
1052 895
1053 status = "disabled"; 896 status = "disabled";
1054 897
1055 pads { 898 pads {
1056 usb2 { 899 usb2 {
1057 clocks = <&te 900 clocks = <&tegra_car TEGRA210_CLK_USB2_TRK>;
1058 clock-names = 901 clock-names = "trk";
1059 status = "dis 902 status = "disabled";
1060 903
1061 lanes { 904 lanes {
1062 usb2- 905 usb2-0 {
1063 906 status = "disabled";
1064 907 #phy-cells = <0>;
1065 }; 908 };
1066 909
1067 usb2- 910 usb2-1 {
1068 911 status = "disabled";
1069 912 #phy-cells = <0>;
1070 }; 913 };
1071 914
1072 usb2- 915 usb2-2 {
1073 916 status = "disabled";
1074 917 #phy-cells = <0>;
1075 }; 918 };
1076 919
1077 usb2- 920 usb2-3 {
1078 921 status = "disabled";
1079 922 #phy-cells = <0>;
1080 }; 923 };
1081 }; 924 };
1082 }; 925 };
1083 926
1084 hsic { 927 hsic {
1085 clocks = <&te 928 clocks = <&tegra_car TEGRA210_CLK_HSIC_TRK>;
1086 clock-names = 929 clock-names = "trk";
1087 status = "dis 930 status = "disabled";
1088 931
1089 lanes { 932 lanes {
1090 hsic- 933 hsic-0 {
1091 934 status = "disabled";
1092 935 #phy-cells = <0>;
1093 }; 936 };
1094 937
1095 hsic- 938 hsic-1 {
1096 939 status = "disabled";
1097 940 #phy-cells = <0>;
1098 }; 941 };
1099 }; 942 };
1100 }; 943 };
1101 944
1102 pcie { 945 pcie {
1103 clocks = <&te 946 clocks = <&tegra_car TEGRA210_CLK_PLL_E>;
1104 clock-names = 947 clock-names = "pll";
1105 resets = <&te 948 resets = <&tegra_car 205>;
1106 reset-names = 949 reset-names = "phy";
1107 status = "dis 950 status = "disabled";
1108 951
1109 lanes { 952 lanes {
1110 pcie- 953 pcie-0 {
1111 954 status = "disabled";
1112 955 #phy-cells = <0>;
1113 }; 956 };
1114 957
1115 pcie- 958 pcie-1 {
1116 959 status = "disabled";
1117 960 #phy-cells = <0>;
1118 }; 961 };
1119 962
1120 pcie- 963 pcie-2 {
1121 964 status = "disabled";
1122 965 #phy-cells = <0>;
1123 }; 966 };
1124 967
1125 pcie- 968 pcie-3 {
1126 969 status = "disabled";
1127 970 #phy-cells = <0>;
1128 }; 971 };
1129 972
1130 pcie- 973 pcie-4 {
1131 974 status = "disabled";
1132 975 #phy-cells = <0>;
1133 }; 976 };
1134 977
1135 pcie- 978 pcie-5 {
1136 979 status = "disabled";
1137 980 #phy-cells = <0>;
1138 }; 981 };
1139 982
1140 pcie- 983 pcie-6 {
1141 984 status = "disabled";
1142 985 #phy-cells = <0>;
1143 }; 986 };
1144 }; 987 };
1145 }; 988 };
1146 989
1147 sata { 990 sata {
1148 clocks = <&te 991 clocks = <&tegra_car TEGRA210_CLK_PLL_E>;
1149 clock-names = 992 clock-names = "pll";
1150 resets = <&te 993 resets = <&tegra_car 204>;
1151 reset-names = 994 reset-names = "phy";
1152 status = "dis 995 status = "disabled";
1153 996
1154 lanes { 997 lanes {
1155 sata- 998 sata-0 {
1156 999 status = "disabled";
1157 1000 #phy-cells = <0>;
1158 }; 1001 };
1159 }; 1002 };
1160 }; 1003 };
1161 }; 1004 };
1162 1005
1163 ports { 1006 ports {
1164 usb2-0 { 1007 usb2-0 {
1165 status = "dis 1008 status = "disabled";
1166 }; 1009 };
1167 1010
1168 usb2-1 { 1011 usb2-1 {
1169 status = "dis 1012 status = "disabled";
1170 }; 1013 };
1171 1014
1172 usb2-2 { 1015 usb2-2 {
1173 status = "dis 1016 status = "disabled";
1174 }; 1017 };
1175 1018
1176 usb2-3 { 1019 usb2-3 {
1177 status = "dis 1020 status = "disabled";
1178 }; 1021 };
1179 1022
1180 hsic-0 { 1023 hsic-0 {
1181 status = "dis 1024 status = "disabled";
1182 }; 1025 };
1183 1026
1184 usb3-0 { 1027 usb3-0 {
1185 status = "dis 1028 status = "disabled";
1186 }; 1029 };
1187 1030
1188 usb3-1 { 1031 usb3-1 {
1189 status = "dis 1032 status = "disabled";
1190 }; 1033 };
1191 1034
1192 usb3-2 { 1035 usb3-2 {
1193 status = "dis 1036 status = "disabled";
1194 }; 1037 };
1195 1038
1196 usb3-3 { 1039 usb3-3 {
1197 status = "dis 1040 status = "disabled";
1198 }; 1041 };
1199 }; 1042 };
1200 }; 1043 };
1201 1044
1202 mmc@700b0000 { !! 1045 sdhci@700b0000 {
1203 compatible = "nvidia,tegra210 !! 1046 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";
1204 reg = <0x0 0x700b0000 0x0 0x2 1047 reg = <0x0 0x700b0000 0x0 0x200>;
1205 interrupts = <GIC_SPI 14 IRQ_ 1048 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1206 clocks = <&tegra_car TEGRA210 !! 1049 clocks = <&tegra_car TEGRA210_CLK_SDMMC1>;
1207 <&tegra_car TEGRA210 !! 1050 clock-names = "sdhci";
1208 clock-names = "sdhci", "tmclk <<
1209 resets = <&tegra_car 14>; 1051 resets = <&tegra_car 14>;
1210 reset-names = "sdhci"; 1052 reset-names = "sdhci";
1211 pinctrl-names = "sdmmc-3v3", !! 1053 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
1212 "sdmmc-3v3-dr <<
1213 pinctrl-0 = <&sdmmc1_3v3>; 1054 pinctrl-0 = <&sdmmc1_3v3>;
1214 pinctrl-1 = <&sdmmc1_1v8>; 1055 pinctrl-1 = <&sdmmc1_1v8>;
1215 pinctrl-2 = <&sdmmc1_3v3_drv> <<
1216 pinctrl-3 = <&sdmmc1_1v8_drv> <<
1217 nvidia,pad-autocal-pull-up-of 1056 nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>;
1218 nvidia,pad-autocal-pull-down- 1057 nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>;
1219 nvidia,pad-autocal-pull-up-of 1058 nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>;
1220 nvidia,pad-autocal-pull-down- 1059 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>;
1221 nvidia,default-tap = <0x2>; 1060 nvidia,default-tap = <0x2>;
1222 nvidia,default-trim = <0x4>; 1061 nvidia,default-trim = <0x4>;
1223 assigned-clocks = <&tegra_car 1062 assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>,
1224 <&tegra_car 1063 <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>,
1225 <&tegra_car 1064 <&tegra_car TEGRA210_CLK_PLL_C4>;
1226 assigned-clock-parents = <&te 1065 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
1227 assigned-clock-rates = <20000 1066 assigned-clock-rates = <200000000>, <1000000000>, <1000000000>;
1228 status = "disabled"; 1067 status = "disabled";
1229 }; 1068 };
1230 1069
1231 mmc@700b0200 { !! 1070 sdhci@700b0200 {
1232 compatible = "nvidia,tegra210 !! 1071 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";
1233 reg = <0x0 0x700b0200 0x0 0x2 1072 reg = <0x0 0x700b0200 0x0 0x200>;
1234 interrupts = <GIC_SPI 15 IRQ_ 1073 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1235 clocks = <&tegra_car TEGRA210 !! 1074 clocks = <&tegra_car TEGRA210_CLK_SDMMC2>;
1236 <&tegra_car TEGRA210 !! 1075 clock-names = "sdhci";
1237 clock-names = "sdhci", "tmclk <<
1238 resets = <&tegra_car 9>; 1076 resets = <&tegra_car 9>;
1239 reset-names = "sdhci"; 1077 reset-names = "sdhci";
1240 pinctrl-names = "sdmmc-1v8-dr <<
1241 pinctrl-0 = <&sdmmc2_1v8_drv> <<
1242 nvidia,pad-autocal-pull-up-of 1078 nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>;
1243 nvidia,pad-autocal-pull-down- 1079 nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>;
1244 nvidia,default-tap = <0x8>; 1080 nvidia,default-tap = <0x8>;
1245 nvidia,default-trim = <0x0>; 1081 nvidia,default-trim = <0x0>;
1246 status = "disabled"; 1082 status = "disabled";
1247 }; 1083 };
1248 1084
1249 mmc@700b0400 { !! 1085 sdhci@700b0400 {
1250 compatible = "nvidia,tegra210 !! 1086 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";
1251 reg = <0x0 0x700b0400 0x0 0x2 1087 reg = <0x0 0x700b0400 0x0 0x200>;
1252 interrupts = <GIC_SPI 19 IRQ_ 1088 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1253 clocks = <&tegra_car TEGRA210 !! 1089 clocks = <&tegra_car TEGRA210_CLK_SDMMC3>;
1254 <&tegra_car TEGRA210 !! 1090 clock-names = "sdhci";
1255 clock-names = "sdhci", "tmclk <<
1256 resets = <&tegra_car 69>; 1091 resets = <&tegra_car 69>;
1257 reset-names = "sdhci"; 1092 reset-names = "sdhci";
1258 pinctrl-names = "sdmmc-3v3", !! 1093 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
1259 "sdmmc-3v3-dr <<
1260 pinctrl-0 = <&sdmmc3_3v3>; 1094 pinctrl-0 = <&sdmmc3_3v3>;
1261 pinctrl-1 = <&sdmmc3_1v8>; 1095 pinctrl-1 = <&sdmmc3_1v8>;
1262 pinctrl-2 = <&sdmmc3_3v3_drv> <<
1263 pinctrl-3 = <&sdmmc3_1v8_drv> <<
1264 nvidia,pad-autocal-pull-up-of 1096 nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>;
1265 nvidia,pad-autocal-pull-down- 1097 nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>;
1266 nvidia,pad-autocal-pull-up-of 1098 nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>;
1267 nvidia,pad-autocal-pull-down- 1099 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>;
1268 nvidia,default-tap = <0x3>; 1100 nvidia,default-tap = <0x3>;
1269 nvidia,default-trim = <0x3>; 1101 nvidia,default-trim = <0x3>;
1270 status = "disabled"; 1102 status = "disabled";
1271 }; 1103 };
1272 1104
1273 mmc@700b0600 { !! 1105 sdhci@700b0600 {
1274 compatible = "nvidia,tegra210 !! 1106 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";
1275 reg = <0x0 0x700b0600 0x0 0x2 1107 reg = <0x0 0x700b0600 0x0 0x200>;
1276 interrupts = <GIC_SPI 31 IRQ_ 1108 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
1277 clocks = <&tegra_car TEGRA210 !! 1109 clocks = <&tegra_car TEGRA210_CLK_SDMMC4>;
1278 <&tegra_car TEGRA210 !! 1110 clock-names = "sdhci";
1279 clock-names = "sdhci", "tmclk <<
1280 resets = <&tegra_car 15>; 1111 resets = <&tegra_car 15>;
1281 reset-names = "sdhci"; 1112 reset-names = "sdhci";
1282 pinctrl-names = "sdmmc-3v3-dr <<
1283 pinctrl-0 = <&sdmmc4_1v8_drv> <<
1284 pinctrl-1 = <&sdmmc4_1v8_drv> <<
1285 nvidia,pad-autocal-pull-up-of 1113 nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>;
1286 nvidia,pad-autocal-pull-down- 1114 nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>;
1287 nvidia,default-tap = <0x8>; 1115 nvidia,default-tap = <0x8>;
1288 nvidia,default-trim = <0x0>; 1116 nvidia,default-trim = <0x0>;
1289 assigned-clocks = <&tegra_car 1117 assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>,
1290 <&tegra_car 1118 <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
1291 assigned-clock-parents = <&te 1119 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
1292 nvidia,dqs-trim = <40>; 1120 nvidia,dqs-trim = <40>;
1293 mmc-hs400-1_8v; 1121 mmc-hs400-1_8v;
1294 status = "disabled"; 1122 status = "disabled";
1295 }; 1123 };
1296 1124
1297 usb@700d0000 { <<
1298 compatible = "nvidia,tegra210 <<
1299 reg = <0x0 0x700d0000 0x0 0x8 <<
1300 <0x0 0x700d8000 0x0 0x1 <<
1301 <0x0 0x700d9000 0x0 0x1 <<
1302 reg-names = "base", "fpci", " <<
1303 interrupts = <GIC_SPI 44 IRQ_ <<
1304 clocks = <&tegra_car TEGRA210 <<
1305 <&tegra_car TEGRA210 <<
1306 <&tegra_car TEGRA210 <<
1307 <&tegra_car TEGRA210 <<
1308 <&tegra_car TEGRA210 <<
1309 clock-names = "dev", "ss", "s <<
1310 power-domains = <&pd_xusbdev> <<
1311 power-domain-names = "dev", " <<
1312 nvidia,xusb-padctl = <&padctl <<
1313 status = "disabled"; <<
1314 }; <<
1315 <<
1316 soctherm: thermal-sensor@700e2000 { <<
1317 compatible = "nvidia,tegra210 <<
1318 reg = <0x0 0x700e2000 0x0 0x6 <<
1319 <0x0 0x60006000 0x0 0x4 <<
1320 reg-names = "soctherm-reg", " <<
1321 interrupts = <GIC_SPI 48 IRQ_ <<
1322 <GIC_SPI 51 IRQ_ <<
1323 interrupt-names = "thermal", <<
1324 clocks = <&tegra_car TEGRA210 <<
1325 <&tegra_car TEGRA210_ <<
1326 clock-names = "tsensor", "soc <<
1327 resets = <&tegra_car 78>; <<
1328 reset-names = "soctherm"; <<
1329 #thermal-sensor-cells = <1>; <<
1330 <<
1331 throttle-cfgs { <<
1332 throttle_heavy: heavy <<
1333 nvidia,priori <<
1334 nvidia,cpu-th <<
1335 nvidia,gpu-th <<
1336 <<
1337 #cooling-cell <<
1338 }; <<
1339 }; <<
1340 }; <<
1341 <<
1342 mipi: mipi@700e3000 { 1125 mipi: mipi@700e3000 {
1343 compatible = "nvidia,tegra210 1126 compatible = "nvidia,tegra210-mipi";
1344 reg = <0x0 0x700e3000 0x0 0x1 1127 reg = <0x0 0x700e3000 0x0 0x100>;
1345 clocks = <&tegra_car TEGRA210 1128 clocks = <&tegra_car TEGRA210_CLK_MIPI_CAL>;
1346 clock-names = "mipi-cal"; 1129 clock-names = "mipi-cal";
1347 power-domains = <&pd_sor>; 1130 power-domains = <&pd_sor>;
1348 #nvidia,mipi-calibrate-cells 1131 #nvidia,mipi-calibrate-cells = <1>;
1349 }; 1132 };
1350 1133
1351 dfll: clock@70110000 { <<
1352 compatible = "nvidia,tegra210 <<
1353 reg = <0 0x70110000 0 0x100>, <<
1354 <0 0x70110000 0 0x100>, <<
1355 <0 0x70110100 0 0x100>, <<
1356 <0 0x70110200 0 0x100>; <<
1357 interrupts = <GIC_SPI 62 IRQ_ <<
1358 clocks = <&tegra_car TEGRA210 <<
1359 <&tegra_car TEGRA210 <<
1360 <&tegra_car TEGRA210 <<
1361 clock-names = "soc", "ref", " <<
1362 resets = <&tegra_car TEGRA210 <<
1363 <&tegra_car 155>; <<
1364 reset-names = "dvco", "dfll"; <<
1365 #clock-cells = <0>; <<
1366 clock-output-names = "dfllCPU <<
1367 status = "disabled"; <<
1368 }; <<
1369 <<
1370 aconnect@702c0000 { 1134 aconnect@702c0000 {
1371 compatible = "nvidia,tegra210 1135 compatible = "nvidia,tegra210-aconnect";
1372 clocks = <&tegra_car TEGRA210 1136 clocks = <&tegra_car TEGRA210_CLK_APE>,
1373 <&tegra_car TEGRA210 1137 <&tegra_car TEGRA210_CLK_APB2APE>;
1374 clock-names = "ape", "apb2ape 1138 clock-names = "ape", "apb2ape";
1375 power-domains = <&pd_audio>; 1139 power-domains = <&pd_audio>;
1376 #address-cells = <1>; 1140 #address-cells = <1>;
1377 #size-cells = <1>; 1141 #size-cells = <1>;
1378 ranges = <0x702c0000 0x0 0x70 1142 ranges = <0x702c0000 0x0 0x702c0000 0x00040000>;
1379 status = "disabled"; 1143 status = "disabled";
1380 1144
1381 tegra_ahub: ahub@702d0800 { !! 1145 adma: dma@702e2000 {
1382 compatible = "nvidia, <<
1383 reg = <0x702d0800 0x8 <<
1384 clocks = <&tegra_car <<
1385 clock-names = "ahub"; <<
1386 assigned-clocks = <&t <<
1387 assigned-clock-parent <<
1388 assigned-clock-rates <<
1389 #address-cells = <1>; <<
1390 #size-cells = <1>; <<
1391 ranges = <0x702d0000 <<
1392 status = "disabled"; <<
1393 <<
1394 tegra_admaif: admaif@ <<
1395 compatible = <<
1396 reg = <0x702d <<
1397 dmas = <&adma <<
1398 <&adma <<
1399 <&adma <<
1400 <&adma <<
1401 <&adma <<
1402 <&adma <<
1403 <&adma <<
1404 <&adma <<
1405 <&adma <<
1406 <&adma <<
1407 dma-names = " <<
1408 " <<
1409 " <<
1410 " <<
1411 " <<
1412 " <<
1413 " <<
1414 " <<
1415 " <<
1416 " <<
1417 status = "dis <<
1418 <<
1419 ports { <<
1420 #addr <<
1421 #size <<
1422 <<
1423 admai <<
1424 <<
1425 <<
1426 <<
1427 <<
1428 <<
1429 }; <<
1430 <<
1431 admai <<
1432 <<
1433 <<
1434 <<
1435 <<
1436 <<
1437 }; <<
1438 <<
1439 admai <<
1440 <<
1441 <<
1442 <<
1443 <<
1444 <<
1445 }; <<
1446 <<
1447 admai <<
1448 <<
1449 <<
1450 <<
1451 <<
1452 <<
1453 }; <<
1454 <<
1455 admai <<
1456 <<
1457 <<
1458 <<
1459 <<
1460 <<
1461 }; <<
1462 <<
1463 admai <<
1464 <<
1465 <<
1466 <<
1467 <<
1468 <<
1469 }; <<
1470 <<
1471 admai <<
1472 <<
1473 <<
1474 <<
1475 <<
1476 <<
1477 }; <<
1478 <<
1479 admai <<
1480 <<
1481 <<
1482 <<
1483 <<
1484 <<
1485 }; <<
1486 <<
1487 admai <<
1488 <<
1489 <<
1490 <<
1491 <<
1492 <<
1493 }; <<
1494 <<
1495 admai <<
1496 <<
1497 <<
1498 <<
1499 <<
1500 <<
1501 }; <<
1502 }; <<
1503 }; <<
1504 <<
1505 tegra_i2s1: i2s@702d1 <<
1506 compatible = <<
1507 reg = <0x702d <<
1508 clocks = <&te <<
1509 <&te <<
1510 clock-names = <<
1511 assigned-cloc <<
1512 assigned-cloc <<
1513 assigned-cloc <<
1514 sound-name-pr <<
1515 status = "dis <<
1516 }; <<
1517 <<
1518 tegra_i2s2: i2s@702d1 <<
1519 compatible = <<
1520 reg = <0x702d <<
1521 clocks = <&te <<
1522 <&te <<
1523 clock-names = <<
1524 assigned-cloc <<
1525 assigned-cloc <<
1526 assigned-cloc <<
1527 sound-name-pr <<
1528 status = "dis <<
1529 }; <<
1530 <<
1531 tegra_i2s3: i2s@702d1 <<
1532 compatible = <<
1533 reg = <0x702d <<
1534 clocks = <&te <<
1535 <&te <<
1536 clock-names = <<
1537 assigned-cloc <<
1538 assigned-cloc <<
1539 assigned-cloc <<
1540 sound-name-pr <<
1541 status = "dis <<
1542 }; <<
1543 <<
1544 tegra_i2s4: i2s@702d1 <<
1545 compatible = <<
1546 reg = <0x702d <<
1547 clocks = <&te <<
1548 <&te <<
1549 clock-names = <<
1550 assigned-cloc <<
1551 assigned-cloc <<
1552 assigned-cloc <<
1553 sound-name-pr <<
1554 status = "dis <<
1555 }; <<
1556 <<
1557 tegra_i2s5: i2s@702d1 <<
1558 compatible = <<
1559 reg = <0x702d <<
1560 clocks = <&te <<
1561 <&te <<
1562 clock-names = <<
1563 assigned-cloc <<
1564 assigned-cloc <<
1565 assigned-cloc <<
1566 sound-name-pr <<
1567 status = "dis <<
1568 }; <<
1569 <<
1570 tegra_sfc1: sfc@702d2 <<
1571 compatible = <<
1572 reg = <0x702d <<
1573 sound-name-pr <<
1574 status = "dis <<
1575 }; <<
1576 <<
1577 tegra_sfc2: sfc@702d2 <<
1578 compatible = <<
1579 reg = <0x702d <<
1580 sound-name-pr <<
1581 status = "dis <<
1582 }; <<
1583 <<
1584 tegra_sfc3: sfc@702d2 <<
1585 compatible = <<
1586 reg = <0x702d <<
1587 sound-name-pr <<
1588 status = "dis <<
1589 }; <<
1590 <<
1591 tegra_sfc4: sfc@702d2 <<
1592 compatible = <<
1593 reg = <0x702d <<
1594 sound-name-pr <<
1595 status = "dis <<
1596 }; <<
1597 <<
1598 tegra_amx1: amx@702d3 <<
1599 compatible = <<
1600 reg = <0x702d <<
1601 sound-name-pr <<
1602 status = "dis <<
1603 }; <<
1604 <<
1605 tegra_amx2: amx@702d3 <<
1606 compatible = <<
1607 reg = <0x702d <<
1608 sound-name-pr <<
1609 status = "dis <<
1610 }; <<
1611 <<
1612 tegra_adx1: adx@702d3 <<
1613 compatible = <<
1614 reg = <0x702d <<
1615 sound-name-pr <<
1616 status = "dis <<
1617 }; <<
1618 <<
1619 tegra_adx2: adx@702d3 <<
1620 compatible = <<
1621 reg = <0x702d <<
1622 sound-name-pr <<
1623 status = "dis <<
1624 }; <<
1625 <<
1626 tegra_dmic1: dmic@702 <<
1627 compatible = <<
1628 reg = <0x702d <<
1629 clocks = <&te <<
1630 clock-names = <<
1631 assigned-cloc <<
1632 assigned-cloc <<
1633 assigned-cloc <<
1634 sound-name-pr <<
1635 status = "dis <<
1636 }; <<
1637 <<
1638 tegra_dmic2: dmic@702 <<
1639 compatible = <<
1640 reg = <0x702d <<
1641 clocks = <&te <<
1642 clock-names = <<
1643 assigned-cloc <<
1644 assigned-cloc <<
1645 assigned-cloc <<
1646 sound-name-pr <<
1647 status = "dis <<
1648 }; <<
1649 <<
1650 tegra_dmic3: dmic@702 <<
1651 compatible = <<
1652 reg = <0x702d <<
1653 clocks = <&te <<
1654 clock-names = <<
1655 assigned-cloc <<
1656 assigned-cloc <<
1657 assigned-cloc <<
1658 sound-name-pr <<
1659 status = "dis <<
1660 }; <<
1661 <<
1662 tegra_ope1: processin <<
1663 compatible = <<
1664 reg = <0x702d <<
1665 #address-cell <<
1666 #size-cells = <<
1667 ranges; <<
1668 sound-name-pr <<
1669 status = "dis <<
1670 <<
1671 equalizer@702 <<
1672 compa <<
1673 reg = <<
1674 }; <<
1675 <<
1676 dynamic-range <<
1677 compa <<
1678 reg = <<
1679 }; <<
1680 }; <<
1681 <<
1682 tegra_ope2: processin <<
1683 compatible = <<
1684 reg = <0x702d <<
1685 #address-cell <<
1686 #size-cells = <<
1687 ranges; <<
1688 sound-name-pr <<
1689 status = "dis <<
1690 <<
1691 equalizer@702 <<
1692 compa <<
1693 reg = <<
1694 }; <<
1695 <<
1696 dynamic-range <<
1697 compa <<
1698 reg = <<
1699 }; <<
1700 }; <<
1701 <<
1702 tegra_mvc1: mvc@702da <<
1703 compatible = <<
1704 reg = <0x702d <<
1705 sound-name-pr <<
1706 status = "dis <<
1707 }; <<
1708 <<
1709 tegra_mvc2: mvc@702da <<
1710 compatible = <<
1711 reg = <0x702d <<
1712 sound-name-pr <<
1713 status = "dis <<
1714 }; <<
1715 <<
1716 tegra_amixer: amixer@ <<
1717 compatible = <<
1718 reg = <0x702d <<
1719 sound-name-pr <<
1720 status = "dis <<
1721 }; <<
1722 <<
1723 ports { <<
1724 #address-cell <<
1725 #size-cells = <<
1726 <<
1727 port@0 { <<
1728 reg = <<
1729 <<
1730 xbar_ <<
1731 <<
1732 }; <<
1733 }; <<
1734 <<
1735 port@1 { <<
1736 reg = <<
1737 <<
1738 xbar_ <<
1739 <<
1740 }; <<
1741 }; <<
1742 <<
1743 port@2 { <<
1744 reg = <<
1745 <<
1746 xbar_ <<
1747 <<
1748 }; <<
1749 }; <<
1750 <<
1751 port@3 { <<
1752 reg = <<
1753 <<
1754 xbar_ <<
1755 <<
1756 }; <<
1757 }; <<
1758 <<
1759 port@4 { <<
1760 reg = <<
1761 xbar_ <<
1762 <<
1763 }; <<
1764 }; <<
1765 port@5 { <<
1766 reg = <<
1767 <<
1768 xbar_ <<
1769 <<
1770 }; <<
1771 }; <<
1772 <<
1773 port@6 { <<
1774 reg = <<
1775 <<
1776 xbar_ <<
1777 <<
1778 }; <<
1779 }; <<
1780 <<
1781 port@7 { <<
1782 reg = <<
1783 <<
1784 xbar_ <<
1785 <<
1786 }; <<
1787 }; <<
1788 <<
1789 port@8 { <<
1790 reg = <<
1791 <<
1792 xbar_ <<
1793 <<
1794 }; <<
1795 }; <<
1796 <<
1797 port@9 { <<
1798 reg = <<
1799 <<
1800 xbar_ <<
1801 <<
1802 }; <<
1803 }; <<
1804 }; <<
1805 }; <<
1806 <<
1807 adma: dma-controller@702e2000 <<
1808 compatible = "nvidia, 1146 compatible = "nvidia,tegra210-adma";
1809 reg = <0x702e2000 0x2 1147 reg = <0x702e2000 0x2000>;
1810 interrupt-parent = <& 1148 interrupt-parent = <&agic>;
1811 interrupts = <GIC_SPI 1149 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
1812 <GIC_SPI 1150 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
1813 <GIC_SPI 1151 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
1814 <GIC_SPI 1152 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
1815 <GIC_SPI 1153 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
1816 <GIC_SPI 1154 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
1817 <GIC_SPI 1155 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
1818 <GIC_SPI 1156 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
1819 <GIC_SPI 1157 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
1820 <GIC_SPI 1158 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
1821 <GIC_SPI 1159 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
1822 <GIC_SPI 1160 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
1823 <GIC_SPI 1161 <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
1824 <GIC_SPI 1162 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
1825 <GIC_SPI 1163 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
1826 <GIC_SPI 1164 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
1827 <GIC_SPI 1165 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
1828 <GIC_SPI 1166 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
1829 <GIC_SPI 1167 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
1830 <GIC_SPI 1168 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
1831 <GIC_SPI 1169 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
1832 <GIC_SPI 1170 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1833 #dma-cells = <1>; 1171 #dma-cells = <1>;
1834 clocks = <&tegra_car 1172 clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>;
1835 clock-names = "d_audi 1173 clock-names = "d_audio";
1836 status = "disabled"; 1174 status = "disabled";
1837 }; 1175 };
1838 1176
1839 agic: interrupt-controller@70 !! 1177 agic: agic@702f9000 {
1840 compatible = "nvidia, 1178 compatible = "nvidia,tegra210-agic";
1841 #interrupt-cells = <3 1179 #interrupt-cells = <3>;
1842 interrupt-controller; 1180 interrupt-controller;
1843 reg = <0x702f9000 0x1 !! 1181 reg = <0x702f9000 0x2000>,
1844 <0x702fa000 0x2 1182 <0x702fa000 0x2000>;
1845 interrupts = <GIC_SPI 1183 interrupts = <GIC_SPI 102 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1846 clocks = <&tegra_car 1184 clocks = <&tegra_car TEGRA210_CLK_APE>;
1847 clock-names = "clk"; 1185 clock-names = "clk";
1848 status = "disabled"; 1186 status = "disabled";
1849 }; 1187 };
1850 }; 1188 };
1851 1189
1852 spi@70410000 { 1190 spi@70410000 {
1853 compatible = "nvidia,tegra210 1191 compatible = "nvidia,tegra210-qspi";
1854 reg = <0x0 0x70410000 0x0 0x1 1192 reg = <0x0 0x70410000 0x0 0x1000>;
1855 interrupts = <GIC_SPI 10 IRQ_ 1193 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1856 #address-cells = <1>; 1194 #address-cells = <1>;
1857 #size-cells = <0>; 1195 #size-cells = <0>;
1858 clocks = <&tegra_car TEGRA210 !! 1196 clocks = <&tegra_car TEGRA210_CLK_QSPI>;
1859 <&tegra_car TEGRA210 !! 1197 clock-names = "qspi";
1860 clock-names = "qspi", "qspi_o <<
1861 resets = <&tegra_car 211>; 1198 resets = <&tegra_car 211>;
>> 1199 reset-names = "qspi";
1862 dmas = <&apbdma 5>, <&apbdma 1200 dmas = <&apbdma 5>, <&apbdma 5>;
1863 dma-names = "rx", "tx"; 1201 dma-names = "rx", "tx";
1864 status = "disabled"; 1202 status = "disabled";
1865 }; 1203 };
1866 1204
1867 usb@7d000000 { 1205 usb@7d000000 {
1868 compatible = "nvidia,tegra210 !! 1206 compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci";
1869 reg = <0x0 0x7d000000 0x0 0x4 1207 reg = <0x0 0x7d000000 0x0 0x4000>;
1870 interrupts = <GIC_SPI 20 IRQ_ 1208 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1871 phy_type = "utmi"; 1209 phy_type = "utmi";
1872 clocks = <&tegra_car TEGRA210 1210 clocks = <&tegra_car TEGRA210_CLK_USBD>;
1873 clock-names = "usb"; 1211 clock-names = "usb";
1874 resets = <&tegra_car 22>; 1212 resets = <&tegra_car 22>;
1875 reset-names = "usb"; 1213 reset-names = "usb";
1876 nvidia,phy = <&phy1>; 1214 nvidia,phy = <&phy1>;
1877 status = "disabled"; 1215 status = "disabled";
1878 }; 1216 };
1879 1217
1880 phy1: usb-phy@7d000000 { 1218 phy1: usb-phy@7d000000 {
1881 compatible = "nvidia,tegra210 1219 compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy";
1882 reg = <0x0 0x7d000000 0x0 0x4 1220 reg = <0x0 0x7d000000 0x0 0x4000>,
1883 <0x0 0x7d000000 0x0 0x4 1221 <0x0 0x7d000000 0x0 0x4000>;
1884 phy_type = "utmi"; 1222 phy_type = "utmi";
1885 clocks = <&tegra_car TEGRA210 1223 clocks = <&tegra_car TEGRA210_CLK_USBD>,
1886 <&tegra_car TEGRA210 1224 <&tegra_car TEGRA210_CLK_PLL_U>,
1887 <&tegra_car TEGRA210 1225 <&tegra_car TEGRA210_CLK_USBD>;
1888 clock-names = "reg", "pll_u", 1226 clock-names = "reg", "pll_u", "utmi-pads";
1889 resets = <&tegra_car 22>, <&t 1227 resets = <&tegra_car 22>, <&tegra_car 22>;
1890 reset-names = "usb", "utmi-pa 1228 reset-names = "usb", "utmi-pads";
1891 nvidia,hssync-start-delay = < 1229 nvidia,hssync-start-delay = <0>;
1892 nvidia,idle-wait-delay = <17> 1230 nvidia,idle-wait-delay = <17>;
1893 nvidia,elastic-limit = <16>; 1231 nvidia,elastic-limit = <16>;
1894 nvidia,term-range-adj = <6>; 1232 nvidia,term-range-adj = <6>;
1895 nvidia,xcvr-setup = <9>; 1233 nvidia,xcvr-setup = <9>;
1896 nvidia,xcvr-lsfslew = <0>; 1234 nvidia,xcvr-lsfslew = <0>;
1897 nvidia,xcvr-lsrslew = <3>; 1235 nvidia,xcvr-lsrslew = <3>;
1898 nvidia,hssquelch-level = <2>; 1236 nvidia,hssquelch-level = <2>;
1899 nvidia,hsdiscon-level = <5>; 1237 nvidia,hsdiscon-level = <5>;
1900 nvidia,xcvr-hsslew = <12>; 1238 nvidia,xcvr-hsslew = <12>;
1901 nvidia,has-utmi-pad-registers 1239 nvidia,has-utmi-pad-registers;
1902 status = "disabled"; 1240 status = "disabled";
1903 }; 1241 };
1904 1242
1905 usb@7d004000 { 1243 usb@7d004000 {
1906 compatible = "nvidia,tegra210 !! 1244 compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci";
1907 reg = <0x0 0x7d004000 0x0 0x4 1245 reg = <0x0 0x7d004000 0x0 0x4000>;
1908 interrupts = <GIC_SPI 21 IRQ_ 1246 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
1909 phy_type = "utmi"; 1247 phy_type = "utmi";
1910 clocks = <&tegra_car TEGRA210 1248 clocks = <&tegra_car TEGRA210_CLK_USB2>;
1911 clock-names = "usb"; 1249 clock-names = "usb";
1912 resets = <&tegra_car 58>; 1250 resets = <&tegra_car 58>;
1913 reset-names = "usb"; 1251 reset-names = "usb";
1914 nvidia,phy = <&phy2>; 1252 nvidia,phy = <&phy2>;
1915 status = "disabled"; 1253 status = "disabled";
1916 }; 1254 };
1917 1255
1918 phy2: usb-phy@7d004000 { 1256 phy2: usb-phy@7d004000 {
1919 compatible = "nvidia,tegra210 1257 compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy";
1920 reg = <0x0 0x7d004000 0x0 0x4 1258 reg = <0x0 0x7d004000 0x0 0x4000>,
1921 <0x0 0x7d000000 0x0 0x4 1259 <0x0 0x7d000000 0x0 0x4000>;
1922 phy_type = "utmi"; 1260 phy_type = "utmi";
1923 clocks = <&tegra_car TEGRA210 1261 clocks = <&tegra_car TEGRA210_CLK_USB2>,
1924 <&tegra_car TEGRA210 1262 <&tegra_car TEGRA210_CLK_PLL_U>,
1925 <&tegra_car TEGRA210 1263 <&tegra_car TEGRA210_CLK_USBD>;
1926 clock-names = "reg", "pll_u", 1264 clock-names = "reg", "pll_u", "utmi-pads";
1927 resets = <&tegra_car 58>, <&t 1265 resets = <&tegra_car 58>, <&tegra_car 22>;
1928 reset-names = "usb", "utmi-pa 1266 reset-names = "usb", "utmi-pads";
1929 nvidia,hssync-start-delay = < 1267 nvidia,hssync-start-delay = <0>;
1930 nvidia,idle-wait-delay = <17> 1268 nvidia,idle-wait-delay = <17>;
1931 nvidia,elastic-limit = <16>; 1269 nvidia,elastic-limit = <16>;
1932 nvidia,term-range-adj = <6>; 1270 nvidia,term-range-adj = <6>;
1933 nvidia,xcvr-setup = <9>; 1271 nvidia,xcvr-setup = <9>;
1934 nvidia,xcvr-lsfslew = <0>; 1272 nvidia,xcvr-lsfslew = <0>;
1935 nvidia,xcvr-lsrslew = <3>; 1273 nvidia,xcvr-lsrslew = <3>;
1936 nvidia,hssquelch-level = <2>; 1274 nvidia,hssquelch-level = <2>;
1937 nvidia,hsdiscon-level = <5>; 1275 nvidia,hsdiscon-level = <5>;
1938 nvidia,xcvr-hsslew = <12>; 1276 nvidia,xcvr-hsslew = <12>;
1939 status = "disabled"; 1277 status = "disabled";
1940 }; 1278 };
1941 1279
1942 cpus { 1280 cpus {
1943 #address-cells = <1>; 1281 #address-cells = <1>;
1944 #size-cells = <0>; 1282 #size-cells = <0>;
1945 1283
1946 cpu@0 { 1284 cpu@0 {
1947 device_type = "cpu"; 1285 device_type = "cpu";
1948 compatible = "arm,cor 1286 compatible = "arm,cortex-a57";
1949 reg = <0>; 1287 reg = <0>;
1950 clocks = <&tegra_car <<
1951 <&tegra_car <<
1952 <&tegra_car <<
1953 <&dfll>; <<
1954 clock-names = "cpu_g" <<
1955 clock-latency = <3000 <<
1956 cpu-idle-states = <&C <<
1957 next-level-cache = <& <<
1958 }; 1288 };
1959 1289
1960 cpu@1 { 1290 cpu@1 {
1961 device_type = "cpu"; 1291 device_type = "cpu";
1962 compatible = "arm,cor 1292 compatible = "arm,cortex-a57";
1963 reg = <1>; 1293 reg = <1>;
1964 cpu-idle-states = <&C <<
1965 next-level-cache = <& <<
1966 }; 1294 };
1967 1295
1968 cpu@2 { 1296 cpu@2 {
1969 device_type = "cpu"; 1297 device_type = "cpu";
1970 compatible = "arm,cor 1298 compatible = "arm,cortex-a57";
1971 reg = <2>; 1299 reg = <2>;
1972 cpu-idle-states = <&C <<
1973 next-level-cache = <& <<
1974 }; 1300 };
1975 1301
1976 cpu@3 { 1302 cpu@3 {
1977 device_type = "cpu"; 1303 device_type = "cpu";
1978 compatible = "arm,cor 1304 compatible = "arm,cortex-a57";
1979 reg = <3>; 1305 reg = <3>;
1980 cpu-idle-states = <&C <<
1981 next-level-cache = <& <<
1982 }; <<
1983 <<
1984 idle-states { <<
1985 entry-method = "psci" <<
1986 <<
1987 CPU_SLEEP: cpu-sleep <<
1988 compatible = <<
1989 arm,psci-susp <<
1990 entry-latency <<
1991 exit-latency- <<
1992 min-residency <<
1993 wakeup-latenc <<
1994 idle-state-na <<
1995 status = "dis <<
1996 }; <<
1997 }; <<
1998 <<
1999 L2: l2-cache { <<
2000 compatible = "cache"; <<
2001 cache-level = <2>; <<
2002 cache-unified; <<
2003 }; 1306 };
2004 }; 1307 };
2005 1308
2006 pmu { !! 1309 timer {
2007 compatible = "arm,cortex-a57- !! 1310 compatible = "arm,armv8-timer";
2008 interrupts = <GIC_SPI 144 IRQ !! 1311 interrupts = <GIC_PPI 13
2009 <GIC_SPI 145 IRQ !! 1312 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2010 <GIC_SPI 146 IRQ !! 1313 <GIC_PPI 14
2011 <GIC_SPI 147 IRQ !! 1314 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2012 interrupt-affinity = <&{/cpus !! 1315 <GIC_PPI 11
2013 &{/cpus !! 1316 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
>> 1317 <GIC_PPI 10
>> 1318 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
>> 1319 interrupt-parent = <&gic>;
2014 }; 1320 };
2015 1321
2016 sound { !! 1322 soctherm: thermal-sensor@700e2000 {
2017 status = "disabled"; !! 1323 compatible = "nvidia,tegra210-soctherm";
>> 1324 reg = <0x0 0x700e2000 0x0 0x600 /* SOC_THERM reg_base */
>> 1325 0x0 0x60006000 0x0 0x400>; /* CAR reg_base */
>> 1326 reg-names = "soctherm-reg", "car-reg";
>> 1327 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
>> 1328 clocks = <&tegra_car TEGRA210_CLK_TSENSOR>,
>> 1329 <&tegra_car TEGRA210_CLK_SOC_THERM>;
>> 1330 clock-names = "tsensor", "soctherm";
>> 1331 resets = <&tegra_car 78>;
>> 1332 reset-names = "soctherm";
>> 1333 #thermal-sensor-cells = <1>;
2018 1334
2019 clocks = <&tegra_car TEGRA210 !! 1335 throttle-cfgs {
2020 <&tegra_car TEGRA210 !! 1336 throttle_heavy: heavy {
2021 clock-names = "pll_a", "plla_ !! 1337 nvidia,priority = <100>;
>> 1338 nvidia,cpu-throt-percent = <85>;
2022 1339
2023 assigned-clocks = <&tegra_car !! 1340 #cooling-cells = <2>;
2024 <&tegra_car !! 1341 };
2025 <&tegra_car !! 1342 };
2026 assigned-clock-parents = <0>, <<
2027 assigned-clock-rates = <36864 <<
2028 }; 1343 };
2029 1344
2030 thermal-zones { 1345 thermal-zones {
2031 cpu-thermal { !! 1346 cpu {
2032 polling-delay-passive 1347 polling-delay-passive = <1000>;
2033 polling-delay = <0>; 1348 polling-delay = <0>;
2034 1349
2035 thermal-sensors = 1350 thermal-sensors =
2036 <&soctherm TE 1351 <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>;
2037 1352
2038 trips { 1353 trips {
2039 cpu-shutdown- 1354 cpu-shutdown-trip {
2040 tempe 1355 temperature = <102500>;
2041 hyste 1356 hysteresis = <0>;
2042 type 1357 type = "critical";
2043 }; 1358 };
2044 1359
2045 cpu_throttle_ 1360 cpu_throttle_trip: throttle-trip {
2046 tempe 1361 temperature = <98500>;
2047 hyste 1362 hysteresis = <1000>;
2048 type 1363 type = "hot";
2049 }; 1364 };
2050 }; 1365 };
2051 1366
2052 cooling-maps { 1367 cooling-maps {
2053 map0 { 1368 map0 {
2054 trip 1369 trip = <&cpu_throttle_trip>;
2055 cooli 1370 cooling-device = <&throttle_heavy 1 1>;
2056 }; 1371 };
2057 }; 1372 };
2058 }; 1373 };
2059 !! 1374 mem {
2060 mem-thermal { <<
2061 polling-delay-passive 1375 polling-delay-passive = <0>;
2062 polling-delay = <0>; 1376 polling-delay = <0>;
2063 1377
2064 thermal-sensors = 1378 thermal-sensors =
2065 <&soctherm TE 1379 <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>;
2066 1380
2067 trips { 1381 trips {
2068 dram_nominal: <<
2069 tempe <<
2070 hyste <<
2071 type <<
2072 }; <<
2073 <<
2074 dram_throttle <<
2075 tempe <<
2076 hyste <<
2077 type <<
2078 }; <<
2079 <<
2080 mem-hot-trip <<
2081 tempe <<
2082 hyste <<
2083 type <<
2084 }; <<
2085 <<
2086 mem-shutdown- 1382 mem-shutdown-trip {
2087 tempe 1383 temperature = <103000>;
2088 hyste 1384 hysteresis = <0>;
2089 type 1385 type = "critical";
2090 }; 1386 };
2091 }; 1387 };
2092 1388
2093 cooling-maps { 1389 cooling-maps {
2094 dram-passive !! 1390 /*
2095 cooli !! 1391 * There are currently no cooling maps,
2096 trip !! 1392 * because there are no cooling devices.
2097 }; !! 1393 */
2098 <<
2099 dram-active { <<
2100 cooli <<
2101 trip <<
2102 }; <<
2103 }; 1394 };
2104 }; 1395 };
2105 !! 1396 gpu {
2106 gpu-thermal { <<
2107 polling-delay-passive 1397 polling-delay-passive = <1000>;
2108 polling-delay = <0>; 1398 polling-delay = <0>;
2109 1399
2110 thermal-sensors = 1400 thermal-sensors =
2111 <&soctherm TE 1401 <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>;
2112 1402
2113 trips { 1403 trips {
2114 gpu-shutdown- 1404 gpu-shutdown-trip {
2115 tempe 1405 temperature = <103000>;
2116 hyste 1406 hysteresis = <0>;
2117 type 1407 type = "critical";
2118 }; 1408 };
2119 1409
2120 gpu_throttle_ 1410 gpu_throttle_trip: throttle-trip {
2121 tempe 1411 temperature = <100000>;
2122 hyste 1412 hysteresis = <1000>;
2123 type 1413 type = "hot";
2124 }; 1414 };
2125 }; 1415 };
2126 1416
2127 cooling-maps { 1417 cooling-maps {
2128 map0 { 1418 map0 {
2129 trip 1419 trip = <&gpu_throttle_trip>;
2130 cooli 1420 cooling-device = <&throttle_heavy 1 1>;
2131 }; 1421 };
2132 }; 1422 };
2133 }; 1423 };
2134 !! 1424 pllx {
2135 pllx-thermal { <<
2136 polling-delay-passive 1425 polling-delay-passive = <0>;
2137 polling-delay = <0>; 1426 polling-delay = <0>;
2138 1427
2139 thermal-sensors = 1428 thermal-sensors =
2140 <&soctherm TE 1429 <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>;
2141 1430
2142 trips { 1431 trips {
2143 pllx-shutdown 1432 pllx-shutdown-trip {
2144 tempe 1433 temperature = <103000>;
2145 hyste 1434 hysteresis = <0>;
2146 type 1435 type = "critical";
2147 }; 1436 };
2148 <<
2149 pllx-throttle <<
2150 tempe <<
2151 hyste <<
2152 type <<
2153 }; <<
2154 }; 1437 };
2155 1438
2156 cooling-maps { 1439 cooling-maps {
2157 /* 1440 /*
2158 * There are 1441 * There are currently no cooling maps,
2159 * because th 1442 * because there are no cooling devices.
2160 */ 1443 */
2161 }; 1444 };
2162 }; 1445 };
2163 }; <<
2164 <<
2165 timer { <<
2166 compatible = "arm,armv8-timer <<
2167 interrupts = <GIC_PPI 13 <<
2168 (GIC_CPU_MASK <<
2169 <GIC_PPI 14 <<
2170 (GIC_CPU_MASK <<
2171 <GIC_PPI 11 <<
2172 (GIC_CPU_MASK <<
2173 <GIC_PPI 10 <<
2174 (GIC_CPU_MASK <<
2175 interrupt-parent = <&gic>; <<
2176 arm,no-tick-in-suspend; <<
2177 }; 1446 };
2178 }; 1447 };
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