1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra210-car.h> 2 #include <dt-bindings/clock/tegra210-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h> 3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra210-mc.h> 4 #include <dt-bindings/memory/tegra210-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h> 5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra-io 6 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
7 #include <dt-bindings/reset/tegra210-car.h> 7 #include <dt-bindings/reset/tegra210-car.h>
8 #include <dt-bindings/interrupt-controller/arm 8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/thermal/tegra124-socther 9 #include <dt-bindings/thermal/tegra124-soctherm.h>
10 #include <dt-bindings/soc/tegra-pmc.h> <<
11 10
12 / { 11 / {
13 compatible = "nvidia,tegra210"; 12 compatible = "nvidia,tegra210";
14 interrupt-parent = <&lic>; 13 interrupt-parent = <&lic>;
15 #address-cells = <2>; 14 #address-cells = <2>;
16 #size-cells = <2>; 15 #size-cells = <2>;
17 16
18 pcie@1003000 { 17 pcie@1003000 {
19 compatible = "nvidia,tegra210- 18 compatible = "nvidia,tegra210-pcie";
20 device_type = "pci"; 19 device_type = "pci";
21 reg = <0x0 0x01003000 0x0 0x00 !! 20 reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */
22 <0x0 0x01003800 0x0 0x00 !! 21 0x0 0x01003800 0x0 0x00000800 /* AFI registers */
23 <0x0 0x02000000 0x0 0x10 !! 22 0x0 0x02000000 0x0 0x10000000>; /* configuration space */
24 reg-names = "pads", "afi", "cs 23 reg-names = "pads", "afi", "cs";
25 interrupts = <GIC_SPI 98 IRQ_T 24 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
26 <GIC_SPI 99 IRQ_T 25 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
27 interrupt-names = "intr", "msi 26 interrupt-names = "intr", "msi";
28 27
29 #interrupt-cells = <1>; 28 #interrupt-cells = <1>;
30 interrupt-map-mask = <0 0 0 0> 29 interrupt-map-mask = <0 0 0 0>;
31 interrupt-map = <0 0 0 0 &gic 30 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
32 31
33 bus-range = <0x00 0xff>; 32 bus-range = <0x00 0xff>;
34 #address-cells = <3>; 33 #address-cells = <3>;
35 #size-cells = <2>; 34 #size-cells = <2>;
36 35
37 ranges = <0x02000000 0 0x01000 !! 36 ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000 /* port 0 configuration space */
38 <0x02000000 0 0x01001 !! 37 0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000 /* port 1 configuration space */
39 <0x01000000 0 0x0 !! 38 0x81000000 0 0x0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */
40 <0x02000000 0 0x13000 !! 39 0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */
41 <0x42000000 0 0x20000 !! 40 0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
42 41
43 clocks = <&tegra_car TEGRA210_ 42 clocks = <&tegra_car TEGRA210_CLK_PCIE>,
44 <&tegra_car TEGRA210_ 43 <&tegra_car TEGRA210_CLK_AFI>,
45 <&tegra_car TEGRA210_ 44 <&tegra_car TEGRA210_CLK_PLL_E>,
46 <&tegra_car TEGRA210_ 45 <&tegra_car TEGRA210_CLK_CML0>;
47 clock-names = "pex", "afi", "p 46 clock-names = "pex", "afi", "pll_e", "cml";
48 resets = <&tegra_car 70>, 47 resets = <&tegra_car 70>,
49 <&tegra_car 72>, 48 <&tegra_car 72>,
50 <&tegra_car 74>; 49 <&tegra_car 74>;
51 reset-names = "pex", "afi", "p 50 reset-names = "pex", "afi", "pcie_x";
52 <<
53 pinctrl-names = "default", "id <<
54 pinctrl-0 = <&pex_dpd_disable> <<
55 pinctrl-1 = <&pex_dpd_enable>; <<
56 <<
57 status = "disabled"; 51 status = "disabled";
58 52
59 pci@1,0 { 53 pci@1,0 {
60 device_type = "pci"; 54 device_type = "pci";
61 assigned-addresses = < 55 assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
62 reg = <0x000800 0 0 0 56 reg = <0x000800 0 0 0 0>;
63 bus-range = <0x00 0xff 57 bus-range = <0x00 0xff>;
64 status = "disabled"; 58 status = "disabled";
65 59
66 #address-cells = <3>; 60 #address-cells = <3>;
67 #size-cells = <2>; 61 #size-cells = <2>;
68 ranges; 62 ranges;
69 63
70 nvidia,num-lanes = <4> 64 nvidia,num-lanes = <4>;
71 }; 65 };
72 66
73 pci@2,0 { 67 pci@2,0 {
74 device_type = "pci"; 68 device_type = "pci";
75 assigned-addresses = < 69 assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
76 reg = <0x001000 0 0 0 70 reg = <0x001000 0 0 0 0>;
77 bus-range = <0x00 0xff 71 bus-range = <0x00 0xff>;
78 status = "disabled"; 72 status = "disabled";
79 73
80 #address-cells = <3>; 74 #address-cells = <3>;
81 #size-cells = <2>; 75 #size-cells = <2>;
82 ranges; 76 ranges;
83 77
84 nvidia,num-lanes = <1> 78 nvidia,num-lanes = <1>;
85 }; 79 };
86 }; 80 };
87 81
88 host1x@50000000 { 82 host1x@50000000 {
89 compatible = "nvidia,tegra210- !! 83 compatible = "nvidia,tegra210-host1x", "simple-bus";
90 reg = <0x0 0x50000000 0x0 0x00 84 reg = <0x0 0x50000000 0x0 0x00034000>;
91 interrupts = <GIC_SPI 65 IRQ_T 85 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
92 <GIC_SPI 67 IRQ_T 86 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
93 interrupt-names = "syncpt", "h <<
94 clocks = <&tegra_car TEGRA210_ 87 clocks = <&tegra_car TEGRA210_CLK_HOST1X>;
95 clock-names = "host1x"; 88 clock-names = "host1x";
96 resets = <&tegra_car 28>, <&mc !! 89 resets = <&tegra_car 28>;
97 reset-names = "host1x", "mc"; !! 90 reset-names = "host1x";
98 91
99 #address-cells = <2>; 92 #address-cells = <2>;
100 #size-cells = <2>; 93 #size-cells = <2>;
101 94
102 ranges = <0x0 0x54000000 0x0 0 95 ranges = <0x0 0x54000000 0x0 0x54000000 0x0 0x01000000>;
103 96
104 iommus = <&mc TEGRA_SWGROUP_HC 97 iommus = <&mc TEGRA_SWGROUP_HC>;
105 98
106 dpaux1: dpaux@54040000 { 99 dpaux1: dpaux@54040000 {
107 compatible = "nvidia,t 100 compatible = "nvidia,tegra210-dpaux";
108 reg = <0x0 0x54040000 101 reg = <0x0 0x54040000 0x0 0x00040000>;
109 interrupts = <GIC_SPI 102 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
110 clocks = <&tegra_car T 103 clocks = <&tegra_car TEGRA210_CLK_DPAUX1>,
111 <&tegra_car T 104 <&tegra_car TEGRA210_CLK_PLL_DP>;
112 clock-names = "dpaux", 105 clock-names = "dpaux", "parent";
113 resets = <&tegra_car 2 106 resets = <&tegra_car 207>;
114 reset-names = "dpaux"; 107 reset-names = "dpaux";
115 power-domains = <&pd_s 108 power-domains = <&pd_sor>;
116 status = "disabled"; 109 status = "disabled";
117 110
118 state_dpaux1_aux: pinm 111 state_dpaux1_aux: pinmux-aux {
119 groups = "dpau 112 groups = "dpaux-io";
120 function = "au 113 function = "aux";
121 }; 114 };
122 115
123 state_dpaux1_i2c: pinm 116 state_dpaux1_i2c: pinmux-i2c {
124 groups = "dpau 117 groups = "dpaux-io";
125 function = "i2 118 function = "i2c";
126 }; 119 };
127 120
128 state_dpaux1_off: pinm 121 state_dpaux1_off: pinmux-off {
129 groups = "dpau 122 groups = "dpaux-io";
130 function = "of 123 function = "off";
131 }; 124 };
132 125
133 i2c-bus { 126 i2c-bus {
134 #address-cells 127 #address-cells = <1>;
135 #size-cells = 128 #size-cells = <0>;
136 }; 129 };
137 }; 130 };
138 131
139 vi@54080000 { 132 vi@54080000 {
140 compatible = "nvidia,t 133 compatible = "nvidia,tegra210-vi";
141 reg = <0x0 0x54080000 !! 134 reg = <0x0 0x54080000 0x0 0x00040000>;
142 interrupts = <GIC_SPI 135 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
143 status = "disabled"; 136 status = "disabled";
144 assigned-clocks = <&te <<
145 assigned-clock-parents <<
146 <<
147 clocks = <&tegra_car T <<
148 power-domains = <&pd_v <<
149 <<
150 #address-cells = <1>; <<
151 #size-cells = <1>; <<
152 <<
153 ranges = <0x0 0x0 0x54 <<
154 <<
155 csi@838 { <<
156 compatible = " <<
157 reg = <0x838 0 <<
158 status = "disa <<
159 assigned-clock <<
160 <<
161 <<
162 <<
163 assigned-clock <<
164 <<
165 <<
166 assigned-clock <<
167 <<
168 <<
169 <<
170 <<
171 clocks = <&teg <<
172 <&teg <<
173 <&teg <<
174 <&teg <<
175 <&teg <<
176 clock-names = <<
177 power-domains <<
178 }; <<
179 }; 137 };
180 138
181 tsec@54100000 { 139 tsec@54100000 {
182 compatible = "nvidia,t 140 compatible = "nvidia,tegra210-tsec";
183 reg = <0x0 0x54100000 141 reg = <0x0 0x54100000 0x0 0x00040000>;
184 interrupts = <GIC_SPI <<
185 clocks = <&tegra_car T <<
186 clock-names = "tsec"; <<
187 resets = <&tegra_car 8 <<
188 reset-names = "tsec"; <<
189 status = "disabled"; <<
190 }; 142 };
191 143
192 dc@54200000 { 144 dc@54200000 {
193 compatible = "nvidia,t 145 compatible = "nvidia,tegra210-dc";
194 reg = <0x0 0x54200000 146 reg = <0x0 0x54200000 0x0 0x00040000>;
195 interrupts = <GIC_SPI 147 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
196 clocks = <&tegra_car T !! 148 clocks = <&tegra_car TEGRA210_CLK_DISP1>,
197 clock-names = "dc"; !! 149 <&tegra_car TEGRA210_CLK_PLL_P>;
>> 150 clock-names = "dc", "parent";
198 resets = <&tegra_car 2 151 resets = <&tegra_car 27>;
199 reset-names = "dc"; 152 reset-names = "dc";
200 153
201 iommus = <&mc TEGRA_SW 154 iommus = <&mc TEGRA_SWGROUP_DC>;
202 155
203 nvidia,outputs = <&dsi <<
204 nvidia,head = <0>; 156 nvidia,head = <0>;
205 }; 157 };
206 158
207 dc@54240000 { 159 dc@54240000 {
208 compatible = "nvidia,t 160 compatible = "nvidia,tegra210-dc";
209 reg = <0x0 0x54240000 161 reg = <0x0 0x54240000 0x0 0x00040000>;
210 interrupts = <GIC_SPI 162 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
211 clocks = <&tegra_car T !! 163 clocks = <&tegra_car TEGRA210_CLK_DISP2>,
212 clock-names = "dc"; !! 164 <&tegra_car TEGRA210_CLK_PLL_P>;
>> 165 clock-names = "dc", "parent";
213 resets = <&tegra_car 2 166 resets = <&tegra_car 26>;
214 reset-names = "dc"; 167 reset-names = "dc";
215 168
216 iommus = <&mc TEGRA_SW 169 iommus = <&mc TEGRA_SWGROUP_DCB>;
217 170
218 nvidia,outputs = <&dsi <<
219 nvidia,head = <1>; 171 nvidia,head = <1>;
220 }; 172 };
221 173
222 dsia: dsi@54300000 { !! 174 dsi@54300000 {
223 compatible = "nvidia,t 175 compatible = "nvidia,tegra210-dsi";
224 reg = <0x0 0x54300000 176 reg = <0x0 0x54300000 0x0 0x00040000>;
225 clocks = <&tegra_car T 177 clocks = <&tegra_car TEGRA210_CLK_DSIA>,
226 <&tegra_car T 178 <&tegra_car TEGRA210_CLK_DSIALP>,
227 <&tegra_car T 179 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>;
228 clock-names = "dsi", " 180 clock-names = "dsi", "lp", "parent";
229 resets = <&tegra_car 4 181 resets = <&tegra_car 48>;
230 reset-names = "dsi"; 182 reset-names = "dsi";
231 power-domains = <&pd_s 183 power-domains = <&pd_sor>;
232 nvidia,mipi-calibrate 184 nvidia,mipi-calibrate = <&mipi 0x0c0>; /* DSIA & DSIB pads */
233 185
234 status = "disabled"; 186 status = "disabled";
235 187
236 #address-cells = <1>; 188 #address-cells = <1>;
237 #size-cells = <0>; 189 #size-cells = <0>;
238 }; 190 };
239 191
240 vic@54340000 { 192 vic@54340000 {
241 compatible = "nvidia,t 193 compatible = "nvidia,tegra210-vic";
242 reg = <0x0 0x54340000 194 reg = <0x0 0x54340000 0x0 0x00040000>;
243 interrupts = <GIC_SPI 195 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
244 clocks = <&tegra_car T 196 clocks = <&tegra_car TEGRA210_CLK_VIC03>;
245 clock-names = "vic"; 197 clock-names = "vic";
246 resets = <&tegra_car 1 198 resets = <&tegra_car 178>;
247 reset-names = "vic"; 199 reset-names = "vic";
248 200
249 iommus = <&mc TEGRA_SW 201 iommus = <&mc TEGRA_SWGROUP_VIC>;
250 power-domains = <&pd_v 202 power-domains = <&pd_vic>;
251 }; 203 };
252 204
253 nvjpg@54380000 { 205 nvjpg@54380000 {
254 compatible = "nvidia,t 206 compatible = "nvidia,tegra210-nvjpg";
255 reg = <0x0 0x54380000 207 reg = <0x0 0x54380000 0x0 0x00040000>;
256 status = "disabled"; 208 status = "disabled";
257 }; 209 };
258 210
259 dsib: dsi@54400000 { !! 211 dsi@54400000 {
260 compatible = "nvidia,t 212 compatible = "nvidia,tegra210-dsi";
261 reg = <0x0 0x54400000 213 reg = <0x0 0x54400000 0x0 0x00040000>;
262 clocks = <&tegra_car T 214 clocks = <&tegra_car TEGRA210_CLK_DSIB>,
263 <&tegra_car T 215 <&tegra_car TEGRA210_CLK_DSIBLP>,
264 <&tegra_car T 216 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>;
265 clock-names = "dsi", " 217 clock-names = "dsi", "lp", "parent";
266 resets = <&tegra_car 8 218 resets = <&tegra_car 82>;
267 reset-names = "dsi"; 219 reset-names = "dsi";
268 power-domains = <&pd_s 220 power-domains = <&pd_sor>;
269 nvidia,mipi-calibrate 221 nvidia,mipi-calibrate = <&mipi 0x300>; /* DSIC & DSID pads */
270 222
271 status = "disabled"; 223 status = "disabled";
272 224
273 #address-cells = <1>; 225 #address-cells = <1>;
274 #size-cells = <0>; 226 #size-cells = <0>;
275 }; 227 };
276 228
277 nvdec@54480000 { 229 nvdec@54480000 {
278 compatible = "nvidia,t 230 compatible = "nvidia,tegra210-nvdec";
279 reg = <0x0 0x54480000 231 reg = <0x0 0x54480000 0x0 0x00040000>;
280 status = "disabled"; 232 status = "disabled";
281 }; 233 };
282 234
283 nvenc@544c0000 { 235 nvenc@544c0000 {
284 compatible = "nvidia,t 236 compatible = "nvidia,tegra210-nvenc";
285 reg = <0x0 0x544c0000 237 reg = <0x0 0x544c0000 0x0 0x00040000>;
286 status = "disabled"; 238 status = "disabled";
287 }; 239 };
288 240
289 tsec@54500000 { 241 tsec@54500000 {
290 compatible = "nvidia,t 242 compatible = "nvidia,tegra210-tsec";
291 reg = <0x0 0x54500000 243 reg = <0x0 0x54500000 0x0 0x00040000>;
292 interrupts = <GIC_SPI <<
293 clocks = <&tegra_car T <<
294 clock-names = "tsec"; <<
295 resets = <&tegra_car 2 <<
296 reset-names = "tsec"; <<
297 status = "disabled"; 244 status = "disabled";
298 }; 245 };
299 246
300 sor0: sor@54540000 { !! 247 sor@54540000 {
301 compatible = "nvidia,t 248 compatible = "nvidia,tegra210-sor";
302 reg = <0x0 0x54540000 249 reg = <0x0 0x54540000 0x0 0x00040000>;
303 interrupts = <GIC_SPI 250 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
304 clocks = <&tegra_car T 251 clocks = <&tegra_car TEGRA210_CLK_SOR0>,
305 <&tegra_car T <<
306 <&tegra_car T 252 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>,
307 <&tegra_car T 253 <&tegra_car TEGRA210_CLK_PLL_DP>,
308 <&tegra_car T 254 <&tegra_car TEGRA210_CLK_SOR_SAFE>;
309 clock-names = "sor", " !! 255 clock-names = "sor", "parent", "dp", "safe";
310 resets = <&tegra_car 1 256 resets = <&tegra_car 182>;
311 reset-names = "sor"; 257 reset-names = "sor";
312 pinctrl-0 = <&state_dp 258 pinctrl-0 = <&state_dpaux_aux>;
313 pinctrl-1 = <&state_dp 259 pinctrl-1 = <&state_dpaux_i2c>;
314 pinctrl-2 = <&state_dp 260 pinctrl-2 = <&state_dpaux_off>;
315 pinctrl-names = "aux", 261 pinctrl-names = "aux", "i2c", "off";
316 power-domains = <&pd_s 262 power-domains = <&pd_sor>;
317 status = "disabled"; 263 status = "disabled";
318 }; 264 };
319 265
320 sor1: sor@54580000 { !! 266 sor@54580000 {
321 compatible = "nvidia,t 267 compatible = "nvidia,tegra210-sor1";
322 reg = <0x0 0x54580000 268 reg = <0x0 0x54580000 0x0 0x00040000>;
323 interrupts = <GIC_SPI 269 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
324 clocks = <&tegra_car T 270 clocks = <&tegra_car TEGRA210_CLK_SOR1>,
325 <&tegra_car T 271 <&tegra_car TEGRA210_CLK_SOR1_OUT>,
326 <&tegra_car T 272 <&tegra_car TEGRA210_CLK_PLL_D2_OUT0>,
327 <&tegra_car T 273 <&tegra_car TEGRA210_CLK_PLL_DP>,
328 <&tegra_car T 274 <&tegra_car TEGRA210_CLK_SOR_SAFE>;
329 clock-names = "sor", " 275 clock-names = "sor", "out", "parent", "dp", "safe";
330 resets = <&tegra_car 1 276 resets = <&tegra_car 183>;
331 reset-names = "sor"; 277 reset-names = "sor";
332 pinctrl-0 = <&state_dp 278 pinctrl-0 = <&state_dpaux1_aux>;
333 pinctrl-1 = <&state_dp 279 pinctrl-1 = <&state_dpaux1_i2c>;
334 pinctrl-2 = <&state_dp 280 pinctrl-2 = <&state_dpaux1_off>;
335 pinctrl-names = "aux", 281 pinctrl-names = "aux", "i2c", "off";
336 power-domains = <&pd_s 282 power-domains = <&pd_sor>;
337 status = "disabled"; 283 status = "disabled";
338 }; 284 };
339 285
340 dpaux: dpaux@545c0000 { 286 dpaux: dpaux@545c0000 {
341 compatible = "nvidia,t !! 287 compatible = "nvidia,tegra124-dpaux";
342 reg = <0x0 0x545c0000 288 reg = <0x0 0x545c0000 0x0 0x00040000>;
343 interrupts = <GIC_SPI 289 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
344 clocks = <&tegra_car T 290 clocks = <&tegra_car TEGRA210_CLK_DPAUX>,
345 <&tegra_car T 291 <&tegra_car TEGRA210_CLK_PLL_DP>;
346 clock-names = "dpaux", 292 clock-names = "dpaux", "parent";
347 resets = <&tegra_car 1 293 resets = <&tegra_car 181>;
348 reset-names = "dpaux"; 294 reset-names = "dpaux";
349 power-domains = <&pd_s 295 power-domains = <&pd_sor>;
350 status = "disabled"; 296 status = "disabled";
351 297
352 state_dpaux_aux: pinmu 298 state_dpaux_aux: pinmux-aux {
353 groups = "dpau 299 groups = "dpaux-io";
354 function = "au 300 function = "aux";
355 }; 301 };
356 302
357 state_dpaux_i2c: pinmu 303 state_dpaux_i2c: pinmux-i2c {
358 groups = "dpau 304 groups = "dpaux-io";
359 function = "i2 305 function = "i2c";
360 }; 306 };
361 307
362 state_dpaux_off: pinmu 308 state_dpaux_off: pinmux-off {
363 groups = "dpau 309 groups = "dpaux-io";
364 function = "of 310 function = "off";
365 }; 311 };
366 312
367 i2c-bus { 313 i2c-bus {
368 #address-cells 314 #address-cells = <1>;
369 #size-cells = 315 #size-cells = <0>;
370 }; 316 };
371 }; 317 };
372 318
373 isp@54600000 { 319 isp@54600000 {
374 compatible = "nvidia,t 320 compatible = "nvidia,tegra210-isp";
375 reg = <0x0 0x54600000 321 reg = <0x0 0x54600000 0x0 0x00040000>;
376 interrupts = <GIC_SPI 322 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
377 clocks = <&tegra_car T <<
378 resets = <&tegra_car 2 <<
379 reset-names = "isp"; <<
380 status = "disabled"; 323 status = "disabled";
381 }; 324 };
382 325
383 isp@54680000 { 326 isp@54680000 {
384 compatible = "nvidia,t 327 compatible = "nvidia,tegra210-isp";
385 reg = <0x0 0x54680000 328 reg = <0x0 0x54680000 0x0 0x00040000>;
386 interrupts = <GIC_SPI 329 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
387 clocks = <&tegra_car T <<
388 resets = <&tegra_car 3 <<
389 reset-names = "isp"; <<
390 status = "disabled"; 330 status = "disabled";
391 }; 331 };
392 332
393 i2c@546c0000 { 333 i2c@546c0000 {
394 compatible = "nvidia,t 334 compatible = "nvidia,tegra210-i2c-vi";
395 reg = <0x0 0x546c0000 335 reg = <0x0 0x546c0000 0x0 0x00040000>;
396 interrupts = <GIC_SPI 336 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
397 clocks = <&tegra_car T <<
398 <&tegra_car T <<
399 clock-names = "div-clk <<
400 resets = <&tegra_car 2 <<
401 reset-names = "i2c"; <<
402 power-domains = <&pd_v <<
403 status = "disabled"; 337 status = "disabled";
404 <<
405 #address-cells = <1>; <<
406 #size-cells = <0>; <<
407 }; 338 };
408 }; 339 };
409 340
410 gic: interrupt-controller@50041000 { 341 gic: interrupt-controller@50041000 {
411 compatible = "arm,gic-400"; 342 compatible = "arm,gic-400";
412 #interrupt-cells = <3>; 343 #interrupt-cells = <3>;
413 interrupt-controller; 344 interrupt-controller;
414 reg = <0x0 0x50041000 0x0 0x10 345 reg = <0x0 0x50041000 0x0 0x1000>,
415 <0x0 0x50042000 0x0 0x20 346 <0x0 0x50042000 0x0 0x2000>,
416 <0x0 0x50044000 0x0 0x20 347 <0x0 0x50044000 0x0 0x2000>,
417 <0x0 0x50046000 0x0 0x20 348 <0x0 0x50046000 0x0 0x2000>;
418 interrupts = <GIC_PPI 9 349 interrupts = <GIC_PPI 9
419 (GIC_CPU_MASK_SIMPLE(4 350 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
420 interrupt-parent = <&gic>; 351 interrupt-parent = <&gic>;
421 }; 352 };
422 353
423 gpu@57000000 { 354 gpu@57000000 {
424 compatible = "nvidia,gm20b"; 355 compatible = "nvidia,gm20b";
425 reg = <0x0 0x57000000 0x0 0x01 356 reg = <0x0 0x57000000 0x0 0x01000000>,
426 <0x0 0x58000000 0x0 0x01 357 <0x0 0x58000000 0x0 0x01000000>;
427 interrupts = <GIC_SPI 157 IRQ_ 358 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
428 <GIC_SPI 158 IRQ_ 359 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
429 interrupt-names = "stall", "no 360 interrupt-names = "stall", "nonstall";
430 clocks = <&tegra_car TEGRA210_ 361 clocks = <&tegra_car TEGRA210_CLK_GPU>,
431 <&tegra_car TEGRA210_ 362 <&tegra_car TEGRA210_CLK_PLL_P_OUT5>,
432 <&tegra_car TEGRA210_ 363 <&tegra_car TEGRA210_CLK_PLL_G_REF>;
433 clock-names = "gpu", "pwr", "r 364 clock-names = "gpu", "pwr", "ref";
434 resets = <&tegra_car 184>; 365 resets = <&tegra_car 184>;
435 reset-names = "gpu"; 366 reset-names = "gpu";
436 367
437 iommus = <&mc TEGRA_SWGROUP_GP 368 iommus = <&mc TEGRA_SWGROUP_GPU>;
438 369
439 status = "disabled"; 370 status = "disabled";
440 }; 371 };
441 372
442 lic: interrupt-controller@60004000 { 373 lic: interrupt-controller@60004000 {
443 compatible = "nvidia,tegra210- 374 compatible = "nvidia,tegra210-ictlr";
444 reg = <0x0 0x60004000 0x0 0x40 375 reg = <0x0 0x60004000 0x0 0x40>, /* primary controller */
445 <0x0 0x60004100 0x0 0x40 376 <0x0 0x60004100 0x0 0x40>, /* secondary controller */
446 <0x0 0x60004200 0x0 0x40 377 <0x0 0x60004200 0x0 0x40>, /* tertiary controller */
447 <0x0 0x60004300 0x0 0x40 378 <0x0 0x60004300 0x0 0x40>, /* quaternary controller */
448 <0x0 0x60004400 0x0 0x40 379 <0x0 0x60004400 0x0 0x40>, /* quinary controller */
449 <0x0 0x60004500 0x0 0x40 380 <0x0 0x60004500 0x0 0x40>; /* senary controller */
450 interrupt-controller; 381 interrupt-controller;
451 #interrupt-cells = <3>; 382 #interrupt-cells = <3>;
452 interrupt-parent = <&gic>; 383 interrupt-parent = <&gic>;
453 }; 384 };
454 385
455 timer@60005000 { 386 timer@60005000 {
456 compatible = "nvidia,tegra210- !! 387 compatible = "nvidia,tegra210-timer", "nvidia,tegra20-timer";
457 reg = <0x0 0x60005000 0x0 0x40 388 reg = <0x0 0x60005000 0x0 0x400>;
458 interrupts = <GIC_SPI 156 IRQ_ !! 389 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
459 <GIC_SPI 0 IRQ_TY <<
460 <GIC_SPI 1 IRQ_TY 390 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
461 <GIC_SPI 41 IRQ_T 391 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
462 <GIC_SPI 42 IRQ_T 392 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
463 <GIC_SPI 121 IRQ_ 393 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
464 <GIC_SPI 152 IRQ_ !! 394 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
465 <GIC_SPI 153 IRQ_ <<
466 <GIC_SPI 154 IRQ_ <<
467 <GIC_SPI 155 IRQ_ <<
468 <GIC_SPI 176 IRQ_ <<
469 <GIC_SPI 177 IRQ_ <<
470 <GIC_SPI 178 IRQ_ <<
471 <GIC_SPI 179 IRQ_ <<
472 clocks = <&tegra_car TEGRA210_ 395 clocks = <&tegra_car TEGRA210_CLK_TIMER>;
473 clock-names = "timer"; 396 clock-names = "timer";
474 }; 397 };
475 398
476 tegra_car: clock@60006000 { 399 tegra_car: clock@60006000 {
477 compatible = "nvidia,tegra210- 400 compatible = "nvidia,tegra210-car";
478 reg = <0x0 0x60006000 0x0 0x10 401 reg = <0x0 0x60006000 0x0 0x1000>;
479 #clock-cells = <1>; 402 #clock-cells = <1>;
480 #reset-cells = <1>; 403 #reset-cells = <1>;
481 }; 404 };
482 405
483 flow-controller@60007000 { 406 flow-controller@60007000 {
484 compatible = "nvidia,tegra210- 407 compatible = "nvidia,tegra210-flowctrl";
485 reg = <0x0 0x60007000 0x0 0x10 408 reg = <0x0 0x60007000 0x0 0x1000>;
486 }; 409 };
487 410
488 gpio: gpio@6000d000 { 411 gpio: gpio@6000d000 {
489 compatible = "nvidia,tegra210- 412 compatible = "nvidia,tegra210-gpio", "nvidia,tegra30-gpio";
490 reg = <0x0 0x6000d000 0x0 0x10 413 reg = <0x0 0x6000d000 0x0 0x1000>;
491 interrupts = <GIC_SPI 32 IRQ_T 414 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
492 <GIC_SPI 33 IRQ_T 415 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
493 <GIC_SPI 34 IRQ_T 416 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
494 <GIC_SPI 35 IRQ_T 417 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
495 <GIC_SPI 55 IRQ_T 418 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
496 <GIC_SPI 87 IRQ_T 419 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
497 <GIC_SPI 89 IRQ_T 420 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
498 <GIC_SPI 125 IRQ_ 421 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
499 #gpio-cells = <2>; 422 #gpio-cells = <2>;
500 gpio-controller; 423 gpio-controller;
501 #interrupt-cells = <2>; 424 #interrupt-cells = <2>;
502 interrupt-controller; 425 interrupt-controller;
503 }; 426 };
504 427
505 apbdma: dma@60020000 { 428 apbdma: dma@60020000 {
506 compatible = "nvidia,tegra210- 429 compatible = "nvidia,tegra210-apbdma", "nvidia,tegra148-apbdma";
507 reg = <0x0 0x60020000 0x0 0x14 430 reg = <0x0 0x60020000 0x0 0x1400>;
508 interrupts = <GIC_SPI 104 IRQ_ 431 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
509 <GIC_SPI 105 IRQ_ 432 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
510 <GIC_SPI 106 IRQ_ 433 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
511 <GIC_SPI 107 IRQ_ 434 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
512 <GIC_SPI 108 IRQ_ 435 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
513 <GIC_SPI 109 IRQ_ 436 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
514 <GIC_SPI 110 IRQ_ 437 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
515 <GIC_SPI 111 IRQ_ 438 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
516 <GIC_SPI 112 IRQ_ 439 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
517 <GIC_SPI 113 IRQ_ 440 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
518 <GIC_SPI 114 IRQ_ 441 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
519 <GIC_SPI 115 IRQ_ 442 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
520 <GIC_SPI 116 IRQ_ 443 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
521 <GIC_SPI 117 IRQ_ 444 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
522 <GIC_SPI 118 IRQ_ 445 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
523 <GIC_SPI 119 IRQ_ 446 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
524 <GIC_SPI 128 IRQ_ 447 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
525 <GIC_SPI 129 IRQ_ 448 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
526 <GIC_SPI 130 IRQ_ 449 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
527 <GIC_SPI 131 IRQ_ 450 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
528 <GIC_SPI 132 IRQ_ 451 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
529 <GIC_SPI 133 IRQ_ 452 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
530 <GIC_SPI 134 IRQ_ 453 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
531 <GIC_SPI 135 IRQ_ 454 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
532 <GIC_SPI 136 IRQ_ 455 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
533 <GIC_SPI 137 IRQ_ 456 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
534 <GIC_SPI 138 IRQ_ 457 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
535 <GIC_SPI 139 IRQ_ 458 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
536 <GIC_SPI 140 IRQ_ 459 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
537 <GIC_SPI 141 IRQ_ 460 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
538 <GIC_SPI 142 IRQ_ 461 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
539 <GIC_SPI 143 IRQ_ 462 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
540 clocks = <&tegra_car TEGRA210_ 463 clocks = <&tegra_car TEGRA210_CLK_APBDMA>;
541 clock-names = "dma"; 464 clock-names = "dma";
542 resets = <&tegra_car 34>; 465 resets = <&tegra_car 34>;
543 reset-names = "dma"; 466 reset-names = "dma";
544 #dma-cells = <1>; 467 #dma-cells = <1>;
545 }; 468 };
546 469
547 apbmisc@70000800 { 470 apbmisc@70000800 {
548 compatible = "nvidia,tegra210- 471 compatible = "nvidia,tegra210-apbmisc", "nvidia,tegra20-apbmisc";
549 reg = <0x0 0x70000800 0x0 0x64 472 reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */
550 <0x0 0x70000008 0x0 0x04 473 <0x0 0x70000008 0x0 0x04>; /* Strapping options */
551 }; 474 };
552 475
553 pinmux: pinmux@700008d4 { 476 pinmux: pinmux@700008d4 {
554 compatible = "nvidia,tegra210- 477 compatible = "nvidia,tegra210-pinmux";
555 reg = <0x0 0x700008d4 0x0 0x29 478 reg = <0x0 0x700008d4 0x0 0x29c>, /* Pad control registers */
556 <0x0 0x70003000 0x0 0x29 479 <0x0 0x70003000 0x0 0x294>; /* Mux registers */
557 !! 480 sdmmc1_3v3_drv: sdmmc1-3v3-drv {
558 sdmmc1_1v8_drv: pinmux-sdmmc1- <<
559 sdmmc1 { 481 sdmmc1 {
560 nvidia,pins = 482 nvidia,pins = "drive_sdmmc1";
561 nvidia,pull-do !! 483 nvidia,pull-down-strength = <0x8>;
562 nvidia,pull-up !! 484 nvidia,pull-up-strength = <0x8>;
563 }; 485 };
564 }; 486 };
565 !! 487 sdmmc1_1v8_drv: sdmmc1-1v8-drv {
566 sdmmc1_3v3_drv: pinmux-sdmmc1- <<
567 sdmmc1 { 488 sdmmc1 {
568 nvidia,pins = 489 nvidia,pins = "drive_sdmmc1";
569 nvidia,pull-do !! 490 nvidia,pull-down-strength = <0x4>;
570 nvidia,pull-up !! 491 nvidia,pull-up-strength = <0x3>;
571 }; 492 };
572 }; 493 };
573 !! 494 sdmmc2_1v8_drv: sdmmc2-1v8-drv {
574 sdmmc2_1v8_drv: pinmux-sdmmc2- <<
575 sdmmc2 { 495 sdmmc2 {
576 nvidia,pins = 496 nvidia,pins = "drive_sdmmc2";
577 nvidia,pull-do 497 nvidia,pull-down-strength = <0x10>;
578 nvidia,pull-up 498 nvidia,pull-up-strength = <0x10>;
579 }; 499 };
580 }; 500 };
581 !! 501 sdmmc3_3v3_drv: sdmmc3-3v3-drv {
582 sdmmc3_1v8_drv: pinmux-sdmmc3- <<
583 sdmmc3 { 502 sdmmc3 {
584 nvidia,pins = 503 nvidia,pins = "drive_sdmmc3";
585 nvidia,pull-do !! 504 nvidia,pull-down-strength = <0x8>;
586 nvidia,pull-up !! 505 nvidia,pull-up-strength = <0x8>;
587 }; 506 };
588 }; 507 };
589 !! 508 sdmmc3_1v8_drv: sdmmc3-1v8-drv {
590 sdmmc3_3v3_drv: pinmux-sdmmc3- <<
591 sdmmc3 { 509 sdmmc3 {
592 nvidia,pins = 510 nvidia,pins = "drive_sdmmc3";
593 nvidia,pull-do !! 511 nvidia,pull-down-strength = <0x4>;
594 nvidia,pull-up !! 512 nvidia,pull-up-strength = <0x3>;
595 }; 513 };
596 }; 514 };
597 !! 515 sdmmc4_1v8_drv: sdmmc4-1v8-drv {
598 sdmmc4_1v8_drv: pinmux-sdmmc4- <<
599 sdmmc4 { 516 sdmmc4 {
600 nvidia,pins = 517 nvidia,pins = "drive_sdmmc4";
601 nvidia,pull-do 518 nvidia,pull-down-strength = <0x10>;
602 nvidia,pull-up 519 nvidia,pull-up-strength = <0x10>;
603 }; 520 };
604 }; 521 };
605 }; 522 };
606 523
607 /* 524 /*
608 * There are two serial driver i.e. 82 525 * There are two serial driver i.e. 8250 based simple serial
609 * driver and APB DMA based serial dri 526 * driver and APB DMA based serial driver for higher baudrate
610 * and performance. To enable the 8250 527 * and performance. To enable the 8250 based driver, the compatible
611 * is "nvidia,tegra124-uart", "nvidia, 528 * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable
612 * the APB DMA based serial driver, th 529 * the APB DMA based serial driver, the compatible is
613 * "nvidia,tegra124-hsuart", "nvidia,t 530 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart".
614 */ 531 */
615 uarta: serial@70006000 { 532 uarta: serial@70006000 {
616 compatible = "nvidia,tegra210- 533 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
617 reg = <0x0 0x70006000 0x0 0x40 534 reg = <0x0 0x70006000 0x0 0x40>;
618 reg-shift = <2>; 535 reg-shift = <2>;
619 interrupts = <GIC_SPI 36 IRQ_T 536 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
620 clocks = <&tegra_car TEGRA210_ 537 clocks = <&tegra_car TEGRA210_CLK_UARTA>;
>> 538 clock-names = "serial";
621 resets = <&tegra_car 6>; 539 resets = <&tegra_car 6>;
>> 540 reset-names = "serial";
622 dmas = <&apbdma 8>, <&apbdma 8 541 dmas = <&apbdma 8>, <&apbdma 8>;
623 dma-names = "rx", "tx"; 542 dma-names = "rx", "tx";
624 status = "disabled"; 543 status = "disabled";
625 }; 544 };
626 545
627 uartb: serial@70006040 { 546 uartb: serial@70006040 {
628 compatible = "nvidia,tegra210- 547 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
629 reg = <0x0 0x70006040 0x0 0x40 548 reg = <0x0 0x70006040 0x0 0x40>;
630 reg-shift = <2>; 549 reg-shift = <2>;
631 interrupts = <GIC_SPI 37 IRQ_T 550 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
632 clocks = <&tegra_car TEGRA210_ 551 clocks = <&tegra_car TEGRA210_CLK_UARTB>;
>> 552 clock-names = "serial";
633 resets = <&tegra_car 7>; 553 resets = <&tegra_car 7>;
>> 554 reset-names = "serial";
634 dmas = <&apbdma 9>, <&apbdma 9 555 dmas = <&apbdma 9>, <&apbdma 9>;
635 dma-names = "rx", "tx"; 556 dma-names = "rx", "tx";
636 status = "disabled"; 557 status = "disabled";
637 }; 558 };
638 559
639 uartc: serial@70006200 { 560 uartc: serial@70006200 {
640 compatible = "nvidia,tegra210- 561 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
641 reg = <0x0 0x70006200 0x0 0x40 562 reg = <0x0 0x70006200 0x0 0x40>;
642 reg-shift = <2>; 563 reg-shift = <2>;
643 interrupts = <GIC_SPI 46 IRQ_T 564 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
644 clocks = <&tegra_car TEGRA210_ 565 clocks = <&tegra_car TEGRA210_CLK_UARTC>;
>> 566 clock-names = "serial";
645 resets = <&tegra_car 55>; 567 resets = <&tegra_car 55>;
>> 568 reset-names = "serial";
646 dmas = <&apbdma 10>, <&apbdma 569 dmas = <&apbdma 10>, <&apbdma 10>;
647 dma-names = "rx", "tx"; 570 dma-names = "rx", "tx";
648 status = "disabled"; 571 status = "disabled";
649 }; 572 };
650 573
651 uartd: serial@70006300 { 574 uartd: serial@70006300 {
652 compatible = "nvidia,tegra210- 575 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
653 reg = <0x0 0x70006300 0x0 0x40 576 reg = <0x0 0x70006300 0x0 0x40>;
654 reg-shift = <2>; 577 reg-shift = <2>;
655 interrupts = <GIC_SPI 90 IRQ_T 578 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
656 clocks = <&tegra_car TEGRA210_ 579 clocks = <&tegra_car TEGRA210_CLK_UARTD>;
>> 580 clock-names = "serial";
657 resets = <&tegra_car 65>; 581 resets = <&tegra_car 65>;
>> 582 reset-names = "serial";
658 dmas = <&apbdma 19>, <&apbdma 583 dmas = <&apbdma 19>, <&apbdma 19>;
659 dma-names = "rx", "tx"; 584 dma-names = "rx", "tx";
660 status = "disabled"; 585 status = "disabled";
661 }; 586 };
662 587
663 pwm: pwm@7000a000 { 588 pwm: pwm@7000a000 {
664 compatible = "nvidia,tegra210- 589 compatible = "nvidia,tegra210-pwm", "nvidia,tegra20-pwm";
665 reg = <0x0 0x7000a000 0x0 0x10 590 reg = <0x0 0x7000a000 0x0 0x100>;
666 #pwm-cells = <2>; 591 #pwm-cells = <2>;
667 clocks = <&tegra_car TEGRA210_ 592 clocks = <&tegra_car TEGRA210_CLK_PWM>;
>> 593 clock-names = "pwm";
668 resets = <&tegra_car 17>; 594 resets = <&tegra_car 17>;
669 reset-names = "pwm"; 595 reset-names = "pwm";
670 status = "disabled"; 596 status = "disabled";
671 }; 597 };
672 598
673 i2c@7000c000 { 599 i2c@7000c000 {
674 compatible = "nvidia,tegra210- 600 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c";
675 reg = <0x0 0x7000c000 0x0 0x10 601 reg = <0x0 0x7000c000 0x0 0x100>;
676 interrupts = <GIC_SPI 38 IRQ_T 602 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
677 #address-cells = <1>; 603 #address-cells = <1>;
678 #size-cells = <0>; 604 #size-cells = <0>;
679 clocks = <&tegra_car TEGRA210_ 605 clocks = <&tegra_car TEGRA210_CLK_I2C1>;
680 clock-names = "div-clk"; 606 clock-names = "div-clk";
681 resets = <&tegra_car 12>; 607 resets = <&tegra_car 12>;
682 reset-names = "i2c"; 608 reset-names = "i2c";
683 dmas = <&apbdma 21>, <&apbdma 609 dmas = <&apbdma 21>, <&apbdma 21>;
684 dma-names = "rx", "tx"; 610 dma-names = "rx", "tx";
685 status = "disabled"; 611 status = "disabled";
686 }; 612 };
687 613
688 i2c@7000c400 { 614 i2c@7000c400 {
689 compatible = "nvidia,tegra210- 615 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c";
690 reg = <0x0 0x7000c400 0x0 0x10 616 reg = <0x0 0x7000c400 0x0 0x100>;
691 interrupts = <GIC_SPI 84 IRQ_T 617 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
692 #address-cells = <1>; 618 #address-cells = <1>;
693 #size-cells = <0>; 619 #size-cells = <0>;
694 clocks = <&tegra_car TEGRA210_ 620 clocks = <&tegra_car TEGRA210_CLK_I2C2>;
695 clock-names = "div-clk"; 621 clock-names = "div-clk";
696 resets = <&tegra_car 54>; 622 resets = <&tegra_car 54>;
697 reset-names = "i2c"; 623 reset-names = "i2c";
698 dmas = <&apbdma 22>, <&apbdma 624 dmas = <&apbdma 22>, <&apbdma 22>;
699 dma-names = "rx", "tx"; 625 dma-names = "rx", "tx";
700 status = "disabled"; 626 status = "disabled";
701 }; 627 };
702 628
703 i2c@7000c500 { 629 i2c@7000c500 {
704 compatible = "nvidia,tegra210- 630 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c";
705 reg = <0x0 0x7000c500 0x0 0x10 631 reg = <0x0 0x7000c500 0x0 0x100>;
706 interrupts = <GIC_SPI 92 IRQ_T 632 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
707 #address-cells = <1>; 633 #address-cells = <1>;
708 #size-cells = <0>; 634 #size-cells = <0>;
709 clocks = <&tegra_car TEGRA210_ 635 clocks = <&tegra_car TEGRA210_CLK_I2C3>;
710 clock-names = "div-clk"; 636 clock-names = "div-clk";
711 resets = <&tegra_car 67>; 637 resets = <&tegra_car 67>;
712 reset-names = "i2c"; 638 reset-names = "i2c";
713 dmas = <&apbdma 23>, <&apbdma 639 dmas = <&apbdma 23>, <&apbdma 23>;
714 dma-names = "rx", "tx"; 640 dma-names = "rx", "tx";
715 status = "disabled"; 641 status = "disabled";
716 }; 642 };
717 643
718 i2c@7000c700 { 644 i2c@7000c700 {
719 compatible = "nvidia,tegra210- 645 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c";
720 reg = <0x0 0x7000c700 0x0 0x10 646 reg = <0x0 0x7000c700 0x0 0x100>;
721 interrupts = <GIC_SPI 120 IRQ_ 647 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
722 #address-cells = <1>; 648 #address-cells = <1>;
723 #size-cells = <0>; 649 #size-cells = <0>;
724 clocks = <&tegra_car TEGRA210_ 650 clocks = <&tegra_car TEGRA210_CLK_I2C4>;
725 clock-names = "div-clk"; 651 clock-names = "div-clk";
726 resets = <&tegra_car 103>; 652 resets = <&tegra_car 103>;
727 reset-names = "i2c"; 653 reset-names = "i2c";
728 dmas = <&apbdma 26>, <&apbdma 654 dmas = <&apbdma 26>, <&apbdma 26>;
729 dma-names = "rx", "tx"; 655 dma-names = "rx", "tx";
730 pinctrl-0 = <&state_dpaux1_i2c 656 pinctrl-0 = <&state_dpaux1_i2c>;
731 pinctrl-1 = <&state_dpaux1_off 657 pinctrl-1 = <&state_dpaux1_off>;
732 pinctrl-names = "default", "id 658 pinctrl-names = "default", "idle";
733 status = "disabled"; 659 status = "disabled";
734 }; 660 };
735 661
736 i2c@7000d000 { 662 i2c@7000d000 {
737 compatible = "nvidia,tegra210- 663 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c";
738 reg = <0x0 0x7000d000 0x0 0x10 664 reg = <0x0 0x7000d000 0x0 0x100>;
739 interrupts = <GIC_SPI 53 IRQ_T 665 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
740 #address-cells = <1>; 666 #address-cells = <1>;
741 #size-cells = <0>; 667 #size-cells = <0>;
742 clocks = <&tegra_car TEGRA210_ 668 clocks = <&tegra_car TEGRA210_CLK_I2C5>;
743 clock-names = "div-clk"; 669 clock-names = "div-clk";
744 resets = <&tegra_car 47>; 670 resets = <&tegra_car 47>;
745 reset-names = "i2c"; 671 reset-names = "i2c";
746 dmas = <&apbdma 24>, <&apbdma 672 dmas = <&apbdma 24>, <&apbdma 24>;
747 dma-names = "rx", "tx"; 673 dma-names = "rx", "tx";
748 status = "disabled"; 674 status = "disabled";
749 }; 675 };
750 676
751 i2c@7000d100 { 677 i2c@7000d100 {
752 compatible = "nvidia,tegra210- 678 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c";
753 reg = <0x0 0x7000d100 0x0 0x10 679 reg = <0x0 0x7000d100 0x0 0x100>;
754 interrupts = <GIC_SPI 63 IRQ_T 680 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
755 #address-cells = <1>; 681 #address-cells = <1>;
756 #size-cells = <0>; 682 #size-cells = <0>;
757 clocks = <&tegra_car TEGRA210_ 683 clocks = <&tegra_car TEGRA210_CLK_I2C6>;
758 clock-names = "div-clk"; 684 clock-names = "div-clk";
759 resets = <&tegra_car 166>; 685 resets = <&tegra_car 166>;
760 reset-names = "i2c"; 686 reset-names = "i2c";
761 dmas = <&apbdma 30>, <&apbdma 687 dmas = <&apbdma 30>, <&apbdma 30>;
762 dma-names = "rx", "tx"; 688 dma-names = "rx", "tx";
763 pinctrl-0 = <&state_dpaux_i2c> 689 pinctrl-0 = <&state_dpaux_i2c>;
764 pinctrl-1 = <&state_dpaux_off> 690 pinctrl-1 = <&state_dpaux_off>;
765 pinctrl-names = "default", "id 691 pinctrl-names = "default", "idle";
766 status = "disabled"; 692 status = "disabled";
767 }; 693 };
768 694
769 spi@7000d400 { 695 spi@7000d400 {
770 compatible = "nvidia,tegra210- 696 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
771 reg = <0x0 0x7000d400 0x0 0x20 697 reg = <0x0 0x7000d400 0x0 0x200>;
772 interrupts = <GIC_SPI 59 IRQ_T 698 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
773 #address-cells = <1>; 699 #address-cells = <1>;
774 #size-cells = <0>; 700 #size-cells = <0>;
775 clocks = <&tegra_car TEGRA210_ 701 clocks = <&tegra_car TEGRA210_CLK_SBC1>;
776 clock-names = "spi"; 702 clock-names = "spi";
777 resets = <&tegra_car 41>; 703 resets = <&tegra_car 41>;
778 reset-names = "spi"; 704 reset-names = "spi";
779 dmas = <&apbdma 15>, <&apbdma 705 dmas = <&apbdma 15>, <&apbdma 15>;
780 dma-names = "rx", "tx"; 706 dma-names = "rx", "tx";
781 status = "disabled"; 707 status = "disabled";
782 }; 708 };
783 709
784 spi@7000d600 { 710 spi@7000d600 {
785 compatible = "nvidia,tegra210- 711 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
786 reg = <0x0 0x7000d600 0x0 0x20 712 reg = <0x0 0x7000d600 0x0 0x200>;
787 interrupts = <GIC_SPI 82 IRQ_T 713 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
788 #address-cells = <1>; 714 #address-cells = <1>;
789 #size-cells = <0>; 715 #size-cells = <0>;
790 clocks = <&tegra_car TEGRA210_ 716 clocks = <&tegra_car TEGRA210_CLK_SBC2>;
791 clock-names = "spi"; 717 clock-names = "spi";
792 resets = <&tegra_car 44>; 718 resets = <&tegra_car 44>;
793 reset-names = "spi"; 719 reset-names = "spi";
794 dmas = <&apbdma 16>, <&apbdma 720 dmas = <&apbdma 16>, <&apbdma 16>;
795 dma-names = "rx", "tx"; 721 dma-names = "rx", "tx";
796 status = "disabled"; 722 status = "disabled";
797 }; 723 };
798 724
799 spi@7000d800 { 725 spi@7000d800 {
800 compatible = "nvidia,tegra210- 726 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
801 reg = <0x0 0x7000d800 0x0 0x20 727 reg = <0x0 0x7000d800 0x0 0x200>;
802 interrupts = <GIC_SPI 83 IRQ_T 728 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
803 #address-cells = <1>; 729 #address-cells = <1>;
804 #size-cells = <0>; 730 #size-cells = <0>;
805 clocks = <&tegra_car TEGRA210_ 731 clocks = <&tegra_car TEGRA210_CLK_SBC3>;
806 clock-names = "spi"; 732 clock-names = "spi";
807 resets = <&tegra_car 46>; 733 resets = <&tegra_car 46>;
808 reset-names = "spi"; 734 reset-names = "spi";
809 dmas = <&apbdma 17>, <&apbdma 735 dmas = <&apbdma 17>, <&apbdma 17>;
810 dma-names = "rx", "tx"; 736 dma-names = "rx", "tx";
811 status = "disabled"; 737 status = "disabled";
812 }; 738 };
813 739
814 spi@7000da00 { 740 spi@7000da00 {
815 compatible = "nvidia,tegra210- 741 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
816 reg = <0x0 0x7000da00 0x0 0x20 742 reg = <0x0 0x7000da00 0x0 0x200>;
817 interrupts = <GIC_SPI 93 IRQ_T 743 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
818 #address-cells = <1>; 744 #address-cells = <1>;
819 #size-cells = <0>; 745 #size-cells = <0>;
820 clocks = <&tegra_car TEGRA210_ 746 clocks = <&tegra_car TEGRA210_CLK_SBC4>;
821 clock-names = "spi"; 747 clock-names = "spi";
822 resets = <&tegra_car 68>; 748 resets = <&tegra_car 68>;
823 reset-names = "spi"; 749 reset-names = "spi";
824 dmas = <&apbdma 18>, <&apbdma 750 dmas = <&apbdma 18>, <&apbdma 18>;
825 dma-names = "rx", "tx"; 751 dma-names = "rx", "tx";
826 status = "disabled"; 752 status = "disabled";
827 }; 753 };
828 754
829 rtc@7000e000 { 755 rtc@7000e000 {
830 compatible = "nvidia,tegra210- 756 compatible = "nvidia,tegra210-rtc", "nvidia,tegra20-rtc";
831 reg = <0x0 0x7000e000 0x0 0x10 757 reg = <0x0 0x7000e000 0x0 0x100>;
832 interrupts = <16 IRQ_TYPE_LEVE !! 758 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
833 interrupt-parent = <&tegra_pmc <<
834 clocks = <&tegra_car TEGRA210_ 759 clocks = <&tegra_car TEGRA210_CLK_RTC>;
835 clock-names = "rtc"; 760 clock-names = "rtc";
836 }; 761 };
837 762
838 tegra_pmc: pmc@7000e400 { !! 763 pmc: pmc@7000e400 {
839 compatible = "nvidia,tegra210- 764 compatible = "nvidia,tegra210-pmc";
840 reg = <0x0 0x7000e400 0x0 0x40 765 reg = <0x0 0x7000e400 0x0 0x400>;
841 clocks = <&tegra_car TEGRA210_ 766 clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>;
842 clock-names = "pclk", "clk32k_ 767 clock-names = "pclk", "clk32k_in";
843 #clock-cells = <1>; <<
844 #interrupt-cells = <2>; <<
845 interrupt-controller; <<
846 <<
847 pinmux { <<
848 pex_dpd_disable: pex-d <<
849 pins = "pex-bi <<
850 low-power-disa <<
851 }; <<
852 <<
853 pex_dpd_enable: pex-dp <<
854 pins = "pex-bi <<
855 low-power-enab <<
856 }; <<
857 <<
858 sdmmc1_1v8: sdmmc1-1v8 <<
859 pins = "sdmmc1 <<
860 power-source = <<
861 }; <<
862 <<
863 sdmmc1_3v3: sdmmc1-3v3 <<
864 pins = "sdmmc1 <<
865 power-source = <<
866 }; <<
867 <<
868 sdmmc3_1v8: sdmmc3-1v8 <<
869 pins = "sdmmc3 <<
870 power-source = <<
871 }; <<
872 <<
873 sdmmc3_3v3: sdmmc3-3v3 <<
874 pins = "sdmmc3 <<
875 power-source = <<
876 }; <<
877 }; <<
878 768
879 powergates { 769 powergates {
880 pd_audio: aud { 770 pd_audio: aud {
881 clocks = <&teg 771 clocks = <&tegra_car TEGRA210_CLK_APE>,
882 <&teg 772 <&tegra_car TEGRA210_CLK_APB2APE>;
883 resets = <&teg 773 resets = <&tegra_car 198>;
884 #power-domain- 774 #power-domain-cells = <0>;
885 }; 775 };
886 776
887 pd_sor: sor { 777 pd_sor: sor {
888 clocks = <&teg 778 clocks = <&tegra_car TEGRA210_CLK_SOR0>,
889 <&teg 779 <&tegra_car TEGRA210_CLK_SOR1>,
890 <&teg !! 780 <&tegra_car TEGRA210_CLK_CSI>,
891 <&teg <<
892 <&teg <<
893 <&teg 781 <&tegra_car TEGRA210_CLK_DSIA>,
894 <&teg 782 <&tegra_car TEGRA210_CLK_DSIB>,
895 <&teg 783 <&tegra_car TEGRA210_CLK_DPAUX>,
896 <&teg 784 <&tegra_car TEGRA210_CLK_DPAUX1>,
897 <&teg 785 <&tegra_car TEGRA210_CLK_MIPI_CAL>;
898 resets = <&teg 786 resets = <&tegra_car TEGRA210_CLK_SOR0>,
899 <&teg 787 <&tegra_car TEGRA210_CLK_SOR1>,
>> 788 <&tegra_car TEGRA210_CLK_CSI>,
900 <&teg 789 <&tegra_car TEGRA210_CLK_DSIA>,
901 <&teg 790 <&tegra_car TEGRA210_CLK_DSIB>,
902 <&teg 791 <&tegra_car TEGRA210_CLK_DPAUX>,
903 <&teg 792 <&tegra_car TEGRA210_CLK_DPAUX1>,
904 <&teg 793 <&tegra_car TEGRA210_CLK_MIPI_CAL>;
905 #power-domain- 794 #power-domain-cells = <0>;
906 }; 795 };
907 796
908 pd_venc: venc { <<
909 clocks = <&teg <<
910 <&teg <<
911 resets = <&mc <<
912 <&teg <<
913 <&teg <<
914 #power-domain- <<
915 }; <<
916 <<
917 pd_vic: vic { <<
918 clocks = <&teg <<
919 resets = <&teg <<
920 #power-domain- <<
921 }; <<
922 <<
923 pd_xusbss: xusba { 797 pd_xusbss: xusba {
924 clocks = <&teg 798 clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>;
925 resets = <&teg 799 resets = <&tegra_car TEGRA210_CLK_XUSB_SS>;
926 #power-domain- 800 #power-domain-cells = <0>;
927 }; 801 };
928 802
929 pd_xusbdev: xusbb { 803 pd_xusbdev: xusbb {
930 clocks = <&teg 804 clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>;
931 resets = <&teg 805 resets = <&tegra_car 95>;
932 #power-domain- 806 #power-domain-cells = <0>;
933 }; 807 };
934 808
935 pd_xusbhost: xusbc { 809 pd_xusbhost: xusbc {
936 clocks = <&teg 810 clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>;
937 resets = <&teg 811 resets = <&tegra_car TEGRA210_CLK_XUSB_HOST>;
938 #power-domain- 812 #power-domain-cells = <0>;
939 }; 813 };
>> 814
>> 815 pd_vic: vic {
>> 816 clocks = <&tegra_car TEGRA210_CLK_VIC03>;
>> 817 clock-names = "vic";
>> 818 resets = <&tegra_car 178>;
>> 819 reset-names = "vic";
>> 820 #power-domain-cells = <0>;
>> 821 };
>> 822 };
>> 823
>> 824 sdmmc1_3v3: sdmmc1-3v3 {
>> 825 pins = "sdmmc1";
>> 826 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
>> 827 };
>> 828
>> 829 sdmmc1_1v8: sdmmc1-1v8 {
>> 830 pins = "sdmmc1";
>> 831 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
>> 832 };
>> 833
>> 834 sdmmc3_3v3: sdmmc3-3v3 {
>> 835 pins = "sdmmc3";
>> 836 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
>> 837 };
>> 838
>> 839 sdmmc3_1v8: sdmmc3-1v8 {
>> 840 pins = "sdmmc3";
>> 841 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
940 }; 842 };
941 }; 843 };
942 844
943 fuse@7000f800 { 845 fuse@7000f800 {
944 compatible = "nvidia,tegra210- 846 compatible = "nvidia,tegra210-efuse";
945 reg = <0x0 0x7000f800 0x0 0x40 847 reg = <0x0 0x7000f800 0x0 0x400>;
946 clocks = <&tegra_car TEGRA210_ 848 clocks = <&tegra_car TEGRA210_CLK_FUSE>;
947 clock-names = "fuse"; 849 clock-names = "fuse";
948 resets = <&tegra_car 39>; 850 resets = <&tegra_car 39>;
949 reset-names = "fuse"; 851 reset-names = "fuse";
950 }; 852 };
951 853
952 mc: memory-controller@70019000 { 854 mc: memory-controller@70019000 {
953 compatible = "nvidia,tegra210- 855 compatible = "nvidia,tegra210-mc";
954 reg = <0x0 0x70019000 0x0 0x10 856 reg = <0x0 0x70019000 0x0 0x1000>;
955 clocks = <&tegra_car TEGRA210_ 857 clocks = <&tegra_car TEGRA210_CLK_MC>;
956 clock-names = "mc"; 858 clock-names = "mc";
957 859
958 interrupts = <GIC_SPI 77 IRQ_T 860 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
959 861
960 #iommu-cells = <1>; 862 #iommu-cells = <1>;
961 #reset-cells = <1>; <<
962 }; <<
963 <<
964 emc: external-memory-controller@7001b0 <<
965 compatible = "nvidia,tegra210- <<
966 reg = <0x0 0x7001b000 0x0 0x10 <<
967 <0x0 0x7001e000 0x0 0x10 <<
968 <0x0 0x7001f000 0x0 0x10 <<
969 clocks = <&tegra_car TEGRA210_ <<
970 clock-names = "emc"; <<
971 interrupts = <GIC_SPI 78 IRQ_T <<
972 nvidia,memory-controller = <&m <<
973 #cooling-cells = <2>; <<
974 }; 863 };
975 864
976 sata@70020000 { 865 sata@70020000 {
977 compatible = "nvidia,tegra210- 866 compatible = "nvidia,tegra210-ahci";
978 reg = <0x0 0x70027000 0x0 0x20 867 reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */
979 <0x0 0x70020000 0x0 0x70 868 <0x0 0x70020000 0x0 0x7000>, /* SATA */
980 <0x0 0x70001100 0x0 0x10 869 <0x0 0x70001100 0x0 0x1000>; /* SATA AUX */
981 interrupts = <GIC_SPI 23 IRQ_T 870 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
982 clocks = <&tegra_car TEGRA210_ 871 clocks = <&tegra_car TEGRA210_CLK_SATA>,
983 <&tegra_car TEGRA210_ 872 <&tegra_car TEGRA210_CLK_SATA_OOB>;
984 clock-names = "sata", "sata-oo 873 clock-names = "sata", "sata-oob";
985 resets = <&tegra_car 124>, 874 resets = <&tegra_car 124>,
986 <&tegra_car 129>, !! 875 <&tegra_car 123>,
987 <&tegra_car 123>; !! 876 <&tegra_car 129>;
988 reset-names = "sata", "sata-co !! 877 reset-names = "sata", "sata-oob", "sata-cold";
989 status = "disabled"; 878 status = "disabled";
990 }; 879 };
991 880
992 hda@70030000 { 881 hda@70030000 {
993 compatible = "nvidia,tegra210- 882 compatible = "nvidia,tegra210-hda", "nvidia,tegra30-hda";
994 reg = <0x0 0x70030000 0x0 0x10 883 reg = <0x0 0x70030000 0x0 0x10000>;
995 interrupts = <GIC_SPI 81 IRQ_T 884 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
996 clocks = <&tegra_car TEGRA210_ 885 clocks = <&tegra_car TEGRA210_CLK_HDA>,
997 <&tegra_car TEGRA210_ 886 <&tegra_car TEGRA210_CLK_HDA2HDMI>,
998 <&tegra_car TEGRA210_ 887 <&tegra_car TEGRA210_CLK_HDA2CODEC_2X>;
999 clock-names = "hda", "hda2hdmi 888 clock-names = "hda", "hda2hdmi", "hda2codec_2x";
1000 resets = <&tegra_car 125>, /* 889 resets = <&tegra_car 125>, /* hda */
1001 <&tegra_car 128>, /* 890 <&tegra_car 128>, /* hda2hdmi */
1002 <&tegra_car 111>; /* 891 <&tegra_car 111>; /* hda2codec_2x */
1003 reset-names = "hda", "hda2hdm 892 reset-names = "hda", "hda2hdmi", "hda2codec_2x";
1004 power-domains = <&pd_sor>; <<
1005 status = "disabled"; 893 status = "disabled";
1006 }; 894 };
1007 895
1008 usb@70090000 { 896 usb@70090000 {
1009 compatible = "nvidia,tegra210 897 compatible = "nvidia,tegra210-xusb";
1010 reg = <0x0 0x70090000 0x0 0x8 898 reg = <0x0 0x70090000 0x0 0x8000>,
1011 <0x0 0x70098000 0x0 0x1 899 <0x0 0x70098000 0x0 0x1000>,
1012 <0x0 0x70099000 0x0 0x1 900 <0x0 0x70099000 0x0 0x1000>;
1013 reg-names = "hcd", "fpci", "i 901 reg-names = "hcd", "fpci", "ipfs";
1014 902
1015 interrupts = <GIC_SPI 39 IRQ_ 903 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
1016 <GIC_SPI 40 IRQ_ 904 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1017 905
1018 clocks = <&tegra_car TEGRA210 906 clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>,
1019 <&tegra_car TEGRA210 907 <&tegra_car TEGRA210_CLK_XUSB_HOST_SRC>,
1020 <&tegra_car TEGRA210 908 <&tegra_car TEGRA210_CLK_XUSB_FALCON_SRC>,
1021 <&tegra_car TEGRA210 909 <&tegra_car TEGRA210_CLK_XUSB_SS>,
1022 <&tegra_car TEGRA210 910 <&tegra_car TEGRA210_CLK_XUSB_SS_DIV2>,
1023 <&tegra_car TEGRA210 911 <&tegra_car TEGRA210_CLK_XUSB_SS_SRC>,
1024 <&tegra_car TEGRA210 912 <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>,
1025 <&tegra_car TEGRA210 913 <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>,
1026 <&tegra_car TEGRA210 914 <&tegra_car TEGRA210_CLK_PLL_U_480M>,
1027 <&tegra_car TEGRA210 915 <&tegra_car TEGRA210_CLK_CLK_M>,
1028 <&tegra_car TEGRA210 916 <&tegra_car TEGRA210_CLK_PLL_E>;
1029 clock-names = "xusb_host", "x 917 clock-names = "xusb_host", "xusb_host_src",
1030 "xusb_falcon_sr 918 "xusb_falcon_src", "xusb_ss",
1031 "xusb_ss_div2", 919 "xusb_ss_div2", "xusb_ss_src",
1032 "xusb_hs_src", 920 "xusb_hs_src", "xusb_fs_src",
1033 "pll_u_480m", " 921 "pll_u_480m", "clk_m", "pll_e";
1034 resets = <&tegra_car 89>, <&t 922 resets = <&tegra_car 89>, <&tegra_car 156>,
1035 <&tegra_car 143>; 923 <&tegra_car 143>;
1036 reset-names = "xusb_host", "x 924 reset-names = "xusb_host", "xusb_ss", "xusb_src";
1037 power-domains = <&pd_xusbhost 925 power-domains = <&pd_xusbhost>, <&pd_xusbss>;
1038 power-domain-names = "xusb_ho 926 power-domain-names = "xusb_host", "xusb_ss";
1039 927
1040 nvidia,xusb-padctl = <&padctl 928 nvidia,xusb-padctl = <&padctl>;
1041 929
1042 status = "disabled"; 930 status = "disabled";
1043 }; 931 };
1044 932
1045 padctl: padctl@7009f000 { 933 padctl: padctl@7009f000 {
1046 compatible = "nvidia,tegra210 934 compatible = "nvidia,tegra210-xusb-padctl";
1047 reg = <0x0 0x7009f000 0x0 0x1 935 reg = <0x0 0x7009f000 0x0 0x1000>;
1048 interrupts = <GIC_SPI 49 IRQ_ <<
1049 resets = <&tegra_car 142>; 936 resets = <&tegra_car 142>;
1050 reset-names = "padctl"; 937 reset-names = "padctl";
1051 nvidia,pmc = <&tegra_pmc>; <<
1052 938
1053 status = "disabled"; 939 status = "disabled";
1054 940
1055 pads { 941 pads {
1056 usb2 { 942 usb2 {
1057 clocks = <&te 943 clocks = <&tegra_car TEGRA210_CLK_USB2_TRK>;
1058 clock-names = 944 clock-names = "trk";
1059 status = "dis 945 status = "disabled";
1060 946
1061 lanes { 947 lanes {
1062 usb2- 948 usb2-0 {
1063 949 status = "disabled";
1064 950 #phy-cells = <0>;
1065 }; 951 };
1066 952
1067 usb2- 953 usb2-1 {
1068 954 status = "disabled";
1069 955 #phy-cells = <0>;
1070 }; 956 };
1071 957
1072 usb2- 958 usb2-2 {
1073 959 status = "disabled";
1074 960 #phy-cells = <0>;
1075 }; 961 };
1076 962
1077 usb2- 963 usb2-3 {
1078 964 status = "disabled";
1079 965 #phy-cells = <0>;
1080 }; 966 };
1081 }; 967 };
1082 }; 968 };
1083 969
1084 hsic { 970 hsic {
1085 clocks = <&te 971 clocks = <&tegra_car TEGRA210_CLK_HSIC_TRK>;
1086 clock-names = 972 clock-names = "trk";
1087 status = "dis 973 status = "disabled";
1088 974
1089 lanes { 975 lanes {
1090 hsic- 976 hsic-0 {
1091 977 status = "disabled";
1092 978 #phy-cells = <0>;
1093 }; 979 };
1094 980
1095 hsic- 981 hsic-1 {
1096 982 status = "disabled";
1097 983 #phy-cells = <0>;
1098 }; 984 };
1099 }; 985 };
1100 }; 986 };
1101 987
1102 pcie { 988 pcie {
1103 clocks = <&te 989 clocks = <&tegra_car TEGRA210_CLK_PLL_E>;
1104 clock-names = 990 clock-names = "pll";
1105 resets = <&te 991 resets = <&tegra_car 205>;
1106 reset-names = 992 reset-names = "phy";
1107 status = "dis 993 status = "disabled";
1108 994
1109 lanes { 995 lanes {
1110 pcie- 996 pcie-0 {
1111 997 status = "disabled";
1112 998 #phy-cells = <0>;
1113 }; 999 };
1114 1000
1115 pcie- 1001 pcie-1 {
1116 1002 status = "disabled";
1117 1003 #phy-cells = <0>;
1118 }; 1004 };
1119 1005
1120 pcie- 1006 pcie-2 {
1121 1007 status = "disabled";
1122 1008 #phy-cells = <0>;
1123 }; 1009 };
1124 1010
1125 pcie- 1011 pcie-3 {
1126 1012 status = "disabled";
1127 1013 #phy-cells = <0>;
1128 }; 1014 };
1129 1015
1130 pcie- 1016 pcie-4 {
1131 1017 status = "disabled";
1132 1018 #phy-cells = <0>;
1133 }; 1019 };
1134 1020
1135 pcie- 1021 pcie-5 {
1136 1022 status = "disabled";
1137 1023 #phy-cells = <0>;
1138 }; 1024 };
1139 1025
1140 pcie- 1026 pcie-6 {
1141 1027 status = "disabled";
1142 1028 #phy-cells = <0>;
1143 }; 1029 };
1144 }; 1030 };
1145 }; 1031 };
1146 1032
1147 sata { 1033 sata {
1148 clocks = <&te 1034 clocks = <&tegra_car TEGRA210_CLK_PLL_E>;
1149 clock-names = 1035 clock-names = "pll";
1150 resets = <&te 1036 resets = <&tegra_car 204>;
1151 reset-names = 1037 reset-names = "phy";
1152 status = "dis 1038 status = "disabled";
1153 1039
1154 lanes { 1040 lanes {
1155 sata- 1041 sata-0 {
1156 1042 status = "disabled";
1157 1043 #phy-cells = <0>;
1158 }; 1044 };
1159 }; 1045 };
1160 }; 1046 };
1161 }; 1047 };
1162 1048
1163 ports { 1049 ports {
1164 usb2-0 { 1050 usb2-0 {
1165 status = "dis 1051 status = "disabled";
1166 }; 1052 };
1167 1053
1168 usb2-1 { 1054 usb2-1 {
1169 status = "dis 1055 status = "disabled";
1170 }; 1056 };
1171 1057
1172 usb2-2 { 1058 usb2-2 {
1173 status = "dis 1059 status = "disabled";
1174 }; 1060 };
1175 1061
1176 usb2-3 { 1062 usb2-3 {
1177 status = "dis 1063 status = "disabled";
1178 }; 1064 };
1179 1065
1180 hsic-0 { 1066 hsic-0 {
1181 status = "dis 1067 status = "disabled";
1182 }; 1068 };
1183 1069
1184 usb3-0 { 1070 usb3-0 {
1185 status = "dis 1071 status = "disabled";
1186 }; 1072 };
1187 1073
1188 usb3-1 { 1074 usb3-1 {
1189 status = "dis 1075 status = "disabled";
1190 }; 1076 };
1191 1077
1192 usb3-2 { 1078 usb3-2 {
1193 status = "dis 1079 status = "disabled";
1194 }; 1080 };
1195 1081
1196 usb3-3 { 1082 usb3-3 {
1197 status = "dis 1083 status = "disabled";
1198 }; 1084 };
1199 }; 1085 };
1200 }; 1086 };
1201 1087
1202 mmc@700b0000 { !! 1088 sdhci@700b0000 {
1203 compatible = "nvidia,tegra210 !! 1089 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";
1204 reg = <0x0 0x700b0000 0x0 0x2 1090 reg = <0x0 0x700b0000 0x0 0x200>;
1205 interrupts = <GIC_SPI 14 IRQ_ 1091 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1206 clocks = <&tegra_car TEGRA210 !! 1092 clocks = <&tegra_car TEGRA210_CLK_SDMMC1>;
1207 <&tegra_car TEGRA210 !! 1093 clock-names = "sdhci";
1208 clock-names = "sdhci", "tmclk <<
1209 resets = <&tegra_car 14>; 1094 resets = <&tegra_car 14>;
1210 reset-names = "sdhci"; 1095 reset-names = "sdhci";
1211 pinctrl-names = "sdmmc-3v3", 1096 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8",
1212 "sdmmc-3v3-dr 1097 "sdmmc-3v3-drv", "sdmmc-1v8-drv";
1213 pinctrl-0 = <&sdmmc1_3v3>; 1098 pinctrl-0 = <&sdmmc1_3v3>;
1214 pinctrl-1 = <&sdmmc1_1v8>; 1099 pinctrl-1 = <&sdmmc1_1v8>;
1215 pinctrl-2 = <&sdmmc1_3v3_drv> 1100 pinctrl-2 = <&sdmmc1_3v3_drv>;
1216 pinctrl-3 = <&sdmmc1_1v8_drv> 1101 pinctrl-3 = <&sdmmc1_1v8_drv>;
1217 nvidia,pad-autocal-pull-up-of 1102 nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>;
1218 nvidia,pad-autocal-pull-down- 1103 nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>;
1219 nvidia,pad-autocal-pull-up-of 1104 nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>;
1220 nvidia,pad-autocal-pull-down- 1105 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>;
1221 nvidia,default-tap = <0x2>; 1106 nvidia,default-tap = <0x2>;
1222 nvidia,default-trim = <0x4>; 1107 nvidia,default-trim = <0x4>;
1223 assigned-clocks = <&tegra_car 1108 assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>,
1224 <&tegra_car 1109 <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>,
1225 <&tegra_car 1110 <&tegra_car TEGRA210_CLK_PLL_C4>;
1226 assigned-clock-parents = <&te 1111 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
1227 assigned-clock-rates = <20000 1112 assigned-clock-rates = <200000000>, <1000000000>, <1000000000>;
1228 status = "disabled"; 1113 status = "disabled";
1229 }; 1114 };
1230 1115
1231 mmc@700b0200 { !! 1116 sdhci@700b0200 {
1232 compatible = "nvidia,tegra210 !! 1117 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";
1233 reg = <0x0 0x700b0200 0x0 0x2 1118 reg = <0x0 0x700b0200 0x0 0x200>;
1234 interrupts = <GIC_SPI 15 IRQ_ 1119 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1235 clocks = <&tegra_car TEGRA210 !! 1120 clocks = <&tegra_car TEGRA210_CLK_SDMMC2>;
1236 <&tegra_car TEGRA210 !! 1121 clock-names = "sdhci";
1237 clock-names = "sdhci", "tmclk <<
1238 resets = <&tegra_car 9>; 1122 resets = <&tegra_car 9>;
1239 reset-names = "sdhci"; 1123 reset-names = "sdhci";
1240 pinctrl-names = "sdmmc-1v8-dr 1124 pinctrl-names = "sdmmc-1v8-drv";
1241 pinctrl-0 = <&sdmmc2_1v8_drv> 1125 pinctrl-0 = <&sdmmc2_1v8_drv>;
1242 nvidia,pad-autocal-pull-up-of 1126 nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>;
1243 nvidia,pad-autocal-pull-down- 1127 nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>;
1244 nvidia,default-tap = <0x8>; 1128 nvidia,default-tap = <0x8>;
1245 nvidia,default-trim = <0x0>; 1129 nvidia,default-trim = <0x0>;
1246 status = "disabled"; 1130 status = "disabled";
1247 }; 1131 };
1248 1132
1249 mmc@700b0400 { !! 1133 sdhci@700b0400 {
1250 compatible = "nvidia,tegra210 !! 1134 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";
1251 reg = <0x0 0x700b0400 0x0 0x2 1135 reg = <0x0 0x700b0400 0x0 0x200>;
1252 interrupts = <GIC_SPI 19 IRQ_ 1136 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1253 clocks = <&tegra_car TEGRA210 !! 1137 clocks = <&tegra_car TEGRA210_CLK_SDMMC3>;
1254 <&tegra_car TEGRA210 !! 1138 clock-names = "sdhci";
1255 clock-names = "sdhci", "tmclk <<
1256 resets = <&tegra_car 69>; 1139 resets = <&tegra_car 69>;
1257 reset-names = "sdhci"; 1140 reset-names = "sdhci";
1258 pinctrl-names = "sdmmc-3v3", 1141 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8",
1259 "sdmmc-3v3-dr 1142 "sdmmc-3v3-drv", "sdmmc-1v8-drv";
1260 pinctrl-0 = <&sdmmc3_3v3>; 1143 pinctrl-0 = <&sdmmc3_3v3>;
1261 pinctrl-1 = <&sdmmc3_1v8>; 1144 pinctrl-1 = <&sdmmc3_1v8>;
1262 pinctrl-2 = <&sdmmc3_3v3_drv> 1145 pinctrl-2 = <&sdmmc3_3v3_drv>;
1263 pinctrl-3 = <&sdmmc3_1v8_drv> 1146 pinctrl-3 = <&sdmmc3_1v8_drv>;
1264 nvidia,pad-autocal-pull-up-of 1147 nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>;
1265 nvidia,pad-autocal-pull-down- 1148 nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>;
1266 nvidia,pad-autocal-pull-up-of 1149 nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>;
1267 nvidia,pad-autocal-pull-down- 1150 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>;
1268 nvidia,default-tap = <0x3>; 1151 nvidia,default-tap = <0x3>;
1269 nvidia,default-trim = <0x3>; 1152 nvidia,default-trim = <0x3>;
1270 status = "disabled"; 1153 status = "disabled";
1271 }; 1154 };
1272 1155
1273 mmc@700b0600 { !! 1156 sdhci@700b0600 {
1274 compatible = "nvidia,tegra210 !! 1157 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";
1275 reg = <0x0 0x700b0600 0x0 0x2 1158 reg = <0x0 0x700b0600 0x0 0x200>;
1276 interrupts = <GIC_SPI 31 IRQ_ 1159 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
1277 clocks = <&tegra_car TEGRA210 !! 1160 clocks = <&tegra_car TEGRA210_CLK_SDMMC4>;
1278 <&tegra_car TEGRA210 !! 1161 clock-names = "sdhci";
1279 clock-names = "sdhci", "tmclk <<
1280 resets = <&tegra_car 15>; 1162 resets = <&tegra_car 15>;
1281 reset-names = "sdhci"; 1163 reset-names = "sdhci";
1282 pinctrl-names = "sdmmc-3v3-dr 1164 pinctrl-names = "sdmmc-3v3-drv", "sdmmc-1v8-drv";
1283 pinctrl-0 = <&sdmmc4_1v8_drv> 1165 pinctrl-0 = <&sdmmc4_1v8_drv>;
1284 pinctrl-1 = <&sdmmc4_1v8_drv> 1166 pinctrl-1 = <&sdmmc4_1v8_drv>;
1285 nvidia,pad-autocal-pull-up-of 1167 nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>;
1286 nvidia,pad-autocal-pull-down- 1168 nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>;
1287 nvidia,default-tap = <0x8>; 1169 nvidia,default-tap = <0x8>;
1288 nvidia,default-trim = <0x0>; 1170 nvidia,default-trim = <0x0>;
1289 assigned-clocks = <&tegra_car 1171 assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>,
1290 <&tegra_car 1172 <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
1291 assigned-clock-parents = <&te 1173 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
1292 nvidia,dqs-trim = <40>; 1174 nvidia,dqs-trim = <40>;
1293 mmc-hs400-1_8v; 1175 mmc-hs400-1_8v;
1294 status = "disabled"; 1176 status = "disabled";
1295 }; 1177 };
1296 1178
1297 usb@700d0000 { <<
1298 compatible = "nvidia,tegra210 <<
1299 reg = <0x0 0x700d0000 0x0 0x8 <<
1300 <0x0 0x700d8000 0x0 0x1 <<
1301 <0x0 0x700d9000 0x0 0x1 <<
1302 reg-names = "base", "fpci", " <<
1303 interrupts = <GIC_SPI 44 IRQ_ <<
1304 clocks = <&tegra_car TEGRA210 <<
1305 <&tegra_car TEGRA210 <<
1306 <&tegra_car TEGRA210 <<
1307 <&tegra_car TEGRA210 <<
1308 <&tegra_car TEGRA210 <<
1309 clock-names = "dev", "ss", "s <<
1310 power-domains = <&pd_xusbdev> <<
1311 power-domain-names = "dev", " <<
1312 nvidia,xusb-padctl = <&padctl <<
1313 status = "disabled"; <<
1314 }; <<
1315 <<
1316 soctherm: thermal-sensor@700e2000 { <<
1317 compatible = "nvidia,tegra210 <<
1318 reg = <0x0 0x700e2000 0x0 0x6 <<
1319 <0x0 0x60006000 0x0 0x4 <<
1320 reg-names = "soctherm-reg", " <<
1321 interrupts = <GIC_SPI 48 IRQ_ <<
1322 <GIC_SPI 51 IRQ_ <<
1323 interrupt-names = "thermal", <<
1324 clocks = <&tegra_car TEGRA210 <<
1325 <&tegra_car TEGRA210_ <<
1326 clock-names = "tsensor", "soc <<
1327 resets = <&tegra_car 78>; <<
1328 reset-names = "soctherm"; <<
1329 #thermal-sensor-cells = <1>; <<
1330 <<
1331 throttle-cfgs { <<
1332 throttle_heavy: heavy <<
1333 nvidia,priori <<
1334 nvidia,cpu-th <<
1335 nvidia,gpu-th <<
1336 <<
1337 #cooling-cell <<
1338 }; <<
1339 }; <<
1340 }; <<
1341 <<
1342 mipi: mipi@700e3000 { 1179 mipi: mipi@700e3000 {
1343 compatible = "nvidia,tegra210 1180 compatible = "nvidia,tegra210-mipi";
1344 reg = <0x0 0x700e3000 0x0 0x1 1181 reg = <0x0 0x700e3000 0x0 0x100>;
1345 clocks = <&tegra_car TEGRA210 1182 clocks = <&tegra_car TEGRA210_CLK_MIPI_CAL>;
1346 clock-names = "mipi-cal"; 1183 clock-names = "mipi-cal";
1347 power-domains = <&pd_sor>; 1184 power-domains = <&pd_sor>;
1348 #nvidia,mipi-calibrate-cells 1185 #nvidia,mipi-calibrate-cells = <1>;
1349 }; 1186 };
1350 1187
1351 dfll: clock@70110000 { 1188 dfll: clock@70110000 {
1352 compatible = "nvidia,tegra210 1189 compatible = "nvidia,tegra210-dfll";
1353 reg = <0 0x70110000 0 0x100>, 1190 reg = <0 0x70110000 0 0x100>, /* DFLL control */
1354 <0 0x70110000 0 0x100>, 1191 <0 0x70110000 0 0x100>, /* I2C output control */
1355 <0 0x70110100 0 0x100>, 1192 <0 0x70110100 0 0x100>, /* Integrated I2C controller */
1356 <0 0x70110200 0 0x100>; 1193 <0 0x70110200 0 0x100>; /* Look-up table RAM */
1357 interrupts = <GIC_SPI 62 IRQ_ 1194 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
1358 clocks = <&tegra_car TEGRA210 1195 clocks = <&tegra_car TEGRA210_CLK_DFLL_SOC>,
1359 <&tegra_car TEGRA210 1196 <&tegra_car TEGRA210_CLK_DFLL_REF>,
1360 <&tegra_car TEGRA210 1197 <&tegra_car TEGRA210_CLK_I2C5>;
1361 clock-names = "soc", "ref", " 1198 clock-names = "soc", "ref", "i2c";
1362 resets = <&tegra_car TEGRA210 !! 1199 resets = <&tegra_car TEGRA210_RST_DFLL_DVCO>;
1363 <&tegra_car 155>; !! 1200 reset-names = "dvco";
1364 reset-names = "dvco", "dfll"; <<
1365 #clock-cells = <0>; 1201 #clock-cells = <0>;
1366 clock-output-names = "dfllCPU 1202 clock-output-names = "dfllCPU_out";
1367 status = "disabled"; 1203 status = "disabled";
1368 }; 1204 };
1369 1205
1370 aconnect@702c0000 { 1206 aconnect@702c0000 {
1371 compatible = "nvidia,tegra210 1207 compatible = "nvidia,tegra210-aconnect";
1372 clocks = <&tegra_car TEGRA210 1208 clocks = <&tegra_car TEGRA210_CLK_APE>,
1373 <&tegra_car TEGRA210 1209 <&tegra_car TEGRA210_CLK_APB2APE>;
1374 clock-names = "ape", "apb2ape 1210 clock-names = "ape", "apb2ape";
1375 power-domains = <&pd_audio>; 1211 power-domains = <&pd_audio>;
1376 #address-cells = <1>; 1212 #address-cells = <1>;
1377 #size-cells = <1>; 1213 #size-cells = <1>;
1378 ranges = <0x702c0000 0x0 0x70 1214 ranges = <0x702c0000 0x0 0x702c0000 0x00040000>;
1379 status = "disabled"; 1215 status = "disabled";
1380 1216
1381 tegra_ahub: ahub@702d0800 { !! 1217 adma: dma@702e2000 {
1382 compatible = "nvidia, <<
1383 reg = <0x702d0800 0x8 <<
1384 clocks = <&tegra_car <<
1385 clock-names = "ahub"; <<
1386 assigned-clocks = <&t <<
1387 assigned-clock-parent <<
1388 assigned-clock-rates <<
1389 #address-cells = <1>; <<
1390 #size-cells = <1>; <<
1391 ranges = <0x702d0000 <<
1392 status = "disabled"; <<
1393 <<
1394 tegra_admaif: admaif@ <<
1395 compatible = <<
1396 reg = <0x702d <<
1397 dmas = <&adma <<
1398 <&adma <<
1399 <&adma <<
1400 <&adma <<
1401 <&adma <<
1402 <&adma <<
1403 <&adma <<
1404 <&adma <<
1405 <&adma <<
1406 <&adma <<
1407 dma-names = " <<
1408 " <<
1409 " <<
1410 " <<
1411 " <<
1412 " <<
1413 " <<
1414 " <<
1415 " <<
1416 " <<
1417 status = "dis <<
1418 <<
1419 ports { <<
1420 #addr <<
1421 #size <<
1422 <<
1423 admai <<
1424 <<
1425 <<
1426 <<
1427 <<
1428 <<
1429 }; <<
1430 <<
1431 admai <<
1432 <<
1433 <<
1434 <<
1435 <<
1436 <<
1437 }; <<
1438 <<
1439 admai <<
1440 <<
1441 <<
1442 <<
1443 <<
1444 <<
1445 }; <<
1446 <<
1447 admai <<
1448 <<
1449 <<
1450 <<
1451 <<
1452 <<
1453 }; <<
1454 <<
1455 admai <<
1456 <<
1457 <<
1458 <<
1459 <<
1460 <<
1461 }; <<
1462 <<
1463 admai <<
1464 <<
1465 <<
1466 <<
1467 <<
1468 <<
1469 }; <<
1470 <<
1471 admai <<
1472 <<
1473 <<
1474 <<
1475 <<
1476 <<
1477 }; <<
1478 <<
1479 admai <<
1480 <<
1481 <<
1482 <<
1483 <<
1484 <<
1485 }; <<
1486 <<
1487 admai <<
1488 <<
1489 <<
1490 <<
1491 <<
1492 <<
1493 }; <<
1494 <<
1495 admai <<
1496 <<
1497 <<
1498 <<
1499 <<
1500 <<
1501 }; <<
1502 }; <<
1503 }; <<
1504 <<
1505 tegra_i2s1: i2s@702d1 <<
1506 compatible = <<
1507 reg = <0x702d <<
1508 clocks = <&te <<
1509 <&te <<
1510 clock-names = <<
1511 assigned-cloc <<
1512 assigned-cloc <<
1513 assigned-cloc <<
1514 sound-name-pr <<
1515 status = "dis <<
1516 }; <<
1517 <<
1518 tegra_i2s2: i2s@702d1 <<
1519 compatible = <<
1520 reg = <0x702d <<
1521 clocks = <&te <<
1522 <&te <<
1523 clock-names = <<
1524 assigned-cloc <<
1525 assigned-cloc <<
1526 assigned-cloc <<
1527 sound-name-pr <<
1528 status = "dis <<
1529 }; <<
1530 <<
1531 tegra_i2s3: i2s@702d1 <<
1532 compatible = <<
1533 reg = <0x702d <<
1534 clocks = <&te <<
1535 <&te <<
1536 clock-names = <<
1537 assigned-cloc <<
1538 assigned-cloc <<
1539 assigned-cloc <<
1540 sound-name-pr <<
1541 status = "dis <<
1542 }; <<
1543 <<
1544 tegra_i2s4: i2s@702d1 <<
1545 compatible = <<
1546 reg = <0x702d <<
1547 clocks = <&te <<
1548 <&te <<
1549 clock-names = <<
1550 assigned-cloc <<
1551 assigned-cloc <<
1552 assigned-cloc <<
1553 sound-name-pr <<
1554 status = "dis <<
1555 }; <<
1556 <<
1557 tegra_i2s5: i2s@702d1 <<
1558 compatible = <<
1559 reg = <0x702d <<
1560 clocks = <&te <<
1561 <&te <<
1562 clock-names = <<
1563 assigned-cloc <<
1564 assigned-cloc <<
1565 assigned-cloc <<
1566 sound-name-pr <<
1567 status = "dis <<
1568 }; <<
1569 <<
1570 tegra_sfc1: sfc@702d2 <<
1571 compatible = <<
1572 reg = <0x702d <<
1573 sound-name-pr <<
1574 status = "dis <<
1575 }; <<
1576 <<
1577 tegra_sfc2: sfc@702d2 <<
1578 compatible = <<
1579 reg = <0x702d <<
1580 sound-name-pr <<
1581 status = "dis <<
1582 }; <<
1583 <<
1584 tegra_sfc3: sfc@702d2 <<
1585 compatible = <<
1586 reg = <0x702d <<
1587 sound-name-pr <<
1588 status = "dis <<
1589 }; <<
1590 <<
1591 tegra_sfc4: sfc@702d2 <<
1592 compatible = <<
1593 reg = <0x702d <<
1594 sound-name-pr <<
1595 status = "dis <<
1596 }; <<
1597 <<
1598 tegra_amx1: amx@702d3 <<
1599 compatible = <<
1600 reg = <0x702d <<
1601 sound-name-pr <<
1602 status = "dis <<
1603 }; <<
1604 <<
1605 tegra_amx2: amx@702d3 <<
1606 compatible = <<
1607 reg = <0x702d <<
1608 sound-name-pr <<
1609 status = "dis <<
1610 }; <<
1611 <<
1612 tegra_adx1: adx@702d3 <<
1613 compatible = <<
1614 reg = <0x702d <<
1615 sound-name-pr <<
1616 status = "dis <<
1617 }; <<
1618 <<
1619 tegra_adx2: adx@702d3 <<
1620 compatible = <<
1621 reg = <0x702d <<
1622 sound-name-pr <<
1623 status = "dis <<
1624 }; <<
1625 <<
1626 tegra_dmic1: dmic@702 <<
1627 compatible = <<
1628 reg = <0x702d <<
1629 clocks = <&te <<
1630 clock-names = <<
1631 assigned-cloc <<
1632 assigned-cloc <<
1633 assigned-cloc <<
1634 sound-name-pr <<
1635 status = "dis <<
1636 }; <<
1637 <<
1638 tegra_dmic2: dmic@702 <<
1639 compatible = <<
1640 reg = <0x702d <<
1641 clocks = <&te <<
1642 clock-names = <<
1643 assigned-cloc <<
1644 assigned-cloc <<
1645 assigned-cloc <<
1646 sound-name-pr <<
1647 status = "dis <<
1648 }; <<
1649 <<
1650 tegra_dmic3: dmic@702 <<
1651 compatible = <<
1652 reg = <0x702d <<
1653 clocks = <&te <<
1654 clock-names = <<
1655 assigned-cloc <<
1656 assigned-cloc <<
1657 assigned-cloc <<
1658 sound-name-pr <<
1659 status = "dis <<
1660 }; <<
1661 <<
1662 tegra_ope1: processin <<
1663 compatible = <<
1664 reg = <0x702d <<
1665 #address-cell <<
1666 #size-cells = <<
1667 ranges; <<
1668 sound-name-pr <<
1669 status = "dis <<
1670 <<
1671 equalizer@702 <<
1672 compa <<
1673 reg = <<
1674 }; <<
1675 <<
1676 dynamic-range <<
1677 compa <<
1678 reg = <<
1679 }; <<
1680 }; <<
1681 <<
1682 tegra_ope2: processin <<
1683 compatible = <<
1684 reg = <0x702d <<
1685 #address-cell <<
1686 #size-cells = <<
1687 ranges; <<
1688 sound-name-pr <<
1689 status = "dis <<
1690 <<
1691 equalizer@702 <<
1692 compa <<
1693 reg = <<
1694 }; <<
1695 <<
1696 dynamic-range <<
1697 compa <<
1698 reg = <<
1699 }; <<
1700 }; <<
1701 <<
1702 tegra_mvc1: mvc@702da <<
1703 compatible = <<
1704 reg = <0x702d <<
1705 sound-name-pr <<
1706 status = "dis <<
1707 }; <<
1708 <<
1709 tegra_mvc2: mvc@702da <<
1710 compatible = <<
1711 reg = <0x702d <<
1712 sound-name-pr <<
1713 status = "dis <<
1714 }; <<
1715 <<
1716 tegra_amixer: amixer@ <<
1717 compatible = <<
1718 reg = <0x702d <<
1719 sound-name-pr <<
1720 status = "dis <<
1721 }; <<
1722 <<
1723 ports { <<
1724 #address-cell <<
1725 #size-cells = <<
1726 <<
1727 port@0 { <<
1728 reg = <<
1729 <<
1730 xbar_ <<
1731 <<
1732 }; <<
1733 }; <<
1734 <<
1735 port@1 { <<
1736 reg = <<
1737 <<
1738 xbar_ <<
1739 <<
1740 }; <<
1741 }; <<
1742 <<
1743 port@2 { <<
1744 reg = <<
1745 <<
1746 xbar_ <<
1747 <<
1748 }; <<
1749 }; <<
1750 <<
1751 port@3 { <<
1752 reg = <<
1753 <<
1754 xbar_ <<
1755 <<
1756 }; <<
1757 }; <<
1758 <<
1759 port@4 { <<
1760 reg = <<
1761 xbar_ <<
1762 <<
1763 }; <<
1764 }; <<
1765 port@5 { <<
1766 reg = <<
1767 <<
1768 xbar_ <<
1769 <<
1770 }; <<
1771 }; <<
1772 <<
1773 port@6 { <<
1774 reg = <<
1775 <<
1776 xbar_ <<
1777 <<
1778 }; <<
1779 }; <<
1780 <<
1781 port@7 { <<
1782 reg = <<
1783 <<
1784 xbar_ <<
1785 <<
1786 }; <<
1787 }; <<
1788 <<
1789 port@8 { <<
1790 reg = <<
1791 <<
1792 xbar_ <<
1793 <<
1794 }; <<
1795 }; <<
1796 <<
1797 port@9 { <<
1798 reg = <<
1799 <<
1800 xbar_ <<
1801 <<
1802 }; <<
1803 }; <<
1804 }; <<
1805 }; <<
1806 <<
1807 adma: dma-controller@702e2000 <<
1808 compatible = "nvidia, 1218 compatible = "nvidia,tegra210-adma";
1809 reg = <0x702e2000 0x2 1219 reg = <0x702e2000 0x2000>;
1810 interrupt-parent = <& 1220 interrupt-parent = <&agic>;
1811 interrupts = <GIC_SPI 1221 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
1812 <GIC_SPI 1222 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
1813 <GIC_SPI 1223 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
1814 <GIC_SPI 1224 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
1815 <GIC_SPI 1225 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
1816 <GIC_SPI 1226 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
1817 <GIC_SPI 1227 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
1818 <GIC_SPI 1228 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
1819 <GIC_SPI 1229 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
1820 <GIC_SPI 1230 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
1821 <GIC_SPI 1231 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
1822 <GIC_SPI 1232 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
1823 <GIC_SPI 1233 <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
1824 <GIC_SPI 1234 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
1825 <GIC_SPI 1235 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
1826 <GIC_SPI 1236 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
1827 <GIC_SPI 1237 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
1828 <GIC_SPI 1238 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
1829 <GIC_SPI 1239 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
1830 <GIC_SPI 1240 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
1831 <GIC_SPI 1241 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
1832 <GIC_SPI 1242 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1833 #dma-cells = <1>; 1243 #dma-cells = <1>;
1834 clocks = <&tegra_car 1244 clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>;
1835 clock-names = "d_audi 1245 clock-names = "d_audio";
1836 status = "disabled"; 1246 status = "disabled";
1837 }; 1247 };
1838 1248
1839 agic: interrupt-controller@70 !! 1249 agic: agic@702f9000 {
1840 compatible = "nvidia, 1250 compatible = "nvidia,tegra210-agic";
1841 #interrupt-cells = <3 1251 #interrupt-cells = <3>;
1842 interrupt-controller; 1252 interrupt-controller;
1843 reg = <0x702f9000 0x1 1253 reg = <0x702f9000 0x1000>,
1844 <0x702fa000 0x2 1254 <0x702fa000 0x2000>;
1845 interrupts = <GIC_SPI 1255 interrupts = <GIC_SPI 102 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1846 clocks = <&tegra_car 1256 clocks = <&tegra_car TEGRA210_CLK_APE>;
1847 clock-names = "clk"; 1257 clock-names = "clk";
1848 status = "disabled"; 1258 status = "disabled";
1849 }; 1259 };
1850 }; 1260 };
1851 1261
1852 spi@70410000 { 1262 spi@70410000 {
1853 compatible = "nvidia,tegra210 1263 compatible = "nvidia,tegra210-qspi";
1854 reg = <0x0 0x70410000 0x0 0x1 1264 reg = <0x0 0x70410000 0x0 0x1000>;
1855 interrupts = <GIC_SPI 10 IRQ_ 1265 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1856 #address-cells = <1>; 1266 #address-cells = <1>;
1857 #size-cells = <0>; 1267 #size-cells = <0>;
1858 clocks = <&tegra_car TEGRA210 !! 1268 clocks = <&tegra_car TEGRA210_CLK_QSPI>;
1859 <&tegra_car TEGRA210 !! 1269 clock-names = "qspi";
1860 clock-names = "qspi", "qspi_o <<
1861 resets = <&tegra_car 211>; 1270 resets = <&tegra_car 211>;
>> 1271 reset-names = "qspi";
1862 dmas = <&apbdma 5>, <&apbdma 1272 dmas = <&apbdma 5>, <&apbdma 5>;
1863 dma-names = "rx", "tx"; 1273 dma-names = "rx", "tx";
1864 status = "disabled"; 1274 status = "disabled";
1865 }; 1275 };
1866 1276
1867 usb@7d000000 { 1277 usb@7d000000 {
1868 compatible = "nvidia,tegra210 !! 1278 compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci";
1869 reg = <0x0 0x7d000000 0x0 0x4 1279 reg = <0x0 0x7d000000 0x0 0x4000>;
1870 interrupts = <GIC_SPI 20 IRQ_ 1280 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1871 phy_type = "utmi"; 1281 phy_type = "utmi";
1872 clocks = <&tegra_car TEGRA210 1282 clocks = <&tegra_car TEGRA210_CLK_USBD>;
1873 clock-names = "usb"; 1283 clock-names = "usb";
1874 resets = <&tegra_car 22>; 1284 resets = <&tegra_car 22>;
1875 reset-names = "usb"; 1285 reset-names = "usb";
1876 nvidia,phy = <&phy1>; 1286 nvidia,phy = <&phy1>;
1877 status = "disabled"; 1287 status = "disabled";
1878 }; 1288 };
1879 1289
1880 phy1: usb-phy@7d000000 { 1290 phy1: usb-phy@7d000000 {
1881 compatible = "nvidia,tegra210 1291 compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy";
1882 reg = <0x0 0x7d000000 0x0 0x4 1292 reg = <0x0 0x7d000000 0x0 0x4000>,
1883 <0x0 0x7d000000 0x0 0x4 1293 <0x0 0x7d000000 0x0 0x4000>;
1884 phy_type = "utmi"; 1294 phy_type = "utmi";
1885 clocks = <&tegra_car TEGRA210 1295 clocks = <&tegra_car TEGRA210_CLK_USBD>,
1886 <&tegra_car TEGRA210 1296 <&tegra_car TEGRA210_CLK_PLL_U>,
1887 <&tegra_car TEGRA210 1297 <&tegra_car TEGRA210_CLK_USBD>;
1888 clock-names = "reg", "pll_u", 1298 clock-names = "reg", "pll_u", "utmi-pads";
1889 resets = <&tegra_car 22>, <&t 1299 resets = <&tegra_car 22>, <&tegra_car 22>;
1890 reset-names = "usb", "utmi-pa 1300 reset-names = "usb", "utmi-pads";
1891 nvidia,hssync-start-delay = < 1301 nvidia,hssync-start-delay = <0>;
1892 nvidia,idle-wait-delay = <17> 1302 nvidia,idle-wait-delay = <17>;
1893 nvidia,elastic-limit = <16>; 1303 nvidia,elastic-limit = <16>;
1894 nvidia,term-range-adj = <6>; 1304 nvidia,term-range-adj = <6>;
1895 nvidia,xcvr-setup = <9>; 1305 nvidia,xcvr-setup = <9>;
1896 nvidia,xcvr-lsfslew = <0>; 1306 nvidia,xcvr-lsfslew = <0>;
1897 nvidia,xcvr-lsrslew = <3>; 1307 nvidia,xcvr-lsrslew = <3>;
1898 nvidia,hssquelch-level = <2>; 1308 nvidia,hssquelch-level = <2>;
1899 nvidia,hsdiscon-level = <5>; 1309 nvidia,hsdiscon-level = <5>;
1900 nvidia,xcvr-hsslew = <12>; 1310 nvidia,xcvr-hsslew = <12>;
1901 nvidia,has-utmi-pad-registers 1311 nvidia,has-utmi-pad-registers;
1902 status = "disabled"; 1312 status = "disabled";
1903 }; 1313 };
1904 1314
1905 usb@7d004000 { 1315 usb@7d004000 {
1906 compatible = "nvidia,tegra210 !! 1316 compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci";
1907 reg = <0x0 0x7d004000 0x0 0x4 1317 reg = <0x0 0x7d004000 0x0 0x4000>;
1908 interrupts = <GIC_SPI 21 IRQ_ 1318 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
1909 phy_type = "utmi"; 1319 phy_type = "utmi";
1910 clocks = <&tegra_car TEGRA210 1320 clocks = <&tegra_car TEGRA210_CLK_USB2>;
1911 clock-names = "usb"; 1321 clock-names = "usb";
1912 resets = <&tegra_car 58>; 1322 resets = <&tegra_car 58>;
1913 reset-names = "usb"; 1323 reset-names = "usb";
1914 nvidia,phy = <&phy2>; 1324 nvidia,phy = <&phy2>;
1915 status = "disabled"; 1325 status = "disabled";
1916 }; 1326 };
1917 1327
1918 phy2: usb-phy@7d004000 { 1328 phy2: usb-phy@7d004000 {
1919 compatible = "nvidia,tegra210 1329 compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy";
1920 reg = <0x0 0x7d004000 0x0 0x4 1330 reg = <0x0 0x7d004000 0x0 0x4000>,
1921 <0x0 0x7d000000 0x0 0x4 1331 <0x0 0x7d000000 0x0 0x4000>;
1922 phy_type = "utmi"; 1332 phy_type = "utmi";
1923 clocks = <&tegra_car TEGRA210 1333 clocks = <&tegra_car TEGRA210_CLK_USB2>,
1924 <&tegra_car TEGRA210 1334 <&tegra_car TEGRA210_CLK_PLL_U>,
1925 <&tegra_car TEGRA210 1335 <&tegra_car TEGRA210_CLK_USBD>;
1926 clock-names = "reg", "pll_u", 1336 clock-names = "reg", "pll_u", "utmi-pads";
1927 resets = <&tegra_car 58>, <&t 1337 resets = <&tegra_car 58>, <&tegra_car 22>;
1928 reset-names = "usb", "utmi-pa 1338 reset-names = "usb", "utmi-pads";
1929 nvidia,hssync-start-delay = < 1339 nvidia,hssync-start-delay = <0>;
1930 nvidia,idle-wait-delay = <17> 1340 nvidia,idle-wait-delay = <17>;
1931 nvidia,elastic-limit = <16>; 1341 nvidia,elastic-limit = <16>;
1932 nvidia,term-range-adj = <6>; 1342 nvidia,term-range-adj = <6>;
1933 nvidia,xcvr-setup = <9>; 1343 nvidia,xcvr-setup = <9>;
1934 nvidia,xcvr-lsfslew = <0>; 1344 nvidia,xcvr-lsfslew = <0>;
1935 nvidia,xcvr-lsrslew = <3>; 1345 nvidia,xcvr-lsrslew = <3>;
1936 nvidia,hssquelch-level = <2>; 1346 nvidia,hssquelch-level = <2>;
1937 nvidia,hsdiscon-level = <5>; 1347 nvidia,hsdiscon-level = <5>;
1938 nvidia,xcvr-hsslew = <12>; 1348 nvidia,xcvr-hsslew = <12>;
1939 status = "disabled"; 1349 status = "disabled";
1940 }; 1350 };
1941 1351
1942 cpus { 1352 cpus {
1943 #address-cells = <1>; 1353 #address-cells = <1>;
1944 #size-cells = <0>; 1354 #size-cells = <0>;
1945 1355
1946 cpu@0 { 1356 cpu@0 {
1947 device_type = "cpu"; 1357 device_type = "cpu";
1948 compatible = "arm,cor 1358 compatible = "arm,cortex-a57";
1949 reg = <0>; 1359 reg = <0>;
1950 clocks = <&tegra_car 1360 clocks = <&tegra_car TEGRA210_CLK_CCLK_G>,
1951 <&tegra_car 1361 <&tegra_car TEGRA210_CLK_PLL_X>,
1952 <&tegra_car 1362 <&tegra_car TEGRA210_CLK_PLL_P_OUT4>,
1953 <&dfll>; 1363 <&dfll>;
1954 clock-names = "cpu_g" 1364 clock-names = "cpu_g", "pll_x", "pll_p", "dfll";
1955 clock-latency = <3000 1365 clock-latency = <300000>;
1956 cpu-idle-states = <&C <<
1957 next-level-cache = <& <<
1958 }; 1366 };
1959 1367
1960 cpu@1 { 1368 cpu@1 {
1961 device_type = "cpu"; 1369 device_type = "cpu";
1962 compatible = "arm,cor 1370 compatible = "arm,cortex-a57";
1963 reg = <1>; 1371 reg = <1>;
1964 cpu-idle-states = <&C <<
1965 next-level-cache = <& <<
1966 }; 1372 };
1967 1373
1968 cpu@2 { 1374 cpu@2 {
1969 device_type = "cpu"; 1375 device_type = "cpu";
1970 compatible = "arm,cor 1376 compatible = "arm,cortex-a57";
1971 reg = <2>; 1377 reg = <2>;
1972 cpu-idle-states = <&C <<
1973 next-level-cache = <& <<
1974 }; 1378 };
1975 1379
1976 cpu@3 { 1380 cpu@3 {
1977 device_type = "cpu"; 1381 device_type = "cpu";
1978 compatible = "arm,cor 1382 compatible = "arm,cortex-a57";
1979 reg = <3>; 1383 reg = <3>;
1980 cpu-idle-states = <&C <<
1981 next-level-cache = <& <<
1982 }; <<
1983 <<
1984 idle-states { <<
1985 entry-method = "psci" <<
1986 <<
1987 CPU_SLEEP: cpu-sleep <<
1988 compatible = <<
1989 arm,psci-susp <<
1990 entry-latency <<
1991 exit-latency- <<
1992 min-residency <<
1993 wakeup-latenc <<
1994 idle-state-na <<
1995 status = "dis <<
1996 }; <<
1997 }; <<
1998 <<
1999 L2: l2-cache { <<
2000 compatible = "cache"; <<
2001 cache-level = <2>; <<
2002 cache-unified; <<
2003 }; 1384 };
2004 }; 1385 };
2005 1386
2006 pmu { !! 1387 timer {
2007 compatible = "arm,cortex-a57- !! 1388 compatible = "arm,armv8-timer";
2008 interrupts = <GIC_SPI 144 IRQ !! 1389 interrupts = <GIC_PPI 13
2009 <GIC_SPI 145 IRQ !! 1390 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2010 <GIC_SPI 146 IRQ !! 1391 <GIC_PPI 14
2011 <GIC_SPI 147 IRQ !! 1392 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2012 interrupt-affinity = <&{/cpus !! 1393 <GIC_PPI 11
2013 &{/cpus !! 1394 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
>> 1395 <GIC_PPI 10
>> 1396 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
>> 1397 interrupt-parent = <&gic>;
2014 }; 1398 };
2015 1399
2016 sound { !! 1400 soctherm: thermal-sensor@700e2000 {
2017 status = "disabled"; !! 1401 compatible = "nvidia,tegra210-soctherm";
>> 1402 reg = <0x0 0x700e2000 0x0 0x600 /* SOC_THERM reg_base */
>> 1403 0x0 0x60006000 0x0 0x400>; /* CAR reg_base */
>> 1404 reg-names = "soctherm-reg", "car-reg";
>> 1405 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
>> 1406 clocks = <&tegra_car TEGRA210_CLK_TSENSOR>,
>> 1407 <&tegra_car TEGRA210_CLK_SOC_THERM>;
>> 1408 clock-names = "tsensor", "soctherm";
>> 1409 resets = <&tegra_car 78>;
>> 1410 reset-names = "soctherm";
>> 1411 #thermal-sensor-cells = <1>;
2018 1412
2019 clocks = <&tegra_car TEGRA210 !! 1413 throttle-cfgs {
2020 <&tegra_car TEGRA210 !! 1414 throttle_heavy: heavy {
2021 clock-names = "pll_a", "plla_ !! 1415 nvidia,priority = <100>;
>> 1416 nvidia,cpu-throt-percent = <85>;
2022 1417
2023 assigned-clocks = <&tegra_car !! 1418 #cooling-cells = <2>;
2024 <&tegra_car !! 1419 };
2025 <&tegra_car !! 1420 };
2026 assigned-clock-parents = <0>, <<
2027 assigned-clock-rates = <36864 <<
2028 }; 1421 };
2029 1422
2030 thermal-zones { 1423 thermal-zones {
2031 cpu-thermal { !! 1424 cpu {
2032 polling-delay-passive 1425 polling-delay-passive = <1000>;
2033 polling-delay = <0>; 1426 polling-delay = <0>;
2034 1427
2035 thermal-sensors = 1428 thermal-sensors =
2036 <&soctherm TE 1429 <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>;
2037 1430
2038 trips { 1431 trips {
2039 cpu-shutdown- 1432 cpu-shutdown-trip {
2040 tempe 1433 temperature = <102500>;
2041 hyste 1434 hysteresis = <0>;
2042 type 1435 type = "critical";
2043 }; 1436 };
2044 1437
2045 cpu_throttle_ 1438 cpu_throttle_trip: throttle-trip {
2046 tempe 1439 temperature = <98500>;
2047 hyste 1440 hysteresis = <1000>;
2048 type 1441 type = "hot";
2049 }; 1442 };
2050 }; 1443 };
2051 1444
2052 cooling-maps { 1445 cooling-maps {
2053 map0 { 1446 map0 {
2054 trip 1447 trip = <&cpu_throttle_trip>;
2055 cooli 1448 cooling-device = <&throttle_heavy 1 1>;
2056 }; 1449 };
2057 }; 1450 };
2058 }; 1451 };
2059 !! 1452 mem {
2060 mem-thermal { <<
2061 polling-delay-passive 1453 polling-delay-passive = <0>;
2062 polling-delay = <0>; 1454 polling-delay = <0>;
2063 1455
2064 thermal-sensors = 1456 thermal-sensors =
2065 <&soctherm TE 1457 <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>;
2066 1458
2067 trips { 1459 trips {
2068 dram_nominal: <<
2069 tempe <<
2070 hyste <<
2071 type <<
2072 }; <<
2073 <<
2074 dram_throttle <<
2075 tempe <<
2076 hyste <<
2077 type <<
2078 }; <<
2079 <<
2080 mem-hot-trip <<
2081 tempe <<
2082 hyste <<
2083 type <<
2084 }; <<
2085 <<
2086 mem-shutdown- 1460 mem-shutdown-trip {
2087 tempe 1461 temperature = <103000>;
2088 hyste 1462 hysteresis = <0>;
2089 type 1463 type = "critical";
2090 }; 1464 };
2091 }; 1465 };
2092 1466
2093 cooling-maps { 1467 cooling-maps {
2094 dram-passive !! 1468 /*
2095 cooli !! 1469 * There are currently no cooling maps,
2096 trip !! 1470 * because there are no cooling devices.
2097 }; !! 1471 */
2098 <<
2099 dram-active { <<
2100 cooli <<
2101 trip <<
2102 }; <<
2103 }; 1472 };
2104 }; 1473 };
2105 !! 1474 gpu {
2106 gpu-thermal { <<
2107 polling-delay-passive 1475 polling-delay-passive = <1000>;
2108 polling-delay = <0>; 1476 polling-delay = <0>;
2109 1477
2110 thermal-sensors = 1478 thermal-sensors =
2111 <&soctherm TE 1479 <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>;
2112 1480
2113 trips { 1481 trips {
2114 gpu-shutdown- 1482 gpu-shutdown-trip {
2115 tempe 1483 temperature = <103000>;
2116 hyste 1484 hysteresis = <0>;
2117 type 1485 type = "critical";
2118 }; 1486 };
2119 1487
2120 gpu_throttle_ 1488 gpu_throttle_trip: throttle-trip {
2121 tempe 1489 temperature = <100000>;
2122 hyste 1490 hysteresis = <1000>;
2123 type 1491 type = "hot";
2124 }; 1492 };
2125 }; 1493 };
2126 1494
2127 cooling-maps { 1495 cooling-maps {
2128 map0 { 1496 map0 {
2129 trip 1497 trip = <&gpu_throttle_trip>;
2130 cooli 1498 cooling-device = <&throttle_heavy 1 1>;
2131 }; 1499 };
2132 }; 1500 };
2133 }; 1501 };
2134 !! 1502 pllx {
2135 pllx-thermal { <<
2136 polling-delay-passive 1503 polling-delay-passive = <0>;
2137 polling-delay = <0>; 1504 polling-delay = <0>;
2138 1505
2139 thermal-sensors = 1506 thermal-sensors =
2140 <&soctherm TE 1507 <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>;
2141 1508
2142 trips { 1509 trips {
2143 pllx-shutdown 1510 pllx-shutdown-trip {
2144 tempe 1511 temperature = <103000>;
2145 hyste 1512 hysteresis = <0>;
2146 type 1513 type = "critical";
2147 }; 1514 };
2148 <<
2149 pllx-throttle <<
2150 tempe <<
2151 hyste <<
2152 type <<
2153 }; <<
2154 }; 1515 };
2155 1516
2156 cooling-maps { 1517 cooling-maps {
2157 /* 1518 /*
2158 * There are 1519 * There are currently no cooling maps,
2159 * because th 1520 * because there are no cooling devices.
2160 */ 1521 */
2161 }; 1522 };
2162 }; 1523 };
2163 }; <<
2164 <<
2165 timer { <<
2166 compatible = "arm,armv8-timer <<
2167 interrupts = <GIC_PPI 13 <<
2168 (GIC_CPU_MASK <<
2169 <GIC_PPI 14 <<
2170 (GIC_CPU_MASK <<
2171 <GIC_PPI 11 <<
2172 (GIC_CPU_MASK <<
2173 <GIC_PPI 10 <<
2174 (GIC_CPU_MASK <<
2175 interrupt-parent = <&gic>; <<
2176 arm,no-tick-in-suspend; <<
2177 }; 1524 };
2178 }; 1525 };
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