1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra210-car.h> 2 #include <dt-bindings/clock/tegra210-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h> 3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra210-mc.h> 4 #include <dt-bindings/memory/tegra210-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h> 5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra-io 6 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
7 #include <dt-bindings/reset/tegra210-car.h> 7 #include <dt-bindings/reset/tegra210-car.h>
8 #include <dt-bindings/interrupt-controller/arm 8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/thermal/tegra124-socther 9 #include <dt-bindings/thermal/tegra124-soctherm.h>
10 #include <dt-bindings/soc/tegra-pmc.h> 10 #include <dt-bindings/soc/tegra-pmc.h>
11 11
12 / { 12 / {
13 compatible = "nvidia,tegra210"; 13 compatible = "nvidia,tegra210";
14 interrupt-parent = <&lic>; 14 interrupt-parent = <&lic>;
15 #address-cells = <2>; 15 #address-cells = <2>;
16 #size-cells = <2>; 16 #size-cells = <2>;
17 17
18 pcie@1003000 { 18 pcie@1003000 {
19 compatible = "nvidia,tegra210- 19 compatible = "nvidia,tegra210-pcie";
20 device_type = "pci"; 20 device_type = "pci";
21 reg = <0x0 0x01003000 0x0 0x00 21 reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */
22 <0x0 0x01003800 0x0 0x00 22 <0x0 0x01003800 0x0 0x00000800>, /* AFI registers */
23 <0x0 0x02000000 0x0 0x10 23 <0x0 0x02000000 0x0 0x10000000>; /* configuration space */
24 reg-names = "pads", "afi", "cs 24 reg-names = "pads", "afi", "cs";
25 interrupts = <GIC_SPI 98 IRQ_T 25 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
26 <GIC_SPI 99 IRQ_T 26 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
27 interrupt-names = "intr", "msi 27 interrupt-names = "intr", "msi";
28 28
29 #interrupt-cells = <1>; 29 #interrupt-cells = <1>;
30 interrupt-map-mask = <0 0 0 0> 30 interrupt-map-mask = <0 0 0 0>;
31 interrupt-map = <0 0 0 0 &gic 31 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
32 32
33 bus-range = <0x00 0xff>; 33 bus-range = <0x00 0xff>;
34 #address-cells = <3>; 34 #address-cells = <3>;
35 #size-cells = <2>; 35 #size-cells = <2>;
36 36
37 ranges = <0x02000000 0 0x01000 37 ranges = <0x02000000 0 0x01000000 0x0 0x01000000 0 0x00001000>, /* port 0 configuration space */
38 <0x02000000 0 0x01001 38 <0x02000000 0 0x01001000 0x0 0x01001000 0 0x00001000>, /* port 1 configuration space */
39 <0x01000000 0 0x0 39 <0x01000000 0 0x0 0x0 0x12000000 0 0x00010000>, /* downstream I/O (64 KiB) */
40 <0x02000000 0 0x13000 40 <0x02000000 0 0x13000000 0x0 0x13000000 0 0x0d000000>, /* non-prefetchable memory (208 MiB) */
41 <0x42000000 0 0x20000 41 <0x42000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
42 42
43 clocks = <&tegra_car TEGRA210_ 43 clocks = <&tegra_car TEGRA210_CLK_PCIE>,
44 <&tegra_car TEGRA210_ 44 <&tegra_car TEGRA210_CLK_AFI>,
45 <&tegra_car TEGRA210_ 45 <&tegra_car TEGRA210_CLK_PLL_E>,
46 <&tegra_car TEGRA210_ 46 <&tegra_car TEGRA210_CLK_CML0>;
47 clock-names = "pex", "afi", "p 47 clock-names = "pex", "afi", "pll_e", "cml";
48 resets = <&tegra_car 70>, 48 resets = <&tegra_car 70>,
49 <&tegra_car 72>, 49 <&tegra_car 72>,
50 <&tegra_car 74>; 50 <&tegra_car 74>;
51 reset-names = "pex", "afi", "p 51 reset-names = "pex", "afi", "pcie_x";
52 52
53 pinctrl-names = "default", "id 53 pinctrl-names = "default", "idle";
54 pinctrl-0 = <&pex_dpd_disable> 54 pinctrl-0 = <&pex_dpd_disable>;
55 pinctrl-1 = <&pex_dpd_enable>; 55 pinctrl-1 = <&pex_dpd_enable>;
56 56
57 status = "disabled"; 57 status = "disabled";
58 58
59 pci@1,0 { 59 pci@1,0 {
60 device_type = "pci"; 60 device_type = "pci";
61 assigned-addresses = < 61 assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
62 reg = <0x000800 0 0 0 62 reg = <0x000800 0 0 0 0>;
63 bus-range = <0x00 0xff 63 bus-range = <0x00 0xff>;
64 status = "disabled"; 64 status = "disabled";
65 65
66 #address-cells = <3>; 66 #address-cells = <3>;
67 #size-cells = <2>; 67 #size-cells = <2>;
68 ranges; 68 ranges;
69 69
70 nvidia,num-lanes = <4> 70 nvidia,num-lanes = <4>;
71 }; 71 };
72 72
73 pci@2,0 { 73 pci@2,0 {
74 device_type = "pci"; 74 device_type = "pci";
75 assigned-addresses = < 75 assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
76 reg = <0x001000 0 0 0 76 reg = <0x001000 0 0 0 0>;
77 bus-range = <0x00 0xff 77 bus-range = <0x00 0xff>;
78 status = "disabled"; 78 status = "disabled";
79 79
80 #address-cells = <3>; 80 #address-cells = <3>;
81 #size-cells = <2>; 81 #size-cells = <2>;
82 ranges; 82 ranges;
83 83
84 nvidia,num-lanes = <1> 84 nvidia,num-lanes = <1>;
85 }; 85 };
86 }; 86 };
87 87
88 host1x@50000000 { 88 host1x@50000000 {
89 compatible = "nvidia,tegra210- 89 compatible = "nvidia,tegra210-host1x";
90 reg = <0x0 0x50000000 0x0 0x00 90 reg = <0x0 0x50000000 0x0 0x00034000>;
91 interrupts = <GIC_SPI 65 IRQ_T 91 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
92 <GIC_SPI 67 IRQ_T 92 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
93 interrupt-names = "syncpt", "h 93 interrupt-names = "syncpt", "host1x";
94 clocks = <&tegra_car TEGRA210_ 94 clocks = <&tegra_car TEGRA210_CLK_HOST1X>;
95 clock-names = "host1x"; 95 clock-names = "host1x";
96 resets = <&tegra_car 28>, <&mc !! 96 resets = <&tegra_car 28>;
97 reset-names = "host1x", "mc"; !! 97 reset-names = "host1x";
98 98
99 #address-cells = <2>; 99 #address-cells = <2>;
100 #size-cells = <2>; 100 #size-cells = <2>;
101 101
102 ranges = <0x0 0x54000000 0x0 0 102 ranges = <0x0 0x54000000 0x0 0x54000000 0x0 0x01000000>;
103 103
104 iommus = <&mc TEGRA_SWGROUP_HC 104 iommus = <&mc TEGRA_SWGROUP_HC>;
105 105
106 dpaux1: dpaux@54040000 { 106 dpaux1: dpaux@54040000 {
107 compatible = "nvidia,t 107 compatible = "nvidia,tegra210-dpaux";
108 reg = <0x0 0x54040000 108 reg = <0x0 0x54040000 0x0 0x00040000>;
109 interrupts = <GIC_SPI 109 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
110 clocks = <&tegra_car T 110 clocks = <&tegra_car TEGRA210_CLK_DPAUX1>,
111 <&tegra_car T 111 <&tegra_car TEGRA210_CLK_PLL_DP>;
112 clock-names = "dpaux", 112 clock-names = "dpaux", "parent";
113 resets = <&tegra_car 2 113 resets = <&tegra_car 207>;
114 reset-names = "dpaux"; 114 reset-names = "dpaux";
115 power-domains = <&pd_s 115 power-domains = <&pd_sor>;
116 status = "disabled"; 116 status = "disabled";
117 117
118 state_dpaux1_aux: pinm 118 state_dpaux1_aux: pinmux-aux {
119 groups = "dpau 119 groups = "dpaux-io";
120 function = "au 120 function = "aux";
121 }; 121 };
122 122
123 state_dpaux1_i2c: pinm 123 state_dpaux1_i2c: pinmux-i2c {
124 groups = "dpau 124 groups = "dpaux-io";
125 function = "i2 125 function = "i2c";
126 }; 126 };
127 127
128 state_dpaux1_off: pinm 128 state_dpaux1_off: pinmux-off {
129 groups = "dpau 129 groups = "dpaux-io";
130 function = "of 130 function = "off";
131 }; 131 };
132 132
133 i2c-bus { 133 i2c-bus {
134 #address-cells 134 #address-cells = <1>;
135 #size-cells = 135 #size-cells = <0>;
136 }; 136 };
137 }; 137 };
138 138
139 vi@54080000 { 139 vi@54080000 {
140 compatible = "nvidia,t 140 compatible = "nvidia,tegra210-vi";
141 reg = <0x0 0x54080000 141 reg = <0x0 0x54080000 0x0 0x700>;
142 interrupts = <GIC_SPI 142 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
143 status = "disabled"; 143 status = "disabled";
144 assigned-clocks = <&te 144 assigned-clocks = <&tegra_car TEGRA210_CLK_VI>;
145 assigned-clock-parents 145 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
146 146
147 clocks = <&tegra_car T 147 clocks = <&tegra_car TEGRA210_CLK_VI>;
148 power-domains = <&pd_v 148 power-domains = <&pd_venc>;
149 149
150 #address-cells = <1>; 150 #address-cells = <1>;
151 #size-cells = <1>; 151 #size-cells = <1>;
152 152
153 ranges = <0x0 0x0 0x54 153 ranges = <0x0 0x0 0x54080000 0x2000>;
154 154
155 csi@838 { 155 csi@838 {
156 compatible = " 156 compatible = "nvidia,tegra210-csi";
157 reg = <0x838 0 157 reg = <0x838 0x1300>;
158 status = "disa 158 status = "disabled";
159 assigned-clock 159 assigned-clocks = <&tegra_car TEGRA210_CLK_CILAB>,
160 160 <&tegra_car TEGRA210_CLK_CILCD>,
161 161 <&tegra_car TEGRA210_CLK_CILE>,
162 162 <&tegra_car TEGRA210_CLK_CSI_TPG>;
163 assigned-clock 163 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>,
164 164 <&tegra_car TEGRA210_CLK_PLL_P>,
165 165 <&tegra_car TEGRA210_CLK_PLL_P>;
166 assigned-clock 166 assigned-clock-rates = <102000000>,
167 167 <102000000>,
168 168 <102000000>,
169 169 <972000000>;
170 170
171 clocks = <&teg 171 clocks = <&tegra_car TEGRA210_CLK_CSI>,
172 <&teg 172 <&tegra_car TEGRA210_CLK_CILAB>,
173 <&teg 173 <&tegra_car TEGRA210_CLK_CILCD>,
174 <&teg 174 <&tegra_car TEGRA210_CLK_CILE>,
175 <&teg 175 <&tegra_car TEGRA210_CLK_CSI_TPG>;
176 clock-names = 176 clock-names = "csi", "cilab", "cilcd", "cile", "csi_tpg";
177 power-domains 177 power-domains = <&pd_sor>;
178 }; 178 };
179 }; 179 };
180 180
181 tsec@54100000 { 181 tsec@54100000 {
182 compatible = "nvidia,t 182 compatible = "nvidia,tegra210-tsec";
183 reg = <0x0 0x54100000 183 reg = <0x0 0x54100000 0x0 0x00040000>;
184 interrupts = <GIC_SPI <<
185 clocks = <&tegra_car T <<
186 clock-names = "tsec"; <<
187 resets = <&tegra_car 8 <<
188 reset-names = "tsec"; <<
189 status = "disabled"; <<
190 }; 184 };
191 185
192 dc@54200000 { 186 dc@54200000 {
193 compatible = "nvidia,t 187 compatible = "nvidia,tegra210-dc";
194 reg = <0x0 0x54200000 188 reg = <0x0 0x54200000 0x0 0x00040000>;
195 interrupts = <GIC_SPI 189 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
196 clocks = <&tegra_car T 190 clocks = <&tegra_car TEGRA210_CLK_DISP1>;
197 clock-names = "dc"; 191 clock-names = "dc";
198 resets = <&tegra_car 2 192 resets = <&tegra_car 27>;
199 reset-names = "dc"; 193 reset-names = "dc";
200 194
201 iommus = <&mc TEGRA_SW 195 iommus = <&mc TEGRA_SWGROUP_DC>;
202 196
203 nvidia,outputs = <&dsi 197 nvidia,outputs = <&dsia &dsib &sor0 &sor1>;
204 nvidia,head = <0>; 198 nvidia,head = <0>;
205 }; 199 };
206 200
207 dc@54240000 { 201 dc@54240000 {
208 compatible = "nvidia,t 202 compatible = "nvidia,tegra210-dc";
209 reg = <0x0 0x54240000 203 reg = <0x0 0x54240000 0x0 0x00040000>;
210 interrupts = <GIC_SPI 204 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
211 clocks = <&tegra_car T 205 clocks = <&tegra_car TEGRA210_CLK_DISP2>;
212 clock-names = "dc"; 206 clock-names = "dc";
213 resets = <&tegra_car 2 207 resets = <&tegra_car 26>;
214 reset-names = "dc"; 208 reset-names = "dc";
215 209
216 iommus = <&mc TEGRA_SW 210 iommus = <&mc TEGRA_SWGROUP_DCB>;
217 211
218 nvidia,outputs = <&dsi 212 nvidia,outputs = <&dsia &dsib &sor0 &sor1>;
219 nvidia,head = <1>; 213 nvidia,head = <1>;
220 }; 214 };
221 215
222 dsia: dsi@54300000 { 216 dsia: dsi@54300000 {
223 compatible = "nvidia,t 217 compatible = "nvidia,tegra210-dsi";
224 reg = <0x0 0x54300000 218 reg = <0x0 0x54300000 0x0 0x00040000>;
225 clocks = <&tegra_car T 219 clocks = <&tegra_car TEGRA210_CLK_DSIA>,
226 <&tegra_car T 220 <&tegra_car TEGRA210_CLK_DSIALP>,
227 <&tegra_car T 221 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>;
228 clock-names = "dsi", " 222 clock-names = "dsi", "lp", "parent";
229 resets = <&tegra_car 4 223 resets = <&tegra_car 48>;
230 reset-names = "dsi"; 224 reset-names = "dsi";
231 power-domains = <&pd_s 225 power-domains = <&pd_sor>;
232 nvidia,mipi-calibrate 226 nvidia,mipi-calibrate = <&mipi 0x0c0>; /* DSIA & DSIB pads */
233 227
234 status = "disabled"; 228 status = "disabled";
235 229
236 #address-cells = <1>; 230 #address-cells = <1>;
237 #size-cells = <0>; 231 #size-cells = <0>;
238 }; 232 };
239 233
240 vic@54340000 { 234 vic@54340000 {
241 compatible = "nvidia,t 235 compatible = "nvidia,tegra210-vic";
242 reg = <0x0 0x54340000 236 reg = <0x0 0x54340000 0x0 0x00040000>;
243 interrupts = <GIC_SPI 237 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
244 clocks = <&tegra_car T 238 clocks = <&tegra_car TEGRA210_CLK_VIC03>;
245 clock-names = "vic"; 239 clock-names = "vic";
246 resets = <&tegra_car 1 240 resets = <&tegra_car 178>;
247 reset-names = "vic"; 241 reset-names = "vic";
248 242
249 iommus = <&mc TEGRA_SW 243 iommus = <&mc TEGRA_SWGROUP_VIC>;
250 power-domains = <&pd_v 244 power-domains = <&pd_vic>;
251 }; 245 };
252 246
253 nvjpg@54380000 { 247 nvjpg@54380000 {
254 compatible = "nvidia,t 248 compatible = "nvidia,tegra210-nvjpg";
255 reg = <0x0 0x54380000 249 reg = <0x0 0x54380000 0x0 0x00040000>;
256 status = "disabled"; 250 status = "disabled";
257 }; 251 };
258 252
259 dsib: dsi@54400000 { 253 dsib: dsi@54400000 {
260 compatible = "nvidia,t 254 compatible = "nvidia,tegra210-dsi";
261 reg = <0x0 0x54400000 255 reg = <0x0 0x54400000 0x0 0x00040000>;
262 clocks = <&tegra_car T 256 clocks = <&tegra_car TEGRA210_CLK_DSIB>,
263 <&tegra_car T 257 <&tegra_car TEGRA210_CLK_DSIBLP>,
264 <&tegra_car T 258 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>;
265 clock-names = "dsi", " 259 clock-names = "dsi", "lp", "parent";
266 resets = <&tegra_car 8 260 resets = <&tegra_car 82>;
267 reset-names = "dsi"; 261 reset-names = "dsi";
268 power-domains = <&pd_s 262 power-domains = <&pd_sor>;
269 nvidia,mipi-calibrate 263 nvidia,mipi-calibrate = <&mipi 0x300>; /* DSIC & DSID pads */
270 264
271 status = "disabled"; 265 status = "disabled";
272 266
273 #address-cells = <1>; 267 #address-cells = <1>;
274 #size-cells = <0>; 268 #size-cells = <0>;
275 }; 269 };
276 270
277 nvdec@54480000 { 271 nvdec@54480000 {
278 compatible = "nvidia,t 272 compatible = "nvidia,tegra210-nvdec";
279 reg = <0x0 0x54480000 273 reg = <0x0 0x54480000 0x0 0x00040000>;
280 status = "disabled"; 274 status = "disabled";
281 }; 275 };
282 276
283 nvenc@544c0000 { 277 nvenc@544c0000 {
284 compatible = "nvidia,t 278 compatible = "nvidia,tegra210-nvenc";
285 reg = <0x0 0x544c0000 279 reg = <0x0 0x544c0000 0x0 0x00040000>;
286 status = "disabled"; 280 status = "disabled";
287 }; 281 };
288 282
289 tsec@54500000 { 283 tsec@54500000 {
290 compatible = "nvidia,t 284 compatible = "nvidia,tegra210-tsec";
291 reg = <0x0 0x54500000 285 reg = <0x0 0x54500000 0x0 0x00040000>;
292 interrupts = <GIC_SPI <<
293 clocks = <&tegra_car T <<
294 clock-names = "tsec"; <<
295 resets = <&tegra_car 2 <<
296 reset-names = "tsec"; <<
297 status = "disabled"; 286 status = "disabled";
298 }; 287 };
299 288
300 sor0: sor@54540000 { 289 sor0: sor@54540000 {
301 compatible = "nvidia,t 290 compatible = "nvidia,tegra210-sor";
302 reg = <0x0 0x54540000 291 reg = <0x0 0x54540000 0x0 0x00040000>;
303 interrupts = <GIC_SPI 292 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
304 clocks = <&tegra_car T 293 clocks = <&tegra_car TEGRA210_CLK_SOR0>,
305 <&tegra_car T 294 <&tegra_car TEGRA210_CLK_SOR0_OUT>,
306 <&tegra_car T 295 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>,
307 <&tegra_car T 296 <&tegra_car TEGRA210_CLK_PLL_DP>,
308 <&tegra_car T 297 <&tegra_car TEGRA210_CLK_SOR_SAFE>;
309 clock-names = "sor", " 298 clock-names = "sor", "out", "parent", "dp", "safe";
310 resets = <&tegra_car 1 299 resets = <&tegra_car 182>;
311 reset-names = "sor"; 300 reset-names = "sor";
312 pinctrl-0 = <&state_dp 301 pinctrl-0 = <&state_dpaux_aux>;
313 pinctrl-1 = <&state_dp 302 pinctrl-1 = <&state_dpaux_i2c>;
314 pinctrl-2 = <&state_dp 303 pinctrl-2 = <&state_dpaux_off>;
315 pinctrl-names = "aux", 304 pinctrl-names = "aux", "i2c", "off";
316 power-domains = <&pd_s 305 power-domains = <&pd_sor>;
317 status = "disabled"; 306 status = "disabled";
318 }; 307 };
319 308
320 sor1: sor@54580000 { 309 sor1: sor@54580000 {
321 compatible = "nvidia,t 310 compatible = "nvidia,tegra210-sor1";
322 reg = <0x0 0x54580000 311 reg = <0x0 0x54580000 0x0 0x00040000>;
323 interrupts = <GIC_SPI 312 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
324 clocks = <&tegra_car T 313 clocks = <&tegra_car TEGRA210_CLK_SOR1>,
325 <&tegra_car T 314 <&tegra_car TEGRA210_CLK_SOR1_OUT>,
326 <&tegra_car T 315 <&tegra_car TEGRA210_CLK_PLL_D2_OUT0>,
327 <&tegra_car T 316 <&tegra_car TEGRA210_CLK_PLL_DP>,
328 <&tegra_car T 317 <&tegra_car TEGRA210_CLK_SOR_SAFE>;
329 clock-names = "sor", " 318 clock-names = "sor", "out", "parent", "dp", "safe";
330 resets = <&tegra_car 1 319 resets = <&tegra_car 183>;
331 reset-names = "sor"; 320 reset-names = "sor";
332 pinctrl-0 = <&state_dp 321 pinctrl-0 = <&state_dpaux1_aux>;
333 pinctrl-1 = <&state_dp 322 pinctrl-1 = <&state_dpaux1_i2c>;
334 pinctrl-2 = <&state_dp 323 pinctrl-2 = <&state_dpaux1_off>;
335 pinctrl-names = "aux", 324 pinctrl-names = "aux", "i2c", "off";
336 power-domains = <&pd_s 325 power-domains = <&pd_sor>;
337 status = "disabled"; 326 status = "disabled";
338 }; 327 };
339 328
340 dpaux: dpaux@545c0000 { 329 dpaux: dpaux@545c0000 {
341 compatible = "nvidia,t 330 compatible = "nvidia,tegra210-dpaux";
342 reg = <0x0 0x545c0000 331 reg = <0x0 0x545c0000 0x0 0x00040000>;
343 interrupts = <GIC_SPI 332 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
344 clocks = <&tegra_car T 333 clocks = <&tegra_car TEGRA210_CLK_DPAUX>,
345 <&tegra_car T 334 <&tegra_car TEGRA210_CLK_PLL_DP>;
346 clock-names = "dpaux", 335 clock-names = "dpaux", "parent";
347 resets = <&tegra_car 1 336 resets = <&tegra_car 181>;
348 reset-names = "dpaux"; 337 reset-names = "dpaux";
349 power-domains = <&pd_s 338 power-domains = <&pd_sor>;
350 status = "disabled"; 339 status = "disabled";
351 340
352 state_dpaux_aux: pinmu 341 state_dpaux_aux: pinmux-aux {
353 groups = "dpau 342 groups = "dpaux-io";
354 function = "au 343 function = "aux";
355 }; 344 };
356 345
357 state_dpaux_i2c: pinmu 346 state_dpaux_i2c: pinmux-i2c {
358 groups = "dpau 347 groups = "dpaux-io";
359 function = "i2 348 function = "i2c";
360 }; 349 };
361 350
362 state_dpaux_off: pinmu 351 state_dpaux_off: pinmux-off {
363 groups = "dpau 352 groups = "dpaux-io";
364 function = "of 353 function = "off";
365 }; 354 };
366 355
367 i2c-bus { 356 i2c-bus {
368 #address-cells 357 #address-cells = <1>;
369 #size-cells = 358 #size-cells = <0>;
370 }; 359 };
371 }; 360 };
372 361
373 isp@54600000 { 362 isp@54600000 {
374 compatible = "nvidia,t 363 compatible = "nvidia,tegra210-isp";
375 reg = <0x0 0x54600000 364 reg = <0x0 0x54600000 0x0 0x00040000>;
376 interrupts = <GIC_SPI 365 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
377 clocks = <&tegra_car T 366 clocks = <&tegra_car TEGRA210_CLK_ISPA>;
378 resets = <&tegra_car 2 367 resets = <&tegra_car 23>;
379 reset-names = "isp"; 368 reset-names = "isp";
380 status = "disabled"; 369 status = "disabled";
381 }; 370 };
382 371
383 isp@54680000 { 372 isp@54680000 {
384 compatible = "nvidia,t 373 compatible = "nvidia,tegra210-isp";
385 reg = <0x0 0x54680000 374 reg = <0x0 0x54680000 0x0 0x00040000>;
386 interrupts = <GIC_SPI 375 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
387 clocks = <&tegra_car T 376 clocks = <&tegra_car TEGRA210_CLK_ISPB>;
388 resets = <&tegra_car 3 377 resets = <&tegra_car 3>;
389 reset-names = "isp"; 378 reset-names = "isp";
390 status = "disabled"; 379 status = "disabled";
391 }; 380 };
392 381
393 i2c@546c0000 { 382 i2c@546c0000 {
394 compatible = "nvidia,t 383 compatible = "nvidia,tegra210-i2c-vi";
395 reg = <0x0 0x546c0000 384 reg = <0x0 0x546c0000 0x0 0x00040000>;
396 interrupts = <GIC_SPI 385 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
397 clocks = <&tegra_car T 386 clocks = <&tegra_car TEGRA210_CLK_VI_I2C>,
398 <&tegra_car T 387 <&tegra_car TEGRA210_CLK_I2CSLOW>;
399 clock-names = "div-clk 388 clock-names = "div-clk", "slow";
400 resets = <&tegra_car 2 389 resets = <&tegra_car 208>;
401 reset-names = "i2c"; 390 reset-names = "i2c";
402 power-domains = <&pd_v 391 power-domains = <&pd_venc>;
403 status = "disabled"; 392 status = "disabled";
404 393
405 #address-cells = <1>; 394 #address-cells = <1>;
406 #size-cells = <0>; 395 #size-cells = <0>;
407 }; 396 };
408 }; 397 };
409 398
410 gic: interrupt-controller@50041000 { 399 gic: interrupt-controller@50041000 {
411 compatible = "arm,gic-400"; 400 compatible = "arm,gic-400";
412 #interrupt-cells = <3>; 401 #interrupt-cells = <3>;
413 interrupt-controller; 402 interrupt-controller;
414 reg = <0x0 0x50041000 0x0 0x10 403 reg = <0x0 0x50041000 0x0 0x1000>,
415 <0x0 0x50042000 0x0 0x20 404 <0x0 0x50042000 0x0 0x2000>,
416 <0x0 0x50044000 0x0 0x20 405 <0x0 0x50044000 0x0 0x2000>,
417 <0x0 0x50046000 0x0 0x20 406 <0x0 0x50046000 0x0 0x2000>;
418 interrupts = <GIC_PPI 9 407 interrupts = <GIC_PPI 9
419 (GIC_CPU_MASK_SIMPLE(4 408 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
420 interrupt-parent = <&gic>; 409 interrupt-parent = <&gic>;
421 }; 410 };
422 411
423 gpu@57000000 { 412 gpu@57000000 {
424 compatible = "nvidia,gm20b"; 413 compatible = "nvidia,gm20b";
425 reg = <0x0 0x57000000 0x0 0x01 414 reg = <0x0 0x57000000 0x0 0x01000000>,
426 <0x0 0x58000000 0x0 0x01 415 <0x0 0x58000000 0x0 0x01000000>;
427 interrupts = <GIC_SPI 157 IRQ_ 416 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
428 <GIC_SPI 158 IRQ_ 417 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
429 interrupt-names = "stall", "no 418 interrupt-names = "stall", "nonstall";
430 clocks = <&tegra_car TEGRA210_ 419 clocks = <&tegra_car TEGRA210_CLK_GPU>,
431 <&tegra_car TEGRA210_ 420 <&tegra_car TEGRA210_CLK_PLL_P_OUT5>,
432 <&tegra_car TEGRA210_ 421 <&tegra_car TEGRA210_CLK_PLL_G_REF>;
433 clock-names = "gpu", "pwr", "r 422 clock-names = "gpu", "pwr", "ref";
434 resets = <&tegra_car 184>; 423 resets = <&tegra_car 184>;
435 reset-names = "gpu"; 424 reset-names = "gpu";
436 425
437 iommus = <&mc TEGRA_SWGROUP_GP 426 iommus = <&mc TEGRA_SWGROUP_GPU>;
438 427
439 status = "disabled"; 428 status = "disabled";
440 }; 429 };
441 430
442 lic: interrupt-controller@60004000 { 431 lic: interrupt-controller@60004000 {
443 compatible = "nvidia,tegra210- 432 compatible = "nvidia,tegra210-ictlr";
444 reg = <0x0 0x60004000 0x0 0x40 433 reg = <0x0 0x60004000 0x0 0x40>, /* primary controller */
445 <0x0 0x60004100 0x0 0x40 434 <0x0 0x60004100 0x0 0x40>, /* secondary controller */
446 <0x0 0x60004200 0x0 0x40 435 <0x0 0x60004200 0x0 0x40>, /* tertiary controller */
447 <0x0 0x60004300 0x0 0x40 436 <0x0 0x60004300 0x0 0x40>, /* quaternary controller */
448 <0x0 0x60004400 0x0 0x40 437 <0x0 0x60004400 0x0 0x40>, /* quinary controller */
449 <0x0 0x60004500 0x0 0x40 438 <0x0 0x60004500 0x0 0x40>; /* senary controller */
450 interrupt-controller; 439 interrupt-controller;
451 #interrupt-cells = <3>; 440 #interrupt-cells = <3>;
452 interrupt-parent = <&gic>; 441 interrupt-parent = <&gic>;
453 }; 442 };
454 443
455 timer@60005000 { 444 timer@60005000 {
456 compatible = "nvidia,tegra210- 445 compatible = "nvidia,tegra210-timer";
457 reg = <0x0 0x60005000 0x0 0x40 446 reg = <0x0 0x60005000 0x0 0x400>;
458 interrupts = <GIC_SPI 156 IRQ_ 447 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
459 <GIC_SPI 0 IRQ_TY 448 <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
460 <GIC_SPI 1 IRQ_TY 449 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
461 <GIC_SPI 41 IRQ_T 450 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
462 <GIC_SPI 42 IRQ_T 451 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
463 <GIC_SPI 121 IRQ_ 452 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
464 <GIC_SPI 152 IRQ_ 453 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
465 <GIC_SPI 153 IRQ_ 454 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
466 <GIC_SPI 154 IRQ_ 455 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
467 <GIC_SPI 155 IRQ_ 456 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
468 <GIC_SPI 176 IRQ_ 457 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
469 <GIC_SPI 177 IRQ_ 458 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
470 <GIC_SPI 178 IRQ_ 459 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
471 <GIC_SPI 179 IRQ_ 460 <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
472 clocks = <&tegra_car TEGRA210_ 461 clocks = <&tegra_car TEGRA210_CLK_TIMER>;
473 clock-names = "timer"; 462 clock-names = "timer";
474 }; 463 };
475 464
476 tegra_car: clock@60006000 { 465 tegra_car: clock@60006000 {
477 compatible = "nvidia,tegra210- 466 compatible = "nvidia,tegra210-car";
478 reg = <0x0 0x60006000 0x0 0x10 467 reg = <0x0 0x60006000 0x0 0x1000>;
479 #clock-cells = <1>; 468 #clock-cells = <1>;
480 #reset-cells = <1>; 469 #reset-cells = <1>;
481 }; 470 };
482 471
483 flow-controller@60007000 { 472 flow-controller@60007000 {
484 compatible = "nvidia,tegra210- 473 compatible = "nvidia,tegra210-flowctrl";
485 reg = <0x0 0x60007000 0x0 0x10 474 reg = <0x0 0x60007000 0x0 0x1000>;
486 }; 475 };
487 476
488 gpio: gpio@6000d000 { 477 gpio: gpio@6000d000 {
489 compatible = "nvidia,tegra210- 478 compatible = "nvidia,tegra210-gpio", "nvidia,tegra30-gpio";
490 reg = <0x0 0x6000d000 0x0 0x10 479 reg = <0x0 0x6000d000 0x0 0x1000>;
491 interrupts = <GIC_SPI 32 IRQ_T 480 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
492 <GIC_SPI 33 IRQ_T 481 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
493 <GIC_SPI 34 IRQ_T 482 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
494 <GIC_SPI 35 IRQ_T 483 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
495 <GIC_SPI 55 IRQ_T 484 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
496 <GIC_SPI 87 IRQ_T 485 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
497 <GIC_SPI 89 IRQ_T 486 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
498 <GIC_SPI 125 IRQ_ 487 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
499 #gpio-cells = <2>; 488 #gpio-cells = <2>;
500 gpio-controller; 489 gpio-controller;
501 #interrupt-cells = <2>; 490 #interrupt-cells = <2>;
502 interrupt-controller; 491 interrupt-controller;
503 }; 492 };
504 493
505 apbdma: dma@60020000 { 494 apbdma: dma@60020000 {
506 compatible = "nvidia,tegra210- 495 compatible = "nvidia,tegra210-apbdma", "nvidia,tegra148-apbdma";
507 reg = <0x0 0x60020000 0x0 0x14 496 reg = <0x0 0x60020000 0x0 0x1400>;
508 interrupts = <GIC_SPI 104 IRQ_ 497 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
509 <GIC_SPI 105 IRQ_ 498 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
510 <GIC_SPI 106 IRQ_ 499 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
511 <GIC_SPI 107 IRQ_ 500 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
512 <GIC_SPI 108 IRQ_ 501 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
513 <GIC_SPI 109 IRQ_ 502 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
514 <GIC_SPI 110 IRQ_ 503 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
515 <GIC_SPI 111 IRQ_ 504 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
516 <GIC_SPI 112 IRQ_ 505 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
517 <GIC_SPI 113 IRQ_ 506 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
518 <GIC_SPI 114 IRQ_ 507 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
519 <GIC_SPI 115 IRQ_ 508 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
520 <GIC_SPI 116 IRQ_ 509 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
521 <GIC_SPI 117 IRQ_ 510 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
522 <GIC_SPI 118 IRQ_ 511 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
523 <GIC_SPI 119 IRQ_ 512 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
524 <GIC_SPI 128 IRQ_ 513 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
525 <GIC_SPI 129 IRQ_ 514 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
526 <GIC_SPI 130 IRQ_ 515 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
527 <GIC_SPI 131 IRQ_ 516 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
528 <GIC_SPI 132 IRQ_ 517 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
529 <GIC_SPI 133 IRQ_ 518 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
530 <GIC_SPI 134 IRQ_ 519 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
531 <GIC_SPI 135 IRQ_ 520 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
532 <GIC_SPI 136 IRQ_ 521 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
533 <GIC_SPI 137 IRQ_ 522 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
534 <GIC_SPI 138 IRQ_ 523 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
535 <GIC_SPI 139 IRQ_ 524 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
536 <GIC_SPI 140 IRQ_ 525 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
537 <GIC_SPI 141 IRQ_ 526 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
538 <GIC_SPI 142 IRQ_ 527 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
539 <GIC_SPI 143 IRQ_ 528 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
540 clocks = <&tegra_car TEGRA210_ 529 clocks = <&tegra_car TEGRA210_CLK_APBDMA>;
541 clock-names = "dma"; 530 clock-names = "dma";
542 resets = <&tegra_car 34>; 531 resets = <&tegra_car 34>;
543 reset-names = "dma"; 532 reset-names = "dma";
544 #dma-cells = <1>; 533 #dma-cells = <1>;
545 }; 534 };
546 535
547 apbmisc@70000800 { 536 apbmisc@70000800 {
548 compatible = "nvidia,tegra210- 537 compatible = "nvidia,tegra210-apbmisc", "nvidia,tegra20-apbmisc";
549 reg = <0x0 0x70000800 0x0 0x64 538 reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */
550 <0x0 0x70000008 0x0 0x04 539 <0x0 0x70000008 0x0 0x04>; /* Strapping options */
551 }; 540 };
552 541
553 pinmux: pinmux@700008d4 { 542 pinmux: pinmux@700008d4 {
554 compatible = "nvidia,tegra210- 543 compatible = "nvidia,tegra210-pinmux";
555 reg = <0x0 0x700008d4 0x0 0x29 544 reg = <0x0 0x700008d4 0x0 0x29c>, /* Pad control registers */
556 <0x0 0x70003000 0x0 0x29 545 <0x0 0x70003000 0x0 0x294>; /* Mux registers */
557 !! 546 sdmmc1_3v3_drv: sdmmc1-3v3-drv {
558 sdmmc1_1v8_drv: pinmux-sdmmc1- <<
559 sdmmc1 { 547 sdmmc1 {
560 nvidia,pins = 548 nvidia,pins = "drive_sdmmc1";
561 nvidia,pull-do !! 549 nvidia,pull-down-strength = <0x8>;
562 nvidia,pull-up !! 550 nvidia,pull-up-strength = <0x8>;
563 }; 551 };
564 }; 552 };
565 !! 553 sdmmc1_1v8_drv: sdmmc1-1v8-drv {
566 sdmmc1_3v3_drv: pinmux-sdmmc1- <<
567 sdmmc1 { 554 sdmmc1 {
568 nvidia,pins = 555 nvidia,pins = "drive_sdmmc1";
569 nvidia,pull-do !! 556 nvidia,pull-down-strength = <0x4>;
570 nvidia,pull-up !! 557 nvidia,pull-up-strength = <0x3>;
571 }; 558 };
572 }; 559 };
573 !! 560 sdmmc2_1v8_drv: sdmmc2-1v8-drv {
574 sdmmc2_1v8_drv: pinmux-sdmmc2- <<
575 sdmmc2 { 561 sdmmc2 {
576 nvidia,pins = 562 nvidia,pins = "drive_sdmmc2";
577 nvidia,pull-do 563 nvidia,pull-down-strength = <0x10>;
578 nvidia,pull-up 564 nvidia,pull-up-strength = <0x10>;
579 }; 565 };
580 }; 566 };
581 !! 567 sdmmc3_3v3_drv: sdmmc3-3v3-drv {
582 sdmmc3_1v8_drv: pinmux-sdmmc3- <<
583 sdmmc3 { 568 sdmmc3 {
584 nvidia,pins = 569 nvidia,pins = "drive_sdmmc3";
585 nvidia,pull-do !! 570 nvidia,pull-down-strength = <0x8>;
586 nvidia,pull-up !! 571 nvidia,pull-up-strength = <0x8>;
587 }; 572 };
588 }; 573 };
589 !! 574 sdmmc3_1v8_drv: sdmmc3-1v8-drv {
590 sdmmc3_3v3_drv: pinmux-sdmmc3- <<
591 sdmmc3 { 575 sdmmc3 {
592 nvidia,pins = 576 nvidia,pins = "drive_sdmmc3";
593 nvidia,pull-do !! 577 nvidia,pull-down-strength = <0x4>;
594 nvidia,pull-up !! 578 nvidia,pull-up-strength = <0x3>;
595 }; 579 };
596 }; 580 };
597 !! 581 sdmmc4_1v8_drv: sdmmc4-1v8-drv {
598 sdmmc4_1v8_drv: pinmux-sdmmc4- <<
599 sdmmc4 { 582 sdmmc4 {
600 nvidia,pins = 583 nvidia,pins = "drive_sdmmc4";
601 nvidia,pull-do 584 nvidia,pull-down-strength = <0x10>;
602 nvidia,pull-up 585 nvidia,pull-up-strength = <0x10>;
603 }; 586 };
604 }; 587 };
605 }; 588 };
606 589
607 /* 590 /*
608 * There are two serial driver i.e. 82 591 * There are two serial driver i.e. 8250 based simple serial
609 * driver and APB DMA based serial dri 592 * driver and APB DMA based serial driver for higher baudrate
610 * and performance. To enable the 8250 593 * and performance. To enable the 8250 based driver, the compatible
611 * is "nvidia,tegra124-uart", "nvidia, 594 * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable
612 * the APB DMA based serial driver, th 595 * the APB DMA based serial driver, the compatible is
613 * "nvidia,tegra124-hsuart", "nvidia,t 596 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart".
614 */ 597 */
615 uarta: serial@70006000 { 598 uarta: serial@70006000 {
616 compatible = "nvidia,tegra210- 599 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
617 reg = <0x0 0x70006000 0x0 0x40 600 reg = <0x0 0x70006000 0x0 0x40>;
618 reg-shift = <2>; 601 reg-shift = <2>;
619 interrupts = <GIC_SPI 36 IRQ_T 602 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
620 clocks = <&tegra_car TEGRA210_ 603 clocks = <&tegra_car TEGRA210_CLK_UARTA>;
>> 604 clock-names = "serial";
621 resets = <&tegra_car 6>; 605 resets = <&tegra_car 6>;
>> 606 reset-names = "serial";
622 dmas = <&apbdma 8>, <&apbdma 8 607 dmas = <&apbdma 8>, <&apbdma 8>;
623 dma-names = "rx", "tx"; 608 dma-names = "rx", "tx";
624 status = "disabled"; 609 status = "disabled";
625 }; 610 };
626 611
627 uartb: serial@70006040 { 612 uartb: serial@70006040 {
628 compatible = "nvidia,tegra210- 613 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
629 reg = <0x0 0x70006040 0x0 0x40 614 reg = <0x0 0x70006040 0x0 0x40>;
630 reg-shift = <2>; 615 reg-shift = <2>;
631 interrupts = <GIC_SPI 37 IRQ_T 616 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
632 clocks = <&tegra_car TEGRA210_ 617 clocks = <&tegra_car TEGRA210_CLK_UARTB>;
>> 618 clock-names = "serial";
633 resets = <&tegra_car 7>; 619 resets = <&tegra_car 7>;
>> 620 reset-names = "serial";
634 dmas = <&apbdma 9>, <&apbdma 9 621 dmas = <&apbdma 9>, <&apbdma 9>;
635 dma-names = "rx", "tx"; 622 dma-names = "rx", "tx";
636 status = "disabled"; 623 status = "disabled";
637 }; 624 };
638 625
639 uartc: serial@70006200 { 626 uartc: serial@70006200 {
640 compatible = "nvidia,tegra210- 627 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
641 reg = <0x0 0x70006200 0x0 0x40 628 reg = <0x0 0x70006200 0x0 0x40>;
642 reg-shift = <2>; 629 reg-shift = <2>;
643 interrupts = <GIC_SPI 46 IRQ_T 630 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
644 clocks = <&tegra_car TEGRA210_ 631 clocks = <&tegra_car TEGRA210_CLK_UARTC>;
>> 632 clock-names = "serial";
645 resets = <&tegra_car 55>; 633 resets = <&tegra_car 55>;
>> 634 reset-names = "serial";
646 dmas = <&apbdma 10>, <&apbdma 635 dmas = <&apbdma 10>, <&apbdma 10>;
647 dma-names = "rx", "tx"; 636 dma-names = "rx", "tx";
648 status = "disabled"; 637 status = "disabled";
649 }; 638 };
650 639
651 uartd: serial@70006300 { 640 uartd: serial@70006300 {
652 compatible = "nvidia,tegra210- 641 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
653 reg = <0x0 0x70006300 0x0 0x40 642 reg = <0x0 0x70006300 0x0 0x40>;
654 reg-shift = <2>; 643 reg-shift = <2>;
655 interrupts = <GIC_SPI 90 IRQ_T 644 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
656 clocks = <&tegra_car TEGRA210_ 645 clocks = <&tegra_car TEGRA210_CLK_UARTD>;
>> 646 clock-names = "serial";
657 resets = <&tegra_car 65>; 647 resets = <&tegra_car 65>;
>> 648 reset-names = "serial";
658 dmas = <&apbdma 19>, <&apbdma 649 dmas = <&apbdma 19>, <&apbdma 19>;
659 dma-names = "rx", "tx"; 650 dma-names = "rx", "tx";
660 status = "disabled"; 651 status = "disabled";
661 }; 652 };
662 653
663 pwm: pwm@7000a000 { 654 pwm: pwm@7000a000 {
664 compatible = "nvidia,tegra210- 655 compatible = "nvidia,tegra210-pwm", "nvidia,tegra20-pwm";
665 reg = <0x0 0x7000a000 0x0 0x10 656 reg = <0x0 0x7000a000 0x0 0x100>;
666 #pwm-cells = <2>; 657 #pwm-cells = <2>;
667 clocks = <&tegra_car TEGRA210_ 658 clocks = <&tegra_car TEGRA210_CLK_PWM>;
>> 659 clock-names = "pwm";
668 resets = <&tegra_car 17>; 660 resets = <&tegra_car 17>;
669 reset-names = "pwm"; 661 reset-names = "pwm";
670 status = "disabled"; 662 status = "disabled";
671 }; 663 };
672 664
673 i2c@7000c000 { 665 i2c@7000c000 {
674 compatible = "nvidia,tegra210- 666 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c";
675 reg = <0x0 0x7000c000 0x0 0x10 667 reg = <0x0 0x7000c000 0x0 0x100>;
676 interrupts = <GIC_SPI 38 IRQ_T 668 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
677 #address-cells = <1>; 669 #address-cells = <1>;
678 #size-cells = <0>; 670 #size-cells = <0>;
679 clocks = <&tegra_car TEGRA210_ 671 clocks = <&tegra_car TEGRA210_CLK_I2C1>;
680 clock-names = "div-clk"; 672 clock-names = "div-clk";
681 resets = <&tegra_car 12>; 673 resets = <&tegra_car 12>;
682 reset-names = "i2c"; 674 reset-names = "i2c";
683 dmas = <&apbdma 21>, <&apbdma 675 dmas = <&apbdma 21>, <&apbdma 21>;
684 dma-names = "rx", "tx"; 676 dma-names = "rx", "tx";
685 status = "disabled"; 677 status = "disabled";
686 }; 678 };
687 679
688 i2c@7000c400 { 680 i2c@7000c400 {
689 compatible = "nvidia,tegra210- 681 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c";
690 reg = <0x0 0x7000c400 0x0 0x10 682 reg = <0x0 0x7000c400 0x0 0x100>;
691 interrupts = <GIC_SPI 84 IRQ_T 683 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
692 #address-cells = <1>; 684 #address-cells = <1>;
693 #size-cells = <0>; 685 #size-cells = <0>;
694 clocks = <&tegra_car TEGRA210_ 686 clocks = <&tegra_car TEGRA210_CLK_I2C2>;
695 clock-names = "div-clk"; 687 clock-names = "div-clk";
696 resets = <&tegra_car 54>; 688 resets = <&tegra_car 54>;
697 reset-names = "i2c"; 689 reset-names = "i2c";
698 dmas = <&apbdma 22>, <&apbdma 690 dmas = <&apbdma 22>, <&apbdma 22>;
699 dma-names = "rx", "tx"; 691 dma-names = "rx", "tx";
700 status = "disabled"; 692 status = "disabled";
701 }; 693 };
702 694
703 i2c@7000c500 { 695 i2c@7000c500 {
704 compatible = "nvidia,tegra210- 696 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c";
705 reg = <0x0 0x7000c500 0x0 0x10 697 reg = <0x0 0x7000c500 0x0 0x100>;
706 interrupts = <GIC_SPI 92 IRQ_T 698 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
707 #address-cells = <1>; 699 #address-cells = <1>;
708 #size-cells = <0>; 700 #size-cells = <0>;
709 clocks = <&tegra_car TEGRA210_ 701 clocks = <&tegra_car TEGRA210_CLK_I2C3>;
710 clock-names = "div-clk"; 702 clock-names = "div-clk";
711 resets = <&tegra_car 67>; 703 resets = <&tegra_car 67>;
712 reset-names = "i2c"; 704 reset-names = "i2c";
713 dmas = <&apbdma 23>, <&apbdma 705 dmas = <&apbdma 23>, <&apbdma 23>;
714 dma-names = "rx", "tx"; 706 dma-names = "rx", "tx";
715 status = "disabled"; 707 status = "disabled";
716 }; 708 };
717 709
718 i2c@7000c700 { 710 i2c@7000c700 {
719 compatible = "nvidia,tegra210- 711 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c";
720 reg = <0x0 0x7000c700 0x0 0x10 712 reg = <0x0 0x7000c700 0x0 0x100>;
721 interrupts = <GIC_SPI 120 IRQ_ 713 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
722 #address-cells = <1>; 714 #address-cells = <1>;
723 #size-cells = <0>; 715 #size-cells = <0>;
724 clocks = <&tegra_car TEGRA210_ 716 clocks = <&tegra_car TEGRA210_CLK_I2C4>;
725 clock-names = "div-clk"; 717 clock-names = "div-clk";
726 resets = <&tegra_car 103>; 718 resets = <&tegra_car 103>;
727 reset-names = "i2c"; 719 reset-names = "i2c";
728 dmas = <&apbdma 26>, <&apbdma 720 dmas = <&apbdma 26>, <&apbdma 26>;
729 dma-names = "rx", "tx"; 721 dma-names = "rx", "tx";
730 pinctrl-0 = <&state_dpaux1_i2c 722 pinctrl-0 = <&state_dpaux1_i2c>;
731 pinctrl-1 = <&state_dpaux1_off 723 pinctrl-1 = <&state_dpaux1_off>;
732 pinctrl-names = "default", "id 724 pinctrl-names = "default", "idle";
733 status = "disabled"; 725 status = "disabled";
734 }; 726 };
735 727
736 i2c@7000d000 { 728 i2c@7000d000 {
737 compatible = "nvidia,tegra210- 729 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c";
738 reg = <0x0 0x7000d000 0x0 0x10 730 reg = <0x0 0x7000d000 0x0 0x100>;
739 interrupts = <GIC_SPI 53 IRQ_T 731 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
740 #address-cells = <1>; 732 #address-cells = <1>;
741 #size-cells = <0>; 733 #size-cells = <0>;
742 clocks = <&tegra_car TEGRA210_ 734 clocks = <&tegra_car TEGRA210_CLK_I2C5>;
743 clock-names = "div-clk"; 735 clock-names = "div-clk";
744 resets = <&tegra_car 47>; 736 resets = <&tegra_car 47>;
745 reset-names = "i2c"; 737 reset-names = "i2c";
746 dmas = <&apbdma 24>, <&apbdma 738 dmas = <&apbdma 24>, <&apbdma 24>;
747 dma-names = "rx", "tx"; 739 dma-names = "rx", "tx";
748 status = "disabled"; 740 status = "disabled";
749 }; 741 };
750 742
751 i2c@7000d100 { 743 i2c@7000d100 {
752 compatible = "nvidia,tegra210- 744 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c";
753 reg = <0x0 0x7000d100 0x0 0x10 745 reg = <0x0 0x7000d100 0x0 0x100>;
754 interrupts = <GIC_SPI 63 IRQ_T 746 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
755 #address-cells = <1>; 747 #address-cells = <1>;
756 #size-cells = <0>; 748 #size-cells = <0>;
757 clocks = <&tegra_car TEGRA210_ 749 clocks = <&tegra_car TEGRA210_CLK_I2C6>;
758 clock-names = "div-clk"; 750 clock-names = "div-clk";
759 resets = <&tegra_car 166>; 751 resets = <&tegra_car 166>;
760 reset-names = "i2c"; 752 reset-names = "i2c";
761 dmas = <&apbdma 30>, <&apbdma 753 dmas = <&apbdma 30>, <&apbdma 30>;
762 dma-names = "rx", "tx"; 754 dma-names = "rx", "tx";
763 pinctrl-0 = <&state_dpaux_i2c> 755 pinctrl-0 = <&state_dpaux_i2c>;
764 pinctrl-1 = <&state_dpaux_off> 756 pinctrl-1 = <&state_dpaux_off>;
765 pinctrl-names = "default", "id 757 pinctrl-names = "default", "idle";
766 status = "disabled"; 758 status = "disabled";
767 }; 759 };
768 760
769 spi@7000d400 { 761 spi@7000d400 {
770 compatible = "nvidia,tegra210- 762 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
771 reg = <0x0 0x7000d400 0x0 0x20 763 reg = <0x0 0x7000d400 0x0 0x200>;
772 interrupts = <GIC_SPI 59 IRQ_T 764 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
773 #address-cells = <1>; 765 #address-cells = <1>;
774 #size-cells = <0>; 766 #size-cells = <0>;
775 clocks = <&tegra_car TEGRA210_ 767 clocks = <&tegra_car TEGRA210_CLK_SBC1>;
776 clock-names = "spi"; 768 clock-names = "spi";
777 resets = <&tegra_car 41>; 769 resets = <&tegra_car 41>;
778 reset-names = "spi"; 770 reset-names = "spi";
779 dmas = <&apbdma 15>, <&apbdma 771 dmas = <&apbdma 15>, <&apbdma 15>;
780 dma-names = "rx", "tx"; 772 dma-names = "rx", "tx";
781 status = "disabled"; 773 status = "disabled";
782 }; 774 };
783 775
784 spi@7000d600 { 776 spi@7000d600 {
785 compatible = "nvidia,tegra210- 777 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
786 reg = <0x0 0x7000d600 0x0 0x20 778 reg = <0x0 0x7000d600 0x0 0x200>;
787 interrupts = <GIC_SPI 82 IRQ_T 779 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
788 #address-cells = <1>; 780 #address-cells = <1>;
789 #size-cells = <0>; 781 #size-cells = <0>;
790 clocks = <&tegra_car TEGRA210_ 782 clocks = <&tegra_car TEGRA210_CLK_SBC2>;
791 clock-names = "spi"; 783 clock-names = "spi";
792 resets = <&tegra_car 44>; 784 resets = <&tegra_car 44>;
793 reset-names = "spi"; 785 reset-names = "spi";
794 dmas = <&apbdma 16>, <&apbdma 786 dmas = <&apbdma 16>, <&apbdma 16>;
795 dma-names = "rx", "tx"; 787 dma-names = "rx", "tx";
796 status = "disabled"; 788 status = "disabled";
797 }; 789 };
798 790
799 spi@7000d800 { 791 spi@7000d800 {
800 compatible = "nvidia,tegra210- 792 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
801 reg = <0x0 0x7000d800 0x0 0x20 793 reg = <0x0 0x7000d800 0x0 0x200>;
802 interrupts = <GIC_SPI 83 IRQ_T 794 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
803 #address-cells = <1>; 795 #address-cells = <1>;
804 #size-cells = <0>; 796 #size-cells = <0>;
805 clocks = <&tegra_car TEGRA210_ 797 clocks = <&tegra_car TEGRA210_CLK_SBC3>;
806 clock-names = "spi"; 798 clock-names = "spi";
807 resets = <&tegra_car 46>; 799 resets = <&tegra_car 46>;
808 reset-names = "spi"; 800 reset-names = "spi";
809 dmas = <&apbdma 17>, <&apbdma 801 dmas = <&apbdma 17>, <&apbdma 17>;
810 dma-names = "rx", "tx"; 802 dma-names = "rx", "tx";
811 status = "disabled"; 803 status = "disabled";
812 }; 804 };
813 805
814 spi@7000da00 { 806 spi@7000da00 {
815 compatible = "nvidia,tegra210- 807 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
816 reg = <0x0 0x7000da00 0x0 0x20 808 reg = <0x0 0x7000da00 0x0 0x200>;
817 interrupts = <GIC_SPI 93 IRQ_T 809 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
818 #address-cells = <1>; 810 #address-cells = <1>;
819 #size-cells = <0>; 811 #size-cells = <0>;
820 clocks = <&tegra_car TEGRA210_ 812 clocks = <&tegra_car TEGRA210_CLK_SBC4>;
821 clock-names = "spi"; 813 clock-names = "spi";
822 resets = <&tegra_car 68>; 814 resets = <&tegra_car 68>;
823 reset-names = "spi"; 815 reset-names = "spi";
824 dmas = <&apbdma 18>, <&apbdma 816 dmas = <&apbdma 18>, <&apbdma 18>;
825 dma-names = "rx", "tx"; 817 dma-names = "rx", "tx";
826 status = "disabled"; 818 status = "disabled";
827 }; 819 };
828 820
829 rtc@7000e000 { 821 rtc@7000e000 {
830 compatible = "nvidia,tegra210- 822 compatible = "nvidia,tegra210-rtc", "nvidia,tegra20-rtc";
831 reg = <0x0 0x7000e000 0x0 0x10 823 reg = <0x0 0x7000e000 0x0 0x100>;
832 interrupts = <16 IRQ_TYPE_LEVE 824 interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
833 interrupt-parent = <&tegra_pmc 825 interrupt-parent = <&tegra_pmc>;
834 clocks = <&tegra_car TEGRA210_ 826 clocks = <&tegra_car TEGRA210_CLK_RTC>;
835 clock-names = "rtc"; 827 clock-names = "rtc";
836 }; 828 };
837 829
838 tegra_pmc: pmc@7000e400 { 830 tegra_pmc: pmc@7000e400 {
839 compatible = "nvidia,tegra210- 831 compatible = "nvidia,tegra210-pmc";
840 reg = <0x0 0x7000e400 0x0 0x40 832 reg = <0x0 0x7000e400 0x0 0x400>;
841 clocks = <&tegra_car TEGRA210_ 833 clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>;
842 clock-names = "pclk", "clk32k_ 834 clock-names = "pclk", "clk32k_in";
843 #clock-cells = <1>; 835 #clock-cells = <1>;
844 #interrupt-cells = <2>; 836 #interrupt-cells = <2>;
845 interrupt-controller; 837 interrupt-controller;
846 838
847 pinmux { <<
848 pex_dpd_disable: pex-d <<
849 pins = "pex-bi <<
850 low-power-disa <<
851 }; <<
852 <<
853 pex_dpd_enable: pex-dp <<
854 pins = "pex-bi <<
855 low-power-enab <<
856 }; <<
857 <<
858 sdmmc1_1v8: sdmmc1-1v8 <<
859 pins = "sdmmc1 <<
860 power-source = <<
861 }; <<
862 <<
863 sdmmc1_3v3: sdmmc1-3v3 <<
864 pins = "sdmmc1 <<
865 power-source = <<
866 }; <<
867 <<
868 sdmmc3_1v8: sdmmc3-1v8 <<
869 pins = "sdmmc3 <<
870 power-source = <<
871 }; <<
872 <<
873 sdmmc3_3v3: sdmmc3-3v3 <<
874 pins = "sdmmc3 <<
875 power-source = <<
876 }; <<
877 }; <<
878 <<
879 powergates { 839 powergates {
880 pd_audio: aud { 840 pd_audio: aud {
881 clocks = <&teg 841 clocks = <&tegra_car TEGRA210_CLK_APE>,
882 <&teg 842 <&tegra_car TEGRA210_CLK_APB2APE>;
883 resets = <&teg 843 resets = <&tegra_car 198>;
884 #power-domain- 844 #power-domain-cells = <0>;
885 }; 845 };
886 846
887 pd_sor: sor { 847 pd_sor: sor {
888 clocks = <&teg 848 clocks = <&tegra_car TEGRA210_CLK_SOR0>,
889 <&teg 849 <&tegra_car TEGRA210_CLK_SOR1>,
890 <&teg 850 <&tegra_car TEGRA210_CLK_CILAB>,
891 <&teg 851 <&tegra_car TEGRA210_CLK_CILCD>,
892 <&teg 852 <&tegra_car TEGRA210_CLK_CILE>,
893 <&teg 853 <&tegra_car TEGRA210_CLK_DSIA>,
894 <&teg 854 <&tegra_car TEGRA210_CLK_DSIB>,
895 <&teg 855 <&tegra_car TEGRA210_CLK_DPAUX>,
896 <&teg 856 <&tegra_car TEGRA210_CLK_DPAUX1>,
897 <&teg 857 <&tegra_car TEGRA210_CLK_MIPI_CAL>;
898 resets = <&teg 858 resets = <&tegra_car TEGRA210_CLK_SOR0>,
899 <&teg 859 <&tegra_car TEGRA210_CLK_SOR1>,
900 <&teg 860 <&tegra_car TEGRA210_CLK_DSIA>,
901 <&teg 861 <&tegra_car TEGRA210_CLK_DSIB>,
902 <&teg 862 <&tegra_car TEGRA210_CLK_DPAUX>,
903 <&teg 863 <&tegra_car TEGRA210_CLK_DPAUX1>,
904 <&teg 864 <&tegra_car TEGRA210_CLK_MIPI_CAL>;
905 #power-domain- 865 #power-domain-cells = <0>;
906 }; 866 };
907 867
908 pd_venc: venc { <<
909 clocks = <&teg <<
910 <&teg <<
911 resets = <&mc <<
912 <&teg <<
913 <&teg <<
914 #power-domain- <<
915 }; <<
916 <<
917 pd_vic: vic { <<
918 clocks = <&teg <<
919 resets = <&teg <<
920 #power-domain- <<
921 }; <<
922 <<
923 pd_xusbss: xusba { 868 pd_xusbss: xusba {
924 clocks = <&teg 869 clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>;
925 resets = <&teg 870 resets = <&tegra_car TEGRA210_CLK_XUSB_SS>;
926 #power-domain- 871 #power-domain-cells = <0>;
927 }; 872 };
928 873
929 pd_xusbdev: xusbb { 874 pd_xusbdev: xusbb {
930 clocks = <&teg 875 clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>;
931 resets = <&teg 876 resets = <&tegra_car 95>;
932 #power-domain- 877 #power-domain-cells = <0>;
933 }; 878 };
934 879
935 pd_xusbhost: xusbc { 880 pd_xusbhost: xusbc {
936 clocks = <&teg 881 clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>;
937 resets = <&teg 882 resets = <&tegra_car TEGRA210_CLK_XUSB_HOST>;
938 #power-domain- 883 #power-domain-cells = <0>;
939 }; 884 };
>> 885
>> 886 pd_vic: vic {
>> 887 clocks = <&tegra_car TEGRA210_CLK_VIC03>;
>> 888 clock-names = "vic";
>> 889 resets = <&tegra_car 178>;
>> 890 reset-names = "vic";
>> 891 #power-domain-cells = <0>;
>> 892 };
>> 893
>> 894 pd_venc: venc {
>> 895 clocks = <&tegra_car TEGRA210_CLK_VI>,
>> 896 <&tegra_car TEGRA210_CLK_CSI>;
>> 897 resets = <&mc TEGRA210_MC_RESET_VI>,
>> 898 <&tegra_car 20>,
>> 899 <&tegra_car 52>;
>> 900 #power-domain-cells = <0>;
>> 901 };
>> 902 };
>> 903
>> 904 sdmmc1_3v3: sdmmc1-3v3 {
>> 905 pins = "sdmmc1";
>> 906 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
>> 907 };
>> 908
>> 909 sdmmc1_1v8: sdmmc1-1v8 {
>> 910 pins = "sdmmc1";
>> 911 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
>> 912 };
>> 913
>> 914 sdmmc3_3v3: sdmmc3-3v3 {
>> 915 pins = "sdmmc3";
>> 916 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
>> 917 };
>> 918
>> 919 sdmmc3_1v8: sdmmc3-1v8 {
>> 920 pins = "sdmmc3";
>> 921 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
>> 922 };
>> 923
>> 924 pex_dpd_disable: pex_en {
>> 925 pex-dpd-disable {
>> 926 pins = "pex-bias", "pex-clk1", "pex-clk2";
>> 927 low-power-disable;
>> 928 };
>> 929 };
>> 930
>> 931 pex_dpd_enable: pex_dis {
>> 932 pex-dpd-enable {
>> 933 pins = "pex-bias", "pex-clk1", "pex-clk2";
>> 934 low-power-enable;
>> 935 };
940 }; 936 };
941 }; 937 };
942 938
943 fuse@7000f800 { 939 fuse@7000f800 {
944 compatible = "nvidia,tegra210- 940 compatible = "nvidia,tegra210-efuse";
945 reg = <0x0 0x7000f800 0x0 0x40 941 reg = <0x0 0x7000f800 0x0 0x400>;
946 clocks = <&tegra_car TEGRA210_ 942 clocks = <&tegra_car TEGRA210_CLK_FUSE>;
947 clock-names = "fuse"; 943 clock-names = "fuse";
948 resets = <&tegra_car 39>; 944 resets = <&tegra_car 39>;
949 reset-names = "fuse"; 945 reset-names = "fuse";
950 }; 946 };
951 947
952 mc: memory-controller@70019000 { 948 mc: memory-controller@70019000 {
953 compatible = "nvidia,tegra210- 949 compatible = "nvidia,tegra210-mc";
954 reg = <0x0 0x70019000 0x0 0x10 950 reg = <0x0 0x70019000 0x0 0x1000>;
955 clocks = <&tegra_car TEGRA210_ 951 clocks = <&tegra_car TEGRA210_CLK_MC>;
956 clock-names = "mc"; 952 clock-names = "mc";
957 953
958 interrupts = <GIC_SPI 77 IRQ_T 954 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
959 955
960 #iommu-cells = <1>; 956 #iommu-cells = <1>;
961 #reset-cells = <1>; 957 #reset-cells = <1>;
962 }; 958 };
963 959
964 emc: external-memory-controller@7001b0 960 emc: external-memory-controller@7001b000 {
965 compatible = "nvidia,tegra210- 961 compatible = "nvidia,tegra210-emc";
966 reg = <0x0 0x7001b000 0x0 0x10 962 reg = <0x0 0x7001b000 0x0 0x1000>,
967 <0x0 0x7001e000 0x0 0x10 963 <0x0 0x7001e000 0x0 0x1000>,
968 <0x0 0x7001f000 0x0 0x10 964 <0x0 0x7001f000 0x0 0x1000>;
969 clocks = <&tegra_car TEGRA210_ 965 clocks = <&tegra_car TEGRA210_CLK_EMC>;
970 clock-names = "emc"; 966 clock-names = "emc";
971 interrupts = <GIC_SPI 78 IRQ_T 967 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
972 nvidia,memory-controller = <&m 968 nvidia,memory-controller = <&mc>;
973 #cooling-cells = <2>; 969 #cooling-cells = <2>;
974 }; 970 };
975 971
976 sata@70020000 { 972 sata@70020000 {
977 compatible = "nvidia,tegra210- 973 compatible = "nvidia,tegra210-ahci";
978 reg = <0x0 0x70027000 0x0 0x20 974 reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */
979 <0x0 0x70020000 0x0 0x70 975 <0x0 0x70020000 0x0 0x7000>, /* SATA */
980 <0x0 0x70001100 0x0 0x10 976 <0x0 0x70001100 0x0 0x1000>; /* SATA AUX */
981 interrupts = <GIC_SPI 23 IRQ_T 977 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
982 clocks = <&tegra_car TEGRA210_ 978 clocks = <&tegra_car TEGRA210_CLK_SATA>,
983 <&tegra_car TEGRA210_ 979 <&tegra_car TEGRA210_CLK_SATA_OOB>;
984 clock-names = "sata", "sata-oo 980 clock-names = "sata", "sata-oob";
985 resets = <&tegra_car 124>, 981 resets = <&tegra_car 124>,
986 <&tegra_car 129>, 982 <&tegra_car 129>,
987 <&tegra_car 123>; 983 <&tegra_car 123>;
988 reset-names = "sata", "sata-co 984 reset-names = "sata", "sata-cold", "sata-oob";
989 status = "disabled"; 985 status = "disabled";
990 }; 986 };
991 987
992 hda@70030000 { 988 hda@70030000 {
993 compatible = "nvidia,tegra210- 989 compatible = "nvidia,tegra210-hda", "nvidia,tegra30-hda";
994 reg = <0x0 0x70030000 0x0 0x10 990 reg = <0x0 0x70030000 0x0 0x10000>;
995 interrupts = <GIC_SPI 81 IRQ_T 991 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
996 clocks = <&tegra_car TEGRA210_ 992 clocks = <&tegra_car TEGRA210_CLK_HDA>,
997 <&tegra_car TEGRA210_ 993 <&tegra_car TEGRA210_CLK_HDA2HDMI>,
998 <&tegra_car TEGRA210_ 994 <&tegra_car TEGRA210_CLK_HDA2CODEC_2X>;
999 clock-names = "hda", "hda2hdmi 995 clock-names = "hda", "hda2hdmi", "hda2codec_2x";
1000 resets = <&tegra_car 125>, /* 996 resets = <&tegra_car 125>, /* hda */
1001 <&tegra_car 128>, /* 997 <&tegra_car 128>, /* hda2hdmi */
1002 <&tegra_car 111>; /* 998 <&tegra_car 111>; /* hda2codec_2x */
1003 reset-names = "hda", "hda2hdm 999 reset-names = "hda", "hda2hdmi", "hda2codec_2x";
1004 power-domains = <&pd_sor>; 1000 power-domains = <&pd_sor>;
1005 status = "disabled"; 1001 status = "disabled";
1006 }; 1002 };
1007 1003
1008 usb@70090000 { 1004 usb@70090000 {
1009 compatible = "nvidia,tegra210 1005 compatible = "nvidia,tegra210-xusb";
1010 reg = <0x0 0x70090000 0x0 0x8 1006 reg = <0x0 0x70090000 0x0 0x8000>,
1011 <0x0 0x70098000 0x0 0x1 1007 <0x0 0x70098000 0x0 0x1000>,
1012 <0x0 0x70099000 0x0 0x1 1008 <0x0 0x70099000 0x0 0x1000>;
1013 reg-names = "hcd", "fpci", "i 1009 reg-names = "hcd", "fpci", "ipfs";
1014 1010
1015 interrupts = <GIC_SPI 39 IRQ_ 1011 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
1016 <GIC_SPI 40 IRQ_ 1012 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1017 1013
1018 clocks = <&tegra_car TEGRA210 1014 clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>,
1019 <&tegra_car TEGRA210 1015 <&tegra_car TEGRA210_CLK_XUSB_HOST_SRC>,
1020 <&tegra_car TEGRA210 1016 <&tegra_car TEGRA210_CLK_XUSB_FALCON_SRC>,
1021 <&tegra_car TEGRA210 1017 <&tegra_car TEGRA210_CLK_XUSB_SS>,
1022 <&tegra_car TEGRA210 <<
1023 <&tegra_car TEGRA210 1018 <&tegra_car TEGRA210_CLK_XUSB_SS_SRC>,
>> 1019 <&tegra_car TEGRA210_CLK_XUSB_SS_DIV2>,
1024 <&tegra_car TEGRA210 1020 <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>,
1025 <&tegra_car TEGRA210 1021 <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>,
1026 <&tegra_car TEGRA210 1022 <&tegra_car TEGRA210_CLK_PLL_U_480M>,
1027 <&tegra_car TEGRA210 1023 <&tegra_car TEGRA210_CLK_CLK_M>,
1028 <&tegra_car TEGRA210 1024 <&tegra_car TEGRA210_CLK_PLL_E>;
1029 clock-names = "xusb_host", "x 1025 clock-names = "xusb_host", "xusb_host_src",
1030 "xusb_falcon_sr 1026 "xusb_falcon_src", "xusb_ss",
1031 "xusb_ss_div2", !! 1027 "xusb_ss_src", "xusb_ss_div2",
1032 "xusb_hs_src", 1028 "xusb_hs_src", "xusb_fs_src",
1033 "pll_u_480m", " 1029 "pll_u_480m", "clk_m", "pll_e";
1034 resets = <&tegra_car 89>, <&t 1030 resets = <&tegra_car 89>, <&tegra_car 156>,
1035 <&tegra_car 143>; 1031 <&tegra_car 143>;
1036 reset-names = "xusb_host", "x 1032 reset-names = "xusb_host", "xusb_ss", "xusb_src";
1037 power-domains = <&pd_xusbhost 1033 power-domains = <&pd_xusbhost>, <&pd_xusbss>;
1038 power-domain-names = "xusb_ho 1034 power-domain-names = "xusb_host", "xusb_ss";
1039 1035
1040 nvidia,xusb-padctl = <&padctl 1036 nvidia,xusb-padctl = <&padctl>;
1041 1037
1042 status = "disabled"; 1038 status = "disabled";
1043 }; 1039 };
1044 1040
1045 padctl: padctl@7009f000 { 1041 padctl: padctl@7009f000 {
1046 compatible = "nvidia,tegra210 1042 compatible = "nvidia,tegra210-xusb-padctl";
1047 reg = <0x0 0x7009f000 0x0 0x1 1043 reg = <0x0 0x7009f000 0x0 0x1000>;
1048 interrupts = <GIC_SPI 49 IRQ_ 1044 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
1049 resets = <&tegra_car 142>; 1045 resets = <&tegra_car 142>;
1050 reset-names = "padctl"; 1046 reset-names = "padctl";
1051 nvidia,pmc = <&tegra_pmc>; !! 1047 nvidia,pmc = <&tegra_pmc>;
1052 1048
1053 status = "disabled"; 1049 status = "disabled";
1054 1050
1055 pads { 1051 pads {
1056 usb2 { 1052 usb2 {
1057 clocks = <&te 1053 clocks = <&tegra_car TEGRA210_CLK_USB2_TRK>;
1058 clock-names = 1054 clock-names = "trk";
1059 status = "dis 1055 status = "disabled";
1060 1056
1061 lanes { 1057 lanes {
1062 usb2- 1058 usb2-0 {
1063 1059 status = "disabled";
1064 1060 #phy-cells = <0>;
1065 }; 1061 };
1066 1062
1067 usb2- 1063 usb2-1 {
1068 1064 status = "disabled";
1069 1065 #phy-cells = <0>;
1070 }; 1066 };
1071 1067
1072 usb2- 1068 usb2-2 {
1073 1069 status = "disabled";
1074 1070 #phy-cells = <0>;
1075 }; 1071 };
1076 1072
1077 usb2- 1073 usb2-3 {
1078 1074 status = "disabled";
1079 1075 #phy-cells = <0>;
1080 }; 1076 };
1081 }; 1077 };
1082 }; 1078 };
1083 1079
1084 hsic { 1080 hsic {
1085 clocks = <&te 1081 clocks = <&tegra_car TEGRA210_CLK_HSIC_TRK>;
1086 clock-names = 1082 clock-names = "trk";
1087 status = "dis 1083 status = "disabled";
1088 1084
1089 lanes { 1085 lanes {
1090 hsic- 1086 hsic-0 {
1091 1087 status = "disabled";
1092 1088 #phy-cells = <0>;
1093 }; 1089 };
1094 1090
1095 hsic- 1091 hsic-1 {
1096 1092 status = "disabled";
1097 1093 #phy-cells = <0>;
1098 }; 1094 };
1099 }; 1095 };
1100 }; 1096 };
1101 1097
1102 pcie { 1098 pcie {
1103 clocks = <&te 1099 clocks = <&tegra_car TEGRA210_CLK_PLL_E>;
1104 clock-names = 1100 clock-names = "pll";
1105 resets = <&te 1101 resets = <&tegra_car 205>;
1106 reset-names = 1102 reset-names = "phy";
1107 status = "dis 1103 status = "disabled";
1108 1104
1109 lanes { 1105 lanes {
1110 pcie- 1106 pcie-0 {
1111 1107 status = "disabled";
1112 1108 #phy-cells = <0>;
1113 }; 1109 };
1114 1110
1115 pcie- 1111 pcie-1 {
1116 1112 status = "disabled";
1117 1113 #phy-cells = <0>;
1118 }; 1114 };
1119 1115
1120 pcie- 1116 pcie-2 {
1121 1117 status = "disabled";
1122 1118 #phy-cells = <0>;
1123 }; 1119 };
1124 1120
1125 pcie- 1121 pcie-3 {
1126 1122 status = "disabled";
1127 1123 #phy-cells = <0>;
1128 }; 1124 };
1129 1125
1130 pcie- 1126 pcie-4 {
1131 1127 status = "disabled";
1132 1128 #phy-cells = <0>;
1133 }; 1129 };
1134 1130
1135 pcie- 1131 pcie-5 {
1136 1132 status = "disabled";
1137 1133 #phy-cells = <0>;
1138 }; 1134 };
1139 1135
1140 pcie- 1136 pcie-6 {
1141 1137 status = "disabled";
1142 1138 #phy-cells = <0>;
1143 }; 1139 };
1144 }; 1140 };
1145 }; 1141 };
1146 1142
1147 sata { 1143 sata {
1148 clocks = <&te 1144 clocks = <&tegra_car TEGRA210_CLK_PLL_E>;
1149 clock-names = 1145 clock-names = "pll";
1150 resets = <&te 1146 resets = <&tegra_car 204>;
1151 reset-names = 1147 reset-names = "phy";
1152 status = "dis 1148 status = "disabled";
1153 1149
1154 lanes { 1150 lanes {
1155 sata- 1151 sata-0 {
1156 1152 status = "disabled";
1157 1153 #phy-cells = <0>;
1158 }; 1154 };
1159 }; 1155 };
1160 }; 1156 };
1161 }; 1157 };
1162 1158
1163 ports { 1159 ports {
1164 usb2-0 { 1160 usb2-0 {
1165 status = "dis 1161 status = "disabled";
1166 }; 1162 };
1167 1163
1168 usb2-1 { 1164 usb2-1 {
1169 status = "dis 1165 status = "disabled";
1170 }; 1166 };
1171 1167
1172 usb2-2 { 1168 usb2-2 {
1173 status = "dis 1169 status = "disabled";
1174 }; 1170 };
1175 1171
1176 usb2-3 { 1172 usb2-3 {
1177 status = "dis 1173 status = "disabled";
1178 }; 1174 };
1179 1175
1180 hsic-0 { 1176 hsic-0 {
1181 status = "dis 1177 status = "disabled";
1182 }; 1178 };
1183 1179
1184 usb3-0 { 1180 usb3-0 {
1185 status = "dis 1181 status = "disabled";
1186 }; 1182 };
1187 1183
1188 usb3-1 { 1184 usb3-1 {
1189 status = "dis 1185 status = "disabled";
1190 }; 1186 };
1191 1187
1192 usb3-2 { 1188 usb3-2 {
1193 status = "dis 1189 status = "disabled";
1194 }; 1190 };
1195 1191
1196 usb3-3 { 1192 usb3-3 {
1197 status = "dis 1193 status = "disabled";
1198 }; 1194 };
1199 }; 1195 };
1200 }; 1196 };
1201 1197
1202 mmc@700b0000 { 1198 mmc@700b0000 {
1203 compatible = "nvidia,tegra210 1199 compatible = "nvidia,tegra210-sdhci";
1204 reg = <0x0 0x700b0000 0x0 0x2 1200 reg = <0x0 0x700b0000 0x0 0x200>;
1205 interrupts = <GIC_SPI 14 IRQ_ 1201 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1206 clocks = <&tegra_car TEGRA210 1202 clocks = <&tegra_car TEGRA210_CLK_SDMMC1>,
1207 <&tegra_car TEGRA210 1203 <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>;
1208 clock-names = "sdhci", "tmclk 1204 clock-names = "sdhci", "tmclk";
1209 resets = <&tegra_car 14>; 1205 resets = <&tegra_car 14>;
1210 reset-names = "sdhci"; 1206 reset-names = "sdhci";
1211 pinctrl-names = "sdmmc-3v3", 1207 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8",
1212 "sdmmc-3v3-dr 1208 "sdmmc-3v3-drv", "sdmmc-1v8-drv";
1213 pinctrl-0 = <&sdmmc1_3v3>; 1209 pinctrl-0 = <&sdmmc1_3v3>;
1214 pinctrl-1 = <&sdmmc1_1v8>; 1210 pinctrl-1 = <&sdmmc1_1v8>;
1215 pinctrl-2 = <&sdmmc1_3v3_drv> 1211 pinctrl-2 = <&sdmmc1_3v3_drv>;
1216 pinctrl-3 = <&sdmmc1_1v8_drv> 1212 pinctrl-3 = <&sdmmc1_1v8_drv>;
1217 nvidia,pad-autocal-pull-up-of 1213 nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>;
1218 nvidia,pad-autocal-pull-down- 1214 nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>;
1219 nvidia,pad-autocal-pull-up-of 1215 nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>;
1220 nvidia,pad-autocal-pull-down- 1216 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>;
1221 nvidia,default-tap = <0x2>; 1217 nvidia,default-tap = <0x2>;
1222 nvidia,default-trim = <0x4>; 1218 nvidia,default-trim = <0x4>;
1223 assigned-clocks = <&tegra_car 1219 assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>,
1224 <&tegra_car 1220 <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>,
1225 <&tegra_car 1221 <&tegra_car TEGRA210_CLK_PLL_C4>;
1226 assigned-clock-parents = <&te 1222 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
1227 assigned-clock-rates = <20000 1223 assigned-clock-rates = <200000000>, <1000000000>, <1000000000>;
1228 status = "disabled"; 1224 status = "disabled";
1229 }; 1225 };
1230 1226
1231 mmc@700b0200 { 1227 mmc@700b0200 {
1232 compatible = "nvidia,tegra210 1228 compatible = "nvidia,tegra210-sdhci";
1233 reg = <0x0 0x700b0200 0x0 0x2 1229 reg = <0x0 0x700b0200 0x0 0x200>;
1234 interrupts = <GIC_SPI 15 IRQ_ 1230 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1235 clocks = <&tegra_car TEGRA210 1231 clocks = <&tegra_car TEGRA210_CLK_SDMMC2>,
1236 <&tegra_car TEGRA210 1232 <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>;
1237 clock-names = "sdhci", "tmclk 1233 clock-names = "sdhci", "tmclk";
1238 resets = <&tegra_car 9>; 1234 resets = <&tegra_car 9>;
1239 reset-names = "sdhci"; 1235 reset-names = "sdhci";
1240 pinctrl-names = "sdmmc-1v8-dr 1236 pinctrl-names = "sdmmc-1v8-drv";
1241 pinctrl-0 = <&sdmmc2_1v8_drv> 1237 pinctrl-0 = <&sdmmc2_1v8_drv>;
1242 nvidia,pad-autocal-pull-up-of 1238 nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>;
1243 nvidia,pad-autocal-pull-down- 1239 nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>;
1244 nvidia,default-tap = <0x8>; 1240 nvidia,default-tap = <0x8>;
1245 nvidia,default-trim = <0x0>; 1241 nvidia,default-trim = <0x0>;
1246 status = "disabled"; 1242 status = "disabled";
1247 }; 1243 };
1248 1244
1249 mmc@700b0400 { 1245 mmc@700b0400 {
1250 compatible = "nvidia,tegra210 1246 compatible = "nvidia,tegra210-sdhci";
1251 reg = <0x0 0x700b0400 0x0 0x2 1247 reg = <0x0 0x700b0400 0x0 0x200>;
1252 interrupts = <GIC_SPI 19 IRQ_ 1248 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1253 clocks = <&tegra_car TEGRA210 1249 clocks = <&tegra_car TEGRA210_CLK_SDMMC3>,
1254 <&tegra_car TEGRA210 1250 <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>;
1255 clock-names = "sdhci", "tmclk 1251 clock-names = "sdhci", "tmclk";
1256 resets = <&tegra_car 69>; 1252 resets = <&tegra_car 69>;
1257 reset-names = "sdhci"; 1253 reset-names = "sdhci";
1258 pinctrl-names = "sdmmc-3v3", 1254 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8",
1259 "sdmmc-3v3-dr 1255 "sdmmc-3v3-drv", "sdmmc-1v8-drv";
1260 pinctrl-0 = <&sdmmc3_3v3>; 1256 pinctrl-0 = <&sdmmc3_3v3>;
1261 pinctrl-1 = <&sdmmc3_1v8>; 1257 pinctrl-1 = <&sdmmc3_1v8>;
1262 pinctrl-2 = <&sdmmc3_3v3_drv> 1258 pinctrl-2 = <&sdmmc3_3v3_drv>;
1263 pinctrl-3 = <&sdmmc3_1v8_drv> 1259 pinctrl-3 = <&sdmmc3_1v8_drv>;
1264 nvidia,pad-autocal-pull-up-of 1260 nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>;
1265 nvidia,pad-autocal-pull-down- 1261 nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>;
1266 nvidia,pad-autocal-pull-up-of 1262 nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>;
1267 nvidia,pad-autocal-pull-down- 1263 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>;
1268 nvidia,default-tap = <0x3>; 1264 nvidia,default-tap = <0x3>;
1269 nvidia,default-trim = <0x3>; 1265 nvidia,default-trim = <0x3>;
1270 status = "disabled"; 1266 status = "disabled";
1271 }; 1267 };
1272 1268
1273 mmc@700b0600 { 1269 mmc@700b0600 {
1274 compatible = "nvidia,tegra210 1270 compatible = "nvidia,tegra210-sdhci";
1275 reg = <0x0 0x700b0600 0x0 0x2 1271 reg = <0x0 0x700b0600 0x0 0x200>;
1276 interrupts = <GIC_SPI 31 IRQ_ 1272 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
1277 clocks = <&tegra_car TEGRA210 1273 clocks = <&tegra_car TEGRA210_CLK_SDMMC4>,
1278 <&tegra_car TEGRA210 1274 <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>;
1279 clock-names = "sdhci", "tmclk 1275 clock-names = "sdhci", "tmclk";
1280 resets = <&tegra_car 15>; 1276 resets = <&tegra_car 15>;
1281 reset-names = "sdhci"; 1277 reset-names = "sdhci";
1282 pinctrl-names = "sdmmc-3v3-dr 1278 pinctrl-names = "sdmmc-3v3-drv", "sdmmc-1v8-drv";
1283 pinctrl-0 = <&sdmmc4_1v8_drv> 1279 pinctrl-0 = <&sdmmc4_1v8_drv>;
1284 pinctrl-1 = <&sdmmc4_1v8_drv> 1280 pinctrl-1 = <&sdmmc4_1v8_drv>;
1285 nvidia,pad-autocal-pull-up-of 1281 nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>;
1286 nvidia,pad-autocal-pull-down- 1282 nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>;
1287 nvidia,default-tap = <0x8>; 1283 nvidia,default-tap = <0x8>;
1288 nvidia,default-trim = <0x0>; 1284 nvidia,default-trim = <0x0>;
1289 assigned-clocks = <&tegra_car 1285 assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>,
1290 <&tegra_car 1286 <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
1291 assigned-clock-parents = <&te 1287 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
1292 nvidia,dqs-trim = <40>; 1288 nvidia,dqs-trim = <40>;
1293 mmc-hs400-1_8v; 1289 mmc-hs400-1_8v;
1294 status = "disabled"; 1290 status = "disabled";
1295 }; 1291 };
1296 1292
1297 usb@700d0000 { 1293 usb@700d0000 {
1298 compatible = "nvidia,tegra210 1294 compatible = "nvidia,tegra210-xudc";
1299 reg = <0x0 0x700d0000 0x0 0x8 1295 reg = <0x0 0x700d0000 0x0 0x8000>,
1300 <0x0 0x700d8000 0x0 0x1 1296 <0x0 0x700d8000 0x0 0x1000>,
1301 <0x0 0x700d9000 0x0 0x1 1297 <0x0 0x700d9000 0x0 0x1000>;
1302 reg-names = "base", "fpci", " 1298 reg-names = "base", "fpci", "ipfs";
1303 interrupts = <GIC_SPI 44 IRQ_ 1299 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
1304 clocks = <&tegra_car TEGRA210 1300 clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>,
1305 <&tegra_car TEGRA210 1301 <&tegra_car TEGRA210_CLK_XUSB_SS>,
1306 <&tegra_car TEGRA210 1302 <&tegra_car TEGRA210_CLK_XUSB_SSP_SRC>,
1307 <&tegra_car TEGRA210 1303 <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>,
1308 <&tegra_car TEGRA210 1304 <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>;
1309 clock-names = "dev", "ss", "s 1305 clock-names = "dev", "ss", "ss_src", "fs_src", "hs_src";
1310 power-domains = <&pd_xusbdev> 1306 power-domains = <&pd_xusbdev>, <&pd_xusbss>;
1311 power-domain-names = "dev", " 1307 power-domain-names = "dev", "ss";
1312 nvidia,xusb-padctl = <&padctl 1308 nvidia,xusb-padctl = <&padctl>;
1313 status = "disabled"; 1309 status = "disabled";
1314 }; 1310 };
1315 1311
1316 soctherm: thermal-sensor@700e2000 { 1312 soctherm: thermal-sensor@700e2000 {
1317 compatible = "nvidia,tegra210 1313 compatible = "nvidia,tegra210-soctherm";
1318 reg = <0x0 0x700e2000 0x0 0x6 1314 reg = <0x0 0x700e2000 0x0 0x600>, /* SOC_THERM reg_base */
1319 <0x0 0x60006000 0x0 0x4 1315 <0x0 0x60006000 0x0 0x400>; /* CAR reg_base */
1320 reg-names = "soctherm-reg", " 1316 reg-names = "soctherm-reg", "car-reg";
1321 interrupts = <GIC_SPI 48 IRQ_ 1317 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
1322 <GIC_SPI 51 IRQ_ 1318 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
1323 interrupt-names = "thermal", 1319 interrupt-names = "thermal", "edp";
1324 clocks = <&tegra_car TEGRA210 1320 clocks = <&tegra_car TEGRA210_CLK_TSENSOR>,
1325 <&tegra_car TEGRA210_ 1321 <&tegra_car TEGRA210_CLK_SOC_THERM>;
1326 clock-names = "tsensor", "soc 1322 clock-names = "tsensor", "soctherm";
1327 resets = <&tegra_car 78>; 1323 resets = <&tegra_car 78>;
1328 reset-names = "soctherm"; 1324 reset-names = "soctherm";
1329 #thermal-sensor-cells = <1>; 1325 #thermal-sensor-cells = <1>;
1330 1326
1331 throttle-cfgs { 1327 throttle-cfgs {
1332 throttle_heavy: heavy 1328 throttle_heavy: heavy {
1333 nvidia,priori 1329 nvidia,priority = <100>;
1334 nvidia,cpu-th 1330 nvidia,cpu-throt-percent = <85>;
1335 nvidia,gpu-th 1331 nvidia,gpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_HIGH>;
1336 1332
1337 #cooling-cell 1333 #cooling-cells = <2>;
1338 }; 1334 };
1339 }; 1335 };
1340 }; 1336 };
1341 1337
1342 mipi: mipi@700e3000 { 1338 mipi: mipi@700e3000 {
1343 compatible = "nvidia,tegra210 1339 compatible = "nvidia,tegra210-mipi";
1344 reg = <0x0 0x700e3000 0x0 0x1 1340 reg = <0x0 0x700e3000 0x0 0x100>;
1345 clocks = <&tegra_car TEGRA210 1341 clocks = <&tegra_car TEGRA210_CLK_MIPI_CAL>;
1346 clock-names = "mipi-cal"; 1342 clock-names = "mipi-cal";
1347 power-domains = <&pd_sor>; 1343 power-domains = <&pd_sor>;
1348 #nvidia,mipi-calibrate-cells 1344 #nvidia,mipi-calibrate-cells = <1>;
1349 }; 1345 };
1350 1346
1351 dfll: clock@70110000 { 1347 dfll: clock@70110000 {
1352 compatible = "nvidia,tegra210 1348 compatible = "nvidia,tegra210-dfll";
1353 reg = <0 0x70110000 0 0x100>, 1349 reg = <0 0x70110000 0 0x100>, /* DFLL control */
1354 <0 0x70110000 0 0x100>, 1350 <0 0x70110000 0 0x100>, /* I2C output control */
1355 <0 0x70110100 0 0x100>, 1351 <0 0x70110100 0 0x100>, /* Integrated I2C controller */
1356 <0 0x70110200 0 0x100>; 1352 <0 0x70110200 0 0x100>; /* Look-up table RAM */
1357 interrupts = <GIC_SPI 62 IRQ_ 1353 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
1358 clocks = <&tegra_car TEGRA210 1354 clocks = <&tegra_car TEGRA210_CLK_DFLL_SOC>,
1359 <&tegra_car TEGRA210 1355 <&tegra_car TEGRA210_CLK_DFLL_REF>,
1360 <&tegra_car TEGRA210 1356 <&tegra_car TEGRA210_CLK_I2C5>;
1361 clock-names = "soc", "ref", " 1357 clock-names = "soc", "ref", "i2c";
1362 resets = <&tegra_car TEGRA210 !! 1358 resets = <&tegra_car TEGRA210_RST_DFLL_DVCO>;
1363 <&tegra_car 155>; !! 1359 reset-names = "dvco";
1364 reset-names = "dvco", "dfll"; <<
1365 #clock-cells = <0>; 1360 #clock-cells = <0>;
1366 clock-output-names = "dfllCPU 1361 clock-output-names = "dfllCPU_out";
1367 status = "disabled"; 1362 status = "disabled";
1368 }; 1363 };
1369 1364
1370 aconnect@702c0000 { 1365 aconnect@702c0000 {
1371 compatible = "nvidia,tegra210 1366 compatible = "nvidia,tegra210-aconnect";
1372 clocks = <&tegra_car TEGRA210 1367 clocks = <&tegra_car TEGRA210_CLK_APE>,
1373 <&tegra_car TEGRA210 1368 <&tegra_car TEGRA210_CLK_APB2APE>;
1374 clock-names = "ape", "apb2ape 1369 clock-names = "ape", "apb2ape";
1375 power-domains = <&pd_audio>; 1370 power-domains = <&pd_audio>;
1376 #address-cells = <1>; 1371 #address-cells = <1>;
1377 #size-cells = <1>; 1372 #size-cells = <1>;
1378 ranges = <0x702c0000 0x0 0x70 1373 ranges = <0x702c0000 0x0 0x702c0000 0x00040000>;
1379 status = "disabled"; 1374 status = "disabled";
1380 1375
>> 1376 adma: dma-controller@702e2000 {
>> 1377 compatible = "nvidia,tegra210-adma";
>> 1378 reg = <0x702e2000 0x2000>;
>> 1379 interrupt-parent = <&agic>;
>> 1380 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
>> 1381 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
>> 1382 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
>> 1383 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
>> 1384 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
>> 1385 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
>> 1386 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
>> 1387 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
>> 1388 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
>> 1389 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
>> 1390 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
>> 1391 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
>> 1392 <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
>> 1393 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
>> 1394 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
>> 1395 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
>> 1396 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
>> 1397 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
>> 1398 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
>> 1399 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
>> 1400 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
>> 1401 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
>> 1402 #dma-cells = <1>;
>> 1403 clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>;
>> 1404 clock-names = "d_audio";
>> 1405 status = "disabled";
>> 1406 };
>> 1407
>> 1408 agic: interrupt-controller@702f9000 {
>> 1409 compatible = "nvidia,tegra210-agic";
>> 1410 #interrupt-cells = <3>;
>> 1411 interrupt-controller;
>> 1412 reg = <0x702f9000 0x1000>,
>> 1413 <0x702fa000 0x2000>;
>> 1414 interrupts = <GIC_SPI 102 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
>> 1415 clocks = <&tegra_car TEGRA210_CLK_APE>;
>> 1416 clock-names = "clk";
>> 1417 status = "disabled";
>> 1418 };
>> 1419
1381 tegra_ahub: ahub@702d0800 { 1420 tegra_ahub: ahub@702d0800 {
1382 compatible = "nvidia, 1421 compatible = "nvidia,tegra210-ahub";
1383 reg = <0x702d0800 0x8 1422 reg = <0x702d0800 0x800>;
1384 clocks = <&tegra_car 1423 clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>;
1385 clock-names = "ahub"; 1424 clock-names = "ahub";
1386 assigned-clocks = <&t 1425 assigned-clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>;
1387 assigned-clock-parent !! 1426 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
1388 assigned-clock-rates <<
1389 #address-cells = <1>; 1427 #address-cells = <1>;
1390 #size-cells = <1>; 1428 #size-cells = <1>;
1391 ranges = <0x702d0000 1429 ranges = <0x702d0000 0x702d0000 0x0000e400>;
1392 status = "disabled"; 1430 status = "disabled";
1393 1431
1394 tegra_admaif: admaif@ 1432 tegra_admaif: admaif@702d0000 {
1395 compatible = 1433 compatible = "nvidia,tegra210-admaif";
1396 reg = <0x702d 1434 reg = <0x702d0000 0x800>;
1397 dmas = <&adma 1435 dmas = <&adma 1>, <&adma 1>,
1398 <&adma 1436 <&adma 2>, <&adma 2>,
1399 <&adma 1437 <&adma 3>, <&adma 3>,
1400 <&adma 1438 <&adma 4>, <&adma 4>,
1401 <&adma 1439 <&adma 5>, <&adma 5>,
1402 <&adma 1440 <&adma 6>, <&adma 6>,
1403 <&adma 1441 <&adma 7>, <&adma 7>,
1404 <&adma 1442 <&adma 8>, <&adma 8>,
1405 <&adma 1443 <&adma 9>, <&adma 9>,
1406 <&adma 1444 <&adma 10>, <&adma 10>;
1407 dma-names = " 1445 dma-names = "rx1", "tx1",
1408 " 1446 "rx2", "tx2",
1409 " 1447 "rx3", "tx3",
1410 " 1448 "rx4", "tx4",
1411 " 1449 "rx5", "tx5",
1412 " 1450 "rx6", "tx6",
1413 " 1451 "rx7", "tx7",
1414 " 1452 "rx8", "tx8",
1415 " 1453 "rx9", "tx9",
1416 " 1454 "rx10", "tx10";
1417 status = "dis 1455 status = "disabled";
1418 1456
1419 ports { 1457 ports {
1420 #addr 1458 #address-cells = <1>;
1421 #size 1459 #size-cells = <0>;
1422 1460
1423 admai 1461 admaif1_port: port@0 {
1424 1462 reg = <0>;
1425 1463
1426 1464 admaif1_ep: endpoint {
1427 1465 remote-endpoint = <&xbar_admaif1_ep>;
1428 1466 };
1429 }; 1467 };
1430 1468
1431 admai 1469 admaif2_port: port@1 {
1432 1470 reg = <1>;
1433 1471
1434 1472 admaif2_ep: endpoint {
1435 1473 remote-endpoint = <&xbar_admaif2_ep>;
1436 1474 };
1437 }; 1475 };
1438 1476
1439 admai 1477 admaif3_port: port@2 {
1440 1478 reg = <2>;
1441 1479
1442 1480 admaif3_ep: endpoint {
1443 1481 remote-endpoint = <&xbar_admaif3_ep>;
1444 1482 };
1445 }; 1483 };
1446 1484
1447 admai 1485 admaif4_port: port@3 {
1448 1486 reg = <3>;
1449 1487
1450 1488 admaif4_ep: endpoint {
1451 1489 remote-endpoint = <&xbar_admaif4_ep>;
1452 1490 };
1453 }; 1491 };
1454 1492
1455 admai 1493 admaif5_port: port@4 {
1456 1494 reg = <4>;
1457 1495
1458 1496 admaif5_ep: endpoint {
1459 1497 remote-endpoint = <&xbar_admaif5_ep>;
1460 1498 };
1461 }; 1499 };
1462 1500
1463 admai 1501 admaif6_port: port@5 {
1464 1502 reg = <5>;
1465 1503
1466 1504 admaif6_ep: endpoint {
1467 1505 remote-endpoint = <&xbar_admaif6_ep>;
1468 1506 };
1469 }; 1507 };
1470 1508
1471 admai 1509 admaif7_port: port@6 {
1472 1510 reg = <6>;
1473 1511
1474 1512 admaif7_ep: endpoint {
1475 1513 remote-endpoint = <&xbar_admaif7_ep>;
1476 1514 };
1477 }; 1515 };
1478 1516
1479 admai 1517 admaif8_port: port@7 {
1480 1518 reg = <7>;
1481 1519
1482 1520 admaif8_ep: endpoint {
1483 1521 remote-endpoint = <&xbar_admaif8_ep>;
1484 1522 };
1485 }; 1523 };
1486 1524
1487 admai 1525 admaif9_port: port@8 {
1488 1526 reg = <8>;
1489 1527
1490 1528 admaif9_ep: endpoint {
1491 1529 remote-endpoint = <&xbar_admaif9_ep>;
1492 1530 };
1493 }; 1531 };
1494 1532
1495 admai 1533 admaif10_port: port@9 {
1496 1534 reg = <9>;
1497 1535
1498 1536 admaif10_ep: endpoint {
1499 1537 remote-endpoint = <&xbar_admaif10_ep>;
1500 1538 };
1501 }; 1539 };
1502 }; 1540 };
1503 }; 1541 };
1504 1542
1505 tegra_i2s1: i2s@702d1 1543 tegra_i2s1: i2s@702d1000 {
1506 compatible = 1544 compatible = "nvidia,tegra210-i2s";
1507 reg = <0x702d 1545 reg = <0x702d1000 0x100>;
1508 clocks = <&te 1546 clocks = <&tegra_car TEGRA210_CLK_I2S0>,
1509 <&te 1547 <&tegra_car TEGRA210_CLK_I2S0_SYNC>;
1510 clock-names = 1548 clock-names = "i2s", "sync_input";
1511 assigned-cloc 1549 assigned-clocks = <&tegra_car TEGRA210_CLK_I2S0>;
1512 assigned-cloc 1550 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
1513 assigned-cloc 1551 assigned-clock-rates = <1536000>;
1514 sound-name-pr 1552 sound-name-prefix = "I2S1";
1515 status = "dis 1553 status = "disabled";
1516 }; 1554 };
1517 1555
1518 tegra_i2s2: i2s@702d1 1556 tegra_i2s2: i2s@702d1100 {
1519 compatible = 1557 compatible = "nvidia,tegra210-i2s";
1520 reg = <0x702d 1558 reg = <0x702d1100 0x100>;
1521 clocks = <&te 1559 clocks = <&tegra_car TEGRA210_CLK_I2S1>,
1522 <&te 1560 <&tegra_car TEGRA210_CLK_I2S1_SYNC>;
1523 clock-names = 1561 clock-names = "i2s", "sync_input";
1524 assigned-cloc 1562 assigned-clocks = <&tegra_car TEGRA210_CLK_I2S1>;
1525 assigned-cloc 1563 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
1526 assigned-cloc 1564 assigned-clock-rates = <1536000>;
1527 sound-name-pr 1565 sound-name-prefix = "I2S2";
1528 status = "dis 1566 status = "disabled";
1529 }; 1567 };
1530 1568
1531 tegra_i2s3: i2s@702d1 1569 tegra_i2s3: i2s@702d1200 {
1532 compatible = 1570 compatible = "nvidia,tegra210-i2s";
1533 reg = <0x702d 1571 reg = <0x702d1200 0x100>;
1534 clocks = <&te 1572 clocks = <&tegra_car TEGRA210_CLK_I2S2>,
1535 <&te 1573 <&tegra_car TEGRA210_CLK_I2S2_SYNC>;
1536 clock-names = 1574 clock-names = "i2s", "sync_input";
1537 assigned-cloc 1575 assigned-clocks = <&tegra_car TEGRA210_CLK_I2S2>;
1538 assigned-cloc 1576 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
1539 assigned-cloc 1577 assigned-clock-rates = <1536000>;
1540 sound-name-pr 1578 sound-name-prefix = "I2S3";
1541 status = "dis 1579 status = "disabled";
1542 }; 1580 };
1543 1581
1544 tegra_i2s4: i2s@702d1 1582 tegra_i2s4: i2s@702d1300 {
1545 compatible = 1583 compatible = "nvidia,tegra210-i2s";
1546 reg = <0x702d 1584 reg = <0x702d1300 0x100>;
1547 clocks = <&te 1585 clocks = <&tegra_car TEGRA210_CLK_I2S3>,
1548 <&te 1586 <&tegra_car TEGRA210_CLK_I2S3_SYNC>;
1549 clock-names = 1587 clock-names = "i2s", "sync_input";
1550 assigned-cloc 1588 assigned-clocks = <&tegra_car TEGRA210_CLK_I2S3>;
1551 assigned-cloc 1589 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
1552 assigned-cloc 1590 assigned-clock-rates = <1536000>;
1553 sound-name-pr 1591 sound-name-prefix = "I2S4";
1554 status = "dis 1592 status = "disabled";
1555 }; 1593 };
1556 1594
1557 tegra_i2s5: i2s@702d1 1595 tegra_i2s5: i2s@702d1400 {
1558 compatible = 1596 compatible = "nvidia,tegra210-i2s";
1559 reg = <0x702d 1597 reg = <0x702d1400 0x100>;
1560 clocks = <&te 1598 clocks = <&tegra_car TEGRA210_CLK_I2S4>,
1561 <&te 1599 <&tegra_car TEGRA210_CLK_I2S4_SYNC>;
1562 clock-names = 1600 clock-names = "i2s", "sync_input";
1563 assigned-cloc 1601 assigned-clocks = <&tegra_car TEGRA210_CLK_I2S4>;
1564 assigned-cloc 1602 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
1565 assigned-cloc 1603 assigned-clock-rates = <1536000>;
1566 sound-name-pr 1604 sound-name-prefix = "I2S5";
1567 status = "dis 1605 status = "disabled";
1568 }; 1606 };
1569 1607
1570 tegra_sfc1: sfc@702d2 <<
1571 compatible = <<
1572 reg = <0x702d <<
1573 sound-name-pr <<
1574 status = "dis <<
1575 }; <<
1576 <<
1577 tegra_sfc2: sfc@702d2 <<
1578 compatible = <<
1579 reg = <0x702d <<
1580 sound-name-pr <<
1581 status = "dis <<
1582 }; <<
1583 <<
1584 tegra_sfc3: sfc@702d2 <<
1585 compatible = <<
1586 reg = <0x702d <<
1587 sound-name-pr <<
1588 status = "dis <<
1589 }; <<
1590 <<
1591 tegra_sfc4: sfc@702d2 <<
1592 compatible = <<
1593 reg = <0x702d <<
1594 sound-name-pr <<
1595 status = "dis <<
1596 }; <<
1597 <<
1598 tegra_amx1: amx@702d3 <<
1599 compatible = <<
1600 reg = <0x702d <<
1601 sound-name-pr <<
1602 status = "dis <<
1603 }; <<
1604 <<
1605 tegra_amx2: amx@702d3 <<
1606 compatible = <<
1607 reg = <0x702d <<
1608 sound-name-pr <<
1609 status = "dis <<
1610 }; <<
1611 <<
1612 tegra_adx1: adx@702d3 <<
1613 compatible = <<
1614 reg = <0x702d <<
1615 sound-name-pr <<
1616 status = "dis <<
1617 }; <<
1618 <<
1619 tegra_adx2: adx@702d3 <<
1620 compatible = <<
1621 reg = <0x702d <<
1622 sound-name-pr <<
1623 status = "dis <<
1624 }; <<
1625 <<
1626 tegra_dmic1: dmic@702 1608 tegra_dmic1: dmic@702d4000 {
1627 compatible = 1609 compatible = "nvidia,tegra210-dmic";
1628 reg = <0x702d 1610 reg = <0x702d4000 0x100>;
1629 clocks = <&te 1611 clocks = <&tegra_car TEGRA210_CLK_DMIC1>;
1630 clock-names = 1612 clock-names = "dmic";
1631 assigned-cloc 1613 assigned-clocks = <&tegra_car TEGRA210_CLK_DMIC1>;
1632 assigned-cloc 1614 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
1633 assigned-cloc 1615 assigned-clock-rates = <3072000>;
1634 sound-name-pr 1616 sound-name-prefix = "DMIC1";
1635 status = "dis 1617 status = "disabled";
1636 }; 1618 };
1637 1619
1638 tegra_dmic2: dmic@702 1620 tegra_dmic2: dmic@702d4100 {
1639 compatible = 1621 compatible = "nvidia,tegra210-dmic";
1640 reg = <0x702d 1622 reg = <0x702d4100 0x100>;
1641 clocks = <&te 1623 clocks = <&tegra_car TEGRA210_CLK_DMIC2>;
1642 clock-names = 1624 clock-names = "dmic";
1643 assigned-cloc 1625 assigned-clocks = <&tegra_car TEGRA210_CLK_DMIC2>;
1644 assigned-cloc 1626 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
1645 assigned-cloc 1627 assigned-clock-rates = <3072000>;
1646 sound-name-pr 1628 sound-name-prefix = "DMIC2";
1647 status = "dis 1629 status = "disabled";
1648 }; 1630 };
1649 1631
1650 tegra_dmic3: dmic@702 1632 tegra_dmic3: dmic@702d4200 {
1651 compatible = 1633 compatible = "nvidia,tegra210-dmic";
1652 reg = <0x702d 1634 reg = <0x702d4200 0x100>;
1653 clocks = <&te 1635 clocks = <&tegra_car TEGRA210_CLK_DMIC3>;
1654 clock-names = 1636 clock-names = "dmic";
1655 assigned-cloc 1637 assigned-clocks = <&tegra_car TEGRA210_CLK_DMIC3>;
1656 assigned-cloc 1638 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
1657 assigned-cloc 1639 assigned-clock-rates = <3072000>;
1658 sound-name-pr 1640 sound-name-prefix = "DMIC3";
1659 status = "dis 1641 status = "disabled";
1660 }; 1642 };
1661 1643
1662 tegra_ope1: processin <<
1663 compatible = <<
1664 reg = <0x702d <<
1665 #address-cell <<
1666 #size-cells = <<
1667 ranges; <<
1668 sound-name-pr <<
1669 status = "dis <<
1670 <<
1671 equalizer@702 <<
1672 compa <<
1673 reg = <<
1674 }; <<
1675 <<
1676 dynamic-range <<
1677 compa <<
1678 reg = <<
1679 }; <<
1680 }; <<
1681 <<
1682 tegra_ope2: processin <<
1683 compatible = <<
1684 reg = <0x702d <<
1685 #address-cell <<
1686 #size-cells = <<
1687 ranges; <<
1688 sound-name-pr <<
1689 status = "dis <<
1690 <<
1691 equalizer@702 <<
1692 compa <<
1693 reg = <<
1694 }; <<
1695 <<
1696 dynamic-range <<
1697 compa <<
1698 reg = <<
1699 }; <<
1700 }; <<
1701 <<
1702 tegra_mvc1: mvc@702da <<
1703 compatible = <<
1704 reg = <0x702d <<
1705 sound-name-pr <<
1706 status = "dis <<
1707 }; <<
1708 <<
1709 tegra_mvc2: mvc@702da <<
1710 compatible = <<
1711 reg = <0x702d <<
1712 sound-name-pr <<
1713 status = "dis <<
1714 }; <<
1715 <<
1716 tegra_amixer: amixer@ <<
1717 compatible = <<
1718 reg = <0x702d <<
1719 sound-name-pr <<
1720 status = "dis <<
1721 }; <<
1722 <<
1723 ports { 1644 ports {
1724 #address-cell 1645 #address-cells = <1>;
1725 #size-cells = 1646 #size-cells = <0>;
1726 1647
1727 port@0 { 1648 port@0 {
1728 reg = 1649 reg = <0x0>;
1729 1650
1730 xbar_ 1651 xbar_admaif1_ep: endpoint {
1731 1652 remote-endpoint = <&admaif1_ep>;
1732 }; 1653 };
1733 }; 1654 };
1734 1655
1735 port@1 { 1656 port@1 {
1736 reg = 1657 reg = <0x1>;
1737 1658
1738 xbar_ 1659 xbar_admaif2_ep: endpoint {
1739 1660 remote-endpoint = <&admaif2_ep>;
1740 }; 1661 };
1741 }; 1662 };
1742 1663
1743 port@2 { 1664 port@2 {
1744 reg = 1665 reg = <0x2>;
1745 1666
1746 xbar_ 1667 xbar_admaif3_ep: endpoint {
1747 1668 remote-endpoint = <&admaif3_ep>;
1748 }; 1669 };
1749 }; 1670 };
1750 1671
1751 port@3 { 1672 port@3 {
1752 reg = 1673 reg = <0x3>;
1753 1674
1754 xbar_ 1675 xbar_admaif4_ep: endpoint {
1755 1676 remote-endpoint = <&admaif4_ep>;
1756 }; 1677 };
1757 }; 1678 };
1758 1679
1759 port@4 { 1680 port@4 {
1760 reg = 1681 reg = <0x4>;
1761 xbar_ 1682 xbar_admaif5_ep: endpoint {
1762 1683 remote-endpoint = <&admaif5_ep>;
1763 }; 1684 };
1764 }; 1685 };
1765 port@5 { 1686 port@5 {
1766 reg = 1687 reg = <0x5>;
1767 1688
1768 xbar_ 1689 xbar_admaif6_ep: endpoint {
1769 1690 remote-endpoint = <&admaif6_ep>;
1770 }; 1691 };
1771 }; 1692 };
1772 1693
1773 port@6 { 1694 port@6 {
1774 reg = 1695 reg = <0x6>;
1775 1696
1776 xbar_ 1697 xbar_admaif7_ep: endpoint {
1777 1698 remote-endpoint = <&admaif7_ep>;
1778 }; 1699 };
1779 }; 1700 };
1780 1701
1781 port@7 { 1702 port@7 {
1782 reg = 1703 reg = <0x7>;
1783 1704
1784 xbar_ 1705 xbar_admaif8_ep: endpoint {
1785 1706 remote-endpoint = <&admaif8_ep>;
1786 }; 1707 };
1787 }; 1708 };
1788 1709
1789 port@8 { 1710 port@8 {
1790 reg = 1711 reg = <0x8>;
1791 1712
1792 xbar_ 1713 xbar_admaif9_ep: endpoint {
1793 1714 remote-endpoint = <&admaif9_ep>;
1794 }; 1715 };
1795 }; 1716 };
1796 1717
1797 port@9 { 1718 port@9 {
1798 reg = 1719 reg = <0x9>;
1799 1720
1800 xbar_ 1721 xbar_admaif10_ep: endpoint {
1801 1722 remote-endpoint = <&admaif10_ep>;
1802 }; 1723 };
1803 }; 1724 };
1804 }; 1725 };
1805 }; 1726 };
1806 <<
1807 adma: dma-controller@702e2000 <<
1808 compatible = "nvidia, <<
1809 reg = <0x702e2000 0x2 <<
1810 interrupt-parent = <& <<
1811 interrupts = <GIC_SPI <<
1812 <GIC_SPI <<
1813 <GIC_SPI <<
1814 <GIC_SPI <<
1815 <GIC_SPI <<
1816 <GIC_SPI <<
1817 <GIC_SPI <<
1818 <GIC_SPI <<
1819 <GIC_SPI <<
1820 <GIC_SPI <<
1821 <GIC_SPI <<
1822 <GIC_SPI <<
1823 <GIC_SPI <<
1824 <GIC_SPI <<
1825 <GIC_SPI <<
1826 <GIC_SPI <<
1827 <GIC_SPI <<
1828 <GIC_SPI <<
1829 <GIC_SPI <<
1830 <GIC_SPI <<
1831 <GIC_SPI <<
1832 <GIC_SPI <<
1833 #dma-cells = <1>; <<
1834 clocks = <&tegra_car <<
1835 clock-names = "d_audi <<
1836 status = "disabled"; <<
1837 }; <<
1838 <<
1839 agic: interrupt-controller@70 <<
1840 compatible = "nvidia, <<
1841 #interrupt-cells = <3 <<
1842 interrupt-controller; <<
1843 reg = <0x702f9000 0x1 <<
1844 <0x702fa000 0x2 <<
1845 interrupts = <GIC_SPI <<
1846 clocks = <&tegra_car <<
1847 clock-names = "clk"; <<
1848 status = "disabled"; <<
1849 }; <<
1850 }; 1727 };
1851 1728
1852 spi@70410000 { 1729 spi@70410000 {
1853 compatible = "nvidia,tegra210 1730 compatible = "nvidia,tegra210-qspi";
1854 reg = <0x0 0x70410000 0x0 0x1 1731 reg = <0x0 0x70410000 0x0 0x1000>;
1855 interrupts = <GIC_SPI 10 IRQ_ 1732 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1856 #address-cells = <1>; 1733 #address-cells = <1>;
1857 #size-cells = <0>; 1734 #size-cells = <0>;
1858 clocks = <&tegra_car TEGRA210 1735 clocks = <&tegra_car TEGRA210_CLK_QSPI>,
1859 <&tegra_car TEGRA210 1736 <&tegra_car TEGRA210_CLK_QSPI_PM>;
1860 clock-names = "qspi", "qspi_o 1737 clock-names = "qspi", "qspi_out";
1861 resets = <&tegra_car 211>; 1738 resets = <&tegra_car 211>;
>> 1739 reset-names = "qspi";
1862 dmas = <&apbdma 5>, <&apbdma 1740 dmas = <&apbdma 5>, <&apbdma 5>;
1863 dma-names = "rx", "tx"; 1741 dma-names = "rx", "tx";
1864 status = "disabled"; 1742 status = "disabled";
1865 }; 1743 };
1866 1744
1867 usb@7d000000 { 1745 usb@7d000000 {
1868 compatible = "nvidia,tegra210 !! 1746 compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci";
1869 reg = <0x0 0x7d000000 0x0 0x4 1747 reg = <0x0 0x7d000000 0x0 0x4000>;
1870 interrupts = <GIC_SPI 20 IRQ_ 1748 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1871 phy_type = "utmi"; 1749 phy_type = "utmi";
1872 clocks = <&tegra_car TEGRA210 1750 clocks = <&tegra_car TEGRA210_CLK_USBD>;
1873 clock-names = "usb"; 1751 clock-names = "usb";
1874 resets = <&tegra_car 22>; 1752 resets = <&tegra_car 22>;
1875 reset-names = "usb"; 1753 reset-names = "usb";
1876 nvidia,phy = <&phy1>; 1754 nvidia,phy = <&phy1>;
1877 status = "disabled"; 1755 status = "disabled";
1878 }; 1756 };
1879 1757
1880 phy1: usb-phy@7d000000 { 1758 phy1: usb-phy@7d000000 {
1881 compatible = "nvidia,tegra210 1759 compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy";
1882 reg = <0x0 0x7d000000 0x0 0x4 1760 reg = <0x0 0x7d000000 0x0 0x4000>,
1883 <0x0 0x7d000000 0x0 0x4 1761 <0x0 0x7d000000 0x0 0x4000>;
1884 phy_type = "utmi"; 1762 phy_type = "utmi";
1885 clocks = <&tegra_car TEGRA210 1763 clocks = <&tegra_car TEGRA210_CLK_USBD>,
1886 <&tegra_car TEGRA210 1764 <&tegra_car TEGRA210_CLK_PLL_U>,
1887 <&tegra_car TEGRA210 1765 <&tegra_car TEGRA210_CLK_USBD>;
1888 clock-names = "reg", "pll_u", 1766 clock-names = "reg", "pll_u", "utmi-pads";
1889 resets = <&tegra_car 22>, <&t 1767 resets = <&tegra_car 22>, <&tegra_car 22>;
1890 reset-names = "usb", "utmi-pa 1768 reset-names = "usb", "utmi-pads";
1891 nvidia,hssync-start-delay = < 1769 nvidia,hssync-start-delay = <0>;
1892 nvidia,idle-wait-delay = <17> 1770 nvidia,idle-wait-delay = <17>;
1893 nvidia,elastic-limit = <16>; 1771 nvidia,elastic-limit = <16>;
1894 nvidia,term-range-adj = <6>; 1772 nvidia,term-range-adj = <6>;
1895 nvidia,xcvr-setup = <9>; 1773 nvidia,xcvr-setup = <9>;
1896 nvidia,xcvr-lsfslew = <0>; 1774 nvidia,xcvr-lsfslew = <0>;
1897 nvidia,xcvr-lsrslew = <3>; 1775 nvidia,xcvr-lsrslew = <3>;
1898 nvidia,hssquelch-level = <2>; 1776 nvidia,hssquelch-level = <2>;
1899 nvidia,hsdiscon-level = <5>; 1777 nvidia,hsdiscon-level = <5>;
1900 nvidia,xcvr-hsslew = <12>; 1778 nvidia,xcvr-hsslew = <12>;
1901 nvidia,has-utmi-pad-registers 1779 nvidia,has-utmi-pad-registers;
1902 status = "disabled"; 1780 status = "disabled";
1903 }; 1781 };
1904 1782
1905 usb@7d004000 { 1783 usb@7d004000 {
1906 compatible = "nvidia,tegra210 !! 1784 compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci";
1907 reg = <0x0 0x7d004000 0x0 0x4 1785 reg = <0x0 0x7d004000 0x0 0x4000>;
1908 interrupts = <GIC_SPI 21 IRQ_ 1786 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
1909 phy_type = "utmi"; 1787 phy_type = "utmi";
1910 clocks = <&tegra_car TEGRA210 1788 clocks = <&tegra_car TEGRA210_CLK_USB2>;
1911 clock-names = "usb"; 1789 clock-names = "usb";
1912 resets = <&tegra_car 58>; 1790 resets = <&tegra_car 58>;
1913 reset-names = "usb"; 1791 reset-names = "usb";
1914 nvidia,phy = <&phy2>; 1792 nvidia,phy = <&phy2>;
1915 status = "disabled"; 1793 status = "disabled";
1916 }; 1794 };
1917 1795
1918 phy2: usb-phy@7d004000 { 1796 phy2: usb-phy@7d004000 {
1919 compatible = "nvidia,tegra210 1797 compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy";
1920 reg = <0x0 0x7d004000 0x0 0x4 1798 reg = <0x0 0x7d004000 0x0 0x4000>,
1921 <0x0 0x7d000000 0x0 0x4 1799 <0x0 0x7d000000 0x0 0x4000>;
1922 phy_type = "utmi"; 1800 phy_type = "utmi";
1923 clocks = <&tegra_car TEGRA210 1801 clocks = <&tegra_car TEGRA210_CLK_USB2>,
1924 <&tegra_car TEGRA210 1802 <&tegra_car TEGRA210_CLK_PLL_U>,
1925 <&tegra_car TEGRA210 1803 <&tegra_car TEGRA210_CLK_USBD>;
1926 clock-names = "reg", "pll_u", 1804 clock-names = "reg", "pll_u", "utmi-pads";
1927 resets = <&tegra_car 58>, <&t 1805 resets = <&tegra_car 58>, <&tegra_car 22>;
1928 reset-names = "usb", "utmi-pa 1806 reset-names = "usb", "utmi-pads";
1929 nvidia,hssync-start-delay = < 1807 nvidia,hssync-start-delay = <0>;
1930 nvidia,idle-wait-delay = <17> 1808 nvidia,idle-wait-delay = <17>;
1931 nvidia,elastic-limit = <16>; 1809 nvidia,elastic-limit = <16>;
1932 nvidia,term-range-adj = <6>; 1810 nvidia,term-range-adj = <6>;
1933 nvidia,xcvr-setup = <9>; 1811 nvidia,xcvr-setup = <9>;
1934 nvidia,xcvr-lsfslew = <0>; 1812 nvidia,xcvr-lsfslew = <0>;
1935 nvidia,xcvr-lsrslew = <3>; 1813 nvidia,xcvr-lsrslew = <3>;
1936 nvidia,hssquelch-level = <2>; 1814 nvidia,hssquelch-level = <2>;
1937 nvidia,hsdiscon-level = <5>; 1815 nvidia,hsdiscon-level = <5>;
1938 nvidia,xcvr-hsslew = <12>; 1816 nvidia,xcvr-hsslew = <12>;
1939 status = "disabled"; 1817 status = "disabled";
1940 }; 1818 };
1941 1819
1942 cpus { 1820 cpus {
1943 #address-cells = <1>; 1821 #address-cells = <1>;
1944 #size-cells = <0>; 1822 #size-cells = <0>;
1945 1823
1946 cpu@0 { 1824 cpu@0 {
1947 device_type = "cpu"; 1825 device_type = "cpu";
1948 compatible = "arm,cor 1826 compatible = "arm,cortex-a57";
1949 reg = <0>; 1827 reg = <0>;
1950 clocks = <&tegra_car 1828 clocks = <&tegra_car TEGRA210_CLK_CCLK_G>,
1951 <&tegra_car 1829 <&tegra_car TEGRA210_CLK_PLL_X>,
1952 <&tegra_car 1830 <&tegra_car TEGRA210_CLK_PLL_P_OUT4>,
1953 <&dfll>; 1831 <&dfll>;
1954 clock-names = "cpu_g" 1832 clock-names = "cpu_g", "pll_x", "pll_p", "dfll";
1955 clock-latency = <3000 1833 clock-latency = <300000>;
1956 cpu-idle-states = <&C 1834 cpu-idle-states = <&CPU_SLEEP>;
1957 next-level-cache = <& 1835 next-level-cache = <&L2>;
1958 }; 1836 };
1959 1837
1960 cpu@1 { 1838 cpu@1 {
1961 device_type = "cpu"; 1839 device_type = "cpu";
1962 compatible = "arm,cor 1840 compatible = "arm,cortex-a57";
1963 reg = <1>; 1841 reg = <1>;
1964 cpu-idle-states = <&C 1842 cpu-idle-states = <&CPU_SLEEP>;
1965 next-level-cache = <& 1843 next-level-cache = <&L2>;
1966 }; 1844 };
1967 1845
1968 cpu@2 { 1846 cpu@2 {
1969 device_type = "cpu"; 1847 device_type = "cpu";
1970 compatible = "arm,cor 1848 compatible = "arm,cortex-a57";
1971 reg = <2>; 1849 reg = <2>;
1972 cpu-idle-states = <&C 1850 cpu-idle-states = <&CPU_SLEEP>;
1973 next-level-cache = <& 1851 next-level-cache = <&L2>;
1974 }; 1852 };
1975 1853
1976 cpu@3 { 1854 cpu@3 {
1977 device_type = "cpu"; 1855 device_type = "cpu";
1978 compatible = "arm,cor 1856 compatible = "arm,cortex-a57";
1979 reg = <3>; 1857 reg = <3>;
1980 cpu-idle-states = <&C 1858 cpu-idle-states = <&CPU_SLEEP>;
1981 next-level-cache = <& 1859 next-level-cache = <&L2>;
1982 }; 1860 };
1983 1861
1984 idle-states { 1862 idle-states {
1985 entry-method = "psci" 1863 entry-method = "psci";
1986 1864
1987 CPU_SLEEP: cpu-sleep 1865 CPU_SLEEP: cpu-sleep {
1988 compatible = 1866 compatible = "arm,idle-state";
1989 arm,psci-susp 1867 arm,psci-suspend-param = <0x40000007>;
1990 entry-latency 1868 entry-latency-us = <100>;
1991 exit-latency- 1869 exit-latency-us = <30>;
1992 min-residency 1870 min-residency-us = <1000>;
1993 wakeup-latenc 1871 wakeup-latency-us = <130>;
1994 idle-state-na 1872 idle-state-name = "cpu-sleep";
1995 status = "dis 1873 status = "disabled";
1996 }; 1874 };
1997 }; 1875 };
1998 1876
1999 L2: l2-cache { 1877 L2: l2-cache {
2000 compatible = "cache"; 1878 compatible = "cache";
2001 cache-level = <2>; <<
2002 cache-unified; <<
2003 }; 1879 };
2004 }; 1880 };
2005 1881
2006 pmu { 1882 pmu {
2007 compatible = "arm,cortex-a57- !! 1883 compatible = "arm,armv8-pmuv3";
2008 interrupts = <GIC_SPI 144 IRQ 1884 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
2009 <GIC_SPI 145 IRQ 1885 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
2010 <GIC_SPI 146 IRQ 1886 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
2011 <GIC_SPI 147 IRQ 1887 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
2012 interrupt-affinity = <&{/cpus 1888 interrupt-affinity = <&{/cpus/cpu@0} &{/cpus/cpu@1}
2013 &{/cpus 1889 &{/cpus/cpu@2} &{/cpus/cpu@3}>;
2014 }; 1890 };
2015 1891
2016 sound { 1892 sound {
2017 status = "disabled"; 1893 status = "disabled";
2018 1894
2019 clocks = <&tegra_car TEGRA210 1895 clocks = <&tegra_car TEGRA210_CLK_PLL_A>,
2020 <&tegra_car TEGRA210 1896 <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
2021 clock-names = "pll_a", "plla_ 1897 clock-names = "pll_a", "plla_out0";
2022 1898
2023 assigned-clocks = <&tegra_car 1899 assigned-clocks = <&tegra_car TEGRA210_CLK_PLL_A>,
2024 <&tegra_car 1900 <&tegra_car TEGRA210_CLK_PLL_A_OUT0>,
2025 <&tegra_car 1901 <&tegra_car TEGRA210_CLK_EXTERN1>;
2026 assigned-clock-parents = <0>, 1902 assigned-clock-parents = <0>, <0>, <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
2027 assigned-clock-rates = <36864 1903 assigned-clock-rates = <368640000>, <49152000>, <12288000>;
2028 }; 1904 };
2029 1905
2030 thermal-zones { 1906 thermal-zones {
2031 cpu-thermal { !! 1907 cpu {
2032 polling-delay-passive 1908 polling-delay-passive = <1000>;
2033 polling-delay = <0>; 1909 polling-delay = <0>;
2034 1910
2035 thermal-sensors = 1911 thermal-sensors =
2036 <&soctherm TE 1912 <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>;
2037 1913
2038 trips { 1914 trips {
2039 cpu-shutdown- 1915 cpu-shutdown-trip {
2040 tempe 1916 temperature = <102500>;
2041 hyste 1917 hysteresis = <0>;
2042 type 1918 type = "critical";
2043 }; 1919 };
2044 1920
2045 cpu_throttle_ 1921 cpu_throttle_trip: throttle-trip {
2046 tempe 1922 temperature = <98500>;
2047 hyste 1923 hysteresis = <1000>;
2048 type 1924 type = "hot";
2049 }; 1925 };
2050 }; 1926 };
2051 1927
2052 cooling-maps { 1928 cooling-maps {
2053 map0 { 1929 map0 {
2054 trip 1930 trip = <&cpu_throttle_trip>;
2055 cooli 1931 cooling-device = <&throttle_heavy 1 1>;
2056 }; 1932 };
2057 }; 1933 };
2058 }; 1934 };
2059 1935
2060 mem-thermal { !! 1936 mem {
2061 polling-delay-passive 1937 polling-delay-passive = <0>;
2062 polling-delay = <0>; 1938 polling-delay = <0>;
2063 1939
2064 thermal-sensors = 1940 thermal-sensors =
2065 <&soctherm TE 1941 <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>;
2066 1942
2067 trips { 1943 trips {
2068 dram_nominal: 1944 dram_nominal: mem-nominal-trip {
2069 tempe 1945 temperature = <50000>;
2070 hyste 1946 hysteresis = <1000>;
2071 type 1947 type = "passive";
2072 }; 1948 };
2073 1949
2074 dram_throttle 1950 dram_throttle: mem-throttle-trip {
2075 tempe 1951 temperature = <70000>;
2076 hyste 1952 hysteresis = <1000>;
2077 type 1953 type = "active";
2078 }; 1954 };
2079 1955
2080 mem-hot-trip 1956 mem-hot-trip {
2081 tempe 1957 temperature = <100000>;
2082 hyste 1958 hysteresis = <1000>;
2083 type 1959 type = "hot";
2084 }; 1960 };
2085 1961
2086 mem-shutdown- 1962 mem-shutdown-trip {
2087 tempe 1963 temperature = <103000>;
2088 hyste 1964 hysteresis = <0>;
2089 type 1965 type = "critical";
2090 }; 1966 };
2091 }; 1967 };
2092 1968
2093 cooling-maps { 1969 cooling-maps {
2094 dram-passive 1970 dram-passive {
2095 cooli 1971 cooling-device = <&emc 0 0>;
2096 trip 1972 trip = <&dram_nominal>;
2097 }; 1973 };
2098 1974
2099 dram-active { 1975 dram-active {
2100 cooli 1976 cooling-device = <&emc 1 1>;
2101 trip 1977 trip = <&dram_throttle>;
2102 }; 1978 };
2103 }; 1979 };
2104 }; 1980 };
2105 1981
2106 gpu-thermal { !! 1982 gpu {
2107 polling-delay-passive 1983 polling-delay-passive = <1000>;
2108 polling-delay = <0>; 1984 polling-delay = <0>;
2109 1985
2110 thermal-sensors = 1986 thermal-sensors =
2111 <&soctherm TE 1987 <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>;
2112 1988
2113 trips { 1989 trips {
2114 gpu-shutdown- 1990 gpu-shutdown-trip {
2115 tempe 1991 temperature = <103000>;
2116 hyste 1992 hysteresis = <0>;
2117 type 1993 type = "critical";
2118 }; 1994 };
2119 1995
2120 gpu_throttle_ 1996 gpu_throttle_trip: throttle-trip {
2121 tempe 1997 temperature = <100000>;
2122 hyste 1998 hysteresis = <1000>;
2123 type 1999 type = "hot";
2124 }; 2000 };
2125 }; 2001 };
2126 2002
2127 cooling-maps { 2003 cooling-maps {
2128 map0 { 2004 map0 {
2129 trip 2005 trip = <&gpu_throttle_trip>;
2130 cooli 2006 cooling-device = <&throttle_heavy 1 1>;
2131 }; 2007 };
2132 }; 2008 };
2133 }; 2009 };
2134 2010
2135 pllx-thermal { !! 2011 pllx {
2136 polling-delay-passive 2012 polling-delay-passive = <0>;
2137 polling-delay = <0>; 2013 polling-delay = <0>;
2138 2014
2139 thermal-sensors = 2015 thermal-sensors =
2140 <&soctherm TE 2016 <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>;
2141 2017
2142 trips { 2018 trips {
2143 pllx-shutdown 2019 pllx-shutdown-trip {
2144 tempe 2020 temperature = <103000>;
2145 hyste 2021 hysteresis = <0>;
2146 type 2022 type = "critical";
2147 }; 2023 };
2148 2024
2149 pllx-throttle 2025 pllx-throttle-trip {
2150 tempe 2026 temperature = <100000>;
2151 hyste 2027 hysteresis = <1000>;
2152 type 2028 type = "hot";
2153 }; 2029 };
2154 }; 2030 };
2155 2031
2156 cooling-maps { 2032 cooling-maps {
2157 /* 2033 /*
2158 * There are 2034 * There are currently no cooling maps,
2159 * because th 2035 * because there are no cooling devices.
2160 */ 2036 */
2161 }; 2037 };
2162 }; 2038 };
2163 }; 2039 };
2164 2040
2165 timer { 2041 timer {
2166 compatible = "arm,armv8-timer 2042 compatible = "arm,armv8-timer";
2167 interrupts = <GIC_PPI 13 2043 interrupts = <GIC_PPI 13
2168 (GIC_CPU_MASK 2044 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2169 <GIC_PPI 14 2045 <GIC_PPI 14
2170 (GIC_CPU_MASK 2046 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2171 <GIC_PPI 11 2047 <GIC_PPI 11
2172 (GIC_CPU_MASK 2048 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2173 <GIC_PPI 10 2049 <GIC_PPI 10
2174 (GIC_CPU_MASK 2050 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
2175 interrupt-parent = <&gic>; 2051 interrupt-parent = <&gic>;
2176 arm,no-tick-in-suspend; 2052 arm,no-tick-in-suspend;
2177 }; 2053 };
2178 }; 2054 };
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