1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra210-car.h> 2 #include <dt-bindings/clock/tegra210-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h> 3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra210-mc.h> 4 #include <dt-bindings/memory/tegra210-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h> 5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra-io 6 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
7 #include <dt-bindings/reset/tegra210-car.h> 7 #include <dt-bindings/reset/tegra210-car.h>
8 #include <dt-bindings/interrupt-controller/arm 8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/thermal/tegra124-socther 9 #include <dt-bindings/thermal/tegra124-soctherm.h>
10 #include <dt-bindings/soc/tegra-pmc.h> 10 #include <dt-bindings/soc/tegra-pmc.h>
11 11
12 / { 12 / {
13 compatible = "nvidia,tegra210"; 13 compatible = "nvidia,tegra210";
14 interrupt-parent = <&lic>; 14 interrupt-parent = <&lic>;
15 #address-cells = <2>; 15 #address-cells = <2>;
16 #size-cells = <2>; 16 #size-cells = <2>;
17 17
18 pcie@1003000 { 18 pcie@1003000 {
19 compatible = "nvidia,tegra210- 19 compatible = "nvidia,tegra210-pcie";
20 device_type = "pci"; 20 device_type = "pci";
21 reg = <0x0 0x01003000 0x0 0x00 21 reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */
22 <0x0 0x01003800 0x0 0x00 22 <0x0 0x01003800 0x0 0x00000800>, /* AFI registers */
23 <0x0 0x02000000 0x0 0x10 23 <0x0 0x02000000 0x0 0x10000000>; /* configuration space */
24 reg-names = "pads", "afi", "cs 24 reg-names = "pads", "afi", "cs";
25 interrupts = <GIC_SPI 98 IRQ_T 25 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
26 <GIC_SPI 99 IRQ_T 26 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
27 interrupt-names = "intr", "msi 27 interrupt-names = "intr", "msi";
28 28
29 #interrupt-cells = <1>; 29 #interrupt-cells = <1>;
30 interrupt-map-mask = <0 0 0 0> 30 interrupt-map-mask = <0 0 0 0>;
31 interrupt-map = <0 0 0 0 &gic 31 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
32 32
33 bus-range = <0x00 0xff>; 33 bus-range = <0x00 0xff>;
34 #address-cells = <3>; 34 #address-cells = <3>;
35 #size-cells = <2>; 35 #size-cells = <2>;
36 36
37 ranges = <0x02000000 0 0x01000 37 ranges = <0x02000000 0 0x01000000 0x0 0x01000000 0 0x00001000>, /* port 0 configuration space */
38 <0x02000000 0 0x01001 38 <0x02000000 0 0x01001000 0x0 0x01001000 0 0x00001000>, /* port 1 configuration space */
39 <0x01000000 0 0x0 39 <0x01000000 0 0x0 0x0 0x12000000 0 0x00010000>, /* downstream I/O (64 KiB) */
40 <0x02000000 0 0x13000 40 <0x02000000 0 0x13000000 0x0 0x13000000 0 0x0d000000>, /* non-prefetchable memory (208 MiB) */
41 <0x42000000 0 0x20000 41 <0x42000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
42 42
43 clocks = <&tegra_car TEGRA210_ 43 clocks = <&tegra_car TEGRA210_CLK_PCIE>,
44 <&tegra_car TEGRA210_ 44 <&tegra_car TEGRA210_CLK_AFI>,
45 <&tegra_car TEGRA210_ 45 <&tegra_car TEGRA210_CLK_PLL_E>,
46 <&tegra_car TEGRA210_ 46 <&tegra_car TEGRA210_CLK_CML0>;
47 clock-names = "pex", "afi", "p 47 clock-names = "pex", "afi", "pll_e", "cml";
48 resets = <&tegra_car 70>, 48 resets = <&tegra_car 70>,
49 <&tegra_car 72>, 49 <&tegra_car 72>,
50 <&tegra_car 74>; 50 <&tegra_car 74>;
51 reset-names = "pex", "afi", "p 51 reset-names = "pex", "afi", "pcie_x";
52 52
53 pinctrl-names = "default", "id 53 pinctrl-names = "default", "idle";
54 pinctrl-0 = <&pex_dpd_disable> 54 pinctrl-0 = <&pex_dpd_disable>;
55 pinctrl-1 = <&pex_dpd_enable>; 55 pinctrl-1 = <&pex_dpd_enable>;
56 56
57 status = "disabled"; 57 status = "disabled";
58 58
59 pci@1,0 { 59 pci@1,0 {
60 device_type = "pci"; 60 device_type = "pci";
61 assigned-addresses = < 61 assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
62 reg = <0x000800 0 0 0 62 reg = <0x000800 0 0 0 0>;
63 bus-range = <0x00 0xff 63 bus-range = <0x00 0xff>;
64 status = "disabled"; 64 status = "disabled";
65 65
66 #address-cells = <3>; 66 #address-cells = <3>;
67 #size-cells = <2>; 67 #size-cells = <2>;
68 ranges; 68 ranges;
69 69
70 nvidia,num-lanes = <4> 70 nvidia,num-lanes = <4>;
71 }; 71 };
72 72
73 pci@2,0 { 73 pci@2,0 {
74 device_type = "pci"; 74 device_type = "pci";
75 assigned-addresses = < 75 assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
76 reg = <0x001000 0 0 0 76 reg = <0x001000 0 0 0 0>;
77 bus-range = <0x00 0xff 77 bus-range = <0x00 0xff>;
78 status = "disabled"; 78 status = "disabled";
79 79
80 #address-cells = <3>; 80 #address-cells = <3>;
81 #size-cells = <2>; 81 #size-cells = <2>;
82 ranges; 82 ranges;
83 83
84 nvidia,num-lanes = <1> 84 nvidia,num-lanes = <1>;
85 }; 85 };
86 }; 86 };
87 87
88 host1x@50000000 { 88 host1x@50000000 {
89 compatible = "nvidia,tegra210- 89 compatible = "nvidia,tegra210-host1x";
90 reg = <0x0 0x50000000 0x0 0x00 90 reg = <0x0 0x50000000 0x0 0x00034000>;
91 interrupts = <GIC_SPI 65 IRQ_T 91 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
92 <GIC_SPI 67 IRQ_T 92 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
93 interrupt-names = "syncpt", "h 93 interrupt-names = "syncpt", "host1x";
94 clocks = <&tegra_car TEGRA210_ 94 clocks = <&tegra_car TEGRA210_CLK_HOST1X>;
95 clock-names = "host1x"; 95 clock-names = "host1x";
96 resets = <&tegra_car 28>, <&mc 96 resets = <&tegra_car 28>, <&mc TEGRA210_MC_RESET_HC>;
97 reset-names = "host1x", "mc"; 97 reset-names = "host1x", "mc";
98 98
99 #address-cells = <2>; 99 #address-cells = <2>;
100 #size-cells = <2>; 100 #size-cells = <2>;
101 101
102 ranges = <0x0 0x54000000 0x0 0 102 ranges = <0x0 0x54000000 0x0 0x54000000 0x0 0x01000000>;
103 103
104 iommus = <&mc TEGRA_SWGROUP_HC 104 iommus = <&mc TEGRA_SWGROUP_HC>;
105 105
106 dpaux1: dpaux@54040000 { 106 dpaux1: dpaux@54040000 {
107 compatible = "nvidia,t 107 compatible = "nvidia,tegra210-dpaux";
108 reg = <0x0 0x54040000 108 reg = <0x0 0x54040000 0x0 0x00040000>;
109 interrupts = <GIC_SPI 109 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
110 clocks = <&tegra_car T 110 clocks = <&tegra_car TEGRA210_CLK_DPAUX1>,
111 <&tegra_car T 111 <&tegra_car TEGRA210_CLK_PLL_DP>;
112 clock-names = "dpaux", 112 clock-names = "dpaux", "parent";
113 resets = <&tegra_car 2 113 resets = <&tegra_car 207>;
114 reset-names = "dpaux"; 114 reset-names = "dpaux";
115 power-domains = <&pd_s 115 power-domains = <&pd_sor>;
116 status = "disabled"; 116 status = "disabled";
117 117
118 state_dpaux1_aux: pinm 118 state_dpaux1_aux: pinmux-aux {
119 groups = "dpau 119 groups = "dpaux-io";
120 function = "au 120 function = "aux";
121 }; 121 };
122 122
123 state_dpaux1_i2c: pinm 123 state_dpaux1_i2c: pinmux-i2c {
124 groups = "dpau 124 groups = "dpaux-io";
125 function = "i2 125 function = "i2c";
126 }; 126 };
127 127
128 state_dpaux1_off: pinm 128 state_dpaux1_off: pinmux-off {
129 groups = "dpau 129 groups = "dpaux-io";
130 function = "of 130 function = "off";
131 }; 131 };
132 132
133 i2c-bus { 133 i2c-bus {
134 #address-cells 134 #address-cells = <1>;
135 #size-cells = 135 #size-cells = <0>;
136 }; 136 };
137 }; 137 };
138 138
139 vi@54080000 { 139 vi@54080000 {
140 compatible = "nvidia,t 140 compatible = "nvidia,tegra210-vi";
141 reg = <0x0 0x54080000 141 reg = <0x0 0x54080000 0x0 0x700>;
142 interrupts = <GIC_SPI 142 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
143 status = "disabled"; 143 status = "disabled";
144 assigned-clocks = <&te 144 assigned-clocks = <&tegra_car TEGRA210_CLK_VI>;
145 assigned-clock-parents 145 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
146 146
147 clocks = <&tegra_car T 147 clocks = <&tegra_car TEGRA210_CLK_VI>;
148 power-domains = <&pd_v 148 power-domains = <&pd_venc>;
149 149
150 #address-cells = <1>; 150 #address-cells = <1>;
151 #size-cells = <1>; 151 #size-cells = <1>;
152 152
153 ranges = <0x0 0x0 0x54 153 ranges = <0x0 0x0 0x54080000 0x2000>;
154 154
155 csi@838 { 155 csi@838 {
156 compatible = " 156 compatible = "nvidia,tegra210-csi";
157 reg = <0x838 0 157 reg = <0x838 0x1300>;
158 status = "disa 158 status = "disabled";
159 assigned-clock 159 assigned-clocks = <&tegra_car TEGRA210_CLK_CILAB>,
160 160 <&tegra_car TEGRA210_CLK_CILCD>,
161 161 <&tegra_car TEGRA210_CLK_CILE>,
162 162 <&tegra_car TEGRA210_CLK_CSI_TPG>;
163 assigned-clock 163 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>,
164 164 <&tegra_car TEGRA210_CLK_PLL_P>,
165 165 <&tegra_car TEGRA210_CLK_PLL_P>;
166 assigned-clock 166 assigned-clock-rates = <102000000>,
167 167 <102000000>,
168 168 <102000000>,
169 169 <972000000>;
170 170
171 clocks = <&teg 171 clocks = <&tegra_car TEGRA210_CLK_CSI>,
172 <&teg 172 <&tegra_car TEGRA210_CLK_CILAB>,
173 <&teg 173 <&tegra_car TEGRA210_CLK_CILCD>,
174 <&teg 174 <&tegra_car TEGRA210_CLK_CILE>,
175 <&teg 175 <&tegra_car TEGRA210_CLK_CSI_TPG>;
176 clock-names = 176 clock-names = "csi", "cilab", "cilcd", "cile", "csi_tpg";
177 power-domains 177 power-domains = <&pd_sor>;
178 }; 178 };
179 }; 179 };
180 180
181 tsec@54100000 { 181 tsec@54100000 {
182 compatible = "nvidia,t 182 compatible = "nvidia,tegra210-tsec";
183 reg = <0x0 0x54100000 183 reg = <0x0 0x54100000 0x0 0x00040000>;
184 interrupts = <GIC_SPI 184 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
185 clocks = <&tegra_car T 185 clocks = <&tegra_car TEGRA210_CLK_TSEC>;
186 clock-names = "tsec"; 186 clock-names = "tsec";
187 resets = <&tegra_car 8 187 resets = <&tegra_car 83>;
188 reset-names = "tsec"; 188 reset-names = "tsec";
189 status = "disabled"; 189 status = "disabled";
190 }; 190 };
191 191
192 dc@54200000 { 192 dc@54200000 {
193 compatible = "nvidia,t 193 compatible = "nvidia,tegra210-dc";
194 reg = <0x0 0x54200000 194 reg = <0x0 0x54200000 0x0 0x00040000>;
195 interrupts = <GIC_SPI 195 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
196 clocks = <&tegra_car T 196 clocks = <&tegra_car TEGRA210_CLK_DISP1>;
197 clock-names = "dc"; 197 clock-names = "dc";
198 resets = <&tegra_car 2 198 resets = <&tegra_car 27>;
199 reset-names = "dc"; 199 reset-names = "dc";
200 200
201 iommus = <&mc TEGRA_SW 201 iommus = <&mc TEGRA_SWGROUP_DC>;
202 202
203 nvidia,outputs = <&dsi 203 nvidia,outputs = <&dsia &dsib &sor0 &sor1>;
204 nvidia,head = <0>; 204 nvidia,head = <0>;
205 }; 205 };
206 206
207 dc@54240000 { 207 dc@54240000 {
208 compatible = "nvidia,t 208 compatible = "nvidia,tegra210-dc";
209 reg = <0x0 0x54240000 209 reg = <0x0 0x54240000 0x0 0x00040000>;
210 interrupts = <GIC_SPI 210 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
211 clocks = <&tegra_car T 211 clocks = <&tegra_car TEGRA210_CLK_DISP2>;
212 clock-names = "dc"; 212 clock-names = "dc";
213 resets = <&tegra_car 2 213 resets = <&tegra_car 26>;
214 reset-names = "dc"; 214 reset-names = "dc";
215 215
216 iommus = <&mc TEGRA_SW 216 iommus = <&mc TEGRA_SWGROUP_DCB>;
217 217
218 nvidia,outputs = <&dsi 218 nvidia,outputs = <&dsia &dsib &sor0 &sor1>;
219 nvidia,head = <1>; 219 nvidia,head = <1>;
220 }; 220 };
221 221
222 dsia: dsi@54300000 { 222 dsia: dsi@54300000 {
223 compatible = "nvidia,t 223 compatible = "nvidia,tegra210-dsi";
224 reg = <0x0 0x54300000 224 reg = <0x0 0x54300000 0x0 0x00040000>;
225 clocks = <&tegra_car T 225 clocks = <&tegra_car TEGRA210_CLK_DSIA>,
226 <&tegra_car T 226 <&tegra_car TEGRA210_CLK_DSIALP>,
227 <&tegra_car T 227 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>;
228 clock-names = "dsi", " 228 clock-names = "dsi", "lp", "parent";
229 resets = <&tegra_car 4 229 resets = <&tegra_car 48>;
230 reset-names = "dsi"; 230 reset-names = "dsi";
231 power-domains = <&pd_s 231 power-domains = <&pd_sor>;
232 nvidia,mipi-calibrate 232 nvidia,mipi-calibrate = <&mipi 0x0c0>; /* DSIA & DSIB pads */
233 233
234 status = "disabled"; 234 status = "disabled";
235 235
236 #address-cells = <1>; 236 #address-cells = <1>;
237 #size-cells = <0>; 237 #size-cells = <0>;
238 }; 238 };
239 239
240 vic@54340000 { 240 vic@54340000 {
241 compatible = "nvidia,t 241 compatible = "nvidia,tegra210-vic";
242 reg = <0x0 0x54340000 242 reg = <0x0 0x54340000 0x0 0x00040000>;
243 interrupts = <GIC_SPI 243 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
244 clocks = <&tegra_car T 244 clocks = <&tegra_car TEGRA210_CLK_VIC03>;
245 clock-names = "vic"; 245 clock-names = "vic";
246 resets = <&tegra_car 1 246 resets = <&tegra_car 178>;
247 reset-names = "vic"; 247 reset-names = "vic";
248 248
249 iommus = <&mc TEGRA_SW 249 iommus = <&mc TEGRA_SWGROUP_VIC>;
250 power-domains = <&pd_v 250 power-domains = <&pd_vic>;
251 }; 251 };
252 252
253 nvjpg@54380000 { 253 nvjpg@54380000 {
254 compatible = "nvidia,t 254 compatible = "nvidia,tegra210-nvjpg";
255 reg = <0x0 0x54380000 255 reg = <0x0 0x54380000 0x0 0x00040000>;
256 status = "disabled"; 256 status = "disabled";
257 }; 257 };
258 258
259 dsib: dsi@54400000 { 259 dsib: dsi@54400000 {
260 compatible = "nvidia,t 260 compatible = "nvidia,tegra210-dsi";
261 reg = <0x0 0x54400000 261 reg = <0x0 0x54400000 0x0 0x00040000>;
262 clocks = <&tegra_car T 262 clocks = <&tegra_car TEGRA210_CLK_DSIB>,
263 <&tegra_car T 263 <&tegra_car TEGRA210_CLK_DSIBLP>,
264 <&tegra_car T 264 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>;
265 clock-names = "dsi", " 265 clock-names = "dsi", "lp", "parent";
266 resets = <&tegra_car 8 266 resets = <&tegra_car 82>;
267 reset-names = "dsi"; 267 reset-names = "dsi";
268 power-domains = <&pd_s 268 power-domains = <&pd_sor>;
269 nvidia,mipi-calibrate 269 nvidia,mipi-calibrate = <&mipi 0x300>; /* DSIC & DSID pads */
270 270
271 status = "disabled"; 271 status = "disabled";
272 272
273 #address-cells = <1>; 273 #address-cells = <1>;
274 #size-cells = <0>; 274 #size-cells = <0>;
275 }; 275 };
276 276
277 nvdec@54480000 { 277 nvdec@54480000 {
278 compatible = "nvidia,t 278 compatible = "nvidia,tegra210-nvdec";
279 reg = <0x0 0x54480000 279 reg = <0x0 0x54480000 0x0 0x00040000>;
280 status = "disabled"; 280 status = "disabled";
281 }; 281 };
282 282
283 nvenc@544c0000 { 283 nvenc@544c0000 {
284 compatible = "nvidia,t 284 compatible = "nvidia,tegra210-nvenc";
285 reg = <0x0 0x544c0000 285 reg = <0x0 0x544c0000 0x0 0x00040000>;
286 status = "disabled"; 286 status = "disabled";
287 }; 287 };
288 288
289 tsec@54500000 { 289 tsec@54500000 {
290 compatible = "nvidia,t 290 compatible = "nvidia,tegra210-tsec";
291 reg = <0x0 0x54500000 291 reg = <0x0 0x54500000 0x0 0x00040000>;
292 interrupts = <GIC_SPI 292 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
293 clocks = <&tegra_car T 293 clocks = <&tegra_car TEGRA210_CLK_TSECB>;
294 clock-names = "tsec"; 294 clock-names = "tsec";
295 resets = <&tegra_car 2 295 resets = <&tegra_car 206>;
296 reset-names = "tsec"; 296 reset-names = "tsec";
297 status = "disabled"; 297 status = "disabled";
298 }; 298 };
299 299
300 sor0: sor@54540000 { 300 sor0: sor@54540000 {
301 compatible = "nvidia,t 301 compatible = "nvidia,tegra210-sor";
302 reg = <0x0 0x54540000 302 reg = <0x0 0x54540000 0x0 0x00040000>;
303 interrupts = <GIC_SPI 303 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
304 clocks = <&tegra_car T 304 clocks = <&tegra_car TEGRA210_CLK_SOR0>,
305 <&tegra_car T 305 <&tegra_car TEGRA210_CLK_SOR0_OUT>,
306 <&tegra_car T 306 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>,
307 <&tegra_car T 307 <&tegra_car TEGRA210_CLK_PLL_DP>,
308 <&tegra_car T 308 <&tegra_car TEGRA210_CLK_SOR_SAFE>;
309 clock-names = "sor", " 309 clock-names = "sor", "out", "parent", "dp", "safe";
310 resets = <&tegra_car 1 310 resets = <&tegra_car 182>;
311 reset-names = "sor"; 311 reset-names = "sor";
312 pinctrl-0 = <&state_dp 312 pinctrl-0 = <&state_dpaux_aux>;
313 pinctrl-1 = <&state_dp 313 pinctrl-1 = <&state_dpaux_i2c>;
314 pinctrl-2 = <&state_dp 314 pinctrl-2 = <&state_dpaux_off>;
315 pinctrl-names = "aux", 315 pinctrl-names = "aux", "i2c", "off";
316 power-domains = <&pd_s 316 power-domains = <&pd_sor>;
317 status = "disabled"; 317 status = "disabled";
318 }; 318 };
319 319
320 sor1: sor@54580000 { 320 sor1: sor@54580000 {
321 compatible = "nvidia,t 321 compatible = "nvidia,tegra210-sor1";
322 reg = <0x0 0x54580000 322 reg = <0x0 0x54580000 0x0 0x00040000>;
323 interrupts = <GIC_SPI 323 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
324 clocks = <&tegra_car T 324 clocks = <&tegra_car TEGRA210_CLK_SOR1>,
325 <&tegra_car T 325 <&tegra_car TEGRA210_CLK_SOR1_OUT>,
326 <&tegra_car T 326 <&tegra_car TEGRA210_CLK_PLL_D2_OUT0>,
327 <&tegra_car T 327 <&tegra_car TEGRA210_CLK_PLL_DP>,
328 <&tegra_car T 328 <&tegra_car TEGRA210_CLK_SOR_SAFE>;
329 clock-names = "sor", " 329 clock-names = "sor", "out", "parent", "dp", "safe";
330 resets = <&tegra_car 1 330 resets = <&tegra_car 183>;
331 reset-names = "sor"; 331 reset-names = "sor";
332 pinctrl-0 = <&state_dp 332 pinctrl-0 = <&state_dpaux1_aux>;
333 pinctrl-1 = <&state_dp 333 pinctrl-1 = <&state_dpaux1_i2c>;
334 pinctrl-2 = <&state_dp 334 pinctrl-2 = <&state_dpaux1_off>;
335 pinctrl-names = "aux", 335 pinctrl-names = "aux", "i2c", "off";
336 power-domains = <&pd_s 336 power-domains = <&pd_sor>;
337 status = "disabled"; 337 status = "disabled";
338 }; 338 };
339 339
340 dpaux: dpaux@545c0000 { 340 dpaux: dpaux@545c0000 {
341 compatible = "nvidia,t 341 compatible = "nvidia,tegra210-dpaux";
342 reg = <0x0 0x545c0000 342 reg = <0x0 0x545c0000 0x0 0x00040000>;
343 interrupts = <GIC_SPI 343 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
344 clocks = <&tegra_car T 344 clocks = <&tegra_car TEGRA210_CLK_DPAUX>,
345 <&tegra_car T 345 <&tegra_car TEGRA210_CLK_PLL_DP>;
346 clock-names = "dpaux", 346 clock-names = "dpaux", "parent";
347 resets = <&tegra_car 1 347 resets = <&tegra_car 181>;
348 reset-names = "dpaux"; 348 reset-names = "dpaux";
349 power-domains = <&pd_s 349 power-domains = <&pd_sor>;
350 status = "disabled"; 350 status = "disabled";
351 351
352 state_dpaux_aux: pinmu 352 state_dpaux_aux: pinmux-aux {
353 groups = "dpau 353 groups = "dpaux-io";
354 function = "au 354 function = "aux";
355 }; 355 };
356 356
357 state_dpaux_i2c: pinmu 357 state_dpaux_i2c: pinmux-i2c {
358 groups = "dpau 358 groups = "dpaux-io";
359 function = "i2 359 function = "i2c";
360 }; 360 };
361 361
362 state_dpaux_off: pinmu 362 state_dpaux_off: pinmux-off {
363 groups = "dpau 363 groups = "dpaux-io";
364 function = "of 364 function = "off";
365 }; 365 };
366 366
367 i2c-bus { 367 i2c-bus {
368 #address-cells 368 #address-cells = <1>;
369 #size-cells = 369 #size-cells = <0>;
370 }; 370 };
371 }; 371 };
372 372
373 isp@54600000 { 373 isp@54600000 {
374 compatible = "nvidia,t 374 compatible = "nvidia,tegra210-isp";
375 reg = <0x0 0x54600000 375 reg = <0x0 0x54600000 0x0 0x00040000>;
376 interrupts = <GIC_SPI 376 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
377 clocks = <&tegra_car T 377 clocks = <&tegra_car TEGRA210_CLK_ISPA>;
378 resets = <&tegra_car 2 378 resets = <&tegra_car 23>;
379 reset-names = "isp"; 379 reset-names = "isp";
380 status = "disabled"; 380 status = "disabled";
381 }; 381 };
382 382
383 isp@54680000 { 383 isp@54680000 {
384 compatible = "nvidia,t 384 compatible = "nvidia,tegra210-isp";
385 reg = <0x0 0x54680000 385 reg = <0x0 0x54680000 0x0 0x00040000>;
386 interrupts = <GIC_SPI 386 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
387 clocks = <&tegra_car T 387 clocks = <&tegra_car TEGRA210_CLK_ISPB>;
388 resets = <&tegra_car 3 388 resets = <&tegra_car 3>;
389 reset-names = "isp"; 389 reset-names = "isp";
390 status = "disabled"; 390 status = "disabled";
391 }; 391 };
392 392
393 i2c@546c0000 { 393 i2c@546c0000 {
394 compatible = "nvidia,t 394 compatible = "nvidia,tegra210-i2c-vi";
395 reg = <0x0 0x546c0000 395 reg = <0x0 0x546c0000 0x0 0x00040000>;
396 interrupts = <GIC_SPI 396 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
397 clocks = <&tegra_car T 397 clocks = <&tegra_car TEGRA210_CLK_VI_I2C>,
398 <&tegra_car T 398 <&tegra_car TEGRA210_CLK_I2CSLOW>;
399 clock-names = "div-clk 399 clock-names = "div-clk", "slow";
400 resets = <&tegra_car 2 400 resets = <&tegra_car 208>;
401 reset-names = "i2c"; 401 reset-names = "i2c";
402 power-domains = <&pd_v 402 power-domains = <&pd_venc>;
403 status = "disabled"; 403 status = "disabled";
404 404
405 #address-cells = <1>; 405 #address-cells = <1>;
406 #size-cells = <0>; 406 #size-cells = <0>;
407 }; 407 };
408 }; 408 };
409 409
410 gic: interrupt-controller@50041000 { 410 gic: interrupt-controller@50041000 {
411 compatible = "arm,gic-400"; 411 compatible = "arm,gic-400";
412 #interrupt-cells = <3>; 412 #interrupt-cells = <3>;
413 interrupt-controller; 413 interrupt-controller;
414 reg = <0x0 0x50041000 0x0 0x10 414 reg = <0x0 0x50041000 0x0 0x1000>,
415 <0x0 0x50042000 0x0 0x20 415 <0x0 0x50042000 0x0 0x2000>,
416 <0x0 0x50044000 0x0 0x20 416 <0x0 0x50044000 0x0 0x2000>,
417 <0x0 0x50046000 0x0 0x20 417 <0x0 0x50046000 0x0 0x2000>;
418 interrupts = <GIC_PPI 9 418 interrupts = <GIC_PPI 9
419 (GIC_CPU_MASK_SIMPLE(4 419 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
420 interrupt-parent = <&gic>; 420 interrupt-parent = <&gic>;
421 }; 421 };
422 422
423 gpu@57000000 { 423 gpu@57000000 {
424 compatible = "nvidia,gm20b"; 424 compatible = "nvidia,gm20b";
425 reg = <0x0 0x57000000 0x0 0x01 425 reg = <0x0 0x57000000 0x0 0x01000000>,
426 <0x0 0x58000000 0x0 0x01 426 <0x0 0x58000000 0x0 0x01000000>;
427 interrupts = <GIC_SPI 157 IRQ_ 427 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
428 <GIC_SPI 158 IRQ_ 428 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
429 interrupt-names = "stall", "no 429 interrupt-names = "stall", "nonstall";
430 clocks = <&tegra_car TEGRA210_ 430 clocks = <&tegra_car TEGRA210_CLK_GPU>,
431 <&tegra_car TEGRA210_ 431 <&tegra_car TEGRA210_CLK_PLL_P_OUT5>,
432 <&tegra_car TEGRA210_ 432 <&tegra_car TEGRA210_CLK_PLL_G_REF>;
433 clock-names = "gpu", "pwr", "r 433 clock-names = "gpu", "pwr", "ref";
434 resets = <&tegra_car 184>; 434 resets = <&tegra_car 184>;
435 reset-names = "gpu"; 435 reset-names = "gpu";
436 436
437 iommus = <&mc TEGRA_SWGROUP_GP 437 iommus = <&mc TEGRA_SWGROUP_GPU>;
438 438
439 status = "disabled"; 439 status = "disabled";
440 }; 440 };
441 441
442 lic: interrupt-controller@60004000 { 442 lic: interrupt-controller@60004000 {
443 compatible = "nvidia,tegra210- 443 compatible = "nvidia,tegra210-ictlr";
444 reg = <0x0 0x60004000 0x0 0x40 444 reg = <0x0 0x60004000 0x0 0x40>, /* primary controller */
445 <0x0 0x60004100 0x0 0x40 445 <0x0 0x60004100 0x0 0x40>, /* secondary controller */
446 <0x0 0x60004200 0x0 0x40 446 <0x0 0x60004200 0x0 0x40>, /* tertiary controller */
447 <0x0 0x60004300 0x0 0x40 447 <0x0 0x60004300 0x0 0x40>, /* quaternary controller */
448 <0x0 0x60004400 0x0 0x40 448 <0x0 0x60004400 0x0 0x40>, /* quinary controller */
449 <0x0 0x60004500 0x0 0x40 449 <0x0 0x60004500 0x0 0x40>; /* senary controller */
450 interrupt-controller; 450 interrupt-controller;
451 #interrupt-cells = <3>; 451 #interrupt-cells = <3>;
452 interrupt-parent = <&gic>; 452 interrupt-parent = <&gic>;
453 }; 453 };
454 454
455 timer@60005000 { 455 timer@60005000 {
456 compatible = "nvidia,tegra210- 456 compatible = "nvidia,tegra210-timer";
457 reg = <0x0 0x60005000 0x0 0x40 457 reg = <0x0 0x60005000 0x0 0x400>;
458 interrupts = <GIC_SPI 156 IRQ_ 458 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
459 <GIC_SPI 0 IRQ_TY 459 <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
460 <GIC_SPI 1 IRQ_TY 460 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
461 <GIC_SPI 41 IRQ_T 461 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
462 <GIC_SPI 42 IRQ_T 462 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
463 <GIC_SPI 121 IRQ_ 463 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
464 <GIC_SPI 152 IRQ_ 464 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
465 <GIC_SPI 153 IRQ_ 465 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
466 <GIC_SPI 154 IRQ_ 466 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
467 <GIC_SPI 155 IRQ_ 467 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
468 <GIC_SPI 176 IRQ_ 468 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
469 <GIC_SPI 177 IRQ_ 469 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
470 <GIC_SPI 178 IRQ_ 470 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
471 <GIC_SPI 179 IRQ_ 471 <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
472 clocks = <&tegra_car TEGRA210_ 472 clocks = <&tegra_car TEGRA210_CLK_TIMER>;
473 clock-names = "timer"; 473 clock-names = "timer";
474 }; 474 };
475 475
476 tegra_car: clock@60006000 { 476 tegra_car: clock@60006000 {
477 compatible = "nvidia,tegra210- 477 compatible = "nvidia,tegra210-car";
478 reg = <0x0 0x60006000 0x0 0x10 478 reg = <0x0 0x60006000 0x0 0x1000>;
479 #clock-cells = <1>; 479 #clock-cells = <1>;
480 #reset-cells = <1>; 480 #reset-cells = <1>;
481 }; 481 };
482 482
483 flow-controller@60007000 { 483 flow-controller@60007000 {
484 compatible = "nvidia,tegra210- 484 compatible = "nvidia,tegra210-flowctrl";
485 reg = <0x0 0x60007000 0x0 0x10 485 reg = <0x0 0x60007000 0x0 0x1000>;
486 }; 486 };
487 487
488 gpio: gpio@6000d000 { 488 gpio: gpio@6000d000 {
489 compatible = "nvidia,tegra210- 489 compatible = "nvidia,tegra210-gpio", "nvidia,tegra30-gpio";
490 reg = <0x0 0x6000d000 0x0 0x10 490 reg = <0x0 0x6000d000 0x0 0x1000>;
491 interrupts = <GIC_SPI 32 IRQ_T 491 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
492 <GIC_SPI 33 IRQ_T 492 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
493 <GIC_SPI 34 IRQ_T 493 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
494 <GIC_SPI 35 IRQ_T 494 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
495 <GIC_SPI 55 IRQ_T 495 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
496 <GIC_SPI 87 IRQ_T 496 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
497 <GIC_SPI 89 IRQ_T 497 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
498 <GIC_SPI 125 IRQ_ 498 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
499 #gpio-cells = <2>; 499 #gpio-cells = <2>;
500 gpio-controller; 500 gpio-controller;
501 #interrupt-cells = <2>; 501 #interrupt-cells = <2>;
502 interrupt-controller; 502 interrupt-controller;
503 }; 503 };
504 504
505 apbdma: dma@60020000 { 505 apbdma: dma@60020000 {
506 compatible = "nvidia,tegra210- 506 compatible = "nvidia,tegra210-apbdma", "nvidia,tegra148-apbdma";
507 reg = <0x0 0x60020000 0x0 0x14 507 reg = <0x0 0x60020000 0x0 0x1400>;
508 interrupts = <GIC_SPI 104 IRQ_ 508 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
509 <GIC_SPI 105 IRQ_ 509 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
510 <GIC_SPI 106 IRQ_ 510 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
511 <GIC_SPI 107 IRQ_ 511 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
512 <GIC_SPI 108 IRQ_ 512 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
513 <GIC_SPI 109 IRQ_ 513 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
514 <GIC_SPI 110 IRQ_ 514 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
515 <GIC_SPI 111 IRQ_ 515 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
516 <GIC_SPI 112 IRQ_ 516 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
517 <GIC_SPI 113 IRQ_ 517 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
518 <GIC_SPI 114 IRQ_ 518 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
519 <GIC_SPI 115 IRQ_ 519 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
520 <GIC_SPI 116 IRQ_ 520 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
521 <GIC_SPI 117 IRQ_ 521 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
522 <GIC_SPI 118 IRQ_ 522 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
523 <GIC_SPI 119 IRQ_ 523 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
524 <GIC_SPI 128 IRQ_ 524 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
525 <GIC_SPI 129 IRQ_ 525 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
526 <GIC_SPI 130 IRQ_ 526 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
527 <GIC_SPI 131 IRQ_ 527 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
528 <GIC_SPI 132 IRQ_ 528 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
529 <GIC_SPI 133 IRQ_ 529 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
530 <GIC_SPI 134 IRQ_ 530 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
531 <GIC_SPI 135 IRQ_ 531 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
532 <GIC_SPI 136 IRQ_ 532 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
533 <GIC_SPI 137 IRQ_ 533 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
534 <GIC_SPI 138 IRQ_ 534 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
535 <GIC_SPI 139 IRQ_ 535 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
536 <GIC_SPI 140 IRQ_ 536 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
537 <GIC_SPI 141 IRQ_ 537 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
538 <GIC_SPI 142 IRQ_ 538 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
539 <GIC_SPI 143 IRQ_ 539 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
540 clocks = <&tegra_car TEGRA210_ 540 clocks = <&tegra_car TEGRA210_CLK_APBDMA>;
541 clock-names = "dma"; 541 clock-names = "dma";
542 resets = <&tegra_car 34>; 542 resets = <&tegra_car 34>;
543 reset-names = "dma"; 543 reset-names = "dma";
544 #dma-cells = <1>; 544 #dma-cells = <1>;
545 }; 545 };
546 546
547 apbmisc@70000800 { 547 apbmisc@70000800 {
548 compatible = "nvidia,tegra210- 548 compatible = "nvidia,tegra210-apbmisc", "nvidia,tegra20-apbmisc";
549 reg = <0x0 0x70000800 0x0 0x64 549 reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */
550 <0x0 0x70000008 0x0 0x04 550 <0x0 0x70000008 0x0 0x04>; /* Strapping options */
551 }; 551 };
552 552
553 pinmux: pinmux@700008d4 { 553 pinmux: pinmux@700008d4 {
554 compatible = "nvidia,tegra210- 554 compatible = "nvidia,tegra210-pinmux";
555 reg = <0x0 0x700008d4 0x0 0x29 555 reg = <0x0 0x700008d4 0x0 0x29c>, /* Pad control registers */
556 <0x0 0x70003000 0x0 0x29 556 <0x0 0x70003000 0x0 0x294>; /* Mux registers */
557 !! 557 sdmmc1_3v3_drv: sdmmc1-3v3-drv {
558 sdmmc1_1v8_drv: pinmux-sdmmc1- <<
559 sdmmc1 { 558 sdmmc1 {
560 nvidia,pins = 559 nvidia,pins = "drive_sdmmc1";
561 nvidia,pull-do !! 560 nvidia,pull-down-strength = <0x8>;
562 nvidia,pull-up !! 561 nvidia,pull-up-strength = <0x8>;
563 }; 562 };
564 }; 563 };
565 !! 564 sdmmc1_1v8_drv: sdmmc1-1v8-drv {
566 sdmmc1_3v3_drv: pinmux-sdmmc1- <<
567 sdmmc1 { 565 sdmmc1 {
568 nvidia,pins = 566 nvidia,pins = "drive_sdmmc1";
569 nvidia,pull-do !! 567 nvidia,pull-down-strength = <0x4>;
570 nvidia,pull-up !! 568 nvidia,pull-up-strength = <0x3>;
571 }; 569 };
572 }; 570 };
573 !! 571 sdmmc2_1v8_drv: sdmmc2-1v8-drv {
574 sdmmc2_1v8_drv: pinmux-sdmmc2- <<
575 sdmmc2 { 572 sdmmc2 {
576 nvidia,pins = 573 nvidia,pins = "drive_sdmmc2";
577 nvidia,pull-do 574 nvidia,pull-down-strength = <0x10>;
578 nvidia,pull-up 575 nvidia,pull-up-strength = <0x10>;
579 }; 576 };
580 }; 577 };
581 !! 578 sdmmc3_3v3_drv: sdmmc3-3v3-drv {
582 sdmmc3_1v8_drv: pinmux-sdmmc3- <<
583 sdmmc3 { 579 sdmmc3 {
584 nvidia,pins = 580 nvidia,pins = "drive_sdmmc3";
585 nvidia,pull-do !! 581 nvidia,pull-down-strength = <0x8>;
586 nvidia,pull-up !! 582 nvidia,pull-up-strength = <0x8>;
587 }; 583 };
588 }; 584 };
589 !! 585 sdmmc3_1v8_drv: sdmmc3-1v8-drv {
590 sdmmc3_3v3_drv: pinmux-sdmmc3- <<
591 sdmmc3 { 586 sdmmc3 {
592 nvidia,pins = 587 nvidia,pins = "drive_sdmmc3";
593 nvidia,pull-do !! 588 nvidia,pull-down-strength = <0x4>;
594 nvidia,pull-up !! 589 nvidia,pull-up-strength = <0x3>;
595 }; 590 };
596 }; 591 };
597 !! 592 sdmmc4_1v8_drv: sdmmc4-1v8-drv {
598 sdmmc4_1v8_drv: pinmux-sdmmc4- <<
599 sdmmc4 { 593 sdmmc4 {
600 nvidia,pins = 594 nvidia,pins = "drive_sdmmc4";
601 nvidia,pull-do 595 nvidia,pull-down-strength = <0x10>;
602 nvidia,pull-up 596 nvidia,pull-up-strength = <0x10>;
603 }; 597 };
604 }; 598 };
605 }; 599 };
606 600
607 /* 601 /*
608 * There are two serial driver i.e. 82 602 * There are two serial driver i.e. 8250 based simple serial
609 * driver and APB DMA based serial dri 603 * driver and APB DMA based serial driver for higher baudrate
610 * and performance. To enable the 8250 604 * and performance. To enable the 8250 based driver, the compatible
611 * is "nvidia,tegra124-uart", "nvidia, 605 * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable
612 * the APB DMA based serial driver, th 606 * the APB DMA based serial driver, the compatible is
613 * "nvidia,tegra124-hsuart", "nvidia,t 607 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart".
614 */ 608 */
615 uarta: serial@70006000 { 609 uarta: serial@70006000 {
616 compatible = "nvidia,tegra210- 610 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
617 reg = <0x0 0x70006000 0x0 0x40 611 reg = <0x0 0x70006000 0x0 0x40>;
618 reg-shift = <2>; 612 reg-shift = <2>;
619 interrupts = <GIC_SPI 36 IRQ_T 613 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
620 clocks = <&tegra_car TEGRA210_ 614 clocks = <&tegra_car TEGRA210_CLK_UARTA>;
>> 615 clock-names = "serial";
621 resets = <&tegra_car 6>; 616 resets = <&tegra_car 6>;
>> 617 reset-names = "serial";
622 dmas = <&apbdma 8>, <&apbdma 8 618 dmas = <&apbdma 8>, <&apbdma 8>;
623 dma-names = "rx", "tx"; 619 dma-names = "rx", "tx";
624 status = "disabled"; 620 status = "disabled";
625 }; 621 };
626 622
627 uartb: serial@70006040 { 623 uartb: serial@70006040 {
628 compatible = "nvidia,tegra210- 624 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
629 reg = <0x0 0x70006040 0x0 0x40 625 reg = <0x0 0x70006040 0x0 0x40>;
630 reg-shift = <2>; 626 reg-shift = <2>;
631 interrupts = <GIC_SPI 37 IRQ_T 627 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
632 clocks = <&tegra_car TEGRA210_ 628 clocks = <&tegra_car TEGRA210_CLK_UARTB>;
>> 629 clock-names = "serial";
633 resets = <&tegra_car 7>; 630 resets = <&tegra_car 7>;
>> 631 reset-names = "serial";
634 dmas = <&apbdma 9>, <&apbdma 9 632 dmas = <&apbdma 9>, <&apbdma 9>;
635 dma-names = "rx", "tx"; 633 dma-names = "rx", "tx";
636 status = "disabled"; 634 status = "disabled";
637 }; 635 };
638 636
639 uartc: serial@70006200 { 637 uartc: serial@70006200 {
640 compatible = "nvidia,tegra210- 638 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
641 reg = <0x0 0x70006200 0x0 0x40 639 reg = <0x0 0x70006200 0x0 0x40>;
642 reg-shift = <2>; 640 reg-shift = <2>;
643 interrupts = <GIC_SPI 46 IRQ_T 641 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
644 clocks = <&tegra_car TEGRA210_ 642 clocks = <&tegra_car TEGRA210_CLK_UARTC>;
>> 643 clock-names = "serial";
645 resets = <&tegra_car 55>; 644 resets = <&tegra_car 55>;
>> 645 reset-names = "serial";
646 dmas = <&apbdma 10>, <&apbdma 646 dmas = <&apbdma 10>, <&apbdma 10>;
647 dma-names = "rx", "tx"; 647 dma-names = "rx", "tx";
648 status = "disabled"; 648 status = "disabled";
649 }; 649 };
650 650
651 uartd: serial@70006300 { 651 uartd: serial@70006300 {
652 compatible = "nvidia,tegra210- 652 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
653 reg = <0x0 0x70006300 0x0 0x40 653 reg = <0x0 0x70006300 0x0 0x40>;
654 reg-shift = <2>; 654 reg-shift = <2>;
655 interrupts = <GIC_SPI 90 IRQ_T 655 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
656 clocks = <&tegra_car TEGRA210_ 656 clocks = <&tegra_car TEGRA210_CLK_UARTD>;
>> 657 clock-names = "serial";
657 resets = <&tegra_car 65>; 658 resets = <&tegra_car 65>;
>> 659 reset-names = "serial";
658 dmas = <&apbdma 19>, <&apbdma 660 dmas = <&apbdma 19>, <&apbdma 19>;
659 dma-names = "rx", "tx"; 661 dma-names = "rx", "tx";
660 status = "disabled"; 662 status = "disabled";
661 }; 663 };
662 664
663 pwm: pwm@7000a000 { 665 pwm: pwm@7000a000 {
664 compatible = "nvidia,tegra210- 666 compatible = "nvidia,tegra210-pwm", "nvidia,tegra20-pwm";
665 reg = <0x0 0x7000a000 0x0 0x10 667 reg = <0x0 0x7000a000 0x0 0x100>;
666 #pwm-cells = <2>; 668 #pwm-cells = <2>;
667 clocks = <&tegra_car TEGRA210_ 669 clocks = <&tegra_car TEGRA210_CLK_PWM>;
>> 670 clock-names = "pwm";
668 resets = <&tegra_car 17>; 671 resets = <&tegra_car 17>;
669 reset-names = "pwm"; 672 reset-names = "pwm";
670 status = "disabled"; 673 status = "disabled";
671 }; 674 };
672 675
673 i2c@7000c000 { 676 i2c@7000c000 {
674 compatible = "nvidia,tegra210- 677 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c";
675 reg = <0x0 0x7000c000 0x0 0x10 678 reg = <0x0 0x7000c000 0x0 0x100>;
676 interrupts = <GIC_SPI 38 IRQ_T 679 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
677 #address-cells = <1>; 680 #address-cells = <1>;
678 #size-cells = <0>; 681 #size-cells = <0>;
679 clocks = <&tegra_car TEGRA210_ 682 clocks = <&tegra_car TEGRA210_CLK_I2C1>;
680 clock-names = "div-clk"; 683 clock-names = "div-clk";
681 resets = <&tegra_car 12>; 684 resets = <&tegra_car 12>;
682 reset-names = "i2c"; 685 reset-names = "i2c";
683 dmas = <&apbdma 21>, <&apbdma 686 dmas = <&apbdma 21>, <&apbdma 21>;
684 dma-names = "rx", "tx"; 687 dma-names = "rx", "tx";
685 status = "disabled"; 688 status = "disabled";
686 }; 689 };
687 690
688 i2c@7000c400 { 691 i2c@7000c400 {
689 compatible = "nvidia,tegra210- 692 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c";
690 reg = <0x0 0x7000c400 0x0 0x10 693 reg = <0x0 0x7000c400 0x0 0x100>;
691 interrupts = <GIC_SPI 84 IRQ_T 694 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
692 #address-cells = <1>; 695 #address-cells = <1>;
693 #size-cells = <0>; 696 #size-cells = <0>;
694 clocks = <&tegra_car TEGRA210_ 697 clocks = <&tegra_car TEGRA210_CLK_I2C2>;
695 clock-names = "div-clk"; 698 clock-names = "div-clk";
696 resets = <&tegra_car 54>; 699 resets = <&tegra_car 54>;
697 reset-names = "i2c"; 700 reset-names = "i2c";
698 dmas = <&apbdma 22>, <&apbdma 701 dmas = <&apbdma 22>, <&apbdma 22>;
699 dma-names = "rx", "tx"; 702 dma-names = "rx", "tx";
700 status = "disabled"; 703 status = "disabled";
701 }; 704 };
702 705
703 i2c@7000c500 { 706 i2c@7000c500 {
704 compatible = "nvidia,tegra210- 707 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c";
705 reg = <0x0 0x7000c500 0x0 0x10 708 reg = <0x0 0x7000c500 0x0 0x100>;
706 interrupts = <GIC_SPI 92 IRQ_T 709 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
707 #address-cells = <1>; 710 #address-cells = <1>;
708 #size-cells = <0>; 711 #size-cells = <0>;
709 clocks = <&tegra_car TEGRA210_ 712 clocks = <&tegra_car TEGRA210_CLK_I2C3>;
710 clock-names = "div-clk"; 713 clock-names = "div-clk";
711 resets = <&tegra_car 67>; 714 resets = <&tegra_car 67>;
712 reset-names = "i2c"; 715 reset-names = "i2c";
713 dmas = <&apbdma 23>, <&apbdma 716 dmas = <&apbdma 23>, <&apbdma 23>;
714 dma-names = "rx", "tx"; 717 dma-names = "rx", "tx";
715 status = "disabled"; 718 status = "disabled";
716 }; 719 };
717 720
718 i2c@7000c700 { 721 i2c@7000c700 {
719 compatible = "nvidia,tegra210- 722 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c";
720 reg = <0x0 0x7000c700 0x0 0x10 723 reg = <0x0 0x7000c700 0x0 0x100>;
721 interrupts = <GIC_SPI 120 IRQ_ 724 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
722 #address-cells = <1>; 725 #address-cells = <1>;
723 #size-cells = <0>; 726 #size-cells = <0>;
724 clocks = <&tegra_car TEGRA210_ 727 clocks = <&tegra_car TEGRA210_CLK_I2C4>;
725 clock-names = "div-clk"; 728 clock-names = "div-clk";
726 resets = <&tegra_car 103>; 729 resets = <&tegra_car 103>;
727 reset-names = "i2c"; 730 reset-names = "i2c";
728 dmas = <&apbdma 26>, <&apbdma 731 dmas = <&apbdma 26>, <&apbdma 26>;
729 dma-names = "rx", "tx"; 732 dma-names = "rx", "tx";
730 pinctrl-0 = <&state_dpaux1_i2c 733 pinctrl-0 = <&state_dpaux1_i2c>;
731 pinctrl-1 = <&state_dpaux1_off 734 pinctrl-1 = <&state_dpaux1_off>;
732 pinctrl-names = "default", "id 735 pinctrl-names = "default", "idle";
733 status = "disabled"; 736 status = "disabled";
734 }; 737 };
735 738
736 i2c@7000d000 { 739 i2c@7000d000 {
737 compatible = "nvidia,tegra210- 740 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c";
738 reg = <0x0 0x7000d000 0x0 0x10 741 reg = <0x0 0x7000d000 0x0 0x100>;
739 interrupts = <GIC_SPI 53 IRQ_T 742 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
740 #address-cells = <1>; 743 #address-cells = <1>;
741 #size-cells = <0>; 744 #size-cells = <0>;
742 clocks = <&tegra_car TEGRA210_ 745 clocks = <&tegra_car TEGRA210_CLK_I2C5>;
743 clock-names = "div-clk"; 746 clock-names = "div-clk";
744 resets = <&tegra_car 47>; 747 resets = <&tegra_car 47>;
745 reset-names = "i2c"; 748 reset-names = "i2c";
746 dmas = <&apbdma 24>, <&apbdma 749 dmas = <&apbdma 24>, <&apbdma 24>;
747 dma-names = "rx", "tx"; 750 dma-names = "rx", "tx";
748 status = "disabled"; 751 status = "disabled";
749 }; 752 };
750 753
751 i2c@7000d100 { 754 i2c@7000d100 {
752 compatible = "nvidia,tegra210- 755 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c";
753 reg = <0x0 0x7000d100 0x0 0x10 756 reg = <0x0 0x7000d100 0x0 0x100>;
754 interrupts = <GIC_SPI 63 IRQ_T 757 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
755 #address-cells = <1>; 758 #address-cells = <1>;
756 #size-cells = <0>; 759 #size-cells = <0>;
757 clocks = <&tegra_car TEGRA210_ 760 clocks = <&tegra_car TEGRA210_CLK_I2C6>;
758 clock-names = "div-clk"; 761 clock-names = "div-clk";
759 resets = <&tegra_car 166>; 762 resets = <&tegra_car 166>;
760 reset-names = "i2c"; 763 reset-names = "i2c";
761 dmas = <&apbdma 30>, <&apbdma 764 dmas = <&apbdma 30>, <&apbdma 30>;
762 dma-names = "rx", "tx"; 765 dma-names = "rx", "tx";
763 pinctrl-0 = <&state_dpaux_i2c> 766 pinctrl-0 = <&state_dpaux_i2c>;
764 pinctrl-1 = <&state_dpaux_off> 767 pinctrl-1 = <&state_dpaux_off>;
765 pinctrl-names = "default", "id 768 pinctrl-names = "default", "idle";
766 status = "disabled"; 769 status = "disabled";
767 }; 770 };
768 771
769 spi@7000d400 { 772 spi@7000d400 {
770 compatible = "nvidia,tegra210- 773 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
771 reg = <0x0 0x7000d400 0x0 0x20 774 reg = <0x0 0x7000d400 0x0 0x200>;
772 interrupts = <GIC_SPI 59 IRQ_T 775 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
773 #address-cells = <1>; 776 #address-cells = <1>;
774 #size-cells = <0>; 777 #size-cells = <0>;
775 clocks = <&tegra_car TEGRA210_ 778 clocks = <&tegra_car TEGRA210_CLK_SBC1>;
776 clock-names = "spi"; 779 clock-names = "spi";
777 resets = <&tegra_car 41>; 780 resets = <&tegra_car 41>;
778 reset-names = "spi"; 781 reset-names = "spi";
779 dmas = <&apbdma 15>, <&apbdma 782 dmas = <&apbdma 15>, <&apbdma 15>;
780 dma-names = "rx", "tx"; 783 dma-names = "rx", "tx";
781 status = "disabled"; 784 status = "disabled";
782 }; 785 };
783 786
784 spi@7000d600 { 787 spi@7000d600 {
785 compatible = "nvidia,tegra210- 788 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
786 reg = <0x0 0x7000d600 0x0 0x20 789 reg = <0x0 0x7000d600 0x0 0x200>;
787 interrupts = <GIC_SPI 82 IRQ_T 790 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
788 #address-cells = <1>; 791 #address-cells = <1>;
789 #size-cells = <0>; 792 #size-cells = <0>;
790 clocks = <&tegra_car TEGRA210_ 793 clocks = <&tegra_car TEGRA210_CLK_SBC2>;
791 clock-names = "spi"; 794 clock-names = "spi";
792 resets = <&tegra_car 44>; 795 resets = <&tegra_car 44>;
793 reset-names = "spi"; 796 reset-names = "spi";
794 dmas = <&apbdma 16>, <&apbdma 797 dmas = <&apbdma 16>, <&apbdma 16>;
795 dma-names = "rx", "tx"; 798 dma-names = "rx", "tx";
796 status = "disabled"; 799 status = "disabled";
797 }; 800 };
798 801
799 spi@7000d800 { 802 spi@7000d800 {
800 compatible = "nvidia,tegra210- 803 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
801 reg = <0x0 0x7000d800 0x0 0x20 804 reg = <0x0 0x7000d800 0x0 0x200>;
802 interrupts = <GIC_SPI 83 IRQ_T 805 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
803 #address-cells = <1>; 806 #address-cells = <1>;
804 #size-cells = <0>; 807 #size-cells = <0>;
805 clocks = <&tegra_car TEGRA210_ 808 clocks = <&tegra_car TEGRA210_CLK_SBC3>;
806 clock-names = "spi"; 809 clock-names = "spi";
807 resets = <&tegra_car 46>; 810 resets = <&tegra_car 46>;
808 reset-names = "spi"; 811 reset-names = "spi";
809 dmas = <&apbdma 17>, <&apbdma 812 dmas = <&apbdma 17>, <&apbdma 17>;
810 dma-names = "rx", "tx"; 813 dma-names = "rx", "tx";
811 status = "disabled"; 814 status = "disabled";
812 }; 815 };
813 816
814 spi@7000da00 { 817 spi@7000da00 {
815 compatible = "nvidia,tegra210- 818 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
816 reg = <0x0 0x7000da00 0x0 0x20 819 reg = <0x0 0x7000da00 0x0 0x200>;
817 interrupts = <GIC_SPI 93 IRQ_T 820 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
818 #address-cells = <1>; 821 #address-cells = <1>;
819 #size-cells = <0>; 822 #size-cells = <0>;
820 clocks = <&tegra_car TEGRA210_ 823 clocks = <&tegra_car TEGRA210_CLK_SBC4>;
821 clock-names = "spi"; 824 clock-names = "spi";
822 resets = <&tegra_car 68>; 825 resets = <&tegra_car 68>;
823 reset-names = "spi"; 826 reset-names = "spi";
824 dmas = <&apbdma 18>, <&apbdma 827 dmas = <&apbdma 18>, <&apbdma 18>;
825 dma-names = "rx", "tx"; 828 dma-names = "rx", "tx";
826 status = "disabled"; 829 status = "disabled";
827 }; 830 };
828 831
829 rtc@7000e000 { 832 rtc@7000e000 {
830 compatible = "nvidia,tegra210- 833 compatible = "nvidia,tegra210-rtc", "nvidia,tegra20-rtc";
831 reg = <0x0 0x7000e000 0x0 0x10 834 reg = <0x0 0x7000e000 0x0 0x100>;
832 interrupts = <16 IRQ_TYPE_LEVE 835 interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
833 interrupt-parent = <&tegra_pmc 836 interrupt-parent = <&tegra_pmc>;
834 clocks = <&tegra_car TEGRA210_ 837 clocks = <&tegra_car TEGRA210_CLK_RTC>;
835 clock-names = "rtc"; 838 clock-names = "rtc";
836 }; 839 };
837 840
838 tegra_pmc: pmc@7000e400 { 841 tegra_pmc: pmc@7000e400 {
839 compatible = "nvidia,tegra210- 842 compatible = "nvidia,tegra210-pmc";
840 reg = <0x0 0x7000e400 0x0 0x40 843 reg = <0x0 0x7000e400 0x0 0x400>;
841 clocks = <&tegra_car TEGRA210_ 844 clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>;
842 clock-names = "pclk", "clk32k_ 845 clock-names = "pclk", "clk32k_in";
843 #clock-cells = <1>; 846 #clock-cells = <1>;
844 #interrupt-cells = <2>; 847 #interrupt-cells = <2>;
845 interrupt-controller; 848 interrupt-controller;
846 849
847 pinmux { <<
848 pex_dpd_disable: pex-d <<
849 pins = "pex-bi <<
850 low-power-disa <<
851 }; <<
852 <<
853 pex_dpd_enable: pex-dp <<
854 pins = "pex-bi <<
855 low-power-enab <<
856 }; <<
857 <<
858 sdmmc1_1v8: sdmmc1-1v8 <<
859 pins = "sdmmc1 <<
860 power-source = <<
861 }; <<
862 <<
863 sdmmc1_3v3: sdmmc1-3v3 <<
864 pins = "sdmmc1 <<
865 power-source = <<
866 }; <<
867 <<
868 sdmmc3_1v8: sdmmc3-1v8 <<
869 pins = "sdmmc3 <<
870 power-source = <<
871 }; <<
872 <<
873 sdmmc3_3v3: sdmmc3-3v3 <<
874 pins = "sdmmc3 <<
875 power-source = <<
876 }; <<
877 }; <<
878 <<
879 powergates { 850 powergates {
880 pd_audio: aud { 851 pd_audio: aud {
881 clocks = <&teg 852 clocks = <&tegra_car TEGRA210_CLK_APE>,
882 <&teg 853 <&tegra_car TEGRA210_CLK_APB2APE>;
883 resets = <&teg 854 resets = <&tegra_car 198>;
884 #power-domain- 855 #power-domain-cells = <0>;
885 }; 856 };
886 857
887 pd_sor: sor { 858 pd_sor: sor {
888 clocks = <&teg 859 clocks = <&tegra_car TEGRA210_CLK_SOR0>,
889 <&teg 860 <&tegra_car TEGRA210_CLK_SOR1>,
890 <&teg 861 <&tegra_car TEGRA210_CLK_CILAB>,
891 <&teg 862 <&tegra_car TEGRA210_CLK_CILCD>,
892 <&teg 863 <&tegra_car TEGRA210_CLK_CILE>,
893 <&teg 864 <&tegra_car TEGRA210_CLK_DSIA>,
894 <&teg 865 <&tegra_car TEGRA210_CLK_DSIB>,
895 <&teg 866 <&tegra_car TEGRA210_CLK_DPAUX>,
896 <&teg 867 <&tegra_car TEGRA210_CLK_DPAUX1>,
897 <&teg 868 <&tegra_car TEGRA210_CLK_MIPI_CAL>;
898 resets = <&teg 869 resets = <&tegra_car TEGRA210_CLK_SOR0>,
899 <&teg 870 <&tegra_car TEGRA210_CLK_SOR1>,
900 <&teg 871 <&tegra_car TEGRA210_CLK_DSIA>,
901 <&teg 872 <&tegra_car TEGRA210_CLK_DSIB>,
902 <&teg 873 <&tegra_car TEGRA210_CLK_DPAUX>,
903 <&teg 874 <&tegra_car TEGRA210_CLK_DPAUX1>,
904 <&teg 875 <&tegra_car TEGRA210_CLK_MIPI_CAL>;
905 #power-domain- 876 #power-domain-cells = <0>;
906 }; 877 };
907 878
908 pd_venc: venc { <<
909 clocks = <&teg <<
910 <&teg <<
911 resets = <&mc <<
912 <&teg <<
913 <&teg <<
914 #power-domain- <<
915 }; <<
916 <<
917 pd_vic: vic { <<
918 clocks = <&teg <<
919 resets = <&teg <<
920 #power-domain- <<
921 }; <<
922 <<
923 pd_xusbss: xusba { 879 pd_xusbss: xusba {
924 clocks = <&teg 880 clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>;
925 resets = <&teg 881 resets = <&tegra_car TEGRA210_CLK_XUSB_SS>;
926 #power-domain- 882 #power-domain-cells = <0>;
927 }; 883 };
928 884
929 pd_xusbdev: xusbb { 885 pd_xusbdev: xusbb {
930 clocks = <&teg 886 clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>;
931 resets = <&teg 887 resets = <&tegra_car 95>;
932 #power-domain- 888 #power-domain-cells = <0>;
933 }; 889 };
934 890
935 pd_xusbhost: xusbc { 891 pd_xusbhost: xusbc {
936 clocks = <&teg 892 clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>;
937 resets = <&teg 893 resets = <&tegra_car TEGRA210_CLK_XUSB_HOST>;
938 #power-domain- 894 #power-domain-cells = <0>;
939 }; 895 };
>> 896
>> 897 pd_vic: vic {
>> 898 clocks = <&tegra_car TEGRA210_CLK_VIC03>;
>> 899 clock-names = "vic";
>> 900 resets = <&tegra_car 178>;
>> 901 reset-names = "vic";
>> 902 #power-domain-cells = <0>;
>> 903 };
>> 904
>> 905 pd_venc: venc {
>> 906 clocks = <&tegra_car TEGRA210_CLK_VI>,
>> 907 <&tegra_car TEGRA210_CLK_CSI>;
>> 908 resets = <&mc TEGRA210_MC_RESET_VI>,
>> 909 <&tegra_car 20>,
>> 910 <&tegra_car 52>;
>> 911 #power-domain-cells = <0>;
>> 912 };
>> 913 };
>> 914
>> 915 sdmmc1_3v3: sdmmc1-3v3 {
>> 916 pins = "sdmmc1";
>> 917 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
>> 918 };
>> 919
>> 920 sdmmc1_1v8: sdmmc1-1v8 {
>> 921 pins = "sdmmc1";
>> 922 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
>> 923 };
>> 924
>> 925 sdmmc3_3v3: sdmmc3-3v3 {
>> 926 pins = "sdmmc3";
>> 927 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
>> 928 };
>> 929
>> 930 sdmmc3_1v8: sdmmc3-1v8 {
>> 931 pins = "sdmmc3";
>> 932 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
>> 933 };
>> 934
>> 935 pex_dpd_disable: pex_en {
>> 936 pex-dpd-disable {
>> 937 pins = "pex-bias", "pex-clk1", "pex-clk2";
>> 938 low-power-disable;
>> 939 };
>> 940 };
>> 941
>> 942 pex_dpd_enable: pex_dis {
>> 943 pex-dpd-enable {
>> 944 pins = "pex-bias", "pex-clk1", "pex-clk2";
>> 945 low-power-enable;
>> 946 };
940 }; 947 };
941 }; 948 };
942 949
943 fuse@7000f800 { 950 fuse@7000f800 {
944 compatible = "nvidia,tegra210- 951 compatible = "nvidia,tegra210-efuse";
945 reg = <0x0 0x7000f800 0x0 0x40 952 reg = <0x0 0x7000f800 0x0 0x400>;
946 clocks = <&tegra_car TEGRA210_ 953 clocks = <&tegra_car TEGRA210_CLK_FUSE>;
947 clock-names = "fuse"; 954 clock-names = "fuse";
948 resets = <&tegra_car 39>; 955 resets = <&tegra_car 39>;
949 reset-names = "fuse"; 956 reset-names = "fuse";
950 }; 957 };
951 958
952 mc: memory-controller@70019000 { 959 mc: memory-controller@70019000 {
953 compatible = "nvidia,tegra210- 960 compatible = "nvidia,tegra210-mc";
954 reg = <0x0 0x70019000 0x0 0x10 961 reg = <0x0 0x70019000 0x0 0x1000>;
955 clocks = <&tegra_car TEGRA210_ 962 clocks = <&tegra_car TEGRA210_CLK_MC>;
956 clock-names = "mc"; 963 clock-names = "mc";
957 964
958 interrupts = <GIC_SPI 77 IRQ_T 965 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
959 966
960 #iommu-cells = <1>; 967 #iommu-cells = <1>;
961 #reset-cells = <1>; 968 #reset-cells = <1>;
962 }; 969 };
963 970
964 emc: external-memory-controller@7001b0 971 emc: external-memory-controller@7001b000 {
965 compatible = "nvidia,tegra210- 972 compatible = "nvidia,tegra210-emc";
966 reg = <0x0 0x7001b000 0x0 0x10 973 reg = <0x0 0x7001b000 0x0 0x1000>,
967 <0x0 0x7001e000 0x0 0x10 974 <0x0 0x7001e000 0x0 0x1000>,
968 <0x0 0x7001f000 0x0 0x10 975 <0x0 0x7001f000 0x0 0x1000>;
969 clocks = <&tegra_car TEGRA210_ 976 clocks = <&tegra_car TEGRA210_CLK_EMC>;
970 clock-names = "emc"; 977 clock-names = "emc";
971 interrupts = <GIC_SPI 78 IRQ_T 978 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
972 nvidia,memory-controller = <&m 979 nvidia,memory-controller = <&mc>;
973 #cooling-cells = <2>; 980 #cooling-cells = <2>;
974 }; 981 };
975 982
976 sata@70020000 { 983 sata@70020000 {
977 compatible = "nvidia,tegra210- 984 compatible = "nvidia,tegra210-ahci";
978 reg = <0x0 0x70027000 0x0 0x20 985 reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */
979 <0x0 0x70020000 0x0 0x70 986 <0x0 0x70020000 0x0 0x7000>, /* SATA */
980 <0x0 0x70001100 0x0 0x10 987 <0x0 0x70001100 0x0 0x1000>; /* SATA AUX */
981 interrupts = <GIC_SPI 23 IRQ_T 988 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
982 clocks = <&tegra_car TEGRA210_ 989 clocks = <&tegra_car TEGRA210_CLK_SATA>,
983 <&tegra_car TEGRA210_ 990 <&tegra_car TEGRA210_CLK_SATA_OOB>;
984 clock-names = "sata", "sata-oo 991 clock-names = "sata", "sata-oob";
985 resets = <&tegra_car 124>, 992 resets = <&tegra_car 124>,
986 <&tegra_car 129>, 993 <&tegra_car 129>,
987 <&tegra_car 123>; 994 <&tegra_car 123>;
988 reset-names = "sata", "sata-co 995 reset-names = "sata", "sata-cold", "sata-oob";
989 status = "disabled"; 996 status = "disabled";
990 }; 997 };
991 998
992 hda@70030000 { 999 hda@70030000 {
993 compatible = "nvidia,tegra210- 1000 compatible = "nvidia,tegra210-hda", "nvidia,tegra30-hda";
994 reg = <0x0 0x70030000 0x0 0x10 1001 reg = <0x0 0x70030000 0x0 0x10000>;
995 interrupts = <GIC_SPI 81 IRQ_T 1002 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
996 clocks = <&tegra_car TEGRA210_ 1003 clocks = <&tegra_car TEGRA210_CLK_HDA>,
997 <&tegra_car TEGRA210_ 1004 <&tegra_car TEGRA210_CLK_HDA2HDMI>,
998 <&tegra_car TEGRA210_ 1005 <&tegra_car TEGRA210_CLK_HDA2CODEC_2X>;
999 clock-names = "hda", "hda2hdmi 1006 clock-names = "hda", "hda2hdmi", "hda2codec_2x";
1000 resets = <&tegra_car 125>, /* 1007 resets = <&tegra_car 125>, /* hda */
1001 <&tegra_car 128>, /* 1008 <&tegra_car 128>, /* hda2hdmi */
1002 <&tegra_car 111>; /* 1009 <&tegra_car 111>; /* hda2codec_2x */
1003 reset-names = "hda", "hda2hdm 1010 reset-names = "hda", "hda2hdmi", "hda2codec_2x";
1004 power-domains = <&pd_sor>; 1011 power-domains = <&pd_sor>;
1005 status = "disabled"; 1012 status = "disabled";
1006 }; 1013 };
1007 1014
1008 usb@70090000 { 1015 usb@70090000 {
1009 compatible = "nvidia,tegra210 1016 compatible = "nvidia,tegra210-xusb";
1010 reg = <0x0 0x70090000 0x0 0x8 1017 reg = <0x0 0x70090000 0x0 0x8000>,
1011 <0x0 0x70098000 0x0 0x1 1018 <0x0 0x70098000 0x0 0x1000>,
1012 <0x0 0x70099000 0x0 0x1 1019 <0x0 0x70099000 0x0 0x1000>;
1013 reg-names = "hcd", "fpci", "i 1020 reg-names = "hcd", "fpci", "ipfs";
1014 1021
1015 interrupts = <GIC_SPI 39 IRQ_ 1022 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
1016 <GIC_SPI 40 IRQ_ 1023 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1017 1024
1018 clocks = <&tegra_car TEGRA210 1025 clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>,
1019 <&tegra_car TEGRA210 1026 <&tegra_car TEGRA210_CLK_XUSB_HOST_SRC>,
1020 <&tegra_car TEGRA210 1027 <&tegra_car TEGRA210_CLK_XUSB_FALCON_SRC>,
1021 <&tegra_car TEGRA210 1028 <&tegra_car TEGRA210_CLK_XUSB_SS>,
1022 <&tegra_car TEGRA210 1029 <&tegra_car TEGRA210_CLK_XUSB_SS_DIV2>,
1023 <&tegra_car TEGRA210 1030 <&tegra_car TEGRA210_CLK_XUSB_SS_SRC>,
1024 <&tegra_car TEGRA210 1031 <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>,
1025 <&tegra_car TEGRA210 1032 <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>,
1026 <&tegra_car TEGRA210 1033 <&tegra_car TEGRA210_CLK_PLL_U_480M>,
1027 <&tegra_car TEGRA210 1034 <&tegra_car TEGRA210_CLK_CLK_M>,
1028 <&tegra_car TEGRA210 1035 <&tegra_car TEGRA210_CLK_PLL_E>;
1029 clock-names = "xusb_host", "x 1036 clock-names = "xusb_host", "xusb_host_src",
1030 "xusb_falcon_sr 1037 "xusb_falcon_src", "xusb_ss",
1031 "xusb_ss_div2", 1038 "xusb_ss_div2", "xusb_ss_src",
1032 "xusb_hs_src", 1039 "xusb_hs_src", "xusb_fs_src",
1033 "pll_u_480m", " 1040 "pll_u_480m", "clk_m", "pll_e";
1034 resets = <&tegra_car 89>, <&t 1041 resets = <&tegra_car 89>, <&tegra_car 156>,
1035 <&tegra_car 143>; 1042 <&tegra_car 143>;
1036 reset-names = "xusb_host", "x 1043 reset-names = "xusb_host", "xusb_ss", "xusb_src";
1037 power-domains = <&pd_xusbhost 1044 power-domains = <&pd_xusbhost>, <&pd_xusbss>;
1038 power-domain-names = "xusb_ho 1045 power-domain-names = "xusb_host", "xusb_ss";
1039 1046
1040 nvidia,xusb-padctl = <&padctl 1047 nvidia,xusb-padctl = <&padctl>;
1041 1048
1042 status = "disabled"; 1049 status = "disabled";
1043 }; 1050 };
1044 1051
1045 padctl: padctl@7009f000 { 1052 padctl: padctl@7009f000 {
1046 compatible = "nvidia,tegra210 1053 compatible = "nvidia,tegra210-xusb-padctl";
1047 reg = <0x0 0x7009f000 0x0 0x1 1054 reg = <0x0 0x7009f000 0x0 0x1000>;
1048 interrupts = <GIC_SPI 49 IRQ_ 1055 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
1049 resets = <&tegra_car 142>; 1056 resets = <&tegra_car 142>;
1050 reset-names = "padctl"; 1057 reset-names = "padctl";
1051 nvidia,pmc = <&tegra_pmc>; !! 1058 nvidia,pmc = <&tegra_pmc>;
1052 1059
1053 status = "disabled"; 1060 status = "disabled";
1054 1061
1055 pads { 1062 pads {
1056 usb2 { 1063 usb2 {
1057 clocks = <&te 1064 clocks = <&tegra_car TEGRA210_CLK_USB2_TRK>;
1058 clock-names = 1065 clock-names = "trk";
1059 status = "dis 1066 status = "disabled";
1060 1067
1061 lanes { 1068 lanes {
1062 usb2- 1069 usb2-0 {
1063 1070 status = "disabled";
1064 1071 #phy-cells = <0>;
1065 }; 1072 };
1066 1073
1067 usb2- 1074 usb2-1 {
1068 1075 status = "disabled";
1069 1076 #phy-cells = <0>;
1070 }; 1077 };
1071 1078
1072 usb2- 1079 usb2-2 {
1073 1080 status = "disabled";
1074 1081 #phy-cells = <0>;
1075 }; 1082 };
1076 1083
1077 usb2- 1084 usb2-3 {
1078 1085 status = "disabled";
1079 1086 #phy-cells = <0>;
1080 }; 1087 };
1081 }; 1088 };
1082 }; 1089 };
1083 1090
1084 hsic { 1091 hsic {
1085 clocks = <&te 1092 clocks = <&tegra_car TEGRA210_CLK_HSIC_TRK>;
1086 clock-names = 1093 clock-names = "trk";
1087 status = "dis 1094 status = "disabled";
1088 1095
1089 lanes { 1096 lanes {
1090 hsic- 1097 hsic-0 {
1091 1098 status = "disabled";
1092 1099 #phy-cells = <0>;
1093 }; 1100 };
1094 1101
1095 hsic- 1102 hsic-1 {
1096 1103 status = "disabled";
1097 1104 #phy-cells = <0>;
1098 }; 1105 };
1099 }; 1106 };
1100 }; 1107 };
1101 1108
1102 pcie { 1109 pcie {
1103 clocks = <&te 1110 clocks = <&tegra_car TEGRA210_CLK_PLL_E>;
1104 clock-names = 1111 clock-names = "pll";
1105 resets = <&te 1112 resets = <&tegra_car 205>;
1106 reset-names = 1113 reset-names = "phy";
1107 status = "dis 1114 status = "disabled";
1108 1115
1109 lanes { 1116 lanes {
1110 pcie- 1117 pcie-0 {
1111 1118 status = "disabled";
1112 1119 #phy-cells = <0>;
1113 }; 1120 };
1114 1121
1115 pcie- 1122 pcie-1 {
1116 1123 status = "disabled";
1117 1124 #phy-cells = <0>;
1118 }; 1125 };
1119 1126
1120 pcie- 1127 pcie-2 {
1121 1128 status = "disabled";
1122 1129 #phy-cells = <0>;
1123 }; 1130 };
1124 1131
1125 pcie- 1132 pcie-3 {
1126 1133 status = "disabled";
1127 1134 #phy-cells = <0>;
1128 }; 1135 };
1129 1136
1130 pcie- 1137 pcie-4 {
1131 1138 status = "disabled";
1132 1139 #phy-cells = <0>;
1133 }; 1140 };
1134 1141
1135 pcie- 1142 pcie-5 {
1136 1143 status = "disabled";
1137 1144 #phy-cells = <0>;
1138 }; 1145 };
1139 1146
1140 pcie- 1147 pcie-6 {
1141 1148 status = "disabled";
1142 1149 #phy-cells = <0>;
1143 }; 1150 };
1144 }; 1151 };
1145 }; 1152 };
1146 1153
1147 sata { 1154 sata {
1148 clocks = <&te 1155 clocks = <&tegra_car TEGRA210_CLK_PLL_E>;
1149 clock-names = 1156 clock-names = "pll";
1150 resets = <&te 1157 resets = <&tegra_car 204>;
1151 reset-names = 1158 reset-names = "phy";
1152 status = "dis 1159 status = "disabled";
1153 1160
1154 lanes { 1161 lanes {
1155 sata- 1162 sata-0 {
1156 1163 status = "disabled";
1157 1164 #phy-cells = <0>;
1158 }; 1165 };
1159 }; 1166 };
1160 }; 1167 };
1161 }; 1168 };
1162 1169
1163 ports { 1170 ports {
1164 usb2-0 { 1171 usb2-0 {
1165 status = "dis 1172 status = "disabled";
1166 }; 1173 };
1167 1174
1168 usb2-1 { 1175 usb2-1 {
1169 status = "dis 1176 status = "disabled";
1170 }; 1177 };
1171 1178
1172 usb2-2 { 1179 usb2-2 {
1173 status = "dis 1180 status = "disabled";
1174 }; 1181 };
1175 1182
1176 usb2-3 { 1183 usb2-3 {
1177 status = "dis 1184 status = "disabled";
1178 }; 1185 };
1179 1186
1180 hsic-0 { 1187 hsic-0 {
1181 status = "dis 1188 status = "disabled";
1182 }; 1189 };
1183 1190
1184 usb3-0 { 1191 usb3-0 {
1185 status = "dis 1192 status = "disabled";
1186 }; 1193 };
1187 1194
1188 usb3-1 { 1195 usb3-1 {
1189 status = "dis 1196 status = "disabled";
1190 }; 1197 };
1191 1198
1192 usb3-2 { 1199 usb3-2 {
1193 status = "dis 1200 status = "disabled";
1194 }; 1201 };
1195 1202
1196 usb3-3 { 1203 usb3-3 {
1197 status = "dis 1204 status = "disabled";
1198 }; 1205 };
1199 }; 1206 };
1200 }; 1207 };
1201 1208
1202 mmc@700b0000 { 1209 mmc@700b0000 {
1203 compatible = "nvidia,tegra210 1210 compatible = "nvidia,tegra210-sdhci";
1204 reg = <0x0 0x700b0000 0x0 0x2 1211 reg = <0x0 0x700b0000 0x0 0x200>;
1205 interrupts = <GIC_SPI 14 IRQ_ 1212 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1206 clocks = <&tegra_car TEGRA210 1213 clocks = <&tegra_car TEGRA210_CLK_SDMMC1>,
1207 <&tegra_car TEGRA210 1214 <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>;
1208 clock-names = "sdhci", "tmclk 1215 clock-names = "sdhci", "tmclk";
1209 resets = <&tegra_car 14>; 1216 resets = <&tegra_car 14>;
1210 reset-names = "sdhci"; 1217 reset-names = "sdhci";
1211 pinctrl-names = "sdmmc-3v3", 1218 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8",
1212 "sdmmc-3v3-dr 1219 "sdmmc-3v3-drv", "sdmmc-1v8-drv";
1213 pinctrl-0 = <&sdmmc1_3v3>; 1220 pinctrl-0 = <&sdmmc1_3v3>;
1214 pinctrl-1 = <&sdmmc1_1v8>; 1221 pinctrl-1 = <&sdmmc1_1v8>;
1215 pinctrl-2 = <&sdmmc1_3v3_drv> 1222 pinctrl-2 = <&sdmmc1_3v3_drv>;
1216 pinctrl-3 = <&sdmmc1_1v8_drv> 1223 pinctrl-3 = <&sdmmc1_1v8_drv>;
1217 nvidia,pad-autocal-pull-up-of 1224 nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>;
1218 nvidia,pad-autocal-pull-down- 1225 nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>;
1219 nvidia,pad-autocal-pull-up-of 1226 nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>;
1220 nvidia,pad-autocal-pull-down- 1227 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>;
1221 nvidia,default-tap = <0x2>; 1228 nvidia,default-tap = <0x2>;
1222 nvidia,default-trim = <0x4>; 1229 nvidia,default-trim = <0x4>;
1223 assigned-clocks = <&tegra_car 1230 assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>,
1224 <&tegra_car 1231 <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>,
1225 <&tegra_car 1232 <&tegra_car TEGRA210_CLK_PLL_C4>;
1226 assigned-clock-parents = <&te 1233 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
1227 assigned-clock-rates = <20000 1234 assigned-clock-rates = <200000000>, <1000000000>, <1000000000>;
1228 status = "disabled"; 1235 status = "disabled";
1229 }; 1236 };
1230 1237
1231 mmc@700b0200 { 1238 mmc@700b0200 {
1232 compatible = "nvidia,tegra210 1239 compatible = "nvidia,tegra210-sdhci";
1233 reg = <0x0 0x700b0200 0x0 0x2 1240 reg = <0x0 0x700b0200 0x0 0x200>;
1234 interrupts = <GIC_SPI 15 IRQ_ 1241 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1235 clocks = <&tegra_car TEGRA210 1242 clocks = <&tegra_car TEGRA210_CLK_SDMMC2>,
1236 <&tegra_car TEGRA210 1243 <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>;
1237 clock-names = "sdhci", "tmclk 1244 clock-names = "sdhci", "tmclk";
1238 resets = <&tegra_car 9>; 1245 resets = <&tegra_car 9>;
1239 reset-names = "sdhci"; 1246 reset-names = "sdhci";
1240 pinctrl-names = "sdmmc-1v8-dr 1247 pinctrl-names = "sdmmc-1v8-drv";
1241 pinctrl-0 = <&sdmmc2_1v8_drv> 1248 pinctrl-0 = <&sdmmc2_1v8_drv>;
1242 nvidia,pad-autocal-pull-up-of 1249 nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>;
1243 nvidia,pad-autocal-pull-down- 1250 nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>;
1244 nvidia,default-tap = <0x8>; 1251 nvidia,default-tap = <0x8>;
1245 nvidia,default-trim = <0x0>; 1252 nvidia,default-trim = <0x0>;
1246 status = "disabled"; 1253 status = "disabled";
1247 }; 1254 };
1248 1255
1249 mmc@700b0400 { 1256 mmc@700b0400 {
1250 compatible = "nvidia,tegra210 1257 compatible = "nvidia,tegra210-sdhci";
1251 reg = <0x0 0x700b0400 0x0 0x2 1258 reg = <0x0 0x700b0400 0x0 0x200>;
1252 interrupts = <GIC_SPI 19 IRQ_ 1259 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1253 clocks = <&tegra_car TEGRA210 1260 clocks = <&tegra_car TEGRA210_CLK_SDMMC3>,
1254 <&tegra_car TEGRA210 1261 <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>;
1255 clock-names = "sdhci", "tmclk 1262 clock-names = "sdhci", "tmclk";
1256 resets = <&tegra_car 69>; 1263 resets = <&tegra_car 69>;
1257 reset-names = "sdhci"; 1264 reset-names = "sdhci";
1258 pinctrl-names = "sdmmc-3v3", 1265 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8",
1259 "sdmmc-3v3-dr 1266 "sdmmc-3v3-drv", "sdmmc-1v8-drv";
1260 pinctrl-0 = <&sdmmc3_3v3>; 1267 pinctrl-0 = <&sdmmc3_3v3>;
1261 pinctrl-1 = <&sdmmc3_1v8>; 1268 pinctrl-1 = <&sdmmc3_1v8>;
1262 pinctrl-2 = <&sdmmc3_3v3_drv> 1269 pinctrl-2 = <&sdmmc3_3v3_drv>;
1263 pinctrl-3 = <&sdmmc3_1v8_drv> 1270 pinctrl-3 = <&sdmmc3_1v8_drv>;
1264 nvidia,pad-autocal-pull-up-of 1271 nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>;
1265 nvidia,pad-autocal-pull-down- 1272 nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>;
1266 nvidia,pad-autocal-pull-up-of 1273 nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>;
1267 nvidia,pad-autocal-pull-down- 1274 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>;
1268 nvidia,default-tap = <0x3>; 1275 nvidia,default-tap = <0x3>;
1269 nvidia,default-trim = <0x3>; 1276 nvidia,default-trim = <0x3>;
1270 status = "disabled"; 1277 status = "disabled";
1271 }; 1278 };
1272 1279
1273 mmc@700b0600 { 1280 mmc@700b0600 {
1274 compatible = "nvidia,tegra210 1281 compatible = "nvidia,tegra210-sdhci";
1275 reg = <0x0 0x700b0600 0x0 0x2 1282 reg = <0x0 0x700b0600 0x0 0x200>;
1276 interrupts = <GIC_SPI 31 IRQ_ 1283 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
1277 clocks = <&tegra_car TEGRA210 1284 clocks = <&tegra_car TEGRA210_CLK_SDMMC4>,
1278 <&tegra_car TEGRA210 1285 <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>;
1279 clock-names = "sdhci", "tmclk 1286 clock-names = "sdhci", "tmclk";
1280 resets = <&tegra_car 15>; 1287 resets = <&tegra_car 15>;
1281 reset-names = "sdhci"; 1288 reset-names = "sdhci";
1282 pinctrl-names = "sdmmc-3v3-dr 1289 pinctrl-names = "sdmmc-3v3-drv", "sdmmc-1v8-drv";
1283 pinctrl-0 = <&sdmmc4_1v8_drv> 1290 pinctrl-0 = <&sdmmc4_1v8_drv>;
1284 pinctrl-1 = <&sdmmc4_1v8_drv> 1291 pinctrl-1 = <&sdmmc4_1v8_drv>;
1285 nvidia,pad-autocal-pull-up-of 1292 nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>;
1286 nvidia,pad-autocal-pull-down- 1293 nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>;
1287 nvidia,default-tap = <0x8>; 1294 nvidia,default-tap = <0x8>;
1288 nvidia,default-trim = <0x0>; 1295 nvidia,default-trim = <0x0>;
1289 assigned-clocks = <&tegra_car 1296 assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>,
1290 <&tegra_car 1297 <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
1291 assigned-clock-parents = <&te 1298 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
1292 nvidia,dqs-trim = <40>; 1299 nvidia,dqs-trim = <40>;
1293 mmc-hs400-1_8v; 1300 mmc-hs400-1_8v;
1294 status = "disabled"; 1301 status = "disabled";
1295 }; 1302 };
1296 1303
1297 usb@700d0000 { 1304 usb@700d0000 {
1298 compatible = "nvidia,tegra210 1305 compatible = "nvidia,tegra210-xudc";
1299 reg = <0x0 0x700d0000 0x0 0x8 1306 reg = <0x0 0x700d0000 0x0 0x8000>,
1300 <0x0 0x700d8000 0x0 0x1 1307 <0x0 0x700d8000 0x0 0x1000>,
1301 <0x0 0x700d9000 0x0 0x1 1308 <0x0 0x700d9000 0x0 0x1000>;
1302 reg-names = "base", "fpci", " 1309 reg-names = "base", "fpci", "ipfs";
1303 interrupts = <GIC_SPI 44 IRQ_ 1310 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
1304 clocks = <&tegra_car TEGRA210 1311 clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>,
1305 <&tegra_car TEGRA210 1312 <&tegra_car TEGRA210_CLK_XUSB_SS>,
1306 <&tegra_car TEGRA210 1313 <&tegra_car TEGRA210_CLK_XUSB_SSP_SRC>,
1307 <&tegra_car TEGRA210 1314 <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>,
1308 <&tegra_car TEGRA210 1315 <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>;
1309 clock-names = "dev", "ss", "s 1316 clock-names = "dev", "ss", "ss_src", "fs_src", "hs_src";
1310 power-domains = <&pd_xusbdev> 1317 power-domains = <&pd_xusbdev>, <&pd_xusbss>;
1311 power-domain-names = "dev", " 1318 power-domain-names = "dev", "ss";
1312 nvidia,xusb-padctl = <&padctl 1319 nvidia,xusb-padctl = <&padctl>;
1313 status = "disabled"; 1320 status = "disabled";
1314 }; 1321 };
1315 1322
1316 soctherm: thermal-sensor@700e2000 { 1323 soctherm: thermal-sensor@700e2000 {
1317 compatible = "nvidia,tegra210 1324 compatible = "nvidia,tegra210-soctherm";
1318 reg = <0x0 0x700e2000 0x0 0x6 1325 reg = <0x0 0x700e2000 0x0 0x600>, /* SOC_THERM reg_base */
1319 <0x0 0x60006000 0x0 0x4 1326 <0x0 0x60006000 0x0 0x400>; /* CAR reg_base */
1320 reg-names = "soctherm-reg", " 1327 reg-names = "soctherm-reg", "car-reg";
1321 interrupts = <GIC_SPI 48 IRQ_ 1328 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
1322 <GIC_SPI 51 IRQ_ 1329 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
1323 interrupt-names = "thermal", 1330 interrupt-names = "thermal", "edp";
1324 clocks = <&tegra_car TEGRA210 1331 clocks = <&tegra_car TEGRA210_CLK_TSENSOR>,
1325 <&tegra_car TEGRA210_ 1332 <&tegra_car TEGRA210_CLK_SOC_THERM>;
1326 clock-names = "tsensor", "soc 1333 clock-names = "tsensor", "soctherm";
1327 resets = <&tegra_car 78>; 1334 resets = <&tegra_car 78>;
1328 reset-names = "soctherm"; 1335 reset-names = "soctherm";
1329 #thermal-sensor-cells = <1>; 1336 #thermal-sensor-cells = <1>;
1330 1337
1331 throttle-cfgs { 1338 throttle-cfgs {
1332 throttle_heavy: heavy 1339 throttle_heavy: heavy {
1333 nvidia,priori 1340 nvidia,priority = <100>;
1334 nvidia,cpu-th 1341 nvidia,cpu-throt-percent = <85>;
1335 nvidia,gpu-th 1342 nvidia,gpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_HIGH>;
1336 1343
1337 #cooling-cell 1344 #cooling-cells = <2>;
1338 }; 1345 };
1339 }; 1346 };
1340 }; 1347 };
1341 1348
1342 mipi: mipi@700e3000 { 1349 mipi: mipi@700e3000 {
1343 compatible = "nvidia,tegra210 1350 compatible = "nvidia,tegra210-mipi";
1344 reg = <0x0 0x700e3000 0x0 0x1 1351 reg = <0x0 0x700e3000 0x0 0x100>;
1345 clocks = <&tegra_car TEGRA210 1352 clocks = <&tegra_car TEGRA210_CLK_MIPI_CAL>;
1346 clock-names = "mipi-cal"; 1353 clock-names = "mipi-cal";
1347 power-domains = <&pd_sor>; 1354 power-domains = <&pd_sor>;
1348 #nvidia,mipi-calibrate-cells 1355 #nvidia,mipi-calibrate-cells = <1>;
1349 }; 1356 };
1350 1357
1351 dfll: clock@70110000 { 1358 dfll: clock@70110000 {
1352 compatible = "nvidia,tegra210 1359 compatible = "nvidia,tegra210-dfll";
1353 reg = <0 0x70110000 0 0x100>, 1360 reg = <0 0x70110000 0 0x100>, /* DFLL control */
1354 <0 0x70110000 0 0x100>, 1361 <0 0x70110000 0 0x100>, /* I2C output control */
1355 <0 0x70110100 0 0x100>, 1362 <0 0x70110100 0 0x100>, /* Integrated I2C controller */
1356 <0 0x70110200 0 0x100>; 1363 <0 0x70110200 0 0x100>; /* Look-up table RAM */
1357 interrupts = <GIC_SPI 62 IRQ_ 1364 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
1358 clocks = <&tegra_car TEGRA210 1365 clocks = <&tegra_car TEGRA210_CLK_DFLL_SOC>,
1359 <&tegra_car TEGRA210 1366 <&tegra_car TEGRA210_CLK_DFLL_REF>,
1360 <&tegra_car TEGRA210 1367 <&tegra_car TEGRA210_CLK_I2C5>;
1361 clock-names = "soc", "ref", " 1368 clock-names = "soc", "ref", "i2c";
1362 resets = <&tegra_car TEGRA210 1369 resets = <&tegra_car TEGRA210_RST_DFLL_DVCO>,
1363 <&tegra_car 155>; 1370 <&tegra_car 155>;
1364 reset-names = "dvco", "dfll"; 1371 reset-names = "dvco", "dfll";
1365 #clock-cells = <0>; 1372 #clock-cells = <0>;
1366 clock-output-names = "dfllCPU 1373 clock-output-names = "dfllCPU_out";
1367 status = "disabled"; 1374 status = "disabled";
1368 }; 1375 };
1369 1376
1370 aconnect@702c0000 { 1377 aconnect@702c0000 {
1371 compatible = "nvidia,tegra210 1378 compatible = "nvidia,tegra210-aconnect";
1372 clocks = <&tegra_car TEGRA210 1379 clocks = <&tegra_car TEGRA210_CLK_APE>,
1373 <&tegra_car TEGRA210 1380 <&tegra_car TEGRA210_CLK_APB2APE>;
1374 clock-names = "ape", "apb2ape 1381 clock-names = "ape", "apb2ape";
1375 power-domains = <&pd_audio>; 1382 power-domains = <&pd_audio>;
1376 #address-cells = <1>; 1383 #address-cells = <1>;
1377 #size-cells = <1>; 1384 #size-cells = <1>;
1378 ranges = <0x702c0000 0x0 0x70 1385 ranges = <0x702c0000 0x0 0x702c0000 0x00040000>;
1379 status = "disabled"; 1386 status = "disabled";
1380 1387
>> 1388 adma: dma-controller@702e2000 {
>> 1389 compatible = "nvidia,tegra210-adma";
>> 1390 reg = <0x702e2000 0x2000>;
>> 1391 interrupt-parent = <&agic>;
>> 1392 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
>> 1393 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
>> 1394 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
>> 1395 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
>> 1396 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
>> 1397 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
>> 1398 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
>> 1399 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
>> 1400 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
>> 1401 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
>> 1402 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
>> 1403 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
>> 1404 <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
>> 1405 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
>> 1406 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
>> 1407 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
>> 1408 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
>> 1409 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
>> 1410 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
>> 1411 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
>> 1412 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
>> 1413 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
>> 1414 #dma-cells = <1>;
>> 1415 clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>;
>> 1416 clock-names = "d_audio";
>> 1417 status = "disabled";
>> 1418 };
>> 1419
>> 1420 agic: interrupt-controller@702f9000 {
>> 1421 compatible = "nvidia,tegra210-agic";
>> 1422 #interrupt-cells = <3>;
>> 1423 interrupt-controller;
>> 1424 reg = <0x702f9000 0x1000>,
>> 1425 <0x702fa000 0x2000>;
>> 1426 interrupts = <GIC_SPI 102 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
>> 1427 clocks = <&tegra_car TEGRA210_CLK_APE>;
>> 1428 clock-names = "clk";
>> 1429 status = "disabled";
>> 1430 };
>> 1431
1381 tegra_ahub: ahub@702d0800 { 1432 tegra_ahub: ahub@702d0800 {
1382 compatible = "nvidia, 1433 compatible = "nvidia,tegra210-ahub";
1383 reg = <0x702d0800 0x8 1434 reg = <0x702d0800 0x800>;
1384 clocks = <&tegra_car 1435 clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>;
1385 clock-names = "ahub"; 1436 clock-names = "ahub";
1386 assigned-clocks = <&t 1437 assigned-clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>;
1387 assigned-clock-parent !! 1438 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
1388 assigned-clock-rates <<
1389 #address-cells = <1>; 1439 #address-cells = <1>;
1390 #size-cells = <1>; 1440 #size-cells = <1>;
1391 ranges = <0x702d0000 1441 ranges = <0x702d0000 0x702d0000 0x0000e400>;
1392 status = "disabled"; 1442 status = "disabled";
1393 1443
1394 tegra_admaif: admaif@ 1444 tegra_admaif: admaif@702d0000 {
1395 compatible = 1445 compatible = "nvidia,tegra210-admaif";
1396 reg = <0x702d 1446 reg = <0x702d0000 0x800>;
1397 dmas = <&adma 1447 dmas = <&adma 1>, <&adma 1>,
1398 <&adma 1448 <&adma 2>, <&adma 2>,
1399 <&adma 1449 <&adma 3>, <&adma 3>,
1400 <&adma 1450 <&adma 4>, <&adma 4>,
1401 <&adma 1451 <&adma 5>, <&adma 5>,
1402 <&adma 1452 <&adma 6>, <&adma 6>,
1403 <&adma 1453 <&adma 7>, <&adma 7>,
1404 <&adma 1454 <&adma 8>, <&adma 8>,
1405 <&adma 1455 <&adma 9>, <&adma 9>,
1406 <&adma 1456 <&adma 10>, <&adma 10>;
1407 dma-names = " 1457 dma-names = "rx1", "tx1",
1408 " 1458 "rx2", "tx2",
1409 " 1459 "rx3", "tx3",
1410 " 1460 "rx4", "tx4",
1411 " 1461 "rx5", "tx5",
1412 " 1462 "rx6", "tx6",
1413 " 1463 "rx7", "tx7",
1414 " 1464 "rx8", "tx8",
1415 " 1465 "rx9", "tx9",
1416 " 1466 "rx10", "tx10";
1417 status = "dis 1467 status = "disabled";
1418 1468
1419 ports { 1469 ports {
1420 #addr 1470 #address-cells = <1>;
1421 #size 1471 #size-cells = <0>;
1422 1472
1423 admai 1473 admaif1_port: port@0 {
1424 1474 reg = <0>;
1425 1475
1426 1476 admaif1_ep: endpoint {
1427 1477 remote-endpoint = <&xbar_admaif1_ep>;
1428 1478 };
1429 }; 1479 };
1430 1480
1431 admai 1481 admaif2_port: port@1 {
1432 1482 reg = <1>;
1433 1483
1434 1484 admaif2_ep: endpoint {
1435 1485 remote-endpoint = <&xbar_admaif2_ep>;
1436 1486 };
1437 }; 1487 };
1438 1488
1439 admai 1489 admaif3_port: port@2 {
1440 1490 reg = <2>;
1441 1491
1442 1492 admaif3_ep: endpoint {
1443 1493 remote-endpoint = <&xbar_admaif3_ep>;
1444 1494 };
1445 }; 1495 };
1446 1496
1447 admai 1497 admaif4_port: port@3 {
1448 1498 reg = <3>;
1449 1499
1450 1500 admaif4_ep: endpoint {
1451 1501 remote-endpoint = <&xbar_admaif4_ep>;
1452 1502 };
1453 }; 1503 };
1454 1504
1455 admai 1505 admaif5_port: port@4 {
1456 1506 reg = <4>;
1457 1507
1458 1508 admaif5_ep: endpoint {
1459 1509 remote-endpoint = <&xbar_admaif5_ep>;
1460 1510 };
1461 }; 1511 };
1462 1512
1463 admai 1513 admaif6_port: port@5 {
1464 1514 reg = <5>;
1465 1515
1466 1516 admaif6_ep: endpoint {
1467 1517 remote-endpoint = <&xbar_admaif6_ep>;
1468 1518 };
1469 }; 1519 };
1470 1520
1471 admai 1521 admaif7_port: port@6 {
1472 1522 reg = <6>;
1473 1523
1474 1524 admaif7_ep: endpoint {
1475 1525 remote-endpoint = <&xbar_admaif7_ep>;
1476 1526 };
1477 }; 1527 };
1478 1528
1479 admai 1529 admaif8_port: port@7 {
1480 1530 reg = <7>;
1481 1531
1482 1532 admaif8_ep: endpoint {
1483 1533 remote-endpoint = <&xbar_admaif8_ep>;
1484 1534 };
1485 }; 1535 };
1486 1536
1487 admai 1537 admaif9_port: port@8 {
1488 1538 reg = <8>;
1489 1539
1490 1540 admaif9_ep: endpoint {
1491 1541 remote-endpoint = <&xbar_admaif9_ep>;
1492 1542 };
1493 }; 1543 };
1494 1544
1495 admai 1545 admaif10_port: port@9 {
1496 1546 reg = <9>;
1497 1547
1498 1548 admaif10_ep: endpoint {
1499 1549 remote-endpoint = <&xbar_admaif10_ep>;
1500 1550 };
1501 }; 1551 };
1502 }; 1552 };
1503 }; 1553 };
1504 1554
1505 tegra_i2s1: i2s@702d1 1555 tegra_i2s1: i2s@702d1000 {
1506 compatible = 1556 compatible = "nvidia,tegra210-i2s";
1507 reg = <0x702d 1557 reg = <0x702d1000 0x100>;
1508 clocks = <&te 1558 clocks = <&tegra_car TEGRA210_CLK_I2S0>,
1509 <&te 1559 <&tegra_car TEGRA210_CLK_I2S0_SYNC>;
1510 clock-names = 1560 clock-names = "i2s", "sync_input";
1511 assigned-cloc 1561 assigned-clocks = <&tegra_car TEGRA210_CLK_I2S0>;
1512 assigned-cloc 1562 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
1513 assigned-cloc 1563 assigned-clock-rates = <1536000>;
1514 sound-name-pr 1564 sound-name-prefix = "I2S1";
1515 status = "dis 1565 status = "disabled";
1516 }; 1566 };
1517 1567
1518 tegra_i2s2: i2s@702d1 1568 tegra_i2s2: i2s@702d1100 {
1519 compatible = 1569 compatible = "nvidia,tegra210-i2s";
1520 reg = <0x702d 1570 reg = <0x702d1100 0x100>;
1521 clocks = <&te 1571 clocks = <&tegra_car TEGRA210_CLK_I2S1>,
1522 <&te 1572 <&tegra_car TEGRA210_CLK_I2S1_SYNC>;
1523 clock-names = 1573 clock-names = "i2s", "sync_input";
1524 assigned-cloc 1574 assigned-clocks = <&tegra_car TEGRA210_CLK_I2S1>;
1525 assigned-cloc 1575 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
1526 assigned-cloc 1576 assigned-clock-rates = <1536000>;
1527 sound-name-pr 1577 sound-name-prefix = "I2S2";
1528 status = "dis 1578 status = "disabled";
1529 }; 1579 };
1530 1580
1531 tegra_i2s3: i2s@702d1 1581 tegra_i2s3: i2s@702d1200 {
1532 compatible = 1582 compatible = "nvidia,tegra210-i2s";
1533 reg = <0x702d 1583 reg = <0x702d1200 0x100>;
1534 clocks = <&te 1584 clocks = <&tegra_car TEGRA210_CLK_I2S2>,
1535 <&te 1585 <&tegra_car TEGRA210_CLK_I2S2_SYNC>;
1536 clock-names = 1586 clock-names = "i2s", "sync_input";
1537 assigned-cloc 1587 assigned-clocks = <&tegra_car TEGRA210_CLK_I2S2>;
1538 assigned-cloc 1588 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
1539 assigned-cloc 1589 assigned-clock-rates = <1536000>;
1540 sound-name-pr 1590 sound-name-prefix = "I2S3";
1541 status = "dis 1591 status = "disabled";
1542 }; 1592 };
1543 1593
1544 tegra_i2s4: i2s@702d1 1594 tegra_i2s4: i2s@702d1300 {
1545 compatible = 1595 compatible = "nvidia,tegra210-i2s";
1546 reg = <0x702d 1596 reg = <0x702d1300 0x100>;
1547 clocks = <&te 1597 clocks = <&tegra_car TEGRA210_CLK_I2S3>,
1548 <&te 1598 <&tegra_car TEGRA210_CLK_I2S3_SYNC>;
1549 clock-names = 1599 clock-names = "i2s", "sync_input";
1550 assigned-cloc 1600 assigned-clocks = <&tegra_car TEGRA210_CLK_I2S3>;
1551 assigned-cloc 1601 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
1552 assigned-cloc 1602 assigned-clock-rates = <1536000>;
1553 sound-name-pr 1603 sound-name-prefix = "I2S4";
1554 status = "dis 1604 status = "disabled";
1555 }; 1605 };
1556 1606
1557 tegra_i2s5: i2s@702d1 1607 tegra_i2s5: i2s@702d1400 {
1558 compatible = 1608 compatible = "nvidia,tegra210-i2s";
1559 reg = <0x702d 1609 reg = <0x702d1400 0x100>;
1560 clocks = <&te 1610 clocks = <&tegra_car TEGRA210_CLK_I2S4>,
1561 <&te 1611 <&tegra_car TEGRA210_CLK_I2S4_SYNC>;
1562 clock-names = 1612 clock-names = "i2s", "sync_input";
1563 assigned-cloc 1613 assigned-clocks = <&tegra_car TEGRA210_CLK_I2S4>;
1564 assigned-cloc 1614 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
1565 assigned-cloc 1615 assigned-clock-rates = <1536000>;
1566 sound-name-pr 1616 sound-name-prefix = "I2S5";
1567 status = "dis 1617 status = "disabled";
1568 }; 1618 };
1569 1619
1570 tegra_sfc1: sfc@702d2 <<
1571 compatible = <<
1572 reg = <0x702d <<
1573 sound-name-pr <<
1574 status = "dis <<
1575 }; <<
1576 <<
1577 tegra_sfc2: sfc@702d2 <<
1578 compatible = <<
1579 reg = <0x702d <<
1580 sound-name-pr <<
1581 status = "dis <<
1582 }; <<
1583 <<
1584 tegra_sfc3: sfc@702d2 <<
1585 compatible = <<
1586 reg = <0x702d <<
1587 sound-name-pr <<
1588 status = "dis <<
1589 }; <<
1590 <<
1591 tegra_sfc4: sfc@702d2 <<
1592 compatible = <<
1593 reg = <0x702d <<
1594 sound-name-pr <<
1595 status = "dis <<
1596 }; <<
1597 <<
1598 tegra_amx1: amx@702d3 <<
1599 compatible = <<
1600 reg = <0x702d <<
1601 sound-name-pr <<
1602 status = "dis <<
1603 }; <<
1604 <<
1605 tegra_amx2: amx@702d3 <<
1606 compatible = <<
1607 reg = <0x702d <<
1608 sound-name-pr <<
1609 status = "dis <<
1610 }; <<
1611 <<
1612 tegra_adx1: adx@702d3 <<
1613 compatible = <<
1614 reg = <0x702d <<
1615 sound-name-pr <<
1616 status = "dis <<
1617 }; <<
1618 <<
1619 tegra_adx2: adx@702d3 <<
1620 compatible = <<
1621 reg = <0x702d <<
1622 sound-name-pr <<
1623 status = "dis <<
1624 }; <<
1625 <<
1626 tegra_dmic1: dmic@702 1620 tegra_dmic1: dmic@702d4000 {
1627 compatible = 1621 compatible = "nvidia,tegra210-dmic";
1628 reg = <0x702d 1622 reg = <0x702d4000 0x100>;
1629 clocks = <&te 1623 clocks = <&tegra_car TEGRA210_CLK_DMIC1>;
1630 clock-names = 1624 clock-names = "dmic";
1631 assigned-cloc 1625 assigned-clocks = <&tegra_car TEGRA210_CLK_DMIC1>;
1632 assigned-cloc 1626 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
1633 assigned-cloc 1627 assigned-clock-rates = <3072000>;
1634 sound-name-pr 1628 sound-name-prefix = "DMIC1";
1635 status = "dis 1629 status = "disabled";
1636 }; 1630 };
1637 1631
1638 tegra_dmic2: dmic@702 1632 tegra_dmic2: dmic@702d4100 {
1639 compatible = 1633 compatible = "nvidia,tegra210-dmic";
1640 reg = <0x702d 1634 reg = <0x702d4100 0x100>;
1641 clocks = <&te 1635 clocks = <&tegra_car TEGRA210_CLK_DMIC2>;
1642 clock-names = 1636 clock-names = "dmic";
1643 assigned-cloc 1637 assigned-clocks = <&tegra_car TEGRA210_CLK_DMIC2>;
1644 assigned-cloc 1638 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
1645 assigned-cloc 1639 assigned-clock-rates = <3072000>;
1646 sound-name-pr 1640 sound-name-prefix = "DMIC2";
1647 status = "dis 1641 status = "disabled";
1648 }; 1642 };
1649 1643
1650 tegra_dmic3: dmic@702 1644 tegra_dmic3: dmic@702d4200 {
1651 compatible = 1645 compatible = "nvidia,tegra210-dmic";
1652 reg = <0x702d 1646 reg = <0x702d4200 0x100>;
1653 clocks = <&te 1647 clocks = <&tegra_car TEGRA210_CLK_DMIC3>;
1654 clock-names = 1648 clock-names = "dmic";
1655 assigned-cloc 1649 assigned-clocks = <&tegra_car TEGRA210_CLK_DMIC3>;
1656 assigned-cloc 1650 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
1657 assigned-cloc 1651 assigned-clock-rates = <3072000>;
1658 sound-name-pr 1652 sound-name-prefix = "DMIC3";
1659 status = "dis 1653 status = "disabled";
1660 }; 1654 };
1661 1655
1662 tegra_ope1: processin !! 1656 tegra_sfc1: sfc@702d2000 {
1663 compatible = !! 1657 compatible = "nvidia,tegra210-sfc";
1664 reg = <0x702d !! 1658 reg = <0x702d2000 0x200>;
1665 #address-cell !! 1659 sound-name-prefix = "SFC1";
1666 #size-cells = <<
1667 ranges; <<
1668 sound-name-pr <<
1669 status = "dis 1660 status = "disabled";
1670 <<
1671 equalizer@702 <<
1672 compa <<
1673 reg = <<
1674 }; <<
1675 <<
1676 dynamic-range <<
1677 compa <<
1678 reg = <<
1679 }; <<
1680 }; 1661 };
1681 1662
1682 tegra_ope2: processin !! 1663 tegra_sfc2: sfc@702d2200 {
1683 compatible = !! 1664 compatible = "nvidia,tegra210-sfc";
1684 reg = <0x702d !! 1665 reg = <0x702d2200 0x200>;
1685 #address-cell !! 1666 sound-name-prefix = "SFC2";
1686 #size-cells = <<
1687 ranges; <<
1688 sound-name-pr <<
1689 status = "dis 1667 status = "disabled";
>> 1668 };
1690 1669
1691 equalizer@702 !! 1670 tegra_sfc3: sfc@702d2400 {
1692 compa !! 1671 compatible = "nvidia,tegra210-sfc";
1693 reg = !! 1672 reg = <0x702d2400 0x200>;
1694 }; !! 1673 sound-name-prefix = "SFC3";
>> 1674 status = "disabled";
>> 1675 };
1695 1676
1696 dynamic-range !! 1677 tegra_sfc4: sfc@702d2600 {
1697 compa !! 1678 compatible = "nvidia,tegra210-sfc";
1698 reg = !! 1679 reg = <0x702d2600 0x200>;
1699 }; !! 1680 sound-name-prefix = "SFC4";
>> 1681 status = "disabled";
1700 }; 1682 };
1701 1683
1702 tegra_mvc1: mvc@702da 1684 tegra_mvc1: mvc@702da000 {
1703 compatible = 1685 compatible = "nvidia,tegra210-mvc";
1704 reg = <0x702d 1686 reg = <0x702da000 0x200>;
1705 sound-name-pr 1687 sound-name-prefix = "MVC1";
1706 status = "dis 1688 status = "disabled";
1707 }; 1689 };
1708 1690
1709 tegra_mvc2: mvc@702da 1691 tegra_mvc2: mvc@702da200 {
1710 compatible = 1692 compatible = "nvidia,tegra210-mvc";
1711 reg = <0x702d 1693 reg = <0x702da200 0x200>;
1712 sound-name-pr 1694 sound-name-prefix = "MVC2";
1713 status = "dis 1695 status = "disabled";
1714 }; 1696 };
1715 1697
>> 1698 tegra_amx1: amx@702d3000 {
>> 1699 compatible = "nvidia,tegra210-amx";
>> 1700 reg = <0x702d3000 0x100>;
>> 1701 sound-name-prefix = "AMX1";
>> 1702 status = "disabled";
>> 1703 };
>> 1704
>> 1705 tegra_amx2: amx@702d3100 {
>> 1706 compatible = "nvidia,tegra210-amx";
>> 1707 reg = <0x702d3100 0x100>;
>> 1708 sound-name-prefix = "AMX2";
>> 1709 status = "disabled";
>> 1710 };
>> 1711
>> 1712 tegra_adx1: adx@702d3800 {
>> 1713 compatible = "nvidia,tegra210-adx";
>> 1714 reg = <0x702d3800 0x100>;
>> 1715 sound-name-prefix = "ADX1";
>> 1716 status = "disabled";
>> 1717 };
>> 1718
>> 1719 tegra_adx2: adx@702d3900 {
>> 1720 compatible = "nvidia,tegra210-adx";
>> 1721 reg = <0x702d3900 0x100>;
>> 1722 sound-name-prefix = "ADX2";
>> 1723 status = "disabled";
>> 1724 };
>> 1725
1716 tegra_amixer: amixer@ 1726 tegra_amixer: amixer@702dbb00 {
1717 compatible = 1727 compatible = "nvidia,tegra210-amixer";
1718 reg = <0x702d 1728 reg = <0x702dbb00 0x800>;
1719 sound-name-pr 1729 sound-name-prefix = "MIXER1";
1720 status = "dis 1730 status = "disabled";
1721 }; 1731 };
1722 1732
1723 ports { 1733 ports {
1724 #address-cell 1734 #address-cells = <1>;
1725 #size-cells = 1735 #size-cells = <0>;
1726 1736
1727 port@0 { 1737 port@0 {
1728 reg = 1738 reg = <0x0>;
1729 1739
1730 xbar_ 1740 xbar_admaif1_ep: endpoint {
1731 1741 remote-endpoint = <&admaif1_ep>;
1732 }; 1742 };
1733 }; 1743 };
1734 1744
1735 port@1 { 1745 port@1 {
1736 reg = 1746 reg = <0x1>;
1737 1747
1738 xbar_ 1748 xbar_admaif2_ep: endpoint {
1739 1749 remote-endpoint = <&admaif2_ep>;
1740 }; 1750 };
1741 }; 1751 };
1742 1752
1743 port@2 { 1753 port@2 {
1744 reg = 1754 reg = <0x2>;
1745 1755
1746 xbar_ 1756 xbar_admaif3_ep: endpoint {
1747 1757 remote-endpoint = <&admaif3_ep>;
1748 }; 1758 };
1749 }; 1759 };
1750 1760
1751 port@3 { 1761 port@3 {
1752 reg = 1762 reg = <0x3>;
1753 1763
1754 xbar_ 1764 xbar_admaif4_ep: endpoint {
1755 1765 remote-endpoint = <&admaif4_ep>;
1756 }; 1766 };
1757 }; 1767 };
1758 1768
1759 port@4 { 1769 port@4 {
1760 reg = 1770 reg = <0x4>;
1761 xbar_ 1771 xbar_admaif5_ep: endpoint {
1762 1772 remote-endpoint = <&admaif5_ep>;
1763 }; 1773 };
1764 }; 1774 };
1765 port@5 { 1775 port@5 {
1766 reg = 1776 reg = <0x5>;
1767 1777
1768 xbar_ 1778 xbar_admaif6_ep: endpoint {
1769 1779 remote-endpoint = <&admaif6_ep>;
1770 }; 1780 };
1771 }; 1781 };
1772 1782
1773 port@6 { 1783 port@6 {
1774 reg = 1784 reg = <0x6>;
1775 1785
1776 xbar_ 1786 xbar_admaif7_ep: endpoint {
1777 1787 remote-endpoint = <&admaif7_ep>;
1778 }; 1788 };
1779 }; 1789 };
1780 1790
1781 port@7 { 1791 port@7 {
1782 reg = 1792 reg = <0x7>;
1783 1793
1784 xbar_ 1794 xbar_admaif8_ep: endpoint {
1785 1795 remote-endpoint = <&admaif8_ep>;
1786 }; 1796 };
1787 }; 1797 };
1788 1798
1789 port@8 { 1799 port@8 {
1790 reg = 1800 reg = <0x8>;
1791 1801
1792 xbar_ 1802 xbar_admaif9_ep: endpoint {
1793 1803 remote-endpoint = <&admaif9_ep>;
1794 }; 1804 };
1795 }; 1805 };
1796 1806
1797 port@9 { 1807 port@9 {
1798 reg = 1808 reg = <0x9>;
1799 1809
1800 xbar_ 1810 xbar_admaif10_ep: endpoint {
1801 1811 remote-endpoint = <&admaif10_ep>;
1802 }; 1812 };
1803 }; 1813 };
1804 }; 1814 };
1805 }; 1815 };
1806 <<
1807 adma: dma-controller@702e2000 <<
1808 compatible = "nvidia, <<
1809 reg = <0x702e2000 0x2 <<
1810 interrupt-parent = <& <<
1811 interrupts = <GIC_SPI <<
1812 <GIC_SPI <<
1813 <GIC_SPI <<
1814 <GIC_SPI <<
1815 <GIC_SPI <<
1816 <GIC_SPI <<
1817 <GIC_SPI <<
1818 <GIC_SPI <<
1819 <GIC_SPI <<
1820 <GIC_SPI <<
1821 <GIC_SPI <<
1822 <GIC_SPI <<
1823 <GIC_SPI <<
1824 <GIC_SPI <<
1825 <GIC_SPI <<
1826 <GIC_SPI <<
1827 <GIC_SPI <<
1828 <GIC_SPI <<
1829 <GIC_SPI <<
1830 <GIC_SPI <<
1831 <GIC_SPI <<
1832 <GIC_SPI <<
1833 #dma-cells = <1>; <<
1834 clocks = <&tegra_car <<
1835 clock-names = "d_audi <<
1836 status = "disabled"; <<
1837 }; <<
1838 <<
1839 agic: interrupt-controller@70 <<
1840 compatible = "nvidia, <<
1841 #interrupt-cells = <3 <<
1842 interrupt-controller; <<
1843 reg = <0x702f9000 0x1 <<
1844 <0x702fa000 0x2 <<
1845 interrupts = <GIC_SPI <<
1846 clocks = <&tegra_car <<
1847 clock-names = "clk"; <<
1848 status = "disabled"; <<
1849 }; <<
1850 }; 1816 };
1851 1817
1852 spi@70410000 { 1818 spi@70410000 {
1853 compatible = "nvidia,tegra210 1819 compatible = "nvidia,tegra210-qspi";
1854 reg = <0x0 0x70410000 0x0 0x1 1820 reg = <0x0 0x70410000 0x0 0x1000>;
1855 interrupts = <GIC_SPI 10 IRQ_ 1821 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1856 #address-cells = <1>; 1822 #address-cells = <1>;
1857 #size-cells = <0>; 1823 #size-cells = <0>;
1858 clocks = <&tegra_car TEGRA210 1824 clocks = <&tegra_car TEGRA210_CLK_QSPI>,
1859 <&tegra_car TEGRA210 1825 <&tegra_car TEGRA210_CLK_QSPI_PM>;
1860 clock-names = "qspi", "qspi_o 1826 clock-names = "qspi", "qspi_out";
1861 resets = <&tegra_car 211>; 1827 resets = <&tegra_car 211>;
>> 1828 reset-names = "qspi";
1862 dmas = <&apbdma 5>, <&apbdma 1829 dmas = <&apbdma 5>, <&apbdma 5>;
1863 dma-names = "rx", "tx"; 1830 dma-names = "rx", "tx";
1864 status = "disabled"; 1831 status = "disabled";
1865 }; 1832 };
1866 1833
1867 usb@7d000000 { 1834 usb@7d000000 {
1868 compatible = "nvidia,tegra210 1835 compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci";
1869 reg = <0x0 0x7d000000 0x0 0x4 1836 reg = <0x0 0x7d000000 0x0 0x4000>;
1870 interrupts = <GIC_SPI 20 IRQ_ 1837 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1871 phy_type = "utmi"; 1838 phy_type = "utmi";
1872 clocks = <&tegra_car TEGRA210 1839 clocks = <&tegra_car TEGRA210_CLK_USBD>;
1873 clock-names = "usb"; 1840 clock-names = "usb";
1874 resets = <&tegra_car 22>; 1841 resets = <&tegra_car 22>;
1875 reset-names = "usb"; 1842 reset-names = "usb";
1876 nvidia,phy = <&phy1>; 1843 nvidia,phy = <&phy1>;
1877 status = "disabled"; 1844 status = "disabled";
1878 }; 1845 };
1879 1846
1880 phy1: usb-phy@7d000000 { 1847 phy1: usb-phy@7d000000 {
1881 compatible = "nvidia,tegra210 1848 compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy";
1882 reg = <0x0 0x7d000000 0x0 0x4 1849 reg = <0x0 0x7d000000 0x0 0x4000>,
1883 <0x0 0x7d000000 0x0 0x4 1850 <0x0 0x7d000000 0x0 0x4000>;
1884 phy_type = "utmi"; 1851 phy_type = "utmi";
1885 clocks = <&tegra_car TEGRA210 1852 clocks = <&tegra_car TEGRA210_CLK_USBD>,
1886 <&tegra_car TEGRA210 1853 <&tegra_car TEGRA210_CLK_PLL_U>,
1887 <&tegra_car TEGRA210 1854 <&tegra_car TEGRA210_CLK_USBD>;
1888 clock-names = "reg", "pll_u", 1855 clock-names = "reg", "pll_u", "utmi-pads";
1889 resets = <&tegra_car 22>, <&t 1856 resets = <&tegra_car 22>, <&tegra_car 22>;
1890 reset-names = "usb", "utmi-pa 1857 reset-names = "usb", "utmi-pads";
1891 nvidia,hssync-start-delay = < 1858 nvidia,hssync-start-delay = <0>;
1892 nvidia,idle-wait-delay = <17> 1859 nvidia,idle-wait-delay = <17>;
1893 nvidia,elastic-limit = <16>; 1860 nvidia,elastic-limit = <16>;
1894 nvidia,term-range-adj = <6>; 1861 nvidia,term-range-adj = <6>;
1895 nvidia,xcvr-setup = <9>; 1862 nvidia,xcvr-setup = <9>;
1896 nvidia,xcvr-lsfslew = <0>; 1863 nvidia,xcvr-lsfslew = <0>;
1897 nvidia,xcvr-lsrslew = <3>; 1864 nvidia,xcvr-lsrslew = <3>;
1898 nvidia,hssquelch-level = <2>; 1865 nvidia,hssquelch-level = <2>;
1899 nvidia,hsdiscon-level = <5>; 1866 nvidia,hsdiscon-level = <5>;
1900 nvidia,xcvr-hsslew = <12>; 1867 nvidia,xcvr-hsslew = <12>;
1901 nvidia,has-utmi-pad-registers 1868 nvidia,has-utmi-pad-registers;
1902 status = "disabled"; 1869 status = "disabled";
1903 }; 1870 };
1904 1871
1905 usb@7d004000 { 1872 usb@7d004000 {
1906 compatible = "nvidia,tegra210 1873 compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci";
1907 reg = <0x0 0x7d004000 0x0 0x4 1874 reg = <0x0 0x7d004000 0x0 0x4000>;
1908 interrupts = <GIC_SPI 21 IRQ_ 1875 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
1909 phy_type = "utmi"; 1876 phy_type = "utmi";
1910 clocks = <&tegra_car TEGRA210 1877 clocks = <&tegra_car TEGRA210_CLK_USB2>;
1911 clock-names = "usb"; 1878 clock-names = "usb";
1912 resets = <&tegra_car 58>; 1879 resets = <&tegra_car 58>;
1913 reset-names = "usb"; 1880 reset-names = "usb";
1914 nvidia,phy = <&phy2>; 1881 nvidia,phy = <&phy2>;
1915 status = "disabled"; 1882 status = "disabled";
1916 }; 1883 };
1917 1884
1918 phy2: usb-phy@7d004000 { 1885 phy2: usb-phy@7d004000 {
1919 compatible = "nvidia,tegra210 1886 compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy";
1920 reg = <0x0 0x7d004000 0x0 0x4 1887 reg = <0x0 0x7d004000 0x0 0x4000>,
1921 <0x0 0x7d000000 0x0 0x4 1888 <0x0 0x7d000000 0x0 0x4000>;
1922 phy_type = "utmi"; 1889 phy_type = "utmi";
1923 clocks = <&tegra_car TEGRA210 1890 clocks = <&tegra_car TEGRA210_CLK_USB2>,
1924 <&tegra_car TEGRA210 1891 <&tegra_car TEGRA210_CLK_PLL_U>,
1925 <&tegra_car TEGRA210 1892 <&tegra_car TEGRA210_CLK_USBD>;
1926 clock-names = "reg", "pll_u", 1893 clock-names = "reg", "pll_u", "utmi-pads";
1927 resets = <&tegra_car 58>, <&t 1894 resets = <&tegra_car 58>, <&tegra_car 22>;
1928 reset-names = "usb", "utmi-pa 1895 reset-names = "usb", "utmi-pads";
1929 nvidia,hssync-start-delay = < 1896 nvidia,hssync-start-delay = <0>;
1930 nvidia,idle-wait-delay = <17> 1897 nvidia,idle-wait-delay = <17>;
1931 nvidia,elastic-limit = <16>; 1898 nvidia,elastic-limit = <16>;
1932 nvidia,term-range-adj = <6>; 1899 nvidia,term-range-adj = <6>;
1933 nvidia,xcvr-setup = <9>; 1900 nvidia,xcvr-setup = <9>;
1934 nvidia,xcvr-lsfslew = <0>; 1901 nvidia,xcvr-lsfslew = <0>;
1935 nvidia,xcvr-lsrslew = <3>; 1902 nvidia,xcvr-lsrslew = <3>;
1936 nvidia,hssquelch-level = <2>; 1903 nvidia,hssquelch-level = <2>;
1937 nvidia,hsdiscon-level = <5>; 1904 nvidia,hsdiscon-level = <5>;
1938 nvidia,xcvr-hsslew = <12>; 1905 nvidia,xcvr-hsslew = <12>;
1939 status = "disabled"; 1906 status = "disabled";
1940 }; 1907 };
1941 1908
1942 cpus { 1909 cpus {
1943 #address-cells = <1>; 1910 #address-cells = <1>;
1944 #size-cells = <0>; 1911 #size-cells = <0>;
1945 1912
1946 cpu@0 { 1913 cpu@0 {
1947 device_type = "cpu"; 1914 device_type = "cpu";
1948 compatible = "arm,cor 1915 compatible = "arm,cortex-a57";
1949 reg = <0>; 1916 reg = <0>;
1950 clocks = <&tegra_car 1917 clocks = <&tegra_car TEGRA210_CLK_CCLK_G>,
1951 <&tegra_car 1918 <&tegra_car TEGRA210_CLK_PLL_X>,
1952 <&tegra_car 1919 <&tegra_car TEGRA210_CLK_PLL_P_OUT4>,
1953 <&dfll>; 1920 <&dfll>;
1954 clock-names = "cpu_g" 1921 clock-names = "cpu_g", "pll_x", "pll_p", "dfll";
1955 clock-latency = <3000 1922 clock-latency = <300000>;
1956 cpu-idle-states = <&C 1923 cpu-idle-states = <&CPU_SLEEP>;
1957 next-level-cache = <& 1924 next-level-cache = <&L2>;
1958 }; 1925 };
1959 1926
1960 cpu@1 { 1927 cpu@1 {
1961 device_type = "cpu"; 1928 device_type = "cpu";
1962 compatible = "arm,cor 1929 compatible = "arm,cortex-a57";
1963 reg = <1>; 1930 reg = <1>;
1964 cpu-idle-states = <&C 1931 cpu-idle-states = <&CPU_SLEEP>;
1965 next-level-cache = <& 1932 next-level-cache = <&L2>;
1966 }; 1933 };
1967 1934
1968 cpu@2 { 1935 cpu@2 {
1969 device_type = "cpu"; 1936 device_type = "cpu";
1970 compatible = "arm,cor 1937 compatible = "arm,cortex-a57";
1971 reg = <2>; 1938 reg = <2>;
1972 cpu-idle-states = <&C 1939 cpu-idle-states = <&CPU_SLEEP>;
1973 next-level-cache = <& 1940 next-level-cache = <&L2>;
1974 }; 1941 };
1975 1942
1976 cpu@3 { 1943 cpu@3 {
1977 device_type = "cpu"; 1944 device_type = "cpu";
1978 compatible = "arm,cor 1945 compatible = "arm,cortex-a57";
1979 reg = <3>; 1946 reg = <3>;
1980 cpu-idle-states = <&C 1947 cpu-idle-states = <&CPU_SLEEP>;
1981 next-level-cache = <& 1948 next-level-cache = <&L2>;
1982 }; 1949 };
1983 1950
1984 idle-states { 1951 idle-states {
1985 entry-method = "psci" 1952 entry-method = "psci";
1986 1953
1987 CPU_SLEEP: cpu-sleep 1954 CPU_SLEEP: cpu-sleep {
1988 compatible = 1955 compatible = "arm,idle-state";
1989 arm,psci-susp 1956 arm,psci-suspend-param = <0x40000007>;
1990 entry-latency 1957 entry-latency-us = <100>;
1991 exit-latency- 1958 exit-latency-us = <30>;
1992 min-residency 1959 min-residency-us = <1000>;
1993 wakeup-latenc 1960 wakeup-latency-us = <130>;
1994 idle-state-na 1961 idle-state-name = "cpu-sleep";
1995 status = "dis 1962 status = "disabled";
1996 }; 1963 };
1997 }; 1964 };
1998 1965
1999 L2: l2-cache { 1966 L2: l2-cache {
2000 compatible = "cache"; 1967 compatible = "cache";
2001 cache-level = <2>; <<
2002 cache-unified; <<
2003 }; 1968 };
2004 }; 1969 };
2005 1970
2006 pmu { 1971 pmu {
2007 compatible = "arm,cortex-a57- !! 1972 compatible = "arm,armv8-pmuv3";
2008 interrupts = <GIC_SPI 144 IRQ 1973 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
2009 <GIC_SPI 145 IRQ 1974 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
2010 <GIC_SPI 146 IRQ 1975 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
2011 <GIC_SPI 147 IRQ 1976 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
2012 interrupt-affinity = <&{/cpus 1977 interrupt-affinity = <&{/cpus/cpu@0} &{/cpus/cpu@1}
2013 &{/cpus 1978 &{/cpus/cpu@2} &{/cpus/cpu@3}>;
2014 }; 1979 };
2015 1980
2016 sound { 1981 sound {
2017 status = "disabled"; 1982 status = "disabled";
2018 1983
2019 clocks = <&tegra_car TEGRA210 1984 clocks = <&tegra_car TEGRA210_CLK_PLL_A>,
2020 <&tegra_car TEGRA210 1985 <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
2021 clock-names = "pll_a", "plla_ 1986 clock-names = "pll_a", "plla_out0";
2022 1987
2023 assigned-clocks = <&tegra_car 1988 assigned-clocks = <&tegra_car TEGRA210_CLK_PLL_A>,
2024 <&tegra_car 1989 <&tegra_car TEGRA210_CLK_PLL_A_OUT0>,
2025 <&tegra_car 1990 <&tegra_car TEGRA210_CLK_EXTERN1>;
2026 assigned-clock-parents = <0>, 1991 assigned-clock-parents = <0>, <0>, <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
2027 assigned-clock-rates = <36864 1992 assigned-clock-rates = <368640000>, <49152000>, <12288000>;
2028 }; 1993 };
2029 1994
2030 thermal-zones { 1995 thermal-zones {
2031 cpu-thermal { 1996 cpu-thermal {
2032 polling-delay-passive 1997 polling-delay-passive = <1000>;
2033 polling-delay = <0>; 1998 polling-delay = <0>;
2034 1999
2035 thermal-sensors = 2000 thermal-sensors =
2036 <&soctherm TE 2001 <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>;
2037 2002
2038 trips { 2003 trips {
2039 cpu-shutdown- 2004 cpu-shutdown-trip {
2040 tempe 2005 temperature = <102500>;
2041 hyste 2006 hysteresis = <0>;
2042 type 2007 type = "critical";
2043 }; 2008 };
2044 2009
2045 cpu_throttle_ 2010 cpu_throttle_trip: throttle-trip {
2046 tempe 2011 temperature = <98500>;
2047 hyste 2012 hysteresis = <1000>;
2048 type 2013 type = "hot";
2049 }; 2014 };
2050 }; 2015 };
2051 2016
2052 cooling-maps { 2017 cooling-maps {
2053 map0 { 2018 map0 {
2054 trip 2019 trip = <&cpu_throttle_trip>;
2055 cooli 2020 cooling-device = <&throttle_heavy 1 1>;
2056 }; 2021 };
2057 }; 2022 };
2058 }; 2023 };
2059 2024
2060 mem-thermal { 2025 mem-thermal {
2061 polling-delay-passive 2026 polling-delay-passive = <0>;
2062 polling-delay = <0>; 2027 polling-delay = <0>;
2063 2028
2064 thermal-sensors = 2029 thermal-sensors =
2065 <&soctherm TE 2030 <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>;
2066 2031
2067 trips { 2032 trips {
2068 dram_nominal: 2033 dram_nominal: mem-nominal-trip {
2069 tempe 2034 temperature = <50000>;
2070 hyste 2035 hysteresis = <1000>;
2071 type 2036 type = "passive";
2072 }; 2037 };
2073 2038
2074 dram_throttle 2039 dram_throttle: mem-throttle-trip {
2075 tempe 2040 temperature = <70000>;
2076 hyste 2041 hysteresis = <1000>;
2077 type 2042 type = "active";
2078 }; 2043 };
2079 2044
2080 mem-hot-trip 2045 mem-hot-trip {
2081 tempe 2046 temperature = <100000>;
2082 hyste 2047 hysteresis = <1000>;
2083 type 2048 type = "hot";
2084 }; 2049 };
2085 2050
2086 mem-shutdown- 2051 mem-shutdown-trip {
2087 tempe 2052 temperature = <103000>;
2088 hyste 2053 hysteresis = <0>;
2089 type 2054 type = "critical";
2090 }; 2055 };
2091 }; 2056 };
2092 2057
2093 cooling-maps { 2058 cooling-maps {
2094 dram-passive 2059 dram-passive {
2095 cooli 2060 cooling-device = <&emc 0 0>;
2096 trip 2061 trip = <&dram_nominal>;
2097 }; 2062 };
2098 2063
2099 dram-active { 2064 dram-active {
2100 cooli 2065 cooling-device = <&emc 1 1>;
2101 trip 2066 trip = <&dram_throttle>;
2102 }; 2067 };
2103 }; 2068 };
2104 }; 2069 };
2105 2070
2106 gpu-thermal { 2071 gpu-thermal {
2107 polling-delay-passive 2072 polling-delay-passive = <1000>;
2108 polling-delay = <0>; 2073 polling-delay = <0>;
2109 2074
2110 thermal-sensors = 2075 thermal-sensors =
2111 <&soctherm TE 2076 <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>;
2112 2077
2113 trips { 2078 trips {
2114 gpu-shutdown- 2079 gpu-shutdown-trip {
2115 tempe 2080 temperature = <103000>;
2116 hyste 2081 hysteresis = <0>;
2117 type 2082 type = "critical";
2118 }; 2083 };
2119 2084
2120 gpu_throttle_ 2085 gpu_throttle_trip: throttle-trip {
2121 tempe 2086 temperature = <100000>;
2122 hyste 2087 hysteresis = <1000>;
2123 type 2088 type = "hot";
2124 }; 2089 };
2125 }; 2090 };
2126 2091
2127 cooling-maps { 2092 cooling-maps {
2128 map0 { 2093 map0 {
2129 trip 2094 trip = <&gpu_throttle_trip>;
2130 cooli 2095 cooling-device = <&throttle_heavy 1 1>;
2131 }; 2096 };
2132 }; 2097 };
2133 }; 2098 };
2134 2099
2135 pllx-thermal { 2100 pllx-thermal {
2136 polling-delay-passive 2101 polling-delay-passive = <0>;
2137 polling-delay = <0>; 2102 polling-delay = <0>;
2138 2103
2139 thermal-sensors = 2104 thermal-sensors =
2140 <&soctherm TE 2105 <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>;
2141 2106
2142 trips { 2107 trips {
2143 pllx-shutdown 2108 pllx-shutdown-trip {
2144 tempe 2109 temperature = <103000>;
2145 hyste 2110 hysteresis = <0>;
2146 type 2111 type = "critical";
2147 }; 2112 };
2148 2113
2149 pllx-throttle 2114 pllx-throttle-trip {
2150 tempe 2115 temperature = <100000>;
2151 hyste 2116 hysteresis = <1000>;
2152 type 2117 type = "hot";
2153 }; 2118 };
2154 }; 2119 };
2155 2120
2156 cooling-maps { 2121 cooling-maps {
2157 /* 2122 /*
2158 * There are 2123 * There are currently no cooling maps,
2159 * because th 2124 * because there are no cooling devices.
2160 */ 2125 */
2161 }; 2126 };
2162 }; 2127 };
2163 }; 2128 };
2164 2129
2165 timer { 2130 timer {
2166 compatible = "arm,armv8-timer 2131 compatible = "arm,armv8-timer";
2167 interrupts = <GIC_PPI 13 2132 interrupts = <GIC_PPI 13
2168 (GIC_CPU_MASK 2133 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2169 <GIC_PPI 14 2134 <GIC_PPI 14
2170 (GIC_CPU_MASK 2135 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2171 <GIC_PPI 11 2136 <GIC_PPI 11
2172 (GIC_CPU_MASK 2137 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2173 <GIC_PPI 10 2138 <GIC_PPI 10
2174 (GIC_CPU_MASK 2139 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
2175 interrupt-parent = <&gic>; 2140 interrupt-parent = <&gic>;
2176 arm,no-tick-in-suspend; 2141 arm,no-tick-in-suspend;
2177 }; 2142 };
2178 }; 2143 };
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.