1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra210-car.h> 2 #include <dt-bindings/clock/tegra210-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h> 3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra210-mc.h> 4 #include <dt-bindings/memory/tegra210-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h> 5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra-io 6 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
7 #include <dt-bindings/reset/tegra210-car.h> 7 #include <dt-bindings/reset/tegra210-car.h>
8 #include <dt-bindings/interrupt-controller/arm 8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/thermal/tegra124-socther 9 #include <dt-bindings/thermal/tegra124-soctherm.h>
10 #include <dt-bindings/soc/tegra-pmc.h> <<
11 10
12 / { 11 / {
13 compatible = "nvidia,tegra210"; 12 compatible = "nvidia,tegra210";
14 interrupt-parent = <&lic>; 13 interrupt-parent = <&lic>;
15 #address-cells = <2>; 14 #address-cells = <2>;
16 #size-cells = <2>; 15 #size-cells = <2>;
17 16
18 pcie@1003000 { 17 pcie@1003000 {
19 compatible = "nvidia,tegra210- 18 compatible = "nvidia,tegra210-pcie";
20 device_type = "pci"; 19 device_type = "pci";
21 reg = <0x0 0x01003000 0x0 0x00 !! 20 reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */
22 <0x0 0x01003800 0x0 0x00 !! 21 0x0 0x01003800 0x0 0x00000800 /* AFI registers */
23 <0x0 0x02000000 0x0 0x10 !! 22 0x0 0x02000000 0x0 0x10000000>; /* configuration space */
24 reg-names = "pads", "afi", "cs 23 reg-names = "pads", "afi", "cs";
25 interrupts = <GIC_SPI 98 IRQ_T 24 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
26 <GIC_SPI 99 IRQ_T 25 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
27 interrupt-names = "intr", "msi 26 interrupt-names = "intr", "msi";
28 27
29 #interrupt-cells = <1>; 28 #interrupt-cells = <1>;
30 interrupt-map-mask = <0 0 0 0> 29 interrupt-map-mask = <0 0 0 0>;
31 interrupt-map = <0 0 0 0 &gic 30 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
32 31
33 bus-range = <0x00 0xff>; 32 bus-range = <0x00 0xff>;
34 #address-cells = <3>; 33 #address-cells = <3>;
35 #size-cells = <2>; 34 #size-cells = <2>;
36 35
37 ranges = <0x02000000 0 0x01000 !! 36 ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000 /* port 0 configuration space */
38 <0x02000000 0 0x01001 !! 37 0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000 /* port 1 configuration space */
39 <0x01000000 0 0x0 !! 38 0x81000000 0 0x0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */
40 <0x02000000 0 0x13000 !! 39 0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */
41 <0x42000000 0 0x20000 !! 40 0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
42 41
43 clocks = <&tegra_car TEGRA210_ 42 clocks = <&tegra_car TEGRA210_CLK_PCIE>,
44 <&tegra_car TEGRA210_ 43 <&tegra_car TEGRA210_CLK_AFI>,
45 <&tegra_car TEGRA210_ 44 <&tegra_car TEGRA210_CLK_PLL_E>,
46 <&tegra_car TEGRA210_ 45 <&tegra_car TEGRA210_CLK_CML0>;
47 clock-names = "pex", "afi", "p 46 clock-names = "pex", "afi", "pll_e", "cml";
48 resets = <&tegra_car 70>, 47 resets = <&tegra_car 70>,
49 <&tegra_car 72>, 48 <&tegra_car 72>,
50 <&tegra_car 74>; 49 <&tegra_car 74>;
51 reset-names = "pex", "afi", "p 50 reset-names = "pex", "afi", "pcie_x";
52 51
53 pinctrl-names = "default", "id 52 pinctrl-names = "default", "idle";
54 pinctrl-0 = <&pex_dpd_disable> 53 pinctrl-0 = <&pex_dpd_disable>;
55 pinctrl-1 = <&pex_dpd_enable>; 54 pinctrl-1 = <&pex_dpd_enable>;
56 55
57 status = "disabled"; 56 status = "disabled";
58 57
59 pci@1,0 { 58 pci@1,0 {
60 device_type = "pci"; 59 device_type = "pci";
61 assigned-addresses = < 60 assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
62 reg = <0x000800 0 0 0 61 reg = <0x000800 0 0 0 0>;
63 bus-range = <0x00 0xff 62 bus-range = <0x00 0xff>;
64 status = "disabled"; 63 status = "disabled";
65 64
66 #address-cells = <3>; 65 #address-cells = <3>;
67 #size-cells = <2>; 66 #size-cells = <2>;
68 ranges; 67 ranges;
69 68
70 nvidia,num-lanes = <4> 69 nvidia,num-lanes = <4>;
71 }; 70 };
72 71
73 pci@2,0 { 72 pci@2,0 {
74 device_type = "pci"; 73 device_type = "pci";
75 assigned-addresses = < 74 assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
76 reg = <0x001000 0 0 0 75 reg = <0x001000 0 0 0 0>;
77 bus-range = <0x00 0xff 76 bus-range = <0x00 0xff>;
78 status = "disabled"; 77 status = "disabled";
79 78
80 #address-cells = <3>; 79 #address-cells = <3>;
81 #size-cells = <2>; 80 #size-cells = <2>;
82 ranges; 81 ranges;
83 82
84 nvidia,num-lanes = <1> 83 nvidia,num-lanes = <1>;
85 }; 84 };
86 }; 85 };
87 86
88 host1x@50000000 { 87 host1x@50000000 {
89 compatible = "nvidia,tegra210- !! 88 compatible = "nvidia,tegra210-host1x", "simple-bus";
90 reg = <0x0 0x50000000 0x0 0x00 89 reg = <0x0 0x50000000 0x0 0x00034000>;
91 interrupts = <GIC_SPI 65 IRQ_T 90 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
92 <GIC_SPI 67 IRQ_T 91 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
93 interrupt-names = "syncpt", "h <<
94 clocks = <&tegra_car TEGRA210_ 92 clocks = <&tegra_car TEGRA210_CLK_HOST1X>;
95 clock-names = "host1x"; 93 clock-names = "host1x";
96 resets = <&tegra_car 28>, <&mc !! 94 resets = <&tegra_car 28>;
97 reset-names = "host1x", "mc"; !! 95 reset-names = "host1x";
98 96
99 #address-cells = <2>; 97 #address-cells = <2>;
100 #size-cells = <2>; 98 #size-cells = <2>;
101 99
102 ranges = <0x0 0x54000000 0x0 0 100 ranges = <0x0 0x54000000 0x0 0x54000000 0x0 0x01000000>;
103 101
104 iommus = <&mc TEGRA_SWGROUP_HC 102 iommus = <&mc TEGRA_SWGROUP_HC>;
105 103
106 dpaux1: dpaux@54040000 { 104 dpaux1: dpaux@54040000 {
107 compatible = "nvidia,t 105 compatible = "nvidia,tegra210-dpaux";
108 reg = <0x0 0x54040000 106 reg = <0x0 0x54040000 0x0 0x00040000>;
109 interrupts = <GIC_SPI 107 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
110 clocks = <&tegra_car T 108 clocks = <&tegra_car TEGRA210_CLK_DPAUX1>,
111 <&tegra_car T 109 <&tegra_car TEGRA210_CLK_PLL_DP>;
112 clock-names = "dpaux", 110 clock-names = "dpaux", "parent";
113 resets = <&tegra_car 2 111 resets = <&tegra_car 207>;
114 reset-names = "dpaux"; 112 reset-names = "dpaux";
115 power-domains = <&pd_s 113 power-domains = <&pd_sor>;
116 status = "disabled"; 114 status = "disabled";
117 115
118 state_dpaux1_aux: pinm 116 state_dpaux1_aux: pinmux-aux {
119 groups = "dpau 117 groups = "dpaux-io";
120 function = "au 118 function = "aux";
121 }; 119 };
122 120
123 state_dpaux1_i2c: pinm 121 state_dpaux1_i2c: pinmux-i2c {
124 groups = "dpau 122 groups = "dpaux-io";
125 function = "i2 123 function = "i2c";
126 }; 124 };
127 125
128 state_dpaux1_off: pinm 126 state_dpaux1_off: pinmux-off {
129 groups = "dpau 127 groups = "dpaux-io";
130 function = "of 128 function = "off";
131 }; 129 };
132 130
133 i2c-bus { 131 i2c-bus {
134 #address-cells 132 #address-cells = <1>;
135 #size-cells = 133 #size-cells = <0>;
136 }; 134 };
137 }; 135 };
138 136
139 vi@54080000 { 137 vi@54080000 {
140 compatible = "nvidia,t 138 compatible = "nvidia,tegra210-vi";
141 reg = <0x0 0x54080000 !! 139 reg = <0x0 0x54080000 0x0 0x00040000>;
142 interrupts = <GIC_SPI 140 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
143 status = "disabled"; 141 status = "disabled";
144 assigned-clocks = <&te <<
145 assigned-clock-parents <<
146 <<
147 clocks = <&tegra_car T <<
148 power-domains = <&pd_v <<
149 <<
150 #address-cells = <1>; <<
151 #size-cells = <1>; <<
152 <<
153 ranges = <0x0 0x0 0x54 <<
154 <<
155 csi@838 { <<
156 compatible = " <<
157 reg = <0x838 0 <<
158 status = "disa <<
159 assigned-clock <<
160 <<
161 <<
162 <<
163 assigned-clock <<
164 <<
165 <<
166 assigned-clock <<
167 <<
168 <<
169 <<
170 <<
171 clocks = <&teg <<
172 <&teg <<
173 <&teg <<
174 <&teg <<
175 <&teg <<
176 clock-names = <<
177 power-domains <<
178 }; <<
179 }; 142 };
180 143
181 tsec@54100000 { 144 tsec@54100000 {
182 compatible = "nvidia,t 145 compatible = "nvidia,tegra210-tsec";
183 reg = <0x0 0x54100000 146 reg = <0x0 0x54100000 0x0 0x00040000>;
184 interrupts = <GIC_SPI <<
185 clocks = <&tegra_car T <<
186 clock-names = "tsec"; <<
187 resets = <&tegra_car 8 <<
188 reset-names = "tsec"; <<
189 status = "disabled"; <<
190 }; 147 };
191 148
192 dc@54200000 { 149 dc@54200000 {
193 compatible = "nvidia,t 150 compatible = "nvidia,tegra210-dc";
194 reg = <0x0 0x54200000 151 reg = <0x0 0x54200000 0x0 0x00040000>;
195 interrupts = <GIC_SPI 152 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
196 clocks = <&tegra_car T !! 153 clocks = <&tegra_car TEGRA210_CLK_DISP1>,
197 clock-names = "dc"; !! 154 <&tegra_car TEGRA210_CLK_PLL_P>;
>> 155 clock-names = "dc", "parent";
198 resets = <&tegra_car 2 156 resets = <&tegra_car 27>;
199 reset-names = "dc"; 157 reset-names = "dc";
200 158
201 iommus = <&mc TEGRA_SW 159 iommus = <&mc TEGRA_SWGROUP_DC>;
202 160
203 nvidia,outputs = <&dsi <<
204 nvidia,head = <0>; 161 nvidia,head = <0>;
205 }; 162 };
206 163
207 dc@54240000 { 164 dc@54240000 {
208 compatible = "nvidia,t 165 compatible = "nvidia,tegra210-dc";
209 reg = <0x0 0x54240000 166 reg = <0x0 0x54240000 0x0 0x00040000>;
210 interrupts = <GIC_SPI 167 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
211 clocks = <&tegra_car T !! 168 clocks = <&tegra_car TEGRA210_CLK_DISP2>,
212 clock-names = "dc"; !! 169 <&tegra_car TEGRA210_CLK_PLL_P>;
>> 170 clock-names = "dc", "parent";
213 resets = <&tegra_car 2 171 resets = <&tegra_car 26>;
214 reset-names = "dc"; 172 reset-names = "dc";
215 173
216 iommus = <&mc TEGRA_SW 174 iommus = <&mc TEGRA_SWGROUP_DCB>;
217 175
218 nvidia,outputs = <&dsi <<
219 nvidia,head = <1>; 176 nvidia,head = <1>;
220 }; 177 };
221 178
222 dsia: dsi@54300000 { !! 179 dsi@54300000 {
223 compatible = "nvidia,t 180 compatible = "nvidia,tegra210-dsi";
224 reg = <0x0 0x54300000 181 reg = <0x0 0x54300000 0x0 0x00040000>;
225 clocks = <&tegra_car T 182 clocks = <&tegra_car TEGRA210_CLK_DSIA>,
226 <&tegra_car T 183 <&tegra_car TEGRA210_CLK_DSIALP>,
227 <&tegra_car T 184 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>;
228 clock-names = "dsi", " 185 clock-names = "dsi", "lp", "parent";
229 resets = <&tegra_car 4 186 resets = <&tegra_car 48>;
230 reset-names = "dsi"; 187 reset-names = "dsi";
231 power-domains = <&pd_s 188 power-domains = <&pd_sor>;
232 nvidia,mipi-calibrate 189 nvidia,mipi-calibrate = <&mipi 0x0c0>; /* DSIA & DSIB pads */
233 190
234 status = "disabled"; 191 status = "disabled";
235 192
236 #address-cells = <1>; 193 #address-cells = <1>;
237 #size-cells = <0>; 194 #size-cells = <0>;
238 }; 195 };
239 196
240 vic@54340000 { 197 vic@54340000 {
241 compatible = "nvidia,t 198 compatible = "nvidia,tegra210-vic";
242 reg = <0x0 0x54340000 199 reg = <0x0 0x54340000 0x0 0x00040000>;
243 interrupts = <GIC_SPI 200 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
244 clocks = <&tegra_car T 201 clocks = <&tegra_car TEGRA210_CLK_VIC03>;
245 clock-names = "vic"; 202 clock-names = "vic";
246 resets = <&tegra_car 1 203 resets = <&tegra_car 178>;
247 reset-names = "vic"; 204 reset-names = "vic";
248 205
249 iommus = <&mc TEGRA_SW 206 iommus = <&mc TEGRA_SWGROUP_VIC>;
250 power-domains = <&pd_v 207 power-domains = <&pd_vic>;
251 }; 208 };
252 209
253 nvjpg@54380000 { 210 nvjpg@54380000 {
254 compatible = "nvidia,t 211 compatible = "nvidia,tegra210-nvjpg";
255 reg = <0x0 0x54380000 212 reg = <0x0 0x54380000 0x0 0x00040000>;
256 status = "disabled"; 213 status = "disabled";
257 }; 214 };
258 215
259 dsib: dsi@54400000 { !! 216 dsi@54400000 {
260 compatible = "nvidia,t 217 compatible = "nvidia,tegra210-dsi";
261 reg = <0x0 0x54400000 218 reg = <0x0 0x54400000 0x0 0x00040000>;
262 clocks = <&tegra_car T 219 clocks = <&tegra_car TEGRA210_CLK_DSIB>,
263 <&tegra_car T 220 <&tegra_car TEGRA210_CLK_DSIBLP>,
264 <&tegra_car T 221 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>;
265 clock-names = "dsi", " 222 clock-names = "dsi", "lp", "parent";
266 resets = <&tegra_car 8 223 resets = <&tegra_car 82>;
267 reset-names = "dsi"; 224 reset-names = "dsi";
268 power-domains = <&pd_s 225 power-domains = <&pd_sor>;
269 nvidia,mipi-calibrate 226 nvidia,mipi-calibrate = <&mipi 0x300>; /* DSIC & DSID pads */
270 227
271 status = "disabled"; 228 status = "disabled";
272 229
273 #address-cells = <1>; 230 #address-cells = <1>;
274 #size-cells = <0>; 231 #size-cells = <0>;
275 }; 232 };
276 233
277 nvdec@54480000 { 234 nvdec@54480000 {
278 compatible = "nvidia,t 235 compatible = "nvidia,tegra210-nvdec";
279 reg = <0x0 0x54480000 236 reg = <0x0 0x54480000 0x0 0x00040000>;
280 status = "disabled"; 237 status = "disabled";
281 }; 238 };
282 239
283 nvenc@544c0000 { 240 nvenc@544c0000 {
284 compatible = "nvidia,t 241 compatible = "nvidia,tegra210-nvenc";
285 reg = <0x0 0x544c0000 242 reg = <0x0 0x544c0000 0x0 0x00040000>;
286 status = "disabled"; 243 status = "disabled";
287 }; 244 };
288 245
289 tsec@54500000 { 246 tsec@54500000 {
290 compatible = "nvidia,t 247 compatible = "nvidia,tegra210-tsec";
291 reg = <0x0 0x54500000 248 reg = <0x0 0x54500000 0x0 0x00040000>;
292 interrupts = <GIC_SPI <<
293 clocks = <&tegra_car T <<
294 clock-names = "tsec"; <<
295 resets = <&tegra_car 2 <<
296 reset-names = "tsec"; <<
297 status = "disabled"; 249 status = "disabled";
298 }; 250 };
299 251
300 sor0: sor@54540000 { !! 252 sor@54540000 {
301 compatible = "nvidia,t 253 compatible = "nvidia,tegra210-sor";
302 reg = <0x0 0x54540000 254 reg = <0x0 0x54540000 0x0 0x00040000>;
303 interrupts = <GIC_SPI 255 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
304 clocks = <&tegra_car T 256 clocks = <&tegra_car TEGRA210_CLK_SOR0>,
305 <&tegra_car T <<
306 <&tegra_car T 257 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>,
307 <&tegra_car T 258 <&tegra_car TEGRA210_CLK_PLL_DP>,
308 <&tegra_car T 259 <&tegra_car TEGRA210_CLK_SOR_SAFE>;
309 clock-names = "sor", " !! 260 clock-names = "sor", "parent", "dp", "safe";
310 resets = <&tegra_car 1 261 resets = <&tegra_car 182>;
311 reset-names = "sor"; 262 reset-names = "sor";
312 pinctrl-0 = <&state_dp 263 pinctrl-0 = <&state_dpaux_aux>;
313 pinctrl-1 = <&state_dp 264 pinctrl-1 = <&state_dpaux_i2c>;
314 pinctrl-2 = <&state_dp 265 pinctrl-2 = <&state_dpaux_off>;
315 pinctrl-names = "aux", 266 pinctrl-names = "aux", "i2c", "off";
316 power-domains = <&pd_s 267 power-domains = <&pd_sor>;
317 status = "disabled"; 268 status = "disabled";
318 }; 269 };
319 270
320 sor1: sor@54580000 { !! 271 sor@54580000 {
321 compatible = "nvidia,t 272 compatible = "nvidia,tegra210-sor1";
322 reg = <0x0 0x54580000 273 reg = <0x0 0x54580000 0x0 0x00040000>;
323 interrupts = <GIC_SPI 274 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
324 clocks = <&tegra_car T 275 clocks = <&tegra_car TEGRA210_CLK_SOR1>,
325 <&tegra_car T 276 <&tegra_car TEGRA210_CLK_SOR1_OUT>,
326 <&tegra_car T 277 <&tegra_car TEGRA210_CLK_PLL_D2_OUT0>,
327 <&tegra_car T 278 <&tegra_car TEGRA210_CLK_PLL_DP>,
328 <&tegra_car T 279 <&tegra_car TEGRA210_CLK_SOR_SAFE>;
329 clock-names = "sor", " 280 clock-names = "sor", "out", "parent", "dp", "safe";
330 resets = <&tegra_car 1 281 resets = <&tegra_car 183>;
331 reset-names = "sor"; 282 reset-names = "sor";
332 pinctrl-0 = <&state_dp 283 pinctrl-0 = <&state_dpaux1_aux>;
333 pinctrl-1 = <&state_dp 284 pinctrl-1 = <&state_dpaux1_i2c>;
334 pinctrl-2 = <&state_dp 285 pinctrl-2 = <&state_dpaux1_off>;
335 pinctrl-names = "aux", 286 pinctrl-names = "aux", "i2c", "off";
336 power-domains = <&pd_s 287 power-domains = <&pd_sor>;
337 status = "disabled"; 288 status = "disabled";
338 }; 289 };
339 290
340 dpaux: dpaux@545c0000 { 291 dpaux: dpaux@545c0000 {
341 compatible = "nvidia,t !! 292 compatible = "nvidia,tegra124-dpaux";
342 reg = <0x0 0x545c0000 293 reg = <0x0 0x545c0000 0x0 0x00040000>;
343 interrupts = <GIC_SPI 294 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
344 clocks = <&tegra_car T 295 clocks = <&tegra_car TEGRA210_CLK_DPAUX>,
345 <&tegra_car T 296 <&tegra_car TEGRA210_CLK_PLL_DP>;
346 clock-names = "dpaux", 297 clock-names = "dpaux", "parent";
347 resets = <&tegra_car 1 298 resets = <&tegra_car 181>;
348 reset-names = "dpaux"; 299 reset-names = "dpaux";
349 power-domains = <&pd_s 300 power-domains = <&pd_sor>;
350 status = "disabled"; 301 status = "disabled";
351 302
352 state_dpaux_aux: pinmu 303 state_dpaux_aux: pinmux-aux {
353 groups = "dpau 304 groups = "dpaux-io";
354 function = "au 305 function = "aux";
355 }; 306 };
356 307
357 state_dpaux_i2c: pinmu 308 state_dpaux_i2c: pinmux-i2c {
358 groups = "dpau 309 groups = "dpaux-io";
359 function = "i2 310 function = "i2c";
360 }; 311 };
361 312
362 state_dpaux_off: pinmu 313 state_dpaux_off: pinmux-off {
363 groups = "dpau 314 groups = "dpaux-io";
364 function = "of 315 function = "off";
365 }; 316 };
366 317
367 i2c-bus { 318 i2c-bus {
368 #address-cells 319 #address-cells = <1>;
369 #size-cells = 320 #size-cells = <0>;
370 }; 321 };
371 }; 322 };
372 323
373 isp@54600000 { 324 isp@54600000 {
374 compatible = "nvidia,t 325 compatible = "nvidia,tegra210-isp";
375 reg = <0x0 0x54600000 326 reg = <0x0 0x54600000 0x0 0x00040000>;
376 interrupts = <GIC_SPI 327 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
377 clocks = <&tegra_car T <<
378 resets = <&tegra_car 2 <<
379 reset-names = "isp"; <<
380 status = "disabled"; 328 status = "disabled";
381 }; 329 };
382 330
383 isp@54680000 { 331 isp@54680000 {
384 compatible = "nvidia,t 332 compatible = "nvidia,tegra210-isp";
385 reg = <0x0 0x54680000 333 reg = <0x0 0x54680000 0x0 0x00040000>;
386 interrupts = <GIC_SPI 334 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
387 clocks = <&tegra_car T <<
388 resets = <&tegra_car 3 <<
389 reset-names = "isp"; <<
390 status = "disabled"; 335 status = "disabled";
391 }; 336 };
392 337
393 i2c@546c0000 { 338 i2c@546c0000 {
394 compatible = "nvidia,t 339 compatible = "nvidia,tegra210-i2c-vi";
395 reg = <0x0 0x546c0000 340 reg = <0x0 0x546c0000 0x0 0x00040000>;
396 interrupts = <GIC_SPI 341 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
397 clocks = <&tegra_car T <<
398 <&tegra_car T <<
399 clock-names = "div-clk <<
400 resets = <&tegra_car 2 <<
401 reset-names = "i2c"; <<
402 power-domains = <&pd_v <<
403 status = "disabled"; 342 status = "disabled";
404 <<
405 #address-cells = <1>; <<
406 #size-cells = <0>; <<
407 }; 343 };
408 }; 344 };
409 345
410 gic: interrupt-controller@50041000 { 346 gic: interrupt-controller@50041000 {
411 compatible = "arm,gic-400"; 347 compatible = "arm,gic-400";
412 #interrupt-cells = <3>; 348 #interrupt-cells = <3>;
413 interrupt-controller; 349 interrupt-controller;
414 reg = <0x0 0x50041000 0x0 0x10 350 reg = <0x0 0x50041000 0x0 0x1000>,
415 <0x0 0x50042000 0x0 0x20 351 <0x0 0x50042000 0x0 0x2000>,
416 <0x0 0x50044000 0x0 0x20 352 <0x0 0x50044000 0x0 0x2000>,
417 <0x0 0x50046000 0x0 0x20 353 <0x0 0x50046000 0x0 0x2000>;
418 interrupts = <GIC_PPI 9 354 interrupts = <GIC_PPI 9
419 (GIC_CPU_MASK_SIMPLE(4 355 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
420 interrupt-parent = <&gic>; 356 interrupt-parent = <&gic>;
421 }; 357 };
422 358
423 gpu@57000000 { 359 gpu@57000000 {
424 compatible = "nvidia,gm20b"; 360 compatible = "nvidia,gm20b";
425 reg = <0x0 0x57000000 0x0 0x01 361 reg = <0x0 0x57000000 0x0 0x01000000>,
426 <0x0 0x58000000 0x0 0x01 362 <0x0 0x58000000 0x0 0x01000000>;
427 interrupts = <GIC_SPI 157 IRQ_ 363 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
428 <GIC_SPI 158 IRQ_ 364 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
429 interrupt-names = "stall", "no 365 interrupt-names = "stall", "nonstall";
430 clocks = <&tegra_car TEGRA210_ 366 clocks = <&tegra_car TEGRA210_CLK_GPU>,
431 <&tegra_car TEGRA210_ 367 <&tegra_car TEGRA210_CLK_PLL_P_OUT5>,
432 <&tegra_car TEGRA210_ 368 <&tegra_car TEGRA210_CLK_PLL_G_REF>;
433 clock-names = "gpu", "pwr", "r 369 clock-names = "gpu", "pwr", "ref";
434 resets = <&tegra_car 184>; 370 resets = <&tegra_car 184>;
435 reset-names = "gpu"; 371 reset-names = "gpu";
436 372
437 iommus = <&mc TEGRA_SWGROUP_GP 373 iommus = <&mc TEGRA_SWGROUP_GPU>;
438 374
439 status = "disabled"; 375 status = "disabled";
440 }; 376 };
441 377
442 lic: interrupt-controller@60004000 { 378 lic: interrupt-controller@60004000 {
443 compatible = "nvidia,tegra210- 379 compatible = "nvidia,tegra210-ictlr";
444 reg = <0x0 0x60004000 0x0 0x40 380 reg = <0x0 0x60004000 0x0 0x40>, /* primary controller */
445 <0x0 0x60004100 0x0 0x40 381 <0x0 0x60004100 0x0 0x40>, /* secondary controller */
446 <0x0 0x60004200 0x0 0x40 382 <0x0 0x60004200 0x0 0x40>, /* tertiary controller */
447 <0x0 0x60004300 0x0 0x40 383 <0x0 0x60004300 0x0 0x40>, /* quaternary controller */
448 <0x0 0x60004400 0x0 0x40 384 <0x0 0x60004400 0x0 0x40>, /* quinary controller */
449 <0x0 0x60004500 0x0 0x40 385 <0x0 0x60004500 0x0 0x40>; /* senary controller */
450 interrupt-controller; 386 interrupt-controller;
451 #interrupt-cells = <3>; 387 #interrupt-cells = <3>;
452 interrupt-parent = <&gic>; 388 interrupt-parent = <&gic>;
453 }; 389 };
454 390
455 timer@60005000 { 391 timer@60005000 {
456 compatible = "nvidia,tegra210- 392 compatible = "nvidia,tegra210-timer";
457 reg = <0x0 0x60005000 0x0 0x40 393 reg = <0x0 0x60005000 0x0 0x400>;
458 interrupts = <GIC_SPI 156 IRQ_ 394 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
459 <GIC_SPI 0 IRQ_TY 395 <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
460 <GIC_SPI 1 IRQ_TY 396 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
461 <GIC_SPI 41 IRQ_T 397 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
462 <GIC_SPI 42 IRQ_T 398 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
463 <GIC_SPI 121 IRQ_ 399 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
464 <GIC_SPI 152 IRQ_ 400 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
465 <GIC_SPI 153 IRQ_ 401 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
466 <GIC_SPI 154 IRQ_ 402 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
467 <GIC_SPI 155 IRQ_ 403 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
468 <GIC_SPI 176 IRQ_ 404 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
469 <GIC_SPI 177 IRQ_ 405 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
470 <GIC_SPI 178 IRQ_ 406 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
471 <GIC_SPI 179 IRQ_ 407 <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
472 clocks = <&tegra_car TEGRA210_ 408 clocks = <&tegra_car TEGRA210_CLK_TIMER>;
473 clock-names = "timer"; 409 clock-names = "timer";
474 }; 410 };
475 411
476 tegra_car: clock@60006000 { 412 tegra_car: clock@60006000 {
477 compatible = "nvidia,tegra210- 413 compatible = "nvidia,tegra210-car";
478 reg = <0x0 0x60006000 0x0 0x10 414 reg = <0x0 0x60006000 0x0 0x1000>;
479 #clock-cells = <1>; 415 #clock-cells = <1>;
480 #reset-cells = <1>; 416 #reset-cells = <1>;
481 }; 417 };
482 418
483 flow-controller@60007000 { 419 flow-controller@60007000 {
484 compatible = "nvidia,tegra210- 420 compatible = "nvidia,tegra210-flowctrl";
485 reg = <0x0 0x60007000 0x0 0x10 421 reg = <0x0 0x60007000 0x0 0x1000>;
486 }; 422 };
487 423
488 gpio: gpio@6000d000 { 424 gpio: gpio@6000d000 {
489 compatible = "nvidia,tegra210- 425 compatible = "nvidia,tegra210-gpio", "nvidia,tegra30-gpio";
490 reg = <0x0 0x6000d000 0x0 0x10 426 reg = <0x0 0x6000d000 0x0 0x1000>;
491 interrupts = <GIC_SPI 32 IRQ_T 427 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
492 <GIC_SPI 33 IRQ_T 428 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
493 <GIC_SPI 34 IRQ_T 429 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
494 <GIC_SPI 35 IRQ_T 430 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
495 <GIC_SPI 55 IRQ_T 431 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
496 <GIC_SPI 87 IRQ_T 432 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
497 <GIC_SPI 89 IRQ_T 433 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
498 <GIC_SPI 125 IRQ_ 434 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
499 #gpio-cells = <2>; 435 #gpio-cells = <2>;
500 gpio-controller; 436 gpio-controller;
501 #interrupt-cells = <2>; 437 #interrupt-cells = <2>;
502 interrupt-controller; 438 interrupt-controller;
503 }; 439 };
504 440
505 apbdma: dma@60020000 { 441 apbdma: dma@60020000 {
506 compatible = "nvidia,tegra210- 442 compatible = "nvidia,tegra210-apbdma", "nvidia,tegra148-apbdma";
507 reg = <0x0 0x60020000 0x0 0x14 443 reg = <0x0 0x60020000 0x0 0x1400>;
508 interrupts = <GIC_SPI 104 IRQ_ 444 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
509 <GIC_SPI 105 IRQ_ 445 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
510 <GIC_SPI 106 IRQ_ 446 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
511 <GIC_SPI 107 IRQ_ 447 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
512 <GIC_SPI 108 IRQ_ 448 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
513 <GIC_SPI 109 IRQ_ 449 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
514 <GIC_SPI 110 IRQ_ 450 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
515 <GIC_SPI 111 IRQ_ 451 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
516 <GIC_SPI 112 IRQ_ 452 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
517 <GIC_SPI 113 IRQ_ 453 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
518 <GIC_SPI 114 IRQ_ 454 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
519 <GIC_SPI 115 IRQ_ 455 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
520 <GIC_SPI 116 IRQ_ 456 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
521 <GIC_SPI 117 IRQ_ 457 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
522 <GIC_SPI 118 IRQ_ 458 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
523 <GIC_SPI 119 IRQ_ 459 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
524 <GIC_SPI 128 IRQ_ 460 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
525 <GIC_SPI 129 IRQ_ 461 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
526 <GIC_SPI 130 IRQ_ 462 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
527 <GIC_SPI 131 IRQ_ 463 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
528 <GIC_SPI 132 IRQ_ 464 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
529 <GIC_SPI 133 IRQ_ 465 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
530 <GIC_SPI 134 IRQ_ 466 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
531 <GIC_SPI 135 IRQ_ 467 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
532 <GIC_SPI 136 IRQ_ 468 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
533 <GIC_SPI 137 IRQ_ 469 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
534 <GIC_SPI 138 IRQ_ 470 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
535 <GIC_SPI 139 IRQ_ 471 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
536 <GIC_SPI 140 IRQ_ 472 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
537 <GIC_SPI 141 IRQ_ 473 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
538 <GIC_SPI 142 IRQ_ 474 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
539 <GIC_SPI 143 IRQ_ 475 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
540 clocks = <&tegra_car TEGRA210_ 476 clocks = <&tegra_car TEGRA210_CLK_APBDMA>;
541 clock-names = "dma"; 477 clock-names = "dma";
542 resets = <&tegra_car 34>; 478 resets = <&tegra_car 34>;
543 reset-names = "dma"; 479 reset-names = "dma";
544 #dma-cells = <1>; 480 #dma-cells = <1>;
545 }; 481 };
546 482
547 apbmisc@70000800 { 483 apbmisc@70000800 {
548 compatible = "nvidia,tegra210- 484 compatible = "nvidia,tegra210-apbmisc", "nvidia,tegra20-apbmisc";
549 reg = <0x0 0x70000800 0x0 0x64 485 reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */
550 <0x0 0x70000008 0x0 0x04 486 <0x0 0x70000008 0x0 0x04>; /* Strapping options */
551 }; 487 };
552 488
553 pinmux: pinmux@700008d4 { 489 pinmux: pinmux@700008d4 {
554 compatible = "nvidia,tegra210- 490 compatible = "nvidia,tegra210-pinmux";
555 reg = <0x0 0x700008d4 0x0 0x29 491 reg = <0x0 0x700008d4 0x0 0x29c>, /* Pad control registers */
556 <0x0 0x70003000 0x0 0x29 492 <0x0 0x70003000 0x0 0x294>; /* Mux registers */
557 !! 493 sdmmc1_3v3_drv: sdmmc1-3v3-drv {
558 sdmmc1_1v8_drv: pinmux-sdmmc1- <<
559 sdmmc1 { 494 sdmmc1 {
560 nvidia,pins = 495 nvidia,pins = "drive_sdmmc1";
561 nvidia,pull-do !! 496 nvidia,pull-down-strength = <0x8>;
562 nvidia,pull-up !! 497 nvidia,pull-up-strength = <0x8>;
563 }; 498 };
564 }; 499 };
565 !! 500 sdmmc1_1v8_drv: sdmmc1-1v8-drv {
566 sdmmc1_3v3_drv: pinmux-sdmmc1- <<
567 sdmmc1 { 501 sdmmc1 {
568 nvidia,pins = 502 nvidia,pins = "drive_sdmmc1";
569 nvidia,pull-do !! 503 nvidia,pull-down-strength = <0x4>;
570 nvidia,pull-up !! 504 nvidia,pull-up-strength = <0x3>;
571 }; 505 };
572 }; 506 };
573 !! 507 sdmmc2_1v8_drv: sdmmc2-1v8-drv {
574 sdmmc2_1v8_drv: pinmux-sdmmc2- <<
575 sdmmc2 { 508 sdmmc2 {
576 nvidia,pins = 509 nvidia,pins = "drive_sdmmc2";
577 nvidia,pull-do 510 nvidia,pull-down-strength = <0x10>;
578 nvidia,pull-up 511 nvidia,pull-up-strength = <0x10>;
579 }; 512 };
580 }; 513 };
581 !! 514 sdmmc3_3v3_drv: sdmmc3-3v3-drv {
582 sdmmc3_1v8_drv: pinmux-sdmmc3- <<
583 sdmmc3 { 515 sdmmc3 {
584 nvidia,pins = 516 nvidia,pins = "drive_sdmmc3";
585 nvidia,pull-do !! 517 nvidia,pull-down-strength = <0x8>;
586 nvidia,pull-up !! 518 nvidia,pull-up-strength = <0x8>;
587 }; 519 };
588 }; 520 };
589 !! 521 sdmmc3_1v8_drv: sdmmc3-1v8-drv {
590 sdmmc3_3v3_drv: pinmux-sdmmc3- <<
591 sdmmc3 { 522 sdmmc3 {
592 nvidia,pins = 523 nvidia,pins = "drive_sdmmc3";
593 nvidia,pull-do !! 524 nvidia,pull-down-strength = <0x4>;
594 nvidia,pull-up !! 525 nvidia,pull-up-strength = <0x3>;
595 }; 526 };
596 }; 527 };
597 !! 528 sdmmc4_1v8_drv: sdmmc4-1v8-drv {
598 sdmmc4_1v8_drv: pinmux-sdmmc4- <<
599 sdmmc4 { 529 sdmmc4 {
600 nvidia,pins = 530 nvidia,pins = "drive_sdmmc4";
601 nvidia,pull-do 531 nvidia,pull-down-strength = <0x10>;
602 nvidia,pull-up 532 nvidia,pull-up-strength = <0x10>;
603 }; 533 };
604 }; 534 };
605 }; 535 };
606 536
607 /* 537 /*
608 * There are two serial driver i.e. 82 538 * There are two serial driver i.e. 8250 based simple serial
609 * driver and APB DMA based serial dri 539 * driver and APB DMA based serial driver for higher baudrate
610 * and performance. To enable the 8250 540 * and performance. To enable the 8250 based driver, the compatible
611 * is "nvidia,tegra124-uart", "nvidia, 541 * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable
612 * the APB DMA based serial driver, th 542 * the APB DMA based serial driver, the compatible is
613 * "nvidia,tegra124-hsuart", "nvidia,t 543 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart".
614 */ 544 */
615 uarta: serial@70006000 { 545 uarta: serial@70006000 {
616 compatible = "nvidia,tegra210- 546 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
617 reg = <0x0 0x70006000 0x0 0x40 547 reg = <0x0 0x70006000 0x0 0x40>;
618 reg-shift = <2>; 548 reg-shift = <2>;
619 interrupts = <GIC_SPI 36 IRQ_T 549 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
620 clocks = <&tegra_car TEGRA210_ 550 clocks = <&tegra_car TEGRA210_CLK_UARTA>;
>> 551 clock-names = "serial";
621 resets = <&tegra_car 6>; 552 resets = <&tegra_car 6>;
>> 553 reset-names = "serial";
622 dmas = <&apbdma 8>, <&apbdma 8 554 dmas = <&apbdma 8>, <&apbdma 8>;
623 dma-names = "rx", "tx"; 555 dma-names = "rx", "tx";
624 status = "disabled"; 556 status = "disabled";
625 }; 557 };
626 558
627 uartb: serial@70006040 { 559 uartb: serial@70006040 {
628 compatible = "nvidia,tegra210- 560 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
629 reg = <0x0 0x70006040 0x0 0x40 561 reg = <0x0 0x70006040 0x0 0x40>;
630 reg-shift = <2>; 562 reg-shift = <2>;
631 interrupts = <GIC_SPI 37 IRQ_T 563 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
632 clocks = <&tegra_car TEGRA210_ 564 clocks = <&tegra_car TEGRA210_CLK_UARTB>;
>> 565 clock-names = "serial";
633 resets = <&tegra_car 7>; 566 resets = <&tegra_car 7>;
>> 567 reset-names = "serial";
634 dmas = <&apbdma 9>, <&apbdma 9 568 dmas = <&apbdma 9>, <&apbdma 9>;
635 dma-names = "rx", "tx"; 569 dma-names = "rx", "tx";
636 status = "disabled"; 570 status = "disabled";
637 }; 571 };
638 572
639 uartc: serial@70006200 { 573 uartc: serial@70006200 {
640 compatible = "nvidia,tegra210- 574 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
641 reg = <0x0 0x70006200 0x0 0x40 575 reg = <0x0 0x70006200 0x0 0x40>;
642 reg-shift = <2>; 576 reg-shift = <2>;
643 interrupts = <GIC_SPI 46 IRQ_T 577 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
644 clocks = <&tegra_car TEGRA210_ 578 clocks = <&tegra_car TEGRA210_CLK_UARTC>;
>> 579 clock-names = "serial";
645 resets = <&tegra_car 55>; 580 resets = <&tegra_car 55>;
>> 581 reset-names = "serial";
646 dmas = <&apbdma 10>, <&apbdma 582 dmas = <&apbdma 10>, <&apbdma 10>;
647 dma-names = "rx", "tx"; 583 dma-names = "rx", "tx";
648 status = "disabled"; 584 status = "disabled";
649 }; 585 };
650 586
651 uartd: serial@70006300 { 587 uartd: serial@70006300 {
652 compatible = "nvidia,tegra210- 588 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
653 reg = <0x0 0x70006300 0x0 0x40 589 reg = <0x0 0x70006300 0x0 0x40>;
654 reg-shift = <2>; 590 reg-shift = <2>;
655 interrupts = <GIC_SPI 90 IRQ_T 591 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
656 clocks = <&tegra_car TEGRA210_ 592 clocks = <&tegra_car TEGRA210_CLK_UARTD>;
>> 593 clock-names = "serial";
657 resets = <&tegra_car 65>; 594 resets = <&tegra_car 65>;
>> 595 reset-names = "serial";
658 dmas = <&apbdma 19>, <&apbdma 596 dmas = <&apbdma 19>, <&apbdma 19>;
659 dma-names = "rx", "tx"; 597 dma-names = "rx", "tx";
660 status = "disabled"; 598 status = "disabled";
661 }; 599 };
662 600
663 pwm: pwm@7000a000 { 601 pwm: pwm@7000a000 {
664 compatible = "nvidia,tegra210- 602 compatible = "nvidia,tegra210-pwm", "nvidia,tegra20-pwm";
665 reg = <0x0 0x7000a000 0x0 0x10 603 reg = <0x0 0x7000a000 0x0 0x100>;
666 #pwm-cells = <2>; 604 #pwm-cells = <2>;
667 clocks = <&tegra_car TEGRA210_ 605 clocks = <&tegra_car TEGRA210_CLK_PWM>;
>> 606 clock-names = "pwm";
668 resets = <&tegra_car 17>; 607 resets = <&tegra_car 17>;
669 reset-names = "pwm"; 608 reset-names = "pwm";
670 status = "disabled"; 609 status = "disabled";
671 }; 610 };
672 611
673 i2c@7000c000 { 612 i2c@7000c000 {
674 compatible = "nvidia,tegra210- 613 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c";
675 reg = <0x0 0x7000c000 0x0 0x10 614 reg = <0x0 0x7000c000 0x0 0x100>;
676 interrupts = <GIC_SPI 38 IRQ_T 615 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
677 #address-cells = <1>; 616 #address-cells = <1>;
678 #size-cells = <0>; 617 #size-cells = <0>;
679 clocks = <&tegra_car TEGRA210_ 618 clocks = <&tegra_car TEGRA210_CLK_I2C1>;
680 clock-names = "div-clk"; 619 clock-names = "div-clk";
681 resets = <&tegra_car 12>; 620 resets = <&tegra_car 12>;
682 reset-names = "i2c"; 621 reset-names = "i2c";
683 dmas = <&apbdma 21>, <&apbdma 622 dmas = <&apbdma 21>, <&apbdma 21>;
684 dma-names = "rx", "tx"; 623 dma-names = "rx", "tx";
685 status = "disabled"; 624 status = "disabled";
686 }; 625 };
687 626
688 i2c@7000c400 { 627 i2c@7000c400 {
689 compatible = "nvidia,tegra210- 628 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c";
690 reg = <0x0 0x7000c400 0x0 0x10 629 reg = <0x0 0x7000c400 0x0 0x100>;
691 interrupts = <GIC_SPI 84 IRQ_T 630 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
692 #address-cells = <1>; 631 #address-cells = <1>;
693 #size-cells = <0>; 632 #size-cells = <0>;
694 clocks = <&tegra_car TEGRA210_ 633 clocks = <&tegra_car TEGRA210_CLK_I2C2>;
695 clock-names = "div-clk"; 634 clock-names = "div-clk";
696 resets = <&tegra_car 54>; 635 resets = <&tegra_car 54>;
697 reset-names = "i2c"; 636 reset-names = "i2c";
698 dmas = <&apbdma 22>, <&apbdma 637 dmas = <&apbdma 22>, <&apbdma 22>;
699 dma-names = "rx", "tx"; 638 dma-names = "rx", "tx";
700 status = "disabled"; 639 status = "disabled";
701 }; 640 };
702 641
703 i2c@7000c500 { 642 i2c@7000c500 {
704 compatible = "nvidia,tegra210- 643 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c";
705 reg = <0x0 0x7000c500 0x0 0x10 644 reg = <0x0 0x7000c500 0x0 0x100>;
706 interrupts = <GIC_SPI 92 IRQ_T 645 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
707 #address-cells = <1>; 646 #address-cells = <1>;
708 #size-cells = <0>; 647 #size-cells = <0>;
709 clocks = <&tegra_car TEGRA210_ 648 clocks = <&tegra_car TEGRA210_CLK_I2C3>;
710 clock-names = "div-clk"; 649 clock-names = "div-clk";
711 resets = <&tegra_car 67>; 650 resets = <&tegra_car 67>;
712 reset-names = "i2c"; 651 reset-names = "i2c";
713 dmas = <&apbdma 23>, <&apbdma 652 dmas = <&apbdma 23>, <&apbdma 23>;
714 dma-names = "rx", "tx"; 653 dma-names = "rx", "tx";
715 status = "disabled"; 654 status = "disabled";
716 }; 655 };
717 656
718 i2c@7000c700 { 657 i2c@7000c700 {
719 compatible = "nvidia,tegra210- 658 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c";
720 reg = <0x0 0x7000c700 0x0 0x10 659 reg = <0x0 0x7000c700 0x0 0x100>;
721 interrupts = <GIC_SPI 120 IRQ_ 660 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
722 #address-cells = <1>; 661 #address-cells = <1>;
723 #size-cells = <0>; 662 #size-cells = <0>;
724 clocks = <&tegra_car TEGRA210_ 663 clocks = <&tegra_car TEGRA210_CLK_I2C4>;
725 clock-names = "div-clk"; 664 clock-names = "div-clk";
726 resets = <&tegra_car 103>; 665 resets = <&tegra_car 103>;
727 reset-names = "i2c"; 666 reset-names = "i2c";
728 dmas = <&apbdma 26>, <&apbdma 667 dmas = <&apbdma 26>, <&apbdma 26>;
729 dma-names = "rx", "tx"; 668 dma-names = "rx", "tx";
730 pinctrl-0 = <&state_dpaux1_i2c 669 pinctrl-0 = <&state_dpaux1_i2c>;
731 pinctrl-1 = <&state_dpaux1_off 670 pinctrl-1 = <&state_dpaux1_off>;
732 pinctrl-names = "default", "id 671 pinctrl-names = "default", "idle";
733 status = "disabled"; 672 status = "disabled";
734 }; 673 };
735 674
736 i2c@7000d000 { 675 i2c@7000d000 {
737 compatible = "nvidia,tegra210- 676 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c";
738 reg = <0x0 0x7000d000 0x0 0x10 677 reg = <0x0 0x7000d000 0x0 0x100>;
739 interrupts = <GIC_SPI 53 IRQ_T 678 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
740 #address-cells = <1>; 679 #address-cells = <1>;
741 #size-cells = <0>; 680 #size-cells = <0>;
742 clocks = <&tegra_car TEGRA210_ 681 clocks = <&tegra_car TEGRA210_CLK_I2C5>;
743 clock-names = "div-clk"; 682 clock-names = "div-clk";
744 resets = <&tegra_car 47>; 683 resets = <&tegra_car 47>;
745 reset-names = "i2c"; 684 reset-names = "i2c";
746 dmas = <&apbdma 24>, <&apbdma 685 dmas = <&apbdma 24>, <&apbdma 24>;
747 dma-names = "rx", "tx"; 686 dma-names = "rx", "tx";
748 status = "disabled"; 687 status = "disabled";
749 }; 688 };
750 689
751 i2c@7000d100 { 690 i2c@7000d100 {
752 compatible = "nvidia,tegra210- 691 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c";
753 reg = <0x0 0x7000d100 0x0 0x10 692 reg = <0x0 0x7000d100 0x0 0x100>;
754 interrupts = <GIC_SPI 63 IRQ_T 693 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
755 #address-cells = <1>; 694 #address-cells = <1>;
756 #size-cells = <0>; 695 #size-cells = <0>;
757 clocks = <&tegra_car TEGRA210_ 696 clocks = <&tegra_car TEGRA210_CLK_I2C6>;
758 clock-names = "div-clk"; 697 clock-names = "div-clk";
759 resets = <&tegra_car 166>; 698 resets = <&tegra_car 166>;
760 reset-names = "i2c"; 699 reset-names = "i2c";
761 dmas = <&apbdma 30>, <&apbdma 700 dmas = <&apbdma 30>, <&apbdma 30>;
762 dma-names = "rx", "tx"; 701 dma-names = "rx", "tx";
763 pinctrl-0 = <&state_dpaux_i2c> 702 pinctrl-0 = <&state_dpaux_i2c>;
764 pinctrl-1 = <&state_dpaux_off> 703 pinctrl-1 = <&state_dpaux_off>;
765 pinctrl-names = "default", "id 704 pinctrl-names = "default", "idle";
766 status = "disabled"; 705 status = "disabled";
767 }; 706 };
768 707
769 spi@7000d400 { 708 spi@7000d400 {
770 compatible = "nvidia,tegra210- 709 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
771 reg = <0x0 0x7000d400 0x0 0x20 710 reg = <0x0 0x7000d400 0x0 0x200>;
772 interrupts = <GIC_SPI 59 IRQ_T 711 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
773 #address-cells = <1>; 712 #address-cells = <1>;
774 #size-cells = <0>; 713 #size-cells = <0>;
775 clocks = <&tegra_car TEGRA210_ 714 clocks = <&tegra_car TEGRA210_CLK_SBC1>;
776 clock-names = "spi"; 715 clock-names = "spi";
777 resets = <&tegra_car 41>; 716 resets = <&tegra_car 41>;
778 reset-names = "spi"; 717 reset-names = "spi";
779 dmas = <&apbdma 15>, <&apbdma 718 dmas = <&apbdma 15>, <&apbdma 15>;
780 dma-names = "rx", "tx"; 719 dma-names = "rx", "tx";
781 status = "disabled"; 720 status = "disabled";
782 }; 721 };
783 722
784 spi@7000d600 { 723 spi@7000d600 {
785 compatible = "nvidia,tegra210- 724 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
786 reg = <0x0 0x7000d600 0x0 0x20 725 reg = <0x0 0x7000d600 0x0 0x200>;
787 interrupts = <GIC_SPI 82 IRQ_T 726 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
788 #address-cells = <1>; 727 #address-cells = <1>;
789 #size-cells = <0>; 728 #size-cells = <0>;
790 clocks = <&tegra_car TEGRA210_ 729 clocks = <&tegra_car TEGRA210_CLK_SBC2>;
791 clock-names = "spi"; 730 clock-names = "spi";
792 resets = <&tegra_car 44>; 731 resets = <&tegra_car 44>;
793 reset-names = "spi"; 732 reset-names = "spi";
794 dmas = <&apbdma 16>, <&apbdma 733 dmas = <&apbdma 16>, <&apbdma 16>;
795 dma-names = "rx", "tx"; 734 dma-names = "rx", "tx";
796 status = "disabled"; 735 status = "disabled";
797 }; 736 };
798 737
799 spi@7000d800 { 738 spi@7000d800 {
800 compatible = "nvidia,tegra210- 739 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
801 reg = <0x0 0x7000d800 0x0 0x20 740 reg = <0x0 0x7000d800 0x0 0x200>;
802 interrupts = <GIC_SPI 83 IRQ_T 741 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
803 #address-cells = <1>; 742 #address-cells = <1>;
804 #size-cells = <0>; 743 #size-cells = <0>;
805 clocks = <&tegra_car TEGRA210_ 744 clocks = <&tegra_car TEGRA210_CLK_SBC3>;
806 clock-names = "spi"; 745 clock-names = "spi";
807 resets = <&tegra_car 46>; 746 resets = <&tegra_car 46>;
808 reset-names = "spi"; 747 reset-names = "spi";
809 dmas = <&apbdma 17>, <&apbdma 748 dmas = <&apbdma 17>, <&apbdma 17>;
810 dma-names = "rx", "tx"; 749 dma-names = "rx", "tx";
811 status = "disabled"; 750 status = "disabled";
812 }; 751 };
813 752
814 spi@7000da00 { 753 spi@7000da00 {
815 compatible = "nvidia,tegra210- 754 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
816 reg = <0x0 0x7000da00 0x0 0x20 755 reg = <0x0 0x7000da00 0x0 0x200>;
817 interrupts = <GIC_SPI 93 IRQ_T 756 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
818 #address-cells = <1>; 757 #address-cells = <1>;
819 #size-cells = <0>; 758 #size-cells = <0>;
820 clocks = <&tegra_car TEGRA210_ 759 clocks = <&tegra_car TEGRA210_CLK_SBC4>;
821 clock-names = "spi"; 760 clock-names = "spi";
822 resets = <&tegra_car 68>; 761 resets = <&tegra_car 68>;
823 reset-names = "spi"; 762 reset-names = "spi";
824 dmas = <&apbdma 18>, <&apbdma 763 dmas = <&apbdma 18>, <&apbdma 18>;
825 dma-names = "rx", "tx"; 764 dma-names = "rx", "tx";
826 status = "disabled"; 765 status = "disabled";
827 }; 766 };
828 767
829 rtc@7000e000 { 768 rtc@7000e000 {
830 compatible = "nvidia,tegra210- 769 compatible = "nvidia,tegra210-rtc", "nvidia,tegra20-rtc";
831 reg = <0x0 0x7000e000 0x0 0x10 770 reg = <0x0 0x7000e000 0x0 0x100>;
832 interrupts = <16 IRQ_TYPE_LEVE !! 771 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
833 interrupt-parent = <&tegra_pmc <<
834 clocks = <&tegra_car TEGRA210_ 772 clocks = <&tegra_car TEGRA210_CLK_RTC>;
835 clock-names = "rtc"; 773 clock-names = "rtc";
836 }; 774 };
837 775
838 tegra_pmc: pmc@7000e400 { !! 776 pmc: pmc@7000e400 {
839 compatible = "nvidia,tegra210- 777 compatible = "nvidia,tegra210-pmc";
840 reg = <0x0 0x7000e400 0x0 0x40 778 reg = <0x0 0x7000e400 0x0 0x400>;
841 clocks = <&tegra_car TEGRA210_ 779 clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>;
842 clock-names = "pclk", "clk32k_ 780 clock-names = "pclk", "clk32k_in";
843 #clock-cells = <1>; <<
844 #interrupt-cells = <2>; <<
845 interrupt-controller; <<
846 <<
847 pinmux { <<
848 pex_dpd_disable: pex-d <<
849 pins = "pex-bi <<
850 low-power-disa <<
851 }; <<
852 <<
853 pex_dpd_enable: pex-dp <<
854 pins = "pex-bi <<
855 low-power-enab <<
856 }; <<
857 <<
858 sdmmc1_1v8: sdmmc1-1v8 <<
859 pins = "sdmmc1 <<
860 power-source = <<
861 }; <<
862 <<
863 sdmmc1_3v3: sdmmc1-3v3 <<
864 pins = "sdmmc1 <<
865 power-source = <<
866 }; <<
867 <<
868 sdmmc3_1v8: sdmmc3-1v8 <<
869 pins = "sdmmc3 <<
870 power-source = <<
871 }; <<
872 <<
873 sdmmc3_3v3: sdmmc3-3v3 <<
874 pins = "sdmmc3 <<
875 power-source = <<
876 }; <<
877 }; <<
878 781
879 powergates { 782 powergates {
880 pd_audio: aud { 783 pd_audio: aud {
881 clocks = <&teg 784 clocks = <&tegra_car TEGRA210_CLK_APE>,
882 <&teg 785 <&tegra_car TEGRA210_CLK_APB2APE>;
883 resets = <&teg 786 resets = <&tegra_car 198>;
884 #power-domain- 787 #power-domain-cells = <0>;
885 }; 788 };
886 789
887 pd_sor: sor { 790 pd_sor: sor {
888 clocks = <&teg 791 clocks = <&tegra_car TEGRA210_CLK_SOR0>,
889 <&teg 792 <&tegra_car TEGRA210_CLK_SOR1>,
890 <&teg !! 793 <&tegra_car TEGRA210_CLK_CSI>,
891 <&teg <<
892 <&teg <<
893 <&teg 794 <&tegra_car TEGRA210_CLK_DSIA>,
894 <&teg 795 <&tegra_car TEGRA210_CLK_DSIB>,
895 <&teg 796 <&tegra_car TEGRA210_CLK_DPAUX>,
896 <&teg 797 <&tegra_car TEGRA210_CLK_DPAUX1>,
897 <&teg 798 <&tegra_car TEGRA210_CLK_MIPI_CAL>;
898 resets = <&teg 799 resets = <&tegra_car TEGRA210_CLK_SOR0>,
899 <&teg 800 <&tegra_car TEGRA210_CLK_SOR1>,
>> 801 <&tegra_car TEGRA210_CLK_CSI>,
900 <&teg 802 <&tegra_car TEGRA210_CLK_DSIA>,
901 <&teg 803 <&tegra_car TEGRA210_CLK_DSIB>,
902 <&teg 804 <&tegra_car TEGRA210_CLK_DPAUX>,
903 <&teg 805 <&tegra_car TEGRA210_CLK_DPAUX1>,
904 <&teg 806 <&tegra_car TEGRA210_CLK_MIPI_CAL>;
905 #power-domain- 807 #power-domain-cells = <0>;
906 }; 808 };
907 809
908 pd_venc: venc { <<
909 clocks = <&teg <<
910 <&teg <<
911 resets = <&mc <<
912 <&teg <<
913 <&teg <<
914 #power-domain- <<
915 }; <<
916 <<
917 pd_vic: vic { <<
918 clocks = <&teg <<
919 resets = <&teg <<
920 #power-domain- <<
921 }; <<
922 <<
923 pd_xusbss: xusba { 810 pd_xusbss: xusba {
924 clocks = <&teg 811 clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>;
925 resets = <&teg 812 resets = <&tegra_car TEGRA210_CLK_XUSB_SS>;
926 #power-domain- 813 #power-domain-cells = <0>;
927 }; 814 };
928 815
929 pd_xusbdev: xusbb { 816 pd_xusbdev: xusbb {
930 clocks = <&teg 817 clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>;
931 resets = <&teg 818 resets = <&tegra_car 95>;
932 #power-domain- 819 #power-domain-cells = <0>;
933 }; 820 };
934 821
935 pd_xusbhost: xusbc { 822 pd_xusbhost: xusbc {
936 clocks = <&teg 823 clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>;
937 resets = <&teg 824 resets = <&tegra_car TEGRA210_CLK_XUSB_HOST>;
938 #power-domain- 825 #power-domain-cells = <0>;
939 }; 826 };
>> 827
>> 828 pd_vic: vic {
>> 829 clocks = <&tegra_car TEGRA210_CLK_VIC03>;
>> 830 clock-names = "vic";
>> 831 resets = <&tegra_car 178>;
>> 832 reset-names = "vic";
>> 833 #power-domain-cells = <0>;
>> 834 };
>> 835 };
>> 836
>> 837 sdmmc1_3v3: sdmmc1-3v3 {
>> 838 pins = "sdmmc1";
>> 839 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
>> 840 };
>> 841
>> 842 sdmmc1_1v8: sdmmc1-1v8 {
>> 843 pins = "sdmmc1";
>> 844 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
>> 845 };
>> 846
>> 847 sdmmc3_3v3: sdmmc3-3v3 {
>> 848 pins = "sdmmc3";
>> 849 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
>> 850 };
>> 851
>> 852 sdmmc3_1v8: sdmmc3-1v8 {
>> 853 pins = "sdmmc3";
>> 854 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
>> 855 };
>> 856
>> 857 pex_dpd_disable: pex_en {
>> 858 pex-dpd-disable {
>> 859 pins = "pex-bias", "pex-clk1", "pex-clk2";
>> 860 low-power-disable;
>> 861 };
>> 862 };
>> 863
>> 864 pex_dpd_enable: pex_dis {
>> 865 pex-dpd-enable {
>> 866 pins = "pex-bias", "pex-clk1", "pex-clk2";
>> 867 low-power-enable;
>> 868 };
940 }; 869 };
941 }; 870 };
942 871
943 fuse@7000f800 { 872 fuse@7000f800 {
944 compatible = "nvidia,tegra210- 873 compatible = "nvidia,tegra210-efuse";
945 reg = <0x0 0x7000f800 0x0 0x40 874 reg = <0x0 0x7000f800 0x0 0x400>;
946 clocks = <&tegra_car TEGRA210_ 875 clocks = <&tegra_car TEGRA210_CLK_FUSE>;
947 clock-names = "fuse"; 876 clock-names = "fuse";
948 resets = <&tegra_car 39>; 877 resets = <&tegra_car 39>;
949 reset-names = "fuse"; 878 reset-names = "fuse";
950 }; 879 };
951 880
952 mc: memory-controller@70019000 { 881 mc: memory-controller@70019000 {
953 compatible = "nvidia,tegra210- 882 compatible = "nvidia,tegra210-mc";
954 reg = <0x0 0x70019000 0x0 0x10 883 reg = <0x0 0x70019000 0x0 0x1000>;
955 clocks = <&tegra_car TEGRA210_ 884 clocks = <&tegra_car TEGRA210_CLK_MC>;
956 clock-names = "mc"; 885 clock-names = "mc";
957 886
958 interrupts = <GIC_SPI 77 IRQ_T 887 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
959 888
960 #iommu-cells = <1>; 889 #iommu-cells = <1>;
961 #reset-cells = <1>; <<
962 }; <<
963 <<
964 emc: external-memory-controller@7001b0 <<
965 compatible = "nvidia,tegra210- <<
966 reg = <0x0 0x7001b000 0x0 0x10 <<
967 <0x0 0x7001e000 0x0 0x10 <<
968 <0x0 0x7001f000 0x0 0x10 <<
969 clocks = <&tegra_car TEGRA210_ <<
970 clock-names = "emc"; <<
971 interrupts = <GIC_SPI 78 IRQ_T <<
972 nvidia,memory-controller = <&m <<
973 #cooling-cells = <2>; <<
974 }; 890 };
975 891
976 sata@70020000 { 892 sata@70020000 {
977 compatible = "nvidia,tegra210- 893 compatible = "nvidia,tegra210-ahci";
978 reg = <0x0 0x70027000 0x0 0x20 894 reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */
979 <0x0 0x70020000 0x0 0x70 895 <0x0 0x70020000 0x0 0x7000>, /* SATA */
980 <0x0 0x70001100 0x0 0x10 896 <0x0 0x70001100 0x0 0x1000>; /* SATA AUX */
981 interrupts = <GIC_SPI 23 IRQ_T 897 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
982 clocks = <&tegra_car TEGRA210_ 898 clocks = <&tegra_car TEGRA210_CLK_SATA>,
983 <&tegra_car TEGRA210_ 899 <&tegra_car TEGRA210_CLK_SATA_OOB>;
984 clock-names = "sata", "sata-oo 900 clock-names = "sata", "sata-oob";
985 resets = <&tegra_car 124>, 901 resets = <&tegra_car 124>,
986 <&tegra_car 129>, !! 902 <&tegra_car 123>,
987 <&tegra_car 123>; !! 903 <&tegra_car 129>;
988 reset-names = "sata", "sata-co !! 904 reset-names = "sata", "sata-oob", "sata-cold";
989 status = "disabled"; 905 status = "disabled";
990 }; 906 };
991 907
992 hda@70030000 { 908 hda@70030000 {
993 compatible = "nvidia,tegra210- 909 compatible = "nvidia,tegra210-hda", "nvidia,tegra30-hda";
994 reg = <0x0 0x70030000 0x0 0x10 910 reg = <0x0 0x70030000 0x0 0x10000>;
995 interrupts = <GIC_SPI 81 IRQ_T 911 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
996 clocks = <&tegra_car TEGRA210_ 912 clocks = <&tegra_car TEGRA210_CLK_HDA>,
997 <&tegra_car TEGRA210_ 913 <&tegra_car TEGRA210_CLK_HDA2HDMI>,
998 <&tegra_car TEGRA210_ 914 <&tegra_car TEGRA210_CLK_HDA2CODEC_2X>;
999 clock-names = "hda", "hda2hdmi 915 clock-names = "hda", "hda2hdmi", "hda2codec_2x";
1000 resets = <&tegra_car 125>, /* 916 resets = <&tegra_car 125>, /* hda */
1001 <&tegra_car 128>, /* 917 <&tegra_car 128>, /* hda2hdmi */
1002 <&tegra_car 111>; /* 918 <&tegra_car 111>; /* hda2codec_2x */
1003 reset-names = "hda", "hda2hdm 919 reset-names = "hda", "hda2hdmi", "hda2codec_2x";
1004 power-domains = <&pd_sor>; 920 power-domains = <&pd_sor>;
1005 status = "disabled"; 921 status = "disabled";
1006 }; 922 };
1007 923
1008 usb@70090000 { 924 usb@70090000 {
1009 compatible = "nvidia,tegra210 925 compatible = "nvidia,tegra210-xusb";
1010 reg = <0x0 0x70090000 0x0 0x8 926 reg = <0x0 0x70090000 0x0 0x8000>,
1011 <0x0 0x70098000 0x0 0x1 927 <0x0 0x70098000 0x0 0x1000>,
1012 <0x0 0x70099000 0x0 0x1 928 <0x0 0x70099000 0x0 0x1000>;
1013 reg-names = "hcd", "fpci", "i 929 reg-names = "hcd", "fpci", "ipfs";
1014 930
1015 interrupts = <GIC_SPI 39 IRQ_ 931 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
1016 <GIC_SPI 40 IRQ_ 932 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1017 933
1018 clocks = <&tegra_car TEGRA210 934 clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>,
1019 <&tegra_car TEGRA210 935 <&tegra_car TEGRA210_CLK_XUSB_HOST_SRC>,
1020 <&tegra_car TEGRA210 936 <&tegra_car TEGRA210_CLK_XUSB_FALCON_SRC>,
1021 <&tegra_car TEGRA210 937 <&tegra_car TEGRA210_CLK_XUSB_SS>,
1022 <&tegra_car TEGRA210 938 <&tegra_car TEGRA210_CLK_XUSB_SS_DIV2>,
1023 <&tegra_car TEGRA210 939 <&tegra_car TEGRA210_CLK_XUSB_SS_SRC>,
1024 <&tegra_car TEGRA210 940 <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>,
1025 <&tegra_car TEGRA210 941 <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>,
1026 <&tegra_car TEGRA210 942 <&tegra_car TEGRA210_CLK_PLL_U_480M>,
1027 <&tegra_car TEGRA210 943 <&tegra_car TEGRA210_CLK_CLK_M>,
1028 <&tegra_car TEGRA210 944 <&tegra_car TEGRA210_CLK_PLL_E>;
1029 clock-names = "xusb_host", "x 945 clock-names = "xusb_host", "xusb_host_src",
1030 "xusb_falcon_sr 946 "xusb_falcon_src", "xusb_ss",
1031 "xusb_ss_div2", 947 "xusb_ss_div2", "xusb_ss_src",
1032 "xusb_hs_src", 948 "xusb_hs_src", "xusb_fs_src",
1033 "pll_u_480m", " 949 "pll_u_480m", "clk_m", "pll_e";
1034 resets = <&tegra_car 89>, <&t 950 resets = <&tegra_car 89>, <&tegra_car 156>,
1035 <&tegra_car 143>; 951 <&tegra_car 143>;
1036 reset-names = "xusb_host", "x 952 reset-names = "xusb_host", "xusb_ss", "xusb_src";
1037 power-domains = <&pd_xusbhost 953 power-domains = <&pd_xusbhost>, <&pd_xusbss>;
1038 power-domain-names = "xusb_ho 954 power-domain-names = "xusb_host", "xusb_ss";
1039 955
1040 nvidia,xusb-padctl = <&padctl 956 nvidia,xusb-padctl = <&padctl>;
1041 957
1042 status = "disabled"; 958 status = "disabled";
1043 }; 959 };
1044 960
1045 padctl: padctl@7009f000 { 961 padctl: padctl@7009f000 {
1046 compatible = "nvidia,tegra210 962 compatible = "nvidia,tegra210-xusb-padctl";
1047 reg = <0x0 0x7009f000 0x0 0x1 963 reg = <0x0 0x7009f000 0x0 0x1000>;
1048 interrupts = <GIC_SPI 49 IRQ_ <<
1049 resets = <&tegra_car 142>; 964 resets = <&tegra_car 142>;
1050 reset-names = "padctl"; 965 reset-names = "padctl";
1051 nvidia,pmc = <&tegra_pmc>; <<
1052 966
1053 status = "disabled"; 967 status = "disabled";
1054 968
1055 pads { 969 pads {
1056 usb2 { 970 usb2 {
1057 clocks = <&te 971 clocks = <&tegra_car TEGRA210_CLK_USB2_TRK>;
1058 clock-names = 972 clock-names = "trk";
1059 status = "dis 973 status = "disabled";
1060 974
1061 lanes { 975 lanes {
1062 usb2- 976 usb2-0 {
1063 977 status = "disabled";
1064 978 #phy-cells = <0>;
1065 }; 979 };
1066 980
1067 usb2- 981 usb2-1 {
1068 982 status = "disabled";
1069 983 #phy-cells = <0>;
1070 }; 984 };
1071 985
1072 usb2- 986 usb2-2 {
1073 987 status = "disabled";
1074 988 #phy-cells = <0>;
1075 }; 989 };
1076 990
1077 usb2- 991 usb2-3 {
1078 992 status = "disabled";
1079 993 #phy-cells = <0>;
1080 }; 994 };
1081 }; 995 };
1082 }; 996 };
1083 997
1084 hsic { 998 hsic {
1085 clocks = <&te 999 clocks = <&tegra_car TEGRA210_CLK_HSIC_TRK>;
1086 clock-names = 1000 clock-names = "trk";
1087 status = "dis 1001 status = "disabled";
1088 1002
1089 lanes { 1003 lanes {
1090 hsic- 1004 hsic-0 {
1091 1005 status = "disabled";
1092 1006 #phy-cells = <0>;
1093 }; 1007 };
1094 1008
1095 hsic- 1009 hsic-1 {
1096 1010 status = "disabled";
1097 1011 #phy-cells = <0>;
1098 }; 1012 };
1099 }; 1013 };
1100 }; 1014 };
1101 1015
1102 pcie { 1016 pcie {
1103 clocks = <&te 1017 clocks = <&tegra_car TEGRA210_CLK_PLL_E>;
1104 clock-names = 1018 clock-names = "pll";
1105 resets = <&te 1019 resets = <&tegra_car 205>;
1106 reset-names = 1020 reset-names = "phy";
1107 status = "dis 1021 status = "disabled";
1108 1022
1109 lanes { 1023 lanes {
1110 pcie- 1024 pcie-0 {
1111 1025 status = "disabled";
1112 1026 #phy-cells = <0>;
1113 }; 1027 };
1114 1028
1115 pcie- 1029 pcie-1 {
1116 1030 status = "disabled";
1117 1031 #phy-cells = <0>;
1118 }; 1032 };
1119 1033
1120 pcie- 1034 pcie-2 {
1121 1035 status = "disabled";
1122 1036 #phy-cells = <0>;
1123 }; 1037 };
1124 1038
1125 pcie- 1039 pcie-3 {
1126 1040 status = "disabled";
1127 1041 #phy-cells = <0>;
1128 }; 1042 };
1129 1043
1130 pcie- 1044 pcie-4 {
1131 1045 status = "disabled";
1132 1046 #phy-cells = <0>;
1133 }; 1047 };
1134 1048
1135 pcie- 1049 pcie-5 {
1136 1050 status = "disabled";
1137 1051 #phy-cells = <0>;
1138 }; 1052 };
1139 1053
1140 pcie- 1054 pcie-6 {
1141 1055 status = "disabled";
1142 1056 #phy-cells = <0>;
1143 }; 1057 };
1144 }; 1058 };
1145 }; 1059 };
1146 1060
1147 sata { 1061 sata {
1148 clocks = <&te 1062 clocks = <&tegra_car TEGRA210_CLK_PLL_E>;
1149 clock-names = 1063 clock-names = "pll";
1150 resets = <&te 1064 resets = <&tegra_car 204>;
1151 reset-names = 1065 reset-names = "phy";
1152 status = "dis 1066 status = "disabled";
1153 1067
1154 lanes { 1068 lanes {
1155 sata- 1069 sata-0 {
1156 1070 status = "disabled";
1157 1071 #phy-cells = <0>;
1158 }; 1072 };
1159 }; 1073 };
1160 }; 1074 };
1161 }; 1075 };
1162 1076
1163 ports { 1077 ports {
1164 usb2-0 { 1078 usb2-0 {
1165 status = "dis 1079 status = "disabled";
1166 }; 1080 };
1167 1081
1168 usb2-1 { 1082 usb2-1 {
1169 status = "dis 1083 status = "disabled";
1170 }; 1084 };
1171 1085
1172 usb2-2 { 1086 usb2-2 {
1173 status = "dis 1087 status = "disabled";
1174 }; 1088 };
1175 1089
1176 usb2-3 { 1090 usb2-3 {
1177 status = "dis 1091 status = "disabled";
1178 }; 1092 };
1179 1093
1180 hsic-0 { 1094 hsic-0 {
1181 status = "dis 1095 status = "disabled";
1182 }; 1096 };
1183 1097
1184 usb3-0 { 1098 usb3-0 {
1185 status = "dis 1099 status = "disabled";
1186 }; 1100 };
1187 1101
1188 usb3-1 { 1102 usb3-1 {
1189 status = "dis 1103 status = "disabled";
1190 }; 1104 };
1191 1105
1192 usb3-2 { 1106 usb3-2 {
1193 status = "dis 1107 status = "disabled";
1194 }; 1108 };
1195 1109
1196 usb3-3 { 1110 usb3-3 {
1197 status = "dis 1111 status = "disabled";
1198 }; 1112 };
1199 }; 1113 };
1200 }; 1114 };
1201 1115
1202 mmc@700b0000 { !! 1116 sdhci@700b0000 {
1203 compatible = "nvidia,tegra210 !! 1117 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";
1204 reg = <0x0 0x700b0000 0x0 0x2 1118 reg = <0x0 0x700b0000 0x0 0x200>;
1205 interrupts = <GIC_SPI 14 IRQ_ 1119 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1206 clocks = <&tegra_car TEGRA210 1120 clocks = <&tegra_car TEGRA210_CLK_SDMMC1>,
1207 <&tegra_car TEGRA210 1121 <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>;
1208 clock-names = "sdhci", "tmclk 1122 clock-names = "sdhci", "tmclk";
1209 resets = <&tegra_car 14>; 1123 resets = <&tegra_car 14>;
1210 reset-names = "sdhci"; 1124 reset-names = "sdhci";
1211 pinctrl-names = "sdmmc-3v3", 1125 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8",
1212 "sdmmc-3v3-dr 1126 "sdmmc-3v3-drv", "sdmmc-1v8-drv";
1213 pinctrl-0 = <&sdmmc1_3v3>; 1127 pinctrl-0 = <&sdmmc1_3v3>;
1214 pinctrl-1 = <&sdmmc1_1v8>; 1128 pinctrl-1 = <&sdmmc1_1v8>;
1215 pinctrl-2 = <&sdmmc1_3v3_drv> 1129 pinctrl-2 = <&sdmmc1_3v3_drv>;
1216 pinctrl-3 = <&sdmmc1_1v8_drv> 1130 pinctrl-3 = <&sdmmc1_1v8_drv>;
1217 nvidia,pad-autocal-pull-up-of 1131 nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>;
1218 nvidia,pad-autocal-pull-down- 1132 nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>;
1219 nvidia,pad-autocal-pull-up-of 1133 nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>;
1220 nvidia,pad-autocal-pull-down- 1134 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>;
1221 nvidia,default-tap = <0x2>; 1135 nvidia,default-tap = <0x2>;
1222 nvidia,default-trim = <0x4>; 1136 nvidia,default-trim = <0x4>;
1223 assigned-clocks = <&tegra_car 1137 assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>,
1224 <&tegra_car 1138 <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>,
1225 <&tegra_car 1139 <&tegra_car TEGRA210_CLK_PLL_C4>;
1226 assigned-clock-parents = <&te 1140 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
1227 assigned-clock-rates = <20000 1141 assigned-clock-rates = <200000000>, <1000000000>, <1000000000>;
1228 status = "disabled"; 1142 status = "disabled";
1229 }; 1143 };
1230 1144
1231 mmc@700b0200 { !! 1145 sdhci@700b0200 {
1232 compatible = "nvidia,tegra210 !! 1146 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";
1233 reg = <0x0 0x700b0200 0x0 0x2 1147 reg = <0x0 0x700b0200 0x0 0x200>;
1234 interrupts = <GIC_SPI 15 IRQ_ 1148 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1235 clocks = <&tegra_car TEGRA210 1149 clocks = <&tegra_car TEGRA210_CLK_SDMMC2>,
1236 <&tegra_car TEGRA210 1150 <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>;
1237 clock-names = "sdhci", "tmclk 1151 clock-names = "sdhci", "tmclk";
1238 resets = <&tegra_car 9>; 1152 resets = <&tegra_car 9>;
1239 reset-names = "sdhci"; 1153 reset-names = "sdhci";
1240 pinctrl-names = "sdmmc-1v8-dr 1154 pinctrl-names = "sdmmc-1v8-drv";
1241 pinctrl-0 = <&sdmmc2_1v8_drv> 1155 pinctrl-0 = <&sdmmc2_1v8_drv>;
1242 nvidia,pad-autocal-pull-up-of 1156 nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>;
1243 nvidia,pad-autocal-pull-down- 1157 nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>;
1244 nvidia,default-tap = <0x8>; 1158 nvidia,default-tap = <0x8>;
1245 nvidia,default-trim = <0x0>; 1159 nvidia,default-trim = <0x0>;
1246 status = "disabled"; 1160 status = "disabled";
1247 }; 1161 };
1248 1162
1249 mmc@700b0400 { !! 1163 sdhci@700b0400 {
1250 compatible = "nvidia,tegra210 !! 1164 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";
1251 reg = <0x0 0x700b0400 0x0 0x2 1165 reg = <0x0 0x700b0400 0x0 0x200>;
1252 interrupts = <GIC_SPI 19 IRQ_ 1166 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1253 clocks = <&tegra_car TEGRA210 1167 clocks = <&tegra_car TEGRA210_CLK_SDMMC3>,
1254 <&tegra_car TEGRA210 1168 <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>;
1255 clock-names = "sdhci", "tmclk 1169 clock-names = "sdhci", "tmclk";
1256 resets = <&tegra_car 69>; 1170 resets = <&tegra_car 69>;
1257 reset-names = "sdhci"; 1171 reset-names = "sdhci";
1258 pinctrl-names = "sdmmc-3v3", 1172 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8",
1259 "sdmmc-3v3-dr 1173 "sdmmc-3v3-drv", "sdmmc-1v8-drv";
1260 pinctrl-0 = <&sdmmc3_3v3>; 1174 pinctrl-0 = <&sdmmc3_3v3>;
1261 pinctrl-1 = <&sdmmc3_1v8>; 1175 pinctrl-1 = <&sdmmc3_1v8>;
1262 pinctrl-2 = <&sdmmc3_3v3_drv> 1176 pinctrl-2 = <&sdmmc3_3v3_drv>;
1263 pinctrl-3 = <&sdmmc3_1v8_drv> 1177 pinctrl-3 = <&sdmmc3_1v8_drv>;
1264 nvidia,pad-autocal-pull-up-of 1178 nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>;
1265 nvidia,pad-autocal-pull-down- 1179 nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>;
1266 nvidia,pad-autocal-pull-up-of 1180 nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>;
1267 nvidia,pad-autocal-pull-down- 1181 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>;
1268 nvidia,default-tap = <0x3>; 1182 nvidia,default-tap = <0x3>;
1269 nvidia,default-trim = <0x3>; 1183 nvidia,default-trim = <0x3>;
1270 status = "disabled"; 1184 status = "disabled";
1271 }; 1185 };
1272 1186
1273 mmc@700b0600 { !! 1187 sdhci@700b0600 {
1274 compatible = "nvidia,tegra210 !! 1188 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";
1275 reg = <0x0 0x700b0600 0x0 0x2 1189 reg = <0x0 0x700b0600 0x0 0x200>;
1276 interrupts = <GIC_SPI 31 IRQ_ 1190 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
1277 clocks = <&tegra_car TEGRA210 1191 clocks = <&tegra_car TEGRA210_CLK_SDMMC4>,
1278 <&tegra_car TEGRA210 1192 <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>;
1279 clock-names = "sdhci", "tmclk 1193 clock-names = "sdhci", "tmclk";
1280 resets = <&tegra_car 15>; 1194 resets = <&tegra_car 15>;
1281 reset-names = "sdhci"; 1195 reset-names = "sdhci";
1282 pinctrl-names = "sdmmc-3v3-dr 1196 pinctrl-names = "sdmmc-3v3-drv", "sdmmc-1v8-drv";
1283 pinctrl-0 = <&sdmmc4_1v8_drv> 1197 pinctrl-0 = <&sdmmc4_1v8_drv>;
1284 pinctrl-1 = <&sdmmc4_1v8_drv> 1198 pinctrl-1 = <&sdmmc4_1v8_drv>;
1285 nvidia,pad-autocal-pull-up-of 1199 nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>;
1286 nvidia,pad-autocal-pull-down- 1200 nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>;
1287 nvidia,default-tap = <0x8>; 1201 nvidia,default-tap = <0x8>;
1288 nvidia,default-trim = <0x0>; 1202 nvidia,default-trim = <0x0>;
1289 assigned-clocks = <&tegra_car 1203 assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>,
1290 <&tegra_car 1204 <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
1291 assigned-clock-parents = <&te 1205 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
1292 nvidia,dqs-trim = <40>; 1206 nvidia,dqs-trim = <40>;
1293 mmc-hs400-1_8v; 1207 mmc-hs400-1_8v;
1294 status = "disabled"; 1208 status = "disabled";
1295 }; 1209 };
1296 1210
1297 usb@700d0000 { <<
1298 compatible = "nvidia,tegra210 <<
1299 reg = <0x0 0x700d0000 0x0 0x8 <<
1300 <0x0 0x700d8000 0x0 0x1 <<
1301 <0x0 0x700d9000 0x0 0x1 <<
1302 reg-names = "base", "fpci", " <<
1303 interrupts = <GIC_SPI 44 IRQ_ <<
1304 clocks = <&tegra_car TEGRA210 <<
1305 <&tegra_car TEGRA210 <<
1306 <&tegra_car TEGRA210 <<
1307 <&tegra_car TEGRA210 <<
1308 <&tegra_car TEGRA210 <<
1309 clock-names = "dev", "ss", "s <<
1310 power-domains = <&pd_xusbdev> <<
1311 power-domain-names = "dev", " <<
1312 nvidia,xusb-padctl = <&padctl <<
1313 status = "disabled"; <<
1314 }; <<
1315 <<
1316 soctherm: thermal-sensor@700e2000 { <<
1317 compatible = "nvidia,tegra210 <<
1318 reg = <0x0 0x700e2000 0x0 0x6 <<
1319 <0x0 0x60006000 0x0 0x4 <<
1320 reg-names = "soctherm-reg", " <<
1321 interrupts = <GIC_SPI 48 IRQ_ <<
1322 <GIC_SPI 51 IRQ_ <<
1323 interrupt-names = "thermal", <<
1324 clocks = <&tegra_car TEGRA210 <<
1325 <&tegra_car TEGRA210_ <<
1326 clock-names = "tsensor", "soc <<
1327 resets = <&tegra_car 78>; <<
1328 reset-names = "soctherm"; <<
1329 #thermal-sensor-cells = <1>; <<
1330 <<
1331 throttle-cfgs { <<
1332 throttle_heavy: heavy <<
1333 nvidia,priori <<
1334 nvidia,cpu-th <<
1335 nvidia,gpu-th <<
1336 <<
1337 #cooling-cell <<
1338 }; <<
1339 }; <<
1340 }; <<
1341 <<
1342 mipi: mipi@700e3000 { 1211 mipi: mipi@700e3000 {
1343 compatible = "nvidia,tegra210 1212 compatible = "nvidia,tegra210-mipi";
1344 reg = <0x0 0x700e3000 0x0 0x1 1213 reg = <0x0 0x700e3000 0x0 0x100>;
1345 clocks = <&tegra_car TEGRA210 1214 clocks = <&tegra_car TEGRA210_CLK_MIPI_CAL>;
1346 clock-names = "mipi-cal"; 1215 clock-names = "mipi-cal";
1347 power-domains = <&pd_sor>; 1216 power-domains = <&pd_sor>;
1348 #nvidia,mipi-calibrate-cells 1217 #nvidia,mipi-calibrate-cells = <1>;
1349 }; 1218 };
1350 1219
1351 dfll: clock@70110000 { 1220 dfll: clock@70110000 {
1352 compatible = "nvidia,tegra210 1221 compatible = "nvidia,tegra210-dfll";
1353 reg = <0 0x70110000 0 0x100>, 1222 reg = <0 0x70110000 0 0x100>, /* DFLL control */
1354 <0 0x70110000 0 0x100>, 1223 <0 0x70110000 0 0x100>, /* I2C output control */
1355 <0 0x70110100 0 0x100>, 1224 <0 0x70110100 0 0x100>, /* Integrated I2C controller */
1356 <0 0x70110200 0 0x100>; 1225 <0 0x70110200 0 0x100>; /* Look-up table RAM */
1357 interrupts = <GIC_SPI 62 IRQ_ 1226 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
1358 clocks = <&tegra_car TEGRA210 1227 clocks = <&tegra_car TEGRA210_CLK_DFLL_SOC>,
1359 <&tegra_car TEGRA210 1228 <&tegra_car TEGRA210_CLK_DFLL_REF>,
1360 <&tegra_car TEGRA210 1229 <&tegra_car TEGRA210_CLK_I2C5>;
1361 clock-names = "soc", "ref", " 1230 clock-names = "soc", "ref", "i2c";
1362 resets = <&tegra_car TEGRA210 !! 1231 resets = <&tegra_car TEGRA210_RST_DFLL_DVCO>;
1363 <&tegra_car 155>; !! 1232 reset-names = "dvco";
1364 reset-names = "dvco", "dfll"; <<
1365 #clock-cells = <0>; 1233 #clock-cells = <0>;
1366 clock-output-names = "dfllCPU 1234 clock-output-names = "dfllCPU_out";
1367 status = "disabled"; 1235 status = "disabled";
1368 }; 1236 };
1369 1237
1370 aconnect@702c0000 { 1238 aconnect@702c0000 {
1371 compatible = "nvidia,tegra210 1239 compatible = "nvidia,tegra210-aconnect";
1372 clocks = <&tegra_car TEGRA210 1240 clocks = <&tegra_car TEGRA210_CLK_APE>,
1373 <&tegra_car TEGRA210 1241 <&tegra_car TEGRA210_CLK_APB2APE>;
1374 clock-names = "ape", "apb2ape 1242 clock-names = "ape", "apb2ape";
1375 power-domains = <&pd_audio>; 1243 power-domains = <&pd_audio>;
1376 #address-cells = <1>; 1244 #address-cells = <1>;
1377 #size-cells = <1>; 1245 #size-cells = <1>;
1378 ranges = <0x702c0000 0x0 0x70 1246 ranges = <0x702c0000 0x0 0x702c0000 0x00040000>;
1379 status = "disabled"; 1247 status = "disabled";
1380 1248
1381 tegra_ahub: ahub@702d0800 { !! 1249 adma: dma@702e2000 {
1382 compatible = "nvidia, <<
1383 reg = <0x702d0800 0x8 <<
1384 clocks = <&tegra_car <<
1385 clock-names = "ahub"; <<
1386 assigned-clocks = <&t <<
1387 assigned-clock-parent <<
1388 assigned-clock-rates <<
1389 #address-cells = <1>; <<
1390 #size-cells = <1>; <<
1391 ranges = <0x702d0000 <<
1392 status = "disabled"; <<
1393 <<
1394 tegra_admaif: admaif@ <<
1395 compatible = <<
1396 reg = <0x702d <<
1397 dmas = <&adma <<
1398 <&adma <<
1399 <&adma <<
1400 <&adma <<
1401 <&adma <<
1402 <&adma <<
1403 <&adma <<
1404 <&adma <<
1405 <&adma <<
1406 <&adma <<
1407 dma-names = " <<
1408 " <<
1409 " <<
1410 " <<
1411 " <<
1412 " <<
1413 " <<
1414 " <<
1415 " <<
1416 " <<
1417 status = "dis <<
1418 <<
1419 ports { <<
1420 #addr <<
1421 #size <<
1422 <<
1423 admai <<
1424 <<
1425 <<
1426 <<
1427 <<
1428 <<
1429 }; <<
1430 <<
1431 admai <<
1432 <<
1433 <<
1434 <<
1435 <<
1436 <<
1437 }; <<
1438 <<
1439 admai <<
1440 <<
1441 <<
1442 <<
1443 <<
1444 <<
1445 }; <<
1446 <<
1447 admai <<
1448 <<
1449 <<
1450 <<
1451 <<
1452 <<
1453 }; <<
1454 <<
1455 admai <<
1456 <<
1457 <<
1458 <<
1459 <<
1460 <<
1461 }; <<
1462 <<
1463 admai <<
1464 <<
1465 <<
1466 <<
1467 <<
1468 <<
1469 }; <<
1470 <<
1471 admai <<
1472 <<
1473 <<
1474 <<
1475 <<
1476 <<
1477 }; <<
1478 <<
1479 admai <<
1480 <<
1481 <<
1482 <<
1483 <<
1484 <<
1485 }; <<
1486 <<
1487 admai <<
1488 <<
1489 <<
1490 <<
1491 <<
1492 <<
1493 }; <<
1494 <<
1495 admai <<
1496 <<
1497 <<
1498 <<
1499 <<
1500 <<
1501 }; <<
1502 }; <<
1503 }; <<
1504 <<
1505 tegra_i2s1: i2s@702d1 <<
1506 compatible = <<
1507 reg = <0x702d <<
1508 clocks = <&te <<
1509 <&te <<
1510 clock-names = <<
1511 assigned-cloc <<
1512 assigned-cloc <<
1513 assigned-cloc <<
1514 sound-name-pr <<
1515 status = "dis <<
1516 }; <<
1517 <<
1518 tegra_i2s2: i2s@702d1 <<
1519 compatible = <<
1520 reg = <0x702d <<
1521 clocks = <&te <<
1522 <&te <<
1523 clock-names = <<
1524 assigned-cloc <<
1525 assigned-cloc <<
1526 assigned-cloc <<
1527 sound-name-pr <<
1528 status = "dis <<
1529 }; <<
1530 <<
1531 tegra_i2s3: i2s@702d1 <<
1532 compatible = <<
1533 reg = <0x702d <<
1534 clocks = <&te <<
1535 <&te <<
1536 clock-names = <<
1537 assigned-cloc <<
1538 assigned-cloc <<
1539 assigned-cloc <<
1540 sound-name-pr <<
1541 status = "dis <<
1542 }; <<
1543 <<
1544 tegra_i2s4: i2s@702d1 <<
1545 compatible = <<
1546 reg = <0x702d <<
1547 clocks = <&te <<
1548 <&te <<
1549 clock-names = <<
1550 assigned-cloc <<
1551 assigned-cloc <<
1552 assigned-cloc <<
1553 sound-name-pr <<
1554 status = "dis <<
1555 }; <<
1556 <<
1557 tegra_i2s5: i2s@702d1 <<
1558 compatible = <<
1559 reg = <0x702d <<
1560 clocks = <&te <<
1561 <&te <<
1562 clock-names = <<
1563 assigned-cloc <<
1564 assigned-cloc <<
1565 assigned-cloc <<
1566 sound-name-pr <<
1567 status = "dis <<
1568 }; <<
1569 <<
1570 tegra_sfc1: sfc@702d2 <<
1571 compatible = <<
1572 reg = <0x702d <<
1573 sound-name-pr <<
1574 status = "dis <<
1575 }; <<
1576 <<
1577 tegra_sfc2: sfc@702d2 <<
1578 compatible = <<
1579 reg = <0x702d <<
1580 sound-name-pr <<
1581 status = "dis <<
1582 }; <<
1583 <<
1584 tegra_sfc3: sfc@702d2 <<
1585 compatible = <<
1586 reg = <0x702d <<
1587 sound-name-pr <<
1588 status = "dis <<
1589 }; <<
1590 <<
1591 tegra_sfc4: sfc@702d2 <<
1592 compatible = <<
1593 reg = <0x702d <<
1594 sound-name-pr <<
1595 status = "dis <<
1596 }; <<
1597 <<
1598 tegra_amx1: amx@702d3 <<
1599 compatible = <<
1600 reg = <0x702d <<
1601 sound-name-pr <<
1602 status = "dis <<
1603 }; <<
1604 <<
1605 tegra_amx2: amx@702d3 <<
1606 compatible = <<
1607 reg = <0x702d <<
1608 sound-name-pr <<
1609 status = "dis <<
1610 }; <<
1611 <<
1612 tegra_adx1: adx@702d3 <<
1613 compatible = <<
1614 reg = <0x702d <<
1615 sound-name-pr <<
1616 status = "dis <<
1617 }; <<
1618 <<
1619 tegra_adx2: adx@702d3 <<
1620 compatible = <<
1621 reg = <0x702d <<
1622 sound-name-pr <<
1623 status = "dis <<
1624 }; <<
1625 <<
1626 tegra_dmic1: dmic@702 <<
1627 compatible = <<
1628 reg = <0x702d <<
1629 clocks = <&te <<
1630 clock-names = <<
1631 assigned-cloc <<
1632 assigned-cloc <<
1633 assigned-cloc <<
1634 sound-name-pr <<
1635 status = "dis <<
1636 }; <<
1637 <<
1638 tegra_dmic2: dmic@702 <<
1639 compatible = <<
1640 reg = <0x702d <<
1641 clocks = <&te <<
1642 clock-names = <<
1643 assigned-cloc <<
1644 assigned-cloc <<
1645 assigned-cloc <<
1646 sound-name-pr <<
1647 status = "dis <<
1648 }; <<
1649 <<
1650 tegra_dmic3: dmic@702 <<
1651 compatible = <<
1652 reg = <0x702d <<
1653 clocks = <&te <<
1654 clock-names = <<
1655 assigned-cloc <<
1656 assigned-cloc <<
1657 assigned-cloc <<
1658 sound-name-pr <<
1659 status = "dis <<
1660 }; <<
1661 <<
1662 tegra_ope1: processin <<
1663 compatible = <<
1664 reg = <0x702d <<
1665 #address-cell <<
1666 #size-cells = <<
1667 ranges; <<
1668 sound-name-pr <<
1669 status = "dis <<
1670 <<
1671 equalizer@702 <<
1672 compa <<
1673 reg = <<
1674 }; <<
1675 <<
1676 dynamic-range <<
1677 compa <<
1678 reg = <<
1679 }; <<
1680 }; <<
1681 <<
1682 tegra_ope2: processin <<
1683 compatible = <<
1684 reg = <0x702d <<
1685 #address-cell <<
1686 #size-cells = <<
1687 ranges; <<
1688 sound-name-pr <<
1689 status = "dis <<
1690 <<
1691 equalizer@702 <<
1692 compa <<
1693 reg = <<
1694 }; <<
1695 <<
1696 dynamic-range <<
1697 compa <<
1698 reg = <<
1699 }; <<
1700 }; <<
1701 <<
1702 tegra_mvc1: mvc@702da <<
1703 compatible = <<
1704 reg = <0x702d <<
1705 sound-name-pr <<
1706 status = "dis <<
1707 }; <<
1708 <<
1709 tegra_mvc2: mvc@702da <<
1710 compatible = <<
1711 reg = <0x702d <<
1712 sound-name-pr <<
1713 status = "dis <<
1714 }; <<
1715 <<
1716 tegra_amixer: amixer@ <<
1717 compatible = <<
1718 reg = <0x702d <<
1719 sound-name-pr <<
1720 status = "dis <<
1721 }; <<
1722 <<
1723 ports { <<
1724 #address-cell <<
1725 #size-cells = <<
1726 <<
1727 port@0 { <<
1728 reg = <<
1729 <<
1730 xbar_ <<
1731 <<
1732 }; <<
1733 }; <<
1734 <<
1735 port@1 { <<
1736 reg = <<
1737 <<
1738 xbar_ <<
1739 <<
1740 }; <<
1741 }; <<
1742 <<
1743 port@2 { <<
1744 reg = <<
1745 <<
1746 xbar_ <<
1747 <<
1748 }; <<
1749 }; <<
1750 <<
1751 port@3 { <<
1752 reg = <<
1753 <<
1754 xbar_ <<
1755 <<
1756 }; <<
1757 }; <<
1758 <<
1759 port@4 { <<
1760 reg = <<
1761 xbar_ <<
1762 <<
1763 }; <<
1764 }; <<
1765 port@5 { <<
1766 reg = <<
1767 <<
1768 xbar_ <<
1769 <<
1770 }; <<
1771 }; <<
1772 <<
1773 port@6 { <<
1774 reg = <<
1775 <<
1776 xbar_ <<
1777 <<
1778 }; <<
1779 }; <<
1780 <<
1781 port@7 { <<
1782 reg = <<
1783 <<
1784 xbar_ <<
1785 <<
1786 }; <<
1787 }; <<
1788 <<
1789 port@8 { <<
1790 reg = <<
1791 <<
1792 xbar_ <<
1793 <<
1794 }; <<
1795 }; <<
1796 <<
1797 port@9 { <<
1798 reg = <<
1799 <<
1800 xbar_ <<
1801 <<
1802 }; <<
1803 }; <<
1804 }; <<
1805 }; <<
1806 <<
1807 adma: dma-controller@702e2000 <<
1808 compatible = "nvidia, 1250 compatible = "nvidia,tegra210-adma";
1809 reg = <0x702e2000 0x2 1251 reg = <0x702e2000 0x2000>;
1810 interrupt-parent = <& 1252 interrupt-parent = <&agic>;
1811 interrupts = <GIC_SPI 1253 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
1812 <GIC_SPI 1254 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
1813 <GIC_SPI 1255 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
1814 <GIC_SPI 1256 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
1815 <GIC_SPI 1257 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
1816 <GIC_SPI 1258 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
1817 <GIC_SPI 1259 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
1818 <GIC_SPI 1260 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
1819 <GIC_SPI 1261 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
1820 <GIC_SPI 1262 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
1821 <GIC_SPI 1263 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
1822 <GIC_SPI 1264 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
1823 <GIC_SPI 1265 <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
1824 <GIC_SPI 1266 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
1825 <GIC_SPI 1267 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
1826 <GIC_SPI 1268 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
1827 <GIC_SPI 1269 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
1828 <GIC_SPI 1270 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
1829 <GIC_SPI 1271 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
1830 <GIC_SPI 1272 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
1831 <GIC_SPI 1273 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
1832 <GIC_SPI 1274 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1833 #dma-cells = <1>; 1275 #dma-cells = <1>;
1834 clocks = <&tegra_car 1276 clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>;
1835 clock-names = "d_audi 1277 clock-names = "d_audio";
1836 status = "disabled"; 1278 status = "disabled";
1837 }; 1279 };
1838 1280
1839 agic: interrupt-controller@70 !! 1281 agic: agic@702f9000 {
1840 compatible = "nvidia, 1282 compatible = "nvidia,tegra210-agic";
1841 #interrupt-cells = <3 1283 #interrupt-cells = <3>;
1842 interrupt-controller; 1284 interrupt-controller;
1843 reg = <0x702f9000 0x1 1285 reg = <0x702f9000 0x1000>,
1844 <0x702fa000 0x2 1286 <0x702fa000 0x2000>;
1845 interrupts = <GIC_SPI 1287 interrupts = <GIC_SPI 102 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1846 clocks = <&tegra_car 1288 clocks = <&tegra_car TEGRA210_CLK_APE>;
1847 clock-names = "clk"; 1289 clock-names = "clk";
1848 status = "disabled"; 1290 status = "disabled";
1849 }; 1291 };
1850 }; 1292 };
1851 1293
1852 spi@70410000 { 1294 spi@70410000 {
1853 compatible = "nvidia,tegra210 1295 compatible = "nvidia,tegra210-qspi";
1854 reg = <0x0 0x70410000 0x0 0x1 1296 reg = <0x0 0x70410000 0x0 0x1000>;
1855 interrupts = <GIC_SPI 10 IRQ_ 1297 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1856 #address-cells = <1>; 1298 #address-cells = <1>;
1857 #size-cells = <0>; 1299 #size-cells = <0>;
1858 clocks = <&tegra_car TEGRA210 !! 1300 clocks = <&tegra_car TEGRA210_CLK_QSPI>;
1859 <&tegra_car TEGRA210 !! 1301 clock-names = "qspi";
1860 clock-names = "qspi", "qspi_o <<
1861 resets = <&tegra_car 211>; 1302 resets = <&tegra_car 211>;
>> 1303 reset-names = "qspi";
1862 dmas = <&apbdma 5>, <&apbdma 1304 dmas = <&apbdma 5>, <&apbdma 5>;
1863 dma-names = "rx", "tx"; 1305 dma-names = "rx", "tx";
1864 status = "disabled"; 1306 status = "disabled";
1865 }; 1307 };
1866 1308
1867 usb@7d000000 { 1309 usb@7d000000 {
1868 compatible = "nvidia,tegra210 !! 1310 compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci";
1869 reg = <0x0 0x7d000000 0x0 0x4 1311 reg = <0x0 0x7d000000 0x0 0x4000>;
1870 interrupts = <GIC_SPI 20 IRQ_ 1312 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1871 phy_type = "utmi"; 1313 phy_type = "utmi";
1872 clocks = <&tegra_car TEGRA210 1314 clocks = <&tegra_car TEGRA210_CLK_USBD>;
1873 clock-names = "usb"; 1315 clock-names = "usb";
1874 resets = <&tegra_car 22>; 1316 resets = <&tegra_car 22>;
1875 reset-names = "usb"; 1317 reset-names = "usb";
1876 nvidia,phy = <&phy1>; 1318 nvidia,phy = <&phy1>;
1877 status = "disabled"; 1319 status = "disabled";
1878 }; 1320 };
1879 1321
1880 phy1: usb-phy@7d000000 { 1322 phy1: usb-phy@7d000000 {
1881 compatible = "nvidia,tegra210 1323 compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy";
1882 reg = <0x0 0x7d000000 0x0 0x4 1324 reg = <0x0 0x7d000000 0x0 0x4000>,
1883 <0x0 0x7d000000 0x0 0x4 1325 <0x0 0x7d000000 0x0 0x4000>;
1884 phy_type = "utmi"; 1326 phy_type = "utmi";
1885 clocks = <&tegra_car TEGRA210 1327 clocks = <&tegra_car TEGRA210_CLK_USBD>,
1886 <&tegra_car TEGRA210 1328 <&tegra_car TEGRA210_CLK_PLL_U>,
1887 <&tegra_car TEGRA210 1329 <&tegra_car TEGRA210_CLK_USBD>;
1888 clock-names = "reg", "pll_u", 1330 clock-names = "reg", "pll_u", "utmi-pads";
1889 resets = <&tegra_car 22>, <&t 1331 resets = <&tegra_car 22>, <&tegra_car 22>;
1890 reset-names = "usb", "utmi-pa 1332 reset-names = "usb", "utmi-pads";
1891 nvidia,hssync-start-delay = < 1333 nvidia,hssync-start-delay = <0>;
1892 nvidia,idle-wait-delay = <17> 1334 nvidia,idle-wait-delay = <17>;
1893 nvidia,elastic-limit = <16>; 1335 nvidia,elastic-limit = <16>;
1894 nvidia,term-range-adj = <6>; 1336 nvidia,term-range-adj = <6>;
1895 nvidia,xcvr-setup = <9>; 1337 nvidia,xcvr-setup = <9>;
1896 nvidia,xcvr-lsfslew = <0>; 1338 nvidia,xcvr-lsfslew = <0>;
1897 nvidia,xcvr-lsrslew = <3>; 1339 nvidia,xcvr-lsrslew = <3>;
1898 nvidia,hssquelch-level = <2>; 1340 nvidia,hssquelch-level = <2>;
1899 nvidia,hsdiscon-level = <5>; 1341 nvidia,hsdiscon-level = <5>;
1900 nvidia,xcvr-hsslew = <12>; 1342 nvidia,xcvr-hsslew = <12>;
1901 nvidia,has-utmi-pad-registers 1343 nvidia,has-utmi-pad-registers;
1902 status = "disabled"; 1344 status = "disabled";
1903 }; 1345 };
1904 1346
1905 usb@7d004000 { 1347 usb@7d004000 {
1906 compatible = "nvidia,tegra210 !! 1348 compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci";
1907 reg = <0x0 0x7d004000 0x0 0x4 1349 reg = <0x0 0x7d004000 0x0 0x4000>;
1908 interrupts = <GIC_SPI 21 IRQ_ 1350 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
1909 phy_type = "utmi"; 1351 phy_type = "utmi";
1910 clocks = <&tegra_car TEGRA210 1352 clocks = <&tegra_car TEGRA210_CLK_USB2>;
1911 clock-names = "usb"; 1353 clock-names = "usb";
1912 resets = <&tegra_car 58>; 1354 resets = <&tegra_car 58>;
1913 reset-names = "usb"; 1355 reset-names = "usb";
1914 nvidia,phy = <&phy2>; 1356 nvidia,phy = <&phy2>;
1915 status = "disabled"; 1357 status = "disabled";
1916 }; 1358 };
1917 1359
1918 phy2: usb-phy@7d004000 { 1360 phy2: usb-phy@7d004000 {
1919 compatible = "nvidia,tegra210 1361 compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy";
1920 reg = <0x0 0x7d004000 0x0 0x4 1362 reg = <0x0 0x7d004000 0x0 0x4000>,
1921 <0x0 0x7d000000 0x0 0x4 1363 <0x0 0x7d000000 0x0 0x4000>;
1922 phy_type = "utmi"; 1364 phy_type = "utmi";
1923 clocks = <&tegra_car TEGRA210 1365 clocks = <&tegra_car TEGRA210_CLK_USB2>,
1924 <&tegra_car TEGRA210 1366 <&tegra_car TEGRA210_CLK_PLL_U>,
1925 <&tegra_car TEGRA210 1367 <&tegra_car TEGRA210_CLK_USBD>;
1926 clock-names = "reg", "pll_u", 1368 clock-names = "reg", "pll_u", "utmi-pads";
1927 resets = <&tegra_car 58>, <&t 1369 resets = <&tegra_car 58>, <&tegra_car 22>;
1928 reset-names = "usb", "utmi-pa 1370 reset-names = "usb", "utmi-pads";
1929 nvidia,hssync-start-delay = < 1371 nvidia,hssync-start-delay = <0>;
1930 nvidia,idle-wait-delay = <17> 1372 nvidia,idle-wait-delay = <17>;
1931 nvidia,elastic-limit = <16>; 1373 nvidia,elastic-limit = <16>;
1932 nvidia,term-range-adj = <6>; 1374 nvidia,term-range-adj = <6>;
1933 nvidia,xcvr-setup = <9>; 1375 nvidia,xcvr-setup = <9>;
1934 nvidia,xcvr-lsfslew = <0>; 1376 nvidia,xcvr-lsfslew = <0>;
1935 nvidia,xcvr-lsrslew = <3>; 1377 nvidia,xcvr-lsrslew = <3>;
1936 nvidia,hssquelch-level = <2>; 1378 nvidia,hssquelch-level = <2>;
1937 nvidia,hsdiscon-level = <5>; 1379 nvidia,hsdiscon-level = <5>;
1938 nvidia,xcvr-hsslew = <12>; 1380 nvidia,xcvr-hsslew = <12>;
1939 status = "disabled"; 1381 status = "disabled";
1940 }; 1382 };
1941 1383
1942 cpus { 1384 cpus {
1943 #address-cells = <1>; 1385 #address-cells = <1>;
1944 #size-cells = <0>; 1386 #size-cells = <0>;
1945 1387
1946 cpu@0 { 1388 cpu@0 {
1947 device_type = "cpu"; 1389 device_type = "cpu";
1948 compatible = "arm,cor 1390 compatible = "arm,cortex-a57";
1949 reg = <0>; 1391 reg = <0>;
1950 clocks = <&tegra_car 1392 clocks = <&tegra_car TEGRA210_CLK_CCLK_G>,
1951 <&tegra_car 1393 <&tegra_car TEGRA210_CLK_PLL_X>,
1952 <&tegra_car 1394 <&tegra_car TEGRA210_CLK_PLL_P_OUT4>,
1953 <&dfll>; 1395 <&dfll>;
1954 clock-names = "cpu_g" 1396 clock-names = "cpu_g", "pll_x", "pll_p", "dfll";
1955 clock-latency = <3000 1397 clock-latency = <300000>;
1956 cpu-idle-states = <&C 1398 cpu-idle-states = <&CPU_SLEEP>;
1957 next-level-cache = <& 1399 next-level-cache = <&L2>;
1958 }; 1400 };
1959 1401
1960 cpu@1 { 1402 cpu@1 {
1961 device_type = "cpu"; 1403 device_type = "cpu";
1962 compatible = "arm,cor 1404 compatible = "arm,cortex-a57";
1963 reg = <1>; 1405 reg = <1>;
1964 cpu-idle-states = <&C 1406 cpu-idle-states = <&CPU_SLEEP>;
1965 next-level-cache = <& 1407 next-level-cache = <&L2>;
1966 }; 1408 };
1967 1409
1968 cpu@2 { 1410 cpu@2 {
1969 device_type = "cpu"; 1411 device_type = "cpu";
1970 compatible = "arm,cor 1412 compatible = "arm,cortex-a57";
1971 reg = <2>; 1413 reg = <2>;
1972 cpu-idle-states = <&C 1414 cpu-idle-states = <&CPU_SLEEP>;
1973 next-level-cache = <& 1415 next-level-cache = <&L2>;
1974 }; 1416 };
1975 1417
1976 cpu@3 { 1418 cpu@3 {
1977 device_type = "cpu"; 1419 device_type = "cpu";
1978 compatible = "arm,cor 1420 compatible = "arm,cortex-a57";
1979 reg = <3>; 1421 reg = <3>;
1980 cpu-idle-states = <&C 1422 cpu-idle-states = <&CPU_SLEEP>;
1981 next-level-cache = <& 1423 next-level-cache = <&L2>;
1982 }; 1424 };
1983 1425
1984 idle-states { 1426 idle-states {
1985 entry-method = "psci" 1427 entry-method = "psci";
1986 1428
1987 CPU_SLEEP: cpu-sleep 1429 CPU_SLEEP: cpu-sleep {
1988 compatible = 1430 compatible = "arm,idle-state";
1989 arm,psci-susp 1431 arm,psci-suspend-param = <0x40000007>;
1990 entry-latency 1432 entry-latency-us = <100>;
1991 exit-latency- 1433 exit-latency-us = <30>;
1992 min-residency 1434 min-residency-us = <1000>;
1993 wakeup-latenc 1435 wakeup-latency-us = <130>;
1994 idle-state-na 1436 idle-state-name = "cpu-sleep";
1995 status = "dis 1437 status = "disabled";
1996 }; 1438 };
1997 }; 1439 };
1998 1440
1999 L2: l2-cache { 1441 L2: l2-cache {
2000 compatible = "cache"; 1442 compatible = "cache";
2001 cache-level = <2>; <<
2002 cache-unified; <<
2003 }; 1443 };
2004 }; 1444 };
2005 1445
2006 pmu { !! 1446 timer {
2007 compatible = "arm,cortex-a57- !! 1447 compatible = "arm,armv8-timer";
2008 interrupts = <GIC_SPI 144 IRQ !! 1448 interrupts = <GIC_PPI 13
2009 <GIC_SPI 145 IRQ !! 1449 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2010 <GIC_SPI 146 IRQ !! 1450 <GIC_PPI 14
2011 <GIC_SPI 147 IRQ !! 1451 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2012 interrupt-affinity = <&{/cpus !! 1452 <GIC_PPI 11
2013 &{/cpus !! 1453 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
>> 1454 <GIC_PPI 10
>> 1455 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
>> 1456 interrupt-parent = <&gic>;
>> 1457 arm,no-tick-in-suspend;
2014 }; 1458 };
2015 1459
2016 sound { !! 1460 soctherm: thermal-sensor@700e2000 {
2017 status = "disabled"; !! 1461 compatible = "nvidia,tegra210-soctherm";
>> 1462 reg = <0x0 0x700e2000 0x0 0x600 /* SOC_THERM reg_base */
>> 1463 0x0 0x60006000 0x0 0x400>; /* CAR reg_base */
>> 1464 reg-names = "soctherm-reg", "car-reg";
>> 1465 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
>> 1466 clocks = <&tegra_car TEGRA210_CLK_TSENSOR>,
>> 1467 <&tegra_car TEGRA210_CLK_SOC_THERM>;
>> 1468 clock-names = "tsensor", "soctherm";
>> 1469 resets = <&tegra_car 78>;
>> 1470 reset-names = "soctherm";
>> 1471 #thermal-sensor-cells = <1>;
2018 1472
2019 clocks = <&tegra_car TEGRA210 !! 1473 throttle-cfgs {
2020 <&tegra_car TEGRA210 !! 1474 throttle_heavy: heavy {
2021 clock-names = "pll_a", "plla_ !! 1475 nvidia,priority = <100>;
>> 1476 nvidia,cpu-throt-percent = <85>;
2022 1477
2023 assigned-clocks = <&tegra_car !! 1478 #cooling-cells = <2>;
2024 <&tegra_car !! 1479 };
2025 <&tegra_car !! 1480 };
2026 assigned-clock-parents = <0>, <<
2027 assigned-clock-rates = <36864 <<
2028 }; 1481 };
2029 1482
2030 thermal-zones { 1483 thermal-zones {
2031 cpu-thermal { !! 1484 cpu {
2032 polling-delay-passive 1485 polling-delay-passive = <1000>;
2033 polling-delay = <0>; 1486 polling-delay = <0>;
2034 1487
2035 thermal-sensors = 1488 thermal-sensors =
2036 <&soctherm TE 1489 <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>;
2037 1490
2038 trips { 1491 trips {
2039 cpu-shutdown- 1492 cpu-shutdown-trip {
2040 tempe 1493 temperature = <102500>;
2041 hyste 1494 hysteresis = <0>;
2042 type 1495 type = "critical";
2043 }; 1496 };
2044 1497
2045 cpu_throttle_ 1498 cpu_throttle_trip: throttle-trip {
2046 tempe 1499 temperature = <98500>;
2047 hyste 1500 hysteresis = <1000>;
2048 type 1501 type = "hot";
2049 }; 1502 };
2050 }; 1503 };
2051 1504
2052 cooling-maps { 1505 cooling-maps {
2053 map0 { 1506 map0 {
2054 trip 1507 trip = <&cpu_throttle_trip>;
2055 cooli 1508 cooling-device = <&throttle_heavy 1 1>;
2056 }; 1509 };
2057 }; 1510 };
2058 }; 1511 };
2059 !! 1512 mem {
2060 mem-thermal { <<
2061 polling-delay-passive 1513 polling-delay-passive = <0>;
2062 polling-delay = <0>; 1514 polling-delay = <0>;
2063 1515
2064 thermal-sensors = 1516 thermal-sensors =
2065 <&soctherm TE 1517 <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>;
2066 1518
2067 trips { 1519 trips {
2068 dram_nominal: <<
2069 tempe <<
2070 hyste <<
2071 type <<
2072 }; <<
2073 <<
2074 dram_throttle <<
2075 tempe <<
2076 hyste <<
2077 type <<
2078 }; <<
2079 <<
2080 mem-hot-trip <<
2081 tempe <<
2082 hyste <<
2083 type <<
2084 }; <<
2085 <<
2086 mem-shutdown- 1520 mem-shutdown-trip {
2087 tempe 1521 temperature = <103000>;
2088 hyste 1522 hysteresis = <0>;
2089 type 1523 type = "critical";
2090 }; 1524 };
2091 }; 1525 };
2092 1526
2093 cooling-maps { 1527 cooling-maps {
2094 dram-passive !! 1528 /*
2095 cooli !! 1529 * There are currently no cooling maps,
2096 trip !! 1530 * because there are no cooling devices.
2097 }; !! 1531 */
2098 <<
2099 dram-active { <<
2100 cooli <<
2101 trip <<
2102 }; <<
2103 }; 1532 };
2104 }; 1533 };
2105 !! 1534 gpu {
2106 gpu-thermal { <<
2107 polling-delay-passive 1535 polling-delay-passive = <1000>;
2108 polling-delay = <0>; 1536 polling-delay = <0>;
2109 1537
2110 thermal-sensors = 1538 thermal-sensors =
2111 <&soctherm TE 1539 <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>;
2112 1540
2113 trips { 1541 trips {
2114 gpu-shutdown- 1542 gpu-shutdown-trip {
2115 tempe 1543 temperature = <103000>;
2116 hyste 1544 hysteresis = <0>;
2117 type 1545 type = "critical";
2118 }; 1546 };
2119 1547
2120 gpu_throttle_ 1548 gpu_throttle_trip: throttle-trip {
2121 tempe 1549 temperature = <100000>;
2122 hyste 1550 hysteresis = <1000>;
2123 type 1551 type = "hot";
2124 }; 1552 };
2125 }; 1553 };
2126 1554
2127 cooling-maps { 1555 cooling-maps {
2128 map0 { 1556 map0 {
2129 trip 1557 trip = <&gpu_throttle_trip>;
2130 cooli 1558 cooling-device = <&throttle_heavy 1 1>;
2131 }; 1559 };
2132 }; 1560 };
2133 }; 1561 };
2134 !! 1562 pllx {
2135 pllx-thermal { <<
2136 polling-delay-passive 1563 polling-delay-passive = <0>;
2137 polling-delay = <0>; 1564 polling-delay = <0>;
2138 1565
2139 thermal-sensors = 1566 thermal-sensors =
2140 <&soctherm TE 1567 <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>;
2141 1568
2142 trips { 1569 trips {
2143 pllx-shutdown 1570 pllx-shutdown-trip {
2144 tempe 1571 temperature = <103000>;
2145 hyste 1572 hysteresis = <0>;
2146 type 1573 type = "critical";
2147 }; 1574 };
2148 <<
2149 pllx-throttle <<
2150 tempe <<
2151 hyste <<
2152 type <<
2153 }; <<
2154 }; 1575 };
2155 1576
2156 cooling-maps { 1577 cooling-maps {
2157 /* 1578 /*
2158 * There are 1579 * There are currently no cooling maps,
2159 * because th 1580 * because there are no cooling devices.
2160 */ 1581 */
2161 }; 1582 };
2162 }; 1583 };
2163 }; <<
2164 <<
2165 timer { <<
2166 compatible = "arm,armv8-timer <<
2167 interrupts = <GIC_PPI 13 <<
2168 (GIC_CPU_MASK <<
2169 <GIC_PPI 14 <<
2170 (GIC_CPU_MASK <<
2171 <GIC_PPI 11 <<
2172 (GIC_CPU_MASK <<
2173 <GIC_PPI 10 <<
2174 (GIC_CPU_MASK <<
2175 interrupt-parent = <&gic>; <<
2176 arm,no-tick-in-suspend; <<
2177 }; 1584 };
2178 }; 1585 };
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