1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra210-car.h> 2 #include <dt-bindings/clock/tegra210-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h> 3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra210-mc.h> 4 #include <dt-bindings/memory/tegra210-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h> 5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra-io 6 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
7 #include <dt-bindings/reset/tegra210-car.h> 7 #include <dt-bindings/reset/tegra210-car.h>
8 #include <dt-bindings/interrupt-controller/arm 8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/thermal/tegra124-socther 9 #include <dt-bindings/thermal/tegra124-soctherm.h>
10 #include <dt-bindings/soc/tegra-pmc.h> <<
11 10
12 / { 11 / {
13 compatible = "nvidia,tegra210"; 12 compatible = "nvidia,tegra210";
14 interrupt-parent = <&lic>; 13 interrupt-parent = <&lic>;
15 #address-cells = <2>; 14 #address-cells = <2>;
16 #size-cells = <2>; 15 #size-cells = <2>;
17 16
18 pcie@1003000 { 17 pcie@1003000 {
19 compatible = "nvidia,tegra210- 18 compatible = "nvidia,tegra210-pcie";
20 device_type = "pci"; 19 device_type = "pci";
21 reg = <0x0 0x01003000 0x0 0x00 !! 20 reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */
22 <0x0 0x01003800 0x0 0x00 !! 21 0x0 0x01003800 0x0 0x00000800 /* AFI registers */
23 <0x0 0x02000000 0x0 0x10 !! 22 0x0 0x02000000 0x0 0x10000000>; /* configuration space */
24 reg-names = "pads", "afi", "cs 23 reg-names = "pads", "afi", "cs";
25 interrupts = <GIC_SPI 98 IRQ_T 24 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
26 <GIC_SPI 99 IRQ_T 25 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
27 interrupt-names = "intr", "msi 26 interrupt-names = "intr", "msi";
28 27
29 #interrupt-cells = <1>; 28 #interrupt-cells = <1>;
30 interrupt-map-mask = <0 0 0 0> 29 interrupt-map-mask = <0 0 0 0>;
31 interrupt-map = <0 0 0 0 &gic 30 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
32 31
33 bus-range = <0x00 0xff>; 32 bus-range = <0x00 0xff>;
34 #address-cells = <3>; 33 #address-cells = <3>;
35 #size-cells = <2>; 34 #size-cells = <2>;
36 35
37 ranges = <0x02000000 0 0x01000 !! 36 ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000 /* port 0 configuration space */
38 <0x02000000 0 0x01001 !! 37 0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000 /* port 1 configuration space */
39 <0x01000000 0 0x0 !! 38 0x81000000 0 0x0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */
40 <0x02000000 0 0x13000 !! 39 0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */
41 <0x42000000 0 0x20000 !! 40 0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
42 41
43 clocks = <&tegra_car TEGRA210_ 42 clocks = <&tegra_car TEGRA210_CLK_PCIE>,
44 <&tegra_car TEGRA210_ 43 <&tegra_car TEGRA210_CLK_AFI>,
45 <&tegra_car TEGRA210_ 44 <&tegra_car TEGRA210_CLK_PLL_E>,
46 <&tegra_car TEGRA210_ 45 <&tegra_car TEGRA210_CLK_CML0>;
47 clock-names = "pex", "afi", "p 46 clock-names = "pex", "afi", "pll_e", "cml";
48 resets = <&tegra_car 70>, 47 resets = <&tegra_car 70>,
49 <&tegra_car 72>, 48 <&tegra_car 72>,
50 <&tegra_car 74>; 49 <&tegra_car 74>;
51 reset-names = "pex", "afi", "p 50 reset-names = "pex", "afi", "pcie_x";
52 51
53 pinctrl-names = "default", "id 52 pinctrl-names = "default", "idle";
54 pinctrl-0 = <&pex_dpd_disable> 53 pinctrl-0 = <&pex_dpd_disable>;
55 pinctrl-1 = <&pex_dpd_enable>; 54 pinctrl-1 = <&pex_dpd_enable>;
56 55
57 status = "disabled"; 56 status = "disabled";
58 57
59 pci@1,0 { 58 pci@1,0 {
60 device_type = "pci"; 59 device_type = "pci";
61 assigned-addresses = < 60 assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
62 reg = <0x000800 0 0 0 61 reg = <0x000800 0 0 0 0>;
63 bus-range = <0x00 0xff 62 bus-range = <0x00 0xff>;
64 status = "disabled"; 63 status = "disabled";
65 64
66 #address-cells = <3>; 65 #address-cells = <3>;
67 #size-cells = <2>; 66 #size-cells = <2>;
68 ranges; 67 ranges;
69 68
70 nvidia,num-lanes = <4> 69 nvidia,num-lanes = <4>;
71 }; 70 };
72 71
73 pci@2,0 { 72 pci@2,0 {
74 device_type = "pci"; 73 device_type = "pci";
75 assigned-addresses = < 74 assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
76 reg = <0x001000 0 0 0 75 reg = <0x001000 0 0 0 0>;
77 bus-range = <0x00 0xff 76 bus-range = <0x00 0xff>;
78 status = "disabled"; 77 status = "disabled";
79 78
80 #address-cells = <3>; 79 #address-cells = <3>;
81 #size-cells = <2>; 80 #size-cells = <2>;
82 ranges; 81 ranges;
83 82
84 nvidia,num-lanes = <1> 83 nvidia,num-lanes = <1>;
85 }; 84 };
86 }; 85 };
87 86
88 host1x@50000000 { 87 host1x@50000000 {
89 compatible = "nvidia,tegra210- !! 88 compatible = "nvidia,tegra210-host1x", "simple-bus";
90 reg = <0x0 0x50000000 0x0 0x00 89 reg = <0x0 0x50000000 0x0 0x00034000>;
91 interrupts = <GIC_SPI 65 IRQ_T 90 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
92 <GIC_SPI 67 IRQ_T 91 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
93 interrupt-names = "syncpt", "h <<
94 clocks = <&tegra_car TEGRA210_ 92 clocks = <&tegra_car TEGRA210_CLK_HOST1X>;
95 clock-names = "host1x"; 93 clock-names = "host1x";
96 resets = <&tegra_car 28>, <&mc !! 94 resets = <&tegra_car 28>;
97 reset-names = "host1x", "mc"; !! 95 reset-names = "host1x";
98 96
99 #address-cells = <2>; 97 #address-cells = <2>;
100 #size-cells = <2>; 98 #size-cells = <2>;
101 99
102 ranges = <0x0 0x54000000 0x0 0 100 ranges = <0x0 0x54000000 0x0 0x54000000 0x0 0x01000000>;
103 101
104 iommus = <&mc TEGRA_SWGROUP_HC 102 iommus = <&mc TEGRA_SWGROUP_HC>;
105 103
106 dpaux1: dpaux@54040000 { 104 dpaux1: dpaux@54040000 {
107 compatible = "nvidia,t 105 compatible = "nvidia,tegra210-dpaux";
108 reg = <0x0 0x54040000 106 reg = <0x0 0x54040000 0x0 0x00040000>;
109 interrupts = <GIC_SPI 107 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
110 clocks = <&tegra_car T 108 clocks = <&tegra_car TEGRA210_CLK_DPAUX1>,
111 <&tegra_car T 109 <&tegra_car TEGRA210_CLK_PLL_DP>;
112 clock-names = "dpaux", 110 clock-names = "dpaux", "parent";
113 resets = <&tegra_car 2 111 resets = <&tegra_car 207>;
114 reset-names = "dpaux"; 112 reset-names = "dpaux";
115 power-domains = <&pd_s 113 power-domains = <&pd_sor>;
116 status = "disabled"; 114 status = "disabled";
117 115
118 state_dpaux1_aux: pinm 116 state_dpaux1_aux: pinmux-aux {
119 groups = "dpau 117 groups = "dpaux-io";
120 function = "au 118 function = "aux";
121 }; 119 };
122 120
123 state_dpaux1_i2c: pinm 121 state_dpaux1_i2c: pinmux-i2c {
124 groups = "dpau 122 groups = "dpaux-io";
125 function = "i2 123 function = "i2c";
126 }; 124 };
127 125
128 state_dpaux1_off: pinm 126 state_dpaux1_off: pinmux-off {
129 groups = "dpau 127 groups = "dpaux-io";
130 function = "of 128 function = "off";
131 }; 129 };
132 130
133 i2c-bus { 131 i2c-bus {
134 #address-cells 132 #address-cells = <1>;
135 #size-cells = 133 #size-cells = <0>;
136 }; 134 };
137 }; 135 };
138 136
139 vi@54080000 { 137 vi@54080000 {
140 compatible = "nvidia,t 138 compatible = "nvidia,tegra210-vi";
141 reg = <0x0 0x54080000 !! 139 reg = <0x0 0x54080000 0x0 0x00040000>;
142 interrupts = <GIC_SPI 140 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
143 status = "disabled"; 141 status = "disabled";
144 assigned-clocks = <&te <<
145 assigned-clock-parents <<
146 <<
147 clocks = <&tegra_car T <<
148 power-domains = <&pd_v <<
149 <<
150 #address-cells = <1>; <<
151 #size-cells = <1>; <<
152 <<
153 ranges = <0x0 0x0 0x54 <<
154 <<
155 csi@838 { <<
156 compatible = " <<
157 reg = <0x838 0 <<
158 status = "disa <<
159 assigned-clock <<
160 <<
161 <<
162 <<
163 assigned-clock <<
164 <<
165 <<
166 assigned-clock <<
167 <<
168 <<
169 <<
170 <<
171 clocks = <&teg <<
172 <&teg <<
173 <&teg <<
174 <&teg <<
175 <&teg <<
176 clock-names = <<
177 power-domains <<
178 }; <<
179 }; 142 };
180 143
181 tsec@54100000 { 144 tsec@54100000 {
182 compatible = "nvidia,t 145 compatible = "nvidia,tegra210-tsec";
183 reg = <0x0 0x54100000 146 reg = <0x0 0x54100000 0x0 0x00040000>;
184 interrupts = <GIC_SPI <<
185 clocks = <&tegra_car T <<
186 clock-names = "tsec"; <<
187 resets = <&tegra_car 8 <<
188 reset-names = "tsec"; <<
189 status = "disabled"; <<
190 }; 147 };
191 148
192 dc@54200000 { 149 dc@54200000 {
193 compatible = "nvidia,t 150 compatible = "nvidia,tegra210-dc";
194 reg = <0x0 0x54200000 151 reg = <0x0 0x54200000 0x0 0x00040000>;
195 interrupts = <GIC_SPI 152 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
196 clocks = <&tegra_car T !! 153 clocks = <&tegra_car TEGRA210_CLK_DISP1>,
197 clock-names = "dc"; !! 154 <&tegra_car TEGRA210_CLK_PLL_P>;
>> 155 clock-names = "dc", "parent";
198 resets = <&tegra_car 2 156 resets = <&tegra_car 27>;
199 reset-names = "dc"; 157 reset-names = "dc";
200 158
201 iommus = <&mc TEGRA_SW 159 iommus = <&mc TEGRA_SWGROUP_DC>;
202 160
203 nvidia,outputs = <&dsi <<
204 nvidia,head = <0>; 161 nvidia,head = <0>;
205 }; 162 };
206 163
207 dc@54240000 { 164 dc@54240000 {
208 compatible = "nvidia,t 165 compatible = "nvidia,tegra210-dc";
209 reg = <0x0 0x54240000 166 reg = <0x0 0x54240000 0x0 0x00040000>;
210 interrupts = <GIC_SPI 167 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
211 clocks = <&tegra_car T !! 168 clocks = <&tegra_car TEGRA210_CLK_DISP2>,
212 clock-names = "dc"; !! 169 <&tegra_car TEGRA210_CLK_PLL_P>;
>> 170 clock-names = "dc", "parent";
213 resets = <&tegra_car 2 171 resets = <&tegra_car 26>;
214 reset-names = "dc"; 172 reset-names = "dc";
215 173
216 iommus = <&mc TEGRA_SW 174 iommus = <&mc TEGRA_SWGROUP_DCB>;
217 175
218 nvidia,outputs = <&dsi <<
219 nvidia,head = <1>; 176 nvidia,head = <1>;
220 }; 177 };
221 178
222 dsia: dsi@54300000 { !! 179 dsi@54300000 {
223 compatible = "nvidia,t 180 compatible = "nvidia,tegra210-dsi";
224 reg = <0x0 0x54300000 181 reg = <0x0 0x54300000 0x0 0x00040000>;
225 clocks = <&tegra_car T 182 clocks = <&tegra_car TEGRA210_CLK_DSIA>,
226 <&tegra_car T 183 <&tegra_car TEGRA210_CLK_DSIALP>,
227 <&tegra_car T 184 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>;
228 clock-names = "dsi", " 185 clock-names = "dsi", "lp", "parent";
229 resets = <&tegra_car 4 186 resets = <&tegra_car 48>;
230 reset-names = "dsi"; 187 reset-names = "dsi";
231 power-domains = <&pd_s 188 power-domains = <&pd_sor>;
232 nvidia,mipi-calibrate 189 nvidia,mipi-calibrate = <&mipi 0x0c0>; /* DSIA & DSIB pads */
233 190
234 status = "disabled"; 191 status = "disabled";
235 192
236 #address-cells = <1>; 193 #address-cells = <1>;
237 #size-cells = <0>; 194 #size-cells = <0>;
238 }; 195 };
239 196
240 vic@54340000 { 197 vic@54340000 {
241 compatible = "nvidia,t 198 compatible = "nvidia,tegra210-vic";
242 reg = <0x0 0x54340000 199 reg = <0x0 0x54340000 0x0 0x00040000>;
243 interrupts = <GIC_SPI 200 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
244 clocks = <&tegra_car T 201 clocks = <&tegra_car TEGRA210_CLK_VIC03>;
245 clock-names = "vic"; 202 clock-names = "vic";
246 resets = <&tegra_car 1 203 resets = <&tegra_car 178>;
247 reset-names = "vic"; 204 reset-names = "vic";
248 205
249 iommus = <&mc TEGRA_SW 206 iommus = <&mc TEGRA_SWGROUP_VIC>;
250 power-domains = <&pd_v 207 power-domains = <&pd_vic>;
251 }; 208 };
252 209
253 nvjpg@54380000 { 210 nvjpg@54380000 {
254 compatible = "nvidia,t 211 compatible = "nvidia,tegra210-nvjpg";
255 reg = <0x0 0x54380000 212 reg = <0x0 0x54380000 0x0 0x00040000>;
256 status = "disabled"; 213 status = "disabled";
257 }; 214 };
258 215
259 dsib: dsi@54400000 { !! 216 dsi@54400000 {
260 compatible = "nvidia,t 217 compatible = "nvidia,tegra210-dsi";
261 reg = <0x0 0x54400000 218 reg = <0x0 0x54400000 0x0 0x00040000>;
262 clocks = <&tegra_car T 219 clocks = <&tegra_car TEGRA210_CLK_DSIB>,
263 <&tegra_car T 220 <&tegra_car TEGRA210_CLK_DSIBLP>,
264 <&tegra_car T 221 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>;
265 clock-names = "dsi", " 222 clock-names = "dsi", "lp", "parent";
266 resets = <&tegra_car 8 223 resets = <&tegra_car 82>;
267 reset-names = "dsi"; 224 reset-names = "dsi";
268 power-domains = <&pd_s 225 power-domains = <&pd_sor>;
269 nvidia,mipi-calibrate 226 nvidia,mipi-calibrate = <&mipi 0x300>; /* DSIC & DSID pads */
270 227
271 status = "disabled"; 228 status = "disabled";
272 229
273 #address-cells = <1>; 230 #address-cells = <1>;
274 #size-cells = <0>; 231 #size-cells = <0>;
275 }; 232 };
276 233
277 nvdec@54480000 { 234 nvdec@54480000 {
278 compatible = "nvidia,t 235 compatible = "nvidia,tegra210-nvdec";
279 reg = <0x0 0x54480000 236 reg = <0x0 0x54480000 0x0 0x00040000>;
280 status = "disabled"; 237 status = "disabled";
281 }; 238 };
282 239
283 nvenc@544c0000 { 240 nvenc@544c0000 {
284 compatible = "nvidia,t 241 compatible = "nvidia,tegra210-nvenc";
285 reg = <0x0 0x544c0000 242 reg = <0x0 0x544c0000 0x0 0x00040000>;
286 status = "disabled"; 243 status = "disabled";
287 }; 244 };
288 245
289 tsec@54500000 { 246 tsec@54500000 {
290 compatible = "nvidia,t 247 compatible = "nvidia,tegra210-tsec";
291 reg = <0x0 0x54500000 248 reg = <0x0 0x54500000 0x0 0x00040000>;
292 interrupts = <GIC_SPI <<
293 clocks = <&tegra_car T <<
294 clock-names = "tsec"; <<
295 resets = <&tegra_car 2 <<
296 reset-names = "tsec"; <<
297 status = "disabled"; 249 status = "disabled";
298 }; 250 };
299 251
300 sor0: sor@54540000 { !! 252 sor@54540000 {
301 compatible = "nvidia,t 253 compatible = "nvidia,tegra210-sor";
302 reg = <0x0 0x54540000 254 reg = <0x0 0x54540000 0x0 0x00040000>;
303 interrupts = <GIC_SPI 255 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
304 clocks = <&tegra_car T 256 clocks = <&tegra_car TEGRA210_CLK_SOR0>,
305 <&tegra_car T 257 <&tegra_car TEGRA210_CLK_SOR0_OUT>,
306 <&tegra_car T 258 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>,
307 <&tegra_car T 259 <&tegra_car TEGRA210_CLK_PLL_DP>,
308 <&tegra_car T 260 <&tegra_car TEGRA210_CLK_SOR_SAFE>;
309 clock-names = "sor", " 261 clock-names = "sor", "out", "parent", "dp", "safe";
310 resets = <&tegra_car 1 262 resets = <&tegra_car 182>;
311 reset-names = "sor"; 263 reset-names = "sor";
312 pinctrl-0 = <&state_dp 264 pinctrl-0 = <&state_dpaux_aux>;
313 pinctrl-1 = <&state_dp 265 pinctrl-1 = <&state_dpaux_i2c>;
314 pinctrl-2 = <&state_dp 266 pinctrl-2 = <&state_dpaux_off>;
315 pinctrl-names = "aux", 267 pinctrl-names = "aux", "i2c", "off";
316 power-domains = <&pd_s 268 power-domains = <&pd_sor>;
317 status = "disabled"; 269 status = "disabled";
318 }; 270 };
319 271
320 sor1: sor@54580000 { !! 272 sor@54580000 {
321 compatible = "nvidia,t 273 compatible = "nvidia,tegra210-sor1";
322 reg = <0x0 0x54580000 274 reg = <0x0 0x54580000 0x0 0x00040000>;
323 interrupts = <GIC_SPI 275 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
324 clocks = <&tegra_car T 276 clocks = <&tegra_car TEGRA210_CLK_SOR1>,
325 <&tegra_car T 277 <&tegra_car TEGRA210_CLK_SOR1_OUT>,
326 <&tegra_car T 278 <&tegra_car TEGRA210_CLK_PLL_D2_OUT0>,
327 <&tegra_car T 279 <&tegra_car TEGRA210_CLK_PLL_DP>,
328 <&tegra_car T 280 <&tegra_car TEGRA210_CLK_SOR_SAFE>;
329 clock-names = "sor", " 281 clock-names = "sor", "out", "parent", "dp", "safe";
330 resets = <&tegra_car 1 282 resets = <&tegra_car 183>;
331 reset-names = "sor"; 283 reset-names = "sor";
332 pinctrl-0 = <&state_dp 284 pinctrl-0 = <&state_dpaux1_aux>;
333 pinctrl-1 = <&state_dp 285 pinctrl-1 = <&state_dpaux1_i2c>;
334 pinctrl-2 = <&state_dp 286 pinctrl-2 = <&state_dpaux1_off>;
335 pinctrl-names = "aux", 287 pinctrl-names = "aux", "i2c", "off";
336 power-domains = <&pd_s 288 power-domains = <&pd_sor>;
337 status = "disabled"; 289 status = "disabled";
338 }; 290 };
339 291
340 dpaux: dpaux@545c0000 { 292 dpaux: dpaux@545c0000 {
341 compatible = "nvidia,t !! 293 compatible = "nvidia,tegra124-dpaux";
342 reg = <0x0 0x545c0000 294 reg = <0x0 0x545c0000 0x0 0x00040000>;
343 interrupts = <GIC_SPI 295 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
344 clocks = <&tegra_car T 296 clocks = <&tegra_car TEGRA210_CLK_DPAUX>,
345 <&tegra_car T 297 <&tegra_car TEGRA210_CLK_PLL_DP>;
346 clock-names = "dpaux", 298 clock-names = "dpaux", "parent";
347 resets = <&tegra_car 1 299 resets = <&tegra_car 181>;
348 reset-names = "dpaux"; 300 reset-names = "dpaux";
349 power-domains = <&pd_s 301 power-domains = <&pd_sor>;
350 status = "disabled"; 302 status = "disabled";
351 303
352 state_dpaux_aux: pinmu 304 state_dpaux_aux: pinmux-aux {
353 groups = "dpau 305 groups = "dpaux-io";
354 function = "au 306 function = "aux";
355 }; 307 };
356 308
357 state_dpaux_i2c: pinmu 309 state_dpaux_i2c: pinmux-i2c {
358 groups = "dpau 310 groups = "dpaux-io";
359 function = "i2 311 function = "i2c";
360 }; 312 };
361 313
362 state_dpaux_off: pinmu 314 state_dpaux_off: pinmux-off {
363 groups = "dpau 315 groups = "dpaux-io";
364 function = "of 316 function = "off";
365 }; 317 };
366 318
367 i2c-bus { 319 i2c-bus {
368 #address-cells 320 #address-cells = <1>;
369 #size-cells = 321 #size-cells = <0>;
370 }; 322 };
371 }; 323 };
372 324
373 isp@54600000 { 325 isp@54600000 {
374 compatible = "nvidia,t 326 compatible = "nvidia,tegra210-isp";
375 reg = <0x0 0x54600000 327 reg = <0x0 0x54600000 0x0 0x00040000>;
376 interrupts = <GIC_SPI 328 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
377 clocks = <&tegra_car T <<
378 resets = <&tegra_car 2 <<
379 reset-names = "isp"; <<
380 status = "disabled"; 329 status = "disabled";
381 }; 330 };
382 331
383 isp@54680000 { 332 isp@54680000 {
384 compatible = "nvidia,t 333 compatible = "nvidia,tegra210-isp";
385 reg = <0x0 0x54680000 334 reg = <0x0 0x54680000 0x0 0x00040000>;
386 interrupts = <GIC_SPI 335 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
387 clocks = <&tegra_car T <<
388 resets = <&tegra_car 3 <<
389 reset-names = "isp"; <<
390 status = "disabled"; 336 status = "disabled";
391 }; 337 };
392 338
393 i2c@546c0000 { 339 i2c@546c0000 {
394 compatible = "nvidia,t 340 compatible = "nvidia,tegra210-i2c-vi";
395 reg = <0x0 0x546c0000 341 reg = <0x0 0x546c0000 0x0 0x00040000>;
396 interrupts = <GIC_SPI 342 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
397 clocks = <&tegra_car T <<
398 <&tegra_car T <<
399 clock-names = "div-clk <<
400 resets = <&tegra_car 2 <<
401 reset-names = "i2c"; <<
402 power-domains = <&pd_v <<
403 status = "disabled"; 343 status = "disabled";
404 <<
405 #address-cells = <1>; <<
406 #size-cells = <0>; <<
407 }; 344 };
408 }; 345 };
409 346
410 gic: interrupt-controller@50041000 { 347 gic: interrupt-controller@50041000 {
411 compatible = "arm,gic-400"; 348 compatible = "arm,gic-400";
412 #interrupt-cells = <3>; 349 #interrupt-cells = <3>;
413 interrupt-controller; 350 interrupt-controller;
414 reg = <0x0 0x50041000 0x0 0x10 351 reg = <0x0 0x50041000 0x0 0x1000>,
415 <0x0 0x50042000 0x0 0x20 352 <0x0 0x50042000 0x0 0x2000>,
416 <0x0 0x50044000 0x0 0x20 353 <0x0 0x50044000 0x0 0x2000>,
417 <0x0 0x50046000 0x0 0x20 354 <0x0 0x50046000 0x0 0x2000>;
418 interrupts = <GIC_PPI 9 355 interrupts = <GIC_PPI 9
419 (GIC_CPU_MASK_SIMPLE(4 356 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
420 interrupt-parent = <&gic>; 357 interrupt-parent = <&gic>;
421 }; 358 };
422 359
423 gpu@57000000 { 360 gpu@57000000 {
424 compatible = "nvidia,gm20b"; 361 compatible = "nvidia,gm20b";
425 reg = <0x0 0x57000000 0x0 0x01 362 reg = <0x0 0x57000000 0x0 0x01000000>,
426 <0x0 0x58000000 0x0 0x01 363 <0x0 0x58000000 0x0 0x01000000>;
427 interrupts = <GIC_SPI 157 IRQ_ 364 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
428 <GIC_SPI 158 IRQ_ 365 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
429 interrupt-names = "stall", "no 366 interrupt-names = "stall", "nonstall";
430 clocks = <&tegra_car TEGRA210_ 367 clocks = <&tegra_car TEGRA210_CLK_GPU>,
431 <&tegra_car TEGRA210_ 368 <&tegra_car TEGRA210_CLK_PLL_P_OUT5>,
432 <&tegra_car TEGRA210_ 369 <&tegra_car TEGRA210_CLK_PLL_G_REF>;
433 clock-names = "gpu", "pwr", "r 370 clock-names = "gpu", "pwr", "ref";
434 resets = <&tegra_car 184>; 371 resets = <&tegra_car 184>;
435 reset-names = "gpu"; 372 reset-names = "gpu";
436 373
437 iommus = <&mc TEGRA_SWGROUP_GP 374 iommus = <&mc TEGRA_SWGROUP_GPU>;
438 375
439 status = "disabled"; 376 status = "disabled";
440 }; 377 };
441 378
442 lic: interrupt-controller@60004000 { 379 lic: interrupt-controller@60004000 {
443 compatible = "nvidia,tegra210- 380 compatible = "nvidia,tegra210-ictlr";
444 reg = <0x0 0x60004000 0x0 0x40 381 reg = <0x0 0x60004000 0x0 0x40>, /* primary controller */
445 <0x0 0x60004100 0x0 0x40 382 <0x0 0x60004100 0x0 0x40>, /* secondary controller */
446 <0x0 0x60004200 0x0 0x40 383 <0x0 0x60004200 0x0 0x40>, /* tertiary controller */
447 <0x0 0x60004300 0x0 0x40 384 <0x0 0x60004300 0x0 0x40>, /* quaternary controller */
448 <0x0 0x60004400 0x0 0x40 385 <0x0 0x60004400 0x0 0x40>, /* quinary controller */
449 <0x0 0x60004500 0x0 0x40 386 <0x0 0x60004500 0x0 0x40>; /* senary controller */
450 interrupt-controller; 387 interrupt-controller;
451 #interrupt-cells = <3>; 388 #interrupt-cells = <3>;
452 interrupt-parent = <&gic>; 389 interrupt-parent = <&gic>;
453 }; 390 };
454 391
455 timer@60005000 { 392 timer@60005000 {
456 compatible = "nvidia,tegra210- 393 compatible = "nvidia,tegra210-timer";
457 reg = <0x0 0x60005000 0x0 0x40 394 reg = <0x0 0x60005000 0x0 0x400>;
458 interrupts = <GIC_SPI 156 IRQ_ 395 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
459 <GIC_SPI 0 IRQ_TY 396 <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
460 <GIC_SPI 1 IRQ_TY 397 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
461 <GIC_SPI 41 IRQ_T 398 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
462 <GIC_SPI 42 IRQ_T 399 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
463 <GIC_SPI 121 IRQ_ 400 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
464 <GIC_SPI 152 IRQ_ 401 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
465 <GIC_SPI 153 IRQ_ 402 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
466 <GIC_SPI 154 IRQ_ 403 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
467 <GIC_SPI 155 IRQ_ 404 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
468 <GIC_SPI 176 IRQ_ 405 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
469 <GIC_SPI 177 IRQ_ 406 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
470 <GIC_SPI 178 IRQ_ 407 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
471 <GIC_SPI 179 IRQ_ 408 <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
472 clocks = <&tegra_car TEGRA210_ 409 clocks = <&tegra_car TEGRA210_CLK_TIMER>;
473 clock-names = "timer"; 410 clock-names = "timer";
474 }; 411 };
475 412
476 tegra_car: clock@60006000 { 413 tegra_car: clock@60006000 {
477 compatible = "nvidia,tegra210- 414 compatible = "nvidia,tegra210-car";
478 reg = <0x0 0x60006000 0x0 0x10 415 reg = <0x0 0x60006000 0x0 0x1000>;
479 #clock-cells = <1>; 416 #clock-cells = <1>;
480 #reset-cells = <1>; 417 #reset-cells = <1>;
481 }; 418 };
482 419
483 flow-controller@60007000 { 420 flow-controller@60007000 {
484 compatible = "nvidia,tegra210- 421 compatible = "nvidia,tegra210-flowctrl";
485 reg = <0x0 0x60007000 0x0 0x10 422 reg = <0x0 0x60007000 0x0 0x1000>;
486 }; 423 };
487 424
488 gpio: gpio@6000d000 { 425 gpio: gpio@6000d000 {
489 compatible = "nvidia,tegra210- 426 compatible = "nvidia,tegra210-gpio", "nvidia,tegra30-gpio";
490 reg = <0x0 0x6000d000 0x0 0x10 427 reg = <0x0 0x6000d000 0x0 0x1000>;
491 interrupts = <GIC_SPI 32 IRQ_T 428 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
492 <GIC_SPI 33 IRQ_T 429 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
493 <GIC_SPI 34 IRQ_T 430 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
494 <GIC_SPI 35 IRQ_T 431 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
495 <GIC_SPI 55 IRQ_T 432 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
496 <GIC_SPI 87 IRQ_T 433 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
497 <GIC_SPI 89 IRQ_T 434 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
498 <GIC_SPI 125 IRQ_ 435 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
499 #gpio-cells = <2>; 436 #gpio-cells = <2>;
500 gpio-controller; 437 gpio-controller;
501 #interrupt-cells = <2>; 438 #interrupt-cells = <2>;
502 interrupt-controller; 439 interrupt-controller;
503 }; 440 };
504 441
505 apbdma: dma@60020000 { 442 apbdma: dma@60020000 {
506 compatible = "nvidia,tegra210- 443 compatible = "nvidia,tegra210-apbdma", "nvidia,tegra148-apbdma";
507 reg = <0x0 0x60020000 0x0 0x14 444 reg = <0x0 0x60020000 0x0 0x1400>;
508 interrupts = <GIC_SPI 104 IRQ_ 445 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
509 <GIC_SPI 105 IRQ_ 446 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
510 <GIC_SPI 106 IRQ_ 447 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
511 <GIC_SPI 107 IRQ_ 448 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
512 <GIC_SPI 108 IRQ_ 449 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
513 <GIC_SPI 109 IRQ_ 450 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
514 <GIC_SPI 110 IRQ_ 451 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
515 <GIC_SPI 111 IRQ_ 452 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
516 <GIC_SPI 112 IRQ_ 453 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
517 <GIC_SPI 113 IRQ_ 454 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
518 <GIC_SPI 114 IRQ_ 455 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
519 <GIC_SPI 115 IRQ_ 456 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
520 <GIC_SPI 116 IRQ_ 457 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
521 <GIC_SPI 117 IRQ_ 458 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
522 <GIC_SPI 118 IRQ_ 459 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
523 <GIC_SPI 119 IRQ_ 460 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
524 <GIC_SPI 128 IRQ_ 461 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
525 <GIC_SPI 129 IRQ_ 462 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
526 <GIC_SPI 130 IRQ_ 463 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
527 <GIC_SPI 131 IRQ_ 464 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
528 <GIC_SPI 132 IRQ_ 465 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
529 <GIC_SPI 133 IRQ_ 466 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
530 <GIC_SPI 134 IRQ_ 467 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
531 <GIC_SPI 135 IRQ_ 468 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
532 <GIC_SPI 136 IRQ_ 469 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
533 <GIC_SPI 137 IRQ_ 470 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
534 <GIC_SPI 138 IRQ_ 471 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
535 <GIC_SPI 139 IRQ_ 472 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
536 <GIC_SPI 140 IRQ_ 473 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
537 <GIC_SPI 141 IRQ_ 474 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
538 <GIC_SPI 142 IRQ_ 475 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
539 <GIC_SPI 143 IRQ_ 476 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
540 clocks = <&tegra_car TEGRA210_ 477 clocks = <&tegra_car TEGRA210_CLK_APBDMA>;
541 clock-names = "dma"; 478 clock-names = "dma";
542 resets = <&tegra_car 34>; 479 resets = <&tegra_car 34>;
543 reset-names = "dma"; 480 reset-names = "dma";
544 #dma-cells = <1>; 481 #dma-cells = <1>;
545 }; 482 };
546 483
547 apbmisc@70000800 { 484 apbmisc@70000800 {
548 compatible = "nvidia,tegra210- 485 compatible = "nvidia,tegra210-apbmisc", "nvidia,tegra20-apbmisc";
549 reg = <0x0 0x70000800 0x0 0x64 486 reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */
550 <0x0 0x70000008 0x0 0x04 487 <0x0 0x70000008 0x0 0x04>; /* Strapping options */
551 }; 488 };
552 489
553 pinmux: pinmux@700008d4 { 490 pinmux: pinmux@700008d4 {
554 compatible = "nvidia,tegra210- 491 compatible = "nvidia,tegra210-pinmux";
555 reg = <0x0 0x700008d4 0x0 0x29 492 reg = <0x0 0x700008d4 0x0 0x29c>, /* Pad control registers */
556 <0x0 0x70003000 0x0 0x29 493 <0x0 0x70003000 0x0 0x294>; /* Mux registers */
557 !! 494 sdmmc1_3v3_drv: sdmmc1-3v3-drv {
558 sdmmc1_1v8_drv: pinmux-sdmmc1- <<
559 sdmmc1 { 495 sdmmc1 {
560 nvidia,pins = 496 nvidia,pins = "drive_sdmmc1";
561 nvidia,pull-do !! 497 nvidia,pull-down-strength = <0x8>;
562 nvidia,pull-up !! 498 nvidia,pull-up-strength = <0x8>;
563 }; 499 };
564 }; 500 };
565 !! 501 sdmmc1_1v8_drv: sdmmc1-1v8-drv {
566 sdmmc1_3v3_drv: pinmux-sdmmc1- <<
567 sdmmc1 { 502 sdmmc1 {
568 nvidia,pins = 503 nvidia,pins = "drive_sdmmc1";
569 nvidia,pull-do !! 504 nvidia,pull-down-strength = <0x4>;
570 nvidia,pull-up !! 505 nvidia,pull-up-strength = <0x3>;
571 }; 506 };
572 }; 507 };
573 !! 508 sdmmc2_1v8_drv: sdmmc2-1v8-drv {
574 sdmmc2_1v8_drv: pinmux-sdmmc2- <<
575 sdmmc2 { 509 sdmmc2 {
576 nvidia,pins = 510 nvidia,pins = "drive_sdmmc2";
577 nvidia,pull-do 511 nvidia,pull-down-strength = <0x10>;
578 nvidia,pull-up 512 nvidia,pull-up-strength = <0x10>;
579 }; 513 };
580 }; 514 };
581 !! 515 sdmmc3_3v3_drv: sdmmc3-3v3-drv {
582 sdmmc3_1v8_drv: pinmux-sdmmc3- <<
583 sdmmc3 { 516 sdmmc3 {
584 nvidia,pins = 517 nvidia,pins = "drive_sdmmc3";
585 nvidia,pull-do !! 518 nvidia,pull-down-strength = <0x8>;
586 nvidia,pull-up !! 519 nvidia,pull-up-strength = <0x8>;
587 }; 520 };
588 }; 521 };
589 !! 522 sdmmc3_1v8_drv: sdmmc3-1v8-drv {
590 sdmmc3_3v3_drv: pinmux-sdmmc3- <<
591 sdmmc3 { 523 sdmmc3 {
592 nvidia,pins = 524 nvidia,pins = "drive_sdmmc3";
593 nvidia,pull-do !! 525 nvidia,pull-down-strength = <0x4>;
594 nvidia,pull-up !! 526 nvidia,pull-up-strength = <0x3>;
595 }; 527 };
596 }; 528 };
597 !! 529 sdmmc4_1v8_drv: sdmmc4-1v8-drv {
598 sdmmc4_1v8_drv: pinmux-sdmmc4- <<
599 sdmmc4 { 530 sdmmc4 {
600 nvidia,pins = 531 nvidia,pins = "drive_sdmmc4";
601 nvidia,pull-do 532 nvidia,pull-down-strength = <0x10>;
602 nvidia,pull-up 533 nvidia,pull-up-strength = <0x10>;
603 }; 534 };
604 }; 535 };
605 }; 536 };
606 537
607 /* 538 /*
608 * There are two serial driver i.e. 82 539 * There are two serial driver i.e. 8250 based simple serial
609 * driver and APB DMA based serial dri 540 * driver and APB DMA based serial driver for higher baudrate
610 * and performance. To enable the 8250 541 * and performance. To enable the 8250 based driver, the compatible
611 * is "nvidia,tegra124-uart", "nvidia, 542 * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable
612 * the APB DMA based serial driver, th 543 * the APB DMA based serial driver, the compatible is
613 * "nvidia,tegra124-hsuart", "nvidia,t 544 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart".
614 */ 545 */
615 uarta: serial@70006000 { 546 uarta: serial@70006000 {
616 compatible = "nvidia,tegra210- 547 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
617 reg = <0x0 0x70006000 0x0 0x40 548 reg = <0x0 0x70006000 0x0 0x40>;
618 reg-shift = <2>; 549 reg-shift = <2>;
619 interrupts = <GIC_SPI 36 IRQ_T 550 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
620 clocks = <&tegra_car TEGRA210_ 551 clocks = <&tegra_car TEGRA210_CLK_UARTA>;
>> 552 clock-names = "serial";
621 resets = <&tegra_car 6>; 553 resets = <&tegra_car 6>;
>> 554 reset-names = "serial";
622 dmas = <&apbdma 8>, <&apbdma 8 555 dmas = <&apbdma 8>, <&apbdma 8>;
623 dma-names = "rx", "tx"; 556 dma-names = "rx", "tx";
624 status = "disabled"; 557 status = "disabled";
625 }; 558 };
626 559
627 uartb: serial@70006040 { 560 uartb: serial@70006040 {
628 compatible = "nvidia,tegra210- 561 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
629 reg = <0x0 0x70006040 0x0 0x40 562 reg = <0x0 0x70006040 0x0 0x40>;
630 reg-shift = <2>; 563 reg-shift = <2>;
631 interrupts = <GIC_SPI 37 IRQ_T 564 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
632 clocks = <&tegra_car TEGRA210_ 565 clocks = <&tegra_car TEGRA210_CLK_UARTB>;
>> 566 clock-names = "serial";
633 resets = <&tegra_car 7>; 567 resets = <&tegra_car 7>;
>> 568 reset-names = "serial";
634 dmas = <&apbdma 9>, <&apbdma 9 569 dmas = <&apbdma 9>, <&apbdma 9>;
635 dma-names = "rx", "tx"; 570 dma-names = "rx", "tx";
636 status = "disabled"; 571 status = "disabled";
637 }; 572 };
638 573
639 uartc: serial@70006200 { 574 uartc: serial@70006200 {
640 compatible = "nvidia,tegra210- 575 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
641 reg = <0x0 0x70006200 0x0 0x40 576 reg = <0x0 0x70006200 0x0 0x40>;
642 reg-shift = <2>; 577 reg-shift = <2>;
643 interrupts = <GIC_SPI 46 IRQ_T 578 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
644 clocks = <&tegra_car TEGRA210_ 579 clocks = <&tegra_car TEGRA210_CLK_UARTC>;
>> 580 clock-names = "serial";
645 resets = <&tegra_car 55>; 581 resets = <&tegra_car 55>;
>> 582 reset-names = "serial";
646 dmas = <&apbdma 10>, <&apbdma 583 dmas = <&apbdma 10>, <&apbdma 10>;
647 dma-names = "rx", "tx"; 584 dma-names = "rx", "tx";
648 status = "disabled"; 585 status = "disabled";
649 }; 586 };
650 587
651 uartd: serial@70006300 { 588 uartd: serial@70006300 {
652 compatible = "nvidia,tegra210- 589 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
653 reg = <0x0 0x70006300 0x0 0x40 590 reg = <0x0 0x70006300 0x0 0x40>;
654 reg-shift = <2>; 591 reg-shift = <2>;
655 interrupts = <GIC_SPI 90 IRQ_T 592 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
656 clocks = <&tegra_car TEGRA210_ 593 clocks = <&tegra_car TEGRA210_CLK_UARTD>;
>> 594 clock-names = "serial";
657 resets = <&tegra_car 65>; 595 resets = <&tegra_car 65>;
>> 596 reset-names = "serial";
658 dmas = <&apbdma 19>, <&apbdma 597 dmas = <&apbdma 19>, <&apbdma 19>;
659 dma-names = "rx", "tx"; 598 dma-names = "rx", "tx";
660 status = "disabled"; 599 status = "disabled";
661 }; 600 };
662 601
663 pwm: pwm@7000a000 { 602 pwm: pwm@7000a000 {
664 compatible = "nvidia,tegra210- 603 compatible = "nvidia,tegra210-pwm", "nvidia,tegra20-pwm";
665 reg = <0x0 0x7000a000 0x0 0x10 604 reg = <0x0 0x7000a000 0x0 0x100>;
666 #pwm-cells = <2>; 605 #pwm-cells = <2>;
667 clocks = <&tegra_car TEGRA210_ 606 clocks = <&tegra_car TEGRA210_CLK_PWM>;
>> 607 clock-names = "pwm";
668 resets = <&tegra_car 17>; 608 resets = <&tegra_car 17>;
669 reset-names = "pwm"; 609 reset-names = "pwm";
670 status = "disabled"; 610 status = "disabled";
671 }; 611 };
672 612
673 i2c@7000c000 { 613 i2c@7000c000 {
674 compatible = "nvidia,tegra210- 614 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c";
675 reg = <0x0 0x7000c000 0x0 0x10 615 reg = <0x0 0x7000c000 0x0 0x100>;
676 interrupts = <GIC_SPI 38 IRQ_T 616 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
677 #address-cells = <1>; 617 #address-cells = <1>;
678 #size-cells = <0>; 618 #size-cells = <0>;
679 clocks = <&tegra_car TEGRA210_ 619 clocks = <&tegra_car TEGRA210_CLK_I2C1>;
680 clock-names = "div-clk"; 620 clock-names = "div-clk";
681 resets = <&tegra_car 12>; 621 resets = <&tegra_car 12>;
682 reset-names = "i2c"; 622 reset-names = "i2c";
683 dmas = <&apbdma 21>, <&apbdma 623 dmas = <&apbdma 21>, <&apbdma 21>;
684 dma-names = "rx", "tx"; 624 dma-names = "rx", "tx";
685 status = "disabled"; 625 status = "disabled";
686 }; 626 };
687 627
688 i2c@7000c400 { 628 i2c@7000c400 {
689 compatible = "nvidia,tegra210- 629 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c";
690 reg = <0x0 0x7000c400 0x0 0x10 630 reg = <0x0 0x7000c400 0x0 0x100>;
691 interrupts = <GIC_SPI 84 IRQ_T 631 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
692 #address-cells = <1>; 632 #address-cells = <1>;
693 #size-cells = <0>; 633 #size-cells = <0>;
694 clocks = <&tegra_car TEGRA210_ 634 clocks = <&tegra_car TEGRA210_CLK_I2C2>;
695 clock-names = "div-clk"; 635 clock-names = "div-clk";
696 resets = <&tegra_car 54>; 636 resets = <&tegra_car 54>;
697 reset-names = "i2c"; 637 reset-names = "i2c";
698 dmas = <&apbdma 22>, <&apbdma 638 dmas = <&apbdma 22>, <&apbdma 22>;
699 dma-names = "rx", "tx"; 639 dma-names = "rx", "tx";
700 status = "disabled"; 640 status = "disabled";
701 }; 641 };
702 642
703 i2c@7000c500 { 643 i2c@7000c500 {
704 compatible = "nvidia,tegra210- 644 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c";
705 reg = <0x0 0x7000c500 0x0 0x10 645 reg = <0x0 0x7000c500 0x0 0x100>;
706 interrupts = <GIC_SPI 92 IRQ_T 646 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
707 #address-cells = <1>; 647 #address-cells = <1>;
708 #size-cells = <0>; 648 #size-cells = <0>;
709 clocks = <&tegra_car TEGRA210_ 649 clocks = <&tegra_car TEGRA210_CLK_I2C3>;
710 clock-names = "div-clk"; 650 clock-names = "div-clk";
711 resets = <&tegra_car 67>; 651 resets = <&tegra_car 67>;
712 reset-names = "i2c"; 652 reset-names = "i2c";
713 dmas = <&apbdma 23>, <&apbdma 653 dmas = <&apbdma 23>, <&apbdma 23>;
714 dma-names = "rx", "tx"; 654 dma-names = "rx", "tx";
715 status = "disabled"; 655 status = "disabled";
716 }; 656 };
717 657
718 i2c@7000c700 { 658 i2c@7000c700 {
719 compatible = "nvidia,tegra210- 659 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c";
720 reg = <0x0 0x7000c700 0x0 0x10 660 reg = <0x0 0x7000c700 0x0 0x100>;
721 interrupts = <GIC_SPI 120 IRQ_ 661 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
722 #address-cells = <1>; 662 #address-cells = <1>;
723 #size-cells = <0>; 663 #size-cells = <0>;
724 clocks = <&tegra_car TEGRA210_ 664 clocks = <&tegra_car TEGRA210_CLK_I2C4>;
725 clock-names = "div-clk"; 665 clock-names = "div-clk";
726 resets = <&tegra_car 103>; 666 resets = <&tegra_car 103>;
727 reset-names = "i2c"; 667 reset-names = "i2c";
728 dmas = <&apbdma 26>, <&apbdma 668 dmas = <&apbdma 26>, <&apbdma 26>;
729 dma-names = "rx", "tx"; 669 dma-names = "rx", "tx";
730 pinctrl-0 = <&state_dpaux1_i2c 670 pinctrl-0 = <&state_dpaux1_i2c>;
731 pinctrl-1 = <&state_dpaux1_off 671 pinctrl-1 = <&state_dpaux1_off>;
732 pinctrl-names = "default", "id 672 pinctrl-names = "default", "idle";
733 status = "disabled"; 673 status = "disabled";
734 }; 674 };
735 675
736 i2c@7000d000 { 676 i2c@7000d000 {
737 compatible = "nvidia,tegra210- 677 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c";
738 reg = <0x0 0x7000d000 0x0 0x10 678 reg = <0x0 0x7000d000 0x0 0x100>;
739 interrupts = <GIC_SPI 53 IRQ_T 679 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
740 #address-cells = <1>; 680 #address-cells = <1>;
741 #size-cells = <0>; 681 #size-cells = <0>;
742 clocks = <&tegra_car TEGRA210_ 682 clocks = <&tegra_car TEGRA210_CLK_I2C5>;
743 clock-names = "div-clk"; 683 clock-names = "div-clk";
744 resets = <&tegra_car 47>; 684 resets = <&tegra_car 47>;
745 reset-names = "i2c"; 685 reset-names = "i2c";
746 dmas = <&apbdma 24>, <&apbdma 686 dmas = <&apbdma 24>, <&apbdma 24>;
747 dma-names = "rx", "tx"; 687 dma-names = "rx", "tx";
748 status = "disabled"; 688 status = "disabled";
749 }; 689 };
750 690
751 i2c@7000d100 { 691 i2c@7000d100 {
752 compatible = "nvidia,tegra210- 692 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c";
753 reg = <0x0 0x7000d100 0x0 0x10 693 reg = <0x0 0x7000d100 0x0 0x100>;
754 interrupts = <GIC_SPI 63 IRQ_T 694 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
755 #address-cells = <1>; 695 #address-cells = <1>;
756 #size-cells = <0>; 696 #size-cells = <0>;
757 clocks = <&tegra_car TEGRA210_ 697 clocks = <&tegra_car TEGRA210_CLK_I2C6>;
758 clock-names = "div-clk"; 698 clock-names = "div-clk";
759 resets = <&tegra_car 166>; 699 resets = <&tegra_car 166>;
760 reset-names = "i2c"; 700 reset-names = "i2c";
761 dmas = <&apbdma 30>, <&apbdma 701 dmas = <&apbdma 30>, <&apbdma 30>;
762 dma-names = "rx", "tx"; 702 dma-names = "rx", "tx";
763 pinctrl-0 = <&state_dpaux_i2c> 703 pinctrl-0 = <&state_dpaux_i2c>;
764 pinctrl-1 = <&state_dpaux_off> 704 pinctrl-1 = <&state_dpaux_off>;
765 pinctrl-names = "default", "id 705 pinctrl-names = "default", "idle";
766 status = "disabled"; 706 status = "disabled";
767 }; 707 };
768 708
769 spi@7000d400 { 709 spi@7000d400 {
770 compatible = "nvidia,tegra210- 710 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
771 reg = <0x0 0x7000d400 0x0 0x20 711 reg = <0x0 0x7000d400 0x0 0x200>;
772 interrupts = <GIC_SPI 59 IRQ_T 712 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
773 #address-cells = <1>; 713 #address-cells = <1>;
774 #size-cells = <0>; 714 #size-cells = <0>;
775 clocks = <&tegra_car TEGRA210_ 715 clocks = <&tegra_car TEGRA210_CLK_SBC1>;
776 clock-names = "spi"; 716 clock-names = "spi";
777 resets = <&tegra_car 41>; 717 resets = <&tegra_car 41>;
778 reset-names = "spi"; 718 reset-names = "spi";
779 dmas = <&apbdma 15>, <&apbdma 719 dmas = <&apbdma 15>, <&apbdma 15>;
780 dma-names = "rx", "tx"; 720 dma-names = "rx", "tx";
781 status = "disabled"; 721 status = "disabled";
782 }; 722 };
783 723
784 spi@7000d600 { 724 spi@7000d600 {
785 compatible = "nvidia,tegra210- 725 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
786 reg = <0x0 0x7000d600 0x0 0x20 726 reg = <0x0 0x7000d600 0x0 0x200>;
787 interrupts = <GIC_SPI 82 IRQ_T 727 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
788 #address-cells = <1>; 728 #address-cells = <1>;
789 #size-cells = <0>; 729 #size-cells = <0>;
790 clocks = <&tegra_car TEGRA210_ 730 clocks = <&tegra_car TEGRA210_CLK_SBC2>;
791 clock-names = "spi"; 731 clock-names = "spi";
792 resets = <&tegra_car 44>; 732 resets = <&tegra_car 44>;
793 reset-names = "spi"; 733 reset-names = "spi";
794 dmas = <&apbdma 16>, <&apbdma 734 dmas = <&apbdma 16>, <&apbdma 16>;
795 dma-names = "rx", "tx"; 735 dma-names = "rx", "tx";
796 status = "disabled"; 736 status = "disabled";
797 }; 737 };
798 738
799 spi@7000d800 { 739 spi@7000d800 {
800 compatible = "nvidia,tegra210- 740 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
801 reg = <0x0 0x7000d800 0x0 0x20 741 reg = <0x0 0x7000d800 0x0 0x200>;
802 interrupts = <GIC_SPI 83 IRQ_T 742 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
803 #address-cells = <1>; 743 #address-cells = <1>;
804 #size-cells = <0>; 744 #size-cells = <0>;
805 clocks = <&tegra_car TEGRA210_ 745 clocks = <&tegra_car TEGRA210_CLK_SBC3>;
806 clock-names = "spi"; 746 clock-names = "spi";
807 resets = <&tegra_car 46>; 747 resets = <&tegra_car 46>;
808 reset-names = "spi"; 748 reset-names = "spi";
809 dmas = <&apbdma 17>, <&apbdma 749 dmas = <&apbdma 17>, <&apbdma 17>;
810 dma-names = "rx", "tx"; 750 dma-names = "rx", "tx";
811 status = "disabled"; 751 status = "disabled";
812 }; 752 };
813 753
814 spi@7000da00 { 754 spi@7000da00 {
815 compatible = "nvidia,tegra210- 755 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
816 reg = <0x0 0x7000da00 0x0 0x20 756 reg = <0x0 0x7000da00 0x0 0x200>;
817 interrupts = <GIC_SPI 93 IRQ_T 757 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
818 #address-cells = <1>; 758 #address-cells = <1>;
819 #size-cells = <0>; 759 #size-cells = <0>;
820 clocks = <&tegra_car TEGRA210_ 760 clocks = <&tegra_car TEGRA210_CLK_SBC4>;
821 clock-names = "spi"; 761 clock-names = "spi";
822 resets = <&tegra_car 68>; 762 resets = <&tegra_car 68>;
823 reset-names = "spi"; 763 reset-names = "spi";
824 dmas = <&apbdma 18>, <&apbdma 764 dmas = <&apbdma 18>, <&apbdma 18>;
825 dma-names = "rx", "tx"; 765 dma-names = "rx", "tx";
826 status = "disabled"; 766 status = "disabled";
827 }; 767 };
828 768
829 rtc@7000e000 { 769 rtc@7000e000 {
830 compatible = "nvidia,tegra210- 770 compatible = "nvidia,tegra210-rtc", "nvidia,tegra20-rtc";
831 reg = <0x0 0x7000e000 0x0 0x10 771 reg = <0x0 0x7000e000 0x0 0x100>;
832 interrupts = <16 IRQ_TYPE_LEVE 772 interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
833 interrupt-parent = <&tegra_pmc !! 773 interrupt-parent = <&pmc>;
834 clocks = <&tegra_car TEGRA210_ 774 clocks = <&tegra_car TEGRA210_CLK_RTC>;
835 clock-names = "rtc"; 775 clock-names = "rtc";
836 }; 776 };
837 777
838 tegra_pmc: pmc@7000e400 { !! 778 pmc: pmc@7000e400 {
839 compatible = "nvidia,tegra210- 779 compatible = "nvidia,tegra210-pmc";
840 reg = <0x0 0x7000e400 0x0 0x40 780 reg = <0x0 0x7000e400 0x0 0x400>;
841 clocks = <&tegra_car TEGRA210_ 781 clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>;
842 clock-names = "pclk", "clk32k_ 782 clock-names = "pclk", "clk32k_in";
843 #clock-cells = <1>; <<
844 #interrupt-cells = <2>; 783 #interrupt-cells = <2>;
845 interrupt-controller; 784 interrupt-controller;
846 785
847 pinmux { <<
848 pex_dpd_disable: pex-d <<
849 pins = "pex-bi <<
850 low-power-disa <<
851 }; <<
852 <<
853 pex_dpd_enable: pex-dp <<
854 pins = "pex-bi <<
855 low-power-enab <<
856 }; <<
857 <<
858 sdmmc1_1v8: sdmmc1-1v8 <<
859 pins = "sdmmc1 <<
860 power-source = <<
861 }; <<
862 <<
863 sdmmc1_3v3: sdmmc1-3v3 <<
864 pins = "sdmmc1 <<
865 power-source = <<
866 }; <<
867 <<
868 sdmmc3_1v8: sdmmc3-1v8 <<
869 pins = "sdmmc3 <<
870 power-source = <<
871 }; <<
872 <<
873 sdmmc3_3v3: sdmmc3-3v3 <<
874 pins = "sdmmc3 <<
875 power-source = <<
876 }; <<
877 }; <<
878 <<
879 powergates { 786 powergates {
880 pd_audio: aud { 787 pd_audio: aud {
881 clocks = <&teg 788 clocks = <&tegra_car TEGRA210_CLK_APE>,
882 <&teg 789 <&tegra_car TEGRA210_CLK_APB2APE>;
883 resets = <&teg 790 resets = <&tegra_car 198>;
884 #power-domain- 791 #power-domain-cells = <0>;
885 }; 792 };
886 793
887 pd_sor: sor { 794 pd_sor: sor {
888 clocks = <&teg 795 clocks = <&tegra_car TEGRA210_CLK_SOR0>,
889 <&teg 796 <&tegra_car TEGRA210_CLK_SOR1>,
890 <&teg !! 797 <&tegra_car TEGRA210_CLK_CSI>,
891 <&teg <<
892 <&teg <<
893 <&teg 798 <&tegra_car TEGRA210_CLK_DSIA>,
894 <&teg 799 <&tegra_car TEGRA210_CLK_DSIB>,
895 <&teg 800 <&tegra_car TEGRA210_CLK_DPAUX>,
896 <&teg 801 <&tegra_car TEGRA210_CLK_DPAUX1>,
897 <&teg 802 <&tegra_car TEGRA210_CLK_MIPI_CAL>;
898 resets = <&teg 803 resets = <&tegra_car TEGRA210_CLK_SOR0>,
899 <&teg 804 <&tegra_car TEGRA210_CLK_SOR1>,
>> 805 <&tegra_car TEGRA210_CLK_CSI>,
900 <&teg 806 <&tegra_car TEGRA210_CLK_DSIA>,
901 <&teg 807 <&tegra_car TEGRA210_CLK_DSIB>,
902 <&teg 808 <&tegra_car TEGRA210_CLK_DPAUX>,
903 <&teg 809 <&tegra_car TEGRA210_CLK_DPAUX1>,
904 <&teg 810 <&tegra_car TEGRA210_CLK_MIPI_CAL>;
905 #power-domain- 811 #power-domain-cells = <0>;
906 }; 812 };
907 813
908 pd_venc: venc { <<
909 clocks = <&teg <<
910 <&teg <<
911 resets = <&mc <<
912 <&teg <<
913 <&teg <<
914 #power-domain- <<
915 }; <<
916 <<
917 pd_vic: vic { <<
918 clocks = <&teg <<
919 resets = <&teg <<
920 #power-domain- <<
921 }; <<
922 <<
923 pd_xusbss: xusba { 814 pd_xusbss: xusba {
924 clocks = <&teg 815 clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>;
925 resets = <&teg 816 resets = <&tegra_car TEGRA210_CLK_XUSB_SS>;
926 #power-domain- 817 #power-domain-cells = <0>;
927 }; 818 };
928 819
929 pd_xusbdev: xusbb { 820 pd_xusbdev: xusbb {
930 clocks = <&teg 821 clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>;
931 resets = <&teg 822 resets = <&tegra_car 95>;
932 #power-domain- 823 #power-domain-cells = <0>;
933 }; 824 };
934 825
935 pd_xusbhost: xusbc { 826 pd_xusbhost: xusbc {
936 clocks = <&teg 827 clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>;
937 resets = <&teg 828 resets = <&tegra_car TEGRA210_CLK_XUSB_HOST>;
938 #power-domain- 829 #power-domain-cells = <0>;
939 }; 830 };
>> 831
>> 832 pd_vic: vic {
>> 833 clocks = <&tegra_car TEGRA210_CLK_VIC03>;
>> 834 clock-names = "vic";
>> 835 resets = <&tegra_car 178>;
>> 836 reset-names = "vic";
>> 837 #power-domain-cells = <0>;
>> 838 };
>> 839 };
>> 840
>> 841 sdmmc1_3v3: sdmmc1-3v3 {
>> 842 pins = "sdmmc1";
>> 843 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
>> 844 };
>> 845
>> 846 sdmmc1_1v8: sdmmc1-1v8 {
>> 847 pins = "sdmmc1";
>> 848 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
>> 849 };
>> 850
>> 851 sdmmc3_3v3: sdmmc3-3v3 {
>> 852 pins = "sdmmc3";
>> 853 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
>> 854 };
>> 855
>> 856 sdmmc3_1v8: sdmmc3-1v8 {
>> 857 pins = "sdmmc3";
>> 858 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
>> 859 };
>> 860
>> 861 pex_dpd_disable: pex_en {
>> 862 pex-dpd-disable {
>> 863 pins = "pex-bias", "pex-clk1", "pex-clk2";
>> 864 low-power-disable;
>> 865 };
>> 866 };
>> 867
>> 868 pex_dpd_enable: pex_dis {
>> 869 pex-dpd-enable {
>> 870 pins = "pex-bias", "pex-clk1", "pex-clk2";
>> 871 low-power-enable;
>> 872 };
940 }; 873 };
941 }; 874 };
942 875
943 fuse@7000f800 { 876 fuse@7000f800 {
944 compatible = "nvidia,tegra210- 877 compatible = "nvidia,tegra210-efuse";
945 reg = <0x0 0x7000f800 0x0 0x40 878 reg = <0x0 0x7000f800 0x0 0x400>;
946 clocks = <&tegra_car TEGRA210_ 879 clocks = <&tegra_car TEGRA210_CLK_FUSE>;
947 clock-names = "fuse"; 880 clock-names = "fuse";
948 resets = <&tegra_car 39>; 881 resets = <&tegra_car 39>;
949 reset-names = "fuse"; 882 reset-names = "fuse";
950 }; 883 };
951 884
952 mc: memory-controller@70019000 { 885 mc: memory-controller@70019000 {
953 compatible = "nvidia,tegra210- 886 compatible = "nvidia,tegra210-mc";
954 reg = <0x0 0x70019000 0x0 0x10 887 reg = <0x0 0x70019000 0x0 0x1000>;
955 clocks = <&tegra_car TEGRA210_ 888 clocks = <&tegra_car TEGRA210_CLK_MC>;
956 clock-names = "mc"; 889 clock-names = "mc";
957 890
958 interrupts = <GIC_SPI 77 IRQ_T 891 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
959 892
960 #iommu-cells = <1>; 893 #iommu-cells = <1>;
961 #reset-cells = <1>; <<
962 }; <<
963 <<
964 emc: external-memory-controller@7001b0 <<
965 compatible = "nvidia,tegra210- <<
966 reg = <0x0 0x7001b000 0x0 0x10 <<
967 <0x0 0x7001e000 0x0 0x10 <<
968 <0x0 0x7001f000 0x0 0x10 <<
969 clocks = <&tegra_car TEGRA210_ <<
970 clock-names = "emc"; <<
971 interrupts = <GIC_SPI 78 IRQ_T <<
972 nvidia,memory-controller = <&m <<
973 #cooling-cells = <2>; <<
974 }; 894 };
975 895
976 sata@70020000 { 896 sata@70020000 {
977 compatible = "nvidia,tegra210- 897 compatible = "nvidia,tegra210-ahci";
978 reg = <0x0 0x70027000 0x0 0x20 898 reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */
979 <0x0 0x70020000 0x0 0x70 899 <0x0 0x70020000 0x0 0x7000>, /* SATA */
980 <0x0 0x70001100 0x0 0x10 900 <0x0 0x70001100 0x0 0x1000>; /* SATA AUX */
981 interrupts = <GIC_SPI 23 IRQ_T 901 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
982 clocks = <&tegra_car TEGRA210_ 902 clocks = <&tegra_car TEGRA210_CLK_SATA>,
983 <&tegra_car TEGRA210_ 903 <&tegra_car TEGRA210_CLK_SATA_OOB>;
984 clock-names = "sata", "sata-oo 904 clock-names = "sata", "sata-oob";
985 resets = <&tegra_car 124>, 905 resets = <&tegra_car 124>,
986 <&tegra_car 129>, !! 906 <&tegra_car 123>,
987 <&tegra_car 123>; !! 907 <&tegra_car 129>;
988 reset-names = "sata", "sata-co !! 908 reset-names = "sata", "sata-oob", "sata-cold";
989 status = "disabled"; 909 status = "disabled";
990 }; 910 };
991 911
992 hda@70030000 { 912 hda@70030000 {
993 compatible = "nvidia,tegra210- 913 compatible = "nvidia,tegra210-hda", "nvidia,tegra30-hda";
994 reg = <0x0 0x70030000 0x0 0x10 914 reg = <0x0 0x70030000 0x0 0x10000>;
995 interrupts = <GIC_SPI 81 IRQ_T 915 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
996 clocks = <&tegra_car TEGRA210_ 916 clocks = <&tegra_car TEGRA210_CLK_HDA>,
997 <&tegra_car TEGRA210_ 917 <&tegra_car TEGRA210_CLK_HDA2HDMI>,
998 <&tegra_car TEGRA210_ 918 <&tegra_car TEGRA210_CLK_HDA2CODEC_2X>;
999 clock-names = "hda", "hda2hdmi 919 clock-names = "hda", "hda2hdmi", "hda2codec_2x";
1000 resets = <&tegra_car 125>, /* 920 resets = <&tegra_car 125>, /* hda */
1001 <&tegra_car 128>, /* 921 <&tegra_car 128>, /* hda2hdmi */
1002 <&tegra_car 111>; /* 922 <&tegra_car 111>; /* hda2codec_2x */
1003 reset-names = "hda", "hda2hdm 923 reset-names = "hda", "hda2hdmi", "hda2codec_2x";
1004 power-domains = <&pd_sor>; <<
1005 status = "disabled"; 924 status = "disabled";
1006 }; 925 };
1007 926
1008 usb@70090000 { 927 usb@70090000 {
1009 compatible = "nvidia,tegra210 928 compatible = "nvidia,tegra210-xusb";
1010 reg = <0x0 0x70090000 0x0 0x8 929 reg = <0x0 0x70090000 0x0 0x8000>,
1011 <0x0 0x70098000 0x0 0x1 930 <0x0 0x70098000 0x0 0x1000>,
1012 <0x0 0x70099000 0x0 0x1 931 <0x0 0x70099000 0x0 0x1000>;
1013 reg-names = "hcd", "fpci", "i 932 reg-names = "hcd", "fpci", "ipfs";
1014 933
1015 interrupts = <GIC_SPI 39 IRQ_ 934 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
1016 <GIC_SPI 40 IRQ_ 935 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1017 936
1018 clocks = <&tegra_car TEGRA210 937 clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>,
1019 <&tegra_car TEGRA210 938 <&tegra_car TEGRA210_CLK_XUSB_HOST_SRC>,
1020 <&tegra_car TEGRA210 939 <&tegra_car TEGRA210_CLK_XUSB_FALCON_SRC>,
1021 <&tegra_car TEGRA210 940 <&tegra_car TEGRA210_CLK_XUSB_SS>,
1022 <&tegra_car TEGRA210 941 <&tegra_car TEGRA210_CLK_XUSB_SS_DIV2>,
1023 <&tegra_car TEGRA210 942 <&tegra_car TEGRA210_CLK_XUSB_SS_SRC>,
1024 <&tegra_car TEGRA210 943 <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>,
1025 <&tegra_car TEGRA210 944 <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>,
1026 <&tegra_car TEGRA210 945 <&tegra_car TEGRA210_CLK_PLL_U_480M>,
1027 <&tegra_car TEGRA210 946 <&tegra_car TEGRA210_CLK_CLK_M>,
1028 <&tegra_car TEGRA210 947 <&tegra_car TEGRA210_CLK_PLL_E>;
1029 clock-names = "xusb_host", "x 948 clock-names = "xusb_host", "xusb_host_src",
1030 "xusb_falcon_sr 949 "xusb_falcon_src", "xusb_ss",
1031 "xusb_ss_div2", 950 "xusb_ss_div2", "xusb_ss_src",
1032 "xusb_hs_src", 951 "xusb_hs_src", "xusb_fs_src",
1033 "pll_u_480m", " 952 "pll_u_480m", "clk_m", "pll_e";
1034 resets = <&tegra_car 89>, <&t 953 resets = <&tegra_car 89>, <&tegra_car 156>,
1035 <&tegra_car 143>; 954 <&tegra_car 143>;
1036 reset-names = "xusb_host", "x 955 reset-names = "xusb_host", "xusb_ss", "xusb_src";
1037 power-domains = <&pd_xusbhost 956 power-domains = <&pd_xusbhost>, <&pd_xusbss>;
1038 power-domain-names = "xusb_ho 957 power-domain-names = "xusb_host", "xusb_ss";
1039 958
1040 nvidia,xusb-padctl = <&padctl 959 nvidia,xusb-padctl = <&padctl>;
1041 960
1042 status = "disabled"; 961 status = "disabled";
1043 }; 962 };
1044 963
1045 padctl: padctl@7009f000 { 964 padctl: padctl@7009f000 {
1046 compatible = "nvidia,tegra210 965 compatible = "nvidia,tegra210-xusb-padctl";
1047 reg = <0x0 0x7009f000 0x0 0x1 966 reg = <0x0 0x7009f000 0x0 0x1000>;
1048 interrupts = <GIC_SPI 49 IRQ_ <<
1049 resets = <&tegra_car 142>; 967 resets = <&tegra_car 142>;
1050 reset-names = "padctl"; 968 reset-names = "padctl";
1051 nvidia,pmc = <&tegra_pmc>; <<
1052 969
1053 status = "disabled"; 970 status = "disabled";
1054 971
1055 pads { 972 pads {
1056 usb2 { 973 usb2 {
1057 clocks = <&te 974 clocks = <&tegra_car TEGRA210_CLK_USB2_TRK>;
1058 clock-names = 975 clock-names = "trk";
1059 status = "dis 976 status = "disabled";
1060 977
1061 lanes { 978 lanes {
1062 usb2- 979 usb2-0 {
1063 980 status = "disabled";
1064 981 #phy-cells = <0>;
1065 }; 982 };
1066 983
1067 usb2- 984 usb2-1 {
1068 985 status = "disabled";
1069 986 #phy-cells = <0>;
1070 }; 987 };
1071 988
1072 usb2- 989 usb2-2 {
1073 990 status = "disabled";
1074 991 #phy-cells = <0>;
1075 }; 992 };
1076 993
1077 usb2- 994 usb2-3 {
1078 995 status = "disabled";
1079 996 #phy-cells = <0>;
1080 }; 997 };
1081 }; 998 };
1082 }; 999 };
1083 1000
1084 hsic { 1001 hsic {
1085 clocks = <&te 1002 clocks = <&tegra_car TEGRA210_CLK_HSIC_TRK>;
1086 clock-names = 1003 clock-names = "trk";
1087 status = "dis 1004 status = "disabled";
1088 1005
1089 lanes { 1006 lanes {
1090 hsic- 1007 hsic-0 {
1091 1008 status = "disabled";
1092 1009 #phy-cells = <0>;
1093 }; 1010 };
1094 1011
1095 hsic- 1012 hsic-1 {
1096 1013 status = "disabled";
1097 1014 #phy-cells = <0>;
1098 }; 1015 };
1099 }; 1016 };
1100 }; 1017 };
1101 1018
1102 pcie { 1019 pcie {
1103 clocks = <&te 1020 clocks = <&tegra_car TEGRA210_CLK_PLL_E>;
1104 clock-names = 1021 clock-names = "pll";
1105 resets = <&te 1022 resets = <&tegra_car 205>;
1106 reset-names = 1023 reset-names = "phy";
1107 status = "dis 1024 status = "disabled";
1108 1025
1109 lanes { 1026 lanes {
1110 pcie- 1027 pcie-0 {
1111 1028 status = "disabled";
1112 1029 #phy-cells = <0>;
1113 }; 1030 };
1114 1031
1115 pcie- 1032 pcie-1 {
1116 1033 status = "disabled";
1117 1034 #phy-cells = <0>;
1118 }; 1035 };
1119 1036
1120 pcie- 1037 pcie-2 {
1121 1038 status = "disabled";
1122 1039 #phy-cells = <0>;
1123 }; 1040 };
1124 1041
1125 pcie- 1042 pcie-3 {
1126 1043 status = "disabled";
1127 1044 #phy-cells = <0>;
1128 }; 1045 };
1129 1046
1130 pcie- 1047 pcie-4 {
1131 1048 status = "disabled";
1132 1049 #phy-cells = <0>;
1133 }; 1050 };
1134 1051
1135 pcie- 1052 pcie-5 {
1136 1053 status = "disabled";
1137 1054 #phy-cells = <0>;
1138 }; 1055 };
1139 1056
1140 pcie- 1057 pcie-6 {
1141 1058 status = "disabled";
1142 1059 #phy-cells = <0>;
1143 }; 1060 };
1144 }; 1061 };
1145 }; 1062 };
1146 1063
1147 sata { 1064 sata {
1148 clocks = <&te 1065 clocks = <&tegra_car TEGRA210_CLK_PLL_E>;
1149 clock-names = 1066 clock-names = "pll";
1150 resets = <&te 1067 resets = <&tegra_car 204>;
1151 reset-names = 1068 reset-names = "phy";
1152 status = "dis 1069 status = "disabled";
1153 1070
1154 lanes { 1071 lanes {
1155 sata- 1072 sata-0 {
1156 1073 status = "disabled";
1157 1074 #phy-cells = <0>;
1158 }; 1075 };
1159 }; 1076 };
1160 }; 1077 };
1161 }; 1078 };
1162 1079
1163 ports { 1080 ports {
1164 usb2-0 { 1081 usb2-0 {
1165 status = "dis 1082 status = "disabled";
1166 }; 1083 };
1167 1084
1168 usb2-1 { 1085 usb2-1 {
1169 status = "dis 1086 status = "disabled";
1170 }; 1087 };
1171 1088
1172 usb2-2 { 1089 usb2-2 {
1173 status = "dis 1090 status = "disabled";
1174 }; 1091 };
1175 1092
1176 usb2-3 { 1093 usb2-3 {
1177 status = "dis 1094 status = "disabled";
1178 }; 1095 };
1179 1096
1180 hsic-0 { 1097 hsic-0 {
1181 status = "dis 1098 status = "disabled";
1182 }; 1099 };
1183 1100
1184 usb3-0 { 1101 usb3-0 {
1185 status = "dis 1102 status = "disabled";
1186 }; 1103 };
1187 1104
1188 usb3-1 { 1105 usb3-1 {
1189 status = "dis 1106 status = "disabled";
1190 }; 1107 };
1191 1108
1192 usb3-2 { 1109 usb3-2 {
1193 status = "dis 1110 status = "disabled";
1194 }; 1111 };
1195 1112
1196 usb3-3 { 1113 usb3-3 {
1197 status = "dis 1114 status = "disabled";
1198 }; 1115 };
1199 }; 1116 };
1200 }; 1117 };
1201 1118
1202 mmc@700b0000 { !! 1119 sdhci@700b0000 {
1203 compatible = "nvidia,tegra210 !! 1120 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";
1204 reg = <0x0 0x700b0000 0x0 0x2 1121 reg = <0x0 0x700b0000 0x0 0x200>;
1205 interrupts = <GIC_SPI 14 IRQ_ 1122 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1206 clocks = <&tegra_car TEGRA210 !! 1123 clocks = <&tegra_car TEGRA210_CLK_SDMMC1>;
1207 <&tegra_car TEGRA210 !! 1124 clock-names = "sdhci";
1208 clock-names = "sdhci", "tmclk <<
1209 resets = <&tegra_car 14>; 1125 resets = <&tegra_car 14>;
1210 reset-names = "sdhci"; 1126 reset-names = "sdhci";
1211 pinctrl-names = "sdmmc-3v3", 1127 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8",
1212 "sdmmc-3v3-dr 1128 "sdmmc-3v3-drv", "sdmmc-1v8-drv";
1213 pinctrl-0 = <&sdmmc1_3v3>; 1129 pinctrl-0 = <&sdmmc1_3v3>;
1214 pinctrl-1 = <&sdmmc1_1v8>; 1130 pinctrl-1 = <&sdmmc1_1v8>;
1215 pinctrl-2 = <&sdmmc1_3v3_drv> 1131 pinctrl-2 = <&sdmmc1_3v3_drv>;
1216 pinctrl-3 = <&sdmmc1_1v8_drv> 1132 pinctrl-3 = <&sdmmc1_1v8_drv>;
1217 nvidia,pad-autocal-pull-up-of 1133 nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>;
1218 nvidia,pad-autocal-pull-down- 1134 nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>;
1219 nvidia,pad-autocal-pull-up-of 1135 nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>;
1220 nvidia,pad-autocal-pull-down- 1136 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>;
1221 nvidia,default-tap = <0x2>; 1137 nvidia,default-tap = <0x2>;
1222 nvidia,default-trim = <0x4>; 1138 nvidia,default-trim = <0x4>;
1223 assigned-clocks = <&tegra_car 1139 assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>,
1224 <&tegra_car 1140 <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>,
1225 <&tegra_car 1141 <&tegra_car TEGRA210_CLK_PLL_C4>;
1226 assigned-clock-parents = <&te 1142 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
1227 assigned-clock-rates = <20000 1143 assigned-clock-rates = <200000000>, <1000000000>, <1000000000>;
1228 status = "disabled"; 1144 status = "disabled";
1229 }; 1145 };
1230 1146
1231 mmc@700b0200 { !! 1147 sdhci@700b0200 {
1232 compatible = "nvidia,tegra210 !! 1148 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";
1233 reg = <0x0 0x700b0200 0x0 0x2 1149 reg = <0x0 0x700b0200 0x0 0x200>;
1234 interrupts = <GIC_SPI 15 IRQ_ 1150 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1235 clocks = <&tegra_car TEGRA210 !! 1151 clocks = <&tegra_car TEGRA210_CLK_SDMMC2>;
1236 <&tegra_car TEGRA210 !! 1152 clock-names = "sdhci";
1237 clock-names = "sdhci", "tmclk <<
1238 resets = <&tegra_car 9>; 1153 resets = <&tegra_car 9>;
1239 reset-names = "sdhci"; 1154 reset-names = "sdhci";
1240 pinctrl-names = "sdmmc-1v8-dr 1155 pinctrl-names = "sdmmc-1v8-drv";
1241 pinctrl-0 = <&sdmmc2_1v8_drv> 1156 pinctrl-0 = <&sdmmc2_1v8_drv>;
1242 nvidia,pad-autocal-pull-up-of 1157 nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>;
1243 nvidia,pad-autocal-pull-down- 1158 nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>;
1244 nvidia,default-tap = <0x8>; 1159 nvidia,default-tap = <0x8>;
1245 nvidia,default-trim = <0x0>; 1160 nvidia,default-trim = <0x0>;
1246 status = "disabled"; 1161 status = "disabled";
1247 }; 1162 };
1248 1163
1249 mmc@700b0400 { !! 1164 sdhci@700b0400 {
1250 compatible = "nvidia,tegra210 !! 1165 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";
1251 reg = <0x0 0x700b0400 0x0 0x2 1166 reg = <0x0 0x700b0400 0x0 0x200>;
1252 interrupts = <GIC_SPI 19 IRQ_ 1167 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1253 clocks = <&tegra_car TEGRA210 !! 1168 clocks = <&tegra_car TEGRA210_CLK_SDMMC3>;
1254 <&tegra_car TEGRA210 !! 1169 clock-names = "sdhci";
1255 clock-names = "sdhci", "tmclk <<
1256 resets = <&tegra_car 69>; 1170 resets = <&tegra_car 69>;
1257 reset-names = "sdhci"; 1171 reset-names = "sdhci";
1258 pinctrl-names = "sdmmc-3v3", 1172 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8",
1259 "sdmmc-3v3-dr 1173 "sdmmc-3v3-drv", "sdmmc-1v8-drv";
1260 pinctrl-0 = <&sdmmc3_3v3>; 1174 pinctrl-0 = <&sdmmc3_3v3>;
1261 pinctrl-1 = <&sdmmc3_1v8>; 1175 pinctrl-1 = <&sdmmc3_1v8>;
1262 pinctrl-2 = <&sdmmc3_3v3_drv> 1176 pinctrl-2 = <&sdmmc3_3v3_drv>;
1263 pinctrl-3 = <&sdmmc3_1v8_drv> 1177 pinctrl-3 = <&sdmmc3_1v8_drv>;
1264 nvidia,pad-autocal-pull-up-of 1178 nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>;
1265 nvidia,pad-autocal-pull-down- 1179 nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>;
1266 nvidia,pad-autocal-pull-up-of 1180 nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>;
1267 nvidia,pad-autocal-pull-down- 1181 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>;
1268 nvidia,default-tap = <0x3>; 1182 nvidia,default-tap = <0x3>;
1269 nvidia,default-trim = <0x3>; 1183 nvidia,default-trim = <0x3>;
1270 status = "disabled"; 1184 status = "disabled";
1271 }; 1185 };
1272 1186
1273 mmc@700b0600 { !! 1187 sdhci@700b0600 {
1274 compatible = "nvidia,tegra210 !! 1188 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";
1275 reg = <0x0 0x700b0600 0x0 0x2 1189 reg = <0x0 0x700b0600 0x0 0x200>;
1276 interrupts = <GIC_SPI 31 IRQ_ 1190 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
1277 clocks = <&tegra_car TEGRA210 !! 1191 clocks = <&tegra_car TEGRA210_CLK_SDMMC4>;
1278 <&tegra_car TEGRA210 !! 1192 clock-names = "sdhci";
1279 clock-names = "sdhci", "tmclk <<
1280 resets = <&tegra_car 15>; 1193 resets = <&tegra_car 15>;
1281 reset-names = "sdhci"; 1194 reset-names = "sdhci";
1282 pinctrl-names = "sdmmc-3v3-dr 1195 pinctrl-names = "sdmmc-3v3-drv", "sdmmc-1v8-drv";
1283 pinctrl-0 = <&sdmmc4_1v8_drv> 1196 pinctrl-0 = <&sdmmc4_1v8_drv>;
1284 pinctrl-1 = <&sdmmc4_1v8_drv> 1197 pinctrl-1 = <&sdmmc4_1v8_drv>;
1285 nvidia,pad-autocal-pull-up-of 1198 nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>;
1286 nvidia,pad-autocal-pull-down- 1199 nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>;
1287 nvidia,default-tap = <0x8>; 1200 nvidia,default-tap = <0x8>;
1288 nvidia,default-trim = <0x0>; 1201 nvidia,default-trim = <0x0>;
1289 assigned-clocks = <&tegra_car 1202 assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>,
1290 <&tegra_car 1203 <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
1291 assigned-clock-parents = <&te 1204 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
1292 nvidia,dqs-trim = <40>; 1205 nvidia,dqs-trim = <40>;
1293 mmc-hs400-1_8v; 1206 mmc-hs400-1_8v;
1294 status = "disabled"; 1207 status = "disabled";
1295 }; 1208 };
1296 1209
1297 usb@700d0000 { <<
1298 compatible = "nvidia,tegra210 <<
1299 reg = <0x0 0x700d0000 0x0 0x8 <<
1300 <0x0 0x700d8000 0x0 0x1 <<
1301 <0x0 0x700d9000 0x0 0x1 <<
1302 reg-names = "base", "fpci", " <<
1303 interrupts = <GIC_SPI 44 IRQ_ <<
1304 clocks = <&tegra_car TEGRA210 <<
1305 <&tegra_car TEGRA210 <<
1306 <&tegra_car TEGRA210 <<
1307 <&tegra_car TEGRA210 <<
1308 <&tegra_car TEGRA210 <<
1309 clock-names = "dev", "ss", "s <<
1310 power-domains = <&pd_xusbdev> <<
1311 power-domain-names = "dev", " <<
1312 nvidia,xusb-padctl = <&padctl <<
1313 status = "disabled"; <<
1314 }; <<
1315 <<
1316 soctherm: thermal-sensor@700e2000 { <<
1317 compatible = "nvidia,tegra210 <<
1318 reg = <0x0 0x700e2000 0x0 0x6 <<
1319 <0x0 0x60006000 0x0 0x4 <<
1320 reg-names = "soctherm-reg", " <<
1321 interrupts = <GIC_SPI 48 IRQ_ <<
1322 <GIC_SPI 51 IRQ_ <<
1323 interrupt-names = "thermal", <<
1324 clocks = <&tegra_car TEGRA210 <<
1325 <&tegra_car TEGRA210_ <<
1326 clock-names = "tsensor", "soc <<
1327 resets = <&tegra_car 78>; <<
1328 reset-names = "soctherm"; <<
1329 #thermal-sensor-cells = <1>; <<
1330 <<
1331 throttle-cfgs { <<
1332 throttle_heavy: heavy <<
1333 nvidia,priori <<
1334 nvidia,cpu-th <<
1335 nvidia,gpu-th <<
1336 <<
1337 #cooling-cell <<
1338 }; <<
1339 }; <<
1340 }; <<
1341 <<
1342 mipi: mipi@700e3000 { 1210 mipi: mipi@700e3000 {
1343 compatible = "nvidia,tegra210 1211 compatible = "nvidia,tegra210-mipi";
1344 reg = <0x0 0x700e3000 0x0 0x1 1212 reg = <0x0 0x700e3000 0x0 0x100>;
1345 clocks = <&tegra_car TEGRA210 1213 clocks = <&tegra_car TEGRA210_CLK_MIPI_CAL>;
1346 clock-names = "mipi-cal"; 1214 clock-names = "mipi-cal";
1347 power-domains = <&pd_sor>; 1215 power-domains = <&pd_sor>;
1348 #nvidia,mipi-calibrate-cells 1216 #nvidia,mipi-calibrate-cells = <1>;
1349 }; 1217 };
1350 1218
1351 dfll: clock@70110000 { 1219 dfll: clock@70110000 {
1352 compatible = "nvidia,tegra210 1220 compatible = "nvidia,tegra210-dfll";
1353 reg = <0 0x70110000 0 0x100>, 1221 reg = <0 0x70110000 0 0x100>, /* DFLL control */
1354 <0 0x70110000 0 0x100>, 1222 <0 0x70110000 0 0x100>, /* I2C output control */
1355 <0 0x70110100 0 0x100>, 1223 <0 0x70110100 0 0x100>, /* Integrated I2C controller */
1356 <0 0x70110200 0 0x100>; 1224 <0 0x70110200 0 0x100>; /* Look-up table RAM */
1357 interrupts = <GIC_SPI 62 IRQ_ 1225 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
1358 clocks = <&tegra_car TEGRA210 1226 clocks = <&tegra_car TEGRA210_CLK_DFLL_SOC>,
1359 <&tegra_car TEGRA210 1227 <&tegra_car TEGRA210_CLK_DFLL_REF>,
1360 <&tegra_car TEGRA210 1228 <&tegra_car TEGRA210_CLK_I2C5>;
1361 clock-names = "soc", "ref", " 1229 clock-names = "soc", "ref", "i2c";
1362 resets = <&tegra_car TEGRA210 !! 1230 resets = <&tegra_car TEGRA210_RST_DFLL_DVCO>;
1363 <&tegra_car 155>; !! 1231 reset-names = "dvco";
1364 reset-names = "dvco", "dfll"; <<
1365 #clock-cells = <0>; 1232 #clock-cells = <0>;
1366 clock-output-names = "dfllCPU 1233 clock-output-names = "dfllCPU_out";
1367 status = "disabled"; 1234 status = "disabled";
1368 }; 1235 };
1369 1236
1370 aconnect@702c0000 { 1237 aconnect@702c0000 {
1371 compatible = "nvidia,tegra210 1238 compatible = "nvidia,tegra210-aconnect";
1372 clocks = <&tegra_car TEGRA210 1239 clocks = <&tegra_car TEGRA210_CLK_APE>,
1373 <&tegra_car TEGRA210 1240 <&tegra_car TEGRA210_CLK_APB2APE>;
1374 clock-names = "ape", "apb2ape 1241 clock-names = "ape", "apb2ape";
1375 power-domains = <&pd_audio>; 1242 power-domains = <&pd_audio>;
1376 #address-cells = <1>; 1243 #address-cells = <1>;
1377 #size-cells = <1>; 1244 #size-cells = <1>;
1378 ranges = <0x702c0000 0x0 0x70 1245 ranges = <0x702c0000 0x0 0x702c0000 0x00040000>;
1379 status = "disabled"; 1246 status = "disabled";
1380 1247
1381 tegra_ahub: ahub@702d0800 { !! 1248 adma: dma@702e2000 {
1382 compatible = "nvidia, <<
1383 reg = <0x702d0800 0x8 <<
1384 clocks = <&tegra_car <<
1385 clock-names = "ahub"; <<
1386 assigned-clocks = <&t <<
1387 assigned-clock-parent <<
1388 assigned-clock-rates <<
1389 #address-cells = <1>; <<
1390 #size-cells = <1>; <<
1391 ranges = <0x702d0000 <<
1392 status = "disabled"; <<
1393 <<
1394 tegra_admaif: admaif@ <<
1395 compatible = <<
1396 reg = <0x702d <<
1397 dmas = <&adma <<
1398 <&adma <<
1399 <&adma <<
1400 <&adma <<
1401 <&adma <<
1402 <&adma <<
1403 <&adma <<
1404 <&adma <<
1405 <&adma <<
1406 <&adma <<
1407 dma-names = " <<
1408 " <<
1409 " <<
1410 " <<
1411 " <<
1412 " <<
1413 " <<
1414 " <<
1415 " <<
1416 " <<
1417 status = "dis <<
1418 <<
1419 ports { <<
1420 #addr <<
1421 #size <<
1422 <<
1423 admai <<
1424 <<
1425 <<
1426 <<
1427 <<
1428 <<
1429 }; <<
1430 <<
1431 admai <<
1432 <<
1433 <<
1434 <<
1435 <<
1436 <<
1437 }; <<
1438 <<
1439 admai <<
1440 <<
1441 <<
1442 <<
1443 <<
1444 <<
1445 }; <<
1446 <<
1447 admai <<
1448 <<
1449 <<
1450 <<
1451 <<
1452 <<
1453 }; <<
1454 <<
1455 admai <<
1456 <<
1457 <<
1458 <<
1459 <<
1460 <<
1461 }; <<
1462 <<
1463 admai <<
1464 <<
1465 <<
1466 <<
1467 <<
1468 <<
1469 }; <<
1470 <<
1471 admai <<
1472 <<
1473 <<
1474 <<
1475 <<
1476 <<
1477 }; <<
1478 <<
1479 admai <<
1480 <<
1481 <<
1482 <<
1483 <<
1484 <<
1485 }; <<
1486 <<
1487 admai <<
1488 <<
1489 <<
1490 <<
1491 <<
1492 <<
1493 }; <<
1494 <<
1495 admai <<
1496 <<
1497 <<
1498 <<
1499 <<
1500 <<
1501 }; <<
1502 }; <<
1503 }; <<
1504 <<
1505 tegra_i2s1: i2s@702d1 <<
1506 compatible = <<
1507 reg = <0x702d <<
1508 clocks = <&te <<
1509 <&te <<
1510 clock-names = <<
1511 assigned-cloc <<
1512 assigned-cloc <<
1513 assigned-cloc <<
1514 sound-name-pr <<
1515 status = "dis <<
1516 }; <<
1517 <<
1518 tegra_i2s2: i2s@702d1 <<
1519 compatible = <<
1520 reg = <0x702d <<
1521 clocks = <&te <<
1522 <&te <<
1523 clock-names = <<
1524 assigned-cloc <<
1525 assigned-cloc <<
1526 assigned-cloc <<
1527 sound-name-pr <<
1528 status = "dis <<
1529 }; <<
1530 <<
1531 tegra_i2s3: i2s@702d1 <<
1532 compatible = <<
1533 reg = <0x702d <<
1534 clocks = <&te <<
1535 <&te <<
1536 clock-names = <<
1537 assigned-cloc <<
1538 assigned-cloc <<
1539 assigned-cloc <<
1540 sound-name-pr <<
1541 status = "dis <<
1542 }; <<
1543 <<
1544 tegra_i2s4: i2s@702d1 <<
1545 compatible = <<
1546 reg = <0x702d <<
1547 clocks = <&te <<
1548 <&te <<
1549 clock-names = <<
1550 assigned-cloc <<
1551 assigned-cloc <<
1552 assigned-cloc <<
1553 sound-name-pr <<
1554 status = "dis <<
1555 }; <<
1556 <<
1557 tegra_i2s5: i2s@702d1 <<
1558 compatible = <<
1559 reg = <0x702d <<
1560 clocks = <&te <<
1561 <&te <<
1562 clock-names = <<
1563 assigned-cloc <<
1564 assigned-cloc <<
1565 assigned-cloc <<
1566 sound-name-pr <<
1567 status = "dis <<
1568 }; <<
1569 <<
1570 tegra_sfc1: sfc@702d2 <<
1571 compatible = <<
1572 reg = <0x702d <<
1573 sound-name-pr <<
1574 status = "dis <<
1575 }; <<
1576 <<
1577 tegra_sfc2: sfc@702d2 <<
1578 compatible = <<
1579 reg = <0x702d <<
1580 sound-name-pr <<
1581 status = "dis <<
1582 }; <<
1583 <<
1584 tegra_sfc3: sfc@702d2 <<
1585 compatible = <<
1586 reg = <0x702d <<
1587 sound-name-pr <<
1588 status = "dis <<
1589 }; <<
1590 <<
1591 tegra_sfc4: sfc@702d2 <<
1592 compatible = <<
1593 reg = <0x702d <<
1594 sound-name-pr <<
1595 status = "dis <<
1596 }; <<
1597 <<
1598 tegra_amx1: amx@702d3 <<
1599 compatible = <<
1600 reg = <0x702d <<
1601 sound-name-pr <<
1602 status = "dis <<
1603 }; <<
1604 <<
1605 tegra_amx2: amx@702d3 <<
1606 compatible = <<
1607 reg = <0x702d <<
1608 sound-name-pr <<
1609 status = "dis <<
1610 }; <<
1611 <<
1612 tegra_adx1: adx@702d3 <<
1613 compatible = <<
1614 reg = <0x702d <<
1615 sound-name-pr <<
1616 status = "dis <<
1617 }; <<
1618 <<
1619 tegra_adx2: adx@702d3 <<
1620 compatible = <<
1621 reg = <0x702d <<
1622 sound-name-pr <<
1623 status = "dis <<
1624 }; <<
1625 <<
1626 tegra_dmic1: dmic@702 <<
1627 compatible = <<
1628 reg = <0x702d <<
1629 clocks = <&te <<
1630 clock-names = <<
1631 assigned-cloc <<
1632 assigned-cloc <<
1633 assigned-cloc <<
1634 sound-name-pr <<
1635 status = "dis <<
1636 }; <<
1637 <<
1638 tegra_dmic2: dmic@702 <<
1639 compatible = <<
1640 reg = <0x702d <<
1641 clocks = <&te <<
1642 clock-names = <<
1643 assigned-cloc <<
1644 assigned-cloc <<
1645 assigned-cloc <<
1646 sound-name-pr <<
1647 status = "dis <<
1648 }; <<
1649 <<
1650 tegra_dmic3: dmic@702 <<
1651 compatible = <<
1652 reg = <0x702d <<
1653 clocks = <&te <<
1654 clock-names = <<
1655 assigned-cloc <<
1656 assigned-cloc <<
1657 assigned-cloc <<
1658 sound-name-pr <<
1659 status = "dis <<
1660 }; <<
1661 <<
1662 tegra_ope1: processin <<
1663 compatible = <<
1664 reg = <0x702d <<
1665 #address-cell <<
1666 #size-cells = <<
1667 ranges; <<
1668 sound-name-pr <<
1669 status = "dis <<
1670 <<
1671 equalizer@702 <<
1672 compa <<
1673 reg = <<
1674 }; <<
1675 <<
1676 dynamic-range <<
1677 compa <<
1678 reg = <<
1679 }; <<
1680 }; <<
1681 <<
1682 tegra_ope2: processin <<
1683 compatible = <<
1684 reg = <0x702d <<
1685 #address-cell <<
1686 #size-cells = <<
1687 ranges; <<
1688 sound-name-pr <<
1689 status = "dis <<
1690 <<
1691 equalizer@702 <<
1692 compa <<
1693 reg = <<
1694 }; <<
1695 <<
1696 dynamic-range <<
1697 compa <<
1698 reg = <<
1699 }; <<
1700 }; <<
1701 <<
1702 tegra_mvc1: mvc@702da <<
1703 compatible = <<
1704 reg = <0x702d <<
1705 sound-name-pr <<
1706 status = "dis <<
1707 }; <<
1708 <<
1709 tegra_mvc2: mvc@702da <<
1710 compatible = <<
1711 reg = <0x702d <<
1712 sound-name-pr <<
1713 status = "dis <<
1714 }; <<
1715 <<
1716 tegra_amixer: amixer@ <<
1717 compatible = <<
1718 reg = <0x702d <<
1719 sound-name-pr <<
1720 status = "dis <<
1721 }; <<
1722 <<
1723 ports { <<
1724 #address-cell <<
1725 #size-cells = <<
1726 <<
1727 port@0 { <<
1728 reg = <<
1729 <<
1730 xbar_ <<
1731 <<
1732 }; <<
1733 }; <<
1734 <<
1735 port@1 { <<
1736 reg = <<
1737 <<
1738 xbar_ <<
1739 <<
1740 }; <<
1741 }; <<
1742 <<
1743 port@2 { <<
1744 reg = <<
1745 <<
1746 xbar_ <<
1747 <<
1748 }; <<
1749 }; <<
1750 <<
1751 port@3 { <<
1752 reg = <<
1753 <<
1754 xbar_ <<
1755 <<
1756 }; <<
1757 }; <<
1758 <<
1759 port@4 { <<
1760 reg = <<
1761 xbar_ <<
1762 <<
1763 }; <<
1764 }; <<
1765 port@5 { <<
1766 reg = <<
1767 <<
1768 xbar_ <<
1769 <<
1770 }; <<
1771 }; <<
1772 <<
1773 port@6 { <<
1774 reg = <<
1775 <<
1776 xbar_ <<
1777 <<
1778 }; <<
1779 }; <<
1780 <<
1781 port@7 { <<
1782 reg = <<
1783 <<
1784 xbar_ <<
1785 <<
1786 }; <<
1787 }; <<
1788 <<
1789 port@8 { <<
1790 reg = <<
1791 <<
1792 xbar_ <<
1793 <<
1794 }; <<
1795 }; <<
1796 <<
1797 port@9 { <<
1798 reg = <<
1799 <<
1800 xbar_ <<
1801 <<
1802 }; <<
1803 }; <<
1804 }; <<
1805 }; <<
1806 <<
1807 adma: dma-controller@702e2000 <<
1808 compatible = "nvidia, 1249 compatible = "nvidia,tegra210-adma";
1809 reg = <0x702e2000 0x2 1250 reg = <0x702e2000 0x2000>;
1810 interrupt-parent = <& 1251 interrupt-parent = <&agic>;
1811 interrupts = <GIC_SPI 1252 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
1812 <GIC_SPI 1253 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
1813 <GIC_SPI 1254 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
1814 <GIC_SPI 1255 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
1815 <GIC_SPI 1256 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
1816 <GIC_SPI 1257 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
1817 <GIC_SPI 1258 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
1818 <GIC_SPI 1259 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
1819 <GIC_SPI 1260 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
1820 <GIC_SPI 1261 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
1821 <GIC_SPI 1262 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
1822 <GIC_SPI 1263 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
1823 <GIC_SPI 1264 <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
1824 <GIC_SPI 1265 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
1825 <GIC_SPI 1266 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
1826 <GIC_SPI 1267 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
1827 <GIC_SPI 1268 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
1828 <GIC_SPI 1269 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
1829 <GIC_SPI 1270 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
1830 <GIC_SPI 1271 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
1831 <GIC_SPI 1272 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
1832 <GIC_SPI 1273 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1833 #dma-cells = <1>; 1274 #dma-cells = <1>;
1834 clocks = <&tegra_car 1275 clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>;
1835 clock-names = "d_audi 1276 clock-names = "d_audio";
1836 status = "disabled"; 1277 status = "disabled";
1837 }; 1278 };
1838 1279
1839 agic: interrupt-controller@70 !! 1280 agic: agic@702f9000 {
1840 compatible = "nvidia, 1281 compatible = "nvidia,tegra210-agic";
1841 #interrupt-cells = <3 1282 #interrupt-cells = <3>;
1842 interrupt-controller; 1283 interrupt-controller;
1843 reg = <0x702f9000 0x1 1284 reg = <0x702f9000 0x1000>,
1844 <0x702fa000 0x2 1285 <0x702fa000 0x2000>;
1845 interrupts = <GIC_SPI 1286 interrupts = <GIC_SPI 102 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1846 clocks = <&tegra_car 1287 clocks = <&tegra_car TEGRA210_CLK_APE>;
1847 clock-names = "clk"; 1288 clock-names = "clk";
1848 status = "disabled"; 1289 status = "disabled";
1849 }; 1290 };
1850 }; 1291 };
1851 1292
1852 spi@70410000 { 1293 spi@70410000 {
1853 compatible = "nvidia,tegra210 1294 compatible = "nvidia,tegra210-qspi";
1854 reg = <0x0 0x70410000 0x0 0x1 1295 reg = <0x0 0x70410000 0x0 0x1000>;
1855 interrupts = <GIC_SPI 10 IRQ_ 1296 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1856 #address-cells = <1>; 1297 #address-cells = <1>;
1857 #size-cells = <0>; 1298 #size-cells = <0>;
1858 clocks = <&tegra_car TEGRA210 !! 1299 clocks = <&tegra_car TEGRA210_CLK_QSPI>;
1859 <&tegra_car TEGRA210 !! 1300 clock-names = "qspi";
1860 clock-names = "qspi", "qspi_o <<
1861 resets = <&tegra_car 211>; 1301 resets = <&tegra_car 211>;
>> 1302 reset-names = "qspi";
1862 dmas = <&apbdma 5>, <&apbdma 1303 dmas = <&apbdma 5>, <&apbdma 5>;
1863 dma-names = "rx", "tx"; 1304 dma-names = "rx", "tx";
1864 status = "disabled"; 1305 status = "disabled";
1865 }; 1306 };
1866 1307
1867 usb@7d000000 { 1308 usb@7d000000 {
1868 compatible = "nvidia,tegra210 !! 1309 compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci";
1869 reg = <0x0 0x7d000000 0x0 0x4 1310 reg = <0x0 0x7d000000 0x0 0x4000>;
1870 interrupts = <GIC_SPI 20 IRQ_ 1311 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1871 phy_type = "utmi"; 1312 phy_type = "utmi";
1872 clocks = <&tegra_car TEGRA210 1313 clocks = <&tegra_car TEGRA210_CLK_USBD>;
1873 clock-names = "usb"; 1314 clock-names = "usb";
1874 resets = <&tegra_car 22>; 1315 resets = <&tegra_car 22>;
1875 reset-names = "usb"; 1316 reset-names = "usb";
1876 nvidia,phy = <&phy1>; 1317 nvidia,phy = <&phy1>;
1877 status = "disabled"; 1318 status = "disabled";
1878 }; 1319 };
1879 1320
1880 phy1: usb-phy@7d000000 { 1321 phy1: usb-phy@7d000000 {
1881 compatible = "nvidia,tegra210 1322 compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy";
1882 reg = <0x0 0x7d000000 0x0 0x4 1323 reg = <0x0 0x7d000000 0x0 0x4000>,
1883 <0x0 0x7d000000 0x0 0x4 1324 <0x0 0x7d000000 0x0 0x4000>;
1884 phy_type = "utmi"; 1325 phy_type = "utmi";
1885 clocks = <&tegra_car TEGRA210 1326 clocks = <&tegra_car TEGRA210_CLK_USBD>,
1886 <&tegra_car TEGRA210 1327 <&tegra_car TEGRA210_CLK_PLL_U>,
1887 <&tegra_car TEGRA210 1328 <&tegra_car TEGRA210_CLK_USBD>;
1888 clock-names = "reg", "pll_u", 1329 clock-names = "reg", "pll_u", "utmi-pads";
1889 resets = <&tegra_car 22>, <&t 1330 resets = <&tegra_car 22>, <&tegra_car 22>;
1890 reset-names = "usb", "utmi-pa 1331 reset-names = "usb", "utmi-pads";
1891 nvidia,hssync-start-delay = < 1332 nvidia,hssync-start-delay = <0>;
1892 nvidia,idle-wait-delay = <17> 1333 nvidia,idle-wait-delay = <17>;
1893 nvidia,elastic-limit = <16>; 1334 nvidia,elastic-limit = <16>;
1894 nvidia,term-range-adj = <6>; 1335 nvidia,term-range-adj = <6>;
1895 nvidia,xcvr-setup = <9>; 1336 nvidia,xcvr-setup = <9>;
1896 nvidia,xcvr-lsfslew = <0>; 1337 nvidia,xcvr-lsfslew = <0>;
1897 nvidia,xcvr-lsrslew = <3>; 1338 nvidia,xcvr-lsrslew = <3>;
1898 nvidia,hssquelch-level = <2>; 1339 nvidia,hssquelch-level = <2>;
1899 nvidia,hsdiscon-level = <5>; 1340 nvidia,hsdiscon-level = <5>;
1900 nvidia,xcvr-hsslew = <12>; 1341 nvidia,xcvr-hsslew = <12>;
1901 nvidia,has-utmi-pad-registers 1342 nvidia,has-utmi-pad-registers;
1902 status = "disabled"; 1343 status = "disabled";
1903 }; 1344 };
1904 1345
1905 usb@7d004000 { 1346 usb@7d004000 {
1906 compatible = "nvidia,tegra210 !! 1347 compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci";
1907 reg = <0x0 0x7d004000 0x0 0x4 1348 reg = <0x0 0x7d004000 0x0 0x4000>;
1908 interrupts = <GIC_SPI 21 IRQ_ 1349 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
1909 phy_type = "utmi"; 1350 phy_type = "utmi";
1910 clocks = <&tegra_car TEGRA210 1351 clocks = <&tegra_car TEGRA210_CLK_USB2>;
1911 clock-names = "usb"; 1352 clock-names = "usb";
1912 resets = <&tegra_car 58>; 1353 resets = <&tegra_car 58>;
1913 reset-names = "usb"; 1354 reset-names = "usb";
1914 nvidia,phy = <&phy2>; 1355 nvidia,phy = <&phy2>;
1915 status = "disabled"; 1356 status = "disabled";
1916 }; 1357 };
1917 1358
1918 phy2: usb-phy@7d004000 { 1359 phy2: usb-phy@7d004000 {
1919 compatible = "nvidia,tegra210 1360 compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy";
1920 reg = <0x0 0x7d004000 0x0 0x4 1361 reg = <0x0 0x7d004000 0x0 0x4000>,
1921 <0x0 0x7d000000 0x0 0x4 1362 <0x0 0x7d000000 0x0 0x4000>;
1922 phy_type = "utmi"; 1363 phy_type = "utmi";
1923 clocks = <&tegra_car TEGRA210 1364 clocks = <&tegra_car TEGRA210_CLK_USB2>,
1924 <&tegra_car TEGRA210 1365 <&tegra_car TEGRA210_CLK_PLL_U>,
1925 <&tegra_car TEGRA210 1366 <&tegra_car TEGRA210_CLK_USBD>;
1926 clock-names = "reg", "pll_u", 1367 clock-names = "reg", "pll_u", "utmi-pads";
1927 resets = <&tegra_car 58>, <&t 1368 resets = <&tegra_car 58>, <&tegra_car 22>;
1928 reset-names = "usb", "utmi-pa 1369 reset-names = "usb", "utmi-pads";
1929 nvidia,hssync-start-delay = < 1370 nvidia,hssync-start-delay = <0>;
1930 nvidia,idle-wait-delay = <17> 1371 nvidia,idle-wait-delay = <17>;
1931 nvidia,elastic-limit = <16>; 1372 nvidia,elastic-limit = <16>;
1932 nvidia,term-range-adj = <6>; 1373 nvidia,term-range-adj = <6>;
1933 nvidia,xcvr-setup = <9>; 1374 nvidia,xcvr-setup = <9>;
1934 nvidia,xcvr-lsfslew = <0>; 1375 nvidia,xcvr-lsfslew = <0>;
1935 nvidia,xcvr-lsrslew = <3>; 1376 nvidia,xcvr-lsrslew = <3>;
1936 nvidia,hssquelch-level = <2>; 1377 nvidia,hssquelch-level = <2>;
1937 nvidia,hsdiscon-level = <5>; 1378 nvidia,hsdiscon-level = <5>;
1938 nvidia,xcvr-hsslew = <12>; 1379 nvidia,xcvr-hsslew = <12>;
1939 status = "disabled"; 1380 status = "disabled";
1940 }; 1381 };
1941 1382
1942 cpus { 1383 cpus {
1943 #address-cells = <1>; 1384 #address-cells = <1>;
1944 #size-cells = <0>; 1385 #size-cells = <0>;
1945 1386
1946 cpu@0 { 1387 cpu@0 {
1947 device_type = "cpu"; 1388 device_type = "cpu";
1948 compatible = "arm,cor 1389 compatible = "arm,cortex-a57";
1949 reg = <0>; 1390 reg = <0>;
1950 clocks = <&tegra_car 1391 clocks = <&tegra_car TEGRA210_CLK_CCLK_G>,
1951 <&tegra_car 1392 <&tegra_car TEGRA210_CLK_PLL_X>,
1952 <&tegra_car 1393 <&tegra_car TEGRA210_CLK_PLL_P_OUT4>,
1953 <&dfll>; 1394 <&dfll>;
1954 clock-names = "cpu_g" 1395 clock-names = "cpu_g", "pll_x", "pll_p", "dfll";
1955 clock-latency = <3000 1396 clock-latency = <300000>;
1956 cpu-idle-states = <&C 1397 cpu-idle-states = <&CPU_SLEEP>;
1957 next-level-cache = <& 1398 next-level-cache = <&L2>;
1958 }; 1399 };
1959 1400
1960 cpu@1 { 1401 cpu@1 {
1961 device_type = "cpu"; 1402 device_type = "cpu";
1962 compatible = "arm,cor 1403 compatible = "arm,cortex-a57";
1963 reg = <1>; 1404 reg = <1>;
1964 cpu-idle-states = <&C 1405 cpu-idle-states = <&CPU_SLEEP>;
1965 next-level-cache = <& 1406 next-level-cache = <&L2>;
1966 }; 1407 };
1967 1408
1968 cpu@2 { 1409 cpu@2 {
1969 device_type = "cpu"; 1410 device_type = "cpu";
1970 compatible = "arm,cor 1411 compatible = "arm,cortex-a57";
1971 reg = <2>; 1412 reg = <2>;
1972 cpu-idle-states = <&C 1413 cpu-idle-states = <&CPU_SLEEP>;
1973 next-level-cache = <& 1414 next-level-cache = <&L2>;
1974 }; 1415 };
1975 1416
1976 cpu@3 { 1417 cpu@3 {
1977 device_type = "cpu"; 1418 device_type = "cpu";
1978 compatible = "arm,cor 1419 compatible = "arm,cortex-a57";
1979 reg = <3>; 1420 reg = <3>;
1980 cpu-idle-states = <&C 1421 cpu-idle-states = <&CPU_SLEEP>;
1981 next-level-cache = <& 1422 next-level-cache = <&L2>;
1982 }; 1423 };
1983 1424
1984 idle-states { 1425 idle-states {
1985 entry-method = "psci" 1426 entry-method = "psci";
1986 1427
1987 CPU_SLEEP: cpu-sleep 1428 CPU_SLEEP: cpu-sleep {
1988 compatible = 1429 compatible = "arm,idle-state";
1989 arm,psci-susp 1430 arm,psci-suspend-param = <0x40000007>;
1990 entry-latency 1431 entry-latency-us = <100>;
1991 exit-latency- 1432 exit-latency-us = <30>;
1992 min-residency 1433 min-residency-us = <1000>;
1993 wakeup-latenc 1434 wakeup-latency-us = <130>;
1994 idle-state-na 1435 idle-state-name = "cpu-sleep";
1995 status = "dis 1436 status = "disabled";
1996 }; 1437 };
1997 }; 1438 };
1998 1439
1999 L2: l2-cache { 1440 L2: l2-cache {
2000 compatible = "cache"; 1441 compatible = "cache";
2001 cache-level = <2>; <<
2002 cache-unified; <<
2003 }; 1442 };
2004 }; 1443 };
2005 1444
2006 pmu { 1445 pmu {
2007 compatible = "arm,cortex-a57- !! 1446 compatible = "arm,armv8-pmuv3";
2008 interrupts = <GIC_SPI 144 IRQ 1447 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
2009 <GIC_SPI 145 IRQ 1448 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
2010 <GIC_SPI 146 IRQ 1449 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
2011 <GIC_SPI 147 IRQ 1450 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
2012 interrupt-affinity = <&{/cpus 1451 interrupt-affinity = <&{/cpus/cpu@0} &{/cpus/cpu@1}
2013 &{/cpus 1452 &{/cpus/cpu@2} &{/cpus/cpu@3}>;
2014 }; 1453 };
2015 1454
2016 sound { !! 1455 timer {
2017 status = "disabled"; !! 1456 compatible = "arm,armv8-timer";
>> 1457 interrupts = <GIC_PPI 13
>> 1458 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
>> 1459 <GIC_PPI 14
>> 1460 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
>> 1461 <GIC_PPI 11
>> 1462 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
>> 1463 <GIC_PPI 10
>> 1464 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
>> 1465 interrupt-parent = <&gic>;
>> 1466 arm,no-tick-in-suspend;
>> 1467 };
2018 1468
2019 clocks = <&tegra_car TEGRA210 !! 1469 soctherm: thermal-sensor@700e2000 {
2020 <&tegra_car TEGRA210 !! 1470 compatible = "nvidia,tegra210-soctherm";
2021 clock-names = "pll_a", "plla_ !! 1471 reg = <0x0 0x700e2000 0x0 0x600 /* SOC_THERM reg_base */
2022 !! 1472 0x0 0x60006000 0x0 0x400>; /* CAR reg_base */
2023 assigned-clocks = <&tegra_car !! 1473 reg-names = "soctherm-reg", "car-reg";
2024 <&tegra_car !! 1474 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
2025 <&tegra_car !! 1475 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
2026 assigned-clock-parents = <0>, !! 1476 interrupt-names = "thermal", "edp";
2027 assigned-clock-rates = <36864 !! 1477 clocks = <&tegra_car TEGRA210_CLK_TSENSOR>,
>> 1478 <&tegra_car TEGRA210_CLK_SOC_THERM>;
>> 1479 clock-names = "tsensor", "soctherm";
>> 1480 resets = <&tegra_car 78>;
>> 1481 reset-names = "soctherm";
>> 1482 #thermal-sensor-cells = <1>;
>> 1483
>> 1484 throttle-cfgs {
>> 1485 throttle_heavy: heavy {
>> 1486 nvidia,priority = <100>;
>> 1487 nvidia,cpu-throt-percent = <85>;
>> 1488
>> 1489 #cooling-cells = <2>;
>> 1490 };
>> 1491 };
2028 }; 1492 };
2029 1493
2030 thermal-zones { 1494 thermal-zones {
2031 cpu-thermal { !! 1495 cpu {
2032 polling-delay-passive 1496 polling-delay-passive = <1000>;
2033 polling-delay = <0>; 1497 polling-delay = <0>;
2034 1498
2035 thermal-sensors = 1499 thermal-sensors =
2036 <&soctherm TE 1500 <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>;
2037 1501
2038 trips { 1502 trips {
2039 cpu-shutdown- 1503 cpu-shutdown-trip {
2040 tempe 1504 temperature = <102500>;
2041 hyste 1505 hysteresis = <0>;
2042 type 1506 type = "critical";
2043 }; 1507 };
2044 1508
2045 cpu_throttle_ 1509 cpu_throttle_trip: throttle-trip {
2046 tempe 1510 temperature = <98500>;
2047 hyste 1511 hysteresis = <1000>;
2048 type 1512 type = "hot";
2049 }; 1513 };
2050 }; 1514 };
2051 1515
2052 cooling-maps { 1516 cooling-maps {
2053 map0 { 1517 map0 {
2054 trip 1518 trip = <&cpu_throttle_trip>;
2055 cooli 1519 cooling-device = <&throttle_heavy 1 1>;
2056 }; 1520 };
2057 }; 1521 };
2058 }; 1522 };
2059 1523
2060 mem-thermal { !! 1524 mem {
2061 polling-delay-passive 1525 polling-delay-passive = <0>;
2062 polling-delay = <0>; 1526 polling-delay = <0>;
2063 1527
2064 thermal-sensors = 1528 thermal-sensors =
2065 <&soctherm TE 1529 <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>;
2066 1530
2067 trips { 1531 trips {
2068 dram_nominal: <<
2069 tempe <<
2070 hyste <<
2071 type <<
2072 }; <<
2073 <<
2074 dram_throttle <<
2075 tempe <<
2076 hyste <<
2077 type <<
2078 }; <<
2079 <<
2080 mem-hot-trip <<
2081 tempe <<
2082 hyste <<
2083 type <<
2084 }; <<
2085 <<
2086 mem-shutdown- 1532 mem-shutdown-trip {
2087 tempe 1533 temperature = <103000>;
2088 hyste 1534 hysteresis = <0>;
2089 type 1535 type = "critical";
2090 }; 1536 };
2091 }; 1537 };
2092 1538
2093 cooling-maps { 1539 cooling-maps {
2094 dram-passive !! 1540 /*
2095 cooli !! 1541 * There are currently no cooling maps,
2096 trip !! 1542 * because there are no cooling devices.
2097 }; !! 1543 */
2098 <<
2099 dram-active { <<
2100 cooli <<
2101 trip <<
2102 }; <<
2103 }; 1544 };
2104 }; 1545 };
2105 1546
2106 gpu-thermal { !! 1547 gpu {
2107 polling-delay-passive 1548 polling-delay-passive = <1000>;
2108 polling-delay = <0>; 1549 polling-delay = <0>;
2109 1550
2110 thermal-sensors = 1551 thermal-sensors =
2111 <&soctherm TE 1552 <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>;
2112 1553
2113 trips { 1554 trips {
2114 gpu-shutdown- 1555 gpu-shutdown-trip {
2115 tempe 1556 temperature = <103000>;
2116 hyste 1557 hysteresis = <0>;
2117 type 1558 type = "critical";
2118 }; 1559 };
2119 1560
2120 gpu_throttle_ 1561 gpu_throttle_trip: throttle-trip {
2121 tempe 1562 temperature = <100000>;
2122 hyste 1563 hysteresis = <1000>;
2123 type 1564 type = "hot";
2124 }; 1565 };
2125 }; 1566 };
2126 1567
2127 cooling-maps { 1568 cooling-maps {
2128 map0 { 1569 map0 {
2129 trip 1570 trip = <&gpu_throttle_trip>;
2130 cooli 1571 cooling-device = <&throttle_heavy 1 1>;
2131 }; 1572 };
2132 }; 1573 };
2133 }; 1574 };
2134 1575
2135 pllx-thermal { !! 1576 pllx {
2136 polling-delay-passive 1577 polling-delay-passive = <0>;
2137 polling-delay = <0>; 1578 polling-delay = <0>;
2138 1579
2139 thermal-sensors = 1580 thermal-sensors =
2140 <&soctherm TE 1581 <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>;
2141 1582
2142 trips { 1583 trips {
2143 pllx-shutdown 1584 pllx-shutdown-trip {
2144 tempe 1585 temperature = <103000>;
2145 hyste 1586 hysteresis = <0>;
2146 type 1587 type = "critical";
2147 }; 1588 };
2148 <<
2149 pllx-throttle <<
2150 tempe <<
2151 hyste <<
2152 type <<
2153 }; <<
2154 }; 1589 };
2155 1590
2156 cooling-maps { 1591 cooling-maps {
2157 /* 1592 /*
2158 * There are 1593 * There are currently no cooling maps,
2159 * because th 1594 * because there are no cooling devices.
2160 */ 1595 */
2161 }; 1596 };
2162 }; 1597 };
2163 }; <<
2164 <<
2165 timer { <<
2166 compatible = "arm,armv8-timer <<
2167 interrupts = <GIC_PPI 13 <<
2168 (GIC_CPU_MASK <<
2169 <GIC_PPI 14 <<
2170 (GIC_CPU_MASK <<
2171 <GIC_PPI 11 <<
2172 (GIC_CPU_MASK <<
2173 <GIC_PPI 10 <<
2174 (GIC_CPU_MASK <<
2175 interrupt-parent = <&gic>; <<
2176 arm,no-tick-in-suspend; <<
2177 }; 1598 };
2178 }; 1599 };
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