1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra210-car.h> 2 #include <dt-bindings/clock/tegra210-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h> 3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra210-mc.h> 4 #include <dt-bindings/memory/tegra210-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h> 5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra-io 6 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
7 #include <dt-bindings/reset/tegra210-car.h> 7 #include <dt-bindings/reset/tegra210-car.h>
8 #include <dt-bindings/interrupt-controller/arm 8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/thermal/tegra124-socther 9 #include <dt-bindings/thermal/tegra124-soctherm.h>
10 #include <dt-bindings/soc/tegra-pmc.h> 10 #include <dt-bindings/soc/tegra-pmc.h>
11 11
12 / { 12 / {
13 compatible = "nvidia,tegra210"; 13 compatible = "nvidia,tegra210";
14 interrupt-parent = <&lic>; 14 interrupt-parent = <&lic>;
15 #address-cells = <2>; 15 #address-cells = <2>;
16 #size-cells = <2>; 16 #size-cells = <2>;
17 17
18 pcie@1003000 { 18 pcie@1003000 {
19 compatible = "nvidia,tegra210- 19 compatible = "nvidia,tegra210-pcie";
20 device_type = "pci"; 20 device_type = "pci";
21 reg = <0x0 0x01003000 0x0 0x00 21 reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */
22 <0x0 0x01003800 0x0 0x00 22 <0x0 0x01003800 0x0 0x00000800>, /* AFI registers */
23 <0x0 0x02000000 0x0 0x10 23 <0x0 0x02000000 0x0 0x10000000>; /* configuration space */
24 reg-names = "pads", "afi", "cs 24 reg-names = "pads", "afi", "cs";
25 interrupts = <GIC_SPI 98 IRQ_T 25 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
26 <GIC_SPI 99 IRQ_T 26 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
27 interrupt-names = "intr", "msi 27 interrupt-names = "intr", "msi";
28 28
29 #interrupt-cells = <1>; 29 #interrupt-cells = <1>;
30 interrupt-map-mask = <0 0 0 0> 30 interrupt-map-mask = <0 0 0 0>;
31 interrupt-map = <0 0 0 0 &gic 31 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
32 32
33 bus-range = <0x00 0xff>; 33 bus-range = <0x00 0xff>;
34 #address-cells = <3>; 34 #address-cells = <3>;
35 #size-cells = <2>; 35 #size-cells = <2>;
36 36
37 ranges = <0x02000000 0 0x01000 37 ranges = <0x02000000 0 0x01000000 0x0 0x01000000 0 0x00001000>, /* port 0 configuration space */
38 <0x02000000 0 0x01001 38 <0x02000000 0 0x01001000 0x0 0x01001000 0 0x00001000>, /* port 1 configuration space */
39 <0x01000000 0 0x0 39 <0x01000000 0 0x0 0x0 0x12000000 0 0x00010000>, /* downstream I/O (64 KiB) */
40 <0x02000000 0 0x13000 40 <0x02000000 0 0x13000000 0x0 0x13000000 0 0x0d000000>, /* non-prefetchable memory (208 MiB) */
41 <0x42000000 0 0x20000 41 <0x42000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
42 42
43 clocks = <&tegra_car TEGRA210_ 43 clocks = <&tegra_car TEGRA210_CLK_PCIE>,
44 <&tegra_car TEGRA210_ 44 <&tegra_car TEGRA210_CLK_AFI>,
45 <&tegra_car TEGRA210_ 45 <&tegra_car TEGRA210_CLK_PLL_E>,
46 <&tegra_car TEGRA210_ 46 <&tegra_car TEGRA210_CLK_CML0>;
47 clock-names = "pex", "afi", "p 47 clock-names = "pex", "afi", "pll_e", "cml";
48 resets = <&tegra_car 70>, 48 resets = <&tegra_car 70>,
49 <&tegra_car 72>, 49 <&tegra_car 72>,
50 <&tegra_car 74>; 50 <&tegra_car 74>;
51 reset-names = "pex", "afi", "p 51 reset-names = "pex", "afi", "pcie_x";
52 52
53 pinctrl-names = "default", "id 53 pinctrl-names = "default", "idle";
54 pinctrl-0 = <&pex_dpd_disable> 54 pinctrl-0 = <&pex_dpd_disable>;
55 pinctrl-1 = <&pex_dpd_enable>; 55 pinctrl-1 = <&pex_dpd_enable>;
56 56
57 status = "disabled"; 57 status = "disabled";
58 58
59 pci@1,0 { 59 pci@1,0 {
60 device_type = "pci"; 60 device_type = "pci";
61 assigned-addresses = < 61 assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
62 reg = <0x000800 0 0 0 62 reg = <0x000800 0 0 0 0>;
63 bus-range = <0x00 0xff 63 bus-range = <0x00 0xff>;
64 status = "disabled"; 64 status = "disabled";
65 65
66 #address-cells = <3>; 66 #address-cells = <3>;
67 #size-cells = <2>; 67 #size-cells = <2>;
68 ranges; 68 ranges;
69 69
70 nvidia,num-lanes = <4> 70 nvidia,num-lanes = <4>;
71 }; 71 };
72 72
73 pci@2,0 { 73 pci@2,0 {
74 device_type = "pci"; 74 device_type = "pci";
75 assigned-addresses = < 75 assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
76 reg = <0x001000 0 0 0 76 reg = <0x001000 0 0 0 0>;
77 bus-range = <0x00 0xff 77 bus-range = <0x00 0xff>;
78 status = "disabled"; 78 status = "disabled";
79 79
80 #address-cells = <3>; 80 #address-cells = <3>;
81 #size-cells = <2>; 81 #size-cells = <2>;
82 ranges; 82 ranges;
83 83
84 nvidia,num-lanes = <1> 84 nvidia,num-lanes = <1>;
85 }; 85 };
86 }; 86 };
87 87
88 host1x@50000000 { 88 host1x@50000000 {
89 compatible = "nvidia,tegra210- 89 compatible = "nvidia,tegra210-host1x";
90 reg = <0x0 0x50000000 0x0 0x00 90 reg = <0x0 0x50000000 0x0 0x00034000>;
91 interrupts = <GIC_SPI 65 IRQ_T 91 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
92 <GIC_SPI 67 IRQ_T 92 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
93 interrupt-names = "syncpt", "h 93 interrupt-names = "syncpt", "host1x";
94 clocks = <&tegra_car TEGRA210_ 94 clocks = <&tegra_car TEGRA210_CLK_HOST1X>;
95 clock-names = "host1x"; 95 clock-names = "host1x";
96 resets = <&tegra_car 28>, <&mc !! 96 resets = <&tegra_car 28>;
97 reset-names = "host1x", "mc"; !! 97 reset-names = "host1x";
98 98
99 #address-cells = <2>; 99 #address-cells = <2>;
100 #size-cells = <2>; 100 #size-cells = <2>;
101 101
102 ranges = <0x0 0x54000000 0x0 0 102 ranges = <0x0 0x54000000 0x0 0x54000000 0x0 0x01000000>;
103 103
104 iommus = <&mc TEGRA_SWGROUP_HC 104 iommus = <&mc TEGRA_SWGROUP_HC>;
105 105
106 dpaux1: dpaux@54040000 { 106 dpaux1: dpaux@54040000 {
107 compatible = "nvidia,t 107 compatible = "nvidia,tegra210-dpaux";
108 reg = <0x0 0x54040000 108 reg = <0x0 0x54040000 0x0 0x00040000>;
109 interrupts = <GIC_SPI 109 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
110 clocks = <&tegra_car T 110 clocks = <&tegra_car TEGRA210_CLK_DPAUX1>,
111 <&tegra_car T 111 <&tegra_car TEGRA210_CLK_PLL_DP>;
112 clock-names = "dpaux", 112 clock-names = "dpaux", "parent";
113 resets = <&tegra_car 2 113 resets = <&tegra_car 207>;
114 reset-names = "dpaux"; 114 reset-names = "dpaux";
115 power-domains = <&pd_s 115 power-domains = <&pd_sor>;
116 status = "disabled"; 116 status = "disabled";
117 117
118 state_dpaux1_aux: pinm 118 state_dpaux1_aux: pinmux-aux {
119 groups = "dpau 119 groups = "dpaux-io";
120 function = "au 120 function = "aux";
121 }; 121 };
122 122
123 state_dpaux1_i2c: pinm 123 state_dpaux1_i2c: pinmux-i2c {
124 groups = "dpau 124 groups = "dpaux-io";
125 function = "i2 125 function = "i2c";
126 }; 126 };
127 127
128 state_dpaux1_off: pinm 128 state_dpaux1_off: pinmux-off {
129 groups = "dpau 129 groups = "dpaux-io";
130 function = "of 130 function = "off";
131 }; 131 };
132 132
133 i2c-bus { 133 i2c-bus {
134 #address-cells 134 #address-cells = <1>;
135 #size-cells = 135 #size-cells = <0>;
136 }; 136 };
137 }; 137 };
138 138
139 vi@54080000 { 139 vi@54080000 {
140 compatible = "nvidia,t 140 compatible = "nvidia,tegra210-vi";
141 reg = <0x0 0x54080000 141 reg = <0x0 0x54080000 0x0 0x700>;
142 interrupts = <GIC_SPI 142 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
143 status = "disabled"; 143 status = "disabled";
144 assigned-clocks = <&te 144 assigned-clocks = <&tegra_car TEGRA210_CLK_VI>;
145 assigned-clock-parents 145 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
146 146
147 clocks = <&tegra_car T 147 clocks = <&tegra_car TEGRA210_CLK_VI>;
148 power-domains = <&pd_v 148 power-domains = <&pd_venc>;
149 149
150 #address-cells = <1>; 150 #address-cells = <1>;
151 #size-cells = <1>; 151 #size-cells = <1>;
152 152
153 ranges = <0x0 0x0 0x54 153 ranges = <0x0 0x0 0x54080000 0x2000>;
154 154
155 csi@838 { 155 csi@838 {
156 compatible = " 156 compatible = "nvidia,tegra210-csi";
157 reg = <0x838 0 157 reg = <0x838 0x1300>;
158 status = "disa 158 status = "disabled";
159 assigned-clock 159 assigned-clocks = <&tegra_car TEGRA210_CLK_CILAB>,
160 160 <&tegra_car TEGRA210_CLK_CILCD>,
161 161 <&tegra_car TEGRA210_CLK_CILE>,
162 162 <&tegra_car TEGRA210_CLK_CSI_TPG>;
163 assigned-clock 163 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>,
164 164 <&tegra_car TEGRA210_CLK_PLL_P>,
165 165 <&tegra_car TEGRA210_CLK_PLL_P>;
166 assigned-clock 166 assigned-clock-rates = <102000000>,
167 167 <102000000>,
168 168 <102000000>,
169 169 <972000000>;
170 170
171 clocks = <&teg 171 clocks = <&tegra_car TEGRA210_CLK_CSI>,
172 <&teg 172 <&tegra_car TEGRA210_CLK_CILAB>,
173 <&teg 173 <&tegra_car TEGRA210_CLK_CILCD>,
174 <&teg 174 <&tegra_car TEGRA210_CLK_CILE>,
175 <&teg 175 <&tegra_car TEGRA210_CLK_CSI_TPG>;
176 clock-names = 176 clock-names = "csi", "cilab", "cilcd", "cile", "csi_tpg";
177 power-domains 177 power-domains = <&pd_sor>;
178 }; 178 };
179 }; 179 };
180 180
181 tsec@54100000 { 181 tsec@54100000 {
182 compatible = "nvidia,t 182 compatible = "nvidia,tegra210-tsec";
183 reg = <0x0 0x54100000 183 reg = <0x0 0x54100000 0x0 0x00040000>;
184 interrupts = <GIC_SPI <<
185 clocks = <&tegra_car T <<
186 clock-names = "tsec"; <<
187 resets = <&tegra_car 8 <<
188 reset-names = "tsec"; <<
189 status = "disabled"; <<
190 }; 184 };
191 185
192 dc@54200000 { 186 dc@54200000 {
193 compatible = "nvidia,t 187 compatible = "nvidia,tegra210-dc";
194 reg = <0x0 0x54200000 188 reg = <0x0 0x54200000 0x0 0x00040000>;
195 interrupts = <GIC_SPI 189 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
196 clocks = <&tegra_car T 190 clocks = <&tegra_car TEGRA210_CLK_DISP1>;
197 clock-names = "dc"; 191 clock-names = "dc";
198 resets = <&tegra_car 2 192 resets = <&tegra_car 27>;
199 reset-names = "dc"; 193 reset-names = "dc";
200 194
201 iommus = <&mc TEGRA_SW 195 iommus = <&mc TEGRA_SWGROUP_DC>;
202 196
203 nvidia,outputs = <&dsi <<
204 nvidia,head = <0>; 197 nvidia,head = <0>;
205 }; 198 };
206 199
207 dc@54240000 { 200 dc@54240000 {
208 compatible = "nvidia,t 201 compatible = "nvidia,tegra210-dc";
209 reg = <0x0 0x54240000 202 reg = <0x0 0x54240000 0x0 0x00040000>;
210 interrupts = <GIC_SPI 203 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
211 clocks = <&tegra_car T 204 clocks = <&tegra_car TEGRA210_CLK_DISP2>;
212 clock-names = "dc"; 205 clock-names = "dc";
213 resets = <&tegra_car 2 206 resets = <&tegra_car 26>;
214 reset-names = "dc"; 207 reset-names = "dc";
215 208
216 iommus = <&mc TEGRA_SW 209 iommus = <&mc TEGRA_SWGROUP_DCB>;
217 210
218 nvidia,outputs = <&dsi <<
219 nvidia,head = <1>; 211 nvidia,head = <1>;
220 }; 212 };
221 213
222 dsia: dsi@54300000 { !! 214 dsi@54300000 {
223 compatible = "nvidia,t 215 compatible = "nvidia,tegra210-dsi";
224 reg = <0x0 0x54300000 216 reg = <0x0 0x54300000 0x0 0x00040000>;
225 clocks = <&tegra_car T 217 clocks = <&tegra_car TEGRA210_CLK_DSIA>,
226 <&tegra_car T 218 <&tegra_car TEGRA210_CLK_DSIALP>,
227 <&tegra_car T 219 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>;
228 clock-names = "dsi", " 220 clock-names = "dsi", "lp", "parent";
229 resets = <&tegra_car 4 221 resets = <&tegra_car 48>;
230 reset-names = "dsi"; 222 reset-names = "dsi";
231 power-domains = <&pd_s 223 power-domains = <&pd_sor>;
232 nvidia,mipi-calibrate 224 nvidia,mipi-calibrate = <&mipi 0x0c0>; /* DSIA & DSIB pads */
233 225
234 status = "disabled"; 226 status = "disabled";
235 227
236 #address-cells = <1>; 228 #address-cells = <1>;
237 #size-cells = <0>; 229 #size-cells = <0>;
238 }; 230 };
239 231
240 vic@54340000 { 232 vic@54340000 {
241 compatible = "nvidia,t 233 compatible = "nvidia,tegra210-vic";
242 reg = <0x0 0x54340000 234 reg = <0x0 0x54340000 0x0 0x00040000>;
243 interrupts = <GIC_SPI 235 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
244 clocks = <&tegra_car T 236 clocks = <&tegra_car TEGRA210_CLK_VIC03>;
245 clock-names = "vic"; 237 clock-names = "vic";
246 resets = <&tegra_car 1 238 resets = <&tegra_car 178>;
247 reset-names = "vic"; 239 reset-names = "vic";
248 240
249 iommus = <&mc TEGRA_SW 241 iommus = <&mc TEGRA_SWGROUP_VIC>;
250 power-domains = <&pd_v 242 power-domains = <&pd_vic>;
251 }; 243 };
252 244
253 nvjpg@54380000 { 245 nvjpg@54380000 {
254 compatible = "nvidia,t 246 compatible = "nvidia,tegra210-nvjpg";
255 reg = <0x0 0x54380000 247 reg = <0x0 0x54380000 0x0 0x00040000>;
256 status = "disabled"; 248 status = "disabled";
257 }; 249 };
258 250
259 dsib: dsi@54400000 { !! 251 dsi@54400000 {
260 compatible = "nvidia,t 252 compatible = "nvidia,tegra210-dsi";
261 reg = <0x0 0x54400000 253 reg = <0x0 0x54400000 0x0 0x00040000>;
262 clocks = <&tegra_car T 254 clocks = <&tegra_car TEGRA210_CLK_DSIB>,
263 <&tegra_car T 255 <&tegra_car TEGRA210_CLK_DSIBLP>,
264 <&tegra_car T 256 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>;
265 clock-names = "dsi", " 257 clock-names = "dsi", "lp", "parent";
266 resets = <&tegra_car 8 258 resets = <&tegra_car 82>;
267 reset-names = "dsi"; 259 reset-names = "dsi";
268 power-domains = <&pd_s 260 power-domains = <&pd_sor>;
269 nvidia,mipi-calibrate 261 nvidia,mipi-calibrate = <&mipi 0x300>; /* DSIC & DSID pads */
270 262
271 status = "disabled"; 263 status = "disabled";
272 264
273 #address-cells = <1>; 265 #address-cells = <1>;
274 #size-cells = <0>; 266 #size-cells = <0>;
275 }; 267 };
276 268
277 nvdec@54480000 { 269 nvdec@54480000 {
278 compatible = "nvidia,t 270 compatible = "nvidia,tegra210-nvdec";
279 reg = <0x0 0x54480000 271 reg = <0x0 0x54480000 0x0 0x00040000>;
280 status = "disabled"; 272 status = "disabled";
281 }; 273 };
282 274
283 nvenc@544c0000 { 275 nvenc@544c0000 {
284 compatible = "nvidia,t 276 compatible = "nvidia,tegra210-nvenc";
285 reg = <0x0 0x544c0000 277 reg = <0x0 0x544c0000 0x0 0x00040000>;
286 status = "disabled"; 278 status = "disabled";
287 }; 279 };
288 280
289 tsec@54500000 { 281 tsec@54500000 {
290 compatible = "nvidia,t 282 compatible = "nvidia,tegra210-tsec";
291 reg = <0x0 0x54500000 283 reg = <0x0 0x54500000 0x0 0x00040000>;
292 interrupts = <GIC_SPI <<
293 clocks = <&tegra_car T <<
294 clock-names = "tsec"; <<
295 resets = <&tegra_car 2 <<
296 reset-names = "tsec"; <<
297 status = "disabled"; 284 status = "disabled";
298 }; 285 };
299 286
300 sor0: sor@54540000 { !! 287 sor@54540000 {
301 compatible = "nvidia,t 288 compatible = "nvidia,tegra210-sor";
302 reg = <0x0 0x54540000 289 reg = <0x0 0x54540000 0x0 0x00040000>;
303 interrupts = <GIC_SPI 290 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
304 clocks = <&tegra_car T 291 clocks = <&tegra_car TEGRA210_CLK_SOR0>,
305 <&tegra_car T 292 <&tegra_car TEGRA210_CLK_SOR0_OUT>,
306 <&tegra_car T 293 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>,
307 <&tegra_car T 294 <&tegra_car TEGRA210_CLK_PLL_DP>,
308 <&tegra_car T 295 <&tegra_car TEGRA210_CLK_SOR_SAFE>;
309 clock-names = "sor", " 296 clock-names = "sor", "out", "parent", "dp", "safe";
310 resets = <&tegra_car 1 297 resets = <&tegra_car 182>;
311 reset-names = "sor"; 298 reset-names = "sor";
312 pinctrl-0 = <&state_dp 299 pinctrl-0 = <&state_dpaux_aux>;
313 pinctrl-1 = <&state_dp 300 pinctrl-1 = <&state_dpaux_i2c>;
314 pinctrl-2 = <&state_dp 301 pinctrl-2 = <&state_dpaux_off>;
315 pinctrl-names = "aux", 302 pinctrl-names = "aux", "i2c", "off";
316 power-domains = <&pd_s 303 power-domains = <&pd_sor>;
317 status = "disabled"; 304 status = "disabled";
318 }; 305 };
319 306
320 sor1: sor@54580000 { !! 307 sor@54580000 {
321 compatible = "nvidia,t 308 compatible = "nvidia,tegra210-sor1";
322 reg = <0x0 0x54580000 309 reg = <0x0 0x54580000 0x0 0x00040000>;
323 interrupts = <GIC_SPI 310 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
324 clocks = <&tegra_car T 311 clocks = <&tegra_car TEGRA210_CLK_SOR1>,
325 <&tegra_car T 312 <&tegra_car TEGRA210_CLK_SOR1_OUT>,
326 <&tegra_car T 313 <&tegra_car TEGRA210_CLK_PLL_D2_OUT0>,
327 <&tegra_car T 314 <&tegra_car TEGRA210_CLK_PLL_DP>,
328 <&tegra_car T 315 <&tegra_car TEGRA210_CLK_SOR_SAFE>;
329 clock-names = "sor", " 316 clock-names = "sor", "out", "parent", "dp", "safe";
330 resets = <&tegra_car 1 317 resets = <&tegra_car 183>;
331 reset-names = "sor"; 318 reset-names = "sor";
332 pinctrl-0 = <&state_dp 319 pinctrl-0 = <&state_dpaux1_aux>;
333 pinctrl-1 = <&state_dp 320 pinctrl-1 = <&state_dpaux1_i2c>;
334 pinctrl-2 = <&state_dp 321 pinctrl-2 = <&state_dpaux1_off>;
335 pinctrl-names = "aux", 322 pinctrl-names = "aux", "i2c", "off";
336 power-domains = <&pd_s 323 power-domains = <&pd_sor>;
337 status = "disabled"; 324 status = "disabled";
338 }; 325 };
339 326
340 dpaux: dpaux@545c0000 { 327 dpaux: dpaux@545c0000 {
341 compatible = "nvidia,t 328 compatible = "nvidia,tegra210-dpaux";
342 reg = <0x0 0x545c0000 329 reg = <0x0 0x545c0000 0x0 0x00040000>;
343 interrupts = <GIC_SPI 330 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
344 clocks = <&tegra_car T 331 clocks = <&tegra_car TEGRA210_CLK_DPAUX>,
345 <&tegra_car T 332 <&tegra_car TEGRA210_CLK_PLL_DP>;
346 clock-names = "dpaux", 333 clock-names = "dpaux", "parent";
347 resets = <&tegra_car 1 334 resets = <&tegra_car 181>;
348 reset-names = "dpaux"; 335 reset-names = "dpaux";
349 power-domains = <&pd_s 336 power-domains = <&pd_sor>;
350 status = "disabled"; 337 status = "disabled";
351 338
352 state_dpaux_aux: pinmu 339 state_dpaux_aux: pinmux-aux {
353 groups = "dpau 340 groups = "dpaux-io";
354 function = "au 341 function = "aux";
355 }; 342 };
356 343
357 state_dpaux_i2c: pinmu 344 state_dpaux_i2c: pinmux-i2c {
358 groups = "dpau 345 groups = "dpaux-io";
359 function = "i2 346 function = "i2c";
360 }; 347 };
361 348
362 state_dpaux_off: pinmu 349 state_dpaux_off: pinmux-off {
363 groups = "dpau 350 groups = "dpaux-io";
364 function = "of 351 function = "off";
365 }; 352 };
366 353
367 i2c-bus { 354 i2c-bus {
368 #address-cells 355 #address-cells = <1>;
369 #size-cells = 356 #size-cells = <0>;
370 }; 357 };
371 }; 358 };
372 359
373 isp@54600000 { 360 isp@54600000 {
374 compatible = "nvidia,t 361 compatible = "nvidia,tegra210-isp";
375 reg = <0x0 0x54600000 362 reg = <0x0 0x54600000 0x0 0x00040000>;
376 interrupts = <GIC_SPI 363 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
377 clocks = <&tegra_car T 364 clocks = <&tegra_car TEGRA210_CLK_ISPA>;
378 resets = <&tegra_car 2 365 resets = <&tegra_car 23>;
379 reset-names = "isp"; 366 reset-names = "isp";
380 status = "disabled"; 367 status = "disabled";
381 }; 368 };
382 369
383 isp@54680000 { 370 isp@54680000 {
384 compatible = "nvidia,t 371 compatible = "nvidia,tegra210-isp";
385 reg = <0x0 0x54680000 372 reg = <0x0 0x54680000 0x0 0x00040000>;
386 interrupts = <GIC_SPI 373 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
387 clocks = <&tegra_car T 374 clocks = <&tegra_car TEGRA210_CLK_ISPB>;
388 resets = <&tegra_car 3 375 resets = <&tegra_car 3>;
389 reset-names = "isp"; 376 reset-names = "isp";
390 status = "disabled"; 377 status = "disabled";
391 }; 378 };
392 379
393 i2c@546c0000 { 380 i2c@546c0000 {
394 compatible = "nvidia,t 381 compatible = "nvidia,tegra210-i2c-vi";
395 reg = <0x0 0x546c0000 382 reg = <0x0 0x546c0000 0x0 0x00040000>;
396 interrupts = <GIC_SPI 383 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
397 clocks = <&tegra_car T 384 clocks = <&tegra_car TEGRA210_CLK_VI_I2C>,
398 <&tegra_car T 385 <&tegra_car TEGRA210_CLK_I2CSLOW>;
399 clock-names = "div-clk 386 clock-names = "div-clk", "slow";
400 resets = <&tegra_car 2 387 resets = <&tegra_car 208>;
401 reset-names = "i2c"; 388 reset-names = "i2c";
402 power-domains = <&pd_v 389 power-domains = <&pd_venc>;
403 status = "disabled"; 390 status = "disabled";
404 391
405 #address-cells = <1>; 392 #address-cells = <1>;
406 #size-cells = <0>; 393 #size-cells = <0>;
407 }; 394 };
408 }; 395 };
409 396
410 gic: interrupt-controller@50041000 { 397 gic: interrupt-controller@50041000 {
411 compatible = "arm,gic-400"; 398 compatible = "arm,gic-400";
412 #interrupt-cells = <3>; 399 #interrupt-cells = <3>;
413 interrupt-controller; 400 interrupt-controller;
414 reg = <0x0 0x50041000 0x0 0x10 401 reg = <0x0 0x50041000 0x0 0x1000>,
415 <0x0 0x50042000 0x0 0x20 402 <0x0 0x50042000 0x0 0x2000>,
416 <0x0 0x50044000 0x0 0x20 403 <0x0 0x50044000 0x0 0x2000>,
417 <0x0 0x50046000 0x0 0x20 404 <0x0 0x50046000 0x0 0x2000>;
418 interrupts = <GIC_PPI 9 405 interrupts = <GIC_PPI 9
419 (GIC_CPU_MASK_SIMPLE(4 406 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
420 interrupt-parent = <&gic>; 407 interrupt-parent = <&gic>;
421 }; 408 };
422 409
423 gpu@57000000 { 410 gpu@57000000 {
424 compatible = "nvidia,gm20b"; 411 compatible = "nvidia,gm20b";
425 reg = <0x0 0x57000000 0x0 0x01 412 reg = <0x0 0x57000000 0x0 0x01000000>,
426 <0x0 0x58000000 0x0 0x01 413 <0x0 0x58000000 0x0 0x01000000>;
427 interrupts = <GIC_SPI 157 IRQ_ 414 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
428 <GIC_SPI 158 IRQ_ 415 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
429 interrupt-names = "stall", "no 416 interrupt-names = "stall", "nonstall";
430 clocks = <&tegra_car TEGRA210_ 417 clocks = <&tegra_car TEGRA210_CLK_GPU>,
431 <&tegra_car TEGRA210_ 418 <&tegra_car TEGRA210_CLK_PLL_P_OUT5>,
432 <&tegra_car TEGRA210_ 419 <&tegra_car TEGRA210_CLK_PLL_G_REF>;
433 clock-names = "gpu", "pwr", "r 420 clock-names = "gpu", "pwr", "ref";
434 resets = <&tegra_car 184>; 421 resets = <&tegra_car 184>;
435 reset-names = "gpu"; 422 reset-names = "gpu";
436 423
437 iommus = <&mc TEGRA_SWGROUP_GP 424 iommus = <&mc TEGRA_SWGROUP_GPU>;
438 425
439 status = "disabled"; 426 status = "disabled";
440 }; 427 };
441 428
442 lic: interrupt-controller@60004000 { 429 lic: interrupt-controller@60004000 {
443 compatible = "nvidia,tegra210- 430 compatible = "nvidia,tegra210-ictlr";
444 reg = <0x0 0x60004000 0x0 0x40 431 reg = <0x0 0x60004000 0x0 0x40>, /* primary controller */
445 <0x0 0x60004100 0x0 0x40 432 <0x0 0x60004100 0x0 0x40>, /* secondary controller */
446 <0x0 0x60004200 0x0 0x40 433 <0x0 0x60004200 0x0 0x40>, /* tertiary controller */
447 <0x0 0x60004300 0x0 0x40 434 <0x0 0x60004300 0x0 0x40>, /* quaternary controller */
448 <0x0 0x60004400 0x0 0x40 435 <0x0 0x60004400 0x0 0x40>, /* quinary controller */
449 <0x0 0x60004500 0x0 0x40 436 <0x0 0x60004500 0x0 0x40>; /* senary controller */
450 interrupt-controller; 437 interrupt-controller;
451 #interrupt-cells = <3>; 438 #interrupt-cells = <3>;
452 interrupt-parent = <&gic>; 439 interrupt-parent = <&gic>;
453 }; 440 };
454 441
455 timer@60005000 { 442 timer@60005000 {
456 compatible = "nvidia,tegra210- 443 compatible = "nvidia,tegra210-timer";
457 reg = <0x0 0x60005000 0x0 0x40 444 reg = <0x0 0x60005000 0x0 0x400>;
458 interrupts = <GIC_SPI 156 IRQ_ 445 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
459 <GIC_SPI 0 IRQ_TY 446 <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
460 <GIC_SPI 1 IRQ_TY 447 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
461 <GIC_SPI 41 IRQ_T 448 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
462 <GIC_SPI 42 IRQ_T 449 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
463 <GIC_SPI 121 IRQ_ 450 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
464 <GIC_SPI 152 IRQ_ 451 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
465 <GIC_SPI 153 IRQ_ 452 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
466 <GIC_SPI 154 IRQ_ 453 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
467 <GIC_SPI 155 IRQ_ 454 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
468 <GIC_SPI 176 IRQ_ 455 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
469 <GIC_SPI 177 IRQ_ 456 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
470 <GIC_SPI 178 IRQ_ 457 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
471 <GIC_SPI 179 IRQ_ 458 <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
472 clocks = <&tegra_car TEGRA210_ 459 clocks = <&tegra_car TEGRA210_CLK_TIMER>;
473 clock-names = "timer"; 460 clock-names = "timer";
474 }; 461 };
475 462
476 tegra_car: clock@60006000 { 463 tegra_car: clock@60006000 {
477 compatible = "nvidia,tegra210- 464 compatible = "nvidia,tegra210-car";
478 reg = <0x0 0x60006000 0x0 0x10 465 reg = <0x0 0x60006000 0x0 0x1000>;
479 #clock-cells = <1>; 466 #clock-cells = <1>;
480 #reset-cells = <1>; 467 #reset-cells = <1>;
481 }; 468 };
482 469
483 flow-controller@60007000 { 470 flow-controller@60007000 {
484 compatible = "nvidia,tegra210- 471 compatible = "nvidia,tegra210-flowctrl";
485 reg = <0x0 0x60007000 0x0 0x10 472 reg = <0x0 0x60007000 0x0 0x1000>;
486 }; 473 };
487 474
488 gpio: gpio@6000d000 { 475 gpio: gpio@6000d000 {
489 compatible = "nvidia,tegra210- 476 compatible = "nvidia,tegra210-gpio", "nvidia,tegra30-gpio";
490 reg = <0x0 0x6000d000 0x0 0x10 477 reg = <0x0 0x6000d000 0x0 0x1000>;
491 interrupts = <GIC_SPI 32 IRQ_T 478 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
492 <GIC_SPI 33 IRQ_T 479 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
493 <GIC_SPI 34 IRQ_T 480 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
494 <GIC_SPI 35 IRQ_T 481 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
495 <GIC_SPI 55 IRQ_T 482 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
496 <GIC_SPI 87 IRQ_T 483 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
497 <GIC_SPI 89 IRQ_T 484 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
498 <GIC_SPI 125 IRQ_ 485 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
499 #gpio-cells = <2>; 486 #gpio-cells = <2>;
500 gpio-controller; 487 gpio-controller;
501 #interrupt-cells = <2>; 488 #interrupt-cells = <2>;
502 interrupt-controller; 489 interrupt-controller;
503 }; 490 };
504 491
505 apbdma: dma@60020000 { 492 apbdma: dma@60020000 {
506 compatible = "nvidia,tegra210- 493 compatible = "nvidia,tegra210-apbdma", "nvidia,tegra148-apbdma";
507 reg = <0x0 0x60020000 0x0 0x14 494 reg = <0x0 0x60020000 0x0 0x1400>;
508 interrupts = <GIC_SPI 104 IRQ_ 495 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
509 <GIC_SPI 105 IRQ_ 496 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
510 <GIC_SPI 106 IRQ_ 497 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
511 <GIC_SPI 107 IRQ_ 498 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
512 <GIC_SPI 108 IRQ_ 499 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
513 <GIC_SPI 109 IRQ_ 500 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
514 <GIC_SPI 110 IRQ_ 501 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
515 <GIC_SPI 111 IRQ_ 502 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
516 <GIC_SPI 112 IRQ_ 503 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
517 <GIC_SPI 113 IRQ_ 504 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
518 <GIC_SPI 114 IRQ_ 505 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
519 <GIC_SPI 115 IRQ_ 506 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
520 <GIC_SPI 116 IRQ_ 507 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
521 <GIC_SPI 117 IRQ_ 508 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
522 <GIC_SPI 118 IRQ_ 509 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
523 <GIC_SPI 119 IRQ_ 510 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
524 <GIC_SPI 128 IRQ_ 511 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
525 <GIC_SPI 129 IRQ_ 512 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
526 <GIC_SPI 130 IRQ_ 513 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
527 <GIC_SPI 131 IRQ_ 514 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
528 <GIC_SPI 132 IRQ_ 515 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
529 <GIC_SPI 133 IRQ_ 516 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
530 <GIC_SPI 134 IRQ_ 517 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
531 <GIC_SPI 135 IRQ_ 518 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
532 <GIC_SPI 136 IRQ_ 519 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
533 <GIC_SPI 137 IRQ_ 520 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
534 <GIC_SPI 138 IRQ_ 521 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
535 <GIC_SPI 139 IRQ_ 522 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
536 <GIC_SPI 140 IRQ_ 523 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
537 <GIC_SPI 141 IRQ_ 524 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
538 <GIC_SPI 142 IRQ_ 525 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
539 <GIC_SPI 143 IRQ_ 526 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
540 clocks = <&tegra_car TEGRA210_ 527 clocks = <&tegra_car TEGRA210_CLK_APBDMA>;
541 clock-names = "dma"; 528 clock-names = "dma";
542 resets = <&tegra_car 34>; 529 resets = <&tegra_car 34>;
543 reset-names = "dma"; 530 reset-names = "dma";
544 #dma-cells = <1>; 531 #dma-cells = <1>;
545 }; 532 };
546 533
547 apbmisc@70000800 { 534 apbmisc@70000800 {
548 compatible = "nvidia,tegra210- 535 compatible = "nvidia,tegra210-apbmisc", "nvidia,tegra20-apbmisc";
549 reg = <0x0 0x70000800 0x0 0x64 536 reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */
550 <0x0 0x70000008 0x0 0x04 537 <0x0 0x70000008 0x0 0x04>; /* Strapping options */
551 }; 538 };
552 539
553 pinmux: pinmux@700008d4 { 540 pinmux: pinmux@700008d4 {
554 compatible = "nvidia,tegra210- 541 compatible = "nvidia,tegra210-pinmux";
555 reg = <0x0 0x700008d4 0x0 0x29 542 reg = <0x0 0x700008d4 0x0 0x29c>, /* Pad control registers */
556 <0x0 0x70003000 0x0 0x29 543 <0x0 0x70003000 0x0 0x294>; /* Mux registers */
557 !! 544 sdmmc1_3v3_drv: sdmmc1-3v3-drv {
558 sdmmc1_1v8_drv: pinmux-sdmmc1- <<
559 sdmmc1 { 545 sdmmc1 {
560 nvidia,pins = 546 nvidia,pins = "drive_sdmmc1";
561 nvidia,pull-do !! 547 nvidia,pull-down-strength = <0x8>;
562 nvidia,pull-up !! 548 nvidia,pull-up-strength = <0x8>;
563 }; 549 };
564 }; 550 };
565 !! 551 sdmmc1_1v8_drv: sdmmc1-1v8-drv {
566 sdmmc1_3v3_drv: pinmux-sdmmc1- <<
567 sdmmc1 { 552 sdmmc1 {
568 nvidia,pins = 553 nvidia,pins = "drive_sdmmc1";
569 nvidia,pull-do !! 554 nvidia,pull-down-strength = <0x4>;
570 nvidia,pull-up !! 555 nvidia,pull-up-strength = <0x3>;
571 }; 556 };
572 }; 557 };
573 !! 558 sdmmc2_1v8_drv: sdmmc2-1v8-drv {
574 sdmmc2_1v8_drv: pinmux-sdmmc2- <<
575 sdmmc2 { 559 sdmmc2 {
576 nvidia,pins = 560 nvidia,pins = "drive_sdmmc2";
577 nvidia,pull-do 561 nvidia,pull-down-strength = <0x10>;
578 nvidia,pull-up 562 nvidia,pull-up-strength = <0x10>;
579 }; 563 };
580 }; 564 };
581 !! 565 sdmmc3_3v3_drv: sdmmc3-3v3-drv {
582 sdmmc3_1v8_drv: pinmux-sdmmc3- <<
583 sdmmc3 { 566 sdmmc3 {
584 nvidia,pins = 567 nvidia,pins = "drive_sdmmc3";
585 nvidia,pull-do !! 568 nvidia,pull-down-strength = <0x8>;
586 nvidia,pull-up !! 569 nvidia,pull-up-strength = <0x8>;
587 }; 570 };
588 }; 571 };
589 !! 572 sdmmc3_1v8_drv: sdmmc3-1v8-drv {
590 sdmmc3_3v3_drv: pinmux-sdmmc3- <<
591 sdmmc3 { 573 sdmmc3 {
592 nvidia,pins = 574 nvidia,pins = "drive_sdmmc3";
593 nvidia,pull-do !! 575 nvidia,pull-down-strength = <0x4>;
594 nvidia,pull-up !! 576 nvidia,pull-up-strength = <0x3>;
595 }; 577 };
596 }; 578 };
597 !! 579 sdmmc4_1v8_drv: sdmmc4-1v8-drv {
598 sdmmc4_1v8_drv: pinmux-sdmmc4- <<
599 sdmmc4 { 580 sdmmc4 {
600 nvidia,pins = 581 nvidia,pins = "drive_sdmmc4";
601 nvidia,pull-do 582 nvidia,pull-down-strength = <0x10>;
602 nvidia,pull-up 583 nvidia,pull-up-strength = <0x10>;
603 }; 584 };
604 }; 585 };
605 }; 586 };
606 587
607 /* 588 /*
608 * There are two serial driver i.e. 82 589 * There are two serial driver i.e. 8250 based simple serial
609 * driver and APB DMA based serial dri 590 * driver and APB DMA based serial driver for higher baudrate
610 * and performance. To enable the 8250 591 * and performance. To enable the 8250 based driver, the compatible
611 * is "nvidia,tegra124-uart", "nvidia, 592 * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable
612 * the APB DMA based serial driver, th 593 * the APB DMA based serial driver, the compatible is
613 * "nvidia,tegra124-hsuart", "nvidia,t 594 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart".
614 */ 595 */
615 uarta: serial@70006000 { 596 uarta: serial@70006000 {
616 compatible = "nvidia,tegra210- 597 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
617 reg = <0x0 0x70006000 0x0 0x40 598 reg = <0x0 0x70006000 0x0 0x40>;
618 reg-shift = <2>; 599 reg-shift = <2>;
619 interrupts = <GIC_SPI 36 IRQ_T 600 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
620 clocks = <&tegra_car TEGRA210_ 601 clocks = <&tegra_car TEGRA210_CLK_UARTA>;
>> 602 clock-names = "serial";
621 resets = <&tegra_car 6>; 603 resets = <&tegra_car 6>;
>> 604 reset-names = "serial";
622 dmas = <&apbdma 8>, <&apbdma 8 605 dmas = <&apbdma 8>, <&apbdma 8>;
623 dma-names = "rx", "tx"; 606 dma-names = "rx", "tx";
624 status = "disabled"; 607 status = "disabled";
625 }; 608 };
626 609
627 uartb: serial@70006040 { 610 uartb: serial@70006040 {
628 compatible = "nvidia,tegra210- 611 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
629 reg = <0x0 0x70006040 0x0 0x40 612 reg = <0x0 0x70006040 0x0 0x40>;
630 reg-shift = <2>; 613 reg-shift = <2>;
631 interrupts = <GIC_SPI 37 IRQ_T 614 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
632 clocks = <&tegra_car TEGRA210_ 615 clocks = <&tegra_car TEGRA210_CLK_UARTB>;
>> 616 clock-names = "serial";
633 resets = <&tegra_car 7>; 617 resets = <&tegra_car 7>;
>> 618 reset-names = "serial";
634 dmas = <&apbdma 9>, <&apbdma 9 619 dmas = <&apbdma 9>, <&apbdma 9>;
635 dma-names = "rx", "tx"; 620 dma-names = "rx", "tx";
636 status = "disabled"; 621 status = "disabled";
637 }; 622 };
638 623
639 uartc: serial@70006200 { 624 uartc: serial@70006200 {
640 compatible = "nvidia,tegra210- 625 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
641 reg = <0x0 0x70006200 0x0 0x40 626 reg = <0x0 0x70006200 0x0 0x40>;
642 reg-shift = <2>; 627 reg-shift = <2>;
643 interrupts = <GIC_SPI 46 IRQ_T 628 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
644 clocks = <&tegra_car TEGRA210_ 629 clocks = <&tegra_car TEGRA210_CLK_UARTC>;
>> 630 clock-names = "serial";
645 resets = <&tegra_car 55>; 631 resets = <&tegra_car 55>;
>> 632 reset-names = "serial";
646 dmas = <&apbdma 10>, <&apbdma 633 dmas = <&apbdma 10>, <&apbdma 10>;
647 dma-names = "rx", "tx"; 634 dma-names = "rx", "tx";
648 status = "disabled"; 635 status = "disabled";
649 }; 636 };
650 637
651 uartd: serial@70006300 { 638 uartd: serial@70006300 {
652 compatible = "nvidia,tegra210- 639 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
653 reg = <0x0 0x70006300 0x0 0x40 640 reg = <0x0 0x70006300 0x0 0x40>;
654 reg-shift = <2>; 641 reg-shift = <2>;
655 interrupts = <GIC_SPI 90 IRQ_T 642 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
656 clocks = <&tegra_car TEGRA210_ 643 clocks = <&tegra_car TEGRA210_CLK_UARTD>;
>> 644 clock-names = "serial";
657 resets = <&tegra_car 65>; 645 resets = <&tegra_car 65>;
>> 646 reset-names = "serial";
658 dmas = <&apbdma 19>, <&apbdma 647 dmas = <&apbdma 19>, <&apbdma 19>;
659 dma-names = "rx", "tx"; 648 dma-names = "rx", "tx";
660 status = "disabled"; 649 status = "disabled";
661 }; 650 };
662 651
663 pwm: pwm@7000a000 { 652 pwm: pwm@7000a000 {
664 compatible = "nvidia,tegra210- 653 compatible = "nvidia,tegra210-pwm", "nvidia,tegra20-pwm";
665 reg = <0x0 0x7000a000 0x0 0x10 654 reg = <0x0 0x7000a000 0x0 0x100>;
666 #pwm-cells = <2>; 655 #pwm-cells = <2>;
667 clocks = <&tegra_car TEGRA210_ 656 clocks = <&tegra_car TEGRA210_CLK_PWM>;
>> 657 clock-names = "pwm";
668 resets = <&tegra_car 17>; 658 resets = <&tegra_car 17>;
669 reset-names = "pwm"; 659 reset-names = "pwm";
670 status = "disabled"; 660 status = "disabled";
671 }; 661 };
672 662
673 i2c@7000c000 { 663 i2c@7000c000 {
674 compatible = "nvidia,tegra210- 664 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c";
675 reg = <0x0 0x7000c000 0x0 0x10 665 reg = <0x0 0x7000c000 0x0 0x100>;
676 interrupts = <GIC_SPI 38 IRQ_T 666 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
677 #address-cells = <1>; 667 #address-cells = <1>;
678 #size-cells = <0>; 668 #size-cells = <0>;
679 clocks = <&tegra_car TEGRA210_ 669 clocks = <&tegra_car TEGRA210_CLK_I2C1>;
680 clock-names = "div-clk"; 670 clock-names = "div-clk";
681 resets = <&tegra_car 12>; 671 resets = <&tegra_car 12>;
682 reset-names = "i2c"; 672 reset-names = "i2c";
683 dmas = <&apbdma 21>, <&apbdma 673 dmas = <&apbdma 21>, <&apbdma 21>;
684 dma-names = "rx", "tx"; 674 dma-names = "rx", "tx";
685 status = "disabled"; 675 status = "disabled";
686 }; 676 };
687 677
688 i2c@7000c400 { 678 i2c@7000c400 {
689 compatible = "nvidia,tegra210- 679 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c";
690 reg = <0x0 0x7000c400 0x0 0x10 680 reg = <0x0 0x7000c400 0x0 0x100>;
691 interrupts = <GIC_SPI 84 IRQ_T 681 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
692 #address-cells = <1>; 682 #address-cells = <1>;
693 #size-cells = <0>; 683 #size-cells = <0>;
694 clocks = <&tegra_car TEGRA210_ 684 clocks = <&tegra_car TEGRA210_CLK_I2C2>;
695 clock-names = "div-clk"; 685 clock-names = "div-clk";
696 resets = <&tegra_car 54>; 686 resets = <&tegra_car 54>;
697 reset-names = "i2c"; 687 reset-names = "i2c";
698 dmas = <&apbdma 22>, <&apbdma 688 dmas = <&apbdma 22>, <&apbdma 22>;
699 dma-names = "rx", "tx"; 689 dma-names = "rx", "tx";
700 status = "disabled"; 690 status = "disabled";
701 }; 691 };
702 692
703 i2c@7000c500 { 693 i2c@7000c500 {
704 compatible = "nvidia,tegra210- 694 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c";
705 reg = <0x0 0x7000c500 0x0 0x10 695 reg = <0x0 0x7000c500 0x0 0x100>;
706 interrupts = <GIC_SPI 92 IRQ_T 696 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
707 #address-cells = <1>; 697 #address-cells = <1>;
708 #size-cells = <0>; 698 #size-cells = <0>;
709 clocks = <&tegra_car TEGRA210_ 699 clocks = <&tegra_car TEGRA210_CLK_I2C3>;
710 clock-names = "div-clk"; 700 clock-names = "div-clk";
711 resets = <&tegra_car 67>; 701 resets = <&tegra_car 67>;
712 reset-names = "i2c"; 702 reset-names = "i2c";
713 dmas = <&apbdma 23>, <&apbdma 703 dmas = <&apbdma 23>, <&apbdma 23>;
714 dma-names = "rx", "tx"; 704 dma-names = "rx", "tx";
715 status = "disabled"; 705 status = "disabled";
716 }; 706 };
717 707
718 i2c@7000c700 { 708 i2c@7000c700 {
719 compatible = "nvidia,tegra210- 709 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c";
720 reg = <0x0 0x7000c700 0x0 0x10 710 reg = <0x0 0x7000c700 0x0 0x100>;
721 interrupts = <GIC_SPI 120 IRQ_ 711 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
722 #address-cells = <1>; 712 #address-cells = <1>;
723 #size-cells = <0>; 713 #size-cells = <0>;
724 clocks = <&tegra_car TEGRA210_ 714 clocks = <&tegra_car TEGRA210_CLK_I2C4>;
725 clock-names = "div-clk"; 715 clock-names = "div-clk";
726 resets = <&tegra_car 103>; 716 resets = <&tegra_car 103>;
727 reset-names = "i2c"; 717 reset-names = "i2c";
728 dmas = <&apbdma 26>, <&apbdma 718 dmas = <&apbdma 26>, <&apbdma 26>;
729 dma-names = "rx", "tx"; 719 dma-names = "rx", "tx";
730 pinctrl-0 = <&state_dpaux1_i2c 720 pinctrl-0 = <&state_dpaux1_i2c>;
731 pinctrl-1 = <&state_dpaux1_off 721 pinctrl-1 = <&state_dpaux1_off>;
732 pinctrl-names = "default", "id 722 pinctrl-names = "default", "idle";
733 status = "disabled"; 723 status = "disabled";
734 }; 724 };
735 725
736 i2c@7000d000 { 726 i2c@7000d000 {
737 compatible = "nvidia,tegra210- 727 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c";
738 reg = <0x0 0x7000d000 0x0 0x10 728 reg = <0x0 0x7000d000 0x0 0x100>;
739 interrupts = <GIC_SPI 53 IRQ_T 729 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
740 #address-cells = <1>; 730 #address-cells = <1>;
741 #size-cells = <0>; 731 #size-cells = <0>;
742 clocks = <&tegra_car TEGRA210_ 732 clocks = <&tegra_car TEGRA210_CLK_I2C5>;
743 clock-names = "div-clk"; 733 clock-names = "div-clk";
744 resets = <&tegra_car 47>; 734 resets = <&tegra_car 47>;
745 reset-names = "i2c"; 735 reset-names = "i2c";
746 dmas = <&apbdma 24>, <&apbdma 736 dmas = <&apbdma 24>, <&apbdma 24>;
747 dma-names = "rx", "tx"; 737 dma-names = "rx", "tx";
748 status = "disabled"; 738 status = "disabled";
749 }; 739 };
750 740
751 i2c@7000d100 { 741 i2c@7000d100 {
752 compatible = "nvidia,tegra210- 742 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c";
753 reg = <0x0 0x7000d100 0x0 0x10 743 reg = <0x0 0x7000d100 0x0 0x100>;
754 interrupts = <GIC_SPI 63 IRQ_T 744 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
755 #address-cells = <1>; 745 #address-cells = <1>;
756 #size-cells = <0>; 746 #size-cells = <0>;
757 clocks = <&tegra_car TEGRA210_ 747 clocks = <&tegra_car TEGRA210_CLK_I2C6>;
758 clock-names = "div-clk"; 748 clock-names = "div-clk";
759 resets = <&tegra_car 166>; 749 resets = <&tegra_car 166>;
760 reset-names = "i2c"; 750 reset-names = "i2c";
761 dmas = <&apbdma 30>, <&apbdma 751 dmas = <&apbdma 30>, <&apbdma 30>;
762 dma-names = "rx", "tx"; 752 dma-names = "rx", "tx";
763 pinctrl-0 = <&state_dpaux_i2c> 753 pinctrl-0 = <&state_dpaux_i2c>;
764 pinctrl-1 = <&state_dpaux_off> 754 pinctrl-1 = <&state_dpaux_off>;
765 pinctrl-names = "default", "id 755 pinctrl-names = "default", "idle";
766 status = "disabled"; 756 status = "disabled";
767 }; 757 };
768 758
769 spi@7000d400 { 759 spi@7000d400 {
770 compatible = "nvidia,tegra210- 760 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
771 reg = <0x0 0x7000d400 0x0 0x20 761 reg = <0x0 0x7000d400 0x0 0x200>;
772 interrupts = <GIC_SPI 59 IRQ_T 762 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
773 #address-cells = <1>; 763 #address-cells = <1>;
774 #size-cells = <0>; 764 #size-cells = <0>;
775 clocks = <&tegra_car TEGRA210_ 765 clocks = <&tegra_car TEGRA210_CLK_SBC1>;
776 clock-names = "spi"; 766 clock-names = "spi";
777 resets = <&tegra_car 41>; 767 resets = <&tegra_car 41>;
778 reset-names = "spi"; 768 reset-names = "spi";
779 dmas = <&apbdma 15>, <&apbdma 769 dmas = <&apbdma 15>, <&apbdma 15>;
780 dma-names = "rx", "tx"; 770 dma-names = "rx", "tx";
781 status = "disabled"; 771 status = "disabled";
782 }; 772 };
783 773
784 spi@7000d600 { 774 spi@7000d600 {
785 compatible = "nvidia,tegra210- 775 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
786 reg = <0x0 0x7000d600 0x0 0x20 776 reg = <0x0 0x7000d600 0x0 0x200>;
787 interrupts = <GIC_SPI 82 IRQ_T 777 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
788 #address-cells = <1>; 778 #address-cells = <1>;
789 #size-cells = <0>; 779 #size-cells = <0>;
790 clocks = <&tegra_car TEGRA210_ 780 clocks = <&tegra_car TEGRA210_CLK_SBC2>;
791 clock-names = "spi"; 781 clock-names = "spi";
792 resets = <&tegra_car 44>; 782 resets = <&tegra_car 44>;
793 reset-names = "spi"; 783 reset-names = "spi";
794 dmas = <&apbdma 16>, <&apbdma 784 dmas = <&apbdma 16>, <&apbdma 16>;
795 dma-names = "rx", "tx"; 785 dma-names = "rx", "tx";
796 status = "disabled"; 786 status = "disabled";
797 }; 787 };
798 788
799 spi@7000d800 { 789 spi@7000d800 {
800 compatible = "nvidia,tegra210- 790 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
801 reg = <0x0 0x7000d800 0x0 0x20 791 reg = <0x0 0x7000d800 0x0 0x200>;
802 interrupts = <GIC_SPI 83 IRQ_T 792 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
803 #address-cells = <1>; 793 #address-cells = <1>;
804 #size-cells = <0>; 794 #size-cells = <0>;
805 clocks = <&tegra_car TEGRA210_ 795 clocks = <&tegra_car TEGRA210_CLK_SBC3>;
806 clock-names = "spi"; 796 clock-names = "spi";
807 resets = <&tegra_car 46>; 797 resets = <&tegra_car 46>;
808 reset-names = "spi"; 798 reset-names = "spi";
809 dmas = <&apbdma 17>, <&apbdma 799 dmas = <&apbdma 17>, <&apbdma 17>;
810 dma-names = "rx", "tx"; 800 dma-names = "rx", "tx";
811 status = "disabled"; 801 status = "disabled";
812 }; 802 };
813 803
814 spi@7000da00 { 804 spi@7000da00 {
815 compatible = "nvidia,tegra210- 805 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
816 reg = <0x0 0x7000da00 0x0 0x20 806 reg = <0x0 0x7000da00 0x0 0x200>;
817 interrupts = <GIC_SPI 93 IRQ_T 807 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
818 #address-cells = <1>; 808 #address-cells = <1>;
819 #size-cells = <0>; 809 #size-cells = <0>;
820 clocks = <&tegra_car TEGRA210_ 810 clocks = <&tegra_car TEGRA210_CLK_SBC4>;
821 clock-names = "spi"; 811 clock-names = "spi";
822 resets = <&tegra_car 68>; 812 resets = <&tegra_car 68>;
823 reset-names = "spi"; 813 reset-names = "spi";
824 dmas = <&apbdma 18>, <&apbdma 814 dmas = <&apbdma 18>, <&apbdma 18>;
825 dma-names = "rx", "tx"; 815 dma-names = "rx", "tx";
826 status = "disabled"; 816 status = "disabled";
827 }; 817 };
828 818
829 rtc@7000e000 { 819 rtc@7000e000 {
830 compatible = "nvidia,tegra210- 820 compatible = "nvidia,tegra210-rtc", "nvidia,tegra20-rtc";
831 reg = <0x0 0x7000e000 0x0 0x10 821 reg = <0x0 0x7000e000 0x0 0x100>;
832 interrupts = <16 IRQ_TYPE_LEVE 822 interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
833 interrupt-parent = <&tegra_pmc 823 interrupt-parent = <&tegra_pmc>;
834 clocks = <&tegra_car TEGRA210_ 824 clocks = <&tegra_car TEGRA210_CLK_RTC>;
835 clock-names = "rtc"; 825 clock-names = "rtc";
836 }; 826 };
837 827
838 tegra_pmc: pmc@7000e400 { 828 tegra_pmc: pmc@7000e400 {
839 compatible = "nvidia,tegra210- 829 compatible = "nvidia,tegra210-pmc";
840 reg = <0x0 0x7000e400 0x0 0x40 830 reg = <0x0 0x7000e400 0x0 0x400>;
841 clocks = <&tegra_car TEGRA210_ 831 clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>;
842 clock-names = "pclk", "clk32k_ 832 clock-names = "pclk", "clk32k_in";
843 #clock-cells = <1>; 833 #clock-cells = <1>;
844 #interrupt-cells = <2>; 834 #interrupt-cells = <2>;
845 interrupt-controller; 835 interrupt-controller;
846 836
847 pinmux { <<
848 pex_dpd_disable: pex-d <<
849 pins = "pex-bi <<
850 low-power-disa <<
851 }; <<
852 <<
853 pex_dpd_enable: pex-dp <<
854 pins = "pex-bi <<
855 low-power-enab <<
856 }; <<
857 <<
858 sdmmc1_1v8: sdmmc1-1v8 <<
859 pins = "sdmmc1 <<
860 power-source = <<
861 }; <<
862 <<
863 sdmmc1_3v3: sdmmc1-3v3 <<
864 pins = "sdmmc1 <<
865 power-source = <<
866 }; <<
867 <<
868 sdmmc3_1v8: sdmmc3-1v8 <<
869 pins = "sdmmc3 <<
870 power-source = <<
871 }; <<
872 <<
873 sdmmc3_3v3: sdmmc3-3v3 <<
874 pins = "sdmmc3 <<
875 power-source = <<
876 }; <<
877 }; <<
878 <<
879 powergates { 837 powergates {
880 pd_audio: aud { 838 pd_audio: aud {
881 clocks = <&teg 839 clocks = <&tegra_car TEGRA210_CLK_APE>,
882 <&teg 840 <&tegra_car TEGRA210_CLK_APB2APE>;
883 resets = <&teg 841 resets = <&tegra_car 198>;
884 #power-domain- 842 #power-domain-cells = <0>;
885 }; 843 };
886 844
887 pd_sor: sor { 845 pd_sor: sor {
888 clocks = <&teg 846 clocks = <&tegra_car TEGRA210_CLK_SOR0>,
889 <&teg 847 <&tegra_car TEGRA210_CLK_SOR1>,
890 <&teg 848 <&tegra_car TEGRA210_CLK_CILAB>,
891 <&teg 849 <&tegra_car TEGRA210_CLK_CILCD>,
892 <&teg 850 <&tegra_car TEGRA210_CLK_CILE>,
893 <&teg 851 <&tegra_car TEGRA210_CLK_DSIA>,
894 <&teg 852 <&tegra_car TEGRA210_CLK_DSIB>,
895 <&teg 853 <&tegra_car TEGRA210_CLK_DPAUX>,
896 <&teg 854 <&tegra_car TEGRA210_CLK_DPAUX1>,
897 <&teg 855 <&tegra_car TEGRA210_CLK_MIPI_CAL>;
898 resets = <&teg 856 resets = <&tegra_car TEGRA210_CLK_SOR0>,
899 <&teg 857 <&tegra_car TEGRA210_CLK_SOR1>,
900 <&teg 858 <&tegra_car TEGRA210_CLK_DSIA>,
901 <&teg 859 <&tegra_car TEGRA210_CLK_DSIB>,
902 <&teg 860 <&tegra_car TEGRA210_CLK_DPAUX>,
903 <&teg 861 <&tegra_car TEGRA210_CLK_DPAUX1>,
904 <&teg 862 <&tegra_car TEGRA210_CLK_MIPI_CAL>;
905 #power-domain- 863 #power-domain-cells = <0>;
906 }; 864 };
907 865
908 pd_venc: venc { <<
909 clocks = <&teg <<
910 <&teg <<
911 resets = <&mc <<
912 <&teg <<
913 <&teg <<
914 #power-domain- <<
915 }; <<
916 <<
917 pd_vic: vic { <<
918 clocks = <&teg <<
919 resets = <&teg <<
920 #power-domain- <<
921 }; <<
922 <<
923 pd_xusbss: xusba { 866 pd_xusbss: xusba {
924 clocks = <&teg 867 clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>;
925 resets = <&teg 868 resets = <&tegra_car TEGRA210_CLK_XUSB_SS>;
926 #power-domain- 869 #power-domain-cells = <0>;
927 }; 870 };
928 871
929 pd_xusbdev: xusbb { 872 pd_xusbdev: xusbb {
930 clocks = <&teg 873 clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>;
931 resets = <&teg 874 resets = <&tegra_car 95>;
932 #power-domain- 875 #power-domain-cells = <0>;
933 }; 876 };
934 877
935 pd_xusbhost: xusbc { 878 pd_xusbhost: xusbc {
936 clocks = <&teg 879 clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>;
937 resets = <&teg 880 resets = <&tegra_car TEGRA210_CLK_XUSB_HOST>;
938 #power-domain- 881 #power-domain-cells = <0>;
939 }; 882 };
>> 883
>> 884 pd_vic: vic {
>> 885 clocks = <&tegra_car TEGRA210_CLK_VIC03>;
>> 886 clock-names = "vic";
>> 887 resets = <&tegra_car 178>;
>> 888 reset-names = "vic";
>> 889 #power-domain-cells = <0>;
>> 890 };
>> 891
>> 892 pd_venc: venc {
>> 893 clocks = <&tegra_car TEGRA210_CLK_VI>,
>> 894 <&tegra_car TEGRA210_CLK_CSI>;
>> 895 resets = <&mc TEGRA210_MC_RESET_VI>,
>> 896 <&tegra_car 20>,
>> 897 <&tegra_car 52>;
>> 898 #power-domain-cells = <0>;
>> 899 };
>> 900 };
>> 901
>> 902 sdmmc1_3v3: sdmmc1-3v3 {
>> 903 pins = "sdmmc1";
>> 904 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
>> 905 };
>> 906
>> 907 sdmmc1_1v8: sdmmc1-1v8 {
>> 908 pins = "sdmmc1";
>> 909 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
>> 910 };
>> 911
>> 912 sdmmc3_3v3: sdmmc3-3v3 {
>> 913 pins = "sdmmc3";
>> 914 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
>> 915 };
>> 916
>> 917 sdmmc3_1v8: sdmmc3-1v8 {
>> 918 pins = "sdmmc3";
>> 919 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
>> 920 };
>> 921
>> 922 pex_dpd_disable: pex_en {
>> 923 pex-dpd-disable {
>> 924 pins = "pex-bias", "pex-clk1", "pex-clk2";
>> 925 low-power-disable;
>> 926 };
>> 927 };
>> 928
>> 929 pex_dpd_enable: pex_dis {
>> 930 pex-dpd-enable {
>> 931 pins = "pex-bias", "pex-clk1", "pex-clk2";
>> 932 low-power-enable;
>> 933 };
940 }; 934 };
941 }; 935 };
942 936
943 fuse@7000f800 { 937 fuse@7000f800 {
944 compatible = "nvidia,tegra210- 938 compatible = "nvidia,tegra210-efuse";
945 reg = <0x0 0x7000f800 0x0 0x40 939 reg = <0x0 0x7000f800 0x0 0x400>;
946 clocks = <&tegra_car TEGRA210_ 940 clocks = <&tegra_car TEGRA210_CLK_FUSE>;
947 clock-names = "fuse"; 941 clock-names = "fuse";
948 resets = <&tegra_car 39>; 942 resets = <&tegra_car 39>;
949 reset-names = "fuse"; 943 reset-names = "fuse";
950 }; 944 };
951 945
952 mc: memory-controller@70019000 { 946 mc: memory-controller@70019000 {
953 compatible = "nvidia,tegra210- 947 compatible = "nvidia,tegra210-mc";
954 reg = <0x0 0x70019000 0x0 0x10 948 reg = <0x0 0x70019000 0x0 0x1000>;
955 clocks = <&tegra_car TEGRA210_ 949 clocks = <&tegra_car TEGRA210_CLK_MC>;
956 clock-names = "mc"; 950 clock-names = "mc";
957 951
958 interrupts = <GIC_SPI 77 IRQ_T 952 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
959 953
960 #iommu-cells = <1>; 954 #iommu-cells = <1>;
961 #reset-cells = <1>; 955 #reset-cells = <1>;
962 }; 956 };
963 957
964 emc: external-memory-controller@7001b0 958 emc: external-memory-controller@7001b000 {
965 compatible = "nvidia,tegra210- 959 compatible = "nvidia,tegra210-emc";
966 reg = <0x0 0x7001b000 0x0 0x10 960 reg = <0x0 0x7001b000 0x0 0x1000>,
967 <0x0 0x7001e000 0x0 0x10 961 <0x0 0x7001e000 0x0 0x1000>,
968 <0x0 0x7001f000 0x0 0x10 962 <0x0 0x7001f000 0x0 0x1000>;
969 clocks = <&tegra_car TEGRA210_ 963 clocks = <&tegra_car TEGRA210_CLK_EMC>;
970 clock-names = "emc"; 964 clock-names = "emc";
971 interrupts = <GIC_SPI 78 IRQ_T 965 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
972 nvidia,memory-controller = <&m 966 nvidia,memory-controller = <&mc>;
973 #cooling-cells = <2>; 967 #cooling-cells = <2>;
974 }; 968 };
975 969
976 sata@70020000 { 970 sata@70020000 {
977 compatible = "nvidia,tegra210- 971 compatible = "nvidia,tegra210-ahci";
978 reg = <0x0 0x70027000 0x0 0x20 972 reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */
979 <0x0 0x70020000 0x0 0x70 973 <0x0 0x70020000 0x0 0x7000>, /* SATA */
980 <0x0 0x70001100 0x0 0x10 974 <0x0 0x70001100 0x0 0x1000>; /* SATA AUX */
981 interrupts = <GIC_SPI 23 IRQ_T 975 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
982 clocks = <&tegra_car TEGRA210_ 976 clocks = <&tegra_car TEGRA210_CLK_SATA>,
983 <&tegra_car TEGRA210_ 977 <&tegra_car TEGRA210_CLK_SATA_OOB>;
984 clock-names = "sata", "sata-oo 978 clock-names = "sata", "sata-oob";
985 resets = <&tegra_car 124>, 979 resets = <&tegra_car 124>,
986 <&tegra_car 129>, !! 980 <&tegra_car 123>,
987 <&tegra_car 123>; !! 981 <&tegra_car 129>;
988 reset-names = "sata", "sata-co !! 982 reset-names = "sata", "sata-oob", "sata-cold";
989 status = "disabled"; 983 status = "disabled";
990 }; 984 };
991 985
992 hda@70030000 { 986 hda@70030000 {
993 compatible = "nvidia,tegra210- 987 compatible = "nvidia,tegra210-hda", "nvidia,tegra30-hda";
994 reg = <0x0 0x70030000 0x0 0x10 988 reg = <0x0 0x70030000 0x0 0x10000>;
995 interrupts = <GIC_SPI 81 IRQ_T 989 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
996 clocks = <&tegra_car TEGRA210_ 990 clocks = <&tegra_car TEGRA210_CLK_HDA>,
997 <&tegra_car TEGRA210_ 991 <&tegra_car TEGRA210_CLK_HDA2HDMI>,
998 <&tegra_car TEGRA210_ 992 <&tegra_car TEGRA210_CLK_HDA2CODEC_2X>;
999 clock-names = "hda", "hda2hdmi 993 clock-names = "hda", "hda2hdmi", "hda2codec_2x";
1000 resets = <&tegra_car 125>, /* 994 resets = <&tegra_car 125>, /* hda */
1001 <&tegra_car 128>, /* 995 <&tegra_car 128>, /* hda2hdmi */
1002 <&tegra_car 111>; /* 996 <&tegra_car 111>; /* hda2codec_2x */
1003 reset-names = "hda", "hda2hdm 997 reset-names = "hda", "hda2hdmi", "hda2codec_2x";
1004 power-domains = <&pd_sor>; <<
1005 status = "disabled"; 998 status = "disabled";
1006 }; 999 };
1007 1000
1008 usb@70090000 { 1001 usb@70090000 {
1009 compatible = "nvidia,tegra210 1002 compatible = "nvidia,tegra210-xusb";
1010 reg = <0x0 0x70090000 0x0 0x8 1003 reg = <0x0 0x70090000 0x0 0x8000>,
1011 <0x0 0x70098000 0x0 0x1 1004 <0x0 0x70098000 0x0 0x1000>,
1012 <0x0 0x70099000 0x0 0x1 1005 <0x0 0x70099000 0x0 0x1000>;
1013 reg-names = "hcd", "fpci", "i 1006 reg-names = "hcd", "fpci", "ipfs";
1014 1007
1015 interrupts = <GIC_SPI 39 IRQ_ 1008 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
1016 <GIC_SPI 40 IRQ_ 1009 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1017 1010
1018 clocks = <&tegra_car TEGRA210 1011 clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>,
1019 <&tegra_car TEGRA210 1012 <&tegra_car TEGRA210_CLK_XUSB_HOST_SRC>,
1020 <&tegra_car TEGRA210 1013 <&tegra_car TEGRA210_CLK_XUSB_FALCON_SRC>,
1021 <&tegra_car TEGRA210 1014 <&tegra_car TEGRA210_CLK_XUSB_SS>,
1022 <&tegra_car TEGRA210 <<
1023 <&tegra_car TEGRA210 1015 <&tegra_car TEGRA210_CLK_XUSB_SS_SRC>,
>> 1016 <&tegra_car TEGRA210_CLK_XUSB_SS_DIV2>,
1024 <&tegra_car TEGRA210 1017 <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>,
1025 <&tegra_car TEGRA210 1018 <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>,
1026 <&tegra_car TEGRA210 1019 <&tegra_car TEGRA210_CLK_PLL_U_480M>,
1027 <&tegra_car TEGRA210 1020 <&tegra_car TEGRA210_CLK_CLK_M>,
1028 <&tegra_car TEGRA210 1021 <&tegra_car TEGRA210_CLK_PLL_E>;
1029 clock-names = "xusb_host", "x 1022 clock-names = "xusb_host", "xusb_host_src",
1030 "xusb_falcon_sr 1023 "xusb_falcon_src", "xusb_ss",
1031 "xusb_ss_div2", !! 1024 "xusb_ss_src", "xusb_ss_div2",
1032 "xusb_hs_src", 1025 "xusb_hs_src", "xusb_fs_src",
1033 "pll_u_480m", " 1026 "pll_u_480m", "clk_m", "pll_e";
1034 resets = <&tegra_car 89>, <&t 1027 resets = <&tegra_car 89>, <&tegra_car 156>,
1035 <&tegra_car 143>; 1028 <&tegra_car 143>;
1036 reset-names = "xusb_host", "x 1029 reset-names = "xusb_host", "xusb_ss", "xusb_src";
1037 power-domains = <&pd_xusbhost 1030 power-domains = <&pd_xusbhost>, <&pd_xusbss>;
1038 power-domain-names = "xusb_ho 1031 power-domain-names = "xusb_host", "xusb_ss";
1039 1032
1040 nvidia,xusb-padctl = <&padctl 1033 nvidia,xusb-padctl = <&padctl>;
1041 1034
1042 status = "disabled"; 1035 status = "disabled";
1043 }; 1036 };
1044 1037
1045 padctl: padctl@7009f000 { 1038 padctl: padctl@7009f000 {
1046 compatible = "nvidia,tegra210 1039 compatible = "nvidia,tegra210-xusb-padctl";
1047 reg = <0x0 0x7009f000 0x0 0x1 1040 reg = <0x0 0x7009f000 0x0 0x1000>;
1048 interrupts = <GIC_SPI 49 IRQ_ <<
1049 resets = <&tegra_car 142>; 1041 resets = <&tegra_car 142>;
1050 reset-names = "padctl"; 1042 reset-names = "padctl";
1051 nvidia,pmc = <&tegra_pmc>; <<
1052 1043
1053 status = "disabled"; 1044 status = "disabled";
1054 1045
1055 pads { 1046 pads {
1056 usb2 { 1047 usb2 {
1057 clocks = <&te 1048 clocks = <&tegra_car TEGRA210_CLK_USB2_TRK>;
1058 clock-names = 1049 clock-names = "trk";
1059 status = "dis 1050 status = "disabled";
1060 1051
1061 lanes { 1052 lanes {
1062 usb2- 1053 usb2-0 {
1063 1054 status = "disabled";
1064 1055 #phy-cells = <0>;
1065 }; 1056 };
1066 1057
1067 usb2- 1058 usb2-1 {
1068 1059 status = "disabled";
1069 1060 #phy-cells = <0>;
1070 }; 1061 };
1071 1062
1072 usb2- 1063 usb2-2 {
1073 1064 status = "disabled";
1074 1065 #phy-cells = <0>;
1075 }; 1066 };
1076 1067
1077 usb2- 1068 usb2-3 {
1078 1069 status = "disabled";
1079 1070 #phy-cells = <0>;
1080 }; 1071 };
1081 }; 1072 };
1082 }; 1073 };
1083 1074
1084 hsic { 1075 hsic {
1085 clocks = <&te 1076 clocks = <&tegra_car TEGRA210_CLK_HSIC_TRK>;
1086 clock-names = 1077 clock-names = "trk";
1087 status = "dis 1078 status = "disabled";
1088 1079
1089 lanes { 1080 lanes {
1090 hsic- 1081 hsic-0 {
1091 1082 status = "disabled";
1092 1083 #phy-cells = <0>;
1093 }; 1084 };
1094 1085
1095 hsic- 1086 hsic-1 {
1096 1087 status = "disabled";
1097 1088 #phy-cells = <0>;
1098 }; 1089 };
1099 }; 1090 };
1100 }; 1091 };
1101 1092
1102 pcie { 1093 pcie {
1103 clocks = <&te 1094 clocks = <&tegra_car TEGRA210_CLK_PLL_E>;
1104 clock-names = 1095 clock-names = "pll";
1105 resets = <&te 1096 resets = <&tegra_car 205>;
1106 reset-names = 1097 reset-names = "phy";
1107 status = "dis 1098 status = "disabled";
1108 1099
1109 lanes { 1100 lanes {
1110 pcie- 1101 pcie-0 {
1111 1102 status = "disabled";
1112 1103 #phy-cells = <0>;
1113 }; 1104 };
1114 1105
1115 pcie- 1106 pcie-1 {
1116 1107 status = "disabled";
1117 1108 #phy-cells = <0>;
1118 }; 1109 };
1119 1110
1120 pcie- 1111 pcie-2 {
1121 1112 status = "disabled";
1122 1113 #phy-cells = <0>;
1123 }; 1114 };
1124 1115
1125 pcie- 1116 pcie-3 {
1126 1117 status = "disabled";
1127 1118 #phy-cells = <0>;
1128 }; 1119 };
1129 1120
1130 pcie- 1121 pcie-4 {
1131 1122 status = "disabled";
1132 1123 #phy-cells = <0>;
1133 }; 1124 };
1134 1125
1135 pcie- 1126 pcie-5 {
1136 1127 status = "disabled";
1137 1128 #phy-cells = <0>;
1138 }; 1129 };
1139 1130
1140 pcie- 1131 pcie-6 {
1141 1132 status = "disabled";
1142 1133 #phy-cells = <0>;
1143 }; 1134 };
1144 }; 1135 };
1145 }; 1136 };
1146 1137
1147 sata { 1138 sata {
1148 clocks = <&te 1139 clocks = <&tegra_car TEGRA210_CLK_PLL_E>;
1149 clock-names = 1140 clock-names = "pll";
1150 resets = <&te 1141 resets = <&tegra_car 204>;
1151 reset-names = 1142 reset-names = "phy";
1152 status = "dis 1143 status = "disabled";
1153 1144
1154 lanes { 1145 lanes {
1155 sata- 1146 sata-0 {
1156 1147 status = "disabled";
1157 1148 #phy-cells = <0>;
1158 }; 1149 };
1159 }; 1150 };
1160 }; 1151 };
1161 }; 1152 };
1162 1153
1163 ports { 1154 ports {
1164 usb2-0 { 1155 usb2-0 {
1165 status = "dis 1156 status = "disabled";
1166 }; 1157 };
1167 1158
1168 usb2-1 { 1159 usb2-1 {
1169 status = "dis 1160 status = "disabled";
1170 }; 1161 };
1171 1162
1172 usb2-2 { 1163 usb2-2 {
1173 status = "dis 1164 status = "disabled";
1174 }; 1165 };
1175 1166
1176 usb2-3 { 1167 usb2-3 {
1177 status = "dis 1168 status = "disabled";
1178 }; 1169 };
1179 1170
1180 hsic-0 { 1171 hsic-0 {
1181 status = "dis 1172 status = "disabled";
1182 }; 1173 };
1183 1174
1184 usb3-0 { 1175 usb3-0 {
1185 status = "dis 1176 status = "disabled";
1186 }; 1177 };
1187 1178
1188 usb3-1 { 1179 usb3-1 {
1189 status = "dis 1180 status = "disabled";
1190 }; 1181 };
1191 1182
1192 usb3-2 { 1183 usb3-2 {
1193 status = "dis 1184 status = "disabled";
1194 }; 1185 };
1195 1186
1196 usb3-3 { 1187 usb3-3 {
1197 status = "dis 1188 status = "disabled";
1198 }; 1189 };
1199 }; 1190 };
1200 }; 1191 };
1201 1192
1202 mmc@700b0000 { 1193 mmc@700b0000 {
1203 compatible = "nvidia,tegra210 1194 compatible = "nvidia,tegra210-sdhci";
1204 reg = <0x0 0x700b0000 0x0 0x2 1195 reg = <0x0 0x700b0000 0x0 0x200>;
1205 interrupts = <GIC_SPI 14 IRQ_ 1196 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1206 clocks = <&tegra_car TEGRA210 1197 clocks = <&tegra_car TEGRA210_CLK_SDMMC1>,
1207 <&tegra_car TEGRA210 1198 <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>;
1208 clock-names = "sdhci", "tmclk 1199 clock-names = "sdhci", "tmclk";
1209 resets = <&tegra_car 14>; 1200 resets = <&tegra_car 14>;
1210 reset-names = "sdhci"; 1201 reset-names = "sdhci";
1211 pinctrl-names = "sdmmc-3v3", 1202 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8",
1212 "sdmmc-3v3-dr 1203 "sdmmc-3v3-drv", "sdmmc-1v8-drv";
1213 pinctrl-0 = <&sdmmc1_3v3>; 1204 pinctrl-0 = <&sdmmc1_3v3>;
1214 pinctrl-1 = <&sdmmc1_1v8>; 1205 pinctrl-1 = <&sdmmc1_1v8>;
1215 pinctrl-2 = <&sdmmc1_3v3_drv> 1206 pinctrl-2 = <&sdmmc1_3v3_drv>;
1216 pinctrl-3 = <&sdmmc1_1v8_drv> 1207 pinctrl-3 = <&sdmmc1_1v8_drv>;
1217 nvidia,pad-autocal-pull-up-of 1208 nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>;
1218 nvidia,pad-autocal-pull-down- 1209 nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>;
1219 nvidia,pad-autocal-pull-up-of 1210 nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>;
1220 nvidia,pad-autocal-pull-down- 1211 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>;
1221 nvidia,default-tap = <0x2>; 1212 nvidia,default-tap = <0x2>;
1222 nvidia,default-trim = <0x4>; 1213 nvidia,default-trim = <0x4>;
1223 assigned-clocks = <&tegra_car 1214 assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>,
1224 <&tegra_car 1215 <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>,
1225 <&tegra_car 1216 <&tegra_car TEGRA210_CLK_PLL_C4>;
1226 assigned-clock-parents = <&te 1217 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
1227 assigned-clock-rates = <20000 1218 assigned-clock-rates = <200000000>, <1000000000>, <1000000000>;
1228 status = "disabled"; 1219 status = "disabled";
1229 }; 1220 };
1230 1221
1231 mmc@700b0200 { 1222 mmc@700b0200 {
1232 compatible = "nvidia,tegra210 1223 compatible = "nvidia,tegra210-sdhci";
1233 reg = <0x0 0x700b0200 0x0 0x2 1224 reg = <0x0 0x700b0200 0x0 0x200>;
1234 interrupts = <GIC_SPI 15 IRQ_ 1225 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1235 clocks = <&tegra_car TEGRA210 1226 clocks = <&tegra_car TEGRA210_CLK_SDMMC2>,
1236 <&tegra_car TEGRA210 1227 <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>;
1237 clock-names = "sdhci", "tmclk 1228 clock-names = "sdhci", "tmclk";
1238 resets = <&tegra_car 9>; 1229 resets = <&tegra_car 9>;
1239 reset-names = "sdhci"; 1230 reset-names = "sdhci";
1240 pinctrl-names = "sdmmc-1v8-dr 1231 pinctrl-names = "sdmmc-1v8-drv";
1241 pinctrl-0 = <&sdmmc2_1v8_drv> 1232 pinctrl-0 = <&sdmmc2_1v8_drv>;
1242 nvidia,pad-autocal-pull-up-of 1233 nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>;
1243 nvidia,pad-autocal-pull-down- 1234 nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>;
1244 nvidia,default-tap = <0x8>; 1235 nvidia,default-tap = <0x8>;
1245 nvidia,default-trim = <0x0>; 1236 nvidia,default-trim = <0x0>;
1246 status = "disabled"; 1237 status = "disabled";
1247 }; 1238 };
1248 1239
1249 mmc@700b0400 { 1240 mmc@700b0400 {
1250 compatible = "nvidia,tegra210 1241 compatible = "nvidia,tegra210-sdhci";
1251 reg = <0x0 0x700b0400 0x0 0x2 1242 reg = <0x0 0x700b0400 0x0 0x200>;
1252 interrupts = <GIC_SPI 19 IRQ_ 1243 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1253 clocks = <&tegra_car TEGRA210 1244 clocks = <&tegra_car TEGRA210_CLK_SDMMC3>,
1254 <&tegra_car TEGRA210 1245 <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>;
1255 clock-names = "sdhci", "tmclk 1246 clock-names = "sdhci", "tmclk";
1256 resets = <&tegra_car 69>; 1247 resets = <&tegra_car 69>;
1257 reset-names = "sdhci"; 1248 reset-names = "sdhci";
1258 pinctrl-names = "sdmmc-3v3", 1249 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8",
1259 "sdmmc-3v3-dr 1250 "sdmmc-3v3-drv", "sdmmc-1v8-drv";
1260 pinctrl-0 = <&sdmmc3_3v3>; 1251 pinctrl-0 = <&sdmmc3_3v3>;
1261 pinctrl-1 = <&sdmmc3_1v8>; 1252 pinctrl-1 = <&sdmmc3_1v8>;
1262 pinctrl-2 = <&sdmmc3_3v3_drv> 1253 pinctrl-2 = <&sdmmc3_3v3_drv>;
1263 pinctrl-3 = <&sdmmc3_1v8_drv> 1254 pinctrl-3 = <&sdmmc3_1v8_drv>;
1264 nvidia,pad-autocal-pull-up-of 1255 nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>;
1265 nvidia,pad-autocal-pull-down- 1256 nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>;
1266 nvidia,pad-autocal-pull-up-of 1257 nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>;
1267 nvidia,pad-autocal-pull-down- 1258 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>;
1268 nvidia,default-tap = <0x3>; 1259 nvidia,default-tap = <0x3>;
1269 nvidia,default-trim = <0x3>; 1260 nvidia,default-trim = <0x3>;
1270 status = "disabled"; 1261 status = "disabled";
1271 }; 1262 };
1272 1263
1273 mmc@700b0600 { 1264 mmc@700b0600 {
1274 compatible = "nvidia,tegra210 1265 compatible = "nvidia,tegra210-sdhci";
1275 reg = <0x0 0x700b0600 0x0 0x2 1266 reg = <0x0 0x700b0600 0x0 0x200>;
1276 interrupts = <GIC_SPI 31 IRQ_ 1267 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
1277 clocks = <&tegra_car TEGRA210 1268 clocks = <&tegra_car TEGRA210_CLK_SDMMC4>,
1278 <&tegra_car TEGRA210 1269 <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>;
1279 clock-names = "sdhci", "tmclk 1270 clock-names = "sdhci", "tmclk";
1280 resets = <&tegra_car 15>; 1271 resets = <&tegra_car 15>;
1281 reset-names = "sdhci"; 1272 reset-names = "sdhci";
1282 pinctrl-names = "sdmmc-3v3-dr 1273 pinctrl-names = "sdmmc-3v3-drv", "sdmmc-1v8-drv";
1283 pinctrl-0 = <&sdmmc4_1v8_drv> 1274 pinctrl-0 = <&sdmmc4_1v8_drv>;
1284 pinctrl-1 = <&sdmmc4_1v8_drv> 1275 pinctrl-1 = <&sdmmc4_1v8_drv>;
1285 nvidia,pad-autocal-pull-up-of 1276 nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>;
1286 nvidia,pad-autocal-pull-down- 1277 nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>;
1287 nvidia,default-tap = <0x8>; 1278 nvidia,default-tap = <0x8>;
1288 nvidia,default-trim = <0x0>; 1279 nvidia,default-trim = <0x0>;
1289 assigned-clocks = <&tegra_car 1280 assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>,
1290 <&tegra_car 1281 <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
1291 assigned-clock-parents = <&te 1282 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
1292 nvidia,dqs-trim = <40>; 1283 nvidia,dqs-trim = <40>;
1293 mmc-hs400-1_8v; 1284 mmc-hs400-1_8v;
1294 status = "disabled"; 1285 status = "disabled";
1295 }; 1286 };
1296 1287
1297 usb@700d0000 { 1288 usb@700d0000 {
1298 compatible = "nvidia,tegra210 1289 compatible = "nvidia,tegra210-xudc";
1299 reg = <0x0 0x700d0000 0x0 0x8 1290 reg = <0x0 0x700d0000 0x0 0x8000>,
1300 <0x0 0x700d8000 0x0 0x1 1291 <0x0 0x700d8000 0x0 0x1000>,
1301 <0x0 0x700d9000 0x0 0x1 1292 <0x0 0x700d9000 0x0 0x1000>;
1302 reg-names = "base", "fpci", " 1293 reg-names = "base", "fpci", "ipfs";
1303 interrupts = <GIC_SPI 44 IRQ_ 1294 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
1304 clocks = <&tegra_car TEGRA210 1295 clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>,
1305 <&tegra_car TEGRA210 1296 <&tegra_car TEGRA210_CLK_XUSB_SS>,
1306 <&tegra_car TEGRA210 1297 <&tegra_car TEGRA210_CLK_XUSB_SSP_SRC>,
1307 <&tegra_car TEGRA210 1298 <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>,
1308 <&tegra_car TEGRA210 1299 <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>;
1309 clock-names = "dev", "ss", "s 1300 clock-names = "dev", "ss", "ss_src", "fs_src", "hs_src";
1310 power-domains = <&pd_xusbdev> 1301 power-domains = <&pd_xusbdev>, <&pd_xusbss>;
1311 power-domain-names = "dev", " 1302 power-domain-names = "dev", "ss";
1312 nvidia,xusb-padctl = <&padctl 1303 nvidia,xusb-padctl = <&padctl>;
1313 status = "disabled"; 1304 status = "disabled";
1314 }; 1305 };
1315 1306
1316 soctherm: thermal-sensor@700e2000 { <<
1317 compatible = "nvidia,tegra210 <<
1318 reg = <0x0 0x700e2000 0x0 0x6 <<
1319 <0x0 0x60006000 0x0 0x4 <<
1320 reg-names = "soctherm-reg", " <<
1321 interrupts = <GIC_SPI 48 IRQ_ <<
1322 <GIC_SPI 51 IRQ_ <<
1323 interrupt-names = "thermal", <<
1324 clocks = <&tegra_car TEGRA210 <<
1325 <&tegra_car TEGRA210_ <<
1326 clock-names = "tsensor", "soc <<
1327 resets = <&tegra_car 78>; <<
1328 reset-names = "soctherm"; <<
1329 #thermal-sensor-cells = <1>; <<
1330 <<
1331 throttle-cfgs { <<
1332 throttle_heavy: heavy <<
1333 nvidia,priori <<
1334 nvidia,cpu-th <<
1335 nvidia,gpu-th <<
1336 <<
1337 #cooling-cell <<
1338 }; <<
1339 }; <<
1340 }; <<
1341 <<
1342 mipi: mipi@700e3000 { 1307 mipi: mipi@700e3000 {
1343 compatible = "nvidia,tegra210 1308 compatible = "nvidia,tegra210-mipi";
1344 reg = <0x0 0x700e3000 0x0 0x1 1309 reg = <0x0 0x700e3000 0x0 0x100>;
1345 clocks = <&tegra_car TEGRA210 1310 clocks = <&tegra_car TEGRA210_CLK_MIPI_CAL>;
1346 clock-names = "mipi-cal"; 1311 clock-names = "mipi-cal";
1347 power-domains = <&pd_sor>; 1312 power-domains = <&pd_sor>;
1348 #nvidia,mipi-calibrate-cells 1313 #nvidia,mipi-calibrate-cells = <1>;
1349 }; 1314 };
1350 1315
1351 dfll: clock@70110000 { 1316 dfll: clock@70110000 {
1352 compatible = "nvidia,tegra210 1317 compatible = "nvidia,tegra210-dfll";
1353 reg = <0 0x70110000 0 0x100>, 1318 reg = <0 0x70110000 0 0x100>, /* DFLL control */
1354 <0 0x70110000 0 0x100>, 1319 <0 0x70110000 0 0x100>, /* I2C output control */
1355 <0 0x70110100 0 0x100>, 1320 <0 0x70110100 0 0x100>, /* Integrated I2C controller */
1356 <0 0x70110200 0 0x100>; 1321 <0 0x70110200 0 0x100>; /* Look-up table RAM */
1357 interrupts = <GIC_SPI 62 IRQ_ 1322 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
1358 clocks = <&tegra_car TEGRA210 1323 clocks = <&tegra_car TEGRA210_CLK_DFLL_SOC>,
1359 <&tegra_car TEGRA210 1324 <&tegra_car TEGRA210_CLK_DFLL_REF>,
1360 <&tegra_car TEGRA210 1325 <&tegra_car TEGRA210_CLK_I2C5>;
1361 clock-names = "soc", "ref", " 1326 clock-names = "soc", "ref", "i2c";
1362 resets = <&tegra_car TEGRA210 !! 1327 resets = <&tegra_car TEGRA210_RST_DFLL_DVCO>;
1363 <&tegra_car 155>; !! 1328 reset-names = "dvco";
1364 reset-names = "dvco", "dfll"; <<
1365 #clock-cells = <0>; 1329 #clock-cells = <0>;
1366 clock-output-names = "dfllCPU 1330 clock-output-names = "dfllCPU_out";
1367 status = "disabled"; 1331 status = "disabled";
1368 }; 1332 };
1369 1333
1370 aconnect@702c0000 { 1334 aconnect@702c0000 {
1371 compatible = "nvidia,tegra210 1335 compatible = "nvidia,tegra210-aconnect";
1372 clocks = <&tegra_car TEGRA210 1336 clocks = <&tegra_car TEGRA210_CLK_APE>,
1373 <&tegra_car TEGRA210 1337 <&tegra_car TEGRA210_CLK_APB2APE>;
1374 clock-names = "ape", "apb2ape 1338 clock-names = "ape", "apb2ape";
1375 power-domains = <&pd_audio>; 1339 power-domains = <&pd_audio>;
1376 #address-cells = <1>; 1340 #address-cells = <1>;
1377 #size-cells = <1>; 1341 #size-cells = <1>;
1378 ranges = <0x702c0000 0x0 0x70 1342 ranges = <0x702c0000 0x0 0x702c0000 0x00040000>;
1379 status = "disabled"; 1343 status = "disabled";
1380 1344
1381 tegra_ahub: ahub@702d0800 { !! 1345 adma: dma@702e2000 {
1382 compatible = "nvidia, <<
1383 reg = <0x702d0800 0x8 <<
1384 clocks = <&tegra_car <<
1385 clock-names = "ahub"; <<
1386 assigned-clocks = <&t <<
1387 assigned-clock-parent <<
1388 assigned-clock-rates <<
1389 #address-cells = <1>; <<
1390 #size-cells = <1>; <<
1391 ranges = <0x702d0000 <<
1392 status = "disabled"; <<
1393 <<
1394 tegra_admaif: admaif@ <<
1395 compatible = <<
1396 reg = <0x702d <<
1397 dmas = <&adma <<
1398 <&adma <<
1399 <&adma <<
1400 <&adma <<
1401 <&adma <<
1402 <&adma <<
1403 <&adma <<
1404 <&adma <<
1405 <&adma <<
1406 <&adma <<
1407 dma-names = " <<
1408 " <<
1409 " <<
1410 " <<
1411 " <<
1412 " <<
1413 " <<
1414 " <<
1415 " <<
1416 " <<
1417 status = "dis <<
1418 <<
1419 ports { <<
1420 #addr <<
1421 #size <<
1422 <<
1423 admai <<
1424 <<
1425 <<
1426 <<
1427 <<
1428 <<
1429 }; <<
1430 <<
1431 admai <<
1432 <<
1433 <<
1434 <<
1435 <<
1436 <<
1437 }; <<
1438 <<
1439 admai <<
1440 <<
1441 <<
1442 <<
1443 <<
1444 <<
1445 }; <<
1446 <<
1447 admai <<
1448 <<
1449 <<
1450 <<
1451 <<
1452 <<
1453 }; <<
1454 <<
1455 admai <<
1456 <<
1457 <<
1458 <<
1459 <<
1460 <<
1461 }; <<
1462 <<
1463 admai <<
1464 <<
1465 <<
1466 <<
1467 <<
1468 <<
1469 }; <<
1470 <<
1471 admai <<
1472 <<
1473 <<
1474 <<
1475 <<
1476 <<
1477 }; <<
1478 <<
1479 admai <<
1480 <<
1481 <<
1482 <<
1483 <<
1484 <<
1485 }; <<
1486 <<
1487 admai <<
1488 <<
1489 <<
1490 <<
1491 <<
1492 <<
1493 }; <<
1494 <<
1495 admai <<
1496 <<
1497 <<
1498 <<
1499 <<
1500 <<
1501 }; <<
1502 }; <<
1503 }; <<
1504 <<
1505 tegra_i2s1: i2s@702d1 <<
1506 compatible = <<
1507 reg = <0x702d <<
1508 clocks = <&te <<
1509 <&te <<
1510 clock-names = <<
1511 assigned-cloc <<
1512 assigned-cloc <<
1513 assigned-cloc <<
1514 sound-name-pr <<
1515 status = "dis <<
1516 }; <<
1517 <<
1518 tegra_i2s2: i2s@702d1 <<
1519 compatible = <<
1520 reg = <0x702d <<
1521 clocks = <&te <<
1522 <&te <<
1523 clock-names = <<
1524 assigned-cloc <<
1525 assigned-cloc <<
1526 assigned-cloc <<
1527 sound-name-pr <<
1528 status = "dis <<
1529 }; <<
1530 <<
1531 tegra_i2s3: i2s@702d1 <<
1532 compatible = <<
1533 reg = <0x702d <<
1534 clocks = <&te <<
1535 <&te <<
1536 clock-names = <<
1537 assigned-cloc <<
1538 assigned-cloc <<
1539 assigned-cloc <<
1540 sound-name-pr <<
1541 status = "dis <<
1542 }; <<
1543 <<
1544 tegra_i2s4: i2s@702d1 <<
1545 compatible = <<
1546 reg = <0x702d <<
1547 clocks = <&te <<
1548 <&te <<
1549 clock-names = <<
1550 assigned-cloc <<
1551 assigned-cloc <<
1552 assigned-cloc <<
1553 sound-name-pr <<
1554 status = "dis <<
1555 }; <<
1556 <<
1557 tegra_i2s5: i2s@702d1 <<
1558 compatible = <<
1559 reg = <0x702d <<
1560 clocks = <&te <<
1561 <&te <<
1562 clock-names = <<
1563 assigned-cloc <<
1564 assigned-cloc <<
1565 assigned-cloc <<
1566 sound-name-pr <<
1567 status = "dis <<
1568 }; <<
1569 <<
1570 tegra_sfc1: sfc@702d2 <<
1571 compatible = <<
1572 reg = <0x702d <<
1573 sound-name-pr <<
1574 status = "dis <<
1575 }; <<
1576 <<
1577 tegra_sfc2: sfc@702d2 <<
1578 compatible = <<
1579 reg = <0x702d <<
1580 sound-name-pr <<
1581 status = "dis <<
1582 }; <<
1583 <<
1584 tegra_sfc3: sfc@702d2 <<
1585 compatible = <<
1586 reg = <0x702d <<
1587 sound-name-pr <<
1588 status = "dis <<
1589 }; <<
1590 <<
1591 tegra_sfc4: sfc@702d2 <<
1592 compatible = <<
1593 reg = <0x702d <<
1594 sound-name-pr <<
1595 status = "dis <<
1596 }; <<
1597 <<
1598 tegra_amx1: amx@702d3 <<
1599 compatible = <<
1600 reg = <0x702d <<
1601 sound-name-pr <<
1602 status = "dis <<
1603 }; <<
1604 <<
1605 tegra_amx2: amx@702d3 <<
1606 compatible = <<
1607 reg = <0x702d <<
1608 sound-name-pr <<
1609 status = "dis <<
1610 }; <<
1611 <<
1612 tegra_adx1: adx@702d3 <<
1613 compatible = <<
1614 reg = <0x702d <<
1615 sound-name-pr <<
1616 status = "dis <<
1617 }; <<
1618 <<
1619 tegra_adx2: adx@702d3 <<
1620 compatible = <<
1621 reg = <0x702d <<
1622 sound-name-pr <<
1623 status = "dis <<
1624 }; <<
1625 <<
1626 tegra_dmic1: dmic@702 <<
1627 compatible = <<
1628 reg = <0x702d <<
1629 clocks = <&te <<
1630 clock-names = <<
1631 assigned-cloc <<
1632 assigned-cloc <<
1633 assigned-cloc <<
1634 sound-name-pr <<
1635 status = "dis <<
1636 }; <<
1637 <<
1638 tegra_dmic2: dmic@702 <<
1639 compatible = <<
1640 reg = <0x702d <<
1641 clocks = <&te <<
1642 clock-names = <<
1643 assigned-cloc <<
1644 assigned-cloc <<
1645 assigned-cloc <<
1646 sound-name-pr <<
1647 status = "dis <<
1648 }; <<
1649 <<
1650 tegra_dmic3: dmic@702 <<
1651 compatible = <<
1652 reg = <0x702d <<
1653 clocks = <&te <<
1654 clock-names = <<
1655 assigned-cloc <<
1656 assigned-cloc <<
1657 assigned-cloc <<
1658 sound-name-pr <<
1659 status = "dis <<
1660 }; <<
1661 <<
1662 tegra_ope1: processin <<
1663 compatible = <<
1664 reg = <0x702d <<
1665 #address-cell <<
1666 #size-cells = <<
1667 ranges; <<
1668 sound-name-pr <<
1669 status = "dis <<
1670 <<
1671 equalizer@702 <<
1672 compa <<
1673 reg = <<
1674 }; <<
1675 <<
1676 dynamic-range <<
1677 compa <<
1678 reg = <<
1679 }; <<
1680 }; <<
1681 <<
1682 tegra_ope2: processin <<
1683 compatible = <<
1684 reg = <0x702d <<
1685 #address-cell <<
1686 #size-cells = <<
1687 ranges; <<
1688 sound-name-pr <<
1689 status = "dis <<
1690 <<
1691 equalizer@702 <<
1692 compa <<
1693 reg = <<
1694 }; <<
1695 <<
1696 dynamic-range <<
1697 compa <<
1698 reg = <<
1699 }; <<
1700 }; <<
1701 <<
1702 tegra_mvc1: mvc@702da <<
1703 compatible = <<
1704 reg = <0x702d <<
1705 sound-name-pr <<
1706 status = "dis <<
1707 }; <<
1708 <<
1709 tegra_mvc2: mvc@702da <<
1710 compatible = <<
1711 reg = <0x702d <<
1712 sound-name-pr <<
1713 status = "dis <<
1714 }; <<
1715 <<
1716 tegra_amixer: amixer@ <<
1717 compatible = <<
1718 reg = <0x702d <<
1719 sound-name-pr <<
1720 status = "dis <<
1721 }; <<
1722 <<
1723 ports { <<
1724 #address-cell <<
1725 #size-cells = <<
1726 <<
1727 port@0 { <<
1728 reg = <<
1729 <<
1730 xbar_ <<
1731 <<
1732 }; <<
1733 }; <<
1734 <<
1735 port@1 { <<
1736 reg = <<
1737 <<
1738 xbar_ <<
1739 <<
1740 }; <<
1741 }; <<
1742 <<
1743 port@2 { <<
1744 reg = <<
1745 <<
1746 xbar_ <<
1747 <<
1748 }; <<
1749 }; <<
1750 <<
1751 port@3 { <<
1752 reg = <<
1753 <<
1754 xbar_ <<
1755 <<
1756 }; <<
1757 }; <<
1758 <<
1759 port@4 { <<
1760 reg = <<
1761 xbar_ <<
1762 <<
1763 }; <<
1764 }; <<
1765 port@5 { <<
1766 reg = <<
1767 <<
1768 xbar_ <<
1769 <<
1770 }; <<
1771 }; <<
1772 <<
1773 port@6 { <<
1774 reg = <<
1775 <<
1776 xbar_ <<
1777 <<
1778 }; <<
1779 }; <<
1780 <<
1781 port@7 { <<
1782 reg = <<
1783 <<
1784 xbar_ <<
1785 <<
1786 }; <<
1787 }; <<
1788 <<
1789 port@8 { <<
1790 reg = <<
1791 <<
1792 xbar_ <<
1793 <<
1794 }; <<
1795 }; <<
1796 <<
1797 port@9 { <<
1798 reg = <<
1799 <<
1800 xbar_ <<
1801 <<
1802 }; <<
1803 }; <<
1804 }; <<
1805 }; <<
1806 <<
1807 adma: dma-controller@702e2000 <<
1808 compatible = "nvidia, 1346 compatible = "nvidia,tegra210-adma";
1809 reg = <0x702e2000 0x2 1347 reg = <0x702e2000 0x2000>;
1810 interrupt-parent = <& 1348 interrupt-parent = <&agic>;
1811 interrupts = <GIC_SPI 1349 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
1812 <GIC_SPI 1350 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
1813 <GIC_SPI 1351 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
1814 <GIC_SPI 1352 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
1815 <GIC_SPI 1353 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
1816 <GIC_SPI 1354 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
1817 <GIC_SPI 1355 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
1818 <GIC_SPI 1356 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
1819 <GIC_SPI 1357 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
1820 <GIC_SPI 1358 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
1821 <GIC_SPI 1359 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
1822 <GIC_SPI 1360 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
1823 <GIC_SPI 1361 <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
1824 <GIC_SPI 1362 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
1825 <GIC_SPI 1363 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
1826 <GIC_SPI 1364 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
1827 <GIC_SPI 1365 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
1828 <GIC_SPI 1366 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
1829 <GIC_SPI 1367 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
1830 <GIC_SPI 1368 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
1831 <GIC_SPI 1369 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
1832 <GIC_SPI 1370 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1833 #dma-cells = <1>; 1371 #dma-cells = <1>;
1834 clocks = <&tegra_car 1372 clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>;
1835 clock-names = "d_audi 1373 clock-names = "d_audio";
1836 status = "disabled"; 1374 status = "disabled";
1837 }; 1375 };
1838 1376
1839 agic: interrupt-controller@70 1377 agic: interrupt-controller@702f9000 {
1840 compatible = "nvidia, 1378 compatible = "nvidia,tegra210-agic";
1841 #interrupt-cells = <3 1379 #interrupt-cells = <3>;
1842 interrupt-controller; 1380 interrupt-controller;
1843 reg = <0x702f9000 0x1 1381 reg = <0x702f9000 0x1000>,
1844 <0x702fa000 0x2 1382 <0x702fa000 0x2000>;
1845 interrupts = <GIC_SPI 1383 interrupts = <GIC_SPI 102 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1846 clocks = <&tegra_car 1384 clocks = <&tegra_car TEGRA210_CLK_APE>;
1847 clock-names = "clk"; 1385 clock-names = "clk";
1848 status = "disabled"; 1386 status = "disabled";
1849 }; 1387 };
1850 }; 1388 };
1851 1389
1852 spi@70410000 { 1390 spi@70410000 {
1853 compatible = "nvidia,tegra210 1391 compatible = "nvidia,tegra210-qspi";
1854 reg = <0x0 0x70410000 0x0 0x1 1392 reg = <0x0 0x70410000 0x0 0x1000>;
1855 interrupts = <GIC_SPI 10 IRQ_ 1393 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1856 #address-cells = <1>; 1394 #address-cells = <1>;
1857 #size-cells = <0>; 1395 #size-cells = <0>;
1858 clocks = <&tegra_car TEGRA210 !! 1396 clocks = <&tegra_car TEGRA210_CLK_QSPI>;
1859 <&tegra_car TEGRA210 !! 1397 clock-names = "qspi";
1860 clock-names = "qspi", "qspi_o <<
1861 resets = <&tegra_car 211>; 1398 resets = <&tegra_car 211>;
>> 1399 reset-names = "qspi";
1862 dmas = <&apbdma 5>, <&apbdma 1400 dmas = <&apbdma 5>, <&apbdma 5>;
1863 dma-names = "rx", "tx"; 1401 dma-names = "rx", "tx";
1864 status = "disabled"; 1402 status = "disabled";
1865 }; 1403 };
1866 1404
1867 usb@7d000000 { 1405 usb@7d000000 {
1868 compatible = "nvidia,tegra210 !! 1406 compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci";
1869 reg = <0x0 0x7d000000 0x0 0x4 1407 reg = <0x0 0x7d000000 0x0 0x4000>;
1870 interrupts = <GIC_SPI 20 IRQ_ 1408 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1871 phy_type = "utmi"; 1409 phy_type = "utmi";
1872 clocks = <&tegra_car TEGRA210 1410 clocks = <&tegra_car TEGRA210_CLK_USBD>;
1873 clock-names = "usb"; 1411 clock-names = "usb";
1874 resets = <&tegra_car 22>; 1412 resets = <&tegra_car 22>;
1875 reset-names = "usb"; 1413 reset-names = "usb";
1876 nvidia,phy = <&phy1>; 1414 nvidia,phy = <&phy1>;
1877 status = "disabled"; 1415 status = "disabled";
1878 }; 1416 };
1879 1417
1880 phy1: usb-phy@7d000000 { 1418 phy1: usb-phy@7d000000 {
1881 compatible = "nvidia,tegra210 1419 compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy";
1882 reg = <0x0 0x7d000000 0x0 0x4 1420 reg = <0x0 0x7d000000 0x0 0x4000>,
1883 <0x0 0x7d000000 0x0 0x4 1421 <0x0 0x7d000000 0x0 0x4000>;
1884 phy_type = "utmi"; 1422 phy_type = "utmi";
1885 clocks = <&tegra_car TEGRA210 1423 clocks = <&tegra_car TEGRA210_CLK_USBD>,
1886 <&tegra_car TEGRA210 1424 <&tegra_car TEGRA210_CLK_PLL_U>,
1887 <&tegra_car TEGRA210 1425 <&tegra_car TEGRA210_CLK_USBD>;
1888 clock-names = "reg", "pll_u", 1426 clock-names = "reg", "pll_u", "utmi-pads";
1889 resets = <&tegra_car 22>, <&t 1427 resets = <&tegra_car 22>, <&tegra_car 22>;
1890 reset-names = "usb", "utmi-pa 1428 reset-names = "usb", "utmi-pads";
1891 nvidia,hssync-start-delay = < 1429 nvidia,hssync-start-delay = <0>;
1892 nvidia,idle-wait-delay = <17> 1430 nvidia,idle-wait-delay = <17>;
1893 nvidia,elastic-limit = <16>; 1431 nvidia,elastic-limit = <16>;
1894 nvidia,term-range-adj = <6>; 1432 nvidia,term-range-adj = <6>;
1895 nvidia,xcvr-setup = <9>; 1433 nvidia,xcvr-setup = <9>;
1896 nvidia,xcvr-lsfslew = <0>; 1434 nvidia,xcvr-lsfslew = <0>;
1897 nvidia,xcvr-lsrslew = <3>; 1435 nvidia,xcvr-lsrslew = <3>;
1898 nvidia,hssquelch-level = <2>; 1436 nvidia,hssquelch-level = <2>;
1899 nvidia,hsdiscon-level = <5>; 1437 nvidia,hsdiscon-level = <5>;
1900 nvidia,xcvr-hsslew = <12>; 1438 nvidia,xcvr-hsslew = <12>;
1901 nvidia,has-utmi-pad-registers 1439 nvidia,has-utmi-pad-registers;
1902 status = "disabled"; 1440 status = "disabled";
1903 }; 1441 };
1904 1442
1905 usb@7d004000 { 1443 usb@7d004000 {
1906 compatible = "nvidia,tegra210 !! 1444 compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci";
1907 reg = <0x0 0x7d004000 0x0 0x4 1445 reg = <0x0 0x7d004000 0x0 0x4000>;
1908 interrupts = <GIC_SPI 21 IRQ_ 1446 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
1909 phy_type = "utmi"; 1447 phy_type = "utmi";
1910 clocks = <&tegra_car TEGRA210 1448 clocks = <&tegra_car TEGRA210_CLK_USB2>;
1911 clock-names = "usb"; 1449 clock-names = "usb";
1912 resets = <&tegra_car 58>; 1450 resets = <&tegra_car 58>;
1913 reset-names = "usb"; 1451 reset-names = "usb";
1914 nvidia,phy = <&phy2>; 1452 nvidia,phy = <&phy2>;
1915 status = "disabled"; 1453 status = "disabled";
1916 }; 1454 };
1917 1455
1918 phy2: usb-phy@7d004000 { 1456 phy2: usb-phy@7d004000 {
1919 compatible = "nvidia,tegra210 1457 compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy";
1920 reg = <0x0 0x7d004000 0x0 0x4 1458 reg = <0x0 0x7d004000 0x0 0x4000>,
1921 <0x0 0x7d000000 0x0 0x4 1459 <0x0 0x7d000000 0x0 0x4000>;
1922 phy_type = "utmi"; 1460 phy_type = "utmi";
1923 clocks = <&tegra_car TEGRA210 1461 clocks = <&tegra_car TEGRA210_CLK_USB2>,
1924 <&tegra_car TEGRA210 1462 <&tegra_car TEGRA210_CLK_PLL_U>,
1925 <&tegra_car TEGRA210 1463 <&tegra_car TEGRA210_CLK_USBD>;
1926 clock-names = "reg", "pll_u", 1464 clock-names = "reg", "pll_u", "utmi-pads";
1927 resets = <&tegra_car 58>, <&t 1465 resets = <&tegra_car 58>, <&tegra_car 22>;
1928 reset-names = "usb", "utmi-pa 1466 reset-names = "usb", "utmi-pads";
1929 nvidia,hssync-start-delay = < 1467 nvidia,hssync-start-delay = <0>;
1930 nvidia,idle-wait-delay = <17> 1468 nvidia,idle-wait-delay = <17>;
1931 nvidia,elastic-limit = <16>; 1469 nvidia,elastic-limit = <16>;
1932 nvidia,term-range-adj = <6>; 1470 nvidia,term-range-adj = <6>;
1933 nvidia,xcvr-setup = <9>; 1471 nvidia,xcvr-setup = <9>;
1934 nvidia,xcvr-lsfslew = <0>; 1472 nvidia,xcvr-lsfslew = <0>;
1935 nvidia,xcvr-lsrslew = <3>; 1473 nvidia,xcvr-lsrslew = <3>;
1936 nvidia,hssquelch-level = <2>; 1474 nvidia,hssquelch-level = <2>;
1937 nvidia,hsdiscon-level = <5>; 1475 nvidia,hsdiscon-level = <5>;
1938 nvidia,xcvr-hsslew = <12>; 1476 nvidia,xcvr-hsslew = <12>;
1939 status = "disabled"; 1477 status = "disabled";
1940 }; 1478 };
1941 1479
1942 cpus { 1480 cpus {
1943 #address-cells = <1>; 1481 #address-cells = <1>;
1944 #size-cells = <0>; 1482 #size-cells = <0>;
1945 1483
1946 cpu@0 { 1484 cpu@0 {
1947 device_type = "cpu"; 1485 device_type = "cpu";
1948 compatible = "arm,cor 1486 compatible = "arm,cortex-a57";
1949 reg = <0>; 1487 reg = <0>;
1950 clocks = <&tegra_car 1488 clocks = <&tegra_car TEGRA210_CLK_CCLK_G>,
1951 <&tegra_car 1489 <&tegra_car TEGRA210_CLK_PLL_X>,
1952 <&tegra_car 1490 <&tegra_car TEGRA210_CLK_PLL_P_OUT4>,
1953 <&dfll>; 1491 <&dfll>;
1954 clock-names = "cpu_g" 1492 clock-names = "cpu_g", "pll_x", "pll_p", "dfll";
1955 clock-latency = <3000 1493 clock-latency = <300000>;
1956 cpu-idle-states = <&C 1494 cpu-idle-states = <&CPU_SLEEP>;
1957 next-level-cache = <& 1495 next-level-cache = <&L2>;
1958 }; 1496 };
1959 1497
1960 cpu@1 { 1498 cpu@1 {
1961 device_type = "cpu"; 1499 device_type = "cpu";
1962 compatible = "arm,cor 1500 compatible = "arm,cortex-a57";
1963 reg = <1>; 1501 reg = <1>;
1964 cpu-idle-states = <&C 1502 cpu-idle-states = <&CPU_SLEEP>;
1965 next-level-cache = <& 1503 next-level-cache = <&L2>;
1966 }; 1504 };
1967 1505
1968 cpu@2 { 1506 cpu@2 {
1969 device_type = "cpu"; 1507 device_type = "cpu";
1970 compatible = "arm,cor 1508 compatible = "arm,cortex-a57";
1971 reg = <2>; 1509 reg = <2>;
1972 cpu-idle-states = <&C 1510 cpu-idle-states = <&CPU_SLEEP>;
1973 next-level-cache = <& 1511 next-level-cache = <&L2>;
1974 }; 1512 };
1975 1513
1976 cpu@3 { 1514 cpu@3 {
1977 device_type = "cpu"; 1515 device_type = "cpu";
1978 compatible = "arm,cor 1516 compatible = "arm,cortex-a57";
1979 reg = <3>; 1517 reg = <3>;
1980 cpu-idle-states = <&C 1518 cpu-idle-states = <&CPU_SLEEP>;
1981 next-level-cache = <& 1519 next-level-cache = <&L2>;
1982 }; 1520 };
1983 1521
1984 idle-states { 1522 idle-states {
1985 entry-method = "psci" 1523 entry-method = "psci";
1986 1524
1987 CPU_SLEEP: cpu-sleep 1525 CPU_SLEEP: cpu-sleep {
1988 compatible = 1526 compatible = "arm,idle-state";
1989 arm,psci-susp 1527 arm,psci-suspend-param = <0x40000007>;
1990 entry-latency 1528 entry-latency-us = <100>;
1991 exit-latency- 1529 exit-latency-us = <30>;
1992 min-residency 1530 min-residency-us = <1000>;
1993 wakeup-latenc 1531 wakeup-latency-us = <130>;
1994 idle-state-na 1532 idle-state-name = "cpu-sleep";
1995 status = "dis 1533 status = "disabled";
1996 }; 1534 };
1997 }; 1535 };
1998 1536
1999 L2: l2-cache { 1537 L2: l2-cache {
2000 compatible = "cache"; 1538 compatible = "cache";
2001 cache-level = <2>; <<
2002 cache-unified; <<
2003 }; 1539 };
2004 }; 1540 };
2005 1541
2006 pmu { 1542 pmu {
2007 compatible = "arm,cortex-a57- !! 1543 compatible = "arm,armv8-pmuv3";
2008 interrupts = <GIC_SPI 144 IRQ 1544 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
2009 <GIC_SPI 145 IRQ 1545 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
2010 <GIC_SPI 146 IRQ 1546 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
2011 <GIC_SPI 147 IRQ 1547 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
2012 interrupt-affinity = <&{/cpus 1548 interrupt-affinity = <&{/cpus/cpu@0} &{/cpus/cpu@1}
2013 &{/cpus 1549 &{/cpus/cpu@2} &{/cpus/cpu@3}>;
2014 }; 1550 };
2015 1551
2016 sound { !! 1552 timer {
2017 status = "disabled"; !! 1553 compatible = "arm,armv8-timer";
>> 1554 interrupts = <GIC_PPI 13
>> 1555 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
>> 1556 <GIC_PPI 14
>> 1557 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
>> 1558 <GIC_PPI 11
>> 1559 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
>> 1560 <GIC_PPI 10
>> 1561 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
>> 1562 interrupt-parent = <&gic>;
>> 1563 arm,no-tick-in-suspend;
>> 1564 };
>> 1565
>> 1566 soctherm: thermal-sensor@700e2000 {
>> 1567 compatible = "nvidia,tegra210-soctherm";
>> 1568 reg = <0x0 0x700e2000 0x0 0x600>, /* SOC_THERM reg_base */
>> 1569 <0x0 0x60006000 0x0 0x400>; /* CAR reg_base */
>> 1570 reg-names = "soctherm-reg", "car-reg";
>> 1571 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
>> 1572 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
>> 1573 interrupt-names = "thermal", "edp";
>> 1574 clocks = <&tegra_car TEGRA210_CLK_TSENSOR>,
>> 1575 <&tegra_car TEGRA210_CLK_SOC_THERM>;
>> 1576 clock-names = "tsensor", "soctherm";
>> 1577 resets = <&tegra_car 78>;
>> 1578 reset-names = "soctherm";
>> 1579 #thermal-sensor-cells = <1>;
2018 1580
2019 clocks = <&tegra_car TEGRA210 !! 1581 throttle-cfgs {
2020 <&tegra_car TEGRA210 !! 1582 throttle_heavy: heavy {
2021 clock-names = "pll_a", "plla_ !! 1583 nvidia,priority = <100>;
2022 !! 1584 nvidia,cpu-throt-percent = <85>;
2023 assigned-clocks = <&tegra_car !! 1585
2024 <&tegra_car !! 1586 #cooling-cells = <2>;
2025 <&tegra_car !! 1587 };
2026 assigned-clock-parents = <0>, !! 1588 };
2027 assigned-clock-rates = <36864 <<
2028 }; 1589 };
2029 1590
2030 thermal-zones { 1591 thermal-zones {
2031 cpu-thermal { !! 1592 cpu {
2032 polling-delay-passive 1593 polling-delay-passive = <1000>;
2033 polling-delay = <0>; 1594 polling-delay = <0>;
2034 1595
2035 thermal-sensors = 1596 thermal-sensors =
2036 <&soctherm TE 1597 <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>;
2037 1598
2038 trips { 1599 trips {
2039 cpu-shutdown- 1600 cpu-shutdown-trip {
2040 tempe 1601 temperature = <102500>;
2041 hyste 1602 hysteresis = <0>;
2042 type 1603 type = "critical";
2043 }; 1604 };
2044 1605
2045 cpu_throttle_ 1606 cpu_throttle_trip: throttle-trip {
2046 tempe 1607 temperature = <98500>;
2047 hyste 1608 hysteresis = <1000>;
2048 type 1609 type = "hot";
2049 }; 1610 };
2050 }; 1611 };
2051 1612
2052 cooling-maps { 1613 cooling-maps {
2053 map0 { 1614 map0 {
2054 trip 1615 trip = <&cpu_throttle_trip>;
2055 cooli 1616 cooling-device = <&throttle_heavy 1 1>;
2056 }; 1617 };
2057 }; 1618 };
2058 }; 1619 };
2059 1620
2060 mem-thermal { !! 1621 mem {
2061 polling-delay-passive 1622 polling-delay-passive = <0>;
2062 polling-delay = <0>; 1623 polling-delay = <0>;
2063 1624
2064 thermal-sensors = 1625 thermal-sensors =
2065 <&soctherm TE 1626 <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>;
2066 1627
2067 trips { 1628 trips {
2068 dram_nominal: 1629 dram_nominal: mem-nominal-trip {
2069 tempe 1630 temperature = <50000>;
2070 hyste 1631 hysteresis = <1000>;
2071 type 1632 type = "passive";
2072 }; 1633 };
2073 1634
2074 dram_throttle 1635 dram_throttle: mem-throttle-trip {
2075 tempe 1636 temperature = <70000>;
2076 hyste 1637 hysteresis = <1000>;
2077 type 1638 type = "active";
2078 }; 1639 };
2079 1640
2080 mem-hot-trip <<
2081 tempe <<
2082 hyste <<
2083 type <<
2084 }; <<
2085 <<
2086 mem-shutdown- 1641 mem-shutdown-trip {
2087 tempe 1642 temperature = <103000>;
2088 hyste 1643 hysteresis = <0>;
2089 type 1644 type = "critical";
2090 }; 1645 };
2091 }; 1646 };
2092 1647
2093 cooling-maps { 1648 cooling-maps {
2094 dram-passive 1649 dram-passive {
2095 cooli 1650 cooling-device = <&emc 0 0>;
2096 trip 1651 trip = <&dram_nominal>;
2097 }; 1652 };
2098 1653
2099 dram-active { 1654 dram-active {
2100 cooli 1655 cooling-device = <&emc 1 1>;
2101 trip 1656 trip = <&dram_throttle>;
2102 }; 1657 };
2103 }; 1658 };
2104 }; 1659 };
2105 1660
2106 gpu-thermal { !! 1661 gpu {
2107 polling-delay-passive 1662 polling-delay-passive = <1000>;
2108 polling-delay = <0>; 1663 polling-delay = <0>;
2109 1664
2110 thermal-sensors = 1665 thermal-sensors =
2111 <&soctherm TE 1666 <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>;
2112 1667
2113 trips { 1668 trips {
2114 gpu-shutdown- 1669 gpu-shutdown-trip {
2115 tempe 1670 temperature = <103000>;
2116 hyste 1671 hysteresis = <0>;
2117 type 1672 type = "critical";
2118 }; 1673 };
2119 1674
2120 gpu_throttle_ 1675 gpu_throttle_trip: throttle-trip {
2121 tempe 1676 temperature = <100000>;
2122 hyste 1677 hysteresis = <1000>;
2123 type 1678 type = "hot";
2124 }; 1679 };
2125 }; 1680 };
2126 1681
2127 cooling-maps { 1682 cooling-maps {
2128 map0 { 1683 map0 {
2129 trip 1684 trip = <&gpu_throttle_trip>;
2130 cooli 1685 cooling-device = <&throttle_heavy 1 1>;
2131 }; 1686 };
2132 }; 1687 };
2133 }; 1688 };
2134 1689
2135 pllx-thermal { !! 1690 pllx {
2136 polling-delay-passive 1691 polling-delay-passive = <0>;
2137 polling-delay = <0>; 1692 polling-delay = <0>;
2138 1693
2139 thermal-sensors = 1694 thermal-sensors =
2140 <&soctherm TE 1695 <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>;
2141 1696
2142 trips { 1697 trips {
2143 pllx-shutdown 1698 pllx-shutdown-trip {
2144 tempe 1699 temperature = <103000>;
2145 hyste 1700 hysteresis = <0>;
2146 type 1701 type = "critical";
2147 }; 1702 };
2148 <<
2149 pllx-throttle <<
2150 tempe <<
2151 hyste <<
2152 type <<
2153 }; <<
2154 }; 1703 };
2155 1704
2156 cooling-maps { 1705 cooling-maps {
2157 /* 1706 /*
2158 * There are 1707 * There are currently no cooling maps,
2159 * because th 1708 * because there are no cooling devices.
2160 */ 1709 */
2161 }; 1710 };
2162 }; 1711 };
2163 }; <<
2164 <<
2165 timer { <<
2166 compatible = "arm,armv8-timer <<
2167 interrupts = <GIC_PPI 13 <<
2168 (GIC_CPU_MASK <<
2169 <GIC_PPI 14 <<
2170 (GIC_CPU_MASK <<
2171 <GIC_PPI 11 <<
2172 (GIC_CPU_MASK <<
2173 <GIC_PPI 10 <<
2174 (GIC_CPU_MASK <<
2175 interrupt-parent = <&gic>; <<
2176 arm,no-tick-in-suspend; <<
2177 }; 1712 };
2178 }; 1713 };
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