1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0 2 #include <dt-bindings/clock/tegra210-car.h> 2 #include <dt-bindings/clock/tegra210-car.h> 3 #include <dt-bindings/gpio/tegra-gpio.h> 3 #include <dt-bindings/gpio/tegra-gpio.h> 4 #include <dt-bindings/memory/tegra210-mc.h> 4 #include <dt-bindings/memory/tegra210-mc.h> 5 #include <dt-bindings/pinctrl/pinctrl-tegra.h> 5 #include <dt-bindings/pinctrl/pinctrl-tegra.h> 6 #include <dt-bindings/pinctrl/pinctrl-tegra-io 6 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 7 #include <dt-bindings/reset/tegra210-car.h> 7 #include <dt-bindings/reset/tegra210-car.h> 8 #include <dt-bindings/interrupt-controller/arm 8 #include <dt-bindings/interrupt-controller/arm-gic.h> 9 #include <dt-bindings/thermal/tegra124-socther 9 #include <dt-bindings/thermal/tegra124-soctherm.h> 10 #include <dt-bindings/soc/tegra-pmc.h> 10 #include <dt-bindings/soc/tegra-pmc.h> 11 11 12 / { 12 / { 13 compatible = "nvidia,tegra210"; 13 compatible = "nvidia,tegra210"; 14 interrupt-parent = <&lic>; 14 interrupt-parent = <&lic>; 15 #address-cells = <2>; 15 #address-cells = <2>; 16 #size-cells = <2>; 16 #size-cells = <2>; 17 17 18 pcie@1003000 { 18 pcie@1003000 { 19 compatible = "nvidia,tegra210- 19 compatible = "nvidia,tegra210-pcie"; 20 device_type = "pci"; 20 device_type = "pci"; 21 reg = <0x0 0x01003000 0x0 0x00 21 reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */ 22 <0x0 0x01003800 0x0 0x00 22 <0x0 0x01003800 0x0 0x00000800>, /* AFI registers */ 23 <0x0 0x02000000 0x0 0x10 23 <0x0 0x02000000 0x0 0x10000000>; /* configuration space */ 24 reg-names = "pads", "afi", "cs 24 reg-names = "pads", "afi", "cs"; 25 interrupts = <GIC_SPI 98 IRQ_T 25 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 26 <GIC_SPI 99 IRQ_T 26 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 27 interrupt-names = "intr", "msi 27 interrupt-names = "intr", "msi"; 28 28 29 #interrupt-cells = <1>; 29 #interrupt-cells = <1>; 30 interrupt-map-mask = <0 0 0 0> 30 interrupt-map-mask = <0 0 0 0>; 31 interrupt-map = <0 0 0 0 &gic 31 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 32 32 33 bus-range = <0x00 0xff>; 33 bus-range = <0x00 0xff>; 34 #address-cells = <3>; 34 #address-cells = <3>; 35 #size-cells = <2>; 35 #size-cells = <2>; 36 36 37 ranges = <0x02000000 0 0x01000 37 ranges = <0x02000000 0 0x01000000 0x0 0x01000000 0 0x00001000>, /* port 0 configuration space */ 38 <0x02000000 0 0x01001 38 <0x02000000 0 0x01001000 0x0 0x01001000 0 0x00001000>, /* port 1 configuration space */ 39 <0x01000000 0 0x0 39 <0x01000000 0 0x0 0x0 0x12000000 0 0x00010000>, /* downstream I/O (64 KiB) */ 40 <0x02000000 0 0x13000 40 <0x02000000 0 0x13000000 0x0 0x13000000 0 0x0d000000>, /* non-prefetchable memory (208 MiB) */ 41 <0x42000000 0 0x20000 41 <0x42000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */ 42 42 43 clocks = <&tegra_car TEGRA210_ 43 clocks = <&tegra_car TEGRA210_CLK_PCIE>, 44 <&tegra_car TEGRA210_ 44 <&tegra_car TEGRA210_CLK_AFI>, 45 <&tegra_car TEGRA210_ 45 <&tegra_car TEGRA210_CLK_PLL_E>, 46 <&tegra_car TEGRA210_ 46 <&tegra_car TEGRA210_CLK_CML0>; 47 clock-names = "pex", "afi", "p 47 clock-names = "pex", "afi", "pll_e", "cml"; 48 resets = <&tegra_car 70>, 48 resets = <&tegra_car 70>, 49 <&tegra_car 72>, 49 <&tegra_car 72>, 50 <&tegra_car 74>; 50 <&tegra_car 74>; 51 reset-names = "pex", "afi", "p 51 reset-names = "pex", "afi", "pcie_x"; 52 52 53 pinctrl-names = "default", "id 53 pinctrl-names = "default", "idle"; 54 pinctrl-0 = <&pex_dpd_disable> 54 pinctrl-0 = <&pex_dpd_disable>; 55 pinctrl-1 = <&pex_dpd_enable>; 55 pinctrl-1 = <&pex_dpd_enable>; 56 56 57 status = "disabled"; 57 status = "disabled"; 58 58 59 pci@1,0 { 59 pci@1,0 { 60 device_type = "pci"; 60 device_type = "pci"; 61 assigned-addresses = < 61 assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>; 62 reg = <0x000800 0 0 0 62 reg = <0x000800 0 0 0 0>; 63 bus-range = <0x00 0xff 63 bus-range = <0x00 0xff>; 64 status = "disabled"; 64 status = "disabled"; 65 65 66 #address-cells = <3>; 66 #address-cells = <3>; 67 #size-cells = <2>; 67 #size-cells = <2>; 68 ranges; 68 ranges; 69 69 70 nvidia,num-lanes = <4> 70 nvidia,num-lanes = <4>; 71 }; 71 }; 72 72 73 pci@2,0 { 73 pci@2,0 { 74 device_type = "pci"; 74 device_type = "pci"; 75 assigned-addresses = < 75 assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>; 76 reg = <0x001000 0 0 0 76 reg = <0x001000 0 0 0 0>; 77 bus-range = <0x00 0xff 77 bus-range = <0x00 0xff>; 78 status = "disabled"; 78 status = "disabled"; 79 79 80 #address-cells = <3>; 80 #address-cells = <3>; 81 #size-cells = <2>; 81 #size-cells = <2>; 82 ranges; 82 ranges; 83 83 84 nvidia,num-lanes = <1> 84 nvidia,num-lanes = <1>; 85 }; 85 }; 86 }; 86 }; 87 87 88 host1x@50000000 { 88 host1x@50000000 { 89 compatible = "nvidia,tegra210- 89 compatible = "nvidia,tegra210-host1x"; 90 reg = <0x0 0x50000000 0x0 0x00 90 reg = <0x0 0x50000000 0x0 0x00034000>; 91 interrupts = <GIC_SPI 65 IRQ_T 91 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ 92 <GIC_SPI 67 IRQ_T 92 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ 93 interrupt-names = "syncpt", "h 93 interrupt-names = "syncpt", "host1x"; 94 clocks = <&tegra_car TEGRA210_ 94 clocks = <&tegra_car TEGRA210_CLK_HOST1X>; 95 clock-names = "host1x"; 95 clock-names = "host1x"; 96 resets = <&tegra_car 28>, <&mc 96 resets = <&tegra_car 28>, <&mc TEGRA210_MC_RESET_HC>; 97 reset-names = "host1x", "mc"; 97 reset-names = "host1x", "mc"; 98 98 99 #address-cells = <2>; 99 #address-cells = <2>; 100 #size-cells = <2>; 100 #size-cells = <2>; 101 101 102 ranges = <0x0 0x54000000 0x0 0 102 ranges = <0x0 0x54000000 0x0 0x54000000 0x0 0x01000000>; 103 103 104 iommus = <&mc TEGRA_SWGROUP_HC 104 iommus = <&mc TEGRA_SWGROUP_HC>; 105 105 106 dpaux1: dpaux@54040000 { 106 dpaux1: dpaux@54040000 { 107 compatible = "nvidia,t 107 compatible = "nvidia,tegra210-dpaux"; 108 reg = <0x0 0x54040000 108 reg = <0x0 0x54040000 0x0 0x00040000>; 109 interrupts = <GIC_SPI 109 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 110 clocks = <&tegra_car T 110 clocks = <&tegra_car TEGRA210_CLK_DPAUX1>, 111 <&tegra_car T 111 <&tegra_car TEGRA210_CLK_PLL_DP>; 112 clock-names = "dpaux", 112 clock-names = "dpaux", "parent"; 113 resets = <&tegra_car 2 113 resets = <&tegra_car 207>; 114 reset-names = "dpaux"; 114 reset-names = "dpaux"; 115 power-domains = <&pd_s 115 power-domains = <&pd_sor>; 116 status = "disabled"; 116 status = "disabled"; 117 117 118 state_dpaux1_aux: pinm 118 state_dpaux1_aux: pinmux-aux { 119 groups = "dpau 119 groups = "dpaux-io"; 120 function = "au 120 function = "aux"; 121 }; 121 }; 122 122 123 state_dpaux1_i2c: pinm 123 state_dpaux1_i2c: pinmux-i2c { 124 groups = "dpau 124 groups = "dpaux-io"; 125 function = "i2 125 function = "i2c"; 126 }; 126 }; 127 127 128 state_dpaux1_off: pinm 128 state_dpaux1_off: pinmux-off { 129 groups = "dpau 129 groups = "dpaux-io"; 130 function = "of 130 function = "off"; 131 }; 131 }; 132 132 133 i2c-bus { 133 i2c-bus { 134 #address-cells 134 #address-cells = <1>; 135 #size-cells = 135 #size-cells = <0>; 136 }; 136 }; 137 }; 137 }; 138 138 139 vi@54080000 { 139 vi@54080000 { 140 compatible = "nvidia,t 140 compatible = "nvidia,tegra210-vi"; 141 reg = <0x0 0x54080000 141 reg = <0x0 0x54080000 0x0 0x700>; 142 interrupts = <GIC_SPI 142 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 143 status = "disabled"; 143 status = "disabled"; 144 assigned-clocks = <&te 144 assigned-clocks = <&tegra_car TEGRA210_CLK_VI>; 145 assigned-clock-parents 145 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; 146 146 147 clocks = <&tegra_car T 147 clocks = <&tegra_car TEGRA210_CLK_VI>; 148 power-domains = <&pd_v 148 power-domains = <&pd_venc>; 149 149 150 #address-cells = <1>; 150 #address-cells = <1>; 151 #size-cells = <1>; 151 #size-cells = <1>; 152 152 153 ranges = <0x0 0x0 0x54 153 ranges = <0x0 0x0 0x54080000 0x2000>; 154 154 155 csi@838 { 155 csi@838 { 156 compatible = " 156 compatible = "nvidia,tegra210-csi"; 157 reg = <0x838 0 157 reg = <0x838 0x1300>; 158 status = "disa 158 status = "disabled"; 159 assigned-clock 159 assigned-clocks = <&tegra_car TEGRA210_CLK_CILAB>, 160 160 <&tegra_car TEGRA210_CLK_CILCD>, 161 161 <&tegra_car TEGRA210_CLK_CILE>, 162 162 <&tegra_car TEGRA210_CLK_CSI_TPG>; 163 assigned-clock 163 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>, 164 164 <&tegra_car TEGRA210_CLK_PLL_P>, 165 165 <&tegra_car TEGRA210_CLK_PLL_P>; 166 assigned-clock 166 assigned-clock-rates = <102000000>, 167 167 <102000000>, 168 168 <102000000>, 169 169 <972000000>; 170 170 171 clocks = <&teg 171 clocks = <&tegra_car TEGRA210_CLK_CSI>, 172 <&teg 172 <&tegra_car TEGRA210_CLK_CILAB>, 173 <&teg 173 <&tegra_car TEGRA210_CLK_CILCD>, 174 <&teg 174 <&tegra_car TEGRA210_CLK_CILE>, 175 <&teg 175 <&tegra_car TEGRA210_CLK_CSI_TPG>; 176 clock-names = 176 clock-names = "csi", "cilab", "cilcd", "cile", "csi_tpg"; 177 power-domains 177 power-domains = <&pd_sor>; 178 }; 178 }; 179 }; 179 }; 180 180 181 tsec@54100000 { 181 tsec@54100000 { 182 compatible = "nvidia,t 182 compatible = "nvidia,tegra210-tsec"; 183 reg = <0x0 0x54100000 183 reg = <0x0 0x54100000 0x0 0x00040000>; 184 interrupts = <GIC_SPI 184 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 185 clocks = <&tegra_car T 185 clocks = <&tegra_car TEGRA210_CLK_TSEC>; 186 clock-names = "tsec"; 186 clock-names = "tsec"; 187 resets = <&tegra_car 8 187 resets = <&tegra_car 83>; 188 reset-names = "tsec"; 188 reset-names = "tsec"; 189 status = "disabled"; 189 status = "disabled"; 190 }; 190 }; 191 191 192 dc@54200000 { 192 dc@54200000 { 193 compatible = "nvidia,t 193 compatible = "nvidia,tegra210-dc"; 194 reg = <0x0 0x54200000 194 reg = <0x0 0x54200000 0x0 0x00040000>; 195 interrupts = <GIC_SPI 195 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 196 clocks = <&tegra_car T 196 clocks = <&tegra_car TEGRA210_CLK_DISP1>; 197 clock-names = "dc"; 197 clock-names = "dc"; 198 resets = <&tegra_car 2 198 resets = <&tegra_car 27>; 199 reset-names = "dc"; 199 reset-names = "dc"; 200 200 201 iommus = <&mc TEGRA_SW 201 iommus = <&mc TEGRA_SWGROUP_DC>; 202 202 203 nvidia,outputs = <&dsi 203 nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 204 nvidia,head = <0>; 204 nvidia,head = <0>; 205 }; 205 }; 206 206 207 dc@54240000 { 207 dc@54240000 { 208 compatible = "nvidia,t 208 compatible = "nvidia,tegra210-dc"; 209 reg = <0x0 0x54240000 209 reg = <0x0 0x54240000 0x0 0x00040000>; 210 interrupts = <GIC_SPI 210 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 211 clocks = <&tegra_car T 211 clocks = <&tegra_car TEGRA210_CLK_DISP2>; 212 clock-names = "dc"; 212 clock-names = "dc"; 213 resets = <&tegra_car 2 213 resets = <&tegra_car 26>; 214 reset-names = "dc"; 214 reset-names = "dc"; 215 215 216 iommus = <&mc TEGRA_SW 216 iommus = <&mc TEGRA_SWGROUP_DCB>; 217 217 218 nvidia,outputs = <&dsi 218 nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 219 nvidia,head = <1>; 219 nvidia,head = <1>; 220 }; 220 }; 221 221 222 dsia: dsi@54300000 { 222 dsia: dsi@54300000 { 223 compatible = "nvidia,t 223 compatible = "nvidia,tegra210-dsi"; 224 reg = <0x0 0x54300000 224 reg = <0x0 0x54300000 0x0 0x00040000>; 225 clocks = <&tegra_car T 225 clocks = <&tegra_car TEGRA210_CLK_DSIA>, 226 <&tegra_car T 226 <&tegra_car TEGRA210_CLK_DSIALP>, 227 <&tegra_car T 227 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>; 228 clock-names = "dsi", " 228 clock-names = "dsi", "lp", "parent"; 229 resets = <&tegra_car 4 229 resets = <&tegra_car 48>; 230 reset-names = "dsi"; 230 reset-names = "dsi"; 231 power-domains = <&pd_s 231 power-domains = <&pd_sor>; 232 nvidia,mipi-calibrate 232 nvidia,mipi-calibrate = <&mipi 0x0c0>; /* DSIA & DSIB pads */ 233 233 234 status = "disabled"; 234 status = "disabled"; 235 235 236 #address-cells = <1>; 236 #address-cells = <1>; 237 #size-cells = <0>; 237 #size-cells = <0>; 238 }; 238 }; 239 239 240 vic@54340000 { 240 vic@54340000 { 241 compatible = "nvidia,t 241 compatible = "nvidia,tegra210-vic"; 242 reg = <0x0 0x54340000 242 reg = <0x0 0x54340000 0x0 0x00040000>; 243 interrupts = <GIC_SPI 243 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 244 clocks = <&tegra_car T 244 clocks = <&tegra_car TEGRA210_CLK_VIC03>; 245 clock-names = "vic"; 245 clock-names = "vic"; 246 resets = <&tegra_car 1 246 resets = <&tegra_car 178>; 247 reset-names = "vic"; 247 reset-names = "vic"; 248 248 249 iommus = <&mc TEGRA_SW 249 iommus = <&mc TEGRA_SWGROUP_VIC>; 250 power-domains = <&pd_v 250 power-domains = <&pd_vic>; 251 }; 251 }; 252 252 253 nvjpg@54380000 { 253 nvjpg@54380000 { 254 compatible = "nvidia,t 254 compatible = "nvidia,tegra210-nvjpg"; 255 reg = <0x0 0x54380000 255 reg = <0x0 0x54380000 0x0 0x00040000>; 256 status = "disabled"; 256 status = "disabled"; 257 }; 257 }; 258 258 259 dsib: dsi@54400000 { 259 dsib: dsi@54400000 { 260 compatible = "nvidia,t 260 compatible = "nvidia,tegra210-dsi"; 261 reg = <0x0 0x54400000 261 reg = <0x0 0x54400000 0x0 0x00040000>; 262 clocks = <&tegra_car T 262 clocks = <&tegra_car TEGRA210_CLK_DSIB>, 263 <&tegra_car T 263 <&tegra_car TEGRA210_CLK_DSIBLP>, 264 <&tegra_car T 264 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>; 265 clock-names = "dsi", " 265 clock-names = "dsi", "lp", "parent"; 266 resets = <&tegra_car 8 266 resets = <&tegra_car 82>; 267 reset-names = "dsi"; 267 reset-names = "dsi"; 268 power-domains = <&pd_s 268 power-domains = <&pd_sor>; 269 nvidia,mipi-calibrate 269 nvidia,mipi-calibrate = <&mipi 0x300>; /* DSIC & DSID pads */ 270 270 271 status = "disabled"; 271 status = "disabled"; 272 272 273 #address-cells = <1>; 273 #address-cells = <1>; 274 #size-cells = <0>; 274 #size-cells = <0>; 275 }; 275 }; 276 276 277 nvdec@54480000 { 277 nvdec@54480000 { 278 compatible = "nvidia,t 278 compatible = "nvidia,tegra210-nvdec"; 279 reg = <0x0 0x54480000 279 reg = <0x0 0x54480000 0x0 0x00040000>; 280 status = "disabled"; 280 status = "disabled"; 281 }; 281 }; 282 282 283 nvenc@544c0000 { 283 nvenc@544c0000 { 284 compatible = "nvidia,t 284 compatible = "nvidia,tegra210-nvenc"; 285 reg = <0x0 0x544c0000 285 reg = <0x0 0x544c0000 0x0 0x00040000>; 286 status = "disabled"; 286 status = "disabled"; 287 }; 287 }; 288 288 289 tsec@54500000 { 289 tsec@54500000 { 290 compatible = "nvidia,t 290 compatible = "nvidia,tegra210-tsec"; 291 reg = <0x0 0x54500000 291 reg = <0x0 0x54500000 0x0 0x00040000>; 292 interrupts = <GIC_SPI 292 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 293 clocks = <&tegra_car T 293 clocks = <&tegra_car TEGRA210_CLK_TSECB>; 294 clock-names = "tsec"; 294 clock-names = "tsec"; 295 resets = <&tegra_car 2 295 resets = <&tegra_car 206>; 296 reset-names = "tsec"; 296 reset-names = "tsec"; 297 status = "disabled"; 297 status = "disabled"; 298 }; 298 }; 299 299 300 sor0: sor@54540000 { 300 sor0: sor@54540000 { 301 compatible = "nvidia,t 301 compatible = "nvidia,tegra210-sor"; 302 reg = <0x0 0x54540000 302 reg = <0x0 0x54540000 0x0 0x00040000>; 303 interrupts = <GIC_SPI 303 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 304 clocks = <&tegra_car T 304 clocks = <&tegra_car TEGRA210_CLK_SOR0>, 305 <&tegra_car T 305 <&tegra_car TEGRA210_CLK_SOR0_OUT>, 306 <&tegra_car T 306 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>, 307 <&tegra_car T 307 <&tegra_car TEGRA210_CLK_PLL_DP>, 308 <&tegra_car T 308 <&tegra_car TEGRA210_CLK_SOR_SAFE>; 309 clock-names = "sor", " 309 clock-names = "sor", "out", "parent", "dp", "safe"; 310 resets = <&tegra_car 1 310 resets = <&tegra_car 182>; 311 reset-names = "sor"; 311 reset-names = "sor"; 312 pinctrl-0 = <&state_dp 312 pinctrl-0 = <&state_dpaux_aux>; 313 pinctrl-1 = <&state_dp 313 pinctrl-1 = <&state_dpaux_i2c>; 314 pinctrl-2 = <&state_dp 314 pinctrl-2 = <&state_dpaux_off>; 315 pinctrl-names = "aux", 315 pinctrl-names = "aux", "i2c", "off"; 316 power-domains = <&pd_s 316 power-domains = <&pd_sor>; 317 status = "disabled"; 317 status = "disabled"; 318 }; 318 }; 319 319 320 sor1: sor@54580000 { 320 sor1: sor@54580000 { 321 compatible = "nvidia,t 321 compatible = "nvidia,tegra210-sor1"; 322 reg = <0x0 0x54580000 322 reg = <0x0 0x54580000 0x0 0x00040000>; 323 interrupts = <GIC_SPI 323 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 324 clocks = <&tegra_car T 324 clocks = <&tegra_car TEGRA210_CLK_SOR1>, 325 <&tegra_car T 325 <&tegra_car TEGRA210_CLK_SOR1_OUT>, 326 <&tegra_car T 326 <&tegra_car TEGRA210_CLK_PLL_D2_OUT0>, 327 <&tegra_car T 327 <&tegra_car TEGRA210_CLK_PLL_DP>, 328 <&tegra_car T 328 <&tegra_car TEGRA210_CLK_SOR_SAFE>; 329 clock-names = "sor", " 329 clock-names = "sor", "out", "parent", "dp", "safe"; 330 resets = <&tegra_car 1 330 resets = <&tegra_car 183>; 331 reset-names = "sor"; 331 reset-names = "sor"; 332 pinctrl-0 = <&state_dp 332 pinctrl-0 = <&state_dpaux1_aux>; 333 pinctrl-1 = <&state_dp 333 pinctrl-1 = <&state_dpaux1_i2c>; 334 pinctrl-2 = <&state_dp 334 pinctrl-2 = <&state_dpaux1_off>; 335 pinctrl-names = "aux", 335 pinctrl-names = "aux", "i2c", "off"; 336 power-domains = <&pd_s 336 power-domains = <&pd_sor>; 337 status = "disabled"; 337 status = "disabled"; 338 }; 338 }; 339 339 340 dpaux: dpaux@545c0000 { 340 dpaux: dpaux@545c0000 { 341 compatible = "nvidia,t 341 compatible = "nvidia,tegra210-dpaux"; 342 reg = <0x0 0x545c0000 342 reg = <0x0 0x545c0000 0x0 0x00040000>; 343 interrupts = <GIC_SPI 343 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 344 clocks = <&tegra_car T 344 clocks = <&tegra_car TEGRA210_CLK_DPAUX>, 345 <&tegra_car T 345 <&tegra_car TEGRA210_CLK_PLL_DP>; 346 clock-names = "dpaux", 346 clock-names = "dpaux", "parent"; 347 resets = <&tegra_car 1 347 resets = <&tegra_car 181>; 348 reset-names = "dpaux"; 348 reset-names = "dpaux"; 349 power-domains = <&pd_s 349 power-domains = <&pd_sor>; 350 status = "disabled"; 350 status = "disabled"; 351 351 352 state_dpaux_aux: pinmu 352 state_dpaux_aux: pinmux-aux { 353 groups = "dpau 353 groups = "dpaux-io"; 354 function = "au 354 function = "aux"; 355 }; 355 }; 356 356 357 state_dpaux_i2c: pinmu 357 state_dpaux_i2c: pinmux-i2c { 358 groups = "dpau 358 groups = "dpaux-io"; 359 function = "i2 359 function = "i2c"; 360 }; 360 }; 361 361 362 state_dpaux_off: pinmu 362 state_dpaux_off: pinmux-off { 363 groups = "dpau 363 groups = "dpaux-io"; 364 function = "of 364 function = "off"; 365 }; 365 }; 366 366 367 i2c-bus { 367 i2c-bus { 368 #address-cells 368 #address-cells = <1>; 369 #size-cells = 369 #size-cells = <0>; 370 }; 370 }; 371 }; 371 }; 372 372 373 isp@54600000 { 373 isp@54600000 { 374 compatible = "nvidia,t 374 compatible = "nvidia,tegra210-isp"; 375 reg = <0x0 0x54600000 375 reg = <0x0 0x54600000 0x0 0x00040000>; 376 interrupts = <GIC_SPI 376 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 377 clocks = <&tegra_car T 377 clocks = <&tegra_car TEGRA210_CLK_ISPA>; 378 resets = <&tegra_car 2 378 resets = <&tegra_car 23>; 379 reset-names = "isp"; 379 reset-names = "isp"; 380 status = "disabled"; 380 status = "disabled"; 381 }; 381 }; 382 382 383 isp@54680000 { 383 isp@54680000 { 384 compatible = "nvidia,t 384 compatible = "nvidia,tegra210-isp"; 385 reg = <0x0 0x54680000 385 reg = <0x0 0x54680000 0x0 0x00040000>; 386 interrupts = <GIC_SPI 386 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 387 clocks = <&tegra_car T 387 clocks = <&tegra_car TEGRA210_CLK_ISPB>; 388 resets = <&tegra_car 3 388 resets = <&tegra_car 3>; 389 reset-names = "isp"; 389 reset-names = "isp"; 390 status = "disabled"; 390 status = "disabled"; 391 }; 391 }; 392 392 393 i2c@546c0000 { 393 i2c@546c0000 { 394 compatible = "nvidia,t 394 compatible = "nvidia,tegra210-i2c-vi"; 395 reg = <0x0 0x546c0000 395 reg = <0x0 0x546c0000 0x0 0x00040000>; 396 interrupts = <GIC_SPI 396 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 397 clocks = <&tegra_car T 397 clocks = <&tegra_car TEGRA210_CLK_VI_I2C>, 398 <&tegra_car T 398 <&tegra_car TEGRA210_CLK_I2CSLOW>; 399 clock-names = "div-clk 399 clock-names = "div-clk", "slow"; 400 resets = <&tegra_car 2 400 resets = <&tegra_car 208>; 401 reset-names = "i2c"; 401 reset-names = "i2c"; 402 power-domains = <&pd_v 402 power-domains = <&pd_venc>; 403 status = "disabled"; 403 status = "disabled"; 404 404 405 #address-cells = <1>; 405 #address-cells = <1>; 406 #size-cells = <0>; 406 #size-cells = <0>; 407 }; 407 }; 408 }; 408 }; 409 409 410 gic: interrupt-controller@50041000 { 410 gic: interrupt-controller@50041000 { 411 compatible = "arm,gic-400"; 411 compatible = "arm,gic-400"; 412 #interrupt-cells = <3>; 412 #interrupt-cells = <3>; 413 interrupt-controller; 413 interrupt-controller; 414 reg = <0x0 0x50041000 0x0 0x10 414 reg = <0x0 0x50041000 0x0 0x1000>, 415 <0x0 0x50042000 0x0 0x20 415 <0x0 0x50042000 0x0 0x2000>, 416 <0x0 0x50044000 0x0 0x20 416 <0x0 0x50044000 0x0 0x2000>, 417 <0x0 0x50046000 0x0 0x20 417 <0x0 0x50046000 0x0 0x2000>; 418 interrupts = <GIC_PPI 9 418 interrupts = <GIC_PPI 9 419 (GIC_CPU_MASK_SIMPLE(4 419 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 420 interrupt-parent = <&gic>; 420 interrupt-parent = <&gic>; 421 }; 421 }; 422 422 423 gpu@57000000 { 423 gpu@57000000 { 424 compatible = "nvidia,gm20b"; 424 compatible = "nvidia,gm20b"; 425 reg = <0x0 0x57000000 0x0 0x01 425 reg = <0x0 0x57000000 0x0 0x01000000>, 426 <0x0 0x58000000 0x0 0x01 426 <0x0 0x58000000 0x0 0x01000000>; 427 interrupts = <GIC_SPI 157 IRQ_ 427 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 428 <GIC_SPI 158 IRQ_ 428 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 429 interrupt-names = "stall", "no 429 interrupt-names = "stall", "nonstall"; 430 clocks = <&tegra_car TEGRA210_ 430 clocks = <&tegra_car TEGRA210_CLK_GPU>, 431 <&tegra_car TEGRA210_ 431 <&tegra_car TEGRA210_CLK_PLL_P_OUT5>, 432 <&tegra_car TEGRA210_ 432 <&tegra_car TEGRA210_CLK_PLL_G_REF>; 433 clock-names = "gpu", "pwr", "r 433 clock-names = "gpu", "pwr", "ref"; 434 resets = <&tegra_car 184>; 434 resets = <&tegra_car 184>; 435 reset-names = "gpu"; 435 reset-names = "gpu"; 436 436 437 iommus = <&mc TEGRA_SWGROUP_GP 437 iommus = <&mc TEGRA_SWGROUP_GPU>; 438 438 439 status = "disabled"; 439 status = "disabled"; 440 }; 440 }; 441 441 442 lic: interrupt-controller@60004000 { 442 lic: interrupt-controller@60004000 { 443 compatible = "nvidia,tegra210- 443 compatible = "nvidia,tegra210-ictlr"; 444 reg = <0x0 0x60004000 0x0 0x40 444 reg = <0x0 0x60004000 0x0 0x40>, /* primary controller */ 445 <0x0 0x60004100 0x0 0x40 445 <0x0 0x60004100 0x0 0x40>, /* secondary controller */ 446 <0x0 0x60004200 0x0 0x40 446 <0x0 0x60004200 0x0 0x40>, /* tertiary controller */ 447 <0x0 0x60004300 0x0 0x40 447 <0x0 0x60004300 0x0 0x40>, /* quaternary controller */ 448 <0x0 0x60004400 0x0 0x40 448 <0x0 0x60004400 0x0 0x40>, /* quinary controller */ 449 <0x0 0x60004500 0x0 0x40 449 <0x0 0x60004500 0x0 0x40>; /* senary controller */ 450 interrupt-controller; 450 interrupt-controller; 451 #interrupt-cells = <3>; 451 #interrupt-cells = <3>; 452 interrupt-parent = <&gic>; 452 interrupt-parent = <&gic>; 453 }; 453 }; 454 454 455 timer@60005000 { 455 timer@60005000 { 456 compatible = "nvidia,tegra210- 456 compatible = "nvidia,tegra210-timer"; 457 reg = <0x0 0x60005000 0x0 0x40 457 reg = <0x0 0x60005000 0x0 0x400>; 458 interrupts = <GIC_SPI 156 IRQ_ 458 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 459 <GIC_SPI 0 IRQ_TY 459 <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 460 <GIC_SPI 1 IRQ_TY 460 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 461 <GIC_SPI 41 IRQ_T 461 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 462 <GIC_SPI 42 IRQ_T 462 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 463 <GIC_SPI 121 IRQ_ 463 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 464 <GIC_SPI 152 IRQ_ 464 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 465 <GIC_SPI 153 IRQ_ 465 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 466 <GIC_SPI 154 IRQ_ 466 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 467 <GIC_SPI 155 IRQ_ 467 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 468 <GIC_SPI 176 IRQ_ 468 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 469 <GIC_SPI 177 IRQ_ 469 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 470 <GIC_SPI 178 IRQ_ 470 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, 471 <GIC_SPI 179 IRQ_ 471 <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 472 clocks = <&tegra_car TEGRA210_ 472 clocks = <&tegra_car TEGRA210_CLK_TIMER>; 473 clock-names = "timer"; 473 clock-names = "timer"; 474 }; 474 }; 475 475 476 tegra_car: clock@60006000 { 476 tegra_car: clock@60006000 { 477 compatible = "nvidia,tegra210- 477 compatible = "nvidia,tegra210-car"; 478 reg = <0x0 0x60006000 0x0 0x10 478 reg = <0x0 0x60006000 0x0 0x1000>; 479 #clock-cells = <1>; 479 #clock-cells = <1>; 480 #reset-cells = <1>; 480 #reset-cells = <1>; 481 }; 481 }; 482 482 483 flow-controller@60007000 { 483 flow-controller@60007000 { 484 compatible = "nvidia,tegra210- 484 compatible = "nvidia,tegra210-flowctrl"; 485 reg = <0x0 0x60007000 0x0 0x10 485 reg = <0x0 0x60007000 0x0 0x1000>; 486 }; 486 }; 487 487 488 gpio: gpio@6000d000 { 488 gpio: gpio@6000d000 { 489 compatible = "nvidia,tegra210- 489 compatible = "nvidia,tegra210-gpio", "nvidia,tegra30-gpio"; 490 reg = <0x0 0x6000d000 0x0 0x10 490 reg = <0x0 0x6000d000 0x0 0x1000>; 491 interrupts = <GIC_SPI 32 IRQ_T 491 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 492 <GIC_SPI 33 IRQ_T 492 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 493 <GIC_SPI 34 IRQ_T 493 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 494 <GIC_SPI 35 IRQ_T 494 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 495 <GIC_SPI 55 IRQ_T 495 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 496 <GIC_SPI 87 IRQ_T 496 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 497 <GIC_SPI 89 IRQ_T 497 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 498 <GIC_SPI 125 IRQ_ 498 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 499 #gpio-cells = <2>; 499 #gpio-cells = <2>; 500 gpio-controller; 500 gpio-controller; 501 #interrupt-cells = <2>; 501 #interrupt-cells = <2>; 502 interrupt-controller; 502 interrupt-controller; 503 }; 503 }; 504 504 505 apbdma: dma@60020000 { 505 apbdma: dma@60020000 { 506 compatible = "nvidia,tegra210- 506 compatible = "nvidia,tegra210-apbdma", "nvidia,tegra148-apbdma"; 507 reg = <0x0 0x60020000 0x0 0x14 507 reg = <0x0 0x60020000 0x0 0x1400>; 508 interrupts = <GIC_SPI 104 IRQ_ 508 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 509 <GIC_SPI 105 IRQ_ 509 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 510 <GIC_SPI 106 IRQ_ 510 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 511 <GIC_SPI 107 IRQ_ 511 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 512 <GIC_SPI 108 IRQ_ 512 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 513 <GIC_SPI 109 IRQ_ 513 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 514 <GIC_SPI 110 IRQ_ 514 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 515 <GIC_SPI 111 IRQ_ 515 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 516 <GIC_SPI 112 IRQ_ 516 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 517 <GIC_SPI 113 IRQ_ 517 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 518 <GIC_SPI 114 IRQ_ 518 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 519 <GIC_SPI 115 IRQ_ 519 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 520 <GIC_SPI 116 IRQ_ 520 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 521 <GIC_SPI 117 IRQ_ 521 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 522 <GIC_SPI 118 IRQ_ 522 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 523 <GIC_SPI 119 IRQ_ 523 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 524 <GIC_SPI 128 IRQ_ 524 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 525 <GIC_SPI 129 IRQ_ 525 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 526 <GIC_SPI 130 IRQ_ 526 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 527 <GIC_SPI 131 IRQ_ 527 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 528 <GIC_SPI 132 IRQ_ 528 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 529 <GIC_SPI 133 IRQ_ 529 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 530 <GIC_SPI 134 IRQ_ 530 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 531 <GIC_SPI 135 IRQ_ 531 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 532 <GIC_SPI 136 IRQ_ 532 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 533 <GIC_SPI 137 IRQ_ 533 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 534 <GIC_SPI 138 IRQ_ 534 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 535 <GIC_SPI 139 IRQ_ 535 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 536 <GIC_SPI 140 IRQ_ 536 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 537 <GIC_SPI 141 IRQ_ 537 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 538 <GIC_SPI 142 IRQ_ 538 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 539 <GIC_SPI 143 IRQ_ 539 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 540 clocks = <&tegra_car TEGRA210_ 540 clocks = <&tegra_car TEGRA210_CLK_APBDMA>; 541 clock-names = "dma"; 541 clock-names = "dma"; 542 resets = <&tegra_car 34>; 542 resets = <&tegra_car 34>; 543 reset-names = "dma"; 543 reset-names = "dma"; 544 #dma-cells = <1>; 544 #dma-cells = <1>; 545 }; 545 }; 546 546 547 apbmisc@70000800 { 547 apbmisc@70000800 { 548 compatible = "nvidia,tegra210- 548 compatible = "nvidia,tegra210-apbmisc", "nvidia,tegra20-apbmisc"; 549 reg = <0x0 0x70000800 0x0 0x64 549 reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */ 550 <0x0 0x70000008 0x0 0x04 550 <0x0 0x70000008 0x0 0x04>; /* Strapping options */ 551 }; 551 }; 552 552 553 pinmux: pinmux@700008d4 { 553 pinmux: pinmux@700008d4 { 554 compatible = "nvidia,tegra210- 554 compatible = "nvidia,tegra210-pinmux"; 555 reg = <0x0 0x700008d4 0x0 0x29 555 reg = <0x0 0x700008d4 0x0 0x29c>, /* Pad control registers */ 556 <0x0 0x70003000 0x0 0x29 556 <0x0 0x70003000 0x0 0x294>; /* Mux registers */ 557 557 558 sdmmc1_1v8_drv: pinmux-sdmmc1- 558 sdmmc1_1v8_drv: pinmux-sdmmc1-1v8-drv { 559 sdmmc1 { 559 sdmmc1 { 560 nvidia,pins = 560 nvidia,pins = "drive_sdmmc1"; 561 nvidia,pull-do 561 nvidia,pull-down-strength = <0x4>; 562 nvidia,pull-up 562 nvidia,pull-up-strength = <0x3>; 563 }; 563 }; 564 }; 564 }; 565 565 566 sdmmc1_3v3_drv: pinmux-sdmmc1- 566 sdmmc1_3v3_drv: pinmux-sdmmc1-3v3-drv { 567 sdmmc1 { 567 sdmmc1 { 568 nvidia,pins = 568 nvidia,pins = "drive_sdmmc1"; 569 nvidia,pull-do 569 nvidia,pull-down-strength = <0x8>; 570 nvidia,pull-up 570 nvidia,pull-up-strength = <0x8>; 571 }; 571 }; 572 }; 572 }; 573 573 574 sdmmc2_1v8_drv: pinmux-sdmmc2- 574 sdmmc2_1v8_drv: pinmux-sdmmc2-1v8-drv { 575 sdmmc2 { 575 sdmmc2 { 576 nvidia,pins = 576 nvidia,pins = "drive_sdmmc2"; 577 nvidia,pull-do 577 nvidia,pull-down-strength = <0x10>; 578 nvidia,pull-up 578 nvidia,pull-up-strength = <0x10>; 579 }; 579 }; 580 }; 580 }; 581 581 582 sdmmc3_1v8_drv: pinmux-sdmmc3- 582 sdmmc3_1v8_drv: pinmux-sdmmc3-1v8-drv { 583 sdmmc3 { 583 sdmmc3 { 584 nvidia,pins = 584 nvidia,pins = "drive_sdmmc3"; 585 nvidia,pull-do 585 nvidia,pull-down-strength = <0x4>; 586 nvidia,pull-up 586 nvidia,pull-up-strength = <0x3>; 587 }; 587 }; 588 }; 588 }; 589 589 590 sdmmc3_3v3_drv: pinmux-sdmmc3- 590 sdmmc3_3v3_drv: pinmux-sdmmc3-3v3-drv { 591 sdmmc3 { 591 sdmmc3 { 592 nvidia,pins = 592 nvidia,pins = "drive_sdmmc3"; 593 nvidia,pull-do 593 nvidia,pull-down-strength = <0x8>; 594 nvidia,pull-up 594 nvidia,pull-up-strength = <0x8>; 595 }; 595 }; 596 }; 596 }; 597 597 598 sdmmc4_1v8_drv: pinmux-sdmmc4- 598 sdmmc4_1v8_drv: pinmux-sdmmc4-1v8-drv { 599 sdmmc4 { 599 sdmmc4 { 600 nvidia,pins = 600 nvidia,pins = "drive_sdmmc4"; 601 nvidia,pull-do 601 nvidia,pull-down-strength = <0x10>; 602 nvidia,pull-up 602 nvidia,pull-up-strength = <0x10>; 603 }; 603 }; 604 }; 604 }; 605 }; 605 }; 606 606 607 /* 607 /* 608 * There are two serial driver i.e. 82 608 * There are two serial driver i.e. 8250 based simple serial 609 * driver and APB DMA based serial dri 609 * driver and APB DMA based serial driver for higher baudrate 610 * and performance. To enable the 8250 610 * and performance. To enable the 8250 based driver, the compatible 611 * is "nvidia,tegra124-uart", "nvidia, 611 * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable 612 * the APB DMA based serial driver, th 612 * the APB DMA based serial driver, the compatible is 613 * "nvidia,tegra124-hsuart", "nvidia,t 613 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart". 614 */ 614 */ 615 uarta: serial@70006000 { 615 uarta: serial@70006000 { 616 compatible = "nvidia,tegra210- 616 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 617 reg = <0x0 0x70006000 0x0 0x40 617 reg = <0x0 0x70006000 0x0 0x40>; 618 reg-shift = <2>; 618 reg-shift = <2>; 619 interrupts = <GIC_SPI 36 IRQ_T 619 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 620 clocks = <&tegra_car TEGRA210_ 620 clocks = <&tegra_car TEGRA210_CLK_UARTA>; 621 resets = <&tegra_car 6>; 621 resets = <&tegra_car 6>; 622 dmas = <&apbdma 8>, <&apbdma 8 622 dmas = <&apbdma 8>, <&apbdma 8>; 623 dma-names = "rx", "tx"; 623 dma-names = "rx", "tx"; 624 status = "disabled"; 624 status = "disabled"; 625 }; 625 }; 626 626 627 uartb: serial@70006040 { 627 uartb: serial@70006040 { 628 compatible = "nvidia,tegra210- 628 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 629 reg = <0x0 0x70006040 0x0 0x40 629 reg = <0x0 0x70006040 0x0 0x40>; 630 reg-shift = <2>; 630 reg-shift = <2>; 631 interrupts = <GIC_SPI 37 IRQ_T 631 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 632 clocks = <&tegra_car TEGRA210_ 632 clocks = <&tegra_car TEGRA210_CLK_UARTB>; 633 resets = <&tegra_car 7>; 633 resets = <&tegra_car 7>; 634 dmas = <&apbdma 9>, <&apbdma 9 634 dmas = <&apbdma 9>, <&apbdma 9>; 635 dma-names = "rx", "tx"; 635 dma-names = "rx", "tx"; 636 status = "disabled"; 636 status = "disabled"; 637 }; 637 }; 638 638 639 uartc: serial@70006200 { 639 uartc: serial@70006200 { 640 compatible = "nvidia,tegra210- 640 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 641 reg = <0x0 0x70006200 0x0 0x40 641 reg = <0x0 0x70006200 0x0 0x40>; 642 reg-shift = <2>; 642 reg-shift = <2>; 643 interrupts = <GIC_SPI 46 IRQ_T 643 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 644 clocks = <&tegra_car TEGRA210_ 644 clocks = <&tegra_car TEGRA210_CLK_UARTC>; 645 resets = <&tegra_car 55>; 645 resets = <&tegra_car 55>; 646 dmas = <&apbdma 10>, <&apbdma 646 dmas = <&apbdma 10>, <&apbdma 10>; 647 dma-names = "rx", "tx"; 647 dma-names = "rx", "tx"; 648 status = "disabled"; 648 status = "disabled"; 649 }; 649 }; 650 650 651 uartd: serial@70006300 { 651 uartd: serial@70006300 { 652 compatible = "nvidia,tegra210- 652 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 653 reg = <0x0 0x70006300 0x0 0x40 653 reg = <0x0 0x70006300 0x0 0x40>; 654 reg-shift = <2>; 654 reg-shift = <2>; 655 interrupts = <GIC_SPI 90 IRQ_T 655 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 656 clocks = <&tegra_car TEGRA210_ 656 clocks = <&tegra_car TEGRA210_CLK_UARTD>; 657 resets = <&tegra_car 65>; 657 resets = <&tegra_car 65>; 658 dmas = <&apbdma 19>, <&apbdma 658 dmas = <&apbdma 19>, <&apbdma 19>; 659 dma-names = "rx", "tx"; 659 dma-names = "rx", "tx"; 660 status = "disabled"; 660 status = "disabled"; 661 }; 661 }; 662 662 663 pwm: pwm@7000a000 { 663 pwm: pwm@7000a000 { 664 compatible = "nvidia,tegra210- 664 compatible = "nvidia,tegra210-pwm", "nvidia,tegra20-pwm"; 665 reg = <0x0 0x7000a000 0x0 0x10 665 reg = <0x0 0x7000a000 0x0 0x100>; 666 #pwm-cells = <2>; 666 #pwm-cells = <2>; 667 clocks = <&tegra_car TEGRA210_ 667 clocks = <&tegra_car TEGRA210_CLK_PWM>; 668 resets = <&tegra_car 17>; 668 resets = <&tegra_car 17>; 669 reset-names = "pwm"; 669 reset-names = "pwm"; 670 status = "disabled"; 670 status = "disabled"; 671 }; 671 }; 672 672 673 i2c@7000c000 { 673 i2c@7000c000 { 674 compatible = "nvidia,tegra210- 674 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 675 reg = <0x0 0x7000c000 0x0 0x10 675 reg = <0x0 0x7000c000 0x0 0x100>; 676 interrupts = <GIC_SPI 38 IRQ_T 676 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 677 #address-cells = <1>; 677 #address-cells = <1>; 678 #size-cells = <0>; 678 #size-cells = <0>; 679 clocks = <&tegra_car TEGRA210_ 679 clocks = <&tegra_car TEGRA210_CLK_I2C1>; 680 clock-names = "div-clk"; 680 clock-names = "div-clk"; 681 resets = <&tegra_car 12>; 681 resets = <&tegra_car 12>; 682 reset-names = "i2c"; 682 reset-names = "i2c"; 683 dmas = <&apbdma 21>, <&apbdma 683 dmas = <&apbdma 21>, <&apbdma 21>; 684 dma-names = "rx", "tx"; 684 dma-names = "rx", "tx"; 685 status = "disabled"; 685 status = "disabled"; 686 }; 686 }; 687 687 688 i2c@7000c400 { 688 i2c@7000c400 { 689 compatible = "nvidia,tegra210- 689 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 690 reg = <0x0 0x7000c400 0x0 0x10 690 reg = <0x0 0x7000c400 0x0 0x100>; 691 interrupts = <GIC_SPI 84 IRQ_T 691 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 692 #address-cells = <1>; 692 #address-cells = <1>; 693 #size-cells = <0>; 693 #size-cells = <0>; 694 clocks = <&tegra_car TEGRA210_ 694 clocks = <&tegra_car TEGRA210_CLK_I2C2>; 695 clock-names = "div-clk"; 695 clock-names = "div-clk"; 696 resets = <&tegra_car 54>; 696 resets = <&tegra_car 54>; 697 reset-names = "i2c"; 697 reset-names = "i2c"; 698 dmas = <&apbdma 22>, <&apbdma 698 dmas = <&apbdma 22>, <&apbdma 22>; 699 dma-names = "rx", "tx"; 699 dma-names = "rx", "tx"; 700 status = "disabled"; 700 status = "disabled"; 701 }; 701 }; 702 702 703 i2c@7000c500 { 703 i2c@7000c500 { 704 compatible = "nvidia,tegra210- 704 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 705 reg = <0x0 0x7000c500 0x0 0x10 705 reg = <0x0 0x7000c500 0x0 0x100>; 706 interrupts = <GIC_SPI 92 IRQ_T 706 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 707 #address-cells = <1>; 707 #address-cells = <1>; 708 #size-cells = <0>; 708 #size-cells = <0>; 709 clocks = <&tegra_car TEGRA210_ 709 clocks = <&tegra_car TEGRA210_CLK_I2C3>; 710 clock-names = "div-clk"; 710 clock-names = "div-clk"; 711 resets = <&tegra_car 67>; 711 resets = <&tegra_car 67>; 712 reset-names = "i2c"; 712 reset-names = "i2c"; 713 dmas = <&apbdma 23>, <&apbdma 713 dmas = <&apbdma 23>, <&apbdma 23>; 714 dma-names = "rx", "tx"; 714 dma-names = "rx", "tx"; 715 status = "disabled"; 715 status = "disabled"; 716 }; 716 }; 717 717 718 i2c@7000c700 { 718 i2c@7000c700 { 719 compatible = "nvidia,tegra210- 719 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 720 reg = <0x0 0x7000c700 0x0 0x10 720 reg = <0x0 0x7000c700 0x0 0x100>; 721 interrupts = <GIC_SPI 120 IRQ_ 721 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 722 #address-cells = <1>; 722 #address-cells = <1>; 723 #size-cells = <0>; 723 #size-cells = <0>; 724 clocks = <&tegra_car TEGRA210_ 724 clocks = <&tegra_car TEGRA210_CLK_I2C4>; 725 clock-names = "div-clk"; 725 clock-names = "div-clk"; 726 resets = <&tegra_car 103>; 726 resets = <&tegra_car 103>; 727 reset-names = "i2c"; 727 reset-names = "i2c"; 728 dmas = <&apbdma 26>, <&apbdma 728 dmas = <&apbdma 26>, <&apbdma 26>; 729 dma-names = "rx", "tx"; 729 dma-names = "rx", "tx"; 730 pinctrl-0 = <&state_dpaux1_i2c 730 pinctrl-0 = <&state_dpaux1_i2c>; 731 pinctrl-1 = <&state_dpaux1_off 731 pinctrl-1 = <&state_dpaux1_off>; 732 pinctrl-names = "default", "id 732 pinctrl-names = "default", "idle"; 733 status = "disabled"; 733 status = "disabled"; 734 }; 734 }; 735 735 736 i2c@7000d000 { 736 i2c@7000d000 { 737 compatible = "nvidia,tegra210- 737 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 738 reg = <0x0 0x7000d000 0x0 0x10 738 reg = <0x0 0x7000d000 0x0 0x100>; 739 interrupts = <GIC_SPI 53 IRQ_T 739 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 740 #address-cells = <1>; 740 #address-cells = <1>; 741 #size-cells = <0>; 741 #size-cells = <0>; 742 clocks = <&tegra_car TEGRA210_ 742 clocks = <&tegra_car TEGRA210_CLK_I2C5>; 743 clock-names = "div-clk"; 743 clock-names = "div-clk"; 744 resets = <&tegra_car 47>; 744 resets = <&tegra_car 47>; 745 reset-names = "i2c"; 745 reset-names = "i2c"; 746 dmas = <&apbdma 24>, <&apbdma 746 dmas = <&apbdma 24>, <&apbdma 24>; 747 dma-names = "rx", "tx"; 747 dma-names = "rx", "tx"; 748 status = "disabled"; 748 status = "disabled"; 749 }; 749 }; 750 750 751 i2c@7000d100 { 751 i2c@7000d100 { 752 compatible = "nvidia,tegra210- 752 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 753 reg = <0x0 0x7000d100 0x0 0x10 753 reg = <0x0 0x7000d100 0x0 0x100>; 754 interrupts = <GIC_SPI 63 IRQ_T 754 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 755 #address-cells = <1>; 755 #address-cells = <1>; 756 #size-cells = <0>; 756 #size-cells = <0>; 757 clocks = <&tegra_car TEGRA210_ 757 clocks = <&tegra_car TEGRA210_CLK_I2C6>; 758 clock-names = "div-clk"; 758 clock-names = "div-clk"; 759 resets = <&tegra_car 166>; 759 resets = <&tegra_car 166>; 760 reset-names = "i2c"; 760 reset-names = "i2c"; 761 dmas = <&apbdma 30>, <&apbdma 761 dmas = <&apbdma 30>, <&apbdma 30>; 762 dma-names = "rx", "tx"; 762 dma-names = "rx", "tx"; 763 pinctrl-0 = <&state_dpaux_i2c> 763 pinctrl-0 = <&state_dpaux_i2c>; 764 pinctrl-1 = <&state_dpaux_off> 764 pinctrl-1 = <&state_dpaux_off>; 765 pinctrl-names = "default", "id 765 pinctrl-names = "default", "idle"; 766 status = "disabled"; 766 status = "disabled"; 767 }; 767 }; 768 768 769 spi@7000d400 { 769 spi@7000d400 { 770 compatible = "nvidia,tegra210- 770 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 771 reg = <0x0 0x7000d400 0x0 0x20 771 reg = <0x0 0x7000d400 0x0 0x200>; 772 interrupts = <GIC_SPI 59 IRQ_T 772 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 773 #address-cells = <1>; 773 #address-cells = <1>; 774 #size-cells = <0>; 774 #size-cells = <0>; 775 clocks = <&tegra_car TEGRA210_ 775 clocks = <&tegra_car TEGRA210_CLK_SBC1>; 776 clock-names = "spi"; 776 clock-names = "spi"; 777 resets = <&tegra_car 41>; 777 resets = <&tegra_car 41>; 778 reset-names = "spi"; 778 reset-names = "spi"; 779 dmas = <&apbdma 15>, <&apbdma 779 dmas = <&apbdma 15>, <&apbdma 15>; 780 dma-names = "rx", "tx"; 780 dma-names = "rx", "tx"; 781 status = "disabled"; 781 status = "disabled"; 782 }; 782 }; 783 783 784 spi@7000d600 { 784 spi@7000d600 { 785 compatible = "nvidia,tegra210- 785 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 786 reg = <0x0 0x7000d600 0x0 0x20 786 reg = <0x0 0x7000d600 0x0 0x200>; 787 interrupts = <GIC_SPI 82 IRQ_T 787 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 788 #address-cells = <1>; 788 #address-cells = <1>; 789 #size-cells = <0>; 789 #size-cells = <0>; 790 clocks = <&tegra_car TEGRA210_ 790 clocks = <&tegra_car TEGRA210_CLK_SBC2>; 791 clock-names = "spi"; 791 clock-names = "spi"; 792 resets = <&tegra_car 44>; 792 resets = <&tegra_car 44>; 793 reset-names = "spi"; 793 reset-names = "spi"; 794 dmas = <&apbdma 16>, <&apbdma 794 dmas = <&apbdma 16>, <&apbdma 16>; 795 dma-names = "rx", "tx"; 795 dma-names = "rx", "tx"; 796 status = "disabled"; 796 status = "disabled"; 797 }; 797 }; 798 798 799 spi@7000d800 { 799 spi@7000d800 { 800 compatible = "nvidia,tegra210- 800 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 801 reg = <0x0 0x7000d800 0x0 0x20 801 reg = <0x0 0x7000d800 0x0 0x200>; 802 interrupts = <GIC_SPI 83 IRQ_T 802 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 803 #address-cells = <1>; 803 #address-cells = <1>; 804 #size-cells = <0>; 804 #size-cells = <0>; 805 clocks = <&tegra_car TEGRA210_ 805 clocks = <&tegra_car TEGRA210_CLK_SBC3>; 806 clock-names = "spi"; 806 clock-names = "spi"; 807 resets = <&tegra_car 46>; 807 resets = <&tegra_car 46>; 808 reset-names = "spi"; 808 reset-names = "spi"; 809 dmas = <&apbdma 17>, <&apbdma 809 dmas = <&apbdma 17>, <&apbdma 17>; 810 dma-names = "rx", "tx"; 810 dma-names = "rx", "tx"; 811 status = "disabled"; 811 status = "disabled"; 812 }; 812 }; 813 813 814 spi@7000da00 { 814 spi@7000da00 { 815 compatible = "nvidia,tegra210- 815 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 816 reg = <0x0 0x7000da00 0x0 0x20 816 reg = <0x0 0x7000da00 0x0 0x200>; 817 interrupts = <GIC_SPI 93 IRQ_T 817 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 818 #address-cells = <1>; 818 #address-cells = <1>; 819 #size-cells = <0>; 819 #size-cells = <0>; 820 clocks = <&tegra_car TEGRA210_ 820 clocks = <&tegra_car TEGRA210_CLK_SBC4>; 821 clock-names = "spi"; 821 clock-names = "spi"; 822 resets = <&tegra_car 68>; 822 resets = <&tegra_car 68>; 823 reset-names = "spi"; 823 reset-names = "spi"; 824 dmas = <&apbdma 18>, <&apbdma 824 dmas = <&apbdma 18>, <&apbdma 18>; 825 dma-names = "rx", "tx"; 825 dma-names = "rx", "tx"; 826 status = "disabled"; 826 status = "disabled"; 827 }; 827 }; 828 828 829 rtc@7000e000 { 829 rtc@7000e000 { 830 compatible = "nvidia,tegra210- 830 compatible = "nvidia,tegra210-rtc", "nvidia,tegra20-rtc"; 831 reg = <0x0 0x7000e000 0x0 0x10 831 reg = <0x0 0x7000e000 0x0 0x100>; 832 interrupts = <16 IRQ_TYPE_LEVE 832 interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; 833 interrupt-parent = <&tegra_pmc 833 interrupt-parent = <&tegra_pmc>; 834 clocks = <&tegra_car TEGRA210_ 834 clocks = <&tegra_car TEGRA210_CLK_RTC>; 835 clock-names = "rtc"; 835 clock-names = "rtc"; 836 }; 836 }; 837 837 838 tegra_pmc: pmc@7000e400 { 838 tegra_pmc: pmc@7000e400 { 839 compatible = "nvidia,tegra210- 839 compatible = "nvidia,tegra210-pmc"; 840 reg = <0x0 0x7000e400 0x0 0x40 840 reg = <0x0 0x7000e400 0x0 0x400>; 841 clocks = <&tegra_car TEGRA210_ 841 clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>; 842 clock-names = "pclk", "clk32k_ 842 clock-names = "pclk", "clk32k_in"; 843 #clock-cells = <1>; 843 #clock-cells = <1>; 844 #interrupt-cells = <2>; 844 #interrupt-cells = <2>; 845 interrupt-controller; 845 interrupt-controller; 846 846 847 pinmux { 847 pinmux { 848 pex_dpd_disable: pex-d 848 pex_dpd_disable: pex-dpd-disable { 849 pins = "pex-bi 849 pins = "pex-bias", "pex-clk1", "pex-clk2"; 850 low-power-disa 850 low-power-disable; 851 }; 851 }; 852 852 853 pex_dpd_enable: pex-dp 853 pex_dpd_enable: pex-dpd-enable { 854 pins = "pex-bi 854 pins = "pex-bias", "pex-clk1", "pex-clk2"; 855 low-power-enab 855 low-power-enable; 856 }; 856 }; 857 857 858 sdmmc1_1v8: sdmmc1-1v8 858 sdmmc1_1v8: sdmmc1-1v8 { 859 pins = "sdmmc1 859 pins = "sdmmc1"; 860 power-source = 860 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 861 }; 861 }; 862 862 863 sdmmc1_3v3: sdmmc1-3v3 863 sdmmc1_3v3: sdmmc1-3v3 { 864 pins = "sdmmc1 864 pins = "sdmmc1"; 865 power-source = 865 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 866 }; 866 }; 867 867 868 sdmmc3_1v8: sdmmc3-1v8 868 sdmmc3_1v8: sdmmc3-1v8 { 869 pins = "sdmmc3 869 pins = "sdmmc3"; 870 power-source = 870 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 871 }; 871 }; 872 872 873 sdmmc3_3v3: sdmmc3-3v3 873 sdmmc3_3v3: sdmmc3-3v3 { 874 pins = "sdmmc3 874 pins = "sdmmc3"; 875 power-source = 875 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 876 }; 876 }; 877 }; 877 }; 878 878 879 powergates { 879 powergates { 880 pd_audio: aud { 880 pd_audio: aud { 881 clocks = <&teg 881 clocks = <&tegra_car TEGRA210_CLK_APE>, 882 <&teg 882 <&tegra_car TEGRA210_CLK_APB2APE>; 883 resets = <&teg 883 resets = <&tegra_car 198>; 884 #power-domain- 884 #power-domain-cells = <0>; 885 }; 885 }; 886 886 887 pd_sor: sor { 887 pd_sor: sor { 888 clocks = <&teg 888 clocks = <&tegra_car TEGRA210_CLK_SOR0>, 889 <&teg 889 <&tegra_car TEGRA210_CLK_SOR1>, 890 <&teg 890 <&tegra_car TEGRA210_CLK_CILAB>, 891 <&teg 891 <&tegra_car TEGRA210_CLK_CILCD>, 892 <&teg 892 <&tegra_car TEGRA210_CLK_CILE>, 893 <&teg 893 <&tegra_car TEGRA210_CLK_DSIA>, 894 <&teg 894 <&tegra_car TEGRA210_CLK_DSIB>, 895 <&teg 895 <&tegra_car TEGRA210_CLK_DPAUX>, 896 <&teg 896 <&tegra_car TEGRA210_CLK_DPAUX1>, 897 <&teg 897 <&tegra_car TEGRA210_CLK_MIPI_CAL>; 898 resets = <&teg 898 resets = <&tegra_car TEGRA210_CLK_SOR0>, 899 <&teg 899 <&tegra_car TEGRA210_CLK_SOR1>, 900 <&teg 900 <&tegra_car TEGRA210_CLK_DSIA>, 901 <&teg 901 <&tegra_car TEGRA210_CLK_DSIB>, 902 <&teg 902 <&tegra_car TEGRA210_CLK_DPAUX>, 903 <&teg 903 <&tegra_car TEGRA210_CLK_DPAUX1>, 904 <&teg 904 <&tegra_car TEGRA210_CLK_MIPI_CAL>; 905 #power-domain- 905 #power-domain-cells = <0>; 906 }; 906 }; 907 907 908 pd_venc: venc { 908 pd_venc: venc { 909 clocks = <&teg 909 clocks = <&tegra_car TEGRA210_CLK_VI>, 910 <&teg 910 <&tegra_car TEGRA210_CLK_CSI>; 911 resets = <&mc 911 resets = <&mc TEGRA210_MC_RESET_VI>, 912 <&teg 912 <&tegra_car 20>, 913 <&teg 913 <&tegra_car 52>; 914 #power-domain- 914 #power-domain-cells = <0>; 915 }; 915 }; 916 916 917 pd_vic: vic { 917 pd_vic: vic { 918 clocks = <&teg 918 clocks = <&tegra_car TEGRA210_CLK_VIC03>; >> 919 clock-names = "vic"; 919 resets = <&teg 920 resets = <&tegra_car 178>; >> 921 reset-names = "vic"; 920 #power-domain- 922 #power-domain-cells = <0>; 921 }; 923 }; 922 924 923 pd_xusbss: xusba { 925 pd_xusbss: xusba { 924 clocks = <&teg 926 clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>; 925 resets = <&teg 927 resets = <&tegra_car TEGRA210_CLK_XUSB_SS>; 926 #power-domain- 928 #power-domain-cells = <0>; 927 }; 929 }; 928 930 929 pd_xusbdev: xusbb { 931 pd_xusbdev: xusbb { 930 clocks = <&teg 932 clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>; 931 resets = <&teg 933 resets = <&tegra_car 95>; 932 #power-domain- 934 #power-domain-cells = <0>; 933 }; 935 }; 934 936 935 pd_xusbhost: xusbc { 937 pd_xusbhost: xusbc { 936 clocks = <&teg 938 clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>; 937 resets = <&teg 939 resets = <&tegra_car TEGRA210_CLK_XUSB_HOST>; 938 #power-domain- 940 #power-domain-cells = <0>; 939 }; 941 }; 940 }; 942 }; 941 }; 943 }; 942 944 943 fuse@7000f800 { 945 fuse@7000f800 { 944 compatible = "nvidia,tegra210- 946 compatible = "nvidia,tegra210-efuse"; 945 reg = <0x0 0x7000f800 0x0 0x40 947 reg = <0x0 0x7000f800 0x0 0x400>; 946 clocks = <&tegra_car TEGRA210_ 948 clocks = <&tegra_car TEGRA210_CLK_FUSE>; 947 clock-names = "fuse"; 949 clock-names = "fuse"; 948 resets = <&tegra_car 39>; 950 resets = <&tegra_car 39>; 949 reset-names = "fuse"; 951 reset-names = "fuse"; 950 }; 952 }; 951 953 952 mc: memory-controller@70019000 { 954 mc: memory-controller@70019000 { 953 compatible = "nvidia,tegra210- 955 compatible = "nvidia,tegra210-mc"; 954 reg = <0x0 0x70019000 0x0 0x10 956 reg = <0x0 0x70019000 0x0 0x1000>; 955 clocks = <&tegra_car TEGRA210_ 957 clocks = <&tegra_car TEGRA210_CLK_MC>; 956 clock-names = "mc"; 958 clock-names = "mc"; 957 959 958 interrupts = <GIC_SPI 77 IRQ_T 960 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 959 961 960 #iommu-cells = <1>; 962 #iommu-cells = <1>; 961 #reset-cells = <1>; 963 #reset-cells = <1>; 962 }; 964 }; 963 965 964 emc: external-memory-controller@7001b0 966 emc: external-memory-controller@7001b000 { 965 compatible = "nvidia,tegra210- 967 compatible = "nvidia,tegra210-emc"; 966 reg = <0x0 0x7001b000 0x0 0x10 968 reg = <0x0 0x7001b000 0x0 0x1000>, 967 <0x0 0x7001e000 0x0 0x10 969 <0x0 0x7001e000 0x0 0x1000>, 968 <0x0 0x7001f000 0x0 0x10 970 <0x0 0x7001f000 0x0 0x1000>; 969 clocks = <&tegra_car TEGRA210_ 971 clocks = <&tegra_car TEGRA210_CLK_EMC>; 970 clock-names = "emc"; 972 clock-names = "emc"; 971 interrupts = <GIC_SPI 78 IRQ_T 973 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 972 nvidia,memory-controller = <&m 974 nvidia,memory-controller = <&mc>; 973 #cooling-cells = <2>; 975 #cooling-cells = <2>; 974 }; 976 }; 975 977 976 sata@70020000 { 978 sata@70020000 { 977 compatible = "nvidia,tegra210- 979 compatible = "nvidia,tegra210-ahci"; 978 reg = <0x0 0x70027000 0x0 0x20 980 reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */ 979 <0x0 0x70020000 0x0 0x70 981 <0x0 0x70020000 0x0 0x7000>, /* SATA */ 980 <0x0 0x70001100 0x0 0x10 982 <0x0 0x70001100 0x0 0x1000>; /* SATA AUX */ 981 interrupts = <GIC_SPI 23 IRQ_T 983 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 982 clocks = <&tegra_car TEGRA210_ 984 clocks = <&tegra_car TEGRA210_CLK_SATA>, 983 <&tegra_car TEGRA210_ 985 <&tegra_car TEGRA210_CLK_SATA_OOB>; 984 clock-names = "sata", "sata-oo 986 clock-names = "sata", "sata-oob"; 985 resets = <&tegra_car 124>, 987 resets = <&tegra_car 124>, 986 <&tegra_car 129>, 988 <&tegra_car 129>, 987 <&tegra_car 123>; 989 <&tegra_car 123>; 988 reset-names = "sata", "sata-co 990 reset-names = "sata", "sata-cold", "sata-oob"; 989 status = "disabled"; 991 status = "disabled"; 990 }; 992 }; 991 993 992 hda@70030000 { 994 hda@70030000 { 993 compatible = "nvidia,tegra210- 995 compatible = "nvidia,tegra210-hda", "nvidia,tegra30-hda"; 994 reg = <0x0 0x70030000 0x0 0x10 996 reg = <0x0 0x70030000 0x0 0x10000>; 995 interrupts = <GIC_SPI 81 IRQ_T 997 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 996 clocks = <&tegra_car TEGRA210_ 998 clocks = <&tegra_car TEGRA210_CLK_HDA>, 997 <&tegra_car TEGRA210_ 999 <&tegra_car TEGRA210_CLK_HDA2HDMI>, 998 <&tegra_car TEGRA210_ 1000 <&tegra_car TEGRA210_CLK_HDA2CODEC_2X>; 999 clock-names = "hda", "hda2hdmi 1001 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 1000 resets = <&tegra_car 125>, /* 1002 resets = <&tegra_car 125>, /* hda */ 1001 <&tegra_car 128>, /* 1003 <&tegra_car 128>, /* hda2hdmi */ 1002 <&tegra_car 111>; /* 1004 <&tegra_car 111>; /* hda2codec_2x */ 1003 reset-names = "hda", "hda2hdm 1005 reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 1004 power-domains = <&pd_sor>; 1006 power-domains = <&pd_sor>; 1005 status = "disabled"; 1007 status = "disabled"; 1006 }; 1008 }; 1007 1009 1008 usb@70090000 { 1010 usb@70090000 { 1009 compatible = "nvidia,tegra210 1011 compatible = "nvidia,tegra210-xusb"; 1010 reg = <0x0 0x70090000 0x0 0x8 1012 reg = <0x0 0x70090000 0x0 0x8000>, 1011 <0x0 0x70098000 0x0 0x1 1013 <0x0 0x70098000 0x0 0x1000>, 1012 <0x0 0x70099000 0x0 0x1 1014 <0x0 0x70099000 0x0 0x1000>; 1013 reg-names = "hcd", "fpci", "i 1015 reg-names = "hcd", "fpci", "ipfs"; 1014 1016 1015 interrupts = <GIC_SPI 39 IRQ_ 1017 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 1016 <GIC_SPI 40 IRQ_ 1018 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 1017 1019 1018 clocks = <&tegra_car TEGRA210 1020 clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>, 1019 <&tegra_car TEGRA210 1021 <&tegra_car TEGRA210_CLK_XUSB_HOST_SRC>, 1020 <&tegra_car TEGRA210 1022 <&tegra_car TEGRA210_CLK_XUSB_FALCON_SRC>, 1021 <&tegra_car TEGRA210 1023 <&tegra_car TEGRA210_CLK_XUSB_SS>, 1022 <&tegra_car TEGRA210 1024 <&tegra_car TEGRA210_CLK_XUSB_SS_DIV2>, 1023 <&tegra_car TEGRA210 1025 <&tegra_car TEGRA210_CLK_XUSB_SS_SRC>, 1024 <&tegra_car TEGRA210 1026 <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>, 1025 <&tegra_car TEGRA210 1027 <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>, 1026 <&tegra_car TEGRA210 1028 <&tegra_car TEGRA210_CLK_PLL_U_480M>, 1027 <&tegra_car TEGRA210 1029 <&tegra_car TEGRA210_CLK_CLK_M>, 1028 <&tegra_car TEGRA210 1030 <&tegra_car TEGRA210_CLK_PLL_E>; 1029 clock-names = "xusb_host", "x 1031 clock-names = "xusb_host", "xusb_host_src", 1030 "xusb_falcon_sr 1032 "xusb_falcon_src", "xusb_ss", 1031 "xusb_ss_div2", 1033 "xusb_ss_div2", "xusb_ss_src", 1032 "xusb_hs_src", 1034 "xusb_hs_src", "xusb_fs_src", 1033 "pll_u_480m", " 1035 "pll_u_480m", "clk_m", "pll_e"; 1034 resets = <&tegra_car 89>, <&t 1036 resets = <&tegra_car 89>, <&tegra_car 156>, 1035 <&tegra_car 143>; 1037 <&tegra_car 143>; 1036 reset-names = "xusb_host", "x 1038 reset-names = "xusb_host", "xusb_ss", "xusb_src"; 1037 power-domains = <&pd_xusbhost 1039 power-domains = <&pd_xusbhost>, <&pd_xusbss>; 1038 power-domain-names = "xusb_ho 1040 power-domain-names = "xusb_host", "xusb_ss"; 1039 1041 1040 nvidia,xusb-padctl = <&padctl 1042 nvidia,xusb-padctl = <&padctl>; 1041 1043 1042 status = "disabled"; 1044 status = "disabled"; 1043 }; 1045 }; 1044 1046 1045 padctl: padctl@7009f000 { 1047 padctl: padctl@7009f000 { 1046 compatible = "nvidia,tegra210 1048 compatible = "nvidia,tegra210-xusb-padctl"; 1047 reg = <0x0 0x7009f000 0x0 0x1 1049 reg = <0x0 0x7009f000 0x0 0x1000>; 1048 interrupts = <GIC_SPI 49 IRQ_ 1050 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 1049 resets = <&tegra_car 142>; 1051 resets = <&tegra_car 142>; 1050 reset-names = "padctl"; 1052 reset-names = "padctl"; 1051 nvidia,pmc = <&tegra_pmc>; 1053 nvidia,pmc = <&tegra_pmc>; 1052 1054 1053 status = "disabled"; 1055 status = "disabled"; 1054 1056 1055 pads { 1057 pads { 1056 usb2 { 1058 usb2 { 1057 clocks = <&te 1059 clocks = <&tegra_car TEGRA210_CLK_USB2_TRK>; 1058 clock-names = 1060 clock-names = "trk"; 1059 status = "dis 1061 status = "disabled"; 1060 1062 1061 lanes { 1063 lanes { 1062 usb2- 1064 usb2-0 { 1063 1065 status = "disabled"; 1064 1066 #phy-cells = <0>; 1065 }; 1067 }; 1066 1068 1067 usb2- 1069 usb2-1 { 1068 1070 status = "disabled"; 1069 1071 #phy-cells = <0>; 1070 }; 1072 }; 1071 1073 1072 usb2- 1074 usb2-2 { 1073 1075 status = "disabled"; 1074 1076 #phy-cells = <0>; 1075 }; 1077 }; 1076 1078 1077 usb2- 1079 usb2-3 { 1078 1080 status = "disabled"; 1079 1081 #phy-cells = <0>; 1080 }; 1082 }; 1081 }; 1083 }; 1082 }; 1084 }; 1083 1085 1084 hsic { 1086 hsic { 1085 clocks = <&te 1087 clocks = <&tegra_car TEGRA210_CLK_HSIC_TRK>; 1086 clock-names = 1088 clock-names = "trk"; 1087 status = "dis 1089 status = "disabled"; 1088 1090 1089 lanes { 1091 lanes { 1090 hsic- 1092 hsic-0 { 1091 1093 status = "disabled"; 1092 1094 #phy-cells = <0>; 1093 }; 1095 }; 1094 1096 1095 hsic- 1097 hsic-1 { 1096 1098 status = "disabled"; 1097 1099 #phy-cells = <0>; 1098 }; 1100 }; 1099 }; 1101 }; 1100 }; 1102 }; 1101 1103 1102 pcie { 1104 pcie { 1103 clocks = <&te 1105 clocks = <&tegra_car TEGRA210_CLK_PLL_E>; 1104 clock-names = 1106 clock-names = "pll"; 1105 resets = <&te 1107 resets = <&tegra_car 205>; 1106 reset-names = 1108 reset-names = "phy"; 1107 status = "dis 1109 status = "disabled"; 1108 1110 1109 lanes { 1111 lanes { 1110 pcie- 1112 pcie-0 { 1111 1113 status = "disabled"; 1112 1114 #phy-cells = <0>; 1113 }; 1115 }; 1114 1116 1115 pcie- 1117 pcie-1 { 1116 1118 status = "disabled"; 1117 1119 #phy-cells = <0>; 1118 }; 1120 }; 1119 1121 1120 pcie- 1122 pcie-2 { 1121 1123 status = "disabled"; 1122 1124 #phy-cells = <0>; 1123 }; 1125 }; 1124 1126 1125 pcie- 1127 pcie-3 { 1126 1128 status = "disabled"; 1127 1129 #phy-cells = <0>; 1128 }; 1130 }; 1129 1131 1130 pcie- 1132 pcie-4 { 1131 1133 status = "disabled"; 1132 1134 #phy-cells = <0>; 1133 }; 1135 }; 1134 1136 1135 pcie- 1137 pcie-5 { 1136 1138 status = "disabled"; 1137 1139 #phy-cells = <0>; 1138 }; 1140 }; 1139 1141 1140 pcie- 1142 pcie-6 { 1141 1143 status = "disabled"; 1142 1144 #phy-cells = <0>; 1143 }; 1145 }; 1144 }; 1146 }; 1145 }; 1147 }; 1146 1148 1147 sata { 1149 sata { 1148 clocks = <&te 1150 clocks = <&tegra_car TEGRA210_CLK_PLL_E>; 1149 clock-names = 1151 clock-names = "pll"; 1150 resets = <&te 1152 resets = <&tegra_car 204>; 1151 reset-names = 1153 reset-names = "phy"; 1152 status = "dis 1154 status = "disabled"; 1153 1155 1154 lanes { 1156 lanes { 1155 sata- 1157 sata-0 { 1156 1158 status = "disabled"; 1157 1159 #phy-cells = <0>; 1158 }; 1160 }; 1159 }; 1161 }; 1160 }; 1162 }; 1161 }; 1163 }; 1162 1164 1163 ports { 1165 ports { 1164 usb2-0 { 1166 usb2-0 { 1165 status = "dis 1167 status = "disabled"; 1166 }; 1168 }; 1167 1169 1168 usb2-1 { 1170 usb2-1 { 1169 status = "dis 1171 status = "disabled"; 1170 }; 1172 }; 1171 1173 1172 usb2-2 { 1174 usb2-2 { 1173 status = "dis 1175 status = "disabled"; 1174 }; 1176 }; 1175 1177 1176 usb2-3 { 1178 usb2-3 { 1177 status = "dis 1179 status = "disabled"; 1178 }; 1180 }; 1179 1181 1180 hsic-0 { 1182 hsic-0 { 1181 status = "dis 1183 status = "disabled"; 1182 }; 1184 }; 1183 1185 1184 usb3-0 { 1186 usb3-0 { 1185 status = "dis 1187 status = "disabled"; 1186 }; 1188 }; 1187 1189 1188 usb3-1 { 1190 usb3-1 { 1189 status = "dis 1191 status = "disabled"; 1190 }; 1192 }; 1191 1193 1192 usb3-2 { 1194 usb3-2 { 1193 status = "dis 1195 status = "disabled"; 1194 }; 1196 }; 1195 1197 1196 usb3-3 { 1198 usb3-3 { 1197 status = "dis 1199 status = "disabled"; 1198 }; 1200 }; 1199 }; 1201 }; 1200 }; 1202 }; 1201 1203 1202 mmc@700b0000 { 1204 mmc@700b0000 { 1203 compatible = "nvidia,tegra210 1205 compatible = "nvidia,tegra210-sdhci"; 1204 reg = <0x0 0x700b0000 0x0 0x2 1206 reg = <0x0 0x700b0000 0x0 0x200>; 1205 interrupts = <GIC_SPI 14 IRQ_ 1207 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1206 clocks = <&tegra_car TEGRA210 1208 clocks = <&tegra_car TEGRA210_CLK_SDMMC1>, 1207 <&tegra_car TEGRA210 1209 <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>; 1208 clock-names = "sdhci", "tmclk 1210 clock-names = "sdhci", "tmclk"; 1209 resets = <&tegra_car 14>; 1211 resets = <&tegra_car 14>; 1210 reset-names = "sdhci"; 1212 reset-names = "sdhci"; 1211 pinctrl-names = "sdmmc-3v3", 1213 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8", 1212 "sdmmc-3v3-dr 1214 "sdmmc-3v3-drv", "sdmmc-1v8-drv"; 1213 pinctrl-0 = <&sdmmc1_3v3>; 1215 pinctrl-0 = <&sdmmc1_3v3>; 1214 pinctrl-1 = <&sdmmc1_1v8>; 1216 pinctrl-1 = <&sdmmc1_1v8>; 1215 pinctrl-2 = <&sdmmc1_3v3_drv> 1217 pinctrl-2 = <&sdmmc1_3v3_drv>; 1216 pinctrl-3 = <&sdmmc1_1v8_drv> 1218 pinctrl-3 = <&sdmmc1_1v8_drv>; 1217 nvidia,pad-autocal-pull-up-of 1219 nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>; 1218 nvidia,pad-autocal-pull-down- 1220 nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>; 1219 nvidia,pad-autocal-pull-up-of 1221 nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>; 1220 nvidia,pad-autocal-pull-down- 1222 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>; 1221 nvidia,default-tap = <0x2>; 1223 nvidia,default-tap = <0x2>; 1222 nvidia,default-trim = <0x4>; 1224 nvidia,default-trim = <0x4>; 1223 assigned-clocks = <&tegra_car 1225 assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>, 1224 <&tegra_car 1226 <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>, 1225 <&tegra_car 1227 <&tegra_car TEGRA210_CLK_PLL_C4>; 1226 assigned-clock-parents = <&te 1228 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; 1227 assigned-clock-rates = <20000 1229 assigned-clock-rates = <200000000>, <1000000000>, <1000000000>; 1228 status = "disabled"; 1230 status = "disabled"; 1229 }; 1231 }; 1230 1232 1231 mmc@700b0200 { 1233 mmc@700b0200 { 1232 compatible = "nvidia,tegra210 1234 compatible = "nvidia,tegra210-sdhci"; 1233 reg = <0x0 0x700b0200 0x0 0x2 1235 reg = <0x0 0x700b0200 0x0 0x200>; 1234 interrupts = <GIC_SPI 15 IRQ_ 1236 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 1235 clocks = <&tegra_car TEGRA210 1237 clocks = <&tegra_car TEGRA210_CLK_SDMMC2>, 1236 <&tegra_car TEGRA210 1238 <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>; 1237 clock-names = "sdhci", "tmclk 1239 clock-names = "sdhci", "tmclk"; 1238 resets = <&tegra_car 9>; 1240 resets = <&tegra_car 9>; 1239 reset-names = "sdhci"; 1241 reset-names = "sdhci"; 1240 pinctrl-names = "sdmmc-1v8-dr 1242 pinctrl-names = "sdmmc-1v8-drv"; 1241 pinctrl-0 = <&sdmmc2_1v8_drv> 1243 pinctrl-0 = <&sdmmc2_1v8_drv>; 1242 nvidia,pad-autocal-pull-up-of 1244 nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>; 1243 nvidia,pad-autocal-pull-down- 1245 nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>; 1244 nvidia,default-tap = <0x8>; 1246 nvidia,default-tap = <0x8>; 1245 nvidia,default-trim = <0x0>; 1247 nvidia,default-trim = <0x0>; 1246 status = "disabled"; 1248 status = "disabled"; 1247 }; 1249 }; 1248 1250 1249 mmc@700b0400 { 1251 mmc@700b0400 { 1250 compatible = "nvidia,tegra210 1252 compatible = "nvidia,tegra210-sdhci"; 1251 reg = <0x0 0x700b0400 0x0 0x2 1253 reg = <0x0 0x700b0400 0x0 0x200>; 1252 interrupts = <GIC_SPI 19 IRQ_ 1254 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 1253 clocks = <&tegra_car TEGRA210 1255 clocks = <&tegra_car TEGRA210_CLK_SDMMC3>, 1254 <&tegra_car TEGRA210 1256 <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>; 1255 clock-names = "sdhci", "tmclk 1257 clock-names = "sdhci", "tmclk"; 1256 resets = <&tegra_car 69>; 1258 resets = <&tegra_car 69>; 1257 reset-names = "sdhci"; 1259 reset-names = "sdhci"; 1258 pinctrl-names = "sdmmc-3v3", 1260 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8", 1259 "sdmmc-3v3-dr 1261 "sdmmc-3v3-drv", "sdmmc-1v8-drv"; 1260 pinctrl-0 = <&sdmmc3_3v3>; 1262 pinctrl-0 = <&sdmmc3_3v3>; 1261 pinctrl-1 = <&sdmmc3_1v8>; 1263 pinctrl-1 = <&sdmmc3_1v8>; 1262 pinctrl-2 = <&sdmmc3_3v3_drv> 1264 pinctrl-2 = <&sdmmc3_3v3_drv>; 1263 pinctrl-3 = <&sdmmc3_1v8_drv> 1265 pinctrl-3 = <&sdmmc3_1v8_drv>; 1264 nvidia,pad-autocal-pull-up-of 1266 nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>; 1265 nvidia,pad-autocal-pull-down- 1267 nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>; 1266 nvidia,pad-autocal-pull-up-of 1268 nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>; 1267 nvidia,pad-autocal-pull-down- 1269 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>; 1268 nvidia,default-tap = <0x3>; 1270 nvidia,default-tap = <0x3>; 1269 nvidia,default-trim = <0x3>; 1271 nvidia,default-trim = <0x3>; 1270 status = "disabled"; 1272 status = "disabled"; 1271 }; 1273 }; 1272 1274 1273 mmc@700b0600 { 1275 mmc@700b0600 { 1274 compatible = "nvidia,tegra210 1276 compatible = "nvidia,tegra210-sdhci"; 1275 reg = <0x0 0x700b0600 0x0 0x2 1277 reg = <0x0 0x700b0600 0x0 0x200>; 1276 interrupts = <GIC_SPI 31 IRQ_ 1278 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 1277 clocks = <&tegra_car TEGRA210 1279 clocks = <&tegra_car TEGRA210_CLK_SDMMC4>, 1278 <&tegra_car TEGRA210 1280 <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>; 1279 clock-names = "sdhci", "tmclk 1281 clock-names = "sdhci", "tmclk"; 1280 resets = <&tegra_car 15>; 1282 resets = <&tegra_car 15>; 1281 reset-names = "sdhci"; 1283 reset-names = "sdhci"; 1282 pinctrl-names = "sdmmc-3v3-dr 1284 pinctrl-names = "sdmmc-3v3-drv", "sdmmc-1v8-drv"; 1283 pinctrl-0 = <&sdmmc4_1v8_drv> 1285 pinctrl-0 = <&sdmmc4_1v8_drv>; 1284 pinctrl-1 = <&sdmmc4_1v8_drv> 1286 pinctrl-1 = <&sdmmc4_1v8_drv>; 1285 nvidia,pad-autocal-pull-up-of 1287 nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>; 1286 nvidia,pad-autocal-pull-down- 1288 nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>; 1287 nvidia,default-tap = <0x8>; 1289 nvidia,default-tap = <0x8>; 1288 nvidia,default-trim = <0x0>; 1290 nvidia,default-trim = <0x0>; 1289 assigned-clocks = <&tegra_car 1291 assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>, 1290 <&tegra_car 1292 <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; 1291 assigned-clock-parents = <&te 1293 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; 1292 nvidia,dqs-trim = <40>; 1294 nvidia,dqs-trim = <40>; 1293 mmc-hs400-1_8v; 1295 mmc-hs400-1_8v; 1294 status = "disabled"; 1296 status = "disabled"; 1295 }; 1297 }; 1296 1298 1297 usb@700d0000 { 1299 usb@700d0000 { 1298 compatible = "nvidia,tegra210 1300 compatible = "nvidia,tegra210-xudc"; 1299 reg = <0x0 0x700d0000 0x0 0x8 1301 reg = <0x0 0x700d0000 0x0 0x8000>, 1300 <0x0 0x700d8000 0x0 0x1 1302 <0x0 0x700d8000 0x0 0x1000>, 1301 <0x0 0x700d9000 0x0 0x1 1303 <0x0 0x700d9000 0x0 0x1000>; 1302 reg-names = "base", "fpci", " 1304 reg-names = "base", "fpci", "ipfs"; 1303 interrupts = <GIC_SPI 44 IRQ_ 1305 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1304 clocks = <&tegra_car TEGRA210 1306 clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>, 1305 <&tegra_car TEGRA210 1307 <&tegra_car TEGRA210_CLK_XUSB_SS>, 1306 <&tegra_car TEGRA210 1308 <&tegra_car TEGRA210_CLK_XUSB_SSP_SRC>, 1307 <&tegra_car TEGRA210 1309 <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>, 1308 <&tegra_car TEGRA210 1310 <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>; 1309 clock-names = "dev", "ss", "s 1311 clock-names = "dev", "ss", "ss_src", "fs_src", "hs_src"; 1310 power-domains = <&pd_xusbdev> 1312 power-domains = <&pd_xusbdev>, <&pd_xusbss>; 1311 power-domain-names = "dev", " 1313 power-domain-names = "dev", "ss"; 1312 nvidia,xusb-padctl = <&padctl 1314 nvidia,xusb-padctl = <&padctl>; 1313 status = "disabled"; 1315 status = "disabled"; 1314 }; 1316 }; 1315 1317 1316 soctherm: thermal-sensor@700e2000 { 1318 soctherm: thermal-sensor@700e2000 { 1317 compatible = "nvidia,tegra210 1319 compatible = "nvidia,tegra210-soctherm"; 1318 reg = <0x0 0x700e2000 0x0 0x6 1320 reg = <0x0 0x700e2000 0x0 0x600>, /* SOC_THERM reg_base */ 1319 <0x0 0x60006000 0x0 0x4 1321 <0x0 0x60006000 0x0 0x400>; /* CAR reg_base */ 1320 reg-names = "soctherm-reg", " 1322 reg-names = "soctherm-reg", "car-reg"; 1321 interrupts = <GIC_SPI 48 IRQ_ 1323 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 1322 <GIC_SPI 51 IRQ_ 1324 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 1323 interrupt-names = "thermal", 1325 interrupt-names = "thermal", "edp"; 1324 clocks = <&tegra_car TEGRA210 1326 clocks = <&tegra_car TEGRA210_CLK_TSENSOR>, 1325 <&tegra_car TEGRA210_ 1327 <&tegra_car TEGRA210_CLK_SOC_THERM>; 1326 clock-names = "tsensor", "soc 1328 clock-names = "tsensor", "soctherm"; 1327 resets = <&tegra_car 78>; 1329 resets = <&tegra_car 78>; 1328 reset-names = "soctherm"; 1330 reset-names = "soctherm"; 1329 #thermal-sensor-cells = <1>; 1331 #thermal-sensor-cells = <1>; 1330 1332 1331 throttle-cfgs { 1333 throttle-cfgs { 1332 throttle_heavy: heavy 1334 throttle_heavy: heavy { 1333 nvidia,priori 1335 nvidia,priority = <100>; 1334 nvidia,cpu-th 1336 nvidia,cpu-throt-percent = <85>; 1335 nvidia,gpu-th 1337 nvidia,gpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_HIGH>; 1336 1338 1337 #cooling-cell 1339 #cooling-cells = <2>; 1338 }; 1340 }; 1339 }; 1341 }; 1340 }; 1342 }; 1341 1343 1342 mipi: mipi@700e3000 { 1344 mipi: mipi@700e3000 { 1343 compatible = "nvidia,tegra210 1345 compatible = "nvidia,tegra210-mipi"; 1344 reg = <0x0 0x700e3000 0x0 0x1 1346 reg = <0x0 0x700e3000 0x0 0x100>; 1345 clocks = <&tegra_car TEGRA210 1347 clocks = <&tegra_car TEGRA210_CLK_MIPI_CAL>; 1346 clock-names = "mipi-cal"; 1348 clock-names = "mipi-cal"; 1347 power-domains = <&pd_sor>; 1349 power-domains = <&pd_sor>; 1348 #nvidia,mipi-calibrate-cells 1350 #nvidia,mipi-calibrate-cells = <1>; 1349 }; 1351 }; 1350 1352 1351 dfll: clock@70110000 { 1353 dfll: clock@70110000 { 1352 compatible = "nvidia,tegra210 1354 compatible = "nvidia,tegra210-dfll"; 1353 reg = <0 0x70110000 0 0x100>, 1355 reg = <0 0x70110000 0 0x100>, /* DFLL control */ 1354 <0 0x70110000 0 0x100>, 1356 <0 0x70110000 0 0x100>, /* I2C output control */ 1355 <0 0x70110100 0 0x100>, 1357 <0 0x70110100 0 0x100>, /* Integrated I2C controller */ 1356 <0 0x70110200 0 0x100>; 1358 <0 0x70110200 0 0x100>; /* Look-up table RAM */ 1357 interrupts = <GIC_SPI 62 IRQ_ 1359 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 1358 clocks = <&tegra_car TEGRA210 1360 clocks = <&tegra_car TEGRA210_CLK_DFLL_SOC>, 1359 <&tegra_car TEGRA210 1361 <&tegra_car TEGRA210_CLK_DFLL_REF>, 1360 <&tegra_car TEGRA210 1362 <&tegra_car TEGRA210_CLK_I2C5>; 1361 clock-names = "soc", "ref", " 1363 clock-names = "soc", "ref", "i2c"; 1362 resets = <&tegra_car TEGRA210 1364 resets = <&tegra_car TEGRA210_RST_DFLL_DVCO>, 1363 <&tegra_car 155>; 1365 <&tegra_car 155>; 1364 reset-names = "dvco", "dfll"; 1366 reset-names = "dvco", "dfll"; 1365 #clock-cells = <0>; 1367 #clock-cells = <0>; 1366 clock-output-names = "dfllCPU 1368 clock-output-names = "dfllCPU_out"; 1367 status = "disabled"; 1369 status = "disabled"; 1368 }; 1370 }; 1369 1371 1370 aconnect@702c0000 { 1372 aconnect@702c0000 { 1371 compatible = "nvidia,tegra210 1373 compatible = "nvidia,tegra210-aconnect"; 1372 clocks = <&tegra_car TEGRA210 1374 clocks = <&tegra_car TEGRA210_CLK_APE>, 1373 <&tegra_car TEGRA210 1375 <&tegra_car TEGRA210_CLK_APB2APE>; 1374 clock-names = "ape", "apb2ape 1376 clock-names = "ape", "apb2ape"; 1375 power-domains = <&pd_audio>; 1377 power-domains = <&pd_audio>; 1376 #address-cells = <1>; 1378 #address-cells = <1>; 1377 #size-cells = <1>; 1379 #size-cells = <1>; 1378 ranges = <0x702c0000 0x0 0x70 1380 ranges = <0x702c0000 0x0 0x702c0000 0x00040000>; 1379 status = "disabled"; 1381 status = "disabled"; 1380 1382 1381 tegra_ahub: ahub@702d0800 { 1383 tegra_ahub: ahub@702d0800 { 1382 compatible = "nvidia, 1384 compatible = "nvidia,tegra210-ahub"; 1383 reg = <0x702d0800 0x8 1385 reg = <0x702d0800 0x800>; 1384 clocks = <&tegra_car 1386 clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>; 1385 clock-names = "ahub"; 1387 clock-names = "ahub"; 1386 assigned-clocks = <&t 1388 assigned-clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>; 1387 assigned-clock-parent !! 1389 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 1388 assigned-clock-rates << 1389 #address-cells = <1>; 1390 #address-cells = <1>; 1390 #size-cells = <1>; 1391 #size-cells = <1>; 1391 ranges = <0x702d0000 1392 ranges = <0x702d0000 0x702d0000 0x0000e400>; 1392 status = "disabled"; 1393 status = "disabled"; 1393 1394 1394 tegra_admaif: admaif@ 1395 tegra_admaif: admaif@702d0000 { 1395 compatible = 1396 compatible = "nvidia,tegra210-admaif"; 1396 reg = <0x702d 1397 reg = <0x702d0000 0x800>; 1397 dmas = <&adma 1398 dmas = <&adma 1>, <&adma 1>, 1398 <&adma 1399 <&adma 2>, <&adma 2>, 1399 <&adma 1400 <&adma 3>, <&adma 3>, 1400 <&adma 1401 <&adma 4>, <&adma 4>, 1401 <&adma 1402 <&adma 5>, <&adma 5>, 1402 <&adma 1403 <&adma 6>, <&adma 6>, 1403 <&adma 1404 <&adma 7>, <&adma 7>, 1404 <&adma 1405 <&adma 8>, <&adma 8>, 1405 <&adma 1406 <&adma 9>, <&adma 9>, 1406 <&adma 1407 <&adma 10>, <&adma 10>; 1407 dma-names = " 1408 dma-names = "rx1", "tx1", 1408 " 1409 "rx2", "tx2", 1409 " 1410 "rx3", "tx3", 1410 " 1411 "rx4", "tx4", 1411 " 1412 "rx5", "tx5", 1412 " 1413 "rx6", "tx6", 1413 " 1414 "rx7", "tx7", 1414 " 1415 "rx8", "tx8", 1415 " 1416 "rx9", "tx9", 1416 " 1417 "rx10", "tx10"; 1417 status = "dis 1418 status = "disabled"; 1418 1419 1419 ports { 1420 ports { 1420 #addr 1421 #address-cells = <1>; 1421 #size 1422 #size-cells = <0>; 1422 1423 1423 admai 1424 admaif1_port: port@0 { 1424 1425 reg = <0>; 1425 1426 1426 1427 admaif1_ep: endpoint { 1427 1428 remote-endpoint = <&xbar_admaif1_ep>; 1428 1429 }; 1429 }; 1430 }; 1430 1431 1431 admai 1432 admaif2_port: port@1 { 1432 1433 reg = <1>; 1433 1434 1434 1435 admaif2_ep: endpoint { 1435 1436 remote-endpoint = <&xbar_admaif2_ep>; 1436 1437 }; 1437 }; 1438 }; 1438 1439 1439 admai 1440 admaif3_port: port@2 { 1440 1441 reg = <2>; 1441 1442 1442 1443 admaif3_ep: endpoint { 1443 1444 remote-endpoint = <&xbar_admaif3_ep>; 1444 1445 }; 1445 }; 1446 }; 1446 1447 1447 admai 1448 admaif4_port: port@3 { 1448 1449 reg = <3>; 1449 1450 1450 1451 admaif4_ep: endpoint { 1451 1452 remote-endpoint = <&xbar_admaif4_ep>; 1452 1453 }; 1453 }; 1454 }; 1454 1455 1455 admai 1456 admaif5_port: port@4 { 1456 1457 reg = <4>; 1457 1458 1458 1459 admaif5_ep: endpoint { 1459 1460 remote-endpoint = <&xbar_admaif5_ep>; 1460 1461 }; 1461 }; 1462 }; 1462 1463 1463 admai 1464 admaif6_port: port@5 { 1464 1465 reg = <5>; 1465 1466 1466 1467 admaif6_ep: endpoint { 1467 1468 remote-endpoint = <&xbar_admaif6_ep>; 1468 1469 }; 1469 }; 1470 }; 1470 1471 1471 admai 1472 admaif7_port: port@6 { 1472 1473 reg = <6>; 1473 1474 1474 1475 admaif7_ep: endpoint { 1475 1476 remote-endpoint = <&xbar_admaif7_ep>; 1476 1477 }; 1477 }; 1478 }; 1478 1479 1479 admai 1480 admaif8_port: port@7 { 1480 1481 reg = <7>; 1481 1482 1482 1483 admaif8_ep: endpoint { 1483 1484 remote-endpoint = <&xbar_admaif8_ep>; 1484 1485 }; 1485 }; 1486 }; 1486 1487 1487 admai 1488 admaif9_port: port@8 { 1488 1489 reg = <8>; 1489 1490 1490 1491 admaif9_ep: endpoint { 1491 1492 remote-endpoint = <&xbar_admaif9_ep>; 1492 1493 }; 1493 }; 1494 }; 1494 1495 1495 admai 1496 admaif10_port: port@9 { 1496 1497 reg = <9>; 1497 1498 1498 1499 admaif10_ep: endpoint { 1499 1500 remote-endpoint = <&xbar_admaif10_ep>; 1500 1501 }; 1501 }; 1502 }; 1502 }; 1503 }; 1503 }; 1504 }; 1504 1505 1505 tegra_i2s1: i2s@702d1 1506 tegra_i2s1: i2s@702d1000 { 1506 compatible = 1507 compatible = "nvidia,tegra210-i2s"; 1507 reg = <0x702d 1508 reg = <0x702d1000 0x100>; 1508 clocks = <&te 1509 clocks = <&tegra_car TEGRA210_CLK_I2S0>, 1509 <&te 1510 <&tegra_car TEGRA210_CLK_I2S0_SYNC>; 1510 clock-names = 1511 clock-names = "i2s", "sync_input"; 1511 assigned-cloc 1512 assigned-clocks = <&tegra_car TEGRA210_CLK_I2S0>; 1512 assigned-cloc 1513 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 1513 assigned-cloc 1514 assigned-clock-rates = <1536000>; 1514 sound-name-pr 1515 sound-name-prefix = "I2S1"; 1515 status = "dis 1516 status = "disabled"; 1516 }; 1517 }; 1517 1518 1518 tegra_i2s2: i2s@702d1 1519 tegra_i2s2: i2s@702d1100 { 1519 compatible = 1520 compatible = "nvidia,tegra210-i2s"; 1520 reg = <0x702d 1521 reg = <0x702d1100 0x100>; 1521 clocks = <&te 1522 clocks = <&tegra_car TEGRA210_CLK_I2S1>, 1522 <&te 1523 <&tegra_car TEGRA210_CLK_I2S1_SYNC>; 1523 clock-names = 1524 clock-names = "i2s", "sync_input"; 1524 assigned-cloc 1525 assigned-clocks = <&tegra_car TEGRA210_CLK_I2S1>; 1525 assigned-cloc 1526 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 1526 assigned-cloc 1527 assigned-clock-rates = <1536000>; 1527 sound-name-pr 1528 sound-name-prefix = "I2S2"; 1528 status = "dis 1529 status = "disabled"; 1529 }; 1530 }; 1530 1531 1531 tegra_i2s3: i2s@702d1 1532 tegra_i2s3: i2s@702d1200 { 1532 compatible = 1533 compatible = "nvidia,tegra210-i2s"; 1533 reg = <0x702d 1534 reg = <0x702d1200 0x100>; 1534 clocks = <&te 1535 clocks = <&tegra_car TEGRA210_CLK_I2S2>, 1535 <&te 1536 <&tegra_car TEGRA210_CLK_I2S2_SYNC>; 1536 clock-names = 1537 clock-names = "i2s", "sync_input"; 1537 assigned-cloc 1538 assigned-clocks = <&tegra_car TEGRA210_CLK_I2S2>; 1538 assigned-cloc 1539 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 1539 assigned-cloc 1540 assigned-clock-rates = <1536000>; 1540 sound-name-pr 1541 sound-name-prefix = "I2S3"; 1541 status = "dis 1542 status = "disabled"; 1542 }; 1543 }; 1543 1544 1544 tegra_i2s4: i2s@702d1 1545 tegra_i2s4: i2s@702d1300 { 1545 compatible = 1546 compatible = "nvidia,tegra210-i2s"; 1546 reg = <0x702d 1547 reg = <0x702d1300 0x100>; 1547 clocks = <&te 1548 clocks = <&tegra_car TEGRA210_CLK_I2S3>, 1548 <&te 1549 <&tegra_car TEGRA210_CLK_I2S3_SYNC>; 1549 clock-names = 1550 clock-names = "i2s", "sync_input"; 1550 assigned-cloc 1551 assigned-clocks = <&tegra_car TEGRA210_CLK_I2S3>; 1551 assigned-cloc 1552 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 1552 assigned-cloc 1553 assigned-clock-rates = <1536000>; 1553 sound-name-pr 1554 sound-name-prefix = "I2S4"; 1554 status = "dis 1555 status = "disabled"; 1555 }; 1556 }; 1556 1557 1557 tegra_i2s5: i2s@702d1 1558 tegra_i2s5: i2s@702d1400 { 1558 compatible = 1559 compatible = "nvidia,tegra210-i2s"; 1559 reg = <0x702d 1560 reg = <0x702d1400 0x100>; 1560 clocks = <&te 1561 clocks = <&tegra_car TEGRA210_CLK_I2S4>, 1561 <&te 1562 <&tegra_car TEGRA210_CLK_I2S4_SYNC>; 1562 clock-names = 1563 clock-names = "i2s", "sync_input"; 1563 assigned-cloc 1564 assigned-clocks = <&tegra_car TEGRA210_CLK_I2S4>; 1564 assigned-cloc 1565 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 1565 assigned-cloc 1566 assigned-clock-rates = <1536000>; 1566 sound-name-pr 1567 sound-name-prefix = "I2S5"; 1567 status = "dis 1568 status = "disabled"; 1568 }; 1569 }; 1569 1570 1570 tegra_sfc1: sfc@702d2 1571 tegra_sfc1: sfc@702d2000 { 1571 compatible = 1572 compatible = "nvidia,tegra210-sfc"; 1572 reg = <0x702d 1573 reg = <0x702d2000 0x200>; 1573 sound-name-pr 1574 sound-name-prefix = "SFC1"; 1574 status = "dis 1575 status = "disabled"; 1575 }; 1576 }; 1576 1577 1577 tegra_sfc2: sfc@702d2 1578 tegra_sfc2: sfc@702d2200 { 1578 compatible = 1579 compatible = "nvidia,tegra210-sfc"; 1579 reg = <0x702d 1580 reg = <0x702d2200 0x200>; 1580 sound-name-pr 1581 sound-name-prefix = "SFC2"; 1581 status = "dis 1582 status = "disabled"; 1582 }; 1583 }; 1583 1584 1584 tegra_sfc3: sfc@702d2 1585 tegra_sfc3: sfc@702d2400 { 1585 compatible = 1586 compatible = "nvidia,tegra210-sfc"; 1586 reg = <0x702d 1587 reg = <0x702d2400 0x200>; 1587 sound-name-pr 1588 sound-name-prefix = "SFC3"; 1588 status = "dis 1589 status = "disabled"; 1589 }; 1590 }; 1590 1591 1591 tegra_sfc4: sfc@702d2 1592 tegra_sfc4: sfc@702d2600 { 1592 compatible = 1593 compatible = "nvidia,tegra210-sfc"; 1593 reg = <0x702d 1594 reg = <0x702d2600 0x200>; 1594 sound-name-pr 1595 sound-name-prefix = "SFC4"; 1595 status = "dis 1596 status = "disabled"; 1596 }; 1597 }; 1597 1598 1598 tegra_amx1: amx@702d3 1599 tegra_amx1: amx@702d3000 { 1599 compatible = 1600 compatible = "nvidia,tegra210-amx"; 1600 reg = <0x702d 1601 reg = <0x702d3000 0x100>; 1601 sound-name-pr 1602 sound-name-prefix = "AMX1"; 1602 status = "dis 1603 status = "disabled"; 1603 }; 1604 }; 1604 1605 1605 tegra_amx2: amx@702d3 1606 tegra_amx2: amx@702d3100 { 1606 compatible = 1607 compatible = "nvidia,tegra210-amx"; 1607 reg = <0x702d 1608 reg = <0x702d3100 0x100>; 1608 sound-name-pr 1609 sound-name-prefix = "AMX2"; 1609 status = "dis 1610 status = "disabled"; 1610 }; 1611 }; 1611 1612 1612 tegra_adx1: adx@702d3 1613 tegra_adx1: adx@702d3800 { 1613 compatible = 1614 compatible = "nvidia,tegra210-adx"; 1614 reg = <0x702d 1615 reg = <0x702d3800 0x100>; 1615 sound-name-pr 1616 sound-name-prefix = "ADX1"; 1616 status = "dis 1617 status = "disabled"; 1617 }; 1618 }; 1618 1619 1619 tegra_adx2: adx@702d3 1620 tegra_adx2: adx@702d3900 { 1620 compatible = 1621 compatible = "nvidia,tegra210-adx"; 1621 reg = <0x702d 1622 reg = <0x702d3900 0x100>; 1622 sound-name-pr 1623 sound-name-prefix = "ADX2"; 1623 status = "dis 1624 status = "disabled"; 1624 }; 1625 }; 1625 1626 1626 tegra_dmic1: dmic@702 1627 tegra_dmic1: dmic@702d4000 { 1627 compatible = 1628 compatible = "nvidia,tegra210-dmic"; 1628 reg = <0x702d 1629 reg = <0x702d4000 0x100>; 1629 clocks = <&te 1630 clocks = <&tegra_car TEGRA210_CLK_DMIC1>; 1630 clock-names = 1631 clock-names = "dmic"; 1631 assigned-cloc 1632 assigned-clocks = <&tegra_car TEGRA210_CLK_DMIC1>; 1632 assigned-cloc 1633 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 1633 assigned-cloc 1634 assigned-clock-rates = <3072000>; 1634 sound-name-pr 1635 sound-name-prefix = "DMIC1"; 1635 status = "dis 1636 status = "disabled"; 1636 }; 1637 }; 1637 1638 1638 tegra_dmic2: dmic@702 1639 tegra_dmic2: dmic@702d4100 { 1639 compatible = 1640 compatible = "nvidia,tegra210-dmic"; 1640 reg = <0x702d 1641 reg = <0x702d4100 0x100>; 1641 clocks = <&te 1642 clocks = <&tegra_car TEGRA210_CLK_DMIC2>; 1642 clock-names = 1643 clock-names = "dmic"; 1643 assigned-cloc 1644 assigned-clocks = <&tegra_car TEGRA210_CLK_DMIC2>; 1644 assigned-cloc 1645 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 1645 assigned-cloc 1646 assigned-clock-rates = <3072000>; 1646 sound-name-pr 1647 sound-name-prefix = "DMIC2"; 1647 status = "dis 1648 status = "disabled"; 1648 }; 1649 }; 1649 1650 1650 tegra_dmic3: dmic@702 1651 tegra_dmic3: dmic@702d4200 { 1651 compatible = 1652 compatible = "nvidia,tegra210-dmic"; 1652 reg = <0x702d 1653 reg = <0x702d4200 0x100>; 1653 clocks = <&te 1654 clocks = <&tegra_car TEGRA210_CLK_DMIC3>; 1654 clock-names = 1655 clock-names = "dmic"; 1655 assigned-cloc 1656 assigned-clocks = <&tegra_car TEGRA210_CLK_DMIC3>; 1656 assigned-cloc 1657 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 1657 assigned-cloc 1658 assigned-clock-rates = <3072000>; 1658 sound-name-pr 1659 sound-name-prefix = "DMIC3"; 1659 status = "dis 1660 status = "disabled"; 1660 }; 1661 }; 1661 1662 1662 tegra_ope1: processin 1663 tegra_ope1: processing-engine@702d8000 { 1663 compatible = 1664 compatible = "nvidia,tegra210-ope"; 1664 reg = <0x702d 1665 reg = <0x702d8000 0x100>; 1665 #address-cell 1666 #address-cells = <1>; 1666 #size-cells = 1667 #size-cells = <1>; 1667 ranges; 1668 ranges; 1668 sound-name-pr 1669 sound-name-prefix = "OPE1"; 1669 status = "dis 1670 status = "disabled"; 1670 1671 1671 equalizer@702 1672 equalizer@702d8100 { 1672 compa 1673 compatible = "nvidia,tegra210-peq"; 1673 reg = 1674 reg = <0x702d8100 0x100>; 1674 }; 1675 }; 1675 1676 1676 dynamic-range 1677 dynamic-range-compressor@702d8200 { 1677 compa 1678 compatible = "nvidia,tegra210-mbdrc"; 1678 reg = 1679 reg = <0x702d8200 0x200>; 1679 }; 1680 }; 1680 }; 1681 }; 1681 1682 1682 tegra_ope2: processin 1683 tegra_ope2: processing-engine@702d8400 { 1683 compatible = 1684 compatible = "nvidia,tegra210-ope"; 1684 reg = <0x702d 1685 reg = <0x702d8400 0x100>; 1685 #address-cell 1686 #address-cells = <1>; 1686 #size-cells = 1687 #size-cells = <1>; 1687 ranges; 1688 ranges; 1688 sound-name-pr 1689 sound-name-prefix = "OPE2"; 1689 status = "dis 1690 status = "disabled"; 1690 1691 1691 equalizer@702 1692 equalizer@702d8500 { 1692 compa 1693 compatible = "nvidia,tegra210-peq"; 1693 reg = 1694 reg = <0x702d8500 0x100>; 1694 }; 1695 }; 1695 1696 1696 dynamic-range 1697 dynamic-range-compressor@702d8600 { 1697 compa 1698 compatible = "nvidia,tegra210-mbdrc"; 1698 reg = 1699 reg = <0x702d8600 0x200>; 1699 }; 1700 }; 1700 }; 1701 }; 1701 1702 1702 tegra_mvc1: mvc@702da 1703 tegra_mvc1: mvc@702da000 { 1703 compatible = 1704 compatible = "nvidia,tegra210-mvc"; 1704 reg = <0x702d 1705 reg = <0x702da000 0x200>; 1705 sound-name-pr 1706 sound-name-prefix = "MVC1"; 1706 status = "dis 1707 status = "disabled"; 1707 }; 1708 }; 1708 1709 1709 tegra_mvc2: mvc@702da 1710 tegra_mvc2: mvc@702da200 { 1710 compatible = 1711 compatible = "nvidia,tegra210-mvc"; 1711 reg = <0x702d 1712 reg = <0x702da200 0x200>; 1712 sound-name-pr 1713 sound-name-prefix = "MVC2"; 1713 status = "dis 1714 status = "disabled"; 1714 }; 1715 }; 1715 1716 1716 tegra_amixer: amixer@ 1717 tegra_amixer: amixer@702dbb00 { 1717 compatible = 1718 compatible = "nvidia,tegra210-amixer"; 1718 reg = <0x702d 1719 reg = <0x702dbb00 0x800>; 1719 sound-name-pr 1720 sound-name-prefix = "MIXER1"; 1720 status = "dis 1721 status = "disabled"; 1721 }; 1722 }; 1722 1723 1723 ports { 1724 ports { 1724 #address-cell 1725 #address-cells = <1>; 1725 #size-cells = 1726 #size-cells = <0>; 1726 1727 1727 port@0 { 1728 port@0 { 1728 reg = 1729 reg = <0x0>; 1729 1730 1730 xbar_ 1731 xbar_admaif1_ep: endpoint { 1731 1732 remote-endpoint = <&admaif1_ep>; 1732 }; 1733 }; 1733 }; 1734 }; 1734 1735 1735 port@1 { 1736 port@1 { 1736 reg = 1737 reg = <0x1>; 1737 1738 1738 xbar_ 1739 xbar_admaif2_ep: endpoint { 1739 1740 remote-endpoint = <&admaif2_ep>; 1740 }; 1741 }; 1741 }; 1742 }; 1742 1743 1743 port@2 { 1744 port@2 { 1744 reg = 1745 reg = <0x2>; 1745 1746 1746 xbar_ 1747 xbar_admaif3_ep: endpoint { 1747 1748 remote-endpoint = <&admaif3_ep>; 1748 }; 1749 }; 1749 }; 1750 }; 1750 1751 1751 port@3 { 1752 port@3 { 1752 reg = 1753 reg = <0x3>; 1753 1754 1754 xbar_ 1755 xbar_admaif4_ep: endpoint { 1755 1756 remote-endpoint = <&admaif4_ep>; 1756 }; 1757 }; 1757 }; 1758 }; 1758 1759 1759 port@4 { 1760 port@4 { 1760 reg = 1761 reg = <0x4>; 1761 xbar_ 1762 xbar_admaif5_ep: endpoint { 1762 1763 remote-endpoint = <&admaif5_ep>; 1763 }; 1764 }; 1764 }; 1765 }; 1765 port@5 { 1766 port@5 { 1766 reg = 1767 reg = <0x5>; 1767 1768 1768 xbar_ 1769 xbar_admaif6_ep: endpoint { 1769 1770 remote-endpoint = <&admaif6_ep>; 1770 }; 1771 }; 1771 }; 1772 }; 1772 1773 1773 port@6 { 1774 port@6 { 1774 reg = 1775 reg = <0x6>; 1775 1776 1776 xbar_ 1777 xbar_admaif7_ep: endpoint { 1777 1778 remote-endpoint = <&admaif7_ep>; 1778 }; 1779 }; 1779 }; 1780 }; 1780 1781 1781 port@7 { 1782 port@7 { 1782 reg = 1783 reg = <0x7>; 1783 1784 1784 xbar_ 1785 xbar_admaif8_ep: endpoint { 1785 1786 remote-endpoint = <&admaif8_ep>; 1786 }; 1787 }; 1787 }; 1788 }; 1788 1789 1789 port@8 { 1790 port@8 { 1790 reg = 1791 reg = <0x8>; 1791 1792 1792 xbar_ 1793 xbar_admaif9_ep: endpoint { 1793 1794 remote-endpoint = <&admaif9_ep>; 1794 }; 1795 }; 1795 }; 1796 }; 1796 1797 1797 port@9 { 1798 port@9 { 1798 reg = 1799 reg = <0x9>; 1799 1800 1800 xbar_ 1801 xbar_admaif10_ep: endpoint { 1801 1802 remote-endpoint = <&admaif10_ep>; 1802 }; 1803 }; 1803 }; 1804 }; 1804 }; 1805 }; 1805 }; 1806 }; 1806 1807 1807 adma: dma-controller@702e2000 1808 adma: dma-controller@702e2000 { 1808 compatible = "nvidia, 1809 compatible = "nvidia,tegra210-adma"; 1809 reg = <0x702e2000 0x2 1810 reg = <0x702e2000 0x2000>; 1810 interrupt-parent = <& 1811 interrupt-parent = <&agic>; 1811 interrupts = <GIC_SPI 1812 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 1812 <GIC_SPI 1813 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 1813 <GIC_SPI 1814 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 1814 <GIC_SPI 1815 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 1815 <GIC_SPI 1816 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 1816 <GIC_SPI 1817 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 1817 <GIC_SPI 1818 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 1818 <GIC_SPI 1819 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 1819 <GIC_SPI 1820 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 1820 <GIC_SPI 1821 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 1821 <GIC_SPI 1822 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 1822 <GIC_SPI 1823 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 1823 <GIC_SPI 1824 <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, 1824 <GIC_SPI 1825 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, 1825 <GIC_SPI 1826 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, 1826 <GIC_SPI 1827 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 1827 <GIC_SPI 1828 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 1828 <GIC_SPI 1829 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 1829 <GIC_SPI 1830 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 1830 <GIC_SPI 1831 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 1831 <GIC_SPI 1832 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 1832 <GIC_SPI 1833 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1833 #dma-cells = <1>; 1834 #dma-cells = <1>; 1834 clocks = <&tegra_car 1835 clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>; 1835 clock-names = "d_audi 1836 clock-names = "d_audio"; 1836 status = "disabled"; 1837 status = "disabled"; 1837 }; 1838 }; 1838 1839 1839 agic: interrupt-controller@70 1840 agic: interrupt-controller@702f9000 { 1840 compatible = "nvidia, 1841 compatible = "nvidia,tegra210-agic"; 1841 #interrupt-cells = <3 1842 #interrupt-cells = <3>; 1842 interrupt-controller; 1843 interrupt-controller; 1843 reg = <0x702f9000 0x1 1844 reg = <0x702f9000 0x1000>, 1844 <0x702fa000 0x2 1845 <0x702fa000 0x2000>; 1845 interrupts = <GIC_SPI 1846 interrupts = <GIC_SPI 102 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1846 clocks = <&tegra_car 1847 clocks = <&tegra_car TEGRA210_CLK_APE>; 1847 clock-names = "clk"; 1848 clock-names = "clk"; 1848 status = "disabled"; 1849 status = "disabled"; 1849 }; 1850 }; 1850 }; 1851 }; 1851 1852 1852 spi@70410000 { 1853 spi@70410000 { 1853 compatible = "nvidia,tegra210 1854 compatible = "nvidia,tegra210-qspi"; 1854 reg = <0x0 0x70410000 0x0 0x1 1855 reg = <0x0 0x70410000 0x0 0x1000>; 1855 interrupts = <GIC_SPI 10 IRQ_ 1856 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1856 #address-cells = <1>; 1857 #address-cells = <1>; 1857 #size-cells = <0>; 1858 #size-cells = <0>; 1858 clocks = <&tegra_car TEGRA210 1859 clocks = <&tegra_car TEGRA210_CLK_QSPI>, 1859 <&tegra_car TEGRA210 1860 <&tegra_car TEGRA210_CLK_QSPI_PM>; 1860 clock-names = "qspi", "qspi_o 1861 clock-names = "qspi", "qspi_out"; 1861 resets = <&tegra_car 211>; 1862 resets = <&tegra_car 211>; 1862 dmas = <&apbdma 5>, <&apbdma 1863 dmas = <&apbdma 5>, <&apbdma 5>; 1863 dma-names = "rx", "tx"; 1864 dma-names = "rx", "tx"; 1864 status = "disabled"; 1865 status = "disabled"; 1865 }; 1866 }; 1866 1867 1867 usb@7d000000 { 1868 usb@7d000000 { 1868 compatible = "nvidia,tegra210 1869 compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci"; 1869 reg = <0x0 0x7d000000 0x0 0x4 1870 reg = <0x0 0x7d000000 0x0 0x4000>; 1870 interrupts = <GIC_SPI 20 IRQ_ 1871 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1871 phy_type = "utmi"; 1872 phy_type = "utmi"; 1872 clocks = <&tegra_car TEGRA210 1873 clocks = <&tegra_car TEGRA210_CLK_USBD>; 1873 clock-names = "usb"; 1874 clock-names = "usb"; 1874 resets = <&tegra_car 22>; 1875 resets = <&tegra_car 22>; 1875 reset-names = "usb"; 1876 reset-names = "usb"; 1876 nvidia,phy = <&phy1>; 1877 nvidia,phy = <&phy1>; 1877 status = "disabled"; 1878 status = "disabled"; 1878 }; 1879 }; 1879 1880 1880 phy1: usb-phy@7d000000 { 1881 phy1: usb-phy@7d000000 { 1881 compatible = "nvidia,tegra210 1882 compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy"; 1882 reg = <0x0 0x7d000000 0x0 0x4 1883 reg = <0x0 0x7d000000 0x0 0x4000>, 1883 <0x0 0x7d000000 0x0 0x4 1884 <0x0 0x7d000000 0x0 0x4000>; 1884 phy_type = "utmi"; 1885 phy_type = "utmi"; 1885 clocks = <&tegra_car TEGRA210 1886 clocks = <&tegra_car TEGRA210_CLK_USBD>, 1886 <&tegra_car TEGRA210 1887 <&tegra_car TEGRA210_CLK_PLL_U>, 1887 <&tegra_car TEGRA210 1888 <&tegra_car TEGRA210_CLK_USBD>; 1888 clock-names = "reg", "pll_u", 1889 clock-names = "reg", "pll_u", "utmi-pads"; 1889 resets = <&tegra_car 22>, <&t 1890 resets = <&tegra_car 22>, <&tegra_car 22>; 1890 reset-names = "usb", "utmi-pa 1891 reset-names = "usb", "utmi-pads"; 1891 nvidia,hssync-start-delay = < 1892 nvidia,hssync-start-delay = <0>; 1892 nvidia,idle-wait-delay = <17> 1893 nvidia,idle-wait-delay = <17>; 1893 nvidia,elastic-limit = <16>; 1894 nvidia,elastic-limit = <16>; 1894 nvidia,term-range-adj = <6>; 1895 nvidia,term-range-adj = <6>; 1895 nvidia,xcvr-setup = <9>; 1896 nvidia,xcvr-setup = <9>; 1896 nvidia,xcvr-lsfslew = <0>; 1897 nvidia,xcvr-lsfslew = <0>; 1897 nvidia,xcvr-lsrslew = <3>; 1898 nvidia,xcvr-lsrslew = <3>; 1898 nvidia,hssquelch-level = <2>; 1899 nvidia,hssquelch-level = <2>; 1899 nvidia,hsdiscon-level = <5>; 1900 nvidia,hsdiscon-level = <5>; 1900 nvidia,xcvr-hsslew = <12>; 1901 nvidia,xcvr-hsslew = <12>; 1901 nvidia,has-utmi-pad-registers 1902 nvidia,has-utmi-pad-registers; 1902 status = "disabled"; 1903 status = "disabled"; 1903 }; 1904 }; 1904 1905 1905 usb@7d004000 { 1906 usb@7d004000 { 1906 compatible = "nvidia,tegra210 1907 compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci"; 1907 reg = <0x0 0x7d004000 0x0 0x4 1908 reg = <0x0 0x7d004000 0x0 0x4000>; 1908 interrupts = <GIC_SPI 21 IRQ_ 1909 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1909 phy_type = "utmi"; 1910 phy_type = "utmi"; 1910 clocks = <&tegra_car TEGRA210 1911 clocks = <&tegra_car TEGRA210_CLK_USB2>; 1911 clock-names = "usb"; 1912 clock-names = "usb"; 1912 resets = <&tegra_car 58>; 1913 resets = <&tegra_car 58>; 1913 reset-names = "usb"; 1914 reset-names = "usb"; 1914 nvidia,phy = <&phy2>; 1915 nvidia,phy = <&phy2>; 1915 status = "disabled"; 1916 status = "disabled"; 1916 }; 1917 }; 1917 1918 1918 phy2: usb-phy@7d004000 { 1919 phy2: usb-phy@7d004000 { 1919 compatible = "nvidia,tegra210 1920 compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy"; 1920 reg = <0x0 0x7d004000 0x0 0x4 1921 reg = <0x0 0x7d004000 0x0 0x4000>, 1921 <0x0 0x7d000000 0x0 0x4 1922 <0x0 0x7d000000 0x0 0x4000>; 1922 phy_type = "utmi"; 1923 phy_type = "utmi"; 1923 clocks = <&tegra_car TEGRA210 1924 clocks = <&tegra_car TEGRA210_CLK_USB2>, 1924 <&tegra_car TEGRA210 1925 <&tegra_car TEGRA210_CLK_PLL_U>, 1925 <&tegra_car TEGRA210 1926 <&tegra_car TEGRA210_CLK_USBD>; 1926 clock-names = "reg", "pll_u", 1927 clock-names = "reg", "pll_u", "utmi-pads"; 1927 resets = <&tegra_car 58>, <&t 1928 resets = <&tegra_car 58>, <&tegra_car 22>; 1928 reset-names = "usb", "utmi-pa 1929 reset-names = "usb", "utmi-pads"; 1929 nvidia,hssync-start-delay = < 1930 nvidia,hssync-start-delay = <0>; 1930 nvidia,idle-wait-delay = <17> 1931 nvidia,idle-wait-delay = <17>; 1931 nvidia,elastic-limit = <16>; 1932 nvidia,elastic-limit = <16>; 1932 nvidia,term-range-adj = <6>; 1933 nvidia,term-range-adj = <6>; 1933 nvidia,xcvr-setup = <9>; 1934 nvidia,xcvr-setup = <9>; 1934 nvidia,xcvr-lsfslew = <0>; 1935 nvidia,xcvr-lsfslew = <0>; 1935 nvidia,xcvr-lsrslew = <3>; 1936 nvidia,xcvr-lsrslew = <3>; 1936 nvidia,hssquelch-level = <2>; 1937 nvidia,hssquelch-level = <2>; 1937 nvidia,hsdiscon-level = <5>; 1938 nvidia,hsdiscon-level = <5>; 1938 nvidia,xcvr-hsslew = <12>; 1939 nvidia,xcvr-hsslew = <12>; 1939 status = "disabled"; 1940 status = "disabled"; 1940 }; 1941 }; 1941 1942 1942 cpus { 1943 cpus { 1943 #address-cells = <1>; 1944 #address-cells = <1>; 1944 #size-cells = <0>; 1945 #size-cells = <0>; 1945 1946 1946 cpu@0 { 1947 cpu@0 { 1947 device_type = "cpu"; 1948 device_type = "cpu"; 1948 compatible = "arm,cor 1949 compatible = "arm,cortex-a57"; 1949 reg = <0>; 1950 reg = <0>; 1950 clocks = <&tegra_car 1951 clocks = <&tegra_car TEGRA210_CLK_CCLK_G>, 1951 <&tegra_car 1952 <&tegra_car TEGRA210_CLK_PLL_X>, 1952 <&tegra_car 1953 <&tegra_car TEGRA210_CLK_PLL_P_OUT4>, 1953 <&dfll>; 1954 <&dfll>; 1954 clock-names = "cpu_g" 1955 clock-names = "cpu_g", "pll_x", "pll_p", "dfll"; 1955 clock-latency = <3000 1956 clock-latency = <300000>; 1956 cpu-idle-states = <&C 1957 cpu-idle-states = <&CPU_SLEEP>; 1957 next-level-cache = <& 1958 next-level-cache = <&L2>; 1958 }; 1959 }; 1959 1960 1960 cpu@1 { 1961 cpu@1 { 1961 device_type = "cpu"; 1962 device_type = "cpu"; 1962 compatible = "arm,cor 1963 compatible = "arm,cortex-a57"; 1963 reg = <1>; 1964 reg = <1>; 1964 cpu-idle-states = <&C 1965 cpu-idle-states = <&CPU_SLEEP>; 1965 next-level-cache = <& 1966 next-level-cache = <&L2>; 1966 }; 1967 }; 1967 1968 1968 cpu@2 { 1969 cpu@2 { 1969 device_type = "cpu"; 1970 device_type = "cpu"; 1970 compatible = "arm,cor 1971 compatible = "arm,cortex-a57"; 1971 reg = <2>; 1972 reg = <2>; 1972 cpu-idle-states = <&C 1973 cpu-idle-states = <&CPU_SLEEP>; 1973 next-level-cache = <& 1974 next-level-cache = <&L2>; 1974 }; 1975 }; 1975 1976 1976 cpu@3 { 1977 cpu@3 { 1977 device_type = "cpu"; 1978 device_type = "cpu"; 1978 compatible = "arm,cor 1979 compatible = "arm,cortex-a57"; 1979 reg = <3>; 1980 reg = <3>; 1980 cpu-idle-states = <&C 1981 cpu-idle-states = <&CPU_SLEEP>; 1981 next-level-cache = <& 1982 next-level-cache = <&L2>; 1982 }; 1983 }; 1983 1984 1984 idle-states { 1985 idle-states { 1985 entry-method = "psci" 1986 entry-method = "psci"; 1986 1987 1987 CPU_SLEEP: cpu-sleep 1988 CPU_SLEEP: cpu-sleep { 1988 compatible = 1989 compatible = "arm,idle-state"; 1989 arm,psci-susp 1990 arm,psci-suspend-param = <0x40000007>; 1990 entry-latency 1991 entry-latency-us = <100>; 1991 exit-latency- 1992 exit-latency-us = <30>; 1992 min-residency 1993 min-residency-us = <1000>; 1993 wakeup-latenc 1994 wakeup-latency-us = <130>; 1994 idle-state-na 1995 idle-state-name = "cpu-sleep"; 1995 status = "dis 1996 status = "disabled"; 1996 }; 1997 }; 1997 }; 1998 }; 1998 1999 1999 L2: l2-cache { 2000 L2: l2-cache { 2000 compatible = "cache"; 2001 compatible = "cache"; 2001 cache-level = <2>; 2002 cache-level = <2>; 2002 cache-unified; << 2003 }; 2003 }; 2004 }; 2004 }; 2005 2005 2006 pmu { 2006 pmu { 2007 compatible = "arm,cortex-a57- !! 2007 compatible = "arm,armv8-pmuv3"; 2008 interrupts = <GIC_SPI 144 IRQ 2008 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 2009 <GIC_SPI 145 IRQ 2009 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 2010 <GIC_SPI 146 IRQ 2010 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 2011 <GIC_SPI 147 IRQ 2011 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 2012 interrupt-affinity = <&{/cpus 2012 interrupt-affinity = <&{/cpus/cpu@0} &{/cpus/cpu@1} 2013 &{/cpus 2013 &{/cpus/cpu@2} &{/cpus/cpu@3}>; 2014 }; 2014 }; 2015 2015 2016 sound { 2016 sound { 2017 status = "disabled"; 2017 status = "disabled"; 2018 2018 2019 clocks = <&tegra_car TEGRA210 2019 clocks = <&tegra_car TEGRA210_CLK_PLL_A>, 2020 <&tegra_car TEGRA210 2020 <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 2021 clock-names = "pll_a", "plla_ 2021 clock-names = "pll_a", "plla_out0"; 2022 2022 2023 assigned-clocks = <&tegra_car 2023 assigned-clocks = <&tegra_car TEGRA210_CLK_PLL_A>, 2024 <&tegra_car 2024 <&tegra_car TEGRA210_CLK_PLL_A_OUT0>, 2025 <&tegra_car 2025 <&tegra_car TEGRA210_CLK_EXTERN1>; 2026 assigned-clock-parents = <0>, 2026 assigned-clock-parents = <0>, <0>, <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 2027 assigned-clock-rates = <36864 2027 assigned-clock-rates = <368640000>, <49152000>, <12288000>; 2028 }; 2028 }; 2029 2029 2030 thermal-zones { 2030 thermal-zones { 2031 cpu-thermal { 2031 cpu-thermal { 2032 polling-delay-passive 2032 polling-delay-passive = <1000>; 2033 polling-delay = <0>; 2033 polling-delay = <0>; 2034 2034 2035 thermal-sensors = 2035 thermal-sensors = 2036 <&soctherm TE 2036 <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>; 2037 2037 2038 trips { 2038 trips { 2039 cpu-shutdown- 2039 cpu-shutdown-trip { 2040 tempe 2040 temperature = <102500>; 2041 hyste 2041 hysteresis = <0>; 2042 type 2042 type = "critical"; 2043 }; 2043 }; 2044 2044 2045 cpu_throttle_ 2045 cpu_throttle_trip: throttle-trip { 2046 tempe 2046 temperature = <98500>; 2047 hyste 2047 hysteresis = <1000>; 2048 type 2048 type = "hot"; 2049 }; 2049 }; 2050 }; 2050 }; 2051 2051 2052 cooling-maps { 2052 cooling-maps { 2053 map0 { 2053 map0 { 2054 trip 2054 trip = <&cpu_throttle_trip>; 2055 cooli 2055 cooling-device = <&throttle_heavy 1 1>; 2056 }; 2056 }; 2057 }; 2057 }; 2058 }; 2058 }; 2059 2059 2060 mem-thermal { 2060 mem-thermal { 2061 polling-delay-passive 2061 polling-delay-passive = <0>; 2062 polling-delay = <0>; 2062 polling-delay = <0>; 2063 2063 2064 thermal-sensors = 2064 thermal-sensors = 2065 <&soctherm TE 2065 <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>; 2066 2066 2067 trips { 2067 trips { 2068 dram_nominal: 2068 dram_nominal: mem-nominal-trip { 2069 tempe 2069 temperature = <50000>; 2070 hyste 2070 hysteresis = <1000>; 2071 type 2071 type = "passive"; 2072 }; 2072 }; 2073 2073 2074 dram_throttle 2074 dram_throttle: mem-throttle-trip { 2075 tempe 2075 temperature = <70000>; 2076 hyste 2076 hysteresis = <1000>; 2077 type 2077 type = "active"; 2078 }; 2078 }; 2079 2079 2080 mem-hot-trip 2080 mem-hot-trip { 2081 tempe 2081 temperature = <100000>; 2082 hyste 2082 hysteresis = <1000>; 2083 type 2083 type = "hot"; 2084 }; 2084 }; 2085 2085 2086 mem-shutdown- 2086 mem-shutdown-trip { 2087 tempe 2087 temperature = <103000>; 2088 hyste 2088 hysteresis = <0>; 2089 type 2089 type = "critical"; 2090 }; 2090 }; 2091 }; 2091 }; 2092 2092 2093 cooling-maps { 2093 cooling-maps { 2094 dram-passive 2094 dram-passive { 2095 cooli 2095 cooling-device = <&emc 0 0>; 2096 trip 2096 trip = <&dram_nominal>; 2097 }; 2097 }; 2098 2098 2099 dram-active { 2099 dram-active { 2100 cooli 2100 cooling-device = <&emc 1 1>; 2101 trip 2101 trip = <&dram_throttle>; 2102 }; 2102 }; 2103 }; 2103 }; 2104 }; 2104 }; 2105 2105 2106 gpu-thermal { 2106 gpu-thermal { 2107 polling-delay-passive 2107 polling-delay-passive = <1000>; 2108 polling-delay = <0>; 2108 polling-delay = <0>; 2109 2109 2110 thermal-sensors = 2110 thermal-sensors = 2111 <&soctherm TE 2111 <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>; 2112 2112 2113 trips { 2113 trips { 2114 gpu-shutdown- 2114 gpu-shutdown-trip { 2115 tempe 2115 temperature = <103000>; 2116 hyste 2116 hysteresis = <0>; 2117 type 2117 type = "critical"; 2118 }; 2118 }; 2119 2119 2120 gpu_throttle_ 2120 gpu_throttle_trip: throttle-trip { 2121 tempe 2121 temperature = <100000>; 2122 hyste 2122 hysteresis = <1000>; 2123 type 2123 type = "hot"; 2124 }; 2124 }; 2125 }; 2125 }; 2126 2126 2127 cooling-maps { 2127 cooling-maps { 2128 map0 { 2128 map0 { 2129 trip 2129 trip = <&gpu_throttle_trip>; 2130 cooli 2130 cooling-device = <&throttle_heavy 1 1>; 2131 }; 2131 }; 2132 }; 2132 }; 2133 }; 2133 }; 2134 2134 2135 pllx-thermal { 2135 pllx-thermal { 2136 polling-delay-passive 2136 polling-delay-passive = <0>; 2137 polling-delay = <0>; 2137 polling-delay = <0>; 2138 2138 2139 thermal-sensors = 2139 thermal-sensors = 2140 <&soctherm TE 2140 <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>; 2141 2141 2142 trips { 2142 trips { 2143 pllx-shutdown 2143 pllx-shutdown-trip { 2144 tempe 2144 temperature = <103000>; 2145 hyste 2145 hysteresis = <0>; 2146 type 2146 type = "critical"; 2147 }; 2147 }; 2148 2148 2149 pllx-throttle 2149 pllx-throttle-trip { 2150 tempe 2150 temperature = <100000>; 2151 hyste 2151 hysteresis = <1000>; 2152 type 2152 type = "hot"; 2153 }; 2153 }; 2154 }; 2154 }; 2155 2155 2156 cooling-maps { 2156 cooling-maps { 2157 /* 2157 /* 2158 * There are 2158 * There are currently no cooling maps, 2159 * because th 2159 * because there are no cooling devices. 2160 */ 2160 */ 2161 }; 2161 }; 2162 }; 2162 }; 2163 }; 2163 }; 2164 2164 2165 timer { 2165 timer { 2166 compatible = "arm,armv8-timer 2166 compatible = "arm,armv8-timer"; 2167 interrupts = <GIC_PPI 13 2167 interrupts = <GIC_PPI 13 2168 (GIC_CPU_MASK 2168 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2169 <GIC_PPI 14 2169 <GIC_PPI 14 2170 (GIC_CPU_MASK 2170 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2171 <GIC_PPI 11 2171 <GIC_PPI 11 2172 (GIC_CPU_MASK 2172 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2173 <GIC_PPI 10 2173 <GIC_PPI 10 2174 (GIC_CPU_MASK 2174 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 2175 interrupt-parent = <&gic>; 2175 interrupt-parent = <&gic>; 2176 arm,no-tick-in-suspend; 2176 arm,no-tick-in-suspend; 2177 }; 2177 }; 2178 }; 2178 };
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