1 // SPDX-License-Identifier: GPL-2.0-only <<
2 /* 1 /*
3 * Copyright (c) 2017, The Linux Foundation. A 2 * Copyright (c) 2017, The Linux Foundation. All rights reserved.
>> 3 *
>> 4 * This program is free software; you can redistribute it and/or modify
>> 5 * it under the terms of the GNU General Public License version 2 and
>> 6 * only version 2 as published by the Free Software Foundation.
>> 7 *
>> 8 * This program is distributed in the hope that it will be useful,
>> 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> 11 * GNU General Public License for more details.
4 */ 12 */
5 13
6 #include <dt-bindings/interrupt-controller/arm 14 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,gcc-ipq8074.h 15 #include <dt-bindings/clock/qcom,gcc-ipq8074.h>
8 16
9 / { 17 / {
10 #address-cells = <2>; <<
11 #size-cells = <2>; <<
12 <<
13 model = "Qualcomm Technologies, Inc. I 18 model = "Qualcomm Technologies, Inc. IPQ8074";
14 compatible = "qcom,ipq8074"; 19 compatible = "qcom,ipq8074";
15 interrupt-parent = <&intc>; <<
16 <<
17 clocks { <<
18 sleep_clk: sleep_clk { <<
19 compatible = "fixed-cl <<
20 clock-frequency = <327 <<
21 #clock-cells = <0>; <<
22 }; <<
23 <<
24 xo: xo { <<
25 compatible = "fixed-cl <<
26 clock-frequency = <192 <<
27 #clock-cells = <0>; <<
28 }; <<
29 }; <<
30 <<
31 cpus { <<
32 #address-cells = <1>; <<
33 #size-cells = <0>; <<
34 <<
35 CPU0: cpu@0 { <<
36 device_type = "cpu"; <<
37 compatible = "arm,cort <<
38 reg = <0x0>; <<
39 next-level-cache = <&L <<
40 enable-method = "psci" <<
41 }; <<
42 <<
43 CPU1: cpu@1 { <<
44 device_type = "cpu"; <<
45 compatible = "arm,cort <<
46 enable-method = "psci" <<
47 reg = <0x1>; <<
48 next-level-cache = <&L <<
49 }; <<
50 <<
51 CPU2: cpu@2 { <<
52 device_type = "cpu"; <<
53 compatible = "arm,cort <<
54 enable-method = "psci" <<
55 reg = <0x2>; <<
56 next-level-cache = <&L <<
57 }; <<
58 <<
59 CPU3: cpu@3 { <<
60 device_type = "cpu"; <<
61 compatible = "arm,cort <<
62 enable-method = "psci" <<
63 reg = <0x3>; <<
64 next-level-cache = <&L <<
65 }; <<
66 <<
67 L2_0: l2-cache { <<
68 compatible = "cache"; <<
69 cache-level = <2>; <<
70 cache-unified; <<
71 }; <<
72 }; <<
73 <<
74 pmu { <<
75 compatible = "arm,cortex-a53-p <<
76 interrupts = <GIC_PPI 7 (GIC_C <<
77 }; <<
78 <<
79 psci { <<
80 compatible = "arm,psci-1.0"; <<
81 method = "smc"; <<
82 }; <<
83 <<
84 reserved-memory { <<
85 #address-cells = <2>; <<
86 #size-cells = <2>; <<
87 ranges; <<
88 <<
89 bootloader@4a600000 { <<
90 reg = <0x0 0x4a600000 <<
91 no-map; <<
92 }; <<
93 <<
94 sbl@4aa00000 { <<
95 reg = <0x0 0x4aa00000 <<
96 no-map; <<
97 }; <<
98 20
99 smem@4ab00000 { !! 21 soc: soc {
100 compatible = "qcom,sme !! 22 #address-cells = <0x1>;
101 reg = <0x0 0x4ab00000 !! 23 #size-cells = <0x1>;
102 no-map; <<
103 <<
104 hwlocks = <&tcsr_mutex <<
105 }; <<
106 <<
107 memory@4ac00000 { <<
108 reg = <0x0 0x4ac00000 <<
109 no-map; <<
110 }; <<
111 }; <<
112 <<
113 firmware { <<
114 scm { <<
115 compatible = "qcom,scm <<
116 qcom,dload-mode = <&tc <<
117 }; <<
118 }; <<
119 <<
120 soc: soc@0 { <<
121 #address-cells = <1>; <<
122 #size-cells = <1>; <<
123 ranges = <0 0 0 0xffffffff>; 24 ranges = <0 0 0 0xffffffff>;
124 compatible = "simple-bus"; 25 compatible = "simple-bus";
125 26
126 ssphy_1: phy@58000 { <<
127 compatible = "qcom,ipq <<
128 reg = <0x00058000 0x10 <<
129 <<
130 clocks = <&gcc GCC_USB <<
131 <&xo>, <<
132 <&gcc GCC_USB <<
133 <&gcc GCC_USB <<
134 clock-names = "aux", <<
135 "ref", <<
136 "cfg_ahb <<
137 "pipe"; <<
138 clock-output-names = " <<
139 #clock-cells = <0>; <<
140 #phy-cells = <0>; <<
141 <<
142 resets = <&gcc GCC_USB <<
143 <&gcc GCC_USB <<
144 reset-names = "phy", <<
145 "phy_phy <<
146 <<
147 status = "disabled"; <<
148 }; <<
149 <<
150 qusb_phy_1: phy@59000 { <<
151 compatible = "qcom,ipq <<
152 reg = <0x00059000 0x18 <<
153 #phy-cells = <0>; <<
154 <<
155 clocks = <&gcc GCC_USB <<
156 <&xo>; <<
157 clock-names = "cfg_ahb <<
158 <<
159 resets = <&gcc GCC_QUS <<
160 status = "disabled"; <<
161 }; <<
162 <<
163 ssphy_0: phy@78000 { <<
164 compatible = "qcom,ipq <<
165 reg = <0x00078000 0x10 <<
166 <<
167 clocks = <&gcc GCC_USB <<
168 <&xo>, <<
169 <&gcc GCC_USB <<
170 <&gcc GCC_USB <<
171 clock-names = "aux", <<
172 "ref", <<
173 "cfg_ahb <<
174 "pipe"; <<
175 clock-output-names = " <<
176 #clock-cells = <0>; <<
177 #phy-cells = <0>; <<
178 <<
179 resets = <&gcc GCC_USB <<
180 <&gcc GCC_USB <<
181 reset-names = "phy", <<
182 "phy_phy <<
183 <<
184 status = "disabled"; <<
185 }; <<
186 <<
187 qusb_phy_0: phy@79000 { <<
188 compatible = "qcom,ipq <<
189 reg = <0x00079000 0x18 <<
190 #phy-cells = <0>; <<
191 <<
192 clocks = <&gcc GCC_USB <<
193 <&xo>; <<
194 clock-names = "cfg_ahb <<
195 <<
196 resets = <&gcc GCC_QUS <<
197 status = "disabled"; <<
198 }; <<
199 <<
200 pcie_qmp0: phy@84000 { <<
201 compatible = "qcom,ipq <<
202 reg = <0x00084000 0x10 <<
203 <<
204 clocks = <&gcc GCC_PCI <<
205 <&gcc GCC_PCI <<
206 <&gcc GCC_PCI <<
207 clock-names = "aux", <<
208 "cfg_ahb <<
209 "pipe"; <<
210 <<
211 clock-output-names = " <<
212 #clock-cells = <0>; <<
213 <<
214 #phy-cells = <0>; <<
215 <<
216 resets = <&gcc GCC_PCI <<
217 <&gcc GCC_PCI <<
218 reset-names = "phy", <<
219 "common" <<
220 status = "disabled"; <<
221 }; <<
222 <<
223 pcie_qmp1: phy@8e000 { <<
224 compatible = "qcom,ipq <<
225 reg = <0x0008e000 0x10 <<
226 <<
227 clocks = <&gcc GCC_PCI <<
228 <&gcc GCC_PCI <<
229 <&gcc GCC_PCI <<
230 clock-names = "aux", <<
231 "cfg_ahb <<
232 "pipe"; <<
233 <<
234 clock-output-names = " <<
235 #clock-cells = <0>; <<
236 <<
237 #phy-cells = <0>; <<
238 <<
239 resets = <&gcc GCC_PCI <<
240 <&gcc GCC_PCI <<
241 reset-names = "phy", <<
242 "common" <<
243 status = "disabled"; <<
244 }; <<
245 <<
246 mdio: mdio@90000 { <<
247 compatible = "qcom,ipq <<
248 reg = <0x00090000 0x64 <<
249 #address-cells = <1>; <<
250 #size-cells = <0>; <<
251 <<
252 clocks = <&gcc GCC_MDI <<
253 clock-names = "gcc_mdi <<
254 <<
255 clock-frequency = <625 <<
256 <<
257 status = "disabled"; <<
258 }; <<
259 <<
260 qfprom: efuse@a4000 { <<
261 compatible = "qcom,ipq <<
262 reg = <0x000a4000 0x20 <<
263 #address-cells = <1>; <<
264 #size-cells = <1>; <<
265 }; <<
266 <<
267 prng: rng@e3000 { <<
268 compatible = "qcom,prn <<
269 reg = <0x000e3000 0x10 <<
270 clocks = <&gcc GCC_PRN <<
271 clock-names = "core"; <<
272 status = "disabled"; <<
273 }; <<
274 <<
275 tsens: thermal-sensor@4a9000 { <<
276 compatible = "qcom,ipq <<
277 reg = <0x4a9000 0x1000 <<
278 <0x4a8000 0x1000 <<
279 interrupts = <GIC_SPI <<
280 interrupt-names = "com <<
281 #qcom,sensors = <16>; <<
282 #thermal-sensor-cells <<
283 }; <<
284 <<
285 cryptobam: dma-controller@7040 <<
286 compatible = "qcom,bam <<
287 reg = <0x00704000 0x20 <<
288 interrupts = <GIC_SPI <<
289 clocks = <&gcc GCC_CRY <<
290 clock-names = "bam_clk <<
291 #dma-cells = <1>; <<
292 qcom,ee = <1>; <<
293 qcom,controlled-remote <<
294 status = "disabled"; <<
295 }; <<
296 <<
297 crypto: crypto@73a000 { <<
298 compatible = "qcom,cry <<
299 reg = <0x0073a000 0x60 <<
300 clocks = <&gcc GCC_CRY <<
301 <&gcc GCC_CRY <<
302 <&gcc GCC_CRY <<
303 clock-names = "iface", <<
304 dmas = <&cryptobam 2>, <<
305 dma-names = "rx", "tx" <<
306 status = "disabled"; <<
307 }; <<
308 <<
309 tlmm: pinctrl@1000000 { 27 tlmm: pinctrl@1000000 {
310 compatible = "qcom,ipq 28 compatible = "qcom,ipq8074-pinctrl";
311 reg = <0x01000000 0x30 !! 29 reg = <0x1000000 0x300000>;
312 interrupts = <GIC_SPI 30 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
313 gpio-controller; 31 gpio-controller;
314 gpio-ranges = <&tlmm 0 !! 32 #gpio-cells = <0x2>;
315 #gpio-cells = <2>; <<
316 interrupt-controller; 33 interrupt-controller;
317 #interrupt-cells = <2> !! 34 #interrupt-cells = <0x2>;
318 35
319 serial_4_pins: serial4 !! 36 serial_4_pins: serial4-pinmux {
320 pins = "gpio23 37 pins = "gpio23", "gpio24";
321 function = "bl 38 function = "blsp4_uart1";
322 drive-strength 39 drive-strength = <8>;
323 bias-disable; 40 bias-disable;
324 }; 41 };
325 42
326 serial_5_pins: serial5 !! 43 i2c_0_pins: i2c-0-pinmux {
327 pins = "gpio9" <<
328 function = "bl <<
329 drive-strength <<
330 bias-disable; <<
331 }; <<
332 <<
333 i2c_0_pins: i2c-0-stat <<
334 pins = "gpio42 44 pins = "gpio42", "gpio43";
335 function = "bl 45 function = "blsp1_i2c";
336 drive-strength 46 drive-strength = <8>;
337 bias-disable; 47 bias-disable;
338 }; 48 };
339 49
340 spi_0_pins: spi-0-stat !! 50 spi_0_pins: spi-0-pins {
341 pins = "gpio38 51 pins = "gpio38", "gpio39", "gpio40", "gpio41";
342 function = "bl 52 function = "blsp0_spi";
343 drive-strength 53 drive-strength = <8>;
344 bias-disable; 54 bias-disable;
345 }; 55 };
346 56
347 hsuart_pins: hsuart-st !! 57 hsuart_pins: hsuart-pins {
348 pins = "gpio46 58 pins = "gpio46", "gpio47", "gpio48", "gpio49";
349 function = "bl 59 function = "blsp2_uart";
350 drive-strength 60 drive-strength = <8>;
351 bias-disable; 61 bias-disable;
352 }; 62 };
353 63
354 qpic_pins: qpic-state !! 64 qpic_pins: qpic-pins {
355 pins = "gpio1" 65 pins = "gpio1", "gpio3", "gpio4",
356 "gpio5" 66 "gpio5", "gpio6", "gpio7",
357 "gpio8" 67 "gpio8", "gpio10", "gpio11",
358 "gpio12 68 "gpio12", "gpio13", "gpio14",
359 "gpio15 !! 69 "gpio15", "gpio16", "gpio17";
360 function = "qp 70 function = "qpic";
361 drive-strength 71 drive-strength = <8>;
362 bias-disable; 72 bias-disable;
363 }; 73 };
364 }; 74 };
365 75
366 gcc: clock-controller@1800000 !! 76 intc: interrupt-controller@b000000 {
367 compatible = "qcom,gcc !! 77 compatible = "qcom,msm-qgic2";
368 reg = <0x01800000 0x80 <<
369 clocks = <&xo>, <<
370 <&sleep_clk>, <<
371 <&pcie_qmp0>, <<
372 <&pcie_qmp1>; <<
373 clock-names = "xo", <<
374 "sleep_c <<
375 "pcie0_p <<
376 "pcie1_p <<
377 #clock-cells = <1>; <<
378 #power-domain-cells = <<
379 #reset-cells = <1>; <<
380 }; <<
381 <<
382 tcsr_mutex: hwlock@1905000 { <<
383 compatible = "qcom,tcs <<
384 reg = <0x01905000 0x20 <<
385 #hwlock-cells = <1>; <<
386 }; <<
387 <<
388 tcsr: syscon@1937000 { <<
389 compatible = "qcom,tcs <<
390 reg = <0x01937000 0x21 <<
391 }; <<
392 <<
393 spmi_bus: spmi@200f000 { <<
394 compatible = "qcom,spm <<
395 reg = <0x0200f000 0x00 <<
396 <0x02400000 0x80 <<
397 <0x02c00000 0x80 <<
398 <0x03800000 0x20 <<
399 <0x0200a000 0x00 <<
400 reg-names = "core", "c <<
401 interrupts = <GIC_SPI <<
402 interrupt-names = "per <<
403 qcom,ee = <0>; <<
404 qcom,channel = <0>; <<
405 #address-cells = <2>; <<
406 #size-cells = <0>; <<
407 interrupt-controller; 78 interrupt-controller;
408 #interrupt-cells = <4> !! 79 #interrupt-cells = <0x3>;
>> 80 reg = <0xb000000 0x1000>, <0xb002000 0x1000>;
>> 81 };
>> 82
>> 83 timer {
>> 84 compatible = "arm,armv8-timer";
>> 85 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
>> 86 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
>> 87 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
>> 88 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
>> 89 };
>> 90
>> 91 timer@b120000 {
>> 92 #address-cells = <1>;
>> 93 #size-cells = <1>;
>> 94 ranges;
>> 95 compatible = "arm,armv7-timer-mem";
>> 96 reg = <0xb120000 0x1000>;
>> 97 clock-frequency = <19200000>;
>> 98
>> 99 frame@b120000 {
>> 100 frame-number = <0>;
>> 101 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
>> 102 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
>> 103 reg = <0xb121000 0x1000>,
>> 104 <0xb122000 0x1000>;
>> 105 };
>> 106
>> 107 frame@b123000 {
>> 108 frame-number = <1>;
>> 109 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
>> 110 reg = <0xb123000 0x1000>;
>> 111 status = "disabled";
>> 112 };
>> 113
>> 114 frame@b124000 {
>> 115 frame-number = <2>;
>> 116 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
>> 117 reg = <0xb124000 0x1000>;
>> 118 status = "disabled";
>> 119 };
>> 120
>> 121 frame@b125000 {
>> 122 frame-number = <3>;
>> 123 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
>> 124 reg = <0xb125000 0x1000>;
>> 125 status = "disabled";
>> 126 };
>> 127
>> 128 frame@b126000 {
>> 129 frame-number = <4>;
>> 130 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
>> 131 reg = <0xb126000 0x1000>;
>> 132 status = "disabled";
>> 133 };
>> 134
>> 135 frame@b127000 {
>> 136 frame-number = <5>;
>> 137 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
>> 138 reg = <0xb127000 0x1000>;
>> 139 status = "disabled";
>> 140 };
>> 141
>> 142 frame@b128000 {
>> 143 frame-number = <6>;
>> 144 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
>> 145 reg = <0xb128000 0x1000>;
>> 146 status = "disabled";
>> 147 };
409 }; 148 };
410 149
411 sdhc_1: mmc@7824900 { !! 150 gcc: gcc@1800000 {
412 compatible = "qcom,ipq !! 151 compatible = "qcom,gcc-ipq8074";
413 reg = <0x7824900 0x500 !! 152 reg = <0x1800000 0x80000>;
414 reg-names = "hc", "cor !! 153 #clock-cells = <0x1>;
415 !! 154 #reset-cells = <0x1>;
416 interrupts = <GIC_SPI !! 155 };
417 <GIC_SPI <<
418 interrupt-names = "hc_ <<
419 <<
420 clocks = <&gcc GCC_SDC <<
421 <&gcc GCC_SDC <<
422 <&xo>; <<
423 clock-names = "iface", <<
424 resets = <&gcc GCC_SDC <<
425 max-frequency = <38400 <<
426 mmc-ddr-1_8v; <<
427 mmc-hs200-1_8v; <<
428 mmc-hs400-1_8v; <<
429 bus-width = <8>; <<
430 156
>> 157 blsp1_uart5: serial@78b3000 {
>> 158 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
>> 159 reg = <0x78b3000 0x200>;
>> 160 interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
>> 161 clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>,
>> 162 <&gcc GCC_BLSP1_AHB_CLK>;
>> 163 clock-names = "core", "iface";
>> 164 pinctrl-0 = <&serial_4_pins>;
>> 165 pinctrl-names = "default";
431 status = "disabled"; 166 status = "disabled";
432 }; 167 };
433 168
434 blsp_dma: dma-controller@78840 !! 169 blsp_dma: dma@7884000 {
435 compatible = "qcom,bam 170 compatible = "qcom,bam-v1.7.0";
436 reg = <0x07884000 0x2b !! 171 reg = <0x7884000 0x2b000>;
437 interrupts = <GIC_SPI 172 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
438 clocks = <&gcc GCC_BLS 173 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
439 clock-names = "bam_clk 174 clock-names = "bam_clk";
440 #dma-cells = <1>; 175 #dma-cells = <1>;
441 qcom,ee = <0>; 176 qcom,ee = <0>;
442 }; 177 };
443 178
444 blsp1_uart1: serial@78af000 { 179 blsp1_uart1: serial@78af000 {
445 compatible = "qcom,msm 180 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
446 reg = <0x078af000 0x20 !! 181 reg = <0x78af000 0x200>;
447 interrupts = <GIC_SPI 182 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
448 clocks = <&gcc GCC_BLS 183 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
449 <&gcc GCC_BLS 184 <&gcc GCC_BLSP1_AHB_CLK>;
450 clock-names = "core", 185 clock-names = "core", "iface";
451 status = "disabled"; 186 status = "disabled";
452 }; 187 };
453 188
454 blsp1_uart3: serial@78b1000 { 189 blsp1_uart3: serial@78b1000 {
455 compatible = "qcom,msm 190 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
456 reg = <0x078b1000 0x20 !! 191 reg = <0x78b1000 0x200>;
457 interrupts = <GIC_SPI 192 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
458 clocks = <&gcc GCC_BLS 193 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
459 <&gcc GCC_BLSP 194 <&gcc GCC_BLSP1_AHB_CLK>;
460 clock-names = "core", 195 clock-names = "core", "iface";
461 dmas = <&blsp_dma 4>, 196 dmas = <&blsp_dma 4>,
462 <&blsp_dma 5>; 197 <&blsp_dma 5>;
463 dma-names = "tx", "rx" 198 dma-names = "tx", "rx";
464 pinctrl-0 = <&hsuart_p 199 pinctrl-0 = <&hsuart_pins>;
465 pinctrl-names = "defau 200 pinctrl-names = "default";
466 status = "disabled"; 201 status = "disabled";
467 }; 202 };
468 203
469 blsp1_uart5: serial@78b3000 { <<
470 compatible = "qcom,msm <<
471 reg = <0x078b3000 0x20 <<
472 interrupts = <GIC_SPI <<
473 clocks = <&gcc GCC_BLS <<
474 <&gcc GCC_BLS <<
475 clock-names = "core", <<
476 pinctrl-0 = <&serial_4 <<
477 pinctrl-names = "defau <<
478 status = "disabled"; <<
479 }; <<
480 <<
481 blsp1_uart6: serial@78b4000 { <<
482 compatible = "qcom,msm <<
483 reg = <0x078b4000 0x20 <<
484 interrupts = <GIC_SPI <<
485 clocks = <&gcc GCC_BLS <<
486 <&gcc GCC_BLS <<
487 clock-names = "core", <<
488 pinctrl-0 = <&serial_5 <<
489 pinctrl-names = "defau <<
490 status = "disabled"; <<
491 }; <<
492 <<
493 blsp1_spi1: spi@78b5000 { 204 blsp1_spi1: spi@78b5000 {
494 compatible = "qcom,spi 205 compatible = "qcom,spi-qup-v2.2.1";
495 #address-cells = <1>; 206 #address-cells = <1>;
496 #size-cells = <0>; 207 #size-cells = <0>;
497 reg = <0x078b5000 0x60 !! 208 reg = <0x78b5000 0x600>;
498 interrupts = <GIC_SPI 209 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
>> 210 spi-max-frequency = <50000000>;
499 clocks = <&gcc GCC_BLS 211 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
500 <&gcc GCC_BLSP 212 <&gcc GCC_BLSP1_AHB_CLK>;
501 clock-names = "core", 213 clock-names = "core", "iface";
502 dmas = <&blsp_dma 12>, 214 dmas = <&blsp_dma 12>, <&blsp_dma 13>;
503 dma-names = "tx", "rx" 215 dma-names = "tx", "rx";
504 pinctrl-0 = <&spi_0_pi 216 pinctrl-0 = <&spi_0_pins>;
505 pinctrl-names = "defau 217 pinctrl-names = "default";
506 status = "disabled"; 218 status = "disabled";
507 }; 219 };
508 220
509 blsp1_i2c2: i2c@78b6000 { 221 blsp1_i2c2: i2c@78b6000 {
510 compatible = "qcom,i2c 222 compatible = "qcom,i2c-qup-v2.2.1";
511 #address-cells = <1>; 223 #address-cells = <1>;
512 #size-cells = <0>; 224 #size-cells = <0>;
513 reg = <0x078b6000 0x60 !! 225 reg = <0x78b6000 0x600>;
514 interrupts = <GIC_SPI 226 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
515 clocks = <&gcc GCC_BLS !! 227 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
516 <&gcc GCC_BLS !! 228 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
517 clock-names = "core", !! 229 clock-names = "iface", "core";
518 clock-frequency = <400 230 clock-frequency = <400000>;
519 dmas = <&blsp_dma 14>, !! 231 dmas = <&blsp_dma 15>, <&blsp_dma 14>;
520 dma-names = "tx", "rx" !! 232 dma-names = "rx", "tx";
521 pinctrl-0 = <&i2c_0_pi 233 pinctrl-0 = <&i2c_0_pins>;
522 pinctrl-names = "defau 234 pinctrl-names = "default";
523 status = "disabled"; 235 status = "disabled";
524 }; 236 };
525 237
526 blsp1_i2c3: i2c@78b7000 { 238 blsp1_i2c3: i2c@78b7000 {
527 compatible = "qcom,i2c 239 compatible = "qcom,i2c-qup-v2.2.1";
528 #address-cells = <1>; 240 #address-cells = <1>;
529 #size-cells = <0>; 241 #size-cells = <0>;
530 reg = <0x078b7000 0x60 !! 242 reg = <0x78b7000 0x600>;
531 interrupts = <GIC_SPI 243 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
532 clocks = <&gcc GCC_BLS !! 244 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
533 <&gcc GCC_BLS !! 245 <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
534 clock-names = "core", !! 246 clock-names = "iface", "core";
535 clock-frequency = <100 247 clock-frequency = <100000>;
536 dmas = <&blsp_dma 16>, !! 248 dmas = <&blsp_dma 17>, <&blsp_dma 16>;
537 dma-names = "tx", "rx" !! 249 dma-names = "rx", "tx";
538 status = "disabled"; <<
539 }; <<
540 <<
541 blsp1_spi4: spi@78b8000 { <<
542 compatible = "qcom,spi <<
543 #address-cells = <1>; <<
544 #size-cells = <0>; <<
545 reg = <0x78b8000 0x600 <<
546 interrupts = <GIC_SPI <<
547 clocks = <&gcc GCC_BLS <<
548 <&gcc GCC_BLS <<
549 clock-names = "core", <<
550 dmas = <&blsp_dma 18>, <<
551 dma-names = "tx", "rx" <<
552 status = "disabled"; <<
553 }; <<
554 <<
555 blsp1_i2c5: i2c@78b9000 { <<
556 compatible = "qcom,i2c <<
557 #address-cells = <1>; <<
558 #size-cells = <0>; <<
559 reg = <0x78b9000 0x600 <<
560 interrupts = <GIC_SPI <<
561 clocks = <&gcc GCC_BLS <<
562 <&gcc GCC_BLS <<
563 clock-names = "core", <<
564 clock-frequency = <400 <<
565 dmas = <&blsp_dma 20>, <<
566 dma-names = "tx", "rx" <<
567 status = "disabled"; <<
568 }; <<
569 <<
570 blsp1_spi5: spi@78b9000 { <<
571 compatible = "qcom,spi <<
572 #address-cells = <1>; <<
573 #size-cells = <0>; <<
574 reg = <0x78b9000 0x600 <<
575 interrupts = <GIC_SPI <<
576 clocks = <&gcc GCC_BLS <<
577 <&gcc GCC_BLS <<
578 clock-names = "core", <<
579 dmas = <&blsp_dma 20>, <<
580 dma-names = "tx", "rx" <<
581 status = "disabled"; <<
582 }; <<
583 <<
584 blsp1_i2c6: i2c@78ba000 { <<
585 compatible = "qcom,i2c <<
586 #address-cells = <1>; <<
587 #size-cells = <0>; <<
588 reg = <0x078ba000 0x60 <<
589 interrupts = <GIC_SPI <<
590 clocks = <&gcc GCC_BLS <<
591 <&gcc GCC_BLS <<
592 clock-names = "core", <<
593 clock-frequency = <100 <<
594 dmas = <&blsp_dma 22>, <<
595 dma-names = "tx", "rx" <<
596 status = "disabled"; 250 status = "disabled";
597 }; 251 };
598 252
599 qpic_bam: dma-controller@79840 !! 253 qpic_bam: dma@7984000 {
600 compatible = "qcom,bam 254 compatible = "qcom,bam-v1.7.0";
601 reg = <0x07984000 0x1a !! 255 reg = <0x7984000 0x1a000>;
602 interrupts = <GIC_SPI 256 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
603 clocks = <&gcc GCC_QPI 257 clocks = <&gcc GCC_QPIC_AHB_CLK>;
604 clock-names = "bam_clk 258 clock-names = "bam_clk";
605 #dma-cells = <1>; 259 #dma-cells = <1>;
606 qcom,ee = <0>; 260 qcom,ee = <0>;
607 status = "disabled"; 261 status = "disabled";
608 }; 262 };
609 263
610 qpic_nand: nand-controller@79b !! 264 qpic_nand: nand@79b0000 {
611 compatible = "qcom,ipq 265 compatible = "qcom,ipq8074-nand";
612 reg = <0x079b0000 0x10 !! 266 reg = <0x79b0000 0x10000>;
613 #address-cells = <1>; 267 #address-cells = <1>;
614 #size-cells = <0>; 268 #size-cells = <0>;
615 clocks = <&gcc GCC_QPI 269 clocks = <&gcc GCC_QPIC_CLK>,
616 <&gcc GCC_QPI 270 <&gcc GCC_QPIC_AHB_CLK>;
617 clock-names = "core", 271 clock-names = "core", "aon";
618 272
619 dmas = <&qpic_bam 0>, 273 dmas = <&qpic_bam 0>,
620 <&qpic_bam 1>, 274 <&qpic_bam 1>,
621 <&qpic_bam 2>; 275 <&qpic_bam 2>;
622 dma-names = "tx", "rx" 276 dma-names = "tx", "rx", "cmd";
623 pinctrl-0 = <&qpic_pin 277 pinctrl-0 = <&qpic_pins>;
624 pinctrl-names = "defau 278 pinctrl-names = "default";
625 status = "disabled"; 279 status = "disabled";
626 }; 280 };
627 281
628 usb_0: usb@8af8800 { !! 282 pcie_phy0: phy@86000 {
629 compatible = "qcom,ipq !! 283 compatible = "qcom,ipq8074-qmp-pcie-phy";
630 reg = <0x08af8800 0x40 !! 284 reg = <0x86000 0x1000>;
631 #address-cells = <1>; !! 285 #phy-cells = <0>;
632 #size-cells = <1>; !! 286 clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
633 ranges; !! 287 clock-names = "pipe_clk";
634 !! 288 clock-output-names = "pcie20_phy0_pipe_clk";
635 clocks = <&gcc GCC_SYS <<
636 <&gcc GCC_USB0 <<
637 <&gcc GCC_USB0 <<
638 <&gcc GCC_USB0 <<
639 clock-names = "cfg_noc <<
640 "core", <<
641 "sleep", <<
642 "mock_utmi"; <<
643 <<
644 assigned-clocks = <&gc <<
645 <&gc <<
646 <&gc <<
647 assigned-clock-rates = <<
648 <<
649 <<
650 <<
651 interrupts = <GIC_SPI <<
652 <GIC_SPI <<
653 <GIC_SPI <<
654 interrupt-names = "pwr <<
655 "qus <<
656 "ss_ <<
657 <<
658 power-domains = <&gcc <<
659 <<
660 resets = <&gcc GCC_USB <<
661 status = "disabled"; <<
662 <<
663 dwc_0: usb@8a00000 { <<
664 compatible = " <<
665 reg = <0x8a000 <<
666 interrupts = < <<
667 phys = <&qusb_ <<
668 phy-names = "u <<
669 snps,parkmode- <<
670 snps,is-utmi-l <<
671 snps,hird-thre <<
672 snps,dis_u2_su <<
673 snps,dis_u3_su <<
674 dr_mode = "hos <<
675 }; <<
676 }; <<
677 <<
678 usb_1: usb@8cf8800 { <<
679 compatible = "qcom,ipq <<
680 reg = <0x08cf8800 0x40 <<
681 #address-cells = <1>; <<
682 #size-cells = <1>; <<
683 ranges; <<
684 <<
685 clocks = <&gcc GCC_SYS <<
686 <&gcc GCC_USB1 <<
687 <&gcc GCC_USB1 <<
688 <&gcc GCC_USB1 <<
689 clock-names = "cfg_noc <<
690 "core", <<
691 "sleep", <<
692 "mock_utmi"; <<
693 <<
694 assigned-clocks = <&gc <<
695 <&gc <<
696 <&gc <<
697 assigned-clock-rates = <<
698 <<
699 <<
700 <<
701 interrupts = <GIC_SPI <<
702 <GIC_SPI <<
703 <GIC_SPI <<
704 interrupt-names = "pwr <<
705 "qus <<
706 "ss_ <<
707 <<
708 power-domains = <&gcc <<
709 289
710 resets = <&gcc GCC_USB !! 290 resets = <&gcc GCC_PCIE0_PHY_BCR>,
>> 291 <&gcc GCC_PCIE0PHY_PHY_BCR>;
>> 292 reset-names = "phy",
>> 293 "common";
711 status = "disabled"; 294 status = "disabled";
712 <<
713 dwc_1: usb@8c00000 { <<
714 compatible = " <<
715 reg = <0x8c000 <<
716 interrupts = < <<
717 phys = <&qusb_ <<
718 phy-names = "u <<
719 snps,parkmode- <<
720 snps,is-utmi-l <<
721 snps,hird-thre <<
722 snps,dis_u2_su <<
723 snps,dis_u3_su <<
724 dr_mode = "hos <<
725 }; <<
726 }; <<
727 <<
728 intc: interrupt-controller@b00 <<
729 compatible = "qcom,msm <<
730 #address-cells = <1>; <<
731 #size-cells = <1>; <<
732 interrupt-controller; <<
733 #interrupt-cells = <3> <<
734 reg = <0x0b000000 0x10 <<
735 ranges = <0 0xb00a000 <<
736 <<
737 v2m@0 { <<
738 compatible = " <<
739 msi-controller <<
740 reg = <0x0 0xf <<
741 }; <<
742 }; <<
743 <<
744 watchdog: watchdog@b017000 { <<
745 compatible = "qcom,kps <<
746 reg = <0xb017000 0x100 <<
747 interrupts = <GIC_SPI <<
748 clocks = <&sleep_clk>; <<
749 timeout-sec = <30>; <<
750 }; <<
751 <<
752 apcs_glb: mailbox@b111000 { <<
753 compatible = "qcom,ipq <<
754 "qcom,ipq <<
755 reg = <0x0b111000 0x10 <<
756 clocks = <&a53pll>, <& <<
757 clock-names = "pll", " <<
758 <<
759 #clock-cells = <1>; <<
760 #mbox-cells = <1>; <<
761 }; <<
762 <<
763 a53pll: clock@b116000 { <<
764 compatible = "qcom,ipq <<
765 reg = <0x0b116000 0x40 <<
766 #clock-cells = <0>; <<
767 clocks = <&xo>; <<
768 clock-names = "xo"; <<
769 }; <<
770 <<
771 timer@b120000 { <<
772 #address-cells = <1>; <<
773 #size-cells = <1>; <<
774 ranges; <<
775 compatible = "arm,armv <<
776 reg = <0x0b120000 0x10 <<
777 <<
778 frame@b120000 { <<
779 frame-number = <<
780 interrupts = < <<
781 < <<
782 reg = <0x0b121 <<
783 <0x0b122 <<
784 }; <<
785 <<
786 frame@b123000 { <<
787 frame-number = <<
788 interrupts = < <<
789 reg = <0x0b123 <<
790 status = "disa <<
791 }; <<
792 <<
793 frame@b124000 { <<
794 frame-number = <<
795 interrupts = < <<
796 reg = <0x0b124 <<
797 status = "disa <<
798 }; <<
799 <<
800 frame@b125000 { <<
801 frame-number = <<
802 interrupts = < <<
803 reg = <0x0b125 <<
804 status = "disa <<
805 }; <<
806 <<
807 frame@b126000 { <<
808 frame-number = <<
809 interrupts = < <<
810 reg = <0x0b126 <<
811 status = "disa <<
812 }; <<
813 <<
814 frame@b127000 { <<
815 frame-number = <<
816 interrupts = < <<
817 reg = <0x0b127 <<
818 status = "disa <<
819 }; <<
820 <<
821 frame@b128000 { <<
822 frame-number = <<
823 interrupts = < <<
824 reg = <0x0b128 <<
825 status = "disa <<
826 }; <<
827 }; 295 };
828 296
829 pcie1: pcie@10000000 { !! 297 pcie0: pci@20000000 {
830 compatible = "qcom,pci 298 compatible = "qcom,pcie-ipq8074";
831 reg = <0x10000000 0xf1 !! 299 reg = <0x20000000 0xf1d
832 <0x10000f20 0xa8 !! 300 0x20000f20 0xa8
833 <0x00088000 0x20 !! 301 0x80000 0x2000
834 <0x10100000 0x10 !! 302 0x20100000 0x1000>;
835 reg-names = "dbi", "el 303 reg-names = "dbi", "elbi", "parf", "config";
836 device_type = "pci"; 304 device_type = "pci";
837 linux,pci-domain = <1> !! 305 linux,pci-domain = <0>;
838 bus-range = <0x00 0xff 306 bus-range = <0x00 0xff>;
839 num-lanes = <1>; 307 num-lanes = <1>;
840 max-link-speed = <2>; <<
841 #address-cells = <3>; 308 #address-cells = <3>;
842 #size-cells = <2>; 309 #size-cells = <2>;
843 310
844 phys = <&pcie_qmp1>; !! 311 phys = <&pcie_phy0>;
845 phy-names = "pciephy"; 312 phy-names = "pciephy";
846 313
847 ranges = <0x81000000 0 !! 314 ranges = <0x81000000 0 0x20200000 0x20200000
848 <0x82000000 0 !! 315 0 0x100000 /* downstream I/O */
>> 316 0x82000000 0 0x20300000 0x20300000
>> 317 0 0xd00000>; /* non-prefetchable memory */
849 318
850 interrupts = <GIC_SPI !! 319 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
851 interrupt-names = "msi 320 interrupt-names = "msi";
852 #interrupt-cells = <1> 321 #interrupt-cells = <1>;
853 interrupt-map-mask = < 322 interrupt-map-mask = <0 0 0 0x7>;
854 interrupt-map = <0 0 0 !! 323 interrupt-map = <0 0 0 1 &intc 0 75
855 IRQ_T 324 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
856 <0 0 0 !! 325 <0 0 0 2 &intc 0 78
857 IRQ_T 326 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
858 <0 0 0 !! 327 <0 0 0 3 &intc 0 79
859 IRQ_T 328 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
860 <0 0 0 !! 329 <0 0 0 4 &intc 0 83
861 IRQ_T 330 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
862 331
863 clocks = <&gcc GCC_SYS !! 332 clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
864 <&gcc GCC_PCI !! 333 <&gcc GCC_PCIE0_AXI_M_CLK>,
865 <&gcc GCC_PCI !! 334 <&gcc GCC_PCIE0_AXI_S_CLK>,
866 <&gcc GCC_PCI !! 335 <&gcc GCC_PCIE0_AHB_CLK>,
867 <&gcc GCC_PCI !! 336 <&gcc GCC_PCIE0_AUX_CLK>;
>> 337
868 clock-names = "iface", 338 clock-names = "iface",
869 "axi_m", 339 "axi_m",
870 "axi_s", 340 "axi_s",
871 "ahb", 341 "ahb",
872 "aux"; 342 "aux";
873 resets = <&gcc GCC_PCI !! 343 resets = <&gcc GCC_PCIE0_PIPE_ARES>,
874 <&gcc GCC_PCI !! 344 <&gcc GCC_PCIE0_SLEEP_ARES>,
875 <&gcc GCC_PCI !! 345 <&gcc GCC_PCIE0_CORE_STICKY_ARES>,
876 <&gcc GCC_PCI !! 346 <&gcc GCC_PCIE0_AXI_MASTER_ARES>,
877 <&gcc GCC_PCI !! 347 <&gcc GCC_PCIE0_AXI_SLAVE_ARES>,
878 <&gcc GCC_PCI !! 348 <&gcc GCC_PCIE0_AHB_ARES>,
879 <&gcc GCC_PCI !! 349 <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>;
880 reset-names = "pipe", 350 reset-names = "pipe",
881 "sleep", 351 "sleep",
882 "sticky" 352 "sticky",
883 "axi_m", 353 "axi_m",
884 "axi_s", 354 "axi_s",
885 "ahb", 355 "ahb",
886 "axi_m_s 356 "axi_m_sticky";
887 status = "disabled"; 357 status = "disabled";
>> 358 };
888 359
889 pcie@0 { !! 360 pcie_phy1: phy@8e000 {
890 device_type = !! 361 compatible = "qcom,ipq8074-qmp-pcie-phy";
891 reg = <0x0 0x0 !! 362 reg = <0x8e000 0x1000>;
892 bus-range = <0 !! 363 #phy-cells = <0>;
893 !! 364 clocks = <&gcc GCC_PCIE1_PIPE_CLK>;
894 #address-cells !! 365 clock-names = "pipe_clk";
895 #size-cells = !! 366 clock-output-names = "pcie20_phy1_pipe_clk";
896 ranges; !! 367
897 }; !! 368 resets = <&gcc GCC_PCIE1_PHY_BCR>,
>> 369 <&gcc GCC_PCIE1PHY_PHY_BCR>;
>> 370 reset-names = "phy",
>> 371 "common";
>> 372 status = "disabled";
898 }; 373 };
899 374
900 pcie0: pcie@20000000 { !! 375 pcie1: pci@10000000 {
901 compatible = "qcom,pci !! 376 compatible = "qcom,pcie-ipq8074";
902 reg = <0x20000000 0xf1 !! 377 reg = <0x10000000 0xf1d
903 <0x20000f20 0xa8 !! 378 0x10000f20 0xa8
904 <0x20001000 0x10 !! 379 0x88000 0x2000
905 <0x00080000 0x40 !! 380 0x10100000 0x1000>;
906 <0x20100000 0x10 !! 381 reg-names = "dbi", "elbi", "parf", "config";
907 reg-names = "dbi", "el <<
908 device_type = "pci"; 382 device_type = "pci";
909 linux,pci-domain = <0> !! 383 linux,pci-domain = <1>;
910 bus-range = <0x00 0xff 384 bus-range = <0x00 0xff>;
911 num-lanes = <1>; 385 num-lanes = <1>;
912 max-link-speed = <3>; <<
913 #address-cells = <3>; 386 #address-cells = <3>;
914 #size-cells = <2>; 387 #size-cells = <2>;
915 388
916 phys = <&pcie_qmp0>; !! 389 phys = <&pcie_phy1>;
917 phy-names = "pciephy"; 390 phy-names = "pciephy";
918 391
919 ranges = <0x81000000 0 !! 392 ranges = <0x81000000 0 0x10200000 0x10200000
920 <0x82000000 0 !! 393 0 0x100000 /* downstream I/O */
>> 394 0x82000000 0 0x10300000 0x10300000
>> 395 0 0xd00000>; /* non-prefetchable memory */
921 396
922 interrupts = <GIC_SPI !! 397 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
923 interrupt-names = "msi 398 interrupt-names = "msi";
924 #interrupt-cells = <1> 399 #interrupt-cells = <1>;
925 interrupt-map-mask = < 400 interrupt-map-mask = <0 0 0 0x7>;
926 interrupt-map = <0 0 0 !! 401 interrupt-map = <0 0 0 1 &intc 0 142
927 IRQ_T 402 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
928 <0 0 0 !! 403 <0 0 0 2 &intc 0 143
929 IRQ_T 404 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
930 <0 0 0 !! 405 <0 0 0 3 &intc 0 144
931 IRQ_T 406 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
932 <0 0 0 !! 407 <0 0 0 4 &intc 0 145
933 IRQ_T 408 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
934 409
935 clocks = <&gcc GCC_SYS !! 410 clocks = <&gcc GCC_SYS_NOC_PCIE1_AXI_CLK>,
936 <&gcc GCC_PCI !! 411 <&gcc GCC_PCIE1_AXI_M_CLK>,
937 <&gcc GCC_PCI !! 412 <&gcc GCC_PCIE1_AXI_S_CLK>,
938 <&gcc GCC_PCI !! 413 <&gcc GCC_PCIE1_AHB_CLK>,
939 <&gcc GCC_PCI !! 414 <&gcc GCC_PCIE1_AUX_CLK>;
940 clock-names = "iface", 415 clock-names = "iface",
941 "axi_m", 416 "axi_m",
942 "axi_s", 417 "axi_s",
943 "axi_bri !! 418 "ahb",
944 "rchng"; !! 419 "aux";
945 !! 420 resets = <&gcc GCC_PCIE1_PIPE_ARES>,
946 resets = <&gcc GCC_PCI !! 421 <&gcc GCC_PCIE1_SLEEP_ARES>,
947 <&gcc GCC_PCI !! 422 <&gcc GCC_PCIE1_CORE_STICKY_ARES>,
948 <&gcc GCC_PCI !! 423 <&gcc GCC_PCIE1_AXI_MASTER_ARES>,
949 <&gcc GCC_PCI !! 424 <&gcc GCC_PCIE1_AXI_SLAVE_ARES>,
950 <&gcc GCC_PCI !! 425 <&gcc GCC_PCIE1_AHB_ARES>,
951 <&gcc GCC_PCI !! 426 <&gcc GCC_PCIE1_AXI_MASTER_STICKY_ARES>;
952 <&gcc GCC_PCI <<
953 <&gcc GCC_PCI <<
954 reset-names = "pipe", 427 reset-names = "pipe",
955 "sleep", 428 "sleep",
956 "sticky" 429 "sticky",
957 "axi_m", 430 "axi_m",
958 "axi_s", 431 "axi_s",
959 "ahb", 432 "ahb",
960 "axi_m_s !! 433 "axi_m_sticky";
961 "axi_s_s <<
962 status = "disabled"; 434 status = "disabled";
963 <<
964 pcie@0 { <<
965 device_type = <<
966 reg = <0x0 0x0 <<
967 bus-range = <0 <<
968 <<
969 #address-cells <<
970 #size-cells = <<
971 ranges; <<
972 }; <<
973 }; 435 };
974 }; 436 };
975 437
976 timer { !! 438 cpus {
977 compatible = "arm,armv8-timer" !! 439 #address-cells = <0x1>;
978 interrupts = <GIC_PPI 2 (GIC_C !! 440 #size-cells = <0x0>;
979 <GIC_PPI 3 (GIC_C <<
980 <GIC_PPI 4 (GIC_C <<
981 <GIC_PPI 1 (GIC_C <<
982 }; <<
983 <<
984 thermal-zones { <<
985 nss-top-thermal { <<
986 polling-delay-passive <<
987 <<
988 thermal-sensors = <&ts <<
989 <<
990 trips { <<
991 nss-top-crit { <<
992 temper <<
993 hyster <<
994 type = <<
995 }; <<
996 }; <<
997 }; <<
998 <<
999 nss0-thermal { <<
1000 polling-delay-passive <<
1001 <<
1002 thermal-sensors = <&t <<
1003 <<
1004 trips { <<
1005 nss-0-crit { <<
1006 tempe <<
1007 hyste <<
1008 type <<
1009 }; <<
1010 }; <<
1011 }; <<
1012 <<
1013 nss1-thermal { <<
1014 polling-delay-passive <<
1015 <<
1016 thermal-sensors = <&t <<
1017 <<
1018 trips { <<
1019 nss-1-crit { <<
1020 tempe <<
1021 hyste <<
1022 type <<
1023 }; <<
1024 }; <<
1025 }; <<
1026 <<
1027 wcss-phya0-thermal { <<
1028 polling-delay-passive <<
1029 <<
1030 thermal-sensors = <&t <<
1031 <<
1032 trips { <<
1033 wcss-phya0-cr <<
1034 tempe <<
1035 hyste <<
1036 type <<
1037 }; <<
1038 }; <<
1039 }; <<
1040 <<
1041 wcss-phya1-thermal { <<
1042 polling-delay-passive <<
1043 <<
1044 thermal-sensors = <&t <<
1045 <<
1046 trips { <<
1047 wcss-phya1-cr <<
1048 tempe <<
1049 hyste <<
1050 type <<
1051 }; <<
1052 }; <<
1053 }; <<
1054 <<
1055 cpu0_thermal: cpu0-thermal { <<
1056 polling-delay-passive <<
1057 <<
1058 thermal-sensors = <&t <<
1059 441
1060 trips { !! 442 CPU0: cpu@0 {
1061 cpu0-crit { !! 443 device_type = "cpu";
1062 tempe !! 444 compatible = "arm,cortex-a53";
1063 hyste !! 445 reg = <0x0>;
1064 type !! 446 next-level-cache = <&L2_0>;
1065 }; !! 447 enable-method = "psci";
1066 }; <<
1067 }; 448 };
1068 449
1069 cpu1_thermal: cpu1-thermal { !! 450 CPU1: cpu@1 {
1070 polling-delay-passive !! 451 device_type = "cpu";
1071 !! 452 compatible = "arm,cortex-a53";
1072 thermal-sensors = <&t !! 453 enable-method = "psci";
1073 !! 454 reg = <0x1>;
1074 trips { !! 455 next-level-cache = <&L2_0>;
1075 cpu1-crit { <<
1076 tempe <<
1077 hyste <<
1078 type <<
1079 }; <<
1080 }; <<
1081 }; 456 };
1082 457
1083 cpu2_thermal: cpu2-thermal { !! 458 CPU2: cpu@2 {
1084 polling-delay-passive !! 459 device_type = "cpu";
1085 !! 460 compatible = "arm,cortex-a53";
1086 thermal-sensors = <&t !! 461 enable-method = "psci";
1087 !! 462 reg = <0x2>;
1088 trips { !! 463 next-level-cache = <&L2_0>;
1089 cpu2-crit { <<
1090 tempe <<
1091 hyste <<
1092 type <<
1093 }; <<
1094 }; <<
1095 }; 464 };
1096 465
1097 cpu3_thermal: cpu3-thermal { !! 466 CPU3: cpu@3 {
1098 polling-delay-passive !! 467 device_type = "cpu";
1099 !! 468 compatible = "arm,cortex-a53";
1100 thermal-sensors = <&t !! 469 enable-method = "psci";
1101 !! 470 reg = <0x3>;
1102 trips { !! 471 next-level-cache = <&L2_0>;
1103 cpu3-crit { <<
1104 tempe <<
1105 hyste <<
1106 type <<
1107 }; <<
1108 }; <<
1109 }; 472 };
1110 473
1111 cluster_thermal: cluster-ther !! 474 L2_0: l2-cache {
1112 polling-delay-passive !! 475 compatible = "cache";
1113 !! 476 cache-level = <0x2>;
1114 thermal-sensors = <&t <<
1115 <<
1116 trips { <<
1117 cluster-crit <<
1118 tempe <<
1119 hyste <<
1120 type <<
1121 }; <<
1122 }; <<
1123 }; 477 };
>> 478 };
1124 479
1125 wcss-phyb0-thermal { !! 480 psci {
1126 polling-delay-passive !! 481 compatible = "arm,psci-1.0";
>> 482 method = "smc";
>> 483 };
1127 484
1128 thermal-sensors = <&t !! 485 pmu {
>> 486 compatible = "arm,armv8-pmuv3";
>> 487 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
>> 488 };
1129 489
1130 trips { !! 490 clocks {
1131 wcss-phyb0-cr !! 491 sleep_clk: sleep_clk {
1132 tempe !! 492 compatible = "fixed-clock";
1133 hyste !! 493 clock-frequency = <32000>;
1134 type !! 494 #clock-cells = <0>;
1135 }; <<
1136 }; <<
1137 }; 495 };
1138 496
1139 wcss-phyb1-thermal { !! 497 xo: xo {
1140 polling-delay-passive !! 498 compatible = "fixed-clock";
1141 !! 499 clock-frequency = <19200000>;
1142 thermal-sensors = <&t !! 500 #clock-cells = <0>;
1143 <<
1144 trips { <<
1145 wcss-phyb1-cr <<
1146 tempe <<
1147 hyste <<
1148 type <<
1149 }; <<
1150 }; <<
1151 }; 501 };
1152 }; 502 };
1153 }; 503 };
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