1 // SPDX-License-Identifier: GPL-2.0-only 1 // SPDX-License-Identifier: GPL-2.0-only
2 /* 2 /*
3 * Copyright (c) 2017, The Linux Foundation. A 3 * Copyright (c) 2017, The Linux Foundation. All rights reserved.
4 */ 4 */
5 5
6 #include <dt-bindings/interrupt-controller/arm 6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,gcc-ipq8074.h 7 #include <dt-bindings/clock/qcom,gcc-ipq8074.h>
8 8
9 / { 9 / {
10 #address-cells = <2>; <<
11 #size-cells = <2>; <<
12 <<
13 model = "Qualcomm Technologies, Inc. I 10 model = "Qualcomm Technologies, Inc. IPQ8074";
14 compatible = "qcom,ipq8074"; 11 compatible = "qcom,ipq8074";
15 interrupt-parent = <&intc>; <<
16 12
17 clocks { 13 clocks {
18 sleep_clk: sleep_clk { 14 sleep_clk: sleep_clk {
19 compatible = "fixed-cl 15 compatible = "fixed-clock";
20 clock-frequency = <327 16 clock-frequency = <32768>;
21 #clock-cells = <0>; 17 #clock-cells = <0>;
22 }; 18 };
23 19
24 xo: xo { 20 xo: xo {
25 compatible = "fixed-cl 21 compatible = "fixed-clock";
26 clock-frequency = <192 22 clock-frequency = <19200000>;
27 #clock-cells = <0>; 23 #clock-cells = <0>;
28 }; 24 };
29 }; 25 };
30 26
31 cpus { 27 cpus {
32 #address-cells = <1>; !! 28 #address-cells = <0x1>;
33 #size-cells = <0>; !! 29 #size-cells = <0x0>;
34 30
35 CPU0: cpu@0 { 31 CPU0: cpu@0 {
36 device_type = "cpu"; 32 device_type = "cpu";
37 compatible = "arm,cort 33 compatible = "arm,cortex-a53";
38 reg = <0x0>; 34 reg = <0x0>;
39 next-level-cache = <&L 35 next-level-cache = <&L2_0>;
40 enable-method = "psci" 36 enable-method = "psci";
41 }; 37 };
42 38
43 CPU1: cpu@1 { 39 CPU1: cpu@1 {
44 device_type = "cpu"; 40 device_type = "cpu";
45 compatible = "arm,cort 41 compatible = "arm,cortex-a53";
46 enable-method = "psci" 42 enable-method = "psci";
47 reg = <0x1>; 43 reg = <0x1>;
48 next-level-cache = <&L 44 next-level-cache = <&L2_0>;
49 }; 45 };
50 46
51 CPU2: cpu@2 { 47 CPU2: cpu@2 {
52 device_type = "cpu"; 48 device_type = "cpu";
53 compatible = "arm,cort 49 compatible = "arm,cortex-a53";
54 enable-method = "psci" 50 enable-method = "psci";
55 reg = <0x2>; 51 reg = <0x2>;
56 next-level-cache = <&L 52 next-level-cache = <&L2_0>;
57 }; 53 };
58 54
59 CPU3: cpu@3 { 55 CPU3: cpu@3 {
60 device_type = "cpu"; 56 device_type = "cpu";
61 compatible = "arm,cort 57 compatible = "arm,cortex-a53";
62 enable-method = "psci" 58 enable-method = "psci";
63 reg = <0x3>; 59 reg = <0x3>;
64 next-level-cache = <&L 60 next-level-cache = <&L2_0>;
65 }; 61 };
66 62
67 L2_0: l2-cache { 63 L2_0: l2-cache {
68 compatible = "cache"; 64 compatible = "cache";
69 cache-level = <2>; !! 65 cache-level = <0x2>;
70 cache-unified; <<
71 }; 66 };
72 }; 67 };
73 68
74 pmu { 69 pmu {
75 compatible = "arm,cortex-a53-p 70 compatible = "arm,cortex-a53-pmu";
76 interrupts = <GIC_PPI 7 (GIC_C 71 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
77 }; 72 };
78 73
79 psci { 74 psci {
80 compatible = "arm,psci-1.0"; 75 compatible = "arm,psci-1.0";
81 method = "smc"; 76 method = "smc";
82 }; 77 };
83 78
84 reserved-memory { <<
85 #address-cells = <2>; <<
86 #size-cells = <2>; <<
87 ranges; <<
88 <<
89 bootloader@4a600000 { <<
90 reg = <0x0 0x4a600000 <<
91 no-map; <<
92 }; <<
93 <<
94 sbl@4aa00000 { <<
95 reg = <0x0 0x4aa00000 <<
96 no-map; <<
97 }; <<
98 <<
99 smem@4ab00000 { <<
100 compatible = "qcom,sme <<
101 reg = <0x0 0x4ab00000 <<
102 no-map; <<
103 <<
104 hwlocks = <&tcsr_mutex <<
105 }; <<
106 <<
107 memory@4ac00000 { <<
108 reg = <0x0 0x4ac00000 <<
109 no-map; <<
110 }; <<
111 }; <<
112 <<
113 firmware { 79 firmware {
114 scm { 80 scm {
115 compatible = "qcom,scm 81 compatible = "qcom,scm-ipq8074", "qcom,scm";
116 qcom,dload-mode = <&tc <<
117 }; 82 };
118 }; 83 };
119 84
120 soc: soc@0 { !! 85 soc: soc {
121 #address-cells = <1>; !! 86 #address-cells = <0x1>;
122 #size-cells = <1>; !! 87 #size-cells = <0x1>;
123 ranges = <0 0 0 0xffffffff>; 88 ranges = <0 0 0 0xffffffff>;
124 compatible = "simple-bus"; 89 compatible = "simple-bus";
125 90
126 ssphy_1: phy@58000 { 91 ssphy_1: phy@58000 {
127 compatible = "qcom,ipq 92 compatible = "qcom,ipq8074-qmp-usb3-phy";
128 reg = <0x00058000 0x10 !! 93 reg = <0x00058000 0x1c4>;
>> 94 #address-cells = <1>;
>> 95 #size-cells = <1>;
>> 96 ranges;
129 97
130 clocks = <&gcc GCC_USB 98 clocks = <&gcc GCC_USB1_AUX_CLK>,
131 <&xo>, !! 99 <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
132 <&gcc GCC_USB !! 100 <&xo>;
133 <&gcc GCC_USB !! 101 clock-names = "aux", "cfg_ahb", "ref";
134 clock-names = "aux", !! 102
135 "ref", !! 103 resets = <&gcc GCC_USB1_PHY_BCR>,
136 "cfg_ahb !! 104 <&gcc GCC_USB3PHY_1_PHY_BCR>;
137 "pipe"; !! 105 reset-names = "phy","common";
138 clock-output-names = " !! 106 status = "disabled";
139 #clock-cells = <0>; !! 107
140 #phy-cells = <0>; !! 108 usb1_ssphy: phy@58200 {
141 !! 109 reg = <0x00058200 0x130>, /* Tx */
142 resets = <&gcc GCC_USB !! 110 <0x00058400 0x200>, /* Rx */
143 <&gcc GCC_USB !! 111 <0x00058800 0x1f8>, /* PCS */
144 reset-names = "phy", !! 112 <0x00058600 0x044>; /* PCS misc*/
145 "phy_phy !! 113 #phy-cells = <0>;
146 !! 114 #clock-cells = <1>;
147 status = "disabled"; !! 115 clocks = <&gcc GCC_USB1_PIPE_CLK>;
>> 116 clock-names = "pipe0";
>> 117 clock-output-names = "gcc_usb1_pipe_clk_src";
>> 118 };
148 }; 119 };
149 120
150 qusb_phy_1: phy@59000 { 121 qusb_phy_1: phy@59000 {
151 compatible = "qcom,ipq 122 compatible = "qcom,ipq8074-qusb2-phy";
152 reg = <0x00059000 0x18 123 reg = <0x00059000 0x180>;
153 #phy-cells = <0>; 124 #phy-cells = <0>;
154 125
155 clocks = <&gcc GCC_USB 126 clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
156 <&xo>; 127 <&xo>;
157 clock-names = "cfg_ahb 128 clock-names = "cfg_ahb", "ref";
158 129
159 resets = <&gcc GCC_QUS 130 resets = <&gcc GCC_QUSB2_1_PHY_BCR>;
160 status = "disabled"; 131 status = "disabled";
161 }; 132 };
162 133
163 ssphy_0: phy@78000 { 134 ssphy_0: phy@78000 {
164 compatible = "qcom,ipq 135 compatible = "qcom,ipq8074-qmp-usb3-phy";
165 reg = <0x00078000 0x10 !! 136 reg = <0x00078000 0x1c4>;
>> 137 #address-cells = <1>;
>> 138 #size-cells = <1>;
>> 139 ranges;
166 140
167 clocks = <&gcc GCC_USB 141 clocks = <&gcc GCC_USB0_AUX_CLK>,
168 <&xo>, !! 142 <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
169 <&gcc GCC_USB !! 143 <&xo>;
170 <&gcc GCC_USB !! 144 clock-names = "aux", "cfg_ahb", "ref";
171 clock-names = "aux", !! 145
172 "ref", !! 146 resets = <&gcc GCC_USB0_PHY_BCR>,
173 "cfg_ahb !! 147 <&gcc GCC_USB3PHY_0_PHY_BCR>;
174 "pipe"; !! 148 reset-names = "phy","common";
175 clock-output-names = " !! 149 status = "disabled";
176 #clock-cells = <0>; !! 150
177 #phy-cells = <0>; !! 151 usb0_ssphy: phy@78200 {
178 !! 152 reg = <0x00078200 0x130>, /* Tx */
179 resets = <&gcc GCC_USB !! 153 <0x00078400 0x200>, /* Rx */
180 <&gcc GCC_USB !! 154 <0x00078800 0x1f8>, /* PCS */
181 reset-names = "phy", !! 155 <0x00078600 0x044>; /* PCS misc*/
182 "phy_phy !! 156 #phy-cells = <0>;
183 !! 157 #clock-cells = <1>;
184 status = "disabled"; !! 158 clocks = <&gcc GCC_USB0_PIPE_CLK>;
>> 159 clock-names = "pipe0";
>> 160 clock-output-names = "gcc_usb0_pipe_clk_src";
>> 161 };
185 }; 162 };
186 163
187 qusb_phy_0: phy@79000 { 164 qusb_phy_0: phy@79000 {
188 compatible = "qcom,ipq 165 compatible = "qcom,ipq8074-qusb2-phy";
189 reg = <0x00079000 0x18 166 reg = <0x00079000 0x180>;
190 #phy-cells = <0>; 167 #phy-cells = <0>;
191 168
192 clocks = <&gcc GCC_USB 169 clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
193 <&xo>; 170 <&xo>;
194 clock-names = "cfg_ahb 171 clock-names = "cfg_ahb", "ref";
195 172
196 resets = <&gcc GCC_QUS 173 resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
197 status = "disabled"; 174 status = "disabled";
198 }; 175 };
199 176
200 pcie_qmp0: phy@84000 { !! 177 pcie_qmp0: phy@86000 {
201 compatible = "qcom,ipq !! 178 compatible = "qcom,ipq8074-qmp-pcie-phy";
202 reg = <0x00084000 0x10 !! 179 reg = <0x00086000 0x1000>;
>> 180 #address-cells = <1>;
>> 181 #size-cells = <1>;
>> 182 ranges;
203 183
204 clocks = <&gcc GCC_PCI 184 clocks = <&gcc GCC_PCIE0_AUX_CLK>,
205 <&gcc GCC_PCI !! 185 <&gcc GCC_PCIE0_AHB_CLK>;
206 <&gcc GCC_PCI !! 186 clock-names = "aux", "cfg_ahb";
207 clock-names = "aux", <<
208 "cfg_ahb <<
209 "pipe"; <<
210 <<
211 clock-output-names = " <<
212 #clock-cells = <0>; <<
213 <<
214 #phy-cells = <0>; <<
215 <<
216 resets = <&gcc GCC_PCI 187 resets = <&gcc GCC_PCIE0_PHY_BCR>,
217 <&gcc GCC_PCI !! 188 <&gcc GCC_PCIE0PHY_PHY_BCR>;
218 reset-names = "phy", 189 reset-names = "phy",
219 "common" 190 "common";
220 status = "disabled"; 191 status = "disabled";
>> 192
>> 193 pcie_phy0: phy@86200 {
>> 194 reg = <0x86200 0x16c>,
>> 195 <0x86400 0x200>,
>> 196 <0x86800 0x4f4>;
>> 197 #phy-cells = <0>;
>> 198 #clock-cells = <0>;
>> 199 clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
>> 200 clock-names = "pipe0";
>> 201 clock-output-names = "pcie_0_pipe_clk";
>> 202 };
221 }; 203 };
222 204
223 pcie_qmp1: phy@8e000 { 205 pcie_qmp1: phy@8e000 {
224 compatible = "qcom,ipq 206 compatible = "qcom,ipq8074-qmp-pcie-phy";
225 reg = <0x0008e000 0x10 207 reg = <0x0008e000 0x1000>;
>> 208 #address-cells = <1>;
>> 209 #size-cells = <1>;
>> 210 ranges;
226 211
227 clocks = <&gcc GCC_PCI 212 clocks = <&gcc GCC_PCIE1_AUX_CLK>,
228 <&gcc GCC_PCI !! 213 <&gcc GCC_PCIE1_AHB_CLK>;
229 <&gcc GCC_PCI !! 214 clock-names = "aux", "cfg_ahb";
230 clock-names = "aux", <<
231 "cfg_ahb <<
232 "pipe"; <<
233 <<
234 clock-output-names = " <<
235 #clock-cells = <0>; <<
236 <<
237 #phy-cells = <0>; <<
238 <<
239 resets = <&gcc GCC_PCI 215 resets = <&gcc GCC_PCIE1_PHY_BCR>,
240 <&gcc GCC_PCI !! 216 <&gcc GCC_PCIE1PHY_PHY_BCR>;
241 reset-names = "phy", 217 reset-names = "phy",
242 "common" 218 "common";
243 status = "disabled"; 219 status = "disabled";
>> 220
>> 221 pcie_phy1: phy@8e200 {
>> 222 reg = <0x8e200 0x16c>,
>> 223 <0x8e400 0x200>,
>> 224 <0x8e800 0x4f4>;
>> 225 #phy-cells = <0>;
>> 226 #clock-cells = <0>;
>> 227 clocks = <&gcc GCC_PCIE1_PIPE_CLK>;
>> 228 clock-names = "pipe0";
>> 229 clock-output-names = "pcie_1_pipe_clk";
>> 230 };
244 }; 231 };
245 232
246 mdio: mdio@90000 { 233 mdio: mdio@90000 {
247 compatible = "qcom,ipq !! 234 compatible = "qcom,ipq4019-mdio";
248 reg = <0x00090000 0x64 235 reg = <0x00090000 0x64>;
249 #address-cells = <1>; 236 #address-cells = <1>;
250 #size-cells = <0>; 237 #size-cells = <0>;
251 238
252 clocks = <&gcc GCC_MDI 239 clocks = <&gcc GCC_MDIO_AHB_CLK>;
253 clock-names = "gcc_mdi 240 clock-names = "gcc_mdio_ahb_clk";
254 241
255 clock-frequency = <625 <<
256 <<
257 status = "disabled"; 242 status = "disabled";
258 }; 243 };
259 244
260 qfprom: efuse@a4000 { <<
261 compatible = "qcom,ipq <<
262 reg = <0x000a4000 0x20 <<
263 #address-cells = <1>; <<
264 #size-cells = <1>; <<
265 }; <<
266 <<
267 prng: rng@e3000 { 245 prng: rng@e3000 {
268 compatible = "qcom,prn 246 compatible = "qcom,prng-ee";
269 reg = <0x000e3000 0x10 247 reg = <0x000e3000 0x1000>;
270 clocks = <&gcc GCC_PRN 248 clocks = <&gcc GCC_PRNG_AHB_CLK>;
271 clock-names = "core"; 249 clock-names = "core";
272 status = "disabled"; 250 status = "disabled";
273 }; 251 };
274 252
275 tsens: thermal-sensor@4a9000 { <<
276 compatible = "qcom,ipq <<
277 reg = <0x4a9000 0x1000 <<
278 <0x4a8000 0x1000 <<
279 interrupts = <GIC_SPI <<
280 interrupt-names = "com <<
281 #qcom,sensors = <16>; <<
282 #thermal-sensor-cells <<
283 }; <<
284 <<
285 cryptobam: dma-controller@7040 253 cryptobam: dma-controller@704000 {
286 compatible = "qcom,bam 254 compatible = "qcom,bam-v1.7.0";
287 reg = <0x00704000 0x20 255 reg = <0x00704000 0x20000>;
288 interrupts = <GIC_SPI 256 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
289 clocks = <&gcc GCC_CRY 257 clocks = <&gcc GCC_CRYPTO_AHB_CLK>;
290 clock-names = "bam_clk 258 clock-names = "bam_clk";
291 #dma-cells = <1>; 259 #dma-cells = <1>;
292 qcom,ee = <1>; 260 qcom,ee = <1>;
293 qcom,controlled-remote 261 qcom,controlled-remotely;
294 status = "disabled"; 262 status = "disabled";
295 }; 263 };
296 264
297 crypto: crypto@73a000 { 265 crypto: crypto@73a000 {
298 compatible = "qcom,cry 266 compatible = "qcom,crypto-v5.1";
299 reg = <0x0073a000 0x60 267 reg = <0x0073a000 0x6000>;
300 clocks = <&gcc GCC_CRY 268 clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
301 <&gcc GCC_CRY 269 <&gcc GCC_CRYPTO_AXI_CLK>,
302 <&gcc GCC_CRY 270 <&gcc GCC_CRYPTO_CLK>;
303 clock-names = "iface", 271 clock-names = "iface", "bus", "core";
304 dmas = <&cryptobam 2>, 272 dmas = <&cryptobam 2>, <&cryptobam 3>;
305 dma-names = "rx", "tx" 273 dma-names = "rx", "tx";
306 status = "disabled"; 274 status = "disabled";
307 }; 275 };
308 276
309 tlmm: pinctrl@1000000 { 277 tlmm: pinctrl@1000000 {
310 compatible = "qcom,ipq 278 compatible = "qcom,ipq8074-pinctrl";
311 reg = <0x01000000 0x30 279 reg = <0x01000000 0x300000>;
312 interrupts = <GIC_SPI 280 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
313 gpio-controller; 281 gpio-controller;
314 gpio-ranges = <&tlmm 0 282 gpio-ranges = <&tlmm 0 0 70>;
315 #gpio-cells = <2>; !! 283 #gpio-cells = <0x2>;
316 interrupt-controller; 284 interrupt-controller;
317 #interrupt-cells = <2> !! 285 #interrupt-cells = <0x2>;
318 286
319 serial_4_pins: serial4 !! 287 serial_4_pins: serial4-pinmux {
320 pins = "gpio23 288 pins = "gpio23", "gpio24";
321 function = "bl 289 function = "blsp4_uart1";
322 drive-strength 290 drive-strength = <8>;
323 bias-disable; 291 bias-disable;
324 }; 292 };
325 293
326 serial_5_pins: serial5 !! 294 i2c_0_pins: i2c-0-pinmux {
327 pins = "gpio9" <<
328 function = "bl <<
329 drive-strength <<
330 bias-disable; <<
331 }; <<
332 <<
333 i2c_0_pins: i2c-0-stat <<
334 pins = "gpio42 295 pins = "gpio42", "gpio43";
335 function = "bl 296 function = "blsp1_i2c";
336 drive-strength 297 drive-strength = <8>;
337 bias-disable; 298 bias-disable;
338 }; 299 };
339 300
340 spi_0_pins: spi-0-stat !! 301 spi_0_pins: spi-0-pins {
341 pins = "gpio38 302 pins = "gpio38", "gpio39", "gpio40", "gpio41";
342 function = "bl 303 function = "blsp0_spi";
343 drive-strength 304 drive-strength = <8>;
344 bias-disable; 305 bias-disable;
345 }; 306 };
346 307
347 hsuart_pins: hsuart-st !! 308 hsuart_pins: hsuart-pins {
348 pins = "gpio46 309 pins = "gpio46", "gpio47", "gpio48", "gpio49";
349 function = "bl 310 function = "blsp2_uart";
350 drive-strength 311 drive-strength = <8>;
351 bias-disable; 312 bias-disable;
352 }; 313 };
353 314
354 qpic_pins: qpic-state !! 315 qpic_pins: qpic-pins {
355 pins = "gpio1" 316 pins = "gpio1", "gpio3", "gpio4",
356 "gpio5" 317 "gpio5", "gpio6", "gpio7",
357 "gpio8" 318 "gpio8", "gpio10", "gpio11",
358 "gpio12 319 "gpio12", "gpio13", "gpio14",
359 "gpio15 !! 320 "gpio15", "gpio16", "gpio17";
360 function = "qp 321 function = "qpic";
361 drive-strength 322 drive-strength = <8>;
362 bias-disable; 323 bias-disable;
363 }; 324 };
364 }; 325 };
365 326
366 gcc: clock-controller@1800000 !! 327 gcc: gcc@1800000 {
367 compatible = "qcom,gcc 328 compatible = "qcom,gcc-ipq8074";
368 reg = <0x01800000 0x80 329 reg = <0x01800000 0x80000>;
369 clocks = <&xo>, !! 330 #clock-cells = <0x1>;
370 <&sleep_clk>, !! 331 #reset-cells = <0x1>;
371 <&pcie_qmp0>, <<
372 <&pcie_qmp1>; <<
373 clock-names = "xo", <<
374 "sleep_c <<
375 "pcie0_p <<
376 "pcie1_p <<
377 #clock-cells = <1>; <<
378 #power-domain-cells = <<
379 #reset-cells = <1>; <<
380 }; <<
381 <<
382 tcsr_mutex: hwlock@1905000 { <<
383 compatible = "qcom,tcs <<
384 reg = <0x01905000 0x20 <<
385 #hwlock-cells = <1>; <<
386 }; <<
387 <<
388 tcsr: syscon@1937000 { <<
389 compatible = "qcom,tcs <<
390 reg = <0x01937000 0x21 <<
391 }; 332 };
392 333
393 spmi_bus: spmi@200f000 { 334 spmi_bus: spmi@200f000 {
394 compatible = "qcom,spm 335 compatible = "qcom,spmi-pmic-arb";
395 reg = <0x0200f000 0x00 336 reg = <0x0200f000 0x001000>,
396 <0x02400000 0x80 337 <0x02400000 0x800000>,
397 <0x02c00000 0x80 338 <0x02c00000 0x800000>,
398 <0x03800000 0x20 339 <0x03800000 0x200000>,
399 <0x0200a000 0x00 340 <0x0200a000 0x000700>;
400 reg-names = "core", "c 341 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
401 interrupts = <GIC_SPI 342 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
402 interrupt-names = "per 343 interrupt-names = "periph_irq";
403 qcom,ee = <0>; 344 qcom,ee = <0>;
404 qcom,channel = <0>; 345 qcom,channel = <0>;
405 #address-cells = <2>; 346 #address-cells = <2>;
406 #size-cells = <0>; 347 #size-cells = <0>;
407 interrupt-controller; 348 interrupt-controller;
408 #interrupt-cells = <4> 349 #interrupt-cells = <4>;
>> 350 cell-index = <0>;
409 }; 351 };
410 352
411 sdhc_1: mmc@7824900 { !! 353 sdhc_1: sdhci@7824900 {
412 compatible = "qcom,ipq !! 354 compatible = "qcom,sdhci-msm-v4";
413 reg = <0x7824900 0x500 355 reg = <0x7824900 0x500>, <0x7824000 0x800>;
414 reg-names = "hc", "cor !! 356 reg-names = "hc_mem", "core_mem";
415 357
416 interrupts = <GIC_SPI 358 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
417 <GIC_SPI 359 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
418 interrupt-names = "hc_ 360 interrupt-names = "hc_irq", "pwr_irq";
419 361
420 clocks = <&gcc GCC_SDC !! 362 clocks = <&xo>,
421 <&gcc GCC_SDC !! 363 <&gcc GCC_SDCC1_AHB_CLK>,
422 <&xo>; !! 364 <&gcc GCC_SDCC1_APPS_CLK>;
423 clock-names = "iface", !! 365 clock-names = "xo", "iface", "core";
424 resets = <&gcc GCC_SDC <<
425 max-frequency = <38400 366 max-frequency = <384000000>;
426 mmc-ddr-1_8v; 367 mmc-ddr-1_8v;
427 mmc-hs200-1_8v; 368 mmc-hs200-1_8v;
428 mmc-hs400-1_8v; 369 mmc-hs400-1_8v;
429 bus-width = <8>; 370 bus-width = <8>;
430 371
431 status = "disabled"; 372 status = "disabled";
432 }; 373 };
433 374
434 blsp_dma: dma-controller@78840 375 blsp_dma: dma-controller@7884000 {
435 compatible = "qcom,bam 376 compatible = "qcom,bam-v1.7.0";
436 reg = <0x07884000 0x2b 377 reg = <0x07884000 0x2b000>;
437 interrupts = <GIC_SPI 378 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
438 clocks = <&gcc GCC_BLS 379 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
439 clock-names = "bam_clk 380 clock-names = "bam_clk";
440 #dma-cells = <1>; 381 #dma-cells = <1>;
441 qcom,ee = <0>; 382 qcom,ee = <0>;
442 }; 383 };
443 384
444 blsp1_uart1: serial@78af000 { 385 blsp1_uart1: serial@78af000 {
445 compatible = "qcom,msm 386 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
446 reg = <0x078af000 0x20 387 reg = <0x078af000 0x200>;
447 interrupts = <GIC_SPI 388 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
448 clocks = <&gcc GCC_BLS 389 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
449 <&gcc GCC_BLS 390 <&gcc GCC_BLSP1_AHB_CLK>;
450 clock-names = "core", 391 clock-names = "core", "iface";
451 status = "disabled"; 392 status = "disabled";
452 }; 393 };
453 394
454 blsp1_uart3: serial@78b1000 { 395 blsp1_uart3: serial@78b1000 {
455 compatible = "qcom,msm 396 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
456 reg = <0x078b1000 0x20 397 reg = <0x078b1000 0x200>;
457 interrupts = <GIC_SPI 398 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
458 clocks = <&gcc GCC_BLS 399 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
459 <&gcc GCC_BLSP 400 <&gcc GCC_BLSP1_AHB_CLK>;
460 clock-names = "core", 401 clock-names = "core", "iface";
461 dmas = <&blsp_dma 4>, 402 dmas = <&blsp_dma 4>,
462 <&blsp_dma 5>; 403 <&blsp_dma 5>;
463 dma-names = "tx", "rx" 404 dma-names = "tx", "rx";
464 pinctrl-0 = <&hsuart_p 405 pinctrl-0 = <&hsuart_pins>;
465 pinctrl-names = "defau 406 pinctrl-names = "default";
466 status = "disabled"; 407 status = "disabled";
467 }; 408 };
468 409
469 blsp1_uart5: serial@78b3000 { 410 blsp1_uart5: serial@78b3000 {
470 compatible = "qcom,msm 411 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
471 reg = <0x078b3000 0x20 412 reg = <0x078b3000 0x200>;
472 interrupts = <GIC_SPI 413 interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
473 clocks = <&gcc GCC_BLS 414 clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>,
474 <&gcc GCC_BLS 415 <&gcc GCC_BLSP1_AHB_CLK>;
475 clock-names = "core", 416 clock-names = "core", "iface";
476 pinctrl-0 = <&serial_4 417 pinctrl-0 = <&serial_4_pins>;
477 pinctrl-names = "defau 418 pinctrl-names = "default";
478 status = "disabled"; 419 status = "disabled";
479 }; 420 };
480 421
481 blsp1_uart6: serial@78b4000 { <<
482 compatible = "qcom,msm <<
483 reg = <0x078b4000 0x20 <<
484 interrupts = <GIC_SPI <<
485 clocks = <&gcc GCC_BLS <<
486 <&gcc GCC_BLS <<
487 clock-names = "core", <<
488 pinctrl-0 = <&serial_5 <<
489 pinctrl-names = "defau <<
490 status = "disabled"; <<
491 }; <<
492 <<
493 blsp1_spi1: spi@78b5000 { 422 blsp1_spi1: spi@78b5000 {
494 compatible = "qcom,spi 423 compatible = "qcom,spi-qup-v2.2.1";
495 #address-cells = <1>; 424 #address-cells = <1>;
496 #size-cells = <0>; 425 #size-cells = <0>;
497 reg = <0x078b5000 0x60 426 reg = <0x078b5000 0x600>;
498 interrupts = <GIC_SPI 427 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
>> 428 spi-max-frequency = <50000000>;
499 clocks = <&gcc GCC_BLS 429 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
500 <&gcc GCC_BLSP 430 <&gcc GCC_BLSP1_AHB_CLK>;
501 clock-names = "core", 431 clock-names = "core", "iface";
502 dmas = <&blsp_dma 12>, 432 dmas = <&blsp_dma 12>, <&blsp_dma 13>;
503 dma-names = "tx", "rx" 433 dma-names = "tx", "rx";
504 pinctrl-0 = <&spi_0_pi 434 pinctrl-0 = <&spi_0_pins>;
505 pinctrl-names = "defau 435 pinctrl-names = "default";
506 status = "disabled"; 436 status = "disabled";
507 }; 437 };
508 438
509 blsp1_i2c2: i2c@78b6000 { 439 blsp1_i2c2: i2c@78b6000 {
510 compatible = "qcom,i2c 440 compatible = "qcom,i2c-qup-v2.2.1";
511 #address-cells = <1>; 441 #address-cells = <1>;
512 #size-cells = <0>; 442 #size-cells = <0>;
513 reg = <0x078b6000 0x60 443 reg = <0x078b6000 0x600>;
514 interrupts = <GIC_SPI 444 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
515 clocks = <&gcc GCC_BLS !! 445 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
516 <&gcc GCC_BLS !! 446 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
517 clock-names = "core", !! 447 clock-names = "iface", "core";
518 clock-frequency = <400 448 clock-frequency = <400000>;
519 dmas = <&blsp_dma 14>, !! 449 dmas = <&blsp_dma 15>, <&blsp_dma 14>;
520 dma-names = "tx", "rx" !! 450 dma-names = "rx", "tx";
521 pinctrl-0 = <&i2c_0_pi 451 pinctrl-0 = <&i2c_0_pins>;
522 pinctrl-names = "defau 452 pinctrl-names = "default";
523 status = "disabled"; 453 status = "disabled";
524 }; 454 };
525 455
526 blsp1_i2c3: i2c@78b7000 { 456 blsp1_i2c3: i2c@78b7000 {
527 compatible = "qcom,i2c 457 compatible = "qcom,i2c-qup-v2.2.1";
528 #address-cells = <1>; 458 #address-cells = <1>;
529 #size-cells = <0>; 459 #size-cells = <0>;
530 reg = <0x078b7000 0x60 460 reg = <0x078b7000 0x600>;
531 interrupts = <GIC_SPI 461 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
532 clocks = <&gcc GCC_BLS !! 462 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
533 <&gcc GCC_BLS !! 463 <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
534 clock-names = "core", !! 464 clock-names = "iface", "core";
535 clock-frequency = <100 465 clock-frequency = <100000>;
536 dmas = <&blsp_dma 16>, !! 466 dmas = <&blsp_dma 17>, <&blsp_dma 16>;
537 dma-names = "tx", "rx" !! 467 dma-names = "rx", "tx";
538 status = "disabled"; <<
539 }; <<
540 <<
541 blsp1_spi4: spi@78b8000 { <<
542 compatible = "qcom,spi <<
543 #address-cells = <1>; <<
544 #size-cells = <0>; <<
545 reg = <0x78b8000 0x600 <<
546 interrupts = <GIC_SPI <<
547 clocks = <&gcc GCC_BLS <<
548 <&gcc GCC_BLS <<
549 clock-names = "core", <<
550 dmas = <&blsp_dma 18>, <<
551 dma-names = "tx", "rx" <<
552 status = "disabled"; 468 status = "disabled";
553 }; 469 };
554 470
555 blsp1_i2c5: i2c@78b9000 { 471 blsp1_i2c5: i2c@78b9000 {
556 compatible = "qcom,i2c 472 compatible = "qcom,i2c-qup-v2.2.1";
557 #address-cells = <1>; 473 #address-cells = <1>;
558 #size-cells = <0>; 474 #size-cells = <0>;
559 reg = <0x78b9000 0x600 475 reg = <0x78b9000 0x600>;
560 interrupts = <GIC_SPI 476 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
561 clocks = <&gcc GCC_BLS !! 477 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
562 <&gcc GCC_BLS !! 478 <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>;
563 clock-names = "core", !! 479 clock-names = "iface", "core";
564 clock-frequency = <400 480 clock-frequency = <400000>;
565 dmas = <&blsp_dma 20>, !! 481 dmas = <&blsp_dma 21>, <&blsp_dma 20>;
566 dma-names = "tx", "rx" !! 482 dma-names = "rx", "tx";
567 status = "disabled"; <<
568 }; <<
569 <<
570 blsp1_spi5: spi@78b9000 { <<
571 compatible = "qcom,spi <<
572 #address-cells = <1>; <<
573 #size-cells = <0>; <<
574 reg = <0x78b9000 0x600 <<
575 interrupts = <GIC_SPI <<
576 clocks = <&gcc GCC_BLS <<
577 <&gcc GCC_BLS <<
578 clock-names = "core", <<
579 dmas = <&blsp_dma 20>, <<
580 dma-names = "tx", "rx" <<
581 status = "disabled"; 483 status = "disabled";
582 }; 484 };
583 485
584 blsp1_i2c6: i2c@78ba000 { 486 blsp1_i2c6: i2c@78ba000 {
585 compatible = "qcom,i2c 487 compatible = "qcom,i2c-qup-v2.2.1";
586 #address-cells = <1>; 488 #address-cells = <1>;
587 #size-cells = <0>; 489 #size-cells = <0>;
588 reg = <0x078ba000 0x60 490 reg = <0x078ba000 0x600>;
589 interrupts = <GIC_SPI 491 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
590 clocks = <&gcc GCC_BLS !! 492 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
591 <&gcc GCC_BLS !! 493 <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;
592 clock-names = "core", !! 494 clock-names = "iface", "core";
593 clock-frequency = <100 495 clock-frequency = <100000>;
594 dmas = <&blsp_dma 22>, !! 496 dmas = <&blsp_dma 23>, <&blsp_dma 22>;
595 dma-names = "tx", "rx" !! 497 dma-names = "rx", "tx";
596 status = "disabled"; 498 status = "disabled";
597 }; 499 };
598 500
599 qpic_bam: dma-controller@79840 501 qpic_bam: dma-controller@7984000 {
600 compatible = "qcom,bam 502 compatible = "qcom,bam-v1.7.0";
601 reg = <0x07984000 0x1a 503 reg = <0x07984000 0x1a000>;
602 interrupts = <GIC_SPI 504 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
603 clocks = <&gcc GCC_QPI 505 clocks = <&gcc GCC_QPIC_AHB_CLK>;
604 clock-names = "bam_clk 506 clock-names = "bam_clk";
605 #dma-cells = <1>; 507 #dma-cells = <1>;
606 qcom,ee = <0>; 508 qcom,ee = <0>;
607 status = "disabled"; 509 status = "disabled";
608 }; 510 };
609 511
610 qpic_nand: nand-controller@79b !! 512 qpic_nand: nand@79b0000 {
611 compatible = "qcom,ipq 513 compatible = "qcom,ipq8074-nand";
612 reg = <0x079b0000 0x10 514 reg = <0x079b0000 0x10000>;
613 #address-cells = <1>; 515 #address-cells = <1>;
614 #size-cells = <0>; 516 #size-cells = <0>;
615 clocks = <&gcc GCC_QPI 517 clocks = <&gcc GCC_QPIC_CLK>,
616 <&gcc GCC_QPI 518 <&gcc GCC_QPIC_AHB_CLK>;
617 clock-names = "core", 519 clock-names = "core", "aon";
618 520
619 dmas = <&qpic_bam 0>, 521 dmas = <&qpic_bam 0>,
620 <&qpic_bam 1>, 522 <&qpic_bam 1>,
621 <&qpic_bam 2>; 523 <&qpic_bam 2>;
622 dma-names = "tx", "rx" 524 dma-names = "tx", "rx", "cmd";
623 pinctrl-0 = <&qpic_pin 525 pinctrl-0 = <&qpic_pins>;
624 pinctrl-names = "defau 526 pinctrl-names = "default";
625 status = "disabled"; 527 status = "disabled";
626 }; 528 };
627 529
628 usb_0: usb@8af8800 { 530 usb_0: usb@8af8800 {
629 compatible = "qcom,ipq !! 531 compatible = "qcom,dwc3";
630 reg = <0x08af8800 0x40 532 reg = <0x08af8800 0x400>;
631 #address-cells = <1>; 533 #address-cells = <1>;
632 #size-cells = <1>; 534 #size-cells = <1>;
633 ranges; 535 ranges;
634 536
635 clocks = <&gcc GCC_SYS 537 clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
636 <&gcc GCC_USB0 538 <&gcc GCC_USB0_MASTER_CLK>,
637 <&gcc GCC_USB0 539 <&gcc GCC_USB0_SLEEP_CLK>,
638 <&gcc GCC_USB0 540 <&gcc GCC_USB0_MOCK_UTMI_CLK>;
639 clock-names = "cfg_noc !! 541 clock-names = "sys_noc_axi",
640 "core", !! 542 "master",
641 "sleep", 543 "sleep",
642 "mock_utmi"; 544 "mock_utmi";
643 545
644 assigned-clocks = <&gc 546 assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
645 <&gc 547 <&gcc GCC_USB0_MASTER_CLK>,
646 <&gc 548 <&gcc GCC_USB0_MOCK_UTMI_CLK>;
647 assigned-clock-rates = 549 assigned-clock-rates = <133330000>,
648 550 <133330000>,
649 551 <19200000>;
650 552
651 interrupts = <GIC_SPI <<
652 <GIC_SPI <<
653 <GIC_SPI <<
654 interrupt-names = "pwr <<
655 "qus <<
656 "ss_ <<
657 <<
658 power-domains = <&gcc <<
659 <<
660 resets = <&gcc GCC_USB 553 resets = <&gcc GCC_USB0_BCR>;
661 status = "disabled"; 554 status = "disabled";
662 555
663 dwc_0: usb@8a00000 { !! 556 dwc_0: dwc3@8a00000 {
664 compatible = " 557 compatible = "snps,dwc3";
665 reg = <0x8a000 558 reg = <0x8a00000 0xcd00>;
666 interrupts = < 559 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
667 phys = <&qusb_ !! 560 phys = <&qusb_phy_0>, <&usb0_ssphy>;
668 phy-names = "u 561 phy-names = "usb2-phy", "usb3-phy";
669 snps,parkmode- <<
670 snps,is-utmi-l 562 snps,is-utmi-l1-suspend;
671 snps,hird-thre 563 snps,hird-threshold = /bits/ 8 <0x0>;
672 snps,dis_u2_su 564 snps,dis_u2_susphy_quirk;
673 snps,dis_u3_su 565 snps,dis_u3_susphy_quirk;
674 dr_mode = "hos 566 dr_mode = "host";
675 }; 567 };
676 }; 568 };
677 569
678 usb_1: usb@8cf8800 { 570 usb_1: usb@8cf8800 {
679 compatible = "qcom,ipq !! 571 compatible = "qcom,dwc3";
680 reg = <0x08cf8800 0x40 572 reg = <0x08cf8800 0x400>;
681 #address-cells = <1>; 573 #address-cells = <1>;
682 #size-cells = <1>; 574 #size-cells = <1>;
683 ranges; 575 ranges;
684 576
685 clocks = <&gcc GCC_SYS 577 clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>,
686 <&gcc GCC_USB1 578 <&gcc GCC_USB1_MASTER_CLK>,
687 <&gcc GCC_USB1 579 <&gcc GCC_USB1_SLEEP_CLK>,
688 <&gcc GCC_USB1 580 <&gcc GCC_USB1_MOCK_UTMI_CLK>;
689 clock-names = "cfg_noc !! 581 clock-names = "sys_noc_axi",
690 "core", !! 582 "master",
691 "sleep", 583 "sleep",
692 "mock_utmi"; 584 "mock_utmi";
693 585
694 assigned-clocks = <&gc 586 assigned-clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>,
695 <&gc 587 <&gcc GCC_USB1_MASTER_CLK>,
696 <&gc 588 <&gcc GCC_USB1_MOCK_UTMI_CLK>;
697 assigned-clock-rates = 589 assigned-clock-rates = <133330000>,
698 590 <133330000>,
699 591 <19200000>;
700 592
701 interrupts = <GIC_SPI <<
702 <GIC_SPI <<
703 <GIC_SPI <<
704 interrupt-names = "pwr <<
705 "qus <<
706 "ss_ <<
707 <<
708 power-domains = <&gcc <<
709 <<
710 resets = <&gcc GCC_USB 593 resets = <&gcc GCC_USB1_BCR>;
711 status = "disabled"; 594 status = "disabled";
712 595
713 dwc_1: usb@8c00000 { !! 596 dwc_1: dwc3@8c00000 {
714 compatible = " 597 compatible = "snps,dwc3";
715 reg = <0x8c000 598 reg = <0x8c00000 0xcd00>;
716 interrupts = < 599 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
717 phys = <&qusb_ !! 600 phys = <&qusb_phy_1>, <&usb1_ssphy>;
718 phy-names = "u 601 phy-names = "usb2-phy", "usb3-phy";
719 snps,parkmode- <<
720 snps,is-utmi-l 602 snps,is-utmi-l1-suspend;
721 snps,hird-thre 603 snps,hird-threshold = /bits/ 8 <0x0>;
722 snps,dis_u2_su 604 snps,dis_u2_susphy_quirk;
723 snps,dis_u3_su 605 snps,dis_u3_susphy_quirk;
724 dr_mode = "hos 606 dr_mode = "host";
725 }; 607 };
726 }; 608 };
727 609
728 intc: interrupt-controller@b00 610 intc: interrupt-controller@b000000 {
729 compatible = "qcom,msm 611 compatible = "qcom,msm-qgic2";
730 #address-cells = <1>; <<
731 #size-cells = <1>; <<
732 interrupt-controller; 612 interrupt-controller;
733 #interrupt-cells = <3> !! 613 #interrupt-cells = <0x3>;
734 reg = <0x0b000000 0x10 614 reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
735 ranges = <0 0xb00a000 !! 615 };
736 616
737 v2m@0 { !! 617 timer {
738 compatible = " !! 618 compatible = "arm,armv8-timer";
739 msi-controller !! 619 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
740 reg = <0x0 0xf !! 620 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
741 }; !! 621 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
>> 622 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
742 }; 623 };
743 624
744 watchdog: watchdog@b017000 { 625 watchdog: watchdog@b017000 {
745 compatible = "qcom,kps 626 compatible = "qcom,kpss-wdt";
746 reg = <0xb017000 0x100 627 reg = <0xb017000 0x1000>;
747 interrupts = <GIC_SPI 628 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
748 clocks = <&sleep_clk>; 629 clocks = <&sleep_clk>;
749 timeout-sec = <30>; 630 timeout-sec = <30>;
750 }; 631 };
751 632
752 apcs_glb: mailbox@b111000 { <<
753 compatible = "qcom,ipq <<
754 "qcom,ipq <<
755 reg = <0x0b111000 0x10 <<
756 clocks = <&a53pll>, <& <<
757 clock-names = "pll", " <<
758 <<
759 #clock-cells = <1>; <<
760 #mbox-cells = <1>; <<
761 }; <<
762 <<
763 a53pll: clock@b116000 { <<
764 compatible = "qcom,ipq <<
765 reg = <0x0b116000 0x40 <<
766 #clock-cells = <0>; <<
767 clocks = <&xo>; <<
768 clock-names = "xo"; <<
769 }; <<
770 <<
771 timer@b120000 { 633 timer@b120000 {
772 #address-cells = <1>; 634 #address-cells = <1>;
773 #size-cells = <1>; 635 #size-cells = <1>;
774 ranges; 636 ranges;
775 compatible = "arm,armv 637 compatible = "arm,armv7-timer-mem";
776 reg = <0x0b120000 0x10 638 reg = <0x0b120000 0x1000>;
>> 639 clock-frequency = <19200000>;
777 640
778 frame@b120000 { 641 frame@b120000 {
779 frame-number = 642 frame-number = <0>;
780 interrupts = < 643 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
781 < 644 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
782 reg = <0x0b121 645 reg = <0x0b121000 0x1000>,
783 <0x0b122 646 <0x0b122000 0x1000>;
784 }; 647 };
785 648
786 frame@b123000 { 649 frame@b123000 {
787 frame-number = 650 frame-number = <1>;
788 interrupts = < 651 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
789 reg = <0x0b123 652 reg = <0x0b123000 0x1000>;
790 status = "disa 653 status = "disabled";
791 }; 654 };
792 655
793 frame@b124000 { 656 frame@b124000 {
794 frame-number = 657 frame-number = <2>;
795 interrupts = < 658 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
796 reg = <0x0b124 659 reg = <0x0b124000 0x1000>;
797 status = "disa 660 status = "disabled";
798 }; 661 };
799 662
800 frame@b125000 { 663 frame@b125000 {
801 frame-number = 664 frame-number = <3>;
802 interrupts = < 665 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
803 reg = <0x0b125 666 reg = <0x0b125000 0x1000>;
804 status = "disa 667 status = "disabled";
805 }; 668 };
806 669
807 frame@b126000 { 670 frame@b126000 {
808 frame-number = 671 frame-number = <4>;
809 interrupts = < 672 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
810 reg = <0x0b126 673 reg = <0x0b126000 0x1000>;
811 status = "disa 674 status = "disabled";
812 }; 675 };
813 676
814 frame@b127000 { 677 frame@b127000 {
815 frame-number = 678 frame-number = <5>;
816 interrupts = < 679 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
817 reg = <0x0b127 680 reg = <0x0b127000 0x1000>;
818 status = "disa 681 status = "disabled";
819 }; 682 };
820 683
821 frame@b128000 { 684 frame@b128000 {
822 frame-number = 685 frame-number = <6>;
823 interrupts = < 686 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
824 reg = <0x0b128 687 reg = <0x0b128000 0x1000>;
825 status = "disa 688 status = "disabled";
826 }; 689 };
827 }; 690 };
828 691
829 pcie1: pcie@10000000 { !! 692 pcie1: pci@10000000 {
830 compatible = "qcom,pci 693 compatible = "qcom,pcie-ipq8074";
831 reg = <0x10000000 0xf1 !! 694 reg = <0x10000000 0xf1d>,
832 <0x10000f20 0xa8 !! 695 <0x10000f20 0xa8>,
833 <0x00088000 0x20 !! 696 <0x00088000 0x2000>,
834 <0x10100000 0x10 !! 697 <0x10100000 0x1000>;
835 reg-names = "dbi", "el 698 reg-names = "dbi", "elbi", "parf", "config";
836 device_type = "pci"; 699 device_type = "pci";
837 linux,pci-domain = <1> 700 linux,pci-domain = <1>;
838 bus-range = <0x00 0xff 701 bus-range = <0x00 0xff>;
839 num-lanes = <1>; 702 num-lanes = <1>;
840 max-link-speed = <2>; <<
841 #address-cells = <3>; 703 #address-cells = <3>;
842 #size-cells = <2>; 704 #size-cells = <2>;
843 705
844 phys = <&pcie_qmp1>; !! 706 phys = <&pcie_phy1>;
845 phy-names = "pciephy"; 707 phy-names = "pciephy";
846 708
847 ranges = <0x81000000 0 !! 709 ranges = <0x81000000 0 0x10200000 0x10200000
848 <0x82000000 0 !! 710 0 0x100000 /* downstream I/O */
>> 711 0x82000000 0 0x10300000 0x10300000
>> 712 0 0xd00000>; /* non-prefetchable memory */
849 713
850 interrupts = <GIC_SPI 714 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
851 interrupt-names = "msi 715 interrupt-names = "msi";
852 #interrupt-cells = <1> 716 #interrupt-cells = <1>;
853 interrupt-map-mask = < 717 interrupt-map-mask = <0 0 0 0x7>;
854 interrupt-map = <0 0 0 !! 718 interrupt-map = <0 0 0 1 &intc 0 142
855 IRQ_T 719 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
856 <0 0 0 !! 720 <0 0 0 2 &intc 0 143
857 IRQ_T 721 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
858 <0 0 0 !! 722 <0 0 0 3 &intc 0 144
859 IRQ_T 723 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
860 <0 0 0 !! 724 <0 0 0 4 &intc 0 145
861 IRQ_T 725 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
862 726
863 clocks = <&gcc GCC_SYS 727 clocks = <&gcc GCC_SYS_NOC_PCIE1_AXI_CLK>,
864 <&gcc GCC_PCI 728 <&gcc GCC_PCIE1_AXI_M_CLK>,
865 <&gcc GCC_PCI 729 <&gcc GCC_PCIE1_AXI_S_CLK>,
866 <&gcc GCC_PCI 730 <&gcc GCC_PCIE1_AHB_CLK>,
867 <&gcc GCC_PCI 731 <&gcc GCC_PCIE1_AUX_CLK>;
868 clock-names = "iface", 732 clock-names = "iface",
869 "axi_m", 733 "axi_m",
870 "axi_s", 734 "axi_s",
871 "ahb", 735 "ahb",
872 "aux"; 736 "aux";
873 resets = <&gcc GCC_PCI 737 resets = <&gcc GCC_PCIE1_PIPE_ARES>,
874 <&gcc GCC_PCI 738 <&gcc GCC_PCIE1_SLEEP_ARES>,
875 <&gcc GCC_PCI 739 <&gcc GCC_PCIE1_CORE_STICKY_ARES>,
876 <&gcc GCC_PCI 740 <&gcc GCC_PCIE1_AXI_MASTER_ARES>,
877 <&gcc GCC_PCI 741 <&gcc GCC_PCIE1_AXI_SLAVE_ARES>,
878 <&gcc GCC_PCI 742 <&gcc GCC_PCIE1_AHB_ARES>,
879 <&gcc GCC_PCI 743 <&gcc GCC_PCIE1_AXI_MASTER_STICKY_ARES>;
880 reset-names = "pipe", 744 reset-names = "pipe",
881 "sleep", 745 "sleep",
882 "sticky" 746 "sticky",
883 "axi_m", 747 "axi_m",
884 "axi_s", 748 "axi_s",
885 "ahb", 749 "ahb",
886 "axi_m_s 750 "axi_m_sticky";
887 status = "disabled"; 751 status = "disabled";
888 <<
889 pcie@0 { <<
890 device_type = <<
891 reg = <0x0 0x0 <<
892 bus-range = <0 <<
893 <<
894 #address-cells <<
895 #size-cells = <<
896 ranges; <<
897 }; <<
898 }; 752 };
899 753
900 pcie0: pcie@20000000 { !! 754 pcie0: pci@20000000 {
901 compatible = "qcom,pci !! 755 compatible = "qcom,pcie-ipq8074";
902 reg = <0x20000000 0xf1 756 reg = <0x20000000 0xf1d>,
903 <0x20000f20 0xa8 757 <0x20000f20 0xa8>,
904 <0x20001000 0x10 !! 758 <0x00080000 0x2000>,
905 <0x00080000 0x40 <<
906 <0x20100000 0x10 759 <0x20100000 0x1000>;
907 reg-names = "dbi", "el !! 760 reg-names = "dbi", "elbi", "parf", "config";
908 device_type = "pci"; 761 device_type = "pci";
909 linux,pci-domain = <0> 762 linux,pci-domain = <0>;
910 bus-range = <0x00 0xff 763 bus-range = <0x00 0xff>;
911 num-lanes = <1>; 764 num-lanes = <1>;
912 max-link-speed = <3>; <<
913 #address-cells = <3>; 765 #address-cells = <3>;
914 #size-cells = <2>; 766 #size-cells = <2>;
915 767
916 phys = <&pcie_qmp0>; !! 768 phys = <&pcie_phy0>;
917 phy-names = "pciephy"; 769 phy-names = "pciephy";
918 770
919 ranges = <0x81000000 0 !! 771 ranges = <0x81000000 0 0x20200000 0x20200000
920 <0x82000000 0 !! 772 0 0x100000 /* downstream I/O */
>> 773 0x82000000 0 0x20300000 0x20300000
>> 774 0 0xd00000>; /* non-prefetchable memory */
921 775
922 interrupts = <GIC_SPI 776 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
923 interrupt-names = "msi 777 interrupt-names = "msi";
924 #interrupt-cells = <1> 778 #interrupt-cells = <1>;
925 interrupt-map-mask = < 779 interrupt-map-mask = <0 0 0 0x7>;
926 interrupt-map = <0 0 0 !! 780 interrupt-map = <0 0 0 1 &intc 0 75
927 IRQ_T 781 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
928 <0 0 0 !! 782 <0 0 0 2 &intc 0 78
929 IRQ_T 783 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
930 <0 0 0 !! 784 <0 0 0 3 &intc 0 79
931 IRQ_T 785 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
932 <0 0 0 !! 786 <0 0 0 4 &intc 0 83
933 IRQ_T 787 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
934 788
935 clocks = <&gcc GCC_SYS 789 clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
936 <&gcc GCC_PCI 790 <&gcc GCC_PCIE0_AXI_M_CLK>,
937 <&gcc GCC_PCI 791 <&gcc GCC_PCIE0_AXI_S_CLK>,
938 <&gcc GCC_PCI !! 792 <&gcc GCC_PCIE0_AHB_CLK>,
939 <&gcc GCC_PCI !! 793 <&gcc GCC_PCIE0_AUX_CLK>;
>> 794
940 clock-names = "iface", 795 clock-names = "iface",
941 "axi_m", 796 "axi_m",
942 "axi_s", 797 "axi_s",
943 "axi_bri !! 798 "ahb",
944 "rchng"; !! 799 "aux";
945 <<
946 resets = <&gcc GCC_PCI 800 resets = <&gcc GCC_PCIE0_PIPE_ARES>,
947 <&gcc GCC_PCI 801 <&gcc GCC_PCIE0_SLEEP_ARES>,
948 <&gcc GCC_PCI 802 <&gcc GCC_PCIE0_CORE_STICKY_ARES>,
949 <&gcc GCC_PCI 803 <&gcc GCC_PCIE0_AXI_MASTER_ARES>,
950 <&gcc GCC_PCI 804 <&gcc GCC_PCIE0_AXI_SLAVE_ARES>,
951 <&gcc GCC_PCI 805 <&gcc GCC_PCIE0_AHB_ARES>,
952 <&gcc GCC_PCI !! 806 <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>;
953 <&gcc GCC_PCI <<
954 reset-names = "pipe", 807 reset-names = "pipe",
955 "sleep", 808 "sleep",
956 "sticky" 809 "sticky",
957 "axi_m", 810 "axi_m",
958 "axi_s", 811 "axi_s",
959 "ahb", 812 "ahb",
960 "axi_m_s !! 813 "axi_m_sticky";
961 "axi_s_s <<
962 status = "disabled"; 814 status = "disabled";
963 <<
964 pcie@0 { <<
965 device_type = <<
966 reg = <0x0 0x0 <<
967 bus-range = <0 <<
968 <<
969 #address-cells <<
970 #size-cells = <<
971 ranges; <<
972 }; <<
973 }; <<
974 }; <<
975 <<
976 timer { <<
977 compatible = "arm,armv8-timer" <<
978 interrupts = <GIC_PPI 2 (GIC_C <<
979 <GIC_PPI 3 (GIC_C <<
980 <GIC_PPI 4 (GIC_C <<
981 <GIC_PPI 1 (GIC_C <<
982 }; <<
983 <<
984 thermal-zones { <<
985 nss-top-thermal { <<
986 polling-delay-passive <<
987 <<
988 thermal-sensors = <&ts <<
989 <<
990 trips { <<
991 nss-top-crit { <<
992 temper <<
993 hyster <<
994 type = <<
995 }; <<
996 }; <<
997 }; <<
998 <<
999 nss0-thermal { <<
1000 polling-delay-passive <<
1001 <<
1002 thermal-sensors = <&t <<
1003 <<
1004 trips { <<
1005 nss-0-crit { <<
1006 tempe <<
1007 hyste <<
1008 type <<
1009 }; <<
1010 }; <<
1011 }; <<
1012 <<
1013 nss1-thermal { <<
1014 polling-delay-passive <<
1015 <<
1016 thermal-sensors = <&t <<
1017 <<
1018 trips { <<
1019 nss-1-crit { <<
1020 tempe <<
1021 hyste <<
1022 type <<
1023 }; <<
1024 }; <<
1025 }; <<
1026 <<
1027 wcss-phya0-thermal { <<
1028 polling-delay-passive <<
1029 <<
1030 thermal-sensors = <&t <<
1031 <<
1032 trips { <<
1033 wcss-phya0-cr <<
1034 tempe <<
1035 hyste <<
1036 type <<
1037 }; <<
1038 }; <<
1039 }; <<
1040 <<
1041 wcss-phya1-thermal { <<
1042 polling-delay-passive <<
1043 <<
1044 thermal-sensors = <&t <<
1045 <<
1046 trips { <<
1047 wcss-phya1-cr <<
1048 tempe <<
1049 hyste <<
1050 type <<
1051 }; <<
1052 }; <<
1053 }; <<
1054 <<
1055 cpu0_thermal: cpu0-thermal { <<
1056 polling-delay-passive <<
1057 <<
1058 thermal-sensors = <&t <<
1059 <<
1060 trips { <<
1061 cpu0-crit { <<
1062 tempe <<
1063 hyste <<
1064 type <<
1065 }; <<
1066 }; <<
1067 }; <<
1068 <<
1069 cpu1_thermal: cpu1-thermal { <<
1070 polling-delay-passive <<
1071 <<
1072 thermal-sensors = <&t <<
1073 <<
1074 trips { <<
1075 cpu1-crit { <<
1076 tempe <<
1077 hyste <<
1078 type <<
1079 }; <<
1080 }; <<
1081 }; <<
1082 <<
1083 cpu2_thermal: cpu2-thermal { <<
1084 polling-delay-passive <<
1085 <<
1086 thermal-sensors = <&t <<
1087 <<
1088 trips { <<
1089 cpu2-crit { <<
1090 tempe <<
1091 hyste <<
1092 type <<
1093 }; <<
1094 }; <<
1095 }; <<
1096 <<
1097 cpu3_thermal: cpu3-thermal { <<
1098 polling-delay-passive <<
1099 <<
1100 thermal-sensors = <&t <<
1101 <<
1102 trips { <<
1103 cpu3-crit { <<
1104 tempe <<
1105 hyste <<
1106 type <<
1107 }; <<
1108 }; <<
1109 }; <<
1110 <<
1111 cluster_thermal: cluster-ther <<
1112 polling-delay-passive <<
1113 <<
1114 thermal-sensors = <&t <<
1115 <<
1116 trips { <<
1117 cluster-crit <<
1118 tempe <<
1119 hyste <<
1120 type <<
1121 }; <<
1122 }; <<
1123 }; <<
1124 <<
1125 wcss-phyb0-thermal { <<
1126 polling-delay-passive <<
1127 <<
1128 thermal-sensors = <&t <<
1129 <<
1130 trips { <<
1131 wcss-phyb0-cr <<
1132 tempe <<
1133 hyste <<
1134 type <<
1135 }; <<
1136 }; <<
1137 }; <<
1138 <<
1139 wcss-phyb1-thermal { <<
1140 polling-delay-passive <<
1141 <<
1142 thermal-sensors = <&t <<
1143 <<
1144 trips { <<
1145 wcss-phyb1-cr <<
1146 tempe <<
1147 hyste <<
1148 type <<
1149 }; <<
1150 }; <<
1151 }; 815 };
1152 }; 816 };
1153 }; 817 };
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.