1 // SPDX-License-Identifier: GPL-2.0-only 1 // SPDX-License-Identifier: GPL-2.0-only
2 /* 2 /*
3 * Copyright (c) 2017, The Linux Foundation. A 3 * Copyright (c) 2017, The Linux Foundation. All rights reserved.
4 */ 4 */
5 5
6 #include <dt-bindings/interrupt-controller/arm 6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,gcc-ipq8074.h 7 #include <dt-bindings/clock/qcom,gcc-ipq8074.h>
8 8
9 / { 9 / {
10 #address-cells = <2>; <<
11 #size-cells = <2>; <<
12 <<
13 model = "Qualcomm Technologies, Inc. I 10 model = "Qualcomm Technologies, Inc. IPQ8074";
14 compatible = "qcom,ipq8074"; 11 compatible = "qcom,ipq8074";
15 interrupt-parent = <&intc>; <<
16 12
17 clocks { 13 clocks {
18 sleep_clk: sleep_clk { 14 sleep_clk: sleep_clk {
19 compatible = "fixed-cl 15 compatible = "fixed-clock";
20 clock-frequency = <327 !! 16 clock-frequency = <32000>;
21 #clock-cells = <0>; 17 #clock-cells = <0>;
22 }; 18 };
23 19
24 xo: xo { 20 xo: xo {
25 compatible = "fixed-cl 21 compatible = "fixed-clock";
26 clock-frequency = <192 22 clock-frequency = <19200000>;
27 #clock-cells = <0>; 23 #clock-cells = <0>;
28 }; 24 };
29 }; 25 };
30 26
31 cpus { 27 cpus {
32 #address-cells = <1>; !! 28 #address-cells = <0x1>;
33 #size-cells = <0>; !! 29 #size-cells = <0x0>;
34 30
35 CPU0: cpu@0 { 31 CPU0: cpu@0 {
36 device_type = "cpu"; 32 device_type = "cpu";
37 compatible = "arm,cort 33 compatible = "arm,cortex-a53";
38 reg = <0x0>; 34 reg = <0x0>;
39 next-level-cache = <&L 35 next-level-cache = <&L2_0>;
40 enable-method = "psci" 36 enable-method = "psci";
41 }; 37 };
42 38
43 CPU1: cpu@1 { 39 CPU1: cpu@1 {
44 device_type = "cpu"; 40 device_type = "cpu";
45 compatible = "arm,cort 41 compatible = "arm,cortex-a53";
46 enable-method = "psci" 42 enable-method = "psci";
47 reg = <0x1>; 43 reg = <0x1>;
48 next-level-cache = <&L 44 next-level-cache = <&L2_0>;
49 }; 45 };
50 46
51 CPU2: cpu@2 { 47 CPU2: cpu@2 {
52 device_type = "cpu"; 48 device_type = "cpu";
53 compatible = "arm,cort 49 compatible = "arm,cortex-a53";
54 enable-method = "psci" 50 enable-method = "psci";
55 reg = <0x2>; 51 reg = <0x2>;
56 next-level-cache = <&L 52 next-level-cache = <&L2_0>;
57 }; 53 };
58 54
59 CPU3: cpu@3 { 55 CPU3: cpu@3 {
60 device_type = "cpu"; 56 device_type = "cpu";
61 compatible = "arm,cort 57 compatible = "arm,cortex-a53";
62 enable-method = "psci" 58 enable-method = "psci";
63 reg = <0x3>; 59 reg = <0x3>;
64 next-level-cache = <&L 60 next-level-cache = <&L2_0>;
65 }; 61 };
66 62
67 L2_0: l2-cache { 63 L2_0: l2-cache {
68 compatible = "cache"; 64 compatible = "cache";
69 cache-level = <2>; !! 65 cache-level = <0x2>;
70 cache-unified; <<
71 }; 66 };
72 }; 67 };
73 68
74 pmu { 69 pmu {
75 compatible = "arm,cortex-a53-p !! 70 compatible = "arm,armv8-pmuv3";
76 interrupts = <GIC_PPI 7 (GIC_C 71 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
77 }; 72 };
78 73
79 psci { 74 psci {
80 compatible = "arm,psci-1.0"; 75 compatible = "arm,psci-1.0";
81 method = "smc"; 76 method = "smc";
82 }; 77 };
83 78
84 reserved-memory { !! 79 soc: soc {
85 #address-cells = <2>; !! 80 #address-cells = <0x1>;
86 #size-cells = <2>; !! 81 #size-cells = <0x1>;
87 ranges; <<
88 <<
89 bootloader@4a600000 { <<
90 reg = <0x0 0x4a600000 <<
91 no-map; <<
92 }; <<
93 <<
94 sbl@4aa00000 { <<
95 reg = <0x0 0x4aa00000 <<
96 no-map; <<
97 }; <<
98 <<
99 smem@4ab00000 { <<
100 compatible = "qcom,sme <<
101 reg = <0x0 0x4ab00000 <<
102 no-map; <<
103 <<
104 hwlocks = <&tcsr_mutex <<
105 }; <<
106 <<
107 memory@4ac00000 { <<
108 reg = <0x0 0x4ac00000 <<
109 no-map; <<
110 }; <<
111 }; <<
112 <<
113 firmware { <<
114 scm { <<
115 compatible = "qcom,scm <<
116 qcom,dload-mode = <&tc <<
117 }; <<
118 }; <<
119 <<
120 soc: soc@0 { <<
121 #address-cells = <1>; <<
122 #size-cells = <1>; <<
123 ranges = <0 0 0 0xffffffff>; 82 ranges = <0 0 0 0xffffffff>;
124 compatible = "simple-bus"; 83 compatible = "simple-bus";
125 84
126 ssphy_1: phy@58000 { 85 ssphy_1: phy@58000 {
127 compatible = "qcom,ipq 86 compatible = "qcom,ipq8074-qmp-usb3-phy";
128 reg = <0x00058000 0x10 !! 87 reg = <0x00058000 0x1c4>;
>> 88 #clock-cells = <1>;
>> 89 #address-cells = <1>;
>> 90 #size-cells = <1>;
>> 91 ranges;
129 92
130 clocks = <&gcc GCC_USB 93 clocks = <&gcc GCC_USB1_AUX_CLK>,
131 <&xo>, !! 94 <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
132 <&gcc GCC_USB !! 95 <&xo>;
133 <&gcc GCC_USB !! 96 clock-names = "aux", "cfg_ahb", "ref";
134 clock-names = "aux", !! 97
135 "ref", !! 98 resets = <&gcc GCC_USB1_PHY_BCR>,
136 "cfg_ahb !! 99 <&gcc GCC_USB3PHY_1_PHY_BCR>;
137 "pipe"; !! 100 reset-names = "phy","common";
138 clock-output-names = " !! 101 status = "disabled";
139 #clock-cells = <0>; !! 102
140 #phy-cells = <0>; !! 103 usb1_ssphy: lane@58200 {
141 !! 104 reg = <0x00058200 0x130>, /* Tx */
142 resets = <&gcc GCC_USB !! 105 <0x00058400 0x200>, /* Rx */
143 <&gcc GCC_USB !! 106 <0x00058800 0x1f8>, /* PCS */
144 reset-names = "phy", !! 107 <0x00058600 0x044>; /* PCS misc*/
145 "phy_phy !! 108 #phy-cells = <0>;
146 !! 109 clocks = <&gcc GCC_USB1_PIPE_CLK>;
147 status = "disabled"; !! 110 clock-names = "pipe0";
>> 111 clock-output-names = "gcc_usb1_pipe_clk_src";
>> 112 };
148 }; 113 };
149 114
150 qusb_phy_1: phy@59000 { 115 qusb_phy_1: phy@59000 {
151 compatible = "qcom,ipq 116 compatible = "qcom,ipq8074-qusb2-phy";
152 reg = <0x00059000 0x18 117 reg = <0x00059000 0x180>;
153 #phy-cells = <0>; 118 #phy-cells = <0>;
154 119
155 clocks = <&gcc GCC_USB 120 clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
156 <&xo>; 121 <&xo>;
157 clock-names = "cfg_ahb 122 clock-names = "cfg_ahb", "ref";
158 123
159 resets = <&gcc GCC_QUS 124 resets = <&gcc GCC_QUSB2_1_PHY_BCR>;
160 status = "disabled"; 125 status = "disabled";
161 }; 126 };
162 127
163 ssphy_0: phy@78000 { 128 ssphy_0: phy@78000 {
164 compatible = "qcom,ipq 129 compatible = "qcom,ipq8074-qmp-usb3-phy";
165 reg = <0x00078000 0x10 !! 130 reg = <0x00078000 0x1c4>;
>> 131 #clock-cells = <1>;
>> 132 #address-cells = <1>;
>> 133 #size-cells = <1>;
>> 134 ranges;
166 135
167 clocks = <&gcc GCC_USB 136 clocks = <&gcc GCC_USB0_AUX_CLK>,
168 <&xo>, !! 137 <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
169 <&gcc GCC_USB !! 138 <&xo>;
170 <&gcc GCC_USB !! 139 clock-names = "aux", "cfg_ahb", "ref";
171 clock-names = "aux", !! 140
172 "ref", !! 141 resets = <&gcc GCC_USB0_PHY_BCR>,
173 "cfg_ahb !! 142 <&gcc GCC_USB3PHY_0_PHY_BCR>;
174 "pipe"; !! 143 reset-names = "phy","common";
175 clock-output-names = " !! 144 status = "disabled";
176 #clock-cells = <0>; !! 145
177 #phy-cells = <0>; !! 146 usb0_ssphy: lane@78200 {
178 !! 147 reg = <0x00078200 0x130>, /* Tx */
179 resets = <&gcc GCC_USB !! 148 <0x00078400 0x200>, /* Rx */
180 <&gcc GCC_USB !! 149 <0x00078800 0x1f8>, /* PCS */
181 reset-names = "phy", !! 150 <0x00078600 0x044>; /* PCS misc*/
182 "phy_phy !! 151 #phy-cells = <0>;
183 !! 152 clocks = <&gcc GCC_USB0_PIPE_CLK>;
184 status = "disabled"; !! 153 clock-names = "pipe0";
>> 154 clock-output-names = "gcc_usb0_pipe_clk_src";
>> 155 };
185 }; 156 };
186 157
187 qusb_phy_0: phy@79000 { 158 qusb_phy_0: phy@79000 {
188 compatible = "qcom,ipq 159 compatible = "qcom,ipq8074-qusb2-phy";
189 reg = <0x00079000 0x18 160 reg = <0x00079000 0x180>;
190 #phy-cells = <0>; 161 #phy-cells = <0>;
191 162
192 clocks = <&gcc GCC_USB 163 clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
193 <&xo>; 164 <&xo>;
194 clock-names = "cfg_ahb 165 clock-names = "cfg_ahb", "ref";
195 166
196 resets = <&gcc GCC_QUS 167 resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
197 status = "disabled"; <<
198 }; 168 };
199 169
200 pcie_qmp0: phy@84000 { !! 170 pcie_phy0: phy@86000 {
201 compatible = "qcom,ipq !! 171 compatible = "qcom,ipq8074-qmp-pcie-phy";
202 reg = <0x00084000 0x10 !! 172 reg = <0x00086000 0x1000>;
203 <<
204 clocks = <&gcc GCC_PCI <<
205 <&gcc GCC_PCI <<
206 <&gcc GCC_PCI <<
207 clock-names = "aux", <<
208 "cfg_ahb <<
209 "pipe"; <<
210 <<
211 clock-output-names = " <<
212 #clock-cells = <0>; <<
213 <<
214 #phy-cells = <0>; 173 #phy-cells = <0>;
>> 174 clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
>> 175 clock-names = "pipe_clk";
>> 176 clock-output-names = "pcie20_phy0_pipe_clk";
215 177
216 resets = <&gcc GCC_PCI 178 resets = <&gcc GCC_PCIE0_PHY_BCR>,
217 <&gcc GCC_PCI !! 179 <&gcc GCC_PCIE0PHY_PHY_BCR>;
218 reset-names = "phy", 180 reset-names = "phy",
219 "common" 181 "common";
220 status = "disabled"; 182 status = "disabled";
221 }; 183 };
222 184
223 pcie_qmp1: phy@8e000 { !! 185 pcie_phy1: phy@8e000 {
224 compatible = "qcom,ipq 186 compatible = "qcom,ipq8074-qmp-pcie-phy";
225 reg = <0x0008e000 0x10 187 reg = <0x0008e000 0x1000>;
226 <<
227 clocks = <&gcc GCC_PCI <<
228 <&gcc GCC_PCI <<
229 <&gcc GCC_PCI <<
230 clock-names = "aux", <<
231 "cfg_ahb <<
232 "pipe"; <<
233 <<
234 clock-output-names = " <<
235 #clock-cells = <0>; <<
236 <<
237 #phy-cells = <0>; 188 #phy-cells = <0>;
>> 189 clocks = <&gcc GCC_PCIE1_PIPE_CLK>;
>> 190 clock-names = "pipe_clk";
>> 191 clock-output-names = "pcie20_phy1_pipe_clk";
238 192
239 resets = <&gcc GCC_PCI 193 resets = <&gcc GCC_PCIE1_PHY_BCR>,
240 <&gcc GCC_PCI !! 194 <&gcc GCC_PCIE1PHY_PHY_BCR>;
241 reset-names = "phy", 195 reset-names = "phy",
242 "common" 196 "common";
243 status = "disabled"; 197 status = "disabled";
244 }; 198 };
245 199
246 mdio: mdio@90000 { <<
247 compatible = "qcom,ipq <<
248 reg = <0x00090000 0x64 <<
249 #address-cells = <1>; <<
250 #size-cells = <0>; <<
251 <<
252 clocks = <&gcc GCC_MDI <<
253 clock-names = "gcc_mdi <<
254 <<
255 clock-frequency = <625 <<
256 <<
257 status = "disabled"; <<
258 }; <<
259 <<
260 qfprom: efuse@a4000 { <<
261 compatible = "qcom,ipq <<
262 reg = <0x000a4000 0x20 <<
263 #address-cells = <1>; <<
264 #size-cells = <1>; <<
265 }; <<
266 <<
267 prng: rng@e3000 { <<
268 compatible = "qcom,prn <<
269 reg = <0x000e3000 0x10 <<
270 clocks = <&gcc GCC_PRN <<
271 clock-names = "core"; <<
272 status = "disabled"; <<
273 }; <<
274 <<
275 tsens: thermal-sensor@4a9000 { <<
276 compatible = "qcom,ipq <<
277 reg = <0x4a9000 0x1000 <<
278 <0x4a8000 0x1000 <<
279 interrupts = <GIC_SPI <<
280 interrupt-names = "com <<
281 #qcom,sensors = <16>; <<
282 #thermal-sensor-cells <<
283 }; <<
284 <<
285 cryptobam: dma-controller@7040 <<
286 compatible = "qcom,bam <<
287 reg = <0x00704000 0x20 <<
288 interrupts = <GIC_SPI <<
289 clocks = <&gcc GCC_CRY <<
290 clock-names = "bam_clk <<
291 #dma-cells = <1>; <<
292 qcom,ee = <1>; <<
293 qcom,controlled-remote <<
294 status = "disabled"; <<
295 }; <<
296 <<
297 crypto: crypto@73a000 { <<
298 compatible = "qcom,cry <<
299 reg = <0x0073a000 0x60 <<
300 clocks = <&gcc GCC_CRY <<
301 <&gcc GCC_CRY <<
302 <&gcc GCC_CRY <<
303 clock-names = "iface", <<
304 dmas = <&cryptobam 2>, <<
305 dma-names = "rx", "tx" <<
306 status = "disabled"; <<
307 }; <<
308 <<
309 tlmm: pinctrl@1000000 { 200 tlmm: pinctrl@1000000 {
310 compatible = "qcom,ipq 201 compatible = "qcom,ipq8074-pinctrl";
311 reg = <0x01000000 0x30 202 reg = <0x01000000 0x300000>;
312 interrupts = <GIC_SPI 203 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
313 gpio-controller; 204 gpio-controller;
314 gpio-ranges = <&tlmm 0 205 gpio-ranges = <&tlmm 0 0 70>;
315 #gpio-cells = <2>; !! 206 #gpio-cells = <0x2>;
316 interrupt-controller; 207 interrupt-controller;
317 #interrupt-cells = <2> !! 208 #interrupt-cells = <0x2>;
318 209
319 serial_4_pins: serial4 !! 210 serial_4_pins: serial4-pinmux {
320 pins = "gpio23 211 pins = "gpio23", "gpio24";
321 function = "bl 212 function = "blsp4_uart1";
322 drive-strength 213 drive-strength = <8>;
323 bias-disable; 214 bias-disable;
324 }; 215 };
325 216
326 serial_5_pins: serial5 !! 217 i2c_0_pins: i2c-0-pinmux {
327 pins = "gpio9" <<
328 function = "bl <<
329 drive-strength <<
330 bias-disable; <<
331 }; <<
332 <<
333 i2c_0_pins: i2c-0-stat <<
334 pins = "gpio42 218 pins = "gpio42", "gpio43";
335 function = "bl 219 function = "blsp1_i2c";
336 drive-strength 220 drive-strength = <8>;
337 bias-disable; 221 bias-disable;
338 }; 222 };
339 223
340 spi_0_pins: spi-0-stat !! 224 spi_0_pins: spi-0-pins {
341 pins = "gpio38 225 pins = "gpio38", "gpio39", "gpio40", "gpio41";
342 function = "bl 226 function = "blsp0_spi";
343 drive-strength 227 drive-strength = <8>;
344 bias-disable; 228 bias-disable;
345 }; 229 };
346 230
347 hsuart_pins: hsuart-st !! 231 hsuart_pins: hsuart-pins {
348 pins = "gpio46 232 pins = "gpio46", "gpio47", "gpio48", "gpio49";
349 function = "bl 233 function = "blsp2_uart";
350 drive-strength 234 drive-strength = <8>;
351 bias-disable; 235 bias-disable;
352 }; 236 };
353 237
354 qpic_pins: qpic-state !! 238 qpic_pins: qpic-pins {
355 pins = "gpio1" 239 pins = "gpio1", "gpio3", "gpio4",
356 "gpio5" 240 "gpio5", "gpio6", "gpio7",
357 "gpio8" 241 "gpio8", "gpio10", "gpio11",
358 "gpio12 242 "gpio12", "gpio13", "gpio14",
359 "gpio15 !! 243 "gpio15", "gpio16", "gpio17";
360 function = "qp 244 function = "qpic";
361 drive-strength 245 drive-strength = <8>;
362 bias-disable; 246 bias-disable;
363 }; 247 };
364 }; 248 };
365 249
366 gcc: clock-controller@1800000 !! 250 gcc: gcc@1800000 {
367 compatible = "qcom,gcc 251 compatible = "qcom,gcc-ipq8074";
368 reg = <0x01800000 0x80 252 reg = <0x01800000 0x80000>;
369 clocks = <&xo>, !! 253 #clock-cells = <0x1>;
370 <&sleep_clk>, !! 254 #reset-cells = <0x1>;
371 <&pcie_qmp0>, <<
372 <&pcie_qmp1>; <<
373 clock-names = "xo", <<
374 "sleep_c <<
375 "pcie0_p <<
376 "pcie1_p <<
377 #clock-cells = <1>; <<
378 #power-domain-cells = <<
379 #reset-cells = <1>; <<
380 }; 255 };
381 256
382 tcsr_mutex: hwlock@1905000 { !! 257 sdhc_1: sdhci@7824900 {
383 compatible = "qcom,tcs !! 258 compatible = "qcom,sdhci-msm-v4";
384 reg = <0x01905000 0x20 <<
385 #hwlock-cells = <1>; <<
386 }; <<
387 <<
388 tcsr: syscon@1937000 { <<
389 compatible = "qcom,tcs <<
390 reg = <0x01937000 0x21 <<
391 }; <<
392 <<
393 spmi_bus: spmi@200f000 { <<
394 compatible = "qcom,spm <<
395 reg = <0x0200f000 0x00 <<
396 <0x02400000 0x80 <<
397 <0x02c00000 0x80 <<
398 <0x03800000 0x20 <<
399 <0x0200a000 0x00 <<
400 reg-names = "core", "c <<
401 interrupts = <GIC_SPI <<
402 interrupt-names = "per <<
403 qcom,ee = <0>; <<
404 qcom,channel = <0>; <<
405 #address-cells = <2>; <<
406 #size-cells = <0>; <<
407 interrupt-controller; <<
408 #interrupt-cells = <4> <<
409 }; <<
410 <<
411 sdhc_1: mmc@7824900 { <<
412 compatible = "qcom,ipq <<
413 reg = <0x7824900 0x500 259 reg = <0x7824900 0x500>, <0x7824000 0x800>;
414 reg-names = "hc", "cor !! 260 reg-names = "hc_mem", "core_mem";
415 261
416 interrupts = <GIC_SPI 262 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
417 <GIC_SPI 263 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
418 interrupt-names = "hc_ 264 interrupt-names = "hc_irq", "pwr_irq";
419 265
420 clocks = <&gcc GCC_SDC !! 266 clocks = <&xo>,
421 <&gcc GCC_SDC !! 267 <&gcc GCC_SDCC1_AHB_CLK>,
422 <&xo>; !! 268 <&gcc GCC_SDCC1_APPS_CLK>;
423 clock-names = "iface", !! 269 clock-names = "xo", "iface", "core";
424 resets = <&gcc GCC_SDC <<
425 max-frequency = <38400 270 max-frequency = <384000000>;
426 mmc-ddr-1_8v; 271 mmc-ddr-1_8v;
427 mmc-hs200-1_8v; 272 mmc-hs200-1_8v;
428 mmc-hs400-1_8v; 273 mmc-hs400-1_8v;
429 bus-width = <8>; 274 bus-width = <8>;
430 275
431 status = "disabled"; 276 status = "disabled";
432 }; 277 };
433 278
434 blsp_dma: dma-controller@78840 !! 279 blsp_dma: dma@7884000 {
435 compatible = "qcom,bam 280 compatible = "qcom,bam-v1.7.0";
436 reg = <0x07884000 0x2b 281 reg = <0x07884000 0x2b000>;
437 interrupts = <GIC_SPI 282 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
438 clocks = <&gcc GCC_BLS 283 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
439 clock-names = "bam_clk 284 clock-names = "bam_clk";
440 #dma-cells = <1>; 285 #dma-cells = <1>;
441 qcom,ee = <0>; 286 qcom,ee = <0>;
442 }; 287 };
443 288
444 blsp1_uart1: serial@78af000 { 289 blsp1_uart1: serial@78af000 {
445 compatible = "qcom,msm 290 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
446 reg = <0x078af000 0x20 291 reg = <0x078af000 0x200>;
447 interrupts = <GIC_SPI 292 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
448 clocks = <&gcc GCC_BLS 293 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
449 <&gcc GCC_BLS 294 <&gcc GCC_BLSP1_AHB_CLK>;
450 clock-names = "core", 295 clock-names = "core", "iface";
451 status = "disabled"; 296 status = "disabled";
452 }; 297 };
453 298
454 blsp1_uart3: serial@78b1000 { 299 blsp1_uart3: serial@78b1000 {
455 compatible = "qcom,msm 300 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
456 reg = <0x078b1000 0x20 301 reg = <0x078b1000 0x200>;
457 interrupts = <GIC_SPI 302 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
458 clocks = <&gcc GCC_BLS 303 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
459 <&gcc GCC_BLSP 304 <&gcc GCC_BLSP1_AHB_CLK>;
460 clock-names = "core", 305 clock-names = "core", "iface";
461 dmas = <&blsp_dma 4>, 306 dmas = <&blsp_dma 4>,
462 <&blsp_dma 5>; 307 <&blsp_dma 5>;
463 dma-names = "tx", "rx" 308 dma-names = "tx", "rx";
464 pinctrl-0 = <&hsuart_p 309 pinctrl-0 = <&hsuart_pins>;
465 pinctrl-names = "defau 310 pinctrl-names = "default";
466 status = "disabled"; 311 status = "disabled";
467 }; 312 };
468 313
469 blsp1_uart5: serial@78b3000 { 314 blsp1_uart5: serial@78b3000 {
470 compatible = "qcom,msm 315 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
471 reg = <0x078b3000 0x20 316 reg = <0x078b3000 0x200>;
472 interrupts = <GIC_SPI 317 interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
473 clocks = <&gcc GCC_BLS 318 clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>,
474 <&gcc GCC_BLS 319 <&gcc GCC_BLSP1_AHB_CLK>;
475 clock-names = "core", 320 clock-names = "core", "iface";
476 pinctrl-0 = <&serial_4 321 pinctrl-0 = <&serial_4_pins>;
477 pinctrl-names = "defau 322 pinctrl-names = "default";
478 status = "disabled"; 323 status = "disabled";
479 }; 324 };
480 325
481 blsp1_uart6: serial@78b4000 { <<
482 compatible = "qcom,msm <<
483 reg = <0x078b4000 0x20 <<
484 interrupts = <GIC_SPI <<
485 clocks = <&gcc GCC_BLS <<
486 <&gcc GCC_BLS <<
487 clock-names = "core", <<
488 pinctrl-0 = <&serial_5 <<
489 pinctrl-names = "defau <<
490 status = "disabled"; <<
491 }; <<
492 <<
493 blsp1_spi1: spi@78b5000 { 326 blsp1_spi1: spi@78b5000 {
494 compatible = "qcom,spi 327 compatible = "qcom,spi-qup-v2.2.1";
495 #address-cells = <1>; 328 #address-cells = <1>;
496 #size-cells = <0>; 329 #size-cells = <0>;
497 reg = <0x078b5000 0x60 330 reg = <0x078b5000 0x600>;
498 interrupts = <GIC_SPI 331 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
>> 332 spi-max-frequency = <50000000>;
499 clocks = <&gcc GCC_BLS 333 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
500 <&gcc GCC_BLSP 334 <&gcc GCC_BLSP1_AHB_CLK>;
501 clock-names = "core", 335 clock-names = "core", "iface";
502 dmas = <&blsp_dma 12>, 336 dmas = <&blsp_dma 12>, <&blsp_dma 13>;
503 dma-names = "tx", "rx" 337 dma-names = "tx", "rx";
504 pinctrl-0 = <&spi_0_pi 338 pinctrl-0 = <&spi_0_pins>;
505 pinctrl-names = "defau 339 pinctrl-names = "default";
506 status = "disabled"; 340 status = "disabled";
507 }; 341 };
508 342
509 blsp1_i2c2: i2c@78b6000 { 343 blsp1_i2c2: i2c@78b6000 {
510 compatible = "qcom,i2c 344 compatible = "qcom,i2c-qup-v2.2.1";
511 #address-cells = <1>; 345 #address-cells = <1>;
512 #size-cells = <0>; 346 #size-cells = <0>;
513 reg = <0x078b6000 0x60 347 reg = <0x078b6000 0x600>;
514 interrupts = <GIC_SPI 348 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
515 clocks = <&gcc GCC_BLS !! 349 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
516 <&gcc GCC_BLS !! 350 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
517 clock-names = "core", !! 351 clock-names = "iface", "core";
518 clock-frequency = <400 352 clock-frequency = <400000>;
519 dmas = <&blsp_dma 14>, !! 353 dmas = <&blsp_dma 15>, <&blsp_dma 14>;
520 dma-names = "tx", "rx" !! 354 dma-names = "rx", "tx";
521 pinctrl-0 = <&i2c_0_pi 355 pinctrl-0 = <&i2c_0_pins>;
522 pinctrl-names = "defau 356 pinctrl-names = "default";
523 status = "disabled"; 357 status = "disabled";
524 }; 358 };
525 359
526 blsp1_i2c3: i2c@78b7000 { 360 blsp1_i2c3: i2c@78b7000 {
527 compatible = "qcom,i2c 361 compatible = "qcom,i2c-qup-v2.2.1";
528 #address-cells = <1>; 362 #address-cells = <1>;
529 #size-cells = <0>; 363 #size-cells = <0>;
530 reg = <0x078b7000 0x60 364 reg = <0x078b7000 0x600>;
531 interrupts = <GIC_SPI 365 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
532 clocks = <&gcc GCC_BLS !! 366 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
533 <&gcc GCC_BLS !! 367 <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
534 clock-names = "core", !! 368 clock-names = "iface", "core";
535 clock-frequency = <100 369 clock-frequency = <100000>;
536 dmas = <&blsp_dma 16>, !! 370 dmas = <&blsp_dma 17>, <&blsp_dma 16>;
537 dma-names = "tx", "rx" !! 371 dma-names = "rx", "tx";
538 status = "disabled"; <<
539 }; <<
540 <<
541 blsp1_spi4: spi@78b8000 { <<
542 compatible = "qcom,spi <<
543 #address-cells = <1>; <<
544 #size-cells = <0>; <<
545 reg = <0x78b8000 0x600 <<
546 interrupts = <GIC_SPI <<
547 clocks = <&gcc GCC_BLS <<
548 <&gcc GCC_BLS <<
549 clock-names = "core", <<
550 dmas = <&blsp_dma 18>, <<
551 dma-names = "tx", "rx" <<
552 status = "disabled"; <<
553 }; <<
554 <<
555 blsp1_i2c5: i2c@78b9000 { <<
556 compatible = "qcom,i2c <<
557 #address-cells = <1>; <<
558 #size-cells = <0>; <<
559 reg = <0x78b9000 0x600 <<
560 interrupts = <GIC_SPI <<
561 clocks = <&gcc GCC_BLS <<
562 <&gcc GCC_BLS <<
563 clock-names = "core", <<
564 clock-frequency = <400 <<
565 dmas = <&blsp_dma 20>, <<
566 dma-names = "tx", "rx" <<
567 status = "disabled"; <<
568 }; <<
569 <<
570 blsp1_spi5: spi@78b9000 { <<
571 compatible = "qcom,spi <<
572 #address-cells = <1>; <<
573 #size-cells = <0>; <<
574 reg = <0x78b9000 0x600 <<
575 interrupts = <GIC_SPI <<
576 clocks = <&gcc GCC_BLS <<
577 <&gcc GCC_BLS <<
578 clock-names = "core", <<
579 dmas = <&blsp_dma 20>, <<
580 dma-names = "tx", "rx" <<
581 status = "disabled"; <<
582 }; <<
583 <<
584 blsp1_i2c6: i2c@78ba000 { <<
585 compatible = "qcom,i2c <<
586 #address-cells = <1>; <<
587 #size-cells = <0>; <<
588 reg = <0x078ba000 0x60 <<
589 interrupts = <GIC_SPI <<
590 clocks = <&gcc GCC_BLS <<
591 <&gcc GCC_BLS <<
592 clock-names = "core", <<
593 clock-frequency = <100 <<
594 dmas = <&blsp_dma 22>, <<
595 dma-names = "tx", "rx" <<
596 status = "disabled"; 372 status = "disabled";
597 }; 373 };
598 374
599 qpic_bam: dma-controller@79840 !! 375 qpic_bam: dma@7984000 {
600 compatible = "qcom,bam 376 compatible = "qcom,bam-v1.7.0";
601 reg = <0x07984000 0x1a 377 reg = <0x07984000 0x1a000>;
602 interrupts = <GIC_SPI 378 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
603 clocks = <&gcc GCC_QPI 379 clocks = <&gcc GCC_QPIC_AHB_CLK>;
604 clock-names = "bam_clk 380 clock-names = "bam_clk";
605 #dma-cells = <1>; 381 #dma-cells = <1>;
606 qcom,ee = <0>; 382 qcom,ee = <0>;
607 status = "disabled"; 383 status = "disabled";
608 }; 384 };
609 385
610 qpic_nand: nand-controller@79b !! 386 qpic_nand: nand@79b0000 {
611 compatible = "qcom,ipq 387 compatible = "qcom,ipq8074-nand";
612 reg = <0x079b0000 0x10 388 reg = <0x079b0000 0x10000>;
613 #address-cells = <1>; 389 #address-cells = <1>;
614 #size-cells = <0>; 390 #size-cells = <0>;
615 clocks = <&gcc GCC_QPI 391 clocks = <&gcc GCC_QPIC_CLK>,
616 <&gcc GCC_QPI 392 <&gcc GCC_QPIC_AHB_CLK>;
617 clock-names = "core", 393 clock-names = "core", "aon";
618 394
619 dmas = <&qpic_bam 0>, 395 dmas = <&qpic_bam 0>,
620 <&qpic_bam 1>, 396 <&qpic_bam 1>,
621 <&qpic_bam 2>; 397 <&qpic_bam 2>;
622 dma-names = "tx", "rx" 398 dma-names = "tx", "rx", "cmd";
623 pinctrl-0 = <&qpic_pin 399 pinctrl-0 = <&qpic_pins>;
624 pinctrl-names = "defau 400 pinctrl-names = "default";
625 status = "disabled"; 401 status = "disabled";
626 }; 402 };
627 403
628 usb_0: usb@8af8800 { 404 usb_0: usb@8af8800 {
629 compatible = "qcom,ipq !! 405 compatible = "qcom,dwc3";
630 reg = <0x08af8800 0x40 406 reg = <0x08af8800 0x400>;
631 #address-cells = <1>; 407 #address-cells = <1>;
632 #size-cells = <1>; 408 #size-cells = <1>;
633 ranges; 409 ranges;
634 410
635 clocks = <&gcc GCC_SYS 411 clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
636 <&gcc GCC_USB0 412 <&gcc GCC_USB0_MASTER_CLK>,
637 <&gcc GCC_USB0 413 <&gcc GCC_USB0_SLEEP_CLK>,
638 <&gcc GCC_USB0 414 <&gcc GCC_USB0_MOCK_UTMI_CLK>;
639 clock-names = "cfg_noc !! 415 clock-names = "sys_noc_axi",
640 "core", !! 416 "master",
641 "sleep", 417 "sleep",
642 "mock_utmi"; 418 "mock_utmi";
643 419
644 assigned-clocks = <&gc 420 assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
645 <&gc 421 <&gcc GCC_USB0_MASTER_CLK>,
646 <&gc 422 <&gcc GCC_USB0_MOCK_UTMI_CLK>;
647 assigned-clock-rates = 423 assigned-clock-rates = <133330000>,
648 424 <133330000>,
649 425 <19200000>;
650 426
651 interrupts = <GIC_SPI <<
652 <GIC_SPI <<
653 <GIC_SPI <<
654 interrupt-names = "pwr <<
655 "qus <<
656 "ss_ <<
657 <<
658 power-domains = <&gcc <<
659 <<
660 resets = <&gcc GCC_USB 427 resets = <&gcc GCC_USB0_BCR>;
661 status = "disabled"; 428 status = "disabled";
662 429
663 dwc_0: usb@8a00000 { !! 430 dwc_0: dwc3@8a00000 {
664 compatible = " 431 compatible = "snps,dwc3";
665 reg = <0x8a000 432 reg = <0x8a00000 0xcd00>;
666 interrupts = < 433 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
667 phys = <&qusb_ !! 434 phys = <&qusb_phy_0>, <&usb0_ssphy>;
668 phy-names = "u 435 phy-names = "usb2-phy", "usb3-phy";
669 snps,parkmode- !! 436 tx-fifo-resize;
670 snps,is-utmi-l 437 snps,is-utmi-l1-suspend;
671 snps,hird-thre 438 snps,hird-threshold = /bits/ 8 <0x0>;
672 snps,dis_u2_su 439 snps,dis_u2_susphy_quirk;
673 snps,dis_u3_su 440 snps,dis_u3_susphy_quirk;
674 dr_mode = "hos 441 dr_mode = "host";
675 }; 442 };
676 }; 443 };
677 444
678 usb_1: usb@8cf8800 { 445 usb_1: usb@8cf8800 {
679 compatible = "qcom,ipq !! 446 compatible = "qcom,dwc3";
680 reg = <0x08cf8800 0x40 447 reg = <0x08cf8800 0x400>;
681 #address-cells = <1>; 448 #address-cells = <1>;
682 #size-cells = <1>; 449 #size-cells = <1>;
683 ranges; 450 ranges;
684 451
685 clocks = <&gcc GCC_SYS 452 clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>,
686 <&gcc GCC_USB1 453 <&gcc GCC_USB1_MASTER_CLK>,
687 <&gcc GCC_USB1 454 <&gcc GCC_USB1_SLEEP_CLK>,
688 <&gcc GCC_USB1 455 <&gcc GCC_USB1_MOCK_UTMI_CLK>;
689 clock-names = "cfg_noc !! 456 clock-names = "sys_noc_axi",
690 "core", !! 457 "master",
691 "sleep", 458 "sleep",
692 "mock_utmi"; 459 "mock_utmi";
693 460
694 assigned-clocks = <&gc 461 assigned-clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>,
695 <&gc 462 <&gcc GCC_USB1_MASTER_CLK>,
696 <&gc 463 <&gcc GCC_USB1_MOCK_UTMI_CLK>;
697 assigned-clock-rates = 464 assigned-clock-rates = <133330000>,
698 465 <133330000>,
699 466 <19200000>;
700 467
701 interrupts = <GIC_SPI <<
702 <GIC_SPI <<
703 <GIC_SPI <<
704 interrupt-names = "pwr <<
705 "qus <<
706 "ss_ <<
707 <<
708 power-domains = <&gcc <<
709 <<
710 resets = <&gcc GCC_USB 468 resets = <&gcc GCC_USB1_BCR>;
711 status = "disabled"; 469 status = "disabled";
712 470
713 dwc_1: usb@8c00000 { !! 471 dwc_1: dwc3@8c00000 {
714 compatible = " 472 compatible = "snps,dwc3";
715 reg = <0x8c000 473 reg = <0x8c00000 0xcd00>;
716 interrupts = < 474 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
717 phys = <&qusb_ !! 475 phys = <&qusb_phy_1>, <&usb1_ssphy>;
718 phy-names = "u 476 phy-names = "usb2-phy", "usb3-phy";
719 snps,parkmode- !! 477 tx-fifo-resize;
720 snps,is-utmi-l 478 snps,is-utmi-l1-suspend;
721 snps,hird-thre 479 snps,hird-threshold = /bits/ 8 <0x0>;
722 snps,dis_u2_su 480 snps,dis_u2_susphy_quirk;
723 snps,dis_u3_su 481 snps,dis_u3_susphy_quirk;
724 dr_mode = "hos 482 dr_mode = "host";
725 }; 483 };
726 }; 484 };
727 485
728 intc: interrupt-controller@b00 486 intc: interrupt-controller@b000000 {
729 compatible = "qcom,msm 487 compatible = "qcom,msm-qgic2";
730 #address-cells = <1>; <<
731 #size-cells = <1>; <<
732 interrupt-controller; 488 interrupt-controller;
733 #interrupt-cells = <3> !! 489 #interrupt-cells = <0x3>;
734 reg = <0x0b000000 0x10 490 reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
735 ranges = <0 0xb00a000 <<
736 <<
737 v2m@0 { <<
738 compatible = " <<
739 msi-controller <<
740 reg = <0x0 0xf <<
741 }; <<
742 }; 491 };
743 492
744 watchdog: watchdog@b017000 { !! 493 timer {
745 compatible = "qcom,kps !! 494 compatible = "arm,armv8-timer";
746 reg = <0xb017000 0x100 !! 495 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
747 interrupts = <GIC_SPI !! 496 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
748 clocks = <&sleep_clk>; !! 497 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
749 timeout-sec = <30>; !! 498 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
750 }; <<
751 <<
752 apcs_glb: mailbox@b111000 { <<
753 compatible = "qcom,ipq <<
754 "qcom,ipq <<
755 reg = <0x0b111000 0x10 <<
756 clocks = <&a53pll>, <& <<
757 clock-names = "pll", " <<
758 <<
759 #clock-cells = <1>; <<
760 #mbox-cells = <1>; <<
761 }; <<
762 <<
763 a53pll: clock@b116000 { <<
764 compatible = "qcom,ipq <<
765 reg = <0x0b116000 0x40 <<
766 #clock-cells = <0>; <<
767 clocks = <&xo>; <<
768 clock-names = "xo"; <<
769 }; 499 };
770 500
771 timer@b120000 { 501 timer@b120000 {
772 #address-cells = <1>; 502 #address-cells = <1>;
773 #size-cells = <1>; 503 #size-cells = <1>;
774 ranges; 504 ranges;
775 compatible = "arm,armv 505 compatible = "arm,armv7-timer-mem";
776 reg = <0x0b120000 0x10 506 reg = <0x0b120000 0x1000>;
>> 507 clock-frequency = <19200000>;
777 508
778 frame@b120000 { 509 frame@b120000 {
779 frame-number = 510 frame-number = <0>;
780 interrupts = < 511 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
781 < 512 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
782 reg = <0x0b121 513 reg = <0x0b121000 0x1000>,
783 <0x0b122 514 <0x0b122000 0x1000>;
784 }; 515 };
785 516
786 frame@b123000 { 517 frame@b123000 {
787 frame-number = 518 frame-number = <1>;
788 interrupts = < 519 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
789 reg = <0x0b123 520 reg = <0x0b123000 0x1000>;
790 status = "disa 521 status = "disabled";
791 }; 522 };
792 523
793 frame@b124000 { 524 frame@b124000 {
794 frame-number = 525 frame-number = <2>;
795 interrupts = < 526 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
796 reg = <0x0b124 527 reg = <0x0b124000 0x1000>;
797 status = "disa 528 status = "disabled";
798 }; 529 };
799 530
800 frame@b125000 { 531 frame@b125000 {
801 frame-number = 532 frame-number = <3>;
802 interrupts = < 533 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
803 reg = <0x0b125 534 reg = <0x0b125000 0x1000>;
804 status = "disa 535 status = "disabled";
805 }; 536 };
806 537
807 frame@b126000 { 538 frame@b126000 {
808 frame-number = 539 frame-number = <4>;
809 interrupts = < 540 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
810 reg = <0x0b126 541 reg = <0x0b126000 0x1000>;
811 status = "disa 542 status = "disabled";
812 }; 543 };
813 544
814 frame@b127000 { 545 frame@b127000 {
815 frame-number = 546 frame-number = <5>;
816 interrupts = < 547 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
817 reg = <0x0b127 548 reg = <0x0b127000 0x1000>;
818 status = "disa 549 status = "disabled";
819 }; 550 };
820 551
821 frame@b128000 { 552 frame@b128000 {
822 frame-number = 553 frame-number = <6>;
823 interrupts = < 554 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
824 reg = <0x0b128 555 reg = <0x0b128000 0x1000>;
825 status = "disa 556 status = "disabled";
826 }; 557 };
827 }; 558 };
828 559
829 pcie1: pcie@10000000 { !! 560 pcie1: pci@10000000 {
830 compatible = "qcom,pci 561 compatible = "qcom,pcie-ipq8074";
831 reg = <0x10000000 0xf1 !! 562 reg = <0x10000000 0xf1d
832 <0x10000f20 0xa8 !! 563 0x10000f20 0xa8
833 <0x00088000 0x20 !! 564 0x00088000 0x2000
834 <0x10100000 0x10 !! 565 0x10100000 0x1000>;
835 reg-names = "dbi", "el 566 reg-names = "dbi", "elbi", "parf", "config";
836 device_type = "pci"; 567 device_type = "pci";
837 linux,pci-domain = <1> 568 linux,pci-domain = <1>;
838 bus-range = <0x00 0xff 569 bus-range = <0x00 0xff>;
839 num-lanes = <1>; 570 num-lanes = <1>;
840 max-link-speed = <2>; <<
841 #address-cells = <3>; 571 #address-cells = <3>;
842 #size-cells = <2>; 572 #size-cells = <2>;
843 573
844 phys = <&pcie_qmp1>; !! 574 phys = <&pcie_phy1>;
845 phy-names = "pciephy"; 575 phy-names = "pciephy";
846 576
847 ranges = <0x81000000 0 !! 577 ranges = <0x81000000 0 0x10200000 0x10200000
848 <0x82000000 0 !! 578 0 0x100000 /* downstream I/O */
>> 579 0x82000000 0 0x10300000 0x10300000
>> 580 0 0xd00000>; /* non-prefetchable memory */
849 581
850 interrupts = <GIC_SPI 582 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
851 interrupt-names = "msi 583 interrupt-names = "msi";
852 #interrupt-cells = <1> 584 #interrupt-cells = <1>;
853 interrupt-map-mask = < 585 interrupt-map-mask = <0 0 0 0x7>;
854 interrupt-map = <0 0 0 !! 586 interrupt-map = <0 0 0 1 &intc 0 142
855 IRQ_T 587 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
856 <0 0 0 !! 588 <0 0 0 2 &intc 0 143
857 IRQ_T 589 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
858 <0 0 0 !! 590 <0 0 0 3 &intc 0 144
859 IRQ_T 591 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
860 <0 0 0 !! 592 <0 0 0 4 &intc 0 145
861 IRQ_T 593 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
862 594
863 clocks = <&gcc GCC_SYS 595 clocks = <&gcc GCC_SYS_NOC_PCIE1_AXI_CLK>,
864 <&gcc GCC_PCI 596 <&gcc GCC_PCIE1_AXI_M_CLK>,
865 <&gcc GCC_PCI 597 <&gcc GCC_PCIE1_AXI_S_CLK>,
866 <&gcc GCC_PCI 598 <&gcc GCC_PCIE1_AHB_CLK>,
867 <&gcc GCC_PCI 599 <&gcc GCC_PCIE1_AUX_CLK>;
868 clock-names = "iface", 600 clock-names = "iface",
869 "axi_m", 601 "axi_m",
870 "axi_s", 602 "axi_s",
871 "ahb", 603 "ahb",
872 "aux"; 604 "aux";
873 resets = <&gcc GCC_PCI 605 resets = <&gcc GCC_PCIE1_PIPE_ARES>,
874 <&gcc GCC_PCI 606 <&gcc GCC_PCIE1_SLEEP_ARES>,
875 <&gcc GCC_PCI 607 <&gcc GCC_PCIE1_CORE_STICKY_ARES>,
876 <&gcc GCC_PCI 608 <&gcc GCC_PCIE1_AXI_MASTER_ARES>,
877 <&gcc GCC_PCI 609 <&gcc GCC_PCIE1_AXI_SLAVE_ARES>,
878 <&gcc GCC_PCI 610 <&gcc GCC_PCIE1_AHB_ARES>,
879 <&gcc GCC_PCI 611 <&gcc GCC_PCIE1_AXI_MASTER_STICKY_ARES>;
880 reset-names = "pipe", 612 reset-names = "pipe",
881 "sleep", 613 "sleep",
882 "sticky" 614 "sticky",
883 "axi_m", 615 "axi_m",
884 "axi_s", 616 "axi_s",
885 "ahb", 617 "ahb",
886 "axi_m_s 618 "axi_m_sticky";
887 status = "disabled"; 619 status = "disabled";
888 <<
889 pcie@0 { <<
890 device_type = <<
891 reg = <0x0 0x0 <<
892 bus-range = <0 <<
893 <<
894 #address-cells <<
895 #size-cells = <<
896 ranges; <<
897 }; <<
898 }; 620 };
899 621
900 pcie0: pcie@20000000 { !! 622 pcie0: pci@20000000 {
901 compatible = "qcom,pci !! 623 compatible = "qcom,pcie-ipq8074";
902 reg = <0x20000000 0xf1 !! 624 reg = <0x20000000 0xf1d
903 <0x20000f20 0xa8 !! 625 0x20000f20 0xa8
904 <0x20001000 0x10 !! 626 0x00080000 0x2000
905 <0x00080000 0x40 !! 627 0x20100000 0x1000>;
906 <0x20100000 0x10 !! 628 reg-names = "dbi", "elbi", "parf", "config";
907 reg-names = "dbi", "el <<
908 device_type = "pci"; 629 device_type = "pci";
909 linux,pci-domain = <0> 630 linux,pci-domain = <0>;
910 bus-range = <0x00 0xff 631 bus-range = <0x00 0xff>;
911 num-lanes = <1>; 632 num-lanes = <1>;
912 max-link-speed = <3>; <<
913 #address-cells = <3>; 633 #address-cells = <3>;
914 #size-cells = <2>; 634 #size-cells = <2>;
915 635
916 phys = <&pcie_qmp0>; !! 636 phys = <&pcie_phy0>;
917 phy-names = "pciephy"; 637 phy-names = "pciephy";
918 638
919 ranges = <0x81000000 0 !! 639 ranges = <0x81000000 0 0x20200000 0x20200000
920 <0x82000000 0 !! 640 0 0x100000 /* downstream I/O */
>> 641 0x82000000 0 0x20300000 0x20300000
>> 642 0 0xd00000>; /* non-prefetchable memory */
921 643
922 interrupts = <GIC_SPI 644 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
923 interrupt-names = "msi 645 interrupt-names = "msi";
924 #interrupt-cells = <1> 646 #interrupt-cells = <1>;
925 interrupt-map-mask = < 647 interrupt-map-mask = <0 0 0 0x7>;
926 interrupt-map = <0 0 0 !! 648 interrupt-map = <0 0 0 1 &intc 0 75
927 IRQ_T 649 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
928 <0 0 0 !! 650 <0 0 0 2 &intc 0 78
929 IRQ_T 651 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
930 <0 0 0 !! 652 <0 0 0 3 &intc 0 79
931 IRQ_T 653 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
932 <0 0 0 !! 654 <0 0 0 4 &intc 0 83
933 IRQ_T 655 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
934 656
935 clocks = <&gcc GCC_SYS 657 clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
936 <&gcc GCC_PCI 658 <&gcc GCC_PCIE0_AXI_M_CLK>,
937 <&gcc GCC_PCI 659 <&gcc GCC_PCIE0_AXI_S_CLK>,
938 <&gcc GCC_PCI !! 660 <&gcc GCC_PCIE0_AHB_CLK>,
939 <&gcc GCC_PCI !! 661 <&gcc GCC_PCIE0_AUX_CLK>;
>> 662
940 clock-names = "iface", 663 clock-names = "iface",
941 "axi_m", 664 "axi_m",
942 "axi_s", 665 "axi_s",
943 "axi_bri !! 666 "ahb",
944 "rchng"; !! 667 "aux";
945 <<
946 resets = <&gcc GCC_PCI 668 resets = <&gcc GCC_PCIE0_PIPE_ARES>,
947 <&gcc GCC_PCI 669 <&gcc GCC_PCIE0_SLEEP_ARES>,
948 <&gcc GCC_PCI 670 <&gcc GCC_PCIE0_CORE_STICKY_ARES>,
949 <&gcc GCC_PCI 671 <&gcc GCC_PCIE0_AXI_MASTER_ARES>,
950 <&gcc GCC_PCI 672 <&gcc GCC_PCIE0_AXI_SLAVE_ARES>,
951 <&gcc GCC_PCI 673 <&gcc GCC_PCIE0_AHB_ARES>,
952 <&gcc GCC_PCI !! 674 <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>;
953 <&gcc GCC_PCI <<
954 reset-names = "pipe", 675 reset-names = "pipe",
955 "sleep", 676 "sleep",
956 "sticky" 677 "sticky",
957 "axi_m", 678 "axi_m",
958 "axi_s", 679 "axi_s",
959 "ahb", 680 "ahb",
960 "axi_m_s !! 681 "axi_m_sticky";
961 "axi_s_s <<
962 status = "disabled"; 682 status = "disabled";
963 <<
964 pcie@0 { <<
965 device_type = <<
966 reg = <0x0 0x0 <<
967 bus-range = <0 <<
968 <<
969 #address-cells <<
970 #size-cells = <<
971 ranges; <<
972 }; <<
973 }; <<
974 }; <<
975 <<
976 timer { <<
977 compatible = "arm,armv8-timer" <<
978 interrupts = <GIC_PPI 2 (GIC_C <<
979 <GIC_PPI 3 (GIC_C <<
980 <GIC_PPI 4 (GIC_C <<
981 <GIC_PPI 1 (GIC_C <<
982 }; <<
983 <<
984 thermal-zones { <<
985 nss-top-thermal { <<
986 polling-delay-passive <<
987 <<
988 thermal-sensors = <&ts <<
989 <<
990 trips { <<
991 nss-top-crit { <<
992 temper <<
993 hyster <<
994 type = <<
995 }; <<
996 }; <<
997 }; <<
998 <<
999 nss0-thermal { <<
1000 polling-delay-passive <<
1001 <<
1002 thermal-sensors = <&t <<
1003 <<
1004 trips { <<
1005 nss-0-crit { <<
1006 tempe <<
1007 hyste <<
1008 type <<
1009 }; <<
1010 }; <<
1011 }; <<
1012 <<
1013 nss1-thermal { <<
1014 polling-delay-passive <<
1015 <<
1016 thermal-sensors = <&t <<
1017 <<
1018 trips { <<
1019 nss-1-crit { <<
1020 tempe <<
1021 hyste <<
1022 type <<
1023 }; <<
1024 }; <<
1025 }; <<
1026 <<
1027 wcss-phya0-thermal { <<
1028 polling-delay-passive <<
1029 <<
1030 thermal-sensors = <&t <<
1031 <<
1032 trips { <<
1033 wcss-phya0-cr <<
1034 tempe <<
1035 hyste <<
1036 type <<
1037 }; <<
1038 }; <<
1039 }; <<
1040 <<
1041 wcss-phya1-thermal { <<
1042 polling-delay-passive <<
1043 <<
1044 thermal-sensors = <&t <<
1045 <<
1046 trips { <<
1047 wcss-phya1-cr <<
1048 tempe <<
1049 hyste <<
1050 type <<
1051 }; <<
1052 }; <<
1053 }; <<
1054 <<
1055 cpu0_thermal: cpu0-thermal { <<
1056 polling-delay-passive <<
1057 <<
1058 thermal-sensors = <&t <<
1059 <<
1060 trips { <<
1061 cpu0-crit { <<
1062 tempe <<
1063 hyste <<
1064 type <<
1065 }; <<
1066 }; <<
1067 }; <<
1068 <<
1069 cpu1_thermal: cpu1-thermal { <<
1070 polling-delay-passive <<
1071 <<
1072 thermal-sensors = <&t <<
1073 <<
1074 trips { <<
1075 cpu1-crit { <<
1076 tempe <<
1077 hyste <<
1078 type <<
1079 }; <<
1080 }; <<
1081 }; <<
1082 <<
1083 cpu2_thermal: cpu2-thermal { <<
1084 polling-delay-passive <<
1085 <<
1086 thermal-sensors = <&t <<
1087 <<
1088 trips { <<
1089 cpu2-crit { <<
1090 tempe <<
1091 hyste <<
1092 type <<
1093 }; <<
1094 }; <<
1095 }; <<
1096 <<
1097 cpu3_thermal: cpu3-thermal { <<
1098 polling-delay-passive <<
1099 <<
1100 thermal-sensors = <&t <<
1101 <<
1102 trips { <<
1103 cpu3-crit { <<
1104 tempe <<
1105 hyste <<
1106 type <<
1107 }; <<
1108 }; <<
1109 }; <<
1110 <<
1111 cluster_thermal: cluster-ther <<
1112 polling-delay-passive <<
1113 <<
1114 thermal-sensors = <&t <<
1115 <<
1116 trips { <<
1117 cluster-crit <<
1118 tempe <<
1119 hyste <<
1120 type <<
1121 }; <<
1122 }; <<
1123 }; <<
1124 <<
1125 wcss-phyb0-thermal { <<
1126 polling-delay-passive <<
1127 <<
1128 thermal-sensors = <&t <<
1129 <<
1130 trips { <<
1131 wcss-phyb0-cr <<
1132 tempe <<
1133 hyste <<
1134 type <<
1135 }; <<
1136 }; <<
1137 }; <<
1138 <<
1139 wcss-phyb1-thermal { <<
1140 polling-delay-passive <<
1141 <<
1142 thermal-sensors = <&t <<
1143 <<
1144 trips { <<
1145 wcss-phyb1-cr <<
1146 tempe <<
1147 hyste <<
1148 type <<
1149 }; <<
1150 }; <<
1151 }; 683 };
1152 }; 684 };
1153 }; 685 };
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