1 // SPDX-License-Identifier: GPL-2.0-only 1 // SPDX-License-Identifier: GPL-2.0-only
2 /* 2 /*
3 * Copyright (c) 2017, The Linux Foundation. A 3 * Copyright (c) 2017, The Linux Foundation. All rights reserved.
4 */ 4 */
5 5
6 #include <dt-bindings/interrupt-controller/arm 6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,gcc-ipq8074.h 7 #include <dt-bindings/clock/qcom,gcc-ipq8074.h>
8 8
9 / { 9 / {
10 #address-cells = <2>; 10 #address-cells = <2>;
11 #size-cells = <2>; 11 #size-cells = <2>;
12 12
13 model = "Qualcomm Technologies, Inc. I 13 model = "Qualcomm Technologies, Inc. IPQ8074";
14 compatible = "qcom,ipq8074"; 14 compatible = "qcom,ipq8074";
15 interrupt-parent = <&intc>; 15 interrupt-parent = <&intc>;
16 16
17 clocks { 17 clocks {
18 sleep_clk: sleep_clk { 18 sleep_clk: sleep_clk {
19 compatible = "fixed-cl 19 compatible = "fixed-clock";
20 clock-frequency = <327 20 clock-frequency = <32768>;
21 #clock-cells = <0>; 21 #clock-cells = <0>;
22 }; 22 };
23 23
24 xo: xo { 24 xo: xo {
25 compatible = "fixed-cl 25 compatible = "fixed-clock";
26 clock-frequency = <192 26 clock-frequency = <19200000>;
27 #clock-cells = <0>; 27 #clock-cells = <0>;
28 }; 28 };
29 }; 29 };
30 30
31 cpus { 31 cpus {
32 #address-cells = <1>; !! 32 #address-cells = <0x1>;
33 #size-cells = <0>; !! 33 #size-cells = <0x0>;
34 34
35 CPU0: cpu@0 { 35 CPU0: cpu@0 {
36 device_type = "cpu"; 36 device_type = "cpu";
37 compatible = "arm,cort 37 compatible = "arm,cortex-a53";
38 reg = <0x0>; 38 reg = <0x0>;
39 next-level-cache = <&L 39 next-level-cache = <&L2_0>;
40 enable-method = "psci" 40 enable-method = "psci";
41 }; 41 };
42 42
43 CPU1: cpu@1 { 43 CPU1: cpu@1 {
44 device_type = "cpu"; 44 device_type = "cpu";
45 compatible = "arm,cort 45 compatible = "arm,cortex-a53";
46 enable-method = "psci" 46 enable-method = "psci";
47 reg = <0x1>; 47 reg = <0x1>;
48 next-level-cache = <&L 48 next-level-cache = <&L2_0>;
49 }; 49 };
50 50
51 CPU2: cpu@2 { 51 CPU2: cpu@2 {
52 device_type = "cpu"; 52 device_type = "cpu";
53 compatible = "arm,cort 53 compatible = "arm,cortex-a53";
54 enable-method = "psci" 54 enable-method = "psci";
55 reg = <0x2>; 55 reg = <0x2>;
56 next-level-cache = <&L 56 next-level-cache = <&L2_0>;
57 }; 57 };
58 58
59 CPU3: cpu@3 { 59 CPU3: cpu@3 {
60 device_type = "cpu"; 60 device_type = "cpu";
61 compatible = "arm,cort 61 compatible = "arm,cortex-a53";
62 enable-method = "psci" 62 enable-method = "psci";
63 reg = <0x3>; 63 reg = <0x3>;
64 next-level-cache = <&L 64 next-level-cache = <&L2_0>;
65 }; 65 };
66 66
67 L2_0: l2-cache { 67 L2_0: l2-cache {
68 compatible = "cache"; 68 compatible = "cache";
69 cache-level = <2>; !! 69 cache-level = <0x2>;
70 cache-unified; <<
71 }; 70 };
72 }; 71 };
73 72
74 pmu { 73 pmu {
75 compatible = "arm,cortex-a53-p 74 compatible = "arm,cortex-a53-pmu";
76 interrupts = <GIC_PPI 7 (GIC_C 75 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
77 }; 76 };
78 77
79 psci { 78 psci {
80 compatible = "arm,psci-1.0"; 79 compatible = "arm,psci-1.0";
81 method = "smc"; 80 method = "smc";
82 }; 81 };
83 82
84 reserved-memory { 83 reserved-memory {
85 #address-cells = <2>; 84 #address-cells = <2>;
86 #size-cells = <2>; 85 #size-cells = <2>;
87 ranges; 86 ranges;
88 87
89 bootloader@4a600000 { <<
90 reg = <0x0 0x4a600000 <<
91 no-map; <<
92 }; <<
93 <<
94 sbl@4aa00000 { <<
95 reg = <0x0 0x4aa00000 <<
96 no-map; <<
97 }; <<
98 <<
99 smem@4ab00000 { 88 smem@4ab00000 {
100 compatible = "qcom,sme 89 compatible = "qcom,smem";
101 reg = <0x0 0x4ab00000 !! 90 reg = <0x0 0x4ab00000 0x0 0x00100000>;
102 no-map; 91 no-map;
103 92
104 hwlocks = <&tcsr_mutex !! 93 hwlocks = <&tcsr_mutex 0>;
105 }; 94 };
106 95
107 memory@4ac00000 { 96 memory@4ac00000 {
108 reg = <0x0 0x4ac00000 <<
109 no-map; 97 no-map;
>> 98 reg = <0x0 0x4ac00000 0x0 0x00400000>;
110 }; 99 };
111 }; 100 };
112 101
113 firmware { 102 firmware {
114 scm { 103 scm {
115 compatible = "qcom,scm 104 compatible = "qcom,scm-ipq8074", "qcom,scm";
116 qcom,dload-mode = <&tc <<
117 }; 105 };
118 }; 106 };
119 107
120 soc: soc@0 { !! 108 soc: soc {
121 #address-cells = <1>; !! 109 #address-cells = <0x1>;
122 #size-cells = <1>; !! 110 #size-cells = <0x1>;
123 ranges = <0 0 0 0xffffffff>; 111 ranges = <0 0 0 0xffffffff>;
124 compatible = "simple-bus"; 112 compatible = "simple-bus";
125 113
126 ssphy_1: phy@58000 { 114 ssphy_1: phy@58000 {
127 compatible = "qcom,ipq 115 compatible = "qcom,ipq8074-qmp-usb3-phy";
128 reg = <0x00058000 0x10 !! 116 reg = <0x00058000 0x1c4>;
>> 117 #address-cells = <1>;
>> 118 #size-cells = <1>;
>> 119 ranges;
129 120
130 clocks = <&gcc GCC_USB 121 clocks = <&gcc GCC_USB1_AUX_CLK>,
131 <&xo>, !! 122 <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
132 <&gcc GCC_USB !! 123 <&xo>;
133 <&gcc GCC_USB !! 124 clock-names = "aux", "cfg_ahb", "ref";
134 clock-names = "aux", <<
135 "ref", <<
136 "cfg_ahb <<
137 "pipe"; <<
138 clock-output-names = " <<
139 #clock-cells = <0>; <<
140 #phy-cells = <0>; <<
141 125
142 resets = <&gcc GCC_USB 126 resets = <&gcc GCC_USB1_PHY_BCR>,
143 <&gcc GCC_USB !! 127 <&gcc GCC_USB3PHY_1_PHY_BCR>;
144 reset-names = "phy", !! 128 reset-names = "phy","common";
145 "phy_phy <<
146 <<
147 status = "disabled"; 129 status = "disabled";
>> 130
>> 131 usb1_ssphy: phy@58200 {
>> 132 reg = <0x00058200 0x130>, /* Tx */
>> 133 <0x00058400 0x200>, /* Rx */
>> 134 <0x00058800 0x1f8>, /* PCS */
>> 135 <0x00058600 0x044>; /* PCS misc */
>> 136 #phy-cells = <0>;
>> 137 #clock-cells = <0>;
>> 138 clocks = <&gcc GCC_USB1_PIPE_CLK>;
>> 139 clock-names = "pipe0";
>> 140 clock-output-names = "usb3phy_1_cc_pipe_clk";
>> 141 };
148 }; 142 };
149 143
150 qusb_phy_1: phy@59000 { 144 qusb_phy_1: phy@59000 {
151 compatible = "qcom,ipq 145 compatible = "qcom,ipq8074-qusb2-phy";
152 reg = <0x00059000 0x18 146 reg = <0x00059000 0x180>;
153 #phy-cells = <0>; 147 #phy-cells = <0>;
154 148
155 clocks = <&gcc GCC_USB 149 clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
156 <&xo>; 150 <&xo>;
157 clock-names = "cfg_ahb 151 clock-names = "cfg_ahb", "ref";
158 152
159 resets = <&gcc GCC_QUS 153 resets = <&gcc GCC_QUSB2_1_PHY_BCR>;
160 status = "disabled"; 154 status = "disabled";
161 }; 155 };
162 156
163 ssphy_0: phy@78000 { 157 ssphy_0: phy@78000 {
164 compatible = "qcom,ipq 158 compatible = "qcom,ipq8074-qmp-usb3-phy";
165 reg = <0x00078000 0x10 !! 159 reg = <0x00078000 0x1c4>;
>> 160 #address-cells = <1>;
>> 161 #size-cells = <1>;
>> 162 ranges;
166 163
167 clocks = <&gcc GCC_USB 164 clocks = <&gcc GCC_USB0_AUX_CLK>,
168 <&xo>, !! 165 <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
169 <&gcc GCC_USB !! 166 <&xo>;
170 <&gcc GCC_USB !! 167 clock-names = "aux", "cfg_ahb", "ref";
171 clock-names = "aux", <<
172 "ref", <<
173 "cfg_ahb <<
174 "pipe"; <<
175 clock-output-names = " <<
176 #clock-cells = <0>; <<
177 #phy-cells = <0>; <<
178 168
179 resets = <&gcc GCC_USB 169 resets = <&gcc GCC_USB0_PHY_BCR>,
180 <&gcc GCC_USB !! 170 <&gcc GCC_USB3PHY_0_PHY_BCR>;
181 reset-names = "phy", !! 171 reset-names = "phy","common";
182 "phy_phy <<
183 <<
184 status = "disabled"; 172 status = "disabled";
>> 173
>> 174 usb0_ssphy: phy@78200 {
>> 175 reg = <0x00078200 0x130>, /* Tx */
>> 176 <0x00078400 0x200>, /* Rx */
>> 177 <0x00078800 0x1f8>, /* PCS */
>> 178 <0x00078600 0x044>; /* PCS misc */
>> 179 #phy-cells = <0>;
>> 180 #clock-cells = <0>;
>> 181 clocks = <&gcc GCC_USB0_PIPE_CLK>;
>> 182 clock-names = "pipe0";
>> 183 clock-output-names = "usb3phy_0_cc_pipe_clk";
>> 184 };
185 }; 185 };
186 186
187 qusb_phy_0: phy@79000 { 187 qusb_phy_0: phy@79000 {
188 compatible = "qcom,ipq 188 compatible = "qcom,ipq8074-qusb2-phy";
189 reg = <0x00079000 0x18 189 reg = <0x00079000 0x180>;
190 #phy-cells = <0>; 190 #phy-cells = <0>;
191 191
192 clocks = <&gcc GCC_USB 192 clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
193 <&xo>; 193 <&xo>;
194 clock-names = "cfg_ahb 194 clock-names = "cfg_ahb", "ref";
195 195
196 resets = <&gcc GCC_QUS 196 resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
197 status = "disabled"; 197 status = "disabled";
198 }; 198 };
199 199
200 pcie_qmp0: phy@84000 { 200 pcie_qmp0: phy@84000 {
201 compatible = "qcom,ipq 201 compatible = "qcom,ipq8074-qmp-gen3-pcie-phy";
202 reg = <0x00084000 0x10 !! 202 reg = <0x00084000 0x1bc>;
>> 203 #address-cells = <1>;
>> 204 #size-cells = <1>;
>> 205 ranges;
203 206
204 clocks = <&gcc GCC_PCI 207 clocks = <&gcc GCC_PCIE0_AUX_CLK>,
205 <&gcc GCC_PCI !! 208 <&gcc GCC_PCIE0_AHB_CLK>;
206 <&gcc GCC_PCI !! 209 clock-names = "aux", "cfg_ahb";
207 clock-names = "aux", <<
208 "cfg_ahb <<
209 "pipe"; <<
210 <<
211 clock-output-names = " <<
212 #clock-cells = <0>; <<
213 <<
214 #phy-cells = <0>; <<
215 <<
216 resets = <&gcc GCC_PCI 210 resets = <&gcc GCC_PCIE0_PHY_BCR>,
217 <&gcc GCC_PCI !! 211 <&gcc GCC_PCIE0PHY_PHY_BCR>;
218 reset-names = "phy", 212 reset-names = "phy",
219 "common" 213 "common";
220 status = "disabled"; 214 status = "disabled";
>> 215
>> 216 pcie_phy0: phy@84200 {
>> 217 reg = <0x84200 0x16c>,
>> 218 <0x84400 0x200>,
>> 219 <0x84800 0x1f0>,
>> 220 <0x84c00 0xf4>;
>> 221 #phy-cells = <0>;
>> 222 #clock-cells = <0>;
>> 223 clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
>> 224 clock-names = "pipe0";
>> 225 clock-output-names = "pcie20_phy0_pipe_clk";
>> 226 };
221 }; 227 };
222 228
223 pcie_qmp1: phy@8e000 { 229 pcie_qmp1: phy@8e000 {
224 compatible = "qcom,ipq 230 compatible = "qcom,ipq8074-qmp-pcie-phy";
225 reg = <0x0008e000 0x10 !! 231 reg = <0x0008e000 0x1c4>;
>> 232 #address-cells = <1>;
>> 233 #size-cells = <1>;
>> 234 ranges;
226 235
227 clocks = <&gcc GCC_PCI 236 clocks = <&gcc GCC_PCIE1_AUX_CLK>,
228 <&gcc GCC_PCI !! 237 <&gcc GCC_PCIE1_AHB_CLK>;
229 <&gcc GCC_PCI !! 238 clock-names = "aux", "cfg_ahb";
230 clock-names = "aux", <<
231 "cfg_ahb <<
232 "pipe"; <<
233 <<
234 clock-output-names = " <<
235 #clock-cells = <0>; <<
236 <<
237 #phy-cells = <0>; <<
238 <<
239 resets = <&gcc GCC_PCI 239 resets = <&gcc GCC_PCIE1_PHY_BCR>,
240 <&gcc GCC_PCI !! 240 <&gcc GCC_PCIE1PHY_PHY_BCR>;
241 reset-names = "phy", 241 reset-names = "phy",
242 "common" 242 "common";
243 status = "disabled"; 243 status = "disabled";
>> 244
>> 245 pcie_phy1: phy@8e200 {
>> 246 reg = <0x8e200 0x130>,
>> 247 <0x8e400 0x200>,
>> 248 <0x8e800 0x1f8>;
>> 249 #phy-cells = <0>;
>> 250 #clock-cells = <0>;
>> 251 clocks = <&gcc GCC_PCIE1_PIPE_CLK>;
>> 252 clock-names = "pipe0";
>> 253 clock-output-names = "pcie20_phy1_pipe_clk";
>> 254 };
244 }; 255 };
245 256
246 mdio: mdio@90000 { 257 mdio: mdio@90000 {
247 compatible = "qcom,ipq !! 258 compatible = "qcom,ipq4019-mdio";
248 reg = <0x00090000 0x64 259 reg = <0x00090000 0x64>;
249 #address-cells = <1>; 260 #address-cells = <1>;
250 #size-cells = <0>; 261 #size-cells = <0>;
251 262
252 clocks = <&gcc GCC_MDI 263 clocks = <&gcc GCC_MDIO_AHB_CLK>;
253 clock-names = "gcc_mdi 264 clock-names = "gcc_mdio_ahb_clk";
254 265
255 clock-frequency = <625 <<
256 <<
257 status = "disabled"; 266 status = "disabled";
258 }; 267 };
259 268
260 qfprom: efuse@a4000 { <<
261 compatible = "qcom,ipq <<
262 reg = <0x000a4000 0x20 <<
263 #address-cells = <1>; <<
264 #size-cells = <1>; <<
265 }; <<
266 <<
267 prng: rng@e3000 { 269 prng: rng@e3000 {
268 compatible = "qcom,prn 270 compatible = "qcom,prng-ee";
269 reg = <0x000e3000 0x10 271 reg = <0x000e3000 0x1000>;
270 clocks = <&gcc GCC_PRN 272 clocks = <&gcc GCC_PRNG_AHB_CLK>;
271 clock-names = "core"; 273 clock-names = "core";
272 status = "disabled"; 274 status = "disabled";
273 }; 275 };
274 276
275 tsens: thermal-sensor@4a9000 { 277 tsens: thermal-sensor@4a9000 {
276 compatible = "qcom,ipq 278 compatible = "qcom,ipq8074-tsens";
277 reg = <0x4a9000 0x1000 279 reg = <0x4a9000 0x1000>, /* TM */
278 <0x4a8000 0x1000 280 <0x4a8000 0x1000>; /* SROT */
279 interrupts = <GIC_SPI 281 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
280 interrupt-names = "com 282 interrupt-names = "combined";
281 #qcom,sensors = <16>; 283 #qcom,sensors = <16>;
282 #thermal-sensor-cells 284 #thermal-sensor-cells = <1>;
283 }; 285 };
284 286
285 cryptobam: dma-controller@7040 287 cryptobam: dma-controller@704000 {
286 compatible = "qcom,bam 288 compatible = "qcom,bam-v1.7.0";
287 reg = <0x00704000 0x20 289 reg = <0x00704000 0x20000>;
288 interrupts = <GIC_SPI 290 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
289 clocks = <&gcc GCC_CRY 291 clocks = <&gcc GCC_CRYPTO_AHB_CLK>;
290 clock-names = "bam_clk 292 clock-names = "bam_clk";
291 #dma-cells = <1>; 293 #dma-cells = <1>;
292 qcom,ee = <1>; 294 qcom,ee = <1>;
293 qcom,controlled-remote 295 qcom,controlled-remotely;
294 status = "disabled"; 296 status = "disabled";
295 }; 297 };
296 298
297 crypto: crypto@73a000 { 299 crypto: crypto@73a000 {
298 compatible = "qcom,cry 300 compatible = "qcom,crypto-v5.1";
299 reg = <0x0073a000 0x60 301 reg = <0x0073a000 0x6000>;
300 clocks = <&gcc GCC_CRY 302 clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
301 <&gcc GCC_CRY 303 <&gcc GCC_CRYPTO_AXI_CLK>,
302 <&gcc GCC_CRY 304 <&gcc GCC_CRYPTO_CLK>;
303 clock-names = "iface", 305 clock-names = "iface", "bus", "core";
304 dmas = <&cryptobam 2>, 306 dmas = <&cryptobam 2>, <&cryptobam 3>;
305 dma-names = "rx", "tx" 307 dma-names = "rx", "tx";
306 status = "disabled"; 308 status = "disabled";
307 }; 309 };
308 310
309 tlmm: pinctrl@1000000 { 311 tlmm: pinctrl@1000000 {
310 compatible = "qcom,ipq 312 compatible = "qcom,ipq8074-pinctrl";
311 reg = <0x01000000 0x30 313 reg = <0x01000000 0x300000>;
312 interrupts = <GIC_SPI 314 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
313 gpio-controller; 315 gpio-controller;
314 gpio-ranges = <&tlmm 0 316 gpio-ranges = <&tlmm 0 0 70>;
315 #gpio-cells = <2>; !! 317 #gpio-cells = <0x2>;
316 interrupt-controller; 318 interrupt-controller;
317 #interrupt-cells = <2> !! 319 #interrupt-cells = <0x2>;
318 320
319 serial_4_pins: serial4 321 serial_4_pins: serial4-state {
320 pins = "gpio23 322 pins = "gpio23", "gpio24";
321 function = "bl 323 function = "blsp4_uart1";
322 drive-strength 324 drive-strength = <8>;
323 bias-disable; 325 bias-disable;
324 }; 326 };
325 327
326 serial_5_pins: serial5 <<
327 pins = "gpio9" <<
328 function = "bl <<
329 drive-strength <<
330 bias-disable; <<
331 }; <<
332 <<
333 i2c_0_pins: i2c-0-stat 328 i2c_0_pins: i2c-0-state {
334 pins = "gpio42 329 pins = "gpio42", "gpio43";
335 function = "bl 330 function = "blsp1_i2c";
336 drive-strength 331 drive-strength = <8>;
337 bias-disable; 332 bias-disable;
338 }; 333 };
339 334
340 spi_0_pins: spi-0-stat 335 spi_0_pins: spi-0-state {
341 pins = "gpio38 336 pins = "gpio38", "gpio39", "gpio40", "gpio41";
342 function = "bl 337 function = "blsp0_spi";
343 drive-strength 338 drive-strength = <8>;
344 bias-disable; 339 bias-disable;
345 }; 340 };
346 341
347 hsuart_pins: hsuart-st 342 hsuart_pins: hsuart-state {
348 pins = "gpio46 343 pins = "gpio46", "gpio47", "gpio48", "gpio49";
349 function = "bl 344 function = "blsp2_uart";
350 drive-strength 345 drive-strength = <8>;
351 bias-disable; 346 bias-disable;
352 }; 347 };
353 348
354 qpic_pins: qpic-state 349 qpic_pins: qpic-state {
355 pins = "gpio1" 350 pins = "gpio1", "gpio3", "gpio4",
356 "gpio5" 351 "gpio5", "gpio6", "gpio7",
357 "gpio8" 352 "gpio8", "gpio10", "gpio11",
358 "gpio12 353 "gpio12", "gpio13", "gpio14",
359 "gpio15 !! 354 "gpio15", "gpio16", "gpio17";
360 function = "qp 355 function = "qpic";
361 drive-strength 356 drive-strength = <8>;
362 bias-disable; 357 bias-disable;
363 }; 358 };
364 }; 359 };
365 360
366 gcc: clock-controller@1800000 !! 361 gcc: gcc@1800000 {
367 compatible = "qcom,gcc 362 compatible = "qcom,gcc-ipq8074";
368 reg = <0x01800000 0x80 363 reg = <0x01800000 0x80000>;
369 clocks = <&xo>, !! 364 clocks = <&xo>, <&sleep_clk>;
370 <&sleep_clk>, !! 365 clock-names = "xo", "sleep_clk";
371 <&pcie_qmp0>, <<
372 <&pcie_qmp1>; <<
373 clock-names = "xo", <<
374 "sleep_c <<
375 "pcie0_p <<
376 "pcie1_p <<
377 #clock-cells = <1>; 366 #clock-cells = <1>;
378 #power-domain-cells = 367 #power-domain-cells = <1>;
379 #reset-cells = <1>; 368 #reset-cells = <1>;
380 }; 369 };
381 370
382 tcsr_mutex: hwlock@1905000 { 371 tcsr_mutex: hwlock@1905000 {
383 compatible = "qcom,tcs 372 compatible = "qcom,tcsr-mutex";
384 reg = <0x01905000 0x20 373 reg = <0x01905000 0x20000>;
385 #hwlock-cells = <1>; 374 #hwlock-cells = <1>;
386 }; 375 };
387 376
388 tcsr: syscon@1937000 { <<
389 compatible = "qcom,tcs <<
390 reg = <0x01937000 0x21 <<
391 }; <<
392 <<
393 spmi_bus: spmi@200f000 { 377 spmi_bus: spmi@200f000 {
394 compatible = "qcom,spm 378 compatible = "qcom,spmi-pmic-arb";
395 reg = <0x0200f000 0x00 379 reg = <0x0200f000 0x001000>,
396 <0x02400000 0x80 380 <0x02400000 0x800000>,
397 <0x02c00000 0x80 381 <0x02c00000 0x800000>,
398 <0x03800000 0x20 382 <0x03800000 0x200000>,
399 <0x0200a000 0x00 383 <0x0200a000 0x000700>;
400 reg-names = "core", "c 384 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
401 interrupts = <GIC_SPI 385 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
402 interrupt-names = "per 386 interrupt-names = "periph_irq";
403 qcom,ee = <0>; 387 qcom,ee = <0>;
404 qcom,channel = <0>; 388 qcom,channel = <0>;
405 #address-cells = <2>; 389 #address-cells = <2>;
406 #size-cells = <0>; 390 #size-cells = <0>;
407 interrupt-controller; 391 interrupt-controller;
408 #interrupt-cells = <4> 392 #interrupt-cells = <4>;
>> 393 cell-index = <0>;
409 }; 394 };
410 395
411 sdhc_1: mmc@7824900 { 396 sdhc_1: mmc@7824900 {
412 compatible = "qcom,ipq !! 397 compatible = "qcom,sdhci-msm-v4";
413 reg = <0x7824900 0x500 398 reg = <0x7824900 0x500>, <0x7824000 0x800>;
414 reg-names = "hc", "cor 399 reg-names = "hc", "core";
415 400
416 interrupts = <GIC_SPI 401 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
417 <GIC_SPI 402 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
418 interrupt-names = "hc_ 403 interrupt-names = "hc_irq", "pwr_irq";
419 404
420 clocks = <&gcc GCC_SDC 405 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
421 <&gcc GCC_SDC 406 <&gcc GCC_SDCC1_APPS_CLK>,
422 <&xo>; 407 <&xo>;
423 clock-names = "iface", 408 clock-names = "iface", "core", "xo";
424 resets = <&gcc GCC_SDC 409 resets = <&gcc GCC_SDCC1_BCR>;
425 max-frequency = <38400 410 max-frequency = <384000000>;
426 mmc-ddr-1_8v; 411 mmc-ddr-1_8v;
427 mmc-hs200-1_8v; 412 mmc-hs200-1_8v;
428 mmc-hs400-1_8v; 413 mmc-hs400-1_8v;
429 bus-width = <8>; 414 bus-width = <8>;
430 415
431 status = "disabled"; 416 status = "disabled";
432 }; 417 };
433 418
434 blsp_dma: dma-controller@78840 419 blsp_dma: dma-controller@7884000 {
435 compatible = "qcom,bam 420 compatible = "qcom,bam-v1.7.0";
436 reg = <0x07884000 0x2b 421 reg = <0x07884000 0x2b000>;
437 interrupts = <GIC_SPI 422 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
438 clocks = <&gcc GCC_BLS 423 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
439 clock-names = "bam_clk 424 clock-names = "bam_clk";
440 #dma-cells = <1>; 425 #dma-cells = <1>;
441 qcom,ee = <0>; 426 qcom,ee = <0>;
442 }; 427 };
443 428
444 blsp1_uart1: serial@78af000 { 429 blsp1_uart1: serial@78af000 {
445 compatible = "qcom,msm 430 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
446 reg = <0x078af000 0x20 431 reg = <0x078af000 0x200>;
447 interrupts = <GIC_SPI 432 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
448 clocks = <&gcc GCC_BLS 433 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
449 <&gcc GCC_BLS 434 <&gcc GCC_BLSP1_AHB_CLK>;
450 clock-names = "core", 435 clock-names = "core", "iface";
451 status = "disabled"; 436 status = "disabled";
452 }; 437 };
453 438
454 blsp1_uart3: serial@78b1000 { 439 blsp1_uart3: serial@78b1000 {
455 compatible = "qcom,msm 440 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
456 reg = <0x078b1000 0x20 441 reg = <0x078b1000 0x200>;
457 interrupts = <GIC_SPI 442 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
458 clocks = <&gcc GCC_BLS 443 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
459 <&gcc GCC_BLSP 444 <&gcc GCC_BLSP1_AHB_CLK>;
460 clock-names = "core", 445 clock-names = "core", "iface";
461 dmas = <&blsp_dma 4>, 446 dmas = <&blsp_dma 4>,
462 <&blsp_dma 5>; 447 <&blsp_dma 5>;
463 dma-names = "tx", "rx" 448 dma-names = "tx", "rx";
464 pinctrl-0 = <&hsuart_p 449 pinctrl-0 = <&hsuart_pins>;
465 pinctrl-names = "defau 450 pinctrl-names = "default";
466 status = "disabled"; 451 status = "disabled";
467 }; 452 };
468 453
469 blsp1_uart5: serial@78b3000 { 454 blsp1_uart5: serial@78b3000 {
470 compatible = "qcom,msm 455 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
471 reg = <0x078b3000 0x20 456 reg = <0x078b3000 0x200>;
472 interrupts = <GIC_SPI 457 interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
473 clocks = <&gcc GCC_BLS 458 clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>,
474 <&gcc GCC_BLS 459 <&gcc GCC_BLSP1_AHB_CLK>;
475 clock-names = "core", 460 clock-names = "core", "iface";
476 pinctrl-0 = <&serial_4 461 pinctrl-0 = <&serial_4_pins>;
477 pinctrl-names = "defau 462 pinctrl-names = "default";
478 status = "disabled"; 463 status = "disabled";
479 }; 464 };
480 465
481 blsp1_uart6: serial@78b4000 { <<
482 compatible = "qcom,msm <<
483 reg = <0x078b4000 0x20 <<
484 interrupts = <GIC_SPI <<
485 clocks = <&gcc GCC_BLS <<
486 <&gcc GCC_BLS <<
487 clock-names = "core", <<
488 pinctrl-0 = <&serial_5 <<
489 pinctrl-names = "defau <<
490 status = "disabled"; <<
491 }; <<
492 <<
493 blsp1_spi1: spi@78b5000 { 466 blsp1_spi1: spi@78b5000 {
494 compatible = "qcom,spi 467 compatible = "qcom,spi-qup-v2.2.1";
495 #address-cells = <1>; 468 #address-cells = <1>;
496 #size-cells = <0>; 469 #size-cells = <0>;
497 reg = <0x078b5000 0x60 470 reg = <0x078b5000 0x600>;
498 interrupts = <GIC_SPI 471 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
>> 472 spi-max-frequency = <50000000>;
499 clocks = <&gcc GCC_BLS 473 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
500 <&gcc GCC_BLSP 474 <&gcc GCC_BLSP1_AHB_CLK>;
501 clock-names = "core", 475 clock-names = "core", "iface";
502 dmas = <&blsp_dma 12>, 476 dmas = <&blsp_dma 12>, <&blsp_dma 13>;
503 dma-names = "tx", "rx" 477 dma-names = "tx", "rx";
504 pinctrl-0 = <&spi_0_pi 478 pinctrl-0 = <&spi_0_pins>;
505 pinctrl-names = "defau 479 pinctrl-names = "default";
506 status = "disabled"; 480 status = "disabled";
507 }; 481 };
508 482
509 blsp1_i2c2: i2c@78b6000 { 483 blsp1_i2c2: i2c@78b6000 {
510 compatible = "qcom,i2c 484 compatible = "qcom,i2c-qup-v2.2.1";
511 #address-cells = <1>; 485 #address-cells = <1>;
512 #size-cells = <0>; 486 #size-cells = <0>;
513 reg = <0x078b6000 0x60 487 reg = <0x078b6000 0x600>;
514 interrupts = <GIC_SPI 488 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
515 clocks = <&gcc GCC_BLS 489 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
516 <&gcc GCC_BLS 490 <&gcc GCC_BLSP1_AHB_CLK>;
517 clock-names = "core", 491 clock-names = "core", "iface";
518 clock-frequency = <400 492 clock-frequency = <400000>;
519 dmas = <&blsp_dma 14>, 493 dmas = <&blsp_dma 14>, <&blsp_dma 15>;
520 dma-names = "tx", "rx" 494 dma-names = "tx", "rx";
521 pinctrl-0 = <&i2c_0_pi 495 pinctrl-0 = <&i2c_0_pins>;
522 pinctrl-names = "defau 496 pinctrl-names = "default";
523 status = "disabled"; 497 status = "disabled";
524 }; 498 };
525 499
526 blsp1_i2c3: i2c@78b7000 { 500 blsp1_i2c3: i2c@78b7000 {
527 compatible = "qcom,i2c 501 compatible = "qcom,i2c-qup-v2.2.1";
528 #address-cells = <1>; 502 #address-cells = <1>;
529 #size-cells = <0>; 503 #size-cells = <0>;
530 reg = <0x078b7000 0x60 504 reg = <0x078b7000 0x600>;
531 interrupts = <GIC_SPI 505 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
532 clocks = <&gcc GCC_BLS 506 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
533 <&gcc GCC_BLS 507 <&gcc GCC_BLSP1_AHB_CLK>;
534 clock-names = "core", 508 clock-names = "core", "iface";
535 clock-frequency = <100 509 clock-frequency = <100000>;
536 dmas = <&blsp_dma 16>, 510 dmas = <&blsp_dma 16>, <&blsp_dma 17>;
537 dma-names = "tx", "rx" 511 dma-names = "tx", "rx";
538 status = "disabled"; 512 status = "disabled";
539 }; 513 };
540 514
541 blsp1_spi4: spi@78b8000 { <<
542 compatible = "qcom,spi <<
543 #address-cells = <1>; <<
544 #size-cells = <0>; <<
545 reg = <0x78b8000 0x600 <<
546 interrupts = <GIC_SPI <<
547 clocks = <&gcc GCC_BLS <<
548 <&gcc GCC_BLS <<
549 clock-names = "core", <<
550 dmas = <&blsp_dma 18>, <<
551 dma-names = "tx", "rx" <<
552 status = "disabled"; <<
553 }; <<
554 <<
555 blsp1_i2c5: i2c@78b9000 { 515 blsp1_i2c5: i2c@78b9000 {
556 compatible = "qcom,i2c 516 compatible = "qcom,i2c-qup-v2.2.1";
557 #address-cells = <1>; 517 #address-cells = <1>;
558 #size-cells = <0>; 518 #size-cells = <0>;
559 reg = <0x78b9000 0x600 519 reg = <0x78b9000 0x600>;
560 interrupts = <GIC_SPI 520 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
561 clocks = <&gcc GCC_BLS 521 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
562 <&gcc GCC_BLS 522 <&gcc GCC_BLSP1_AHB_CLK>;
563 clock-names = "core", 523 clock-names = "core", "iface";
564 clock-frequency = <400 524 clock-frequency = <400000>;
565 dmas = <&blsp_dma 20>, 525 dmas = <&blsp_dma 20>, <&blsp_dma 21>;
566 dma-names = "tx", "rx" 526 dma-names = "tx", "rx";
567 status = "disabled"; 527 status = "disabled";
568 }; 528 };
569 529
570 blsp1_spi5: spi@78b9000 { <<
571 compatible = "qcom,spi <<
572 #address-cells = <1>; <<
573 #size-cells = <0>; <<
574 reg = <0x78b9000 0x600 <<
575 interrupts = <GIC_SPI <<
576 clocks = <&gcc GCC_BLS <<
577 <&gcc GCC_BLS <<
578 clock-names = "core", <<
579 dmas = <&blsp_dma 20>, <<
580 dma-names = "tx", "rx" <<
581 status = "disabled"; <<
582 }; <<
583 <<
584 blsp1_i2c6: i2c@78ba000 { 530 blsp1_i2c6: i2c@78ba000 {
585 compatible = "qcom,i2c 531 compatible = "qcom,i2c-qup-v2.2.1";
586 #address-cells = <1>; 532 #address-cells = <1>;
587 #size-cells = <0>; 533 #size-cells = <0>;
588 reg = <0x078ba000 0x60 534 reg = <0x078ba000 0x600>;
589 interrupts = <GIC_SPI 535 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
590 clocks = <&gcc GCC_BLS 536 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
591 <&gcc GCC_BLS 537 <&gcc GCC_BLSP1_AHB_CLK>;
592 clock-names = "core", 538 clock-names = "core", "iface";
593 clock-frequency = <100 539 clock-frequency = <100000>;
594 dmas = <&blsp_dma 22>, 540 dmas = <&blsp_dma 22>, <&blsp_dma 23>;
595 dma-names = "tx", "rx" 541 dma-names = "tx", "rx";
596 status = "disabled"; 542 status = "disabled";
597 }; 543 };
598 544
599 qpic_bam: dma-controller@79840 545 qpic_bam: dma-controller@7984000 {
600 compatible = "qcom,bam 546 compatible = "qcom,bam-v1.7.0";
601 reg = <0x07984000 0x1a 547 reg = <0x07984000 0x1a000>;
602 interrupts = <GIC_SPI 548 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
603 clocks = <&gcc GCC_QPI 549 clocks = <&gcc GCC_QPIC_AHB_CLK>;
604 clock-names = "bam_clk 550 clock-names = "bam_clk";
605 #dma-cells = <1>; 551 #dma-cells = <1>;
606 qcom,ee = <0>; 552 qcom,ee = <0>;
607 status = "disabled"; 553 status = "disabled";
608 }; 554 };
609 555
610 qpic_nand: nand-controller@79b 556 qpic_nand: nand-controller@79b0000 {
611 compatible = "qcom,ipq 557 compatible = "qcom,ipq8074-nand";
612 reg = <0x079b0000 0x10 558 reg = <0x079b0000 0x10000>;
613 #address-cells = <1>; 559 #address-cells = <1>;
614 #size-cells = <0>; 560 #size-cells = <0>;
615 clocks = <&gcc GCC_QPI 561 clocks = <&gcc GCC_QPIC_CLK>,
616 <&gcc GCC_QPI 562 <&gcc GCC_QPIC_AHB_CLK>;
617 clock-names = "core", 563 clock-names = "core", "aon";
618 564
619 dmas = <&qpic_bam 0>, 565 dmas = <&qpic_bam 0>,
620 <&qpic_bam 1>, 566 <&qpic_bam 1>,
621 <&qpic_bam 2>; 567 <&qpic_bam 2>;
622 dma-names = "tx", "rx" 568 dma-names = "tx", "rx", "cmd";
623 pinctrl-0 = <&qpic_pin 569 pinctrl-0 = <&qpic_pins>;
624 pinctrl-names = "defau 570 pinctrl-names = "default";
625 status = "disabled"; 571 status = "disabled";
626 }; 572 };
627 573
628 usb_0: usb@8af8800 { 574 usb_0: usb@8af8800 {
629 compatible = "qcom,ipq 575 compatible = "qcom,ipq8074-dwc3", "qcom,dwc3";
630 reg = <0x08af8800 0x40 576 reg = <0x08af8800 0x400>;
631 #address-cells = <1>; 577 #address-cells = <1>;
632 #size-cells = <1>; 578 #size-cells = <1>;
633 ranges; 579 ranges;
634 580
635 clocks = <&gcc GCC_SYS 581 clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
636 <&gcc GCC_USB0 582 <&gcc GCC_USB0_MASTER_CLK>,
637 <&gcc GCC_USB0 583 <&gcc GCC_USB0_SLEEP_CLK>,
638 <&gcc GCC_USB0 584 <&gcc GCC_USB0_MOCK_UTMI_CLK>;
639 clock-names = "cfg_noc 585 clock-names = "cfg_noc",
640 "core", 586 "core",
641 "sleep", 587 "sleep",
642 "mock_utmi"; 588 "mock_utmi";
643 589
644 assigned-clocks = <&gc 590 assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
645 <&gc 591 <&gcc GCC_USB0_MASTER_CLK>,
646 <&gc 592 <&gcc GCC_USB0_MOCK_UTMI_CLK>;
647 assigned-clock-rates = 593 assigned-clock-rates = <133330000>,
648 594 <133330000>,
649 595 <19200000>;
650 596
651 interrupts = <GIC_SPI <<
652 <GIC_SPI <<
653 <GIC_SPI <<
654 interrupt-names = "pwr <<
655 "qus <<
656 "ss_ <<
657 <<
658 power-domains = <&gcc 597 power-domains = <&gcc USB0_GDSC>;
659 598
660 resets = <&gcc GCC_USB 599 resets = <&gcc GCC_USB0_BCR>;
661 status = "disabled"; 600 status = "disabled";
662 601
663 dwc_0: usb@8a00000 { 602 dwc_0: usb@8a00000 {
664 compatible = " 603 compatible = "snps,dwc3";
665 reg = <0x8a000 604 reg = <0x8a00000 0xcd00>;
666 interrupts = < 605 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
667 phys = <&qusb_ !! 606 phys = <&qusb_phy_0>, <&usb0_ssphy>;
668 phy-names = "u 607 phy-names = "usb2-phy", "usb3-phy";
669 snps,parkmode- <<
670 snps,is-utmi-l 608 snps,is-utmi-l1-suspend;
671 snps,hird-thre 609 snps,hird-threshold = /bits/ 8 <0x0>;
672 snps,dis_u2_su 610 snps,dis_u2_susphy_quirk;
673 snps,dis_u3_su 611 snps,dis_u3_susphy_quirk;
674 dr_mode = "hos 612 dr_mode = "host";
675 }; 613 };
676 }; 614 };
677 615
678 usb_1: usb@8cf8800 { 616 usb_1: usb@8cf8800 {
679 compatible = "qcom,ipq 617 compatible = "qcom,ipq8074-dwc3", "qcom,dwc3";
680 reg = <0x08cf8800 0x40 618 reg = <0x08cf8800 0x400>;
681 #address-cells = <1>; 619 #address-cells = <1>;
682 #size-cells = <1>; 620 #size-cells = <1>;
683 ranges; 621 ranges;
684 622
685 clocks = <&gcc GCC_SYS 623 clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>,
686 <&gcc GCC_USB1 624 <&gcc GCC_USB1_MASTER_CLK>,
687 <&gcc GCC_USB1 625 <&gcc GCC_USB1_SLEEP_CLK>,
688 <&gcc GCC_USB1 626 <&gcc GCC_USB1_MOCK_UTMI_CLK>;
689 clock-names = "cfg_noc 627 clock-names = "cfg_noc",
690 "core", 628 "core",
691 "sleep", 629 "sleep",
692 "mock_utmi"; 630 "mock_utmi";
693 631
694 assigned-clocks = <&gc 632 assigned-clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>,
695 <&gc 633 <&gcc GCC_USB1_MASTER_CLK>,
696 <&gc 634 <&gcc GCC_USB1_MOCK_UTMI_CLK>;
697 assigned-clock-rates = 635 assigned-clock-rates = <133330000>,
698 636 <133330000>,
699 637 <19200000>;
700 638
701 interrupts = <GIC_SPI <<
702 <GIC_SPI <<
703 <GIC_SPI <<
704 interrupt-names = "pwr <<
705 "qus <<
706 "ss_ <<
707 <<
708 power-domains = <&gcc 639 power-domains = <&gcc USB1_GDSC>;
709 640
710 resets = <&gcc GCC_USB 641 resets = <&gcc GCC_USB1_BCR>;
711 status = "disabled"; 642 status = "disabled";
712 643
713 dwc_1: usb@8c00000 { 644 dwc_1: usb@8c00000 {
714 compatible = " 645 compatible = "snps,dwc3";
715 reg = <0x8c000 646 reg = <0x8c00000 0xcd00>;
716 interrupts = < 647 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
717 phys = <&qusb_ !! 648 phys = <&qusb_phy_1>, <&usb1_ssphy>;
718 phy-names = "u 649 phy-names = "usb2-phy", "usb3-phy";
719 snps,parkmode- <<
720 snps,is-utmi-l 650 snps,is-utmi-l1-suspend;
721 snps,hird-thre 651 snps,hird-threshold = /bits/ 8 <0x0>;
722 snps,dis_u2_su 652 snps,dis_u2_susphy_quirk;
723 snps,dis_u3_su 653 snps,dis_u3_susphy_quirk;
724 dr_mode = "hos 654 dr_mode = "host";
725 }; 655 };
726 }; 656 };
727 657
728 intc: interrupt-controller@b00 658 intc: interrupt-controller@b000000 {
729 compatible = "qcom,msm 659 compatible = "qcom,msm-qgic2";
730 #address-cells = <1>; 660 #address-cells = <1>;
731 #size-cells = <1>; 661 #size-cells = <1>;
732 interrupt-controller; 662 interrupt-controller;
733 #interrupt-cells = <3> !! 663 #interrupt-cells = <0x3>;
734 reg = <0x0b000000 0x10 664 reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
735 ranges = <0 0xb00a000 665 ranges = <0 0xb00a000 0xffd>;
736 666
737 v2m@0 { 667 v2m@0 {
738 compatible = " 668 compatible = "arm,gic-v2m-frame";
739 msi-controller 669 msi-controller;
740 reg = <0x0 0xf 670 reg = <0x0 0xffd>;
741 }; 671 };
742 }; 672 };
743 673
744 watchdog: watchdog@b017000 { 674 watchdog: watchdog@b017000 {
745 compatible = "qcom,kps 675 compatible = "qcom,kpss-wdt";
746 reg = <0xb017000 0x100 676 reg = <0xb017000 0x1000>;
747 interrupts = <GIC_SPI 677 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
748 clocks = <&sleep_clk>; 678 clocks = <&sleep_clk>;
749 timeout-sec = <30>; 679 timeout-sec = <30>;
750 }; 680 };
751 681
752 apcs_glb: mailbox@b111000 { 682 apcs_glb: mailbox@b111000 {
753 compatible = "qcom,ipq !! 683 compatible = "qcom,ipq8074-apcs-apps-global";
754 "qcom,ipq <<
755 reg = <0x0b111000 0x10 684 reg = <0x0b111000 0x1000>;
756 clocks = <&a53pll>, <& !! 685 clocks = <&a53pll>, <&xo>;
757 clock-names = "pll", " !! 686 clock-names = "pll", "xo";
758 687
759 #clock-cells = <1>; 688 #clock-cells = <1>;
760 #mbox-cells = <1>; 689 #mbox-cells = <1>;
761 }; 690 };
762 691
763 a53pll: clock@b116000 { 692 a53pll: clock@b116000 {
764 compatible = "qcom,ipq 693 compatible = "qcom,ipq8074-a53pll";
765 reg = <0x0b116000 0x40 694 reg = <0x0b116000 0x40>;
766 #clock-cells = <0>; 695 #clock-cells = <0>;
767 clocks = <&xo>; 696 clocks = <&xo>;
768 clock-names = "xo"; 697 clock-names = "xo";
769 }; 698 };
770 699
771 timer@b120000 { 700 timer@b120000 {
772 #address-cells = <1>; 701 #address-cells = <1>;
773 #size-cells = <1>; 702 #size-cells = <1>;
774 ranges; 703 ranges;
775 compatible = "arm,armv 704 compatible = "arm,armv7-timer-mem";
776 reg = <0x0b120000 0x10 705 reg = <0x0b120000 0x1000>;
777 706
778 frame@b120000 { 707 frame@b120000 {
779 frame-number = 708 frame-number = <0>;
780 interrupts = < 709 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
781 < 710 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
782 reg = <0x0b121 711 reg = <0x0b121000 0x1000>,
783 <0x0b122 712 <0x0b122000 0x1000>;
784 }; 713 };
785 714
786 frame@b123000 { 715 frame@b123000 {
787 frame-number = 716 frame-number = <1>;
788 interrupts = < 717 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
789 reg = <0x0b123 718 reg = <0x0b123000 0x1000>;
790 status = "disa 719 status = "disabled";
791 }; 720 };
792 721
793 frame@b124000 { 722 frame@b124000 {
794 frame-number = 723 frame-number = <2>;
795 interrupts = < 724 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
796 reg = <0x0b124 725 reg = <0x0b124000 0x1000>;
797 status = "disa 726 status = "disabled";
798 }; 727 };
799 728
800 frame@b125000 { 729 frame@b125000 {
801 frame-number = 730 frame-number = <3>;
802 interrupts = < 731 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
803 reg = <0x0b125 732 reg = <0x0b125000 0x1000>;
804 status = "disa 733 status = "disabled";
805 }; 734 };
806 735
807 frame@b126000 { 736 frame@b126000 {
808 frame-number = 737 frame-number = <4>;
809 interrupts = < 738 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
810 reg = <0x0b126 739 reg = <0x0b126000 0x1000>;
811 status = "disa 740 status = "disabled";
812 }; 741 };
813 742
814 frame@b127000 { 743 frame@b127000 {
815 frame-number = 744 frame-number = <5>;
816 interrupts = < 745 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
817 reg = <0x0b127 746 reg = <0x0b127000 0x1000>;
818 status = "disa 747 status = "disabled";
819 }; 748 };
820 749
821 frame@b128000 { 750 frame@b128000 {
822 frame-number = 751 frame-number = <6>;
823 interrupts = < 752 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
824 reg = <0x0b128 753 reg = <0x0b128000 0x1000>;
825 status = "disa 754 status = "disabled";
826 }; 755 };
827 }; 756 };
828 757
829 pcie1: pcie@10000000 { !! 758 pcie1: pci@10000000 {
830 compatible = "qcom,pci 759 compatible = "qcom,pcie-ipq8074";
831 reg = <0x10000000 0xf1 !! 760 reg = <0x10000000 0xf1d>,
832 <0x10000f20 0xa8 !! 761 <0x10000f20 0xa8>,
833 <0x00088000 0x20 !! 762 <0x00088000 0x2000>,
834 <0x10100000 0x10 !! 763 <0x10100000 0x1000>;
835 reg-names = "dbi", "el 764 reg-names = "dbi", "elbi", "parf", "config";
836 device_type = "pci"; 765 device_type = "pci";
837 linux,pci-domain = <1> 766 linux,pci-domain = <1>;
838 bus-range = <0x00 0xff 767 bus-range = <0x00 0xff>;
839 num-lanes = <1>; 768 num-lanes = <1>;
840 max-link-speed = <2>; <<
841 #address-cells = <3>; 769 #address-cells = <3>;
842 #size-cells = <2>; 770 #size-cells = <2>;
843 771
844 phys = <&pcie_qmp1>; !! 772 phys = <&pcie_phy1>;
845 phy-names = "pciephy"; 773 phy-names = "pciephy";
846 774
847 ranges = <0x81000000 0 775 ranges = <0x81000000 0x0 0x00000000 0x10200000 0x0 0x10000>, /* I/O */
848 <0x82000000 0 776 <0x82000000 0x0 0x10220000 0x10220000 0x0 0xfde0000>; /* MEM */
849 777
850 interrupts = <GIC_SPI 778 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
851 interrupt-names = "msi 779 interrupt-names = "msi";
852 #interrupt-cells = <1> 780 #interrupt-cells = <1>;
853 interrupt-map-mask = < 781 interrupt-map-mask = <0 0 0 0x7>;
854 interrupt-map = <0 0 0 !! 782 interrupt-map = <0 0 0 1 &intc 0 142
855 IRQ_T 783 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
856 <0 0 0 !! 784 <0 0 0 2 &intc 0 143
857 IRQ_T 785 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
858 <0 0 0 !! 786 <0 0 0 3 &intc 0 144
859 IRQ_T 787 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
860 <0 0 0 !! 788 <0 0 0 4 &intc 0 145
861 IRQ_T 789 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
862 790
863 clocks = <&gcc GCC_SYS 791 clocks = <&gcc GCC_SYS_NOC_PCIE1_AXI_CLK>,
864 <&gcc GCC_PCI 792 <&gcc GCC_PCIE1_AXI_M_CLK>,
865 <&gcc GCC_PCI 793 <&gcc GCC_PCIE1_AXI_S_CLK>,
866 <&gcc GCC_PCI 794 <&gcc GCC_PCIE1_AHB_CLK>,
867 <&gcc GCC_PCI 795 <&gcc GCC_PCIE1_AUX_CLK>;
868 clock-names = "iface", 796 clock-names = "iface",
869 "axi_m", 797 "axi_m",
870 "axi_s", 798 "axi_s",
871 "ahb", 799 "ahb",
872 "aux"; 800 "aux";
873 resets = <&gcc GCC_PCI 801 resets = <&gcc GCC_PCIE1_PIPE_ARES>,
874 <&gcc GCC_PCI 802 <&gcc GCC_PCIE1_SLEEP_ARES>,
875 <&gcc GCC_PCI 803 <&gcc GCC_PCIE1_CORE_STICKY_ARES>,
876 <&gcc GCC_PCI 804 <&gcc GCC_PCIE1_AXI_MASTER_ARES>,
877 <&gcc GCC_PCI 805 <&gcc GCC_PCIE1_AXI_SLAVE_ARES>,
878 <&gcc GCC_PCI 806 <&gcc GCC_PCIE1_AHB_ARES>,
879 <&gcc GCC_PCI 807 <&gcc GCC_PCIE1_AXI_MASTER_STICKY_ARES>;
880 reset-names = "pipe", 808 reset-names = "pipe",
881 "sleep", 809 "sleep",
882 "sticky" 810 "sticky",
883 "axi_m", 811 "axi_m",
884 "axi_s", 812 "axi_s",
885 "ahb", 813 "ahb",
886 "axi_m_s 814 "axi_m_sticky";
887 status = "disabled"; 815 status = "disabled";
888 <<
889 pcie@0 { <<
890 device_type = <<
891 reg = <0x0 0x0 <<
892 bus-range = <0 <<
893 <<
894 #address-cells <<
895 #size-cells = <<
896 ranges; <<
897 }; <<
898 }; 816 };
899 817
900 pcie0: pcie@20000000 { !! 818 pcie0: pci@20000000 {
901 compatible = "qcom,pci 819 compatible = "qcom,pcie-ipq8074-gen3";
902 reg = <0x20000000 0xf1 820 reg = <0x20000000 0xf1d>,
903 <0x20000f20 0xa8 821 <0x20000f20 0xa8>,
904 <0x20001000 0x10 822 <0x20001000 0x1000>,
905 <0x00080000 0x40 823 <0x00080000 0x4000>,
906 <0x20100000 0x10 824 <0x20100000 0x1000>;
907 reg-names = "dbi", "el 825 reg-names = "dbi", "elbi", "atu", "parf", "config";
908 device_type = "pci"; 826 device_type = "pci";
909 linux,pci-domain = <0> 827 linux,pci-domain = <0>;
910 bus-range = <0x00 0xff 828 bus-range = <0x00 0xff>;
911 num-lanes = <1>; 829 num-lanes = <1>;
912 max-link-speed = <3>; 830 max-link-speed = <3>;
913 #address-cells = <3>; 831 #address-cells = <3>;
914 #size-cells = <2>; 832 #size-cells = <2>;
915 833
916 phys = <&pcie_qmp0>; !! 834 phys = <&pcie_phy0>;
917 phy-names = "pciephy"; 835 phy-names = "pciephy";
918 836
919 ranges = <0x81000000 0 837 ranges = <0x81000000 0x0 0x00000000 0x20200000 0x0 0x10000>, /* I/O */
920 <0x82000000 0 838 <0x82000000 0x0 0x20220000 0x20220000 0x0 0xfde0000>; /* MEM */
921 839
922 interrupts = <GIC_SPI 840 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
923 interrupt-names = "msi 841 interrupt-names = "msi";
924 #interrupt-cells = <1> 842 #interrupt-cells = <1>;
925 interrupt-map-mask = < 843 interrupt-map-mask = <0 0 0 0x7>;
926 interrupt-map = <0 0 0 !! 844 interrupt-map = <0 0 0 1 &intc 0 75
927 IRQ_T 845 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
928 <0 0 0 !! 846 <0 0 0 2 &intc 0 78
929 IRQ_T 847 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
930 <0 0 0 !! 848 <0 0 0 3 &intc 0 79
931 IRQ_T 849 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
932 <0 0 0 !! 850 <0 0 0 4 &intc 0 83
933 IRQ_T 851 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
934 852
935 clocks = <&gcc GCC_SYS 853 clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
936 <&gcc GCC_PCI 854 <&gcc GCC_PCIE0_AXI_M_CLK>,
937 <&gcc GCC_PCI 855 <&gcc GCC_PCIE0_AXI_S_CLK>,
938 <&gcc GCC_PCI 856 <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>,
939 <&gcc GCC_PCI 857 <&gcc GCC_PCIE0_RCHNG_CLK>;
940 clock-names = "iface", 858 clock-names = "iface",
941 "axi_m", 859 "axi_m",
942 "axi_s", 860 "axi_s",
943 "axi_bri 861 "axi_bridge",
944 "rchng"; 862 "rchng";
945 863
946 resets = <&gcc GCC_PCI 864 resets = <&gcc GCC_PCIE0_PIPE_ARES>,
947 <&gcc GCC_PCI 865 <&gcc GCC_PCIE0_SLEEP_ARES>,
948 <&gcc GCC_PCI 866 <&gcc GCC_PCIE0_CORE_STICKY_ARES>,
949 <&gcc GCC_PCI 867 <&gcc GCC_PCIE0_AXI_MASTER_ARES>,
950 <&gcc GCC_PCI 868 <&gcc GCC_PCIE0_AXI_SLAVE_ARES>,
951 <&gcc GCC_PCI 869 <&gcc GCC_PCIE0_AHB_ARES>,
952 <&gcc GCC_PCI 870 <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>,
953 <&gcc GCC_PCI 871 <&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>;
954 reset-names = "pipe", 872 reset-names = "pipe",
955 "sleep", 873 "sleep",
956 "sticky" 874 "sticky",
957 "axi_m", 875 "axi_m",
958 "axi_s", 876 "axi_s",
959 "ahb", 877 "ahb",
960 "axi_m_s 878 "axi_m_sticky",
961 "axi_s_s 879 "axi_s_sticky";
962 status = "disabled"; 880 status = "disabled";
963 <<
964 pcie@0 { <<
965 device_type = <<
966 reg = <0x0 0x0 <<
967 bus-range = <0 <<
968 <<
969 #address-cells <<
970 #size-cells = <<
971 ranges; <<
972 }; <<
973 }; 881 };
974 }; 882 };
975 883
976 timer { 884 timer {
977 compatible = "arm,armv8-timer" 885 compatible = "arm,armv8-timer";
978 interrupts = <GIC_PPI 2 (GIC_C 886 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
979 <GIC_PPI 3 (GIC_C 887 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
980 <GIC_PPI 4 (GIC_C 888 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
981 <GIC_PPI 1 (GIC_C 889 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
982 }; 890 };
983 891
984 thermal-zones { 892 thermal-zones {
985 nss-top-thermal { 893 nss-top-thermal {
986 polling-delay-passive 894 polling-delay-passive = <250>;
>> 895 polling-delay = <1000>;
987 896
988 thermal-sensors = <&ts 897 thermal-sensors = <&tsens 4>;
989 <<
990 trips { <<
991 nss-top-crit { <<
992 temper <<
993 hyster <<
994 type = <<
995 }; <<
996 }; <<
997 }; 898 };
998 899
999 nss0-thermal { 900 nss0-thermal {
1000 polling-delay-passive 901 polling-delay-passive = <250>;
>> 902 polling-delay = <1000>;
1001 903
1002 thermal-sensors = <&t 904 thermal-sensors = <&tsens 5>;
1003 <<
1004 trips { <<
1005 nss-0-crit { <<
1006 tempe <<
1007 hyste <<
1008 type <<
1009 }; <<
1010 }; <<
1011 }; 905 };
1012 906
1013 nss1-thermal { 907 nss1-thermal {
1014 polling-delay-passive 908 polling-delay-passive = <250>;
>> 909 polling-delay = <1000>;
1015 910
1016 thermal-sensors = <&t 911 thermal-sensors = <&tsens 6>;
1017 <<
1018 trips { <<
1019 nss-1-crit { <<
1020 tempe <<
1021 hyste <<
1022 type <<
1023 }; <<
1024 }; <<
1025 }; 912 };
1026 913
1027 wcss-phya0-thermal { 914 wcss-phya0-thermal {
1028 polling-delay-passive 915 polling-delay-passive = <250>;
>> 916 polling-delay = <1000>;
1029 917
1030 thermal-sensors = <&t 918 thermal-sensors = <&tsens 7>;
1031 <<
1032 trips { <<
1033 wcss-phya0-cr <<
1034 tempe <<
1035 hyste <<
1036 type <<
1037 }; <<
1038 }; <<
1039 }; 919 };
1040 920
1041 wcss-phya1-thermal { 921 wcss-phya1-thermal {
1042 polling-delay-passive 922 polling-delay-passive = <250>;
>> 923 polling-delay = <1000>;
1043 924
1044 thermal-sensors = <&t 925 thermal-sensors = <&tsens 8>;
1045 <<
1046 trips { <<
1047 wcss-phya1-cr <<
1048 tempe <<
1049 hyste <<
1050 type <<
1051 }; <<
1052 }; <<
1053 }; 926 };
1054 927
1055 cpu0_thermal: cpu0-thermal { 928 cpu0_thermal: cpu0-thermal {
1056 polling-delay-passive 929 polling-delay-passive = <250>;
>> 930 polling-delay = <1000>;
1057 931
1058 thermal-sensors = <&t 932 thermal-sensors = <&tsens 9>;
1059 <<
1060 trips { <<
1061 cpu0-crit { <<
1062 tempe <<
1063 hyste <<
1064 type <<
1065 }; <<
1066 }; <<
1067 }; 933 };
1068 934
1069 cpu1_thermal: cpu1-thermal { 935 cpu1_thermal: cpu1-thermal {
1070 polling-delay-passive 936 polling-delay-passive = <250>;
>> 937 polling-delay = <1000>;
1071 938
1072 thermal-sensors = <&t 939 thermal-sensors = <&tsens 10>;
1073 <<
1074 trips { <<
1075 cpu1-crit { <<
1076 tempe <<
1077 hyste <<
1078 type <<
1079 }; <<
1080 }; <<
1081 }; 940 };
1082 941
1083 cpu2_thermal: cpu2-thermal { 942 cpu2_thermal: cpu2-thermal {
1084 polling-delay-passive 943 polling-delay-passive = <250>;
>> 944 polling-delay = <1000>;
1085 945
1086 thermal-sensors = <&t 946 thermal-sensors = <&tsens 11>;
1087 <<
1088 trips { <<
1089 cpu2-crit { <<
1090 tempe <<
1091 hyste <<
1092 type <<
1093 }; <<
1094 }; <<
1095 }; 947 };
1096 948
1097 cpu3_thermal: cpu3-thermal { 949 cpu3_thermal: cpu3-thermal {
1098 polling-delay-passive 950 polling-delay-passive = <250>;
>> 951 polling-delay = <1000>;
1099 952
1100 thermal-sensors = <&t 953 thermal-sensors = <&tsens 12>;
1101 <<
1102 trips { <<
1103 cpu3-crit { <<
1104 tempe <<
1105 hyste <<
1106 type <<
1107 }; <<
1108 }; <<
1109 }; 954 };
1110 955
1111 cluster_thermal: cluster-ther 956 cluster_thermal: cluster-thermal {
1112 polling-delay-passive 957 polling-delay-passive = <250>;
>> 958 polling-delay = <1000>;
1113 959
1114 thermal-sensors = <&t 960 thermal-sensors = <&tsens 13>;
1115 <<
1116 trips { <<
1117 cluster-crit <<
1118 tempe <<
1119 hyste <<
1120 type <<
1121 }; <<
1122 }; <<
1123 }; 961 };
1124 962
1125 wcss-phyb0-thermal { 963 wcss-phyb0-thermal {
1126 polling-delay-passive 964 polling-delay-passive = <250>;
>> 965 polling-delay = <1000>;
1127 966
1128 thermal-sensors = <&t 967 thermal-sensors = <&tsens 14>;
1129 <<
1130 trips { <<
1131 wcss-phyb0-cr <<
1132 tempe <<
1133 hyste <<
1134 type <<
1135 }; <<
1136 }; <<
1137 }; 968 };
1138 969
1139 wcss-phyb1-thermal { 970 wcss-phyb1-thermal {
1140 polling-delay-passive 971 polling-delay-passive = <250>;
>> 972 polling-delay = <1000>;
1141 973
1142 thermal-sensors = <&t 974 thermal-sensors = <&tsens 15>;
1143 <<
1144 trips { <<
1145 wcss-phyb1-cr <<
1146 tempe <<
1147 hyste <<
1148 type <<
1149 }; <<
1150 }; <<
1151 }; 975 };
1152 }; 976 };
1153 }; 977 };
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