1 // SPDX-License-Identifier: GPL-2.0-only 1 // SPDX-License-Identifier: GPL-2.0-only
2 /* 2 /*
3 * Copyright (c) 2017, The Linux Foundation. A 3 * Copyright (c) 2017, The Linux Foundation. All rights reserved.
4 */ 4 */
5 5
6 #include <dt-bindings/interrupt-controller/arm 6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,gcc-ipq8074.h 7 #include <dt-bindings/clock/qcom,gcc-ipq8074.h>
8 8
9 / { 9 / {
10 #address-cells = <2>; 10 #address-cells = <2>;
11 #size-cells = <2>; 11 #size-cells = <2>;
12 12
13 model = "Qualcomm Technologies, Inc. I 13 model = "Qualcomm Technologies, Inc. IPQ8074";
14 compatible = "qcom,ipq8074"; 14 compatible = "qcom,ipq8074";
15 interrupt-parent = <&intc>; 15 interrupt-parent = <&intc>;
16 16
17 clocks { 17 clocks {
18 sleep_clk: sleep_clk { 18 sleep_clk: sleep_clk {
19 compatible = "fixed-cl 19 compatible = "fixed-clock";
20 clock-frequency = <327 20 clock-frequency = <32768>;
21 #clock-cells = <0>; 21 #clock-cells = <0>;
22 }; 22 };
23 23
24 xo: xo { 24 xo: xo {
25 compatible = "fixed-cl 25 compatible = "fixed-clock";
26 clock-frequency = <192 26 clock-frequency = <19200000>;
27 #clock-cells = <0>; 27 #clock-cells = <0>;
28 }; 28 };
29 }; 29 };
30 30
31 cpus { 31 cpus {
32 #address-cells = <1>; 32 #address-cells = <1>;
33 #size-cells = <0>; 33 #size-cells = <0>;
34 34
35 CPU0: cpu@0 { 35 CPU0: cpu@0 {
36 device_type = "cpu"; 36 device_type = "cpu";
37 compatible = "arm,cort 37 compatible = "arm,cortex-a53";
38 reg = <0x0>; 38 reg = <0x0>;
39 next-level-cache = <&L 39 next-level-cache = <&L2_0>;
40 enable-method = "psci" 40 enable-method = "psci";
41 }; 41 };
42 42
43 CPU1: cpu@1 { 43 CPU1: cpu@1 {
44 device_type = "cpu"; 44 device_type = "cpu";
45 compatible = "arm,cort 45 compatible = "arm,cortex-a53";
46 enable-method = "psci" 46 enable-method = "psci";
47 reg = <0x1>; 47 reg = <0x1>;
48 next-level-cache = <&L 48 next-level-cache = <&L2_0>;
49 }; 49 };
50 50
51 CPU2: cpu@2 { 51 CPU2: cpu@2 {
52 device_type = "cpu"; 52 device_type = "cpu";
53 compatible = "arm,cort 53 compatible = "arm,cortex-a53";
54 enable-method = "psci" 54 enable-method = "psci";
55 reg = <0x2>; 55 reg = <0x2>;
56 next-level-cache = <&L 56 next-level-cache = <&L2_0>;
57 }; 57 };
58 58
59 CPU3: cpu@3 { 59 CPU3: cpu@3 {
60 device_type = "cpu"; 60 device_type = "cpu";
61 compatible = "arm,cort 61 compatible = "arm,cortex-a53";
62 enable-method = "psci" 62 enable-method = "psci";
63 reg = <0x3>; 63 reg = <0x3>;
64 next-level-cache = <&L 64 next-level-cache = <&L2_0>;
65 }; 65 };
66 66
67 L2_0: l2-cache { 67 L2_0: l2-cache {
68 compatible = "cache"; 68 compatible = "cache";
69 cache-level = <2>; 69 cache-level = <2>;
70 cache-unified; 70 cache-unified;
71 }; 71 };
72 }; 72 };
73 73
74 pmu { 74 pmu {
75 compatible = "arm,cortex-a53-p 75 compatible = "arm,cortex-a53-pmu";
76 interrupts = <GIC_PPI 7 (GIC_C 76 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
77 }; 77 };
78 78
79 psci { 79 psci {
80 compatible = "arm,psci-1.0"; 80 compatible = "arm,psci-1.0";
81 method = "smc"; 81 method = "smc";
82 }; 82 };
83 83
84 reserved-memory { 84 reserved-memory {
85 #address-cells = <2>; 85 #address-cells = <2>;
86 #size-cells = <2>; 86 #size-cells = <2>;
87 ranges; 87 ranges;
88 88
89 bootloader@4a600000 { 89 bootloader@4a600000 {
90 reg = <0x0 0x4a600000 90 reg = <0x0 0x4a600000 0x0 0x400000>;
91 no-map; 91 no-map;
92 }; 92 };
93 93
94 sbl@4aa00000 { 94 sbl@4aa00000 {
95 reg = <0x0 0x4aa00000 95 reg = <0x0 0x4aa00000 0x0 0x100000>;
96 no-map; 96 no-map;
97 }; 97 };
98 98
99 smem@4ab00000 { 99 smem@4ab00000 {
100 compatible = "qcom,sme 100 compatible = "qcom,smem";
101 reg = <0x0 0x4ab00000 101 reg = <0x0 0x4ab00000 0x0 0x100000>;
102 no-map; 102 no-map;
103 103
104 hwlocks = <&tcsr_mutex 104 hwlocks = <&tcsr_mutex 3>;
105 }; 105 };
106 106
107 memory@4ac00000 { 107 memory@4ac00000 {
108 reg = <0x0 0x4ac00000 108 reg = <0x0 0x4ac00000 0x0 0x400000>;
109 no-map; 109 no-map;
110 }; 110 };
111 }; 111 };
112 112
113 firmware { 113 firmware {
114 scm { 114 scm {
115 compatible = "qcom,scm 115 compatible = "qcom,scm-ipq8074", "qcom,scm";
116 qcom,dload-mode = <&tc 116 qcom,dload-mode = <&tcsr 0x6100>;
117 }; 117 };
118 }; 118 };
119 119
120 soc: soc@0 { 120 soc: soc@0 {
121 #address-cells = <1>; 121 #address-cells = <1>;
122 #size-cells = <1>; 122 #size-cells = <1>;
123 ranges = <0 0 0 0xffffffff>; 123 ranges = <0 0 0 0xffffffff>;
124 compatible = "simple-bus"; 124 compatible = "simple-bus";
125 125
126 ssphy_1: phy@58000 { 126 ssphy_1: phy@58000 {
127 compatible = "qcom,ipq 127 compatible = "qcom,ipq8074-qmp-usb3-phy";
128 reg = <0x00058000 0x10 !! 128 reg = <0x00058000 0x1c4>;
>> 129 #address-cells = <1>;
>> 130 #size-cells = <1>;
>> 131 ranges;
129 132
130 clocks = <&gcc GCC_USB 133 clocks = <&gcc GCC_USB1_AUX_CLK>,
131 <&xo>, !! 134 <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
132 <&gcc GCC_USB !! 135 <&xo>;
133 <&gcc GCC_USB !! 136 clock-names = "aux", "cfg_ahb", "ref";
134 clock-names = "aux", <<
135 "ref", <<
136 "cfg_ahb <<
137 "pipe"; <<
138 clock-output-names = " <<
139 #clock-cells = <0>; <<
140 #phy-cells = <0>; <<
141 137
142 resets = <&gcc GCC_USB 138 resets = <&gcc GCC_USB1_PHY_BCR>,
143 <&gcc GCC_USB !! 139 <&gcc GCC_USB3PHY_1_PHY_BCR>;
144 reset-names = "phy", !! 140 reset-names = "phy","common";
145 "phy_phy <<
146 <<
147 status = "disabled"; 141 status = "disabled";
>> 142
>> 143 usb1_ssphy: phy@58200 {
>> 144 reg = <0x00058200 0x130>, /* Tx */
>> 145 <0x00058400 0x200>, /* Rx */
>> 146 <0x00058800 0x1f8>, /* PCS */
>> 147 <0x00058600 0x044>; /* PCS misc */
>> 148 #phy-cells = <0>;
>> 149 #clock-cells = <0>;
>> 150 clocks = <&gcc GCC_USB1_PIPE_CLK>;
>> 151 clock-names = "pipe0";
>> 152 clock-output-names = "usb3phy_1_cc_pipe_clk";
>> 153 };
148 }; 154 };
149 155
150 qusb_phy_1: phy@59000 { 156 qusb_phy_1: phy@59000 {
151 compatible = "qcom,ipq 157 compatible = "qcom,ipq8074-qusb2-phy";
152 reg = <0x00059000 0x18 158 reg = <0x00059000 0x180>;
153 #phy-cells = <0>; 159 #phy-cells = <0>;
154 160
155 clocks = <&gcc GCC_USB 161 clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
156 <&xo>; 162 <&xo>;
157 clock-names = "cfg_ahb 163 clock-names = "cfg_ahb", "ref";
158 164
159 resets = <&gcc GCC_QUS 165 resets = <&gcc GCC_QUSB2_1_PHY_BCR>;
160 status = "disabled"; 166 status = "disabled";
161 }; 167 };
162 168
163 ssphy_0: phy@78000 { 169 ssphy_0: phy@78000 {
164 compatible = "qcom,ipq 170 compatible = "qcom,ipq8074-qmp-usb3-phy";
165 reg = <0x00078000 0x10 !! 171 reg = <0x00078000 0x1c4>;
>> 172 #address-cells = <1>;
>> 173 #size-cells = <1>;
>> 174 ranges;
166 175
167 clocks = <&gcc GCC_USB 176 clocks = <&gcc GCC_USB0_AUX_CLK>,
168 <&xo>, !! 177 <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
169 <&gcc GCC_USB !! 178 <&xo>;
170 <&gcc GCC_USB !! 179 clock-names = "aux", "cfg_ahb", "ref";
171 clock-names = "aux", <<
172 "ref", <<
173 "cfg_ahb <<
174 "pipe"; <<
175 clock-output-names = " <<
176 #clock-cells = <0>; <<
177 #phy-cells = <0>; <<
178 180
179 resets = <&gcc GCC_USB 181 resets = <&gcc GCC_USB0_PHY_BCR>,
180 <&gcc GCC_USB !! 182 <&gcc GCC_USB3PHY_0_PHY_BCR>;
181 reset-names = "phy", !! 183 reset-names = "phy","common";
182 "phy_phy <<
183 <<
184 status = "disabled"; 184 status = "disabled";
>> 185
>> 186 usb0_ssphy: phy@78200 {
>> 187 reg = <0x00078200 0x130>, /* Tx */
>> 188 <0x00078400 0x200>, /* Rx */
>> 189 <0x00078800 0x1f8>, /* PCS */
>> 190 <0x00078600 0x044>; /* PCS misc */
>> 191 #phy-cells = <0>;
>> 192 #clock-cells = <0>;
>> 193 clocks = <&gcc GCC_USB0_PIPE_CLK>;
>> 194 clock-names = "pipe0";
>> 195 clock-output-names = "usb3phy_0_cc_pipe_clk";
>> 196 };
185 }; 197 };
186 198
187 qusb_phy_0: phy@79000 { 199 qusb_phy_0: phy@79000 {
188 compatible = "qcom,ipq 200 compatible = "qcom,ipq8074-qusb2-phy";
189 reg = <0x00079000 0x18 201 reg = <0x00079000 0x180>;
190 #phy-cells = <0>; 202 #phy-cells = <0>;
191 203
192 clocks = <&gcc GCC_USB 204 clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
193 <&xo>; 205 <&xo>;
194 clock-names = "cfg_ahb 206 clock-names = "cfg_ahb", "ref";
195 207
196 resets = <&gcc GCC_QUS 208 resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
197 status = "disabled"; 209 status = "disabled";
198 }; 210 };
199 211
200 pcie_qmp0: phy@84000 { 212 pcie_qmp0: phy@84000 {
201 compatible = "qcom,ipq 213 compatible = "qcom,ipq8074-qmp-gen3-pcie-phy";
202 reg = <0x00084000 0x10 !! 214 reg = <0x00084000 0x1bc>;
>> 215 #address-cells = <1>;
>> 216 #size-cells = <1>;
>> 217 ranges;
203 218
204 clocks = <&gcc GCC_PCI 219 clocks = <&gcc GCC_PCIE0_AUX_CLK>,
205 <&gcc GCC_PCI !! 220 <&gcc GCC_PCIE0_AHB_CLK>;
206 <&gcc GCC_PCI !! 221 clock-names = "aux", "cfg_ahb";
207 clock-names = "aux", <<
208 "cfg_ahb <<
209 "pipe"; <<
210 <<
211 clock-output-names = " <<
212 #clock-cells = <0>; <<
213 <<
214 #phy-cells = <0>; <<
215 <<
216 resets = <&gcc GCC_PCI 222 resets = <&gcc GCC_PCIE0_PHY_BCR>,
217 <&gcc GCC_PCI !! 223 <&gcc GCC_PCIE0PHY_PHY_BCR>;
218 reset-names = "phy", 224 reset-names = "phy",
219 "common" 225 "common";
220 status = "disabled"; 226 status = "disabled";
>> 227
>> 228 pcie_phy0: phy@84200 {
>> 229 reg = <0x84200 0x16c>,
>> 230 <0x84400 0x200>,
>> 231 <0x84800 0x1f0>,
>> 232 <0x84c00 0xf4>;
>> 233 #phy-cells = <0>;
>> 234 #clock-cells = <0>;
>> 235 clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
>> 236 clock-names = "pipe0";
>> 237 clock-output-names = "pcie20_phy0_pipe_clk";
>> 238 };
221 }; 239 };
222 240
223 pcie_qmp1: phy@8e000 { 241 pcie_qmp1: phy@8e000 {
224 compatible = "qcom,ipq 242 compatible = "qcom,ipq8074-qmp-pcie-phy";
225 reg = <0x0008e000 0x10 !! 243 reg = <0x0008e000 0x1c4>;
>> 244 #address-cells = <1>;
>> 245 #size-cells = <1>;
>> 246 ranges;
226 247
227 clocks = <&gcc GCC_PCI 248 clocks = <&gcc GCC_PCIE1_AUX_CLK>,
228 <&gcc GCC_PCI !! 249 <&gcc GCC_PCIE1_AHB_CLK>;
229 <&gcc GCC_PCI !! 250 clock-names = "aux", "cfg_ahb";
230 clock-names = "aux", <<
231 "cfg_ahb <<
232 "pipe"; <<
233 <<
234 clock-output-names = " <<
235 #clock-cells = <0>; <<
236 <<
237 #phy-cells = <0>; <<
238 <<
239 resets = <&gcc GCC_PCI 251 resets = <&gcc GCC_PCIE1_PHY_BCR>,
240 <&gcc GCC_PCI !! 252 <&gcc GCC_PCIE1PHY_PHY_BCR>;
241 reset-names = "phy", 253 reset-names = "phy",
242 "common" 254 "common";
243 status = "disabled"; 255 status = "disabled";
>> 256
>> 257 pcie_phy1: phy@8e200 {
>> 258 reg = <0x8e200 0x130>,
>> 259 <0x8e400 0x200>,
>> 260 <0x8e800 0x1f8>;
>> 261 #phy-cells = <0>;
>> 262 #clock-cells = <0>;
>> 263 clocks = <&gcc GCC_PCIE1_PIPE_CLK>;
>> 264 clock-names = "pipe0";
>> 265 clock-output-names = "pcie20_phy1_pipe_clk";
>> 266 };
244 }; 267 };
245 268
246 mdio: mdio@90000 { 269 mdio: mdio@90000 {
247 compatible = "qcom,ipq 270 compatible = "qcom,ipq8074-mdio", "qcom,ipq4019-mdio";
248 reg = <0x00090000 0x64 271 reg = <0x00090000 0x64>;
249 #address-cells = <1>; 272 #address-cells = <1>;
250 #size-cells = <0>; 273 #size-cells = <0>;
251 274
252 clocks = <&gcc GCC_MDI 275 clocks = <&gcc GCC_MDIO_AHB_CLK>;
253 clock-names = "gcc_mdi 276 clock-names = "gcc_mdio_ahb_clk";
254 277
255 clock-frequency = <625 <<
256 <<
257 status = "disabled"; 278 status = "disabled";
258 }; 279 };
259 280
260 qfprom: efuse@a4000 { 281 qfprom: efuse@a4000 {
261 compatible = "qcom,ipq 282 compatible = "qcom,ipq8074-qfprom", "qcom,qfprom";
262 reg = <0x000a4000 0x20 283 reg = <0x000a4000 0x2000>;
263 #address-cells = <1>; 284 #address-cells = <1>;
264 #size-cells = <1>; 285 #size-cells = <1>;
265 }; 286 };
266 287
267 prng: rng@e3000 { 288 prng: rng@e3000 {
268 compatible = "qcom,prn 289 compatible = "qcom,prng-ee";
269 reg = <0x000e3000 0x10 290 reg = <0x000e3000 0x1000>;
270 clocks = <&gcc GCC_PRN 291 clocks = <&gcc GCC_PRNG_AHB_CLK>;
271 clock-names = "core"; 292 clock-names = "core";
272 status = "disabled"; 293 status = "disabled";
273 }; 294 };
274 295
275 tsens: thermal-sensor@4a9000 { 296 tsens: thermal-sensor@4a9000 {
276 compatible = "qcom,ipq 297 compatible = "qcom,ipq8074-tsens";
277 reg = <0x4a9000 0x1000 298 reg = <0x4a9000 0x1000>, /* TM */
278 <0x4a8000 0x1000 299 <0x4a8000 0x1000>; /* SROT */
279 interrupts = <GIC_SPI 300 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
280 interrupt-names = "com 301 interrupt-names = "combined";
281 #qcom,sensors = <16>; 302 #qcom,sensors = <16>;
282 #thermal-sensor-cells 303 #thermal-sensor-cells = <1>;
283 }; 304 };
284 305
285 cryptobam: dma-controller@7040 306 cryptobam: dma-controller@704000 {
286 compatible = "qcom,bam 307 compatible = "qcom,bam-v1.7.0";
287 reg = <0x00704000 0x20 308 reg = <0x00704000 0x20000>;
288 interrupts = <GIC_SPI 309 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
289 clocks = <&gcc GCC_CRY 310 clocks = <&gcc GCC_CRYPTO_AHB_CLK>;
290 clock-names = "bam_clk 311 clock-names = "bam_clk";
291 #dma-cells = <1>; 312 #dma-cells = <1>;
292 qcom,ee = <1>; 313 qcom,ee = <1>;
293 qcom,controlled-remote 314 qcom,controlled-remotely;
294 status = "disabled"; 315 status = "disabled";
295 }; 316 };
296 317
297 crypto: crypto@73a000 { 318 crypto: crypto@73a000 {
298 compatible = "qcom,cry 319 compatible = "qcom,crypto-v5.1";
299 reg = <0x0073a000 0x60 320 reg = <0x0073a000 0x6000>;
300 clocks = <&gcc GCC_CRY 321 clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
301 <&gcc GCC_CRY 322 <&gcc GCC_CRYPTO_AXI_CLK>,
302 <&gcc GCC_CRY 323 <&gcc GCC_CRYPTO_CLK>;
303 clock-names = "iface", 324 clock-names = "iface", "bus", "core";
304 dmas = <&cryptobam 2>, 325 dmas = <&cryptobam 2>, <&cryptobam 3>;
305 dma-names = "rx", "tx" 326 dma-names = "rx", "tx";
306 status = "disabled"; 327 status = "disabled";
307 }; 328 };
308 329
309 tlmm: pinctrl@1000000 { 330 tlmm: pinctrl@1000000 {
310 compatible = "qcom,ipq 331 compatible = "qcom,ipq8074-pinctrl";
311 reg = <0x01000000 0x30 332 reg = <0x01000000 0x300000>;
312 interrupts = <GIC_SPI 333 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
313 gpio-controller; 334 gpio-controller;
314 gpio-ranges = <&tlmm 0 335 gpio-ranges = <&tlmm 0 0 70>;
315 #gpio-cells = <2>; 336 #gpio-cells = <2>;
316 interrupt-controller; 337 interrupt-controller;
317 #interrupt-cells = <2> 338 #interrupt-cells = <2>;
318 339
319 serial_4_pins: serial4 340 serial_4_pins: serial4-state {
320 pins = "gpio23 341 pins = "gpio23", "gpio24";
321 function = "bl 342 function = "blsp4_uart1";
322 drive-strength 343 drive-strength = <8>;
323 bias-disable; 344 bias-disable;
324 }; 345 };
325 346
326 serial_5_pins: serial5 <<
327 pins = "gpio9" <<
328 function = "bl <<
329 drive-strength <<
330 bias-disable; <<
331 }; <<
332 <<
333 i2c_0_pins: i2c-0-stat 347 i2c_0_pins: i2c-0-state {
334 pins = "gpio42 348 pins = "gpio42", "gpio43";
335 function = "bl 349 function = "blsp1_i2c";
336 drive-strength 350 drive-strength = <8>;
337 bias-disable; 351 bias-disable;
338 }; 352 };
339 353
340 spi_0_pins: spi-0-stat 354 spi_0_pins: spi-0-state {
341 pins = "gpio38 355 pins = "gpio38", "gpio39", "gpio40", "gpio41";
342 function = "bl 356 function = "blsp0_spi";
343 drive-strength 357 drive-strength = <8>;
344 bias-disable; 358 bias-disable;
345 }; 359 };
346 360
347 hsuart_pins: hsuart-st 361 hsuart_pins: hsuart-state {
348 pins = "gpio46 362 pins = "gpio46", "gpio47", "gpio48", "gpio49";
349 function = "bl 363 function = "blsp2_uart";
350 drive-strength 364 drive-strength = <8>;
351 bias-disable; 365 bias-disable;
352 }; 366 };
353 367
354 qpic_pins: qpic-state 368 qpic_pins: qpic-state {
355 pins = "gpio1" 369 pins = "gpio1", "gpio3", "gpio4",
356 "gpio5" 370 "gpio5", "gpio6", "gpio7",
357 "gpio8" 371 "gpio8", "gpio10", "gpio11",
358 "gpio12 372 "gpio12", "gpio13", "gpio14",
359 "gpio15 !! 373 "gpio15", "gpio16", "gpio17";
360 function = "qp 374 function = "qpic";
361 drive-strength 375 drive-strength = <8>;
362 bias-disable; 376 bias-disable;
363 }; 377 };
364 }; 378 };
365 379
366 gcc: clock-controller@1800000 !! 380 gcc: gcc@1800000 {
367 compatible = "qcom,gcc 381 compatible = "qcom,gcc-ipq8074";
368 reg = <0x01800000 0x80 382 reg = <0x01800000 0x80000>;
369 clocks = <&xo>, !! 383 clocks = <&xo>, <&sleep_clk>;
370 <&sleep_clk>, !! 384 clock-names = "xo", "sleep_clk";
371 <&pcie_qmp0>, <<
372 <&pcie_qmp1>; <<
373 clock-names = "xo", <<
374 "sleep_c <<
375 "pcie0_p <<
376 "pcie1_p <<
377 #clock-cells = <1>; 385 #clock-cells = <1>;
378 #power-domain-cells = 386 #power-domain-cells = <1>;
379 #reset-cells = <1>; 387 #reset-cells = <1>;
380 }; 388 };
381 389
382 tcsr_mutex: hwlock@1905000 { 390 tcsr_mutex: hwlock@1905000 {
383 compatible = "qcom,tcs 391 compatible = "qcom,tcsr-mutex";
384 reg = <0x01905000 0x20 392 reg = <0x01905000 0x20000>;
385 #hwlock-cells = <1>; 393 #hwlock-cells = <1>;
386 }; 394 };
387 395
388 tcsr: syscon@1937000 { 396 tcsr: syscon@1937000 {
389 compatible = "qcom,tcs 397 compatible = "qcom,tcsr-ipq8074", "syscon";
390 reg = <0x01937000 0x21 398 reg = <0x01937000 0x21000>;
391 }; 399 };
392 400
393 spmi_bus: spmi@200f000 { 401 spmi_bus: spmi@200f000 {
394 compatible = "qcom,spm 402 compatible = "qcom,spmi-pmic-arb";
395 reg = <0x0200f000 0x00 403 reg = <0x0200f000 0x001000>,
396 <0x02400000 0x80 404 <0x02400000 0x800000>,
397 <0x02c00000 0x80 405 <0x02c00000 0x800000>,
398 <0x03800000 0x20 406 <0x03800000 0x200000>,
399 <0x0200a000 0x00 407 <0x0200a000 0x000700>;
400 reg-names = "core", "c 408 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
401 interrupts = <GIC_SPI 409 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
402 interrupt-names = "per 410 interrupt-names = "periph_irq";
403 qcom,ee = <0>; 411 qcom,ee = <0>;
404 qcom,channel = <0>; 412 qcom,channel = <0>;
405 #address-cells = <2>; 413 #address-cells = <2>;
406 #size-cells = <0>; 414 #size-cells = <0>;
407 interrupt-controller; 415 interrupt-controller;
408 #interrupt-cells = <4> 416 #interrupt-cells = <4>;
409 }; 417 };
410 418
411 sdhc_1: mmc@7824900 { 419 sdhc_1: mmc@7824900 {
412 compatible = "qcom,ipq !! 420 compatible = "qcom,sdhci-msm-v4";
413 reg = <0x7824900 0x500 421 reg = <0x7824900 0x500>, <0x7824000 0x800>;
414 reg-names = "hc", "cor 422 reg-names = "hc", "core";
415 423
416 interrupts = <GIC_SPI 424 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
417 <GIC_SPI 425 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
418 interrupt-names = "hc_ 426 interrupt-names = "hc_irq", "pwr_irq";
419 427
420 clocks = <&gcc GCC_SDC 428 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
421 <&gcc GCC_SDC 429 <&gcc GCC_SDCC1_APPS_CLK>,
422 <&xo>; 430 <&xo>;
423 clock-names = "iface", 431 clock-names = "iface", "core", "xo";
424 resets = <&gcc GCC_SDC 432 resets = <&gcc GCC_SDCC1_BCR>;
425 max-frequency = <38400 433 max-frequency = <384000000>;
426 mmc-ddr-1_8v; 434 mmc-ddr-1_8v;
427 mmc-hs200-1_8v; 435 mmc-hs200-1_8v;
428 mmc-hs400-1_8v; 436 mmc-hs400-1_8v;
429 bus-width = <8>; 437 bus-width = <8>;
430 438
431 status = "disabled"; 439 status = "disabled";
432 }; 440 };
433 441
434 blsp_dma: dma-controller@78840 442 blsp_dma: dma-controller@7884000 {
435 compatible = "qcom,bam 443 compatible = "qcom,bam-v1.7.0";
436 reg = <0x07884000 0x2b 444 reg = <0x07884000 0x2b000>;
437 interrupts = <GIC_SPI 445 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
438 clocks = <&gcc GCC_BLS 446 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
439 clock-names = "bam_clk 447 clock-names = "bam_clk";
440 #dma-cells = <1>; 448 #dma-cells = <1>;
441 qcom,ee = <0>; 449 qcom,ee = <0>;
442 }; 450 };
443 451
444 blsp1_uart1: serial@78af000 { 452 blsp1_uart1: serial@78af000 {
445 compatible = "qcom,msm 453 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
446 reg = <0x078af000 0x20 454 reg = <0x078af000 0x200>;
447 interrupts = <GIC_SPI 455 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
448 clocks = <&gcc GCC_BLS 456 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
449 <&gcc GCC_BLS 457 <&gcc GCC_BLSP1_AHB_CLK>;
450 clock-names = "core", 458 clock-names = "core", "iface";
451 status = "disabled"; 459 status = "disabled";
452 }; 460 };
453 461
454 blsp1_uart3: serial@78b1000 { 462 blsp1_uart3: serial@78b1000 {
455 compatible = "qcom,msm 463 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
456 reg = <0x078b1000 0x20 464 reg = <0x078b1000 0x200>;
457 interrupts = <GIC_SPI 465 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
458 clocks = <&gcc GCC_BLS 466 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
459 <&gcc GCC_BLSP 467 <&gcc GCC_BLSP1_AHB_CLK>;
460 clock-names = "core", 468 clock-names = "core", "iface";
461 dmas = <&blsp_dma 4>, 469 dmas = <&blsp_dma 4>,
462 <&blsp_dma 5>; 470 <&blsp_dma 5>;
463 dma-names = "tx", "rx" 471 dma-names = "tx", "rx";
464 pinctrl-0 = <&hsuart_p 472 pinctrl-0 = <&hsuart_pins>;
465 pinctrl-names = "defau 473 pinctrl-names = "default";
466 status = "disabled"; 474 status = "disabled";
467 }; 475 };
468 476
469 blsp1_uart5: serial@78b3000 { 477 blsp1_uart5: serial@78b3000 {
470 compatible = "qcom,msm 478 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
471 reg = <0x078b3000 0x20 479 reg = <0x078b3000 0x200>;
472 interrupts = <GIC_SPI 480 interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
473 clocks = <&gcc GCC_BLS 481 clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>,
474 <&gcc GCC_BLS 482 <&gcc GCC_BLSP1_AHB_CLK>;
475 clock-names = "core", 483 clock-names = "core", "iface";
476 pinctrl-0 = <&serial_4 484 pinctrl-0 = <&serial_4_pins>;
477 pinctrl-names = "defau 485 pinctrl-names = "default";
478 status = "disabled"; 486 status = "disabled";
479 }; 487 };
480 488
481 blsp1_uart6: serial@78b4000 { <<
482 compatible = "qcom,msm <<
483 reg = <0x078b4000 0x20 <<
484 interrupts = <GIC_SPI <<
485 clocks = <&gcc GCC_BLS <<
486 <&gcc GCC_BLS <<
487 clock-names = "core", <<
488 pinctrl-0 = <&serial_5 <<
489 pinctrl-names = "defau <<
490 status = "disabled"; <<
491 }; <<
492 <<
493 blsp1_spi1: spi@78b5000 { 489 blsp1_spi1: spi@78b5000 {
494 compatible = "qcom,spi 490 compatible = "qcom,spi-qup-v2.2.1";
495 #address-cells = <1>; 491 #address-cells = <1>;
496 #size-cells = <0>; 492 #size-cells = <0>;
497 reg = <0x078b5000 0x60 493 reg = <0x078b5000 0x600>;
498 interrupts = <GIC_SPI 494 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
499 clocks = <&gcc GCC_BLS 495 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
500 <&gcc GCC_BLSP 496 <&gcc GCC_BLSP1_AHB_CLK>;
501 clock-names = "core", 497 clock-names = "core", "iface";
502 dmas = <&blsp_dma 12>, 498 dmas = <&blsp_dma 12>, <&blsp_dma 13>;
503 dma-names = "tx", "rx" 499 dma-names = "tx", "rx";
504 pinctrl-0 = <&spi_0_pi 500 pinctrl-0 = <&spi_0_pins>;
505 pinctrl-names = "defau 501 pinctrl-names = "default";
506 status = "disabled"; 502 status = "disabled";
507 }; 503 };
508 504
509 blsp1_i2c2: i2c@78b6000 { 505 blsp1_i2c2: i2c@78b6000 {
510 compatible = "qcom,i2c 506 compatible = "qcom,i2c-qup-v2.2.1";
511 #address-cells = <1>; 507 #address-cells = <1>;
512 #size-cells = <0>; 508 #size-cells = <0>;
513 reg = <0x078b6000 0x60 509 reg = <0x078b6000 0x600>;
514 interrupts = <GIC_SPI 510 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
515 clocks = <&gcc GCC_BLS 511 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
516 <&gcc GCC_BLS 512 <&gcc GCC_BLSP1_AHB_CLK>;
517 clock-names = "core", 513 clock-names = "core", "iface";
518 clock-frequency = <400 514 clock-frequency = <400000>;
519 dmas = <&blsp_dma 14>, 515 dmas = <&blsp_dma 14>, <&blsp_dma 15>;
520 dma-names = "tx", "rx" 516 dma-names = "tx", "rx";
521 pinctrl-0 = <&i2c_0_pi 517 pinctrl-0 = <&i2c_0_pins>;
522 pinctrl-names = "defau 518 pinctrl-names = "default";
523 status = "disabled"; 519 status = "disabled";
524 }; 520 };
525 521
526 blsp1_i2c3: i2c@78b7000 { 522 blsp1_i2c3: i2c@78b7000 {
527 compatible = "qcom,i2c 523 compatible = "qcom,i2c-qup-v2.2.1";
528 #address-cells = <1>; 524 #address-cells = <1>;
529 #size-cells = <0>; 525 #size-cells = <0>;
530 reg = <0x078b7000 0x60 526 reg = <0x078b7000 0x600>;
531 interrupts = <GIC_SPI 527 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
532 clocks = <&gcc GCC_BLS 528 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
533 <&gcc GCC_BLS 529 <&gcc GCC_BLSP1_AHB_CLK>;
534 clock-names = "core", 530 clock-names = "core", "iface";
535 clock-frequency = <100 531 clock-frequency = <100000>;
536 dmas = <&blsp_dma 16>, 532 dmas = <&blsp_dma 16>, <&blsp_dma 17>;
537 dma-names = "tx", "rx" 533 dma-names = "tx", "rx";
538 status = "disabled"; 534 status = "disabled";
539 }; 535 };
540 536
541 blsp1_spi4: spi@78b8000 { <<
542 compatible = "qcom,spi <<
543 #address-cells = <1>; <<
544 #size-cells = <0>; <<
545 reg = <0x78b8000 0x600 <<
546 interrupts = <GIC_SPI <<
547 clocks = <&gcc GCC_BLS <<
548 <&gcc GCC_BLS <<
549 clock-names = "core", <<
550 dmas = <&blsp_dma 18>, <<
551 dma-names = "tx", "rx" <<
552 status = "disabled"; <<
553 }; <<
554 <<
555 blsp1_i2c5: i2c@78b9000 { 537 blsp1_i2c5: i2c@78b9000 {
556 compatible = "qcom,i2c 538 compatible = "qcom,i2c-qup-v2.2.1";
557 #address-cells = <1>; 539 #address-cells = <1>;
558 #size-cells = <0>; 540 #size-cells = <0>;
559 reg = <0x78b9000 0x600 541 reg = <0x78b9000 0x600>;
560 interrupts = <GIC_SPI 542 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
561 clocks = <&gcc GCC_BLS 543 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
562 <&gcc GCC_BLS 544 <&gcc GCC_BLSP1_AHB_CLK>;
563 clock-names = "core", 545 clock-names = "core", "iface";
564 clock-frequency = <400 546 clock-frequency = <400000>;
565 dmas = <&blsp_dma 20>, 547 dmas = <&blsp_dma 20>, <&blsp_dma 21>;
566 dma-names = "tx", "rx" 548 dma-names = "tx", "rx";
567 status = "disabled"; 549 status = "disabled";
568 }; 550 };
569 551
570 blsp1_spi5: spi@78b9000 { 552 blsp1_spi5: spi@78b9000 {
571 compatible = "qcom,spi 553 compatible = "qcom,spi-qup-v2.2.1";
572 #address-cells = <1>; 554 #address-cells = <1>;
573 #size-cells = <0>; 555 #size-cells = <0>;
574 reg = <0x78b9000 0x600 556 reg = <0x78b9000 0x600>;
575 interrupts = <GIC_SPI 557 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
576 clocks = <&gcc GCC_BLS 558 clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
577 <&gcc GCC_BLS 559 <&gcc GCC_BLSP1_AHB_CLK>;
578 clock-names = "core", 560 clock-names = "core", "iface";
579 dmas = <&blsp_dma 20>, 561 dmas = <&blsp_dma 20>, <&blsp_dma 21>;
580 dma-names = "tx", "rx" 562 dma-names = "tx", "rx";
581 status = "disabled"; 563 status = "disabled";
582 }; 564 };
583 565
584 blsp1_i2c6: i2c@78ba000 { 566 blsp1_i2c6: i2c@78ba000 {
585 compatible = "qcom,i2c 567 compatible = "qcom,i2c-qup-v2.2.1";
586 #address-cells = <1>; 568 #address-cells = <1>;
587 #size-cells = <0>; 569 #size-cells = <0>;
588 reg = <0x078ba000 0x60 570 reg = <0x078ba000 0x600>;
589 interrupts = <GIC_SPI 571 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
590 clocks = <&gcc GCC_BLS 572 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
591 <&gcc GCC_BLS 573 <&gcc GCC_BLSP1_AHB_CLK>;
592 clock-names = "core", 574 clock-names = "core", "iface";
593 clock-frequency = <100 575 clock-frequency = <100000>;
594 dmas = <&blsp_dma 22>, 576 dmas = <&blsp_dma 22>, <&blsp_dma 23>;
595 dma-names = "tx", "rx" 577 dma-names = "tx", "rx";
596 status = "disabled"; 578 status = "disabled";
597 }; 579 };
598 580
599 qpic_bam: dma-controller@79840 581 qpic_bam: dma-controller@7984000 {
600 compatible = "qcom,bam 582 compatible = "qcom,bam-v1.7.0";
601 reg = <0x07984000 0x1a 583 reg = <0x07984000 0x1a000>;
602 interrupts = <GIC_SPI 584 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
603 clocks = <&gcc GCC_QPI 585 clocks = <&gcc GCC_QPIC_AHB_CLK>;
604 clock-names = "bam_clk 586 clock-names = "bam_clk";
605 #dma-cells = <1>; 587 #dma-cells = <1>;
606 qcom,ee = <0>; 588 qcom,ee = <0>;
607 status = "disabled"; 589 status = "disabled";
608 }; 590 };
609 591
610 qpic_nand: nand-controller@79b 592 qpic_nand: nand-controller@79b0000 {
611 compatible = "qcom,ipq 593 compatible = "qcom,ipq8074-nand";
612 reg = <0x079b0000 0x10 594 reg = <0x079b0000 0x10000>;
613 #address-cells = <1>; 595 #address-cells = <1>;
614 #size-cells = <0>; 596 #size-cells = <0>;
615 clocks = <&gcc GCC_QPI 597 clocks = <&gcc GCC_QPIC_CLK>,
616 <&gcc GCC_QPI 598 <&gcc GCC_QPIC_AHB_CLK>;
617 clock-names = "core", 599 clock-names = "core", "aon";
618 600
619 dmas = <&qpic_bam 0>, 601 dmas = <&qpic_bam 0>,
620 <&qpic_bam 1>, 602 <&qpic_bam 1>,
621 <&qpic_bam 2>; 603 <&qpic_bam 2>;
622 dma-names = "tx", "rx" 604 dma-names = "tx", "rx", "cmd";
623 pinctrl-0 = <&qpic_pin 605 pinctrl-0 = <&qpic_pins>;
624 pinctrl-names = "defau 606 pinctrl-names = "default";
625 status = "disabled"; 607 status = "disabled";
626 }; 608 };
627 609
628 usb_0: usb@8af8800 { 610 usb_0: usb@8af8800 {
629 compatible = "qcom,ipq 611 compatible = "qcom,ipq8074-dwc3", "qcom,dwc3";
630 reg = <0x08af8800 0x40 612 reg = <0x08af8800 0x400>;
631 #address-cells = <1>; 613 #address-cells = <1>;
632 #size-cells = <1>; 614 #size-cells = <1>;
633 ranges; 615 ranges;
634 616
635 clocks = <&gcc GCC_SYS 617 clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
636 <&gcc GCC_USB0 618 <&gcc GCC_USB0_MASTER_CLK>,
637 <&gcc GCC_USB0 619 <&gcc GCC_USB0_SLEEP_CLK>,
638 <&gcc GCC_USB0 620 <&gcc GCC_USB0_MOCK_UTMI_CLK>;
639 clock-names = "cfg_noc 621 clock-names = "cfg_noc",
640 "core", 622 "core",
641 "sleep", 623 "sleep",
642 "mock_utmi"; 624 "mock_utmi";
643 625
644 assigned-clocks = <&gc 626 assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
645 <&gc 627 <&gcc GCC_USB0_MASTER_CLK>,
646 <&gc 628 <&gcc GCC_USB0_MOCK_UTMI_CLK>;
647 assigned-clock-rates = 629 assigned-clock-rates = <133330000>,
648 630 <133330000>,
649 631 <19200000>;
650 632
651 interrupts = <GIC_SPI <<
652 <GIC_SPI <<
653 <GIC_SPI <<
654 interrupt-names = "pwr <<
655 "qus <<
656 "ss_ <<
657 <<
658 power-domains = <&gcc 633 power-domains = <&gcc USB0_GDSC>;
659 634
660 resets = <&gcc GCC_USB 635 resets = <&gcc GCC_USB0_BCR>;
661 status = "disabled"; 636 status = "disabled";
662 637
663 dwc_0: usb@8a00000 { 638 dwc_0: usb@8a00000 {
664 compatible = " 639 compatible = "snps,dwc3";
665 reg = <0x8a000 640 reg = <0x8a00000 0xcd00>;
666 interrupts = < 641 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
667 phys = <&qusb_ !! 642 phys = <&qusb_phy_0>, <&usb0_ssphy>;
668 phy-names = "u 643 phy-names = "usb2-phy", "usb3-phy";
669 snps,parkmode- 644 snps,parkmode-disable-ss-quirk;
670 snps,is-utmi-l 645 snps,is-utmi-l1-suspend;
671 snps,hird-thre 646 snps,hird-threshold = /bits/ 8 <0x0>;
672 snps,dis_u2_su 647 snps,dis_u2_susphy_quirk;
673 snps,dis_u3_su 648 snps,dis_u3_susphy_quirk;
674 dr_mode = "hos 649 dr_mode = "host";
675 }; 650 };
676 }; 651 };
677 652
678 usb_1: usb@8cf8800 { 653 usb_1: usb@8cf8800 {
679 compatible = "qcom,ipq 654 compatible = "qcom,ipq8074-dwc3", "qcom,dwc3";
680 reg = <0x08cf8800 0x40 655 reg = <0x08cf8800 0x400>;
681 #address-cells = <1>; 656 #address-cells = <1>;
682 #size-cells = <1>; 657 #size-cells = <1>;
683 ranges; 658 ranges;
684 659
685 clocks = <&gcc GCC_SYS 660 clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>,
686 <&gcc GCC_USB1 661 <&gcc GCC_USB1_MASTER_CLK>,
687 <&gcc GCC_USB1 662 <&gcc GCC_USB1_SLEEP_CLK>,
688 <&gcc GCC_USB1 663 <&gcc GCC_USB1_MOCK_UTMI_CLK>;
689 clock-names = "cfg_noc 664 clock-names = "cfg_noc",
690 "core", 665 "core",
691 "sleep", 666 "sleep",
692 "mock_utmi"; 667 "mock_utmi";
693 668
694 assigned-clocks = <&gc 669 assigned-clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>,
695 <&gc 670 <&gcc GCC_USB1_MASTER_CLK>,
696 <&gc 671 <&gcc GCC_USB1_MOCK_UTMI_CLK>;
697 assigned-clock-rates = 672 assigned-clock-rates = <133330000>,
698 673 <133330000>,
699 674 <19200000>;
700 675
701 interrupts = <GIC_SPI <<
702 <GIC_SPI <<
703 <GIC_SPI <<
704 interrupt-names = "pwr <<
705 "qus <<
706 "ss_ <<
707 <<
708 power-domains = <&gcc 676 power-domains = <&gcc USB1_GDSC>;
709 677
710 resets = <&gcc GCC_USB 678 resets = <&gcc GCC_USB1_BCR>;
711 status = "disabled"; 679 status = "disabled";
712 680
713 dwc_1: usb@8c00000 { 681 dwc_1: usb@8c00000 {
714 compatible = " 682 compatible = "snps,dwc3";
715 reg = <0x8c000 683 reg = <0x8c00000 0xcd00>;
716 interrupts = < 684 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
717 phys = <&qusb_ !! 685 phys = <&qusb_phy_1>, <&usb1_ssphy>;
718 phy-names = "u 686 phy-names = "usb2-phy", "usb3-phy";
719 snps,parkmode- 687 snps,parkmode-disable-ss-quirk;
720 snps,is-utmi-l 688 snps,is-utmi-l1-suspend;
721 snps,hird-thre 689 snps,hird-threshold = /bits/ 8 <0x0>;
722 snps,dis_u2_su 690 snps,dis_u2_susphy_quirk;
723 snps,dis_u3_su 691 snps,dis_u3_susphy_quirk;
724 dr_mode = "hos 692 dr_mode = "host";
725 }; 693 };
726 }; 694 };
727 695
728 intc: interrupt-controller@b00 696 intc: interrupt-controller@b000000 {
729 compatible = "qcom,msm 697 compatible = "qcom,msm-qgic2";
730 #address-cells = <1>; 698 #address-cells = <1>;
731 #size-cells = <1>; 699 #size-cells = <1>;
732 interrupt-controller; 700 interrupt-controller;
733 #interrupt-cells = <3> 701 #interrupt-cells = <3>;
734 reg = <0x0b000000 0x10 702 reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
735 ranges = <0 0xb00a000 703 ranges = <0 0xb00a000 0xffd>;
736 704
737 v2m@0 { 705 v2m@0 {
738 compatible = " 706 compatible = "arm,gic-v2m-frame";
739 msi-controller 707 msi-controller;
740 reg = <0x0 0xf 708 reg = <0x0 0xffd>;
741 }; 709 };
742 }; 710 };
743 711
744 watchdog: watchdog@b017000 { 712 watchdog: watchdog@b017000 {
745 compatible = "qcom,kps 713 compatible = "qcom,kpss-wdt";
746 reg = <0xb017000 0x100 714 reg = <0xb017000 0x1000>;
747 interrupts = <GIC_SPI 715 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
748 clocks = <&sleep_clk>; 716 clocks = <&sleep_clk>;
749 timeout-sec = <30>; 717 timeout-sec = <30>;
750 }; 718 };
751 719
752 apcs_glb: mailbox@b111000 { 720 apcs_glb: mailbox@b111000 {
753 compatible = "qcom,ipq 721 compatible = "qcom,ipq8074-apcs-apps-global",
754 "qcom,ipq 722 "qcom,ipq6018-apcs-apps-global";
755 reg = <0x0b111000 0x10 723 reg = <0x0b111000 0x1000>;
756 clocks = <&a53pll>, <& !! 724 clocks = <&a53pll>, <&xo>;
757 clock-names = "pll", " !! 725 clock-names = "pll", "xo";
758 726
759 #clock-cells = <1>; 727 #clock-cells = <1>;
760 #mbox-cells = <1>; 728 #mbox-cells = <1>;
761 }; 729 };
762 730
763 a53pll: clock@b116000 { 731 a53pll: clock@b116000 {
764 compatible = "qcom,ipq 732 compatible = "qcom,ipq8074-a53pll";
765 reg = <0x0b116000 0x40 733 reg = <0x0b116000 0x40>;
766 #clock-cells = <0>; 734 #clock-cells = <0>;
767 clocks = <&xo>; 735 clocks = <&xo>;
768 clock-names = "xo"; 736 clock-names = "xo";
769 }; 737 };
770 738
771 timer@b120000 { 739 timer@b120000 {
772 #address-cells = <1>; 740 #address-cells = <1>;
773 #size-cells = <1>; 741 #size-cells = <1>;
774 ranges; 742 ranges;
775 compatible = "arm,armv 743 compatible = "arm,armv7-timer-mem";
776 reg = <0x0b120000 0x10 744 reg = <0x0b120000 0x1000>;
777 745
778 frame@b120000 { 746 frame@b120000 {
779 frame-number = 747 frame-number = <0>;
780 interrupts = < 748 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
781 < 749 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
782 reg = <0x0b121 750 reg = <0x0b121000 0x1000>,
783 <0x0b122 751 <0x0b122000 0x1000>;
784 }; 752 };
785 753
786 frame@b123000 { 754 frame@b123000 {
787 frame-number = 755 frame-number = <1>;
788 interrupts = < 756 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
789 reg = <0x0b123 757 reg = <0x0b123000 0x1000>;
790 status = "disa 758 status = "disabled";
791 }; 759 };
792 760
793 frame@b124000 { 761 frame@b124000 {
794 frame-number = 762 frame-number = <2>;
795 interrupts = < 763 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
796 reg = <0x0b124 764 reg = <0x0b124000 0x1000>;
797 status = "disa 765 status = "disabled";
798 }; 766 };
799 767
800 frame@b125000 { 768 frame@b125000 {
801 frame-number = 769 frame-number = <3>;
802 interrupts = < 770 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
803 reg = <0x0b125 771 reg = <0x0b125000 0x1000>;
804 status = "disa 772 status = "disabled";
805 }; 773 };
806 774
807 frame@b126000 { 775 frame@b126000 {
808 frame-number = 776 frame-number = <4>;
809 interrupts = < 777 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
810 reg = <0x0b126 778 reg = <0x0b126000 0x1000>;
811 status = "disa 779 status = "disabled";
812 }; 780 };
813 781
814 frame@b127000 { 782 frame@b127000 {
815 frame-number = 783 frame-number = <5>;
816 interrupts = < 784 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
817 reg = <0x0b127 785 reg = <0x0b127000 0x1000>;
818 status = "disa 786 status = "disabled";
819 }; 787 };
820 788
821 frame@b128000 { 789 frame@b128000 {
822 frame-number = 790 frame-number = <6>;
823 interrupts = < 791 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
824 reg = <0x0b128 792 reg = <0x0b128000 0x1000>;
825 status = "disa 793 status = "disabled";
826 }; 794 };
827 }; 795 };
828 796
829 pcie1: pcie@10000000 { !! 797 pcie1: pci@10000000 {
830 compatible = "qcom,pci 798 compatible = "qcom,pcie-ipq8074";
831 reg = <0x10000000 0xf1 799 reg = <0x10000000 0xf1d>,
832 <0x10000f20 0xa8 800 <0x10000f20 0xa8>,
833 <0x00088000 0x20 801 <0x00088000 0x2000>,
834 <0x10100000 0x10 802 <0x10100000 0x1000>;
835 reg-names = "dbi", "el 803 reg-names = "dbi", "elbi", "parf", "config";
836 device_type = "pci"; 804 device_type = "pci";
837 linux,pci-domain = <1> 805 linux,pci-domain = <1>;
838 bus-range = <0x00 0xff 806 bus-range = <0x00 0xff>;
839 num-lanes = <1>; 807 num-lanes = <1>;
840 max-link-speed = <2>; 808 max-link-speed = <2>;
841 #address-cells = <3>; 809 #address-cells = <3>;
842 #size-cells = <2>; 810 #size-cells = <2>;
843 811
844 phys = <&pcie_qmp1>; !! 812 phys = <&pcie_phy1>;
845 phy-names = "pciephy"; 813 phy-names = "pciephy";
846 814
847 ranges = <0x81000000 0 815 ranges = <0x81000000 0x0 0x00000000 0x10200000 0x0 0x10000>, /* I/O */
848 <0x82000000 0 816 <0x82000000 0x0 0x10220000 0x10220000 0x0 0xfde0000>; /* MEM */
849 817
850 interrupts = <GIC_SPI 818 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
851 interrupt-names = "msi 819 interrupt-names = "msi";
852 #interrupt-cells = <1> 820 #interrupt-cells = <1>;
853 interrupt-map-mask = < 821 interrupt-map-mask = <0 0 0 0x7>;
854 interrupt-map = <0 0 0 822 interrupt-map = <0 0 0 1 &intc 0 0 142
855 IRQ_T 823 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
856 <0 0 0 824 <0 0 0 2 &intc 0 0 143
857 IRQ_T 825 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
858 <0 0 0 826 <0 0 0 3 &intc 0 0 144
859 IRQ_T 827 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
860 <0 0 0 828 <0 0 0 4 &intc 0 0 145
861 IRQ_T 829 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
862 830
863 clocks = <&gcc GCC_SYS 831 clocks = <&gcc GCC_SYS_NOC_PCIE1_AXI_CLK>,
864 <&gcc GCC_PCI 832 <&gcc GCC_PCIE1_AXI_M_CLK>,
865 <&gcc GCC_PCI 833 <&gcc GCC_PCIE1_AXI_S_CLK>,
866 <&gcc GCC_PCI 834 <&gcc GCC_PCIE1_AHB_CLK>,
867 <&gcc GCC_PCI 835 <&gcc GCC_PCIE1_AUX_CLK>;
868 clock-names = "iface", 836 clock-names = "iface",
869 "axi_m", 837 "axi_m",
870 "axi_s", 838 "axi_s",
871 "ahb", 839 "ahb",
872 "aux"; 840 "aux";
873 resets = <&gcc GCC_PCI 841 resets = <&gcc GCC_PCIE1_PIPE_ARES>,
874 <&gcc GCC_PCI 842 <&gcc GCC_PCIE1_SLEEP_ARES>,
875 <&gcc GCC_PCI 843 <&gcc GCC_PCIE1_CORE_STICKY_ARES>,
876 <&gcc GCC_PCI 844 <&gcc GCC_PCIE1_AXI_MASTER_ARES>,
877 <&gcc GCC_PCI 845 <&gcc GCC_PCIE1_AXI_SLAVE_ARES>,
878 <&gcc GCC_PCI 846 <&gcc GCC_PCIE1_AHB_ARES>,
879 <&gcc GCC_PCI 847 <&gcc GCC_PCIE1_AXI_MASTER_STICKY_ARES>;
880 reset-names = "pipe", 848 reset-names = "pipe",
881 "sleep", 849 "sleep",
882 "sticky" 850 "sticky",
883 "axi_m", 851 "axi_m",
884 "axi_s", 852 "axi_s",
885 "ahb", 853 "ahb",
886 "axi_m_s 854 "axi_m_sticky";
887 status = "disabled"; 855 status = "disabled";
888 <<
889 pcie@0 { <<
890 device_type = <<
891 reg = <0x0 0x0 <<
892 bus-range = <0 <<
893 <<
894 #address-cells <<
895 #size-cells = <<
896 ranges; <<
897 }; <<
898 }; 856 };
899 857
900 pcie0: pcie@20000000 { !! 858 pcie0: pci@20000000 {
901 compatible = "qcom,pci 859 compatible = "qcom,pcie-ipq8074-gen3";
902 reg = <0x20000000 0xf1 860 reg = <0x20000000 0xf1d>,
903 <0x20000f20 0xa8 861 <0x20000f20 0xa8>,
904 <0x20001000 0x10 862 <0x20001000 0x1000>,
905 <0x00080000 0x40 863 <0x00080000 0x4000>,
906 <0x20100000 0x10 864 <0x20100000 0x1000>;
907 reg-names = "dbi", "el 865 reg-names = "dbi", "elbi", "atu", "parf", "config";
908 device_type = "pci"; 866 device_type = "pci";
909 linux,pci-domain = <0> 867 linux,pci-domain = <0>;
910 bus-range = <0x00 0xff 868 bus-range = <0x00 0xff>;
911 num-lanes = <1>; 869 num-lanes = <1>;
912 max-link-speed = <3>; 870 max-link-speed = <3>;
913 #address-cells = <3>; 871 #address-cells = <3>;
914 #size-cells = <2>; 872 #size-cells = <2>;
915 873
916 phys = <&pcie_qmp0>; !! 874 phys = <&pcie_phy0>;
917 phy-names = "pciephy"; 875 phy-names = "pciephy";
918 876
919 ranges = <0x81000000 0 877 ranges = <0x81000000 0x0 0x00000000 0x20200000 0x0 0x10000>, /* I/O */
920 <0x82000000 0 878 <0x82000000 0x0 0x20220000 0x20220000 0x0 0xfde0000>; /* MEM */
921 879
922 interrupts = <GIC_SPI 880 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
923 interrupt-names = "msi 881 interrupt-names = "msi";
924 #interrupt-cells = <1> 882 #interrupt-cells = <1>;
925 interrupt-map-mask = < 883 interrupt-map-mask = <0 0 0 0x7>;
926 interrupt-map = <0 0 0 884 interrupt-map = <0 0 0 1 &intc 0 0 75
927 IRQ_T 885 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
928 <0 0 0 886 <0 0 0 2 &intc 0 0 78
929 IRQ_T 887 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
930 <0 0 0 888 <0 0 0 3 &intc 0 0 79
931 IRQ_T 889 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
932 <0 0 0 890 <0 0 0 4 &intc 0 0 83
933 IRQ_T 891 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
934 892
935 clocks = <&gcc GCC_SYS 893 clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
936 <&gcc GCC_PCI 894 <&gcc GCC_PCIE0_AXI_M_CLK>,
937 <&gcc GCC_PCI 895 <&gcc GCC_PCIE0_AXI_S_CLK>,
938 <&gcc GCC_PCI 896 <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>,
939 <&gcc GCC_PCI 897 <&gcc GCC_PCIE0_RCHNG_CLK>;
940 clock-names = "iface", 898 clock-names = "iface",
941 "axi_m", 899 "axi_m",
942 "axi_s", 900 "axi_s",
943 "axi_bri 901 "axi_bridge",
944 "rchng"; 902 "rchng";
945 903
946 resets = <&gcc GCC_PCI 904 resets = <&gcc GCC_PCIE0_PIPE_ARES>,
947 <&gcc GCC_PCI 905 <&gcc GCC_PCIE0_SLEEP_ARES>,
948 <&gcc GCC_PCI 906 <&gcc GCC_PCIE0_CORE_STICKY_ARES>,
949 <&gcc GCC_PCI 907 <&gcc GCC_PCIE0_AXI_MASTER_ARES>,
950 <&gcc GCC_PCI 908 <&gcc GCC_PCIE0_AXI_SLAVE_ARES>,
951 <&gcc GCC_PCI 909 <&gcc GCC_PCIE0_AHB_ARES>,
952 <&gcc GCC_PCI 910 <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>,
953 <&gcc GCC_PCI 911 <&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>;
954 reset-names = "pipe", 912 reset-names = "pipe",
955 "sleep", 913 "sleep",
956 "sticky" 914 "sticky",
957 "axi_m", 915 "axi_m",
958 "axi_s", 916 "axi_s",
959 "ahb", 917 "ahb",
960 "axi_m_s 918 "axi_m_sticky",
961 "axi_s_s 919 "axi_s_sticky";
962 status = "disabled"; 920 status = "disabled";
963 <<
964 pcie@0 { <<
965 device_type = <<
966 reg = <0x0 0x0 <<
967 bus-range = <0 <<
968 <<
969 #address-cells <<
970 #size-cells = <<
971 ranges; <<
972 }; <<
973 }; 921 };
974 }; 922 };
975 923
976 timer { 924 timer {
977 compatible = "arm,armv8-timer" 925 compatible = "arm,armv8-timer";
978 interrupts = <GIC_PPI 2 (GIC_C 926 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
979 <GIC_PPI 3 (GIC_C 927 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
980 <GIC_PPI 4 (GIC_C 928 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
981 <GIC_PPI 1 (GIC_C 929 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
982 }; 930 };
983 931
984 thermal-zones { 932 thermal-zones {
985 nss-top-thermal { 933 nss-top-thermal {
986 polling-delay-passive 934 polling-delay-passive = <250>;
>> 935 polling-delay = <1000>;
987 936
988 thermal-sensors = <&ts 937 thermal-sensors = <&tsens 4>;
989 938
990 trips { 939 trips {
991 nss-top-crit { 940 nss-top-crit {
992 temper 941 temperature = <110000>;
993 hyster 942 hysteresis = <1000>;
994 type = 943 type = "critical";
995 }; 944 };
996 }; 945 };
997 }; 946 };
998 947
999 nss0-thermal { 948 nss0-thermal {
1000 polling-delay-passive 949 polling-delay-passive = <250>;
>> 950 polling-delay = <1000>;
1001 951
1002 thermal-sensors = <&t 952 thermal-sensors = <&tsens 5>;
1003 953
1004 trips { 954 trips {
1005 nss-0-crit { 955 nss-0-crit {
1006 tempe 956 temperature = <110000>;
1007 hyste 957 hysteresis = <1000>;
1008 type 958 type = "critical";
1009 }; 959 };
1010 }; 960 };
1011 }; 961 };
1012 962
1013 nss1-thermal { 963 nss1-thermal {
1014 polling-delay-passive 964 polling-delay-passive = <250>;
>> 965 polling-delay = <1000>;
1015 966
1016 thermal-sensors = <&t 967 thermal-sensors = <&tsens 6>;
1017 968
1018 trips { 969 trips {
1019 nss-1-crit { 970 nss-1-crit {
1020 tempe 971 temperature = <110000>;
1021 hyste 972 hysteresis = <1000>;
1022 type 973 type = "critical";
1023 }; 974 };
1024 }; 975 };
1025 }; 976 };
1026 977
1027 wcss-phya0-thermal { 978 wcss-phya0-thermal {
1028 polling-delay-passive 979 polling-delay-passive = <250>;
>> 980 polling-delay = <1000>;
1029 981
1030 thermal-sensors = <&t 982 thermal-sensors = <&tsens 7>;
1031 983
1032 trips { 984 trips {
1033 wcss-phya0-cr 985 wcss-phya0-crit {
1034 tempe 986 temperature = <110000>;
1035 hyste 987 hysteresis = <1000>;
1036 type 988 type = "critical";
1037 }; 989 };
1038 }; 990 };
1039 }; 991 };
1040 992
1041 wcss-phya1-thermal { 993 wcss-phya1-thermal {
1042 polling-delay-passive 994 polling-delay-passive = <250>;
>> 995 polling-delay = <1000>;
1043 996
1044 thermal-sensors = <&t 997 thermal-sensors = <&tsens 8>;
1045 998
1046 trips { 999 trips {
1047 wcss-phya1-cr 1000 wcss-phya1-crit {
1048 tempe 1001 temperature = <110000>;
1049 hyste 1002 hysteresis = <1000>;
1050 type 1003 type = "critical";
1051 }; 1004 };
1052 }; 1005 };
1053 }; 1006 };
1054 1007
1055 cpu0_thermal: cpu0-thermal { 1008 cpu0_thermal: cpu0-thermal {
1056 polling-delay-passive 1009 polling-delay-passive = <250>;
>> 1010 polling-delay = <1000>;
1057 1011
1058 thermal-sensors = <&t 1012 thermal-sensors = <&tsens 9>;
1059 1013
1060 trips { 1014 trips {
1061 cpu0-crit { 1015 cpu0-crit {
1062 tempe 1016 temperature = <110000>;
1063 hyste 1017 hysteresis = <1000>;
1064 type 1018 type = "critical";
1065 }; 1019 };
1066 }; 1020 };
1067 }; 1021 };
1068 1022
1069 cpu1_thermal: cpu1-thermal { 1023 cpu1_thermal: cpu1-thermal {
1070 polling-delay-passive 1024 polling-delay-passive = <250>;
>> 1025 polling-delay = <1000>;
1071 1026
1072 thermal-sensors = <&t 1027 thermal-sensors = <&tsens 10>;
1073 1028
1074 trips { 1029 trips {
1075 cpu1-crit { 1030 cpu1-crit {
1076 tempe 1031 temperature = <110000>;
1077 hyste 1032 hysteresis = <1000>;
1078 type 1033 type = "critical";
1079 }; 1034 };
1080 }; 1035 };
1081 }; 1036 };
1082 1037
1083 cpu2_thermal: cpu2-thermal { 1038 cpu2_thermal: cpu2-thermal {
1084 polling-delay-passive 1039 polling-delay-passive = <250>;
>> 1040 polling-delay = <1000>;
1085 1041
1086 thermal-sensors = <&t 1042 thermal-sensors = <&tsens 11>;
1087 1043
1088 trips { 1044 trips {
1089 cpu2-crit { 1045 cpu2-crit {
1090 tempe 1046 temperature = <110000>;
1091 hyste 1047 hysteresis = <1000>;
1092 type 1048 type = "critical";
1093 }; 1049 };
1094 }; 1050 };
1095 }; 1051 };
1096 1052
1097 cpu3_thermal: cpu3-thermal { 1053 cpu3_thermal: cpu3-thermal {
1098 polling-delay-passive 1054 polling-delay-passive = <250>;
>> 1055 polling-delay = <1000>;
1099 1056
1100 thermal-sensors = <&t 1057 thermal-sensors = <&tsens 12>;
1101 1058
1102 trips { 1059 trips {
1103 cpu3-crit { 1060 cpu3-crit {
1104 tempe 1061 temperature = <110000>;
1105 hyste 1062 hysteresis = <1000>;
1106 type 1063 type = "critical";
1107 }; 1064 };
1108 }; 1065 };
1109 }; 1066 };
1110 1067
1111 cluster_thermal: cluster-ther 1068 cluster_thermal: cluster-thermal {
1112 polling-delay-passive 1069 polling-delay-passive = <250>;
>> 1070 polling-delay = <1000>;
1113 1071
1114 thermal-sensors = <&t 1072 thermal-sensors = <&tsens 13>;
1115 1073
1116 trips { 1074 trips {
1117 cluster-crit 1075 cluster-crit {
1118 tempe 1076 temperature = <110000>;
1119 hyste 1077 hysteresis = <1000>;
1120 type 1078 type = "critical";
1121 }; 1079 };
1122 }; 1080 };
1123 }; 1081 };
1124 1082
1125 wcss-phyb0-thermal { 1083 wcss-phyb0-thermal {
1126 polling-delay-passive 1084 polling-delay-passive = <250>;
>> 1085 polling-delay = <1000>;
1127 1086
1128 thermal-sensors = <&t 1087 thermal-sensors = <&tsens 14>;
1129 1088
1130 trips { 1089 trips {
1131 wcss-phyb0-cr 1090 wcss-phyb0-crit {
1132 tempe 1091 temperature = <110000>;
1133 hyste 1092 hysteresis = <1000>;
1134 type 1093 type = "critical";
1135 }; 1094 };
1136 }; 1095 };
1137 }; 1096 };
1138 1097
1139 wcss-phyb1-thermal { 1098 wcss-phyb1-thermal {
1140 polling-delay-passive 1099 polling-delay-passive = <250>;
>> 1100 polling-delay = <1000>;
1141 1101
1142 thermal-sensors = <&t 1102 thermal-sensors = <&tsens 15>;
1143 1103
1144 trips { 1104 trips {
1145 wcss-phyb1-cr 1105 wcss-phyb1-crit {
1146 tempe 1106 temperature = <110000>;
1147 hyste 1107 hysteresis = <1000>;
1148 type 1108 type = "critical";
1149 }; 1109 };
1150 }; 1110 };
1151 }; 1111 };
1152 }; 1112 };
1153 }; 1113 };
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