1 // SPDX-License-Identifier: GPL-2.0-only 1 // SPDX-License-Identifier: GPL-2.0-only
2 /* 2 /*
3 * Copyright (c) 2017, The Linux Foundation. A 3 * Copyright (c) 2017, The Linux Foundation. All rights reserved.
4 */ 4 */
5 5
6 #include <dt-bindings/interrupt-controller/arm 6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,gcc-ipq8074.h 7 #include <dt-bindings/clock/qcom,gcc-ipq8074.h>
8 8
9 / { 9 / {
10 #address-cells = <2>; 10 #address-cells = <2>;
11 #size-cells = <2>; 11 #size-cells = <2>;
12 12
13 model = "Qualcomm Technologies, Inc. I 13 model = "Qualcomm Technologies, Inc. IPQ8074";
14 compatible = "qcom,ipq8074"; 14 compatible = "qcom,ipq8074";
15 interrupt-parent = <&intc>; 15 interrupt-parent = <&intc>;
16 16
17 clocks { 17 clocks {
18 sleep_clk: sleep_clk { 18 sleep_clk: sleep_clk {
19 compatible = "fixed-cl 19 compatible = "fixed-clock";
20 clock-frequency = <327 20 clock-frequency = <32768>;
21 #clock-cells = <0>; 21 #clock-cells = <0>;
22 }; 22 };
23 23
24 xo: xo { 24 xo: xo {
25 compatible = "fixed-cl 25 compatible = "fixed-clock";
26 clock-frequency = <192 26 clock-frequency = <19200000>;
27 #clock-cells = <0>; 27 #clock-cells = <0>;
28 }; 28 };
29 }; 29 };
30 30
31 cpus { 31 cpus {
32 #address-cells = <1>; 32 #address-cells = <1>;
33 #size-cells = <0>; 33 #size-cells = <0>;
34 34
35 CPU0: cpu@0 { 35 CPU0: cpu@0 {
36 device_type = "cpu"; 36 device_type = "cpu";
37 compatible = "arm,cort 37 compatible = "arm,cortex-a53";
38 reg = <0x0>; 38 reg = <0x0>;
39 next-level-cache = <&L 39 next-level-cache = <&L2_0>;
40 enable-method = "psci" 40 enable-method = "psci";
41 }; 41 };
42 42
43 CPU1: cpu@1 { 43 CPU1: cpu@1 {
44 device_type = "cpu"; 44 device_type = "cpu";
45 compatible = "arm,cort 45 compatible = "arm,cortex-a53";
46 enable-method = "psci" 46 enable-method = "psci";
47 reg = <0x1>; 47 reg = <0x1>;
48 next-level-cache = <&L 48 next-level-cache = <&L2_0>;
49 }; 49 };
50 50
51 CPU2: cpu@2 { 51 CPU2: cpu@2 {
52 device_type = "cpu"; 52 device_type = "cpu";
53 compatible = "arm,cort 53 compatible = "arm,cortex-a53";
54 enable-method = "psci" 54 enable-method = "psci";
55 reg = <0x2>; 55 reg = <0x2>;
56 next-level-cache = <&L 56 next-level-cache = <&L2_0>;
57 }; 57 };
58 58
59 CPU3: cpu@3 { 59 CPU3: cpu@3 {
60 device_type = "cpu"; 60 device_type = "cpu";
61 compatible = "arm,cort 61 compatible = "arm,cortex-a53";
62 enable-method = "psci" 62 enable-method = "psci";
63 reg = <0x3>; 63 reg = <0x3>;
64 next-level-cache = <&L 64 next-level-cache = <&L2_0>;
65 }; 65 };
66 66
67 L2_0: l2-cache { 67 L2_0: l2-cache {
68 compatible = "cache"; 68 compatible = "cache";
69 cache-level = <2>; 69 cache-level = <2>;
70 cache-unified; 70 cache-unified;
71 }; 71 };
72 }; 72 };
73 73
74 pmu { 74 pmu {
75 compatible = "arm,cortex-a53-p 75 compatible = "arm,cortex-a53-pmu";
76 interrupts = <GIC_PPI 7 (GIC_C 76 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
77 }; 77 };
78 78
79 psci { 79 psci {
80 compatible = "arm,psci-1.0"; 80 compatible = "arm,psci-1.0";
81 method = "smc"; 81 method = "smc";
82 }; 82 };
83 83
84 reserved-memory { 84 reserved-memory {
85 #address-cells = <2>; 85 #address-cells = <2>;
86 #size-cells = <2>; 86 #size-cells = <2>;
87 ranges; 87 ranges;
88 88
89 bootloader@4a600000 { 89 bootloader@4a600000 {
90 reg = <0x0 0x4a600000 90 reg = <0x0 0x4a600000 0x0 0x400000>;
91 no-map; 91 no-map;
92 }; 92 };
93 93
94 sbl@4aa00000 { 94 sbl@4aa00000 {
95 reg = <0x0 0x4aa00000 95 reg = <0x0 0x4aa00000 0x0 0x100000>;
96 no-map; 96 no-map;
97 }; 97 };
98 98
99 smem@4ab00000 { 99 smem@4ab00000 {
100 compatible = "qcom,sme 100 compatible = "qcom,smem";
101 reg = <0x0 0x4ab00000 101 reg = <0x0 0x4ab00000 0x0 0x100000>;
102 no-map; 102 no-map;
103 103
104 hwlocks = <&tcsr_mutex 104 hwlocks = <&tcsr_mutex 3>;
105 }; 105 };
106 106
107 memory@4ac00000 { 107 memory@4ac00000 {
108 reg = <0x0 0x4ac00000 108 reg = <0x0 0x4ac00000 0x0 0x400000>;
109 no-map; 109 no-map;
110 }; 110 };
111 }; 111 };
112 112
113 firmware { 113 firmware {
114 scm { 114 scm {
115 compatible = "qcom,scm 115 compatible = "qcom,scm-ipq8074", "qcom,scm";
116 qcom,dload-mode = <&tc 116 qcom,dload-mode = <&tcsr 0x6100>;
117 }; 117 };
118 }; 118 };
119 119
120 soc: soc@0 { 120 soc: soc@0 {
121 #address-cells = <1>; 121 #address-cells = <1>;
122 #size-cells = <1>; 122 #size-cells = <1>;
123 ranges = <0 0 0 0xffffffff>; 123 ranges = <0 0 0 0xffffffff>;
124 compatible = "simple-bus"; 124 compatible = "simple-bus";
125 125
126 ssphy_1: phy@58000 { 126 ssphy_1: phy@58000 {
127 compatible = "qcom,ipq 127 compatible = "qcom,ipq8074-qmp-usb3-phy";
128 reg = <0x00058000 0x10 !! 128 reg = <0x00058000 0x1c4>;
>> 129 #address-cells = <1>;
>> 130 #size-cells = <1>;
>> 131 ranges;
129 132
130 clocks = <&gcc GCC_USB 133 clocks = <&gcc GCC_USB1_AUX_CLK>,
131 <&xo>, !! 134 <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
132 <&gcc GCC_USB !! 135 <&xo>;
133 <&gcc GCC_USB !! 136 clock-names = "aux", "cfg_ahb", "ref";
134 clock-names = "aux", <<
135 "ref", <<
136 "cfg_ahb <<
137 "pipe"; <<
138 clock-output-names = " <<
139 #clock-cells = <0>; <<
140 #phy-cells = <0>; <<
141 137
142 resets = <&gcc GCC_USB 138 resets = <&gcc GCC_USB1_PHY_BCR>,
143 <&gcc GCC_USB !! 139 <&gcc GCC_USB3PHY_1_PHY_BCR>;
144 reset-names = "phy", !! 140 reset-names = "phy","common";
145 "phy_phy <<
146 <<
147 status = "disabled"; 141 status = "disabled";
>> 142
>> 143 usb1_ssphy: phy@58200 {
>> 144 reg = <0x00058200 0x130>, /* Tx */
>> 145 <0x00058400 0x200>, /* Rx */
>> 146 <0x00058800 0x1f8>, /* PCS */
>> 147 <0x00058600 0x044>; /* PCS misc */
>> 148 #phy-cells = <0>;
>> 149 #clock-cells = <0>;
>> 150 clocks = <&gcc GCC_USB1_PIPE_CLK>;
>> 151 clock-names = "pipe0";
>> 152 clock-output-names = "usb3phy_1_cc_pipe_clk";
>> 153 };
148 }; 154 };
149 155
150 qusb_phy_1: phy@59000 { 156 qusb_phy_1: phy@59000 {
151 compatible = "qcom,ipq 157 compatible = "qcom,ipq8074-qusb2-phy";
152 reg = <0x00059000 0x18 158 reg = <0x00059000 0x180>;
153 #phy-cells = <0>; 159 #phy-cells = <0>;
154 160
155 clocks = <&gcc GCC_USB 161 clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
156 <&xo>; 162 <&xo>;
157 clock-names = "cfg_ahb 163 clock-names = "cfg_ahb", "ref";
158 164
159 resets = <&gcc GCC_QUS 165 resets = <&gcc GCC_QUSB2_1_PHY_BCR>;
160 status = "disabled"; 166 status = "disabled";
161 }; 167 };
162 168
163 ssphy_0: phy@78000 { 169 ssphy_0: phy@78000 {
164 compatible = "qcom,ipq 170 compatible = "qcom,ipq8074-qmp-usb3-phy";
165 reg = <0x00078000 0x10 !! 171 reg = <0x00078000 0x1c4>;
>> 172 #address-cells = <1>;
>> 173 #size-cells = <1>;
>> 174 ranges;
166 175
167 clocks = <&gcc GCC_USB 176 clocks = <&gcc GCC_USB0_AUX_CLK>,
168 <&xo>, !! 177 <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
169 <&gcc GCC_USB !! 178 <&xo>;
170 <&gcc GCC_USB !! 179 clock-names = "aux", "cfg_ahb", "ref";
171 clock-names = "aux", <<
172 "ref", <<
173 "cfg_ahb <<
174 "pipe"; <<
175 clock-output-names = " <<
176 #clock-cells = <0>; <<
177 #phy-cells = <0>; <<
178 180
179 resets = <&gcc GCC_USB 181 resets = <&gcc GCC_USB0_PHY_BCR>,
180 <&gcc GCC_USB !! 182 <&gcc GCC_USB3PHY_0_PHY_BCR>;
181 reset-names = "phy", !! 183 reset-names = "phy","common";
182 "phy_phy <<
183 <<
184 status = "disabled"; 184 status = "disabled";
>> 185
>> 186 usb0_ssphy: phy@78200 {
>> 187 reg = <0x00078200 0x130>, /* Tx */
>> 188 <0x00078400 0x200>, /* Rx */
>> 189 <0x00078800 0x1f8>, /* PCS */
>> 190 <0x00078600 0x044>; /* PCS misc */
>> 191 #phy-cells = <0>;
>> 192 #clock-cells = <0>;
>> 193 clocks = <&gcc GCC_USB0_PIPE_CLK>;
>> 194 clock-names = "pipe0";
>> 195 clock-output-names = "usb3phy_0_cc_pipe_clk";
>> 196 };
185 }; 197 };
186 198
187 qusb_phy_0: phy@79000 { 199 qusb_phy_0: phy@79000 {
188 compatible = "qcom,ipq 200 compatible = "qcom,ipq8074-qusb2-phy";
189 reg = <0x00079000 0x18 201 reg = <0x00079000 0x180>;
190 #phy-cells = <0>; 202 #phy-cells = <0>;
191 203
192 clocks = <&gcc GCC_USB 204 clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
193 <&xo>; 205 <&xo>;
194 clock-names = "cfg_ahb 206 clock-names = "cfg_ahb", "ref";
195 207
196 resets = <&gcc GCC_QUS 208 resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
197 status = "disabled"; 209 status = "disabled";
198 }; 210 };
199 211
200 pcie_qmp0: phy@84000 { 212 pcie_qmp0: phy@84000 {
201 compatible = "qcom,ipq 213 compatible = "qcom,ipq8074-qmp-gen3-pcie-phy";
202 reg = <0x00084000 0x10 214 reg = <0x00084000 0x1000>;
203 215
204 clocks = <&gcc GCC_PCI 216 clocks = <&gcc GCC_PCIE0_AUX_CLK>,
205 <&gcc GCC_PCI 217 <&gcc GCC_PCIE0_AHB_CLK>,
206 <&gcc GCC_PCI 218 <&gcc GCC_PCIE0_PIPE_CLK>;
207 clock-names = "aux", 219 clock-names = "aux",
208 "cfg_ahb 220 "cfg_ahb",
209 "pipe"; 221 "pipe";
210 222
211 clock-output-names = " 223 clock-output-names = "pcie20_phy0_pipe_clk";
212 #clock-cells = <0>; 224 #clock-cells = <0>;
213 225
214 #phy-cells = <0>; 226 #phy-cells = <0>;
215 227
216 resets = <&gcc GCC_PCI 228 resets = <&gcc GCC_PCIE0_PHY_BCR>,
217 <&gcc GCC_PCI 229 <&gcc GCC_PCIE0PHY_PHY_BCR>;
218 reset-names = "phy", 230 reset-names = "phy",
219 "common" 231 "common";
220 status = "disabled"; 232 status = "disabled";
221 }; 233 };
222 234
223 pcie_qmp1: phy@8e000 { 235 pcie_qmp1: phy@8e000 {
224 compatible = "qcom,ipq 236 compatible = "qcom,ipq8074-qmp-pcie-phy";
225 reg = <0x0008e000 0x10 237 reg = <0x0008e000 0x1000>;
226 238
227 clocks = <&gcc GCC_PCI 239 clocks = <&gcc GCC_PCIE1_AUX_CLK>,
228 <&gcc GCC_PCI 240 <&gcc GCC_PCIE1_AHB_CLK>,
229 <&gcc GCC_PCI 241 <&gcc GCC_PCIE1_PIPE_CLK>;
230 clock-names = "aux", 242 clock-names = "aux",
231 "cfg_ahb 243 "cfg_ahb",
232 "pipe"; 244 "pipe";
233 245
234 clock-output-names = " 246 clock-output-names = "pcie20_phy1_pipe_clk";
235 #clock-cells = <0>; 247 #clock-cells = <0>;
236 248
237 #phy-cells = <0>; 249 #phy-cells = <0>;
238 250
239 resets = <&gcc GCC_PCI 251 resets = <&gcc GCC_PCIE1_PHY_BCR>,
240 <&gcc GCC_PCI 252 <&gcc GCC_PCIE1PHY_PHY_BCR>;
241 reset-names = "phy", 253 reset-names = "phy",
242 "common" 254 "common";
243 status = "disabled"; 255 status = "disabled";
244 }; 256 };
245 257
246 mdio: mdio@90000 { 258 mdio: mdio@90000 {
247 compatible = "qcom,ipq 259 compatible = "qcom,ipq8074-mdio", "qcom,ipq4019-mdio";
248 reg = <0x00090000 0x64 260 reg = <0x00090000 0x64>;
249 #address-cells = <1>; 261 #address-cells = <1>;
250 #size-cells = <0>; 262 #size-cells = <0>;
251 263
252 clocks = <&gcc GCC_MDI 264 clocks = <&gcc GCC_MDIO_AHB_CLK>;
253 clock-names = "gcc_mdi 265 clock-names = "gcc_mdio_ahb_clk";
254 266
255 clock-frequency = <625 <<
256 <<
257 status = "disabled"; 267 status = "disabled";
258 }; 268 };
259 269
260 qfprom: efuse@a4000 { 270 qfprom: efuse@a4000 {
261 compatible = "qcom,ipq 271 compatible = "qcom,ipq8074-qfprom", "qcom,qfprom";
262 reg = <0x000a4000 0x20 272 reg = <0x000a4000 0x2000>;
263 #address-cells = <1>; 273 #address-cells = <1>;
264 #size-cells = <1>; 274 #size-cells = <1>;
265 }; 275 };
266 276
267 prng: rng@e3000 { 277 prng: rng@e3000 {
268 compatible = "qcom,prn 278 compatible = "qcom,prng-ee";
269 reg = <0x000e3000 0x10 279 reg = <0x000e3000 0x1000>;
270 clocks = <&gcc GCC_PRN 280 clocks = <&gcc GCC_PRNG_AHB_CLK>;
271 clock-names = "core"; 281 clock-names = "core";
272 status = "disabled"; 282 status = "disabled";
273 }; 283 };
274 284
275 tsens: thermal-sensor@4a9000 { 285 tsens: thermal-sensor@4a9000 {
276 compatible = "qcom,ipq 286 compatible = "qcom,ipq8074-tsens";
277 reg = <0x4a9000 0x1000 287 reg = <0x4a9000 0x1000>, /* TM */
278 <0x4a8000 0x1000 288 <0x4a8000 0x1000>; /* SROT */
279 interrupts = <GIC_SPI 289 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
280 interrupt-names = "com 290 interrupt-names = "combined";
281 #qcom,sensors = <16>; 291 #qcom,sensors = <16>;
282 #thermal-sensor-cells 292 #thermal-sensor-cells = <1>;
283 }; 293 };
284 294
285 cryptobam: dma-controller@7040 295 cryptobam: dma-controller@704000 {
286 compatible = "qcom,bam 296 compatible = "qcom,bam-v1.7.0";
287 reg = <0x00704000 0x20 297 reg = <0x00704000 0x20000>;
288 interrupts = <GIC_SPI 298 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
289 clocks = <&gcc GCC_CRY 299 clocks = <&gcc GCC_CRYPTO_AHB_CLK>;
290 clock-names = "bam_clk 300 clock-names = "bam_clk";
291 #dma-cells = <1>; 301 #dma-cells = <1>;
292 qcom,ee = <1>; 302 qcom,ee = <1>;
293 qcom,controlled-remote 303 qcom,controlled-remotely;
294 status = "disabled"; 304 status = "disabled";
295 }; 305 };
296 306
297 crypto: crypto@73a000 { 307 crypto: crypto@73a000 {
298 compatible = "qcom,cry 308 compatible = "qcom,crypto-v5.1";
299 reg = <0x0073a000 0x60 309 reg = <0x0073a000 0x6000>;
300 clocks = <&gcc GCC_CRY 310 clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
301 <&gcc GCC_CRY 311 <&gcc GCC_CRYPTO_AXI_CLK>,
302 <&gcc GCC_CRY 312 <&gcc GCC_CRYPTO_CLK>;
303 clock-names = "iface", 313 clock-names = "iface", "bus", "core";
304 dmas = <&cryptobam 2>, 314 dmas = <&cryptobam 2>, <&cryptobam 3>;
305 dma-names = "rx", "tx" 315 dma-names = "rx", "tx";
306 status = "disabled"; 316 status = "disabled";
307 }; 317 };
308 318
309 tlmm: pinctrl@1000000 { 319 tlmm: pinctrl@1000000 {
310 compatible = "qcom,ipq 320 compatible = "qcom,ipq8074-pinctrl";
311 reg = <0x01000000 0x30 321 reg = <0x01000000 0x300000>;
312 interrupts = <GIC_SPI 322 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
313 gpio-controller; 323 gpio-controller;
314 gpio-ranges = <&tlmm 0 324 gpio-ranges = <&tlmm 0 0 70>;
315 #gpio-cells = <2>; 325 #gpio-cells = <2>;
316 interrupt-controller; 326 interrupt-controller;
317 #interrupt-cells = <2> 327 #interrupt-cells = <2>;
318 328
319 serial_4_pins: serial4 329 serial_4_pins: serial4-state {
320 pins = "gpio23 330 pins = "gpio23", "gpio24";
321 function = "bl 331 function = "blsp4_uart1";
322 drive-strength 332 drive-strength = <8>;
323 bias-disable; 333 bias-disable;
324 }; 334 };
325 335
326 serial_5_pins: serial5 <<
327 pins = "gpio9" <<
328 function = "bl <<
329 drive-strength <<
330 bias-disable; <<
331 }; <<
332 <<
333 i2c_0_pins: i2c-0-stat 336 i2c_0_pins: i2c-0-state {
334 pins = "gpio42 337 pins = "gpio42", "gpio43";
335 function = "bl 338 function = "blsp1_i2c";
336 drive-strength 339 drive-strength = <8>;
337 bias-disable; 340 bias-disable;
338 }; 341 };
339 342
340 spi_0_pins: spi-0-stat 343 spi_0_pins: spi-0-state {
341 pins = "gpio38 344 pins = "gpio38", "gpio39", "gpio40", "gpio41";
342 function = "bl 345 function = "blsp0_spi";
343 drive-strength 346 drive-strength = <8>;
344 bias-disable; 347 bias-disable;
345 }; 348 };
346 349
347 hsuart_pins: hsuart-st 350 hsuart_pins: hsuart-state {
348 pins = "gpio46 351 pins = "gpio46", "gpio47", "gpio48", "gpio49";
349 function = "bl 352 function = "blsp2_uart";
350 drive-strength 353 drive-strength = <8>;
351 bias-disable; 354 bias-disable;
352 }; 355 };
353 356
354 qpic_pins: qpic-state 357 qpic_pins: qpic-state {
355 pins = "gpio1" 358 pins = "gpio1", "gpio3", "gpio4",
356 "gpio5" 359 "gpio5", "gpio6", "gpio7",
357 "gpio8" 360 "gpio8", "gpio10", "gpio11",
358 "gpio12 361 "gpio12", "gpio13", "gpio14",
359 "gpio15 !! 362 "gpio15", "gpio16", "gpio17";
360 function = "qp 363 function = "qpic";
361 drive-strength 364 drive-strength = <8>;
362 bias-disable; 365 bias-disable;
363 }; 366 };
364 }; 367 };
365 368
366 gcc: clock-controller@1800000 !! 369 gcc: gcc@1800000 {
367 compatible = "qcom,gcc 370 compatible = "qcom,gcc-ipq8074";
368 reg = <0x01800000 0x80 371 reg = <0x01800000 0x80000>;
369 clocks = <&xo>, !! 372 clocks = <&xo>, <&sleep_clk>;
370 <&sleep_clk>, !! 373 clock-names = "xo", "sleep_clk";
371 <&pcie_qmp0>, <<
372 <&pcie_qmp1>; <<
373 clock-names = "xo", <<
374 "sleep_c <<
375 "pcie0_p <<
376 "pcie1_p <<
377 #clock-cells = <1>; 374 #clock-cells = <1>;
378 #power-domain-cells = 375 #power-domain-cells = <1>;
379 #reset-cells = <1>; 376 #reset-cells = <1>;
380 }; 377 };
381 378
382 tcsr_mutex: hwlock@1905000 { 379 tcsr_mutex: hwlock@1905000 {
383 compatible = "qcom,tcs 380 compatible = "qcom,tcsr-mutex";
384 reg = <0x01905000 0x20 381 reg = <0x01905000 0x20000>;
385 #hwlock-cells = <1>; 382 #hwlock-cells = <1>;
386 }; 383 };
387 384
388 tcsr: syscon@1937000 { 385 tcsr: syscon@1937000 {
389 compatible = "qcom,tcs 386 compatible = "qcom,tcsr-ipq8074", "syscon";
390 reg = <0x01937000 0x21 387 reg = <0x01937000 0x21000>;
391 }; 388 };
392 389
393 spmi_bus: spmi@200f000 { 390 spmi_bus: spmi@200f000 {
394 compatible = "qcom,spm 391 compatible = "qcom,spmi-pmic-arb";
395 reg = <0x0200f000 0x00 392 reg = <0x0200f000 0x001000>,
396 <0x02400000 0x80 393 <0x02400000 0x800000>,
397 <0x02c00000 0x80 394 <0x02c00000 0x800000>,
398 <0x03800000 0x20 395 <0x03800000 0x200000>,
399 <0x0200a000 0x00 396 <0x0200a000 0x000700>;
400 reg-names = "core", "c 397 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
401 interrupts = <GIC_SPI 398 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
402 interrupt-names = "per 399 interrupt-names = "periph_irq";
403 qcom,ee = <0>; 400 qcom,ee = <0>;
404 qcom,channel = <0>; 401 qcom,channel = <0>;
405 #address-cells = <2>; 402 #address-cells = <2>;
406 #size-cells = <0>; 403 #size-cells = <0>;
407 interrupt-controller; 404 interrupt-controller;
408 #interrupt-cells = <4> 405 #interrupt-cells = <4>;
409 }; 406 };
410 407
411 sdhc_1: mmc@7824900 { 408 sdhc_1: mmc@7824900 {
412 compatible = "qcom,ipq !! 409 compatible = "qcom,sdhci-msm-v4";
413 reg = <0x7824900 0x500 410 reg = <0x7824900 0x500>, <0x7824000 0x800>;
414 reg-names = "hc", "cor 411 reg-names = "hc", "core";
415 412
416 interrupts = <GIC_SPI 413 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
417 <GIC_SPI 414 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
418 interrupt-names = "hc_ 415 interrupt-names = "hc_irq", "pwr_irq";
419 416
420 clocks = <&gcc GCC_SDC 417 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
421 <&gcc GCC_SDC 418 <&gcc GCC_SDCC1_APPS_CLK>,
422 <&xo>; 419 <&xo>;
423 clock-names = "iface", 420 clock-names = "iface", "core", "xo";
424 resets = <&gcc GCC_SDC 421 resets = <&gcc GCC_SDCC1_BCR>;
425 max-frequency = <38400 422 max-frequency = <384000000>;
426 mmc-ddr-1_8v; 423 mmc-ddr-1_8v;
427 mmc-hs200-1_8v; 424 mmc-hs200-1_8v;
428 mmc-hs400-1_8v; 425 mmc-hs400-1_8v;
429 bus-width = <8>; 426 bus-width = <8>;
430 427
431 status = "disabled"; 428 status = "disabled";
432 }; 429 };
433 430
434 blsp_dma: dma-controller@78840 431 blsp_dma: dma-controller@7884000 {
435 compatible = "qcom,bam 432 compatible = "qcom,bam-v1.7.0";
436 reg = <0x07884000 0x2b 433 reg = <0x07884000 0x2b000>;
437 interrupts = <GIC_SPI 434 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
438 clocks = <&gcc GCC_BLS 435 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
439 clock-names = "bam_clk 436 clock-names = "bam_clk";
440 #dma-cells = <1>; 437 #dma-cells = <1>;
441 qcom,ee = <0>; 438 qcom,ee = <0>;
442 }; 439 };
443 440
444 blsp1_uart1: serial@78af000 { 441 blsp1_uart1: serial@78af000 {
445 compatible = "qcom,msm 442 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
446 reg = <0x078af000 0x20 443 reg = <0x078af000 0x200>;
447 interrupts = <GIC_SPI 444 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
448 clocks = <&gcc GCC_BLS 445 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
449 <&gcc GCC_BLS 446 <&gcc GCC_BLSP1_AHB_CLK>;
450 clock-names = "core", 447 clock-names = "core", "iface";
451 status = "disabled"; 448 status = "disabled";
452 }; 449 };
453 450
454 blsp1_uart3: serial@78b1000 { 451 blsp1_uart3: serial@78b1000 {
455 compatible = "qcom,msm 452 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
456 reg = <0x078b1000 0x20 453 reg = <0x078b1000 0x200>;
457 interrupts = <GIC_SPI 454 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
458 clocks = <&gcc GCC_BLS 455 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
459 <&gcc GCC_BLSP 456 <&gcc GCC_BLSP1_AHB_CLK>;
460 clock-names = "core", 457 clock-names = "core", "iface";
461 dmas = <&blsp_dma 4>, 458 dmas = <&blsp_dma 4>,
462 <&blsp_dma 5>; 459 <&blsp_dma 5>;
463 dma-names = "tx", "rx" 460 dma-names = "tx", "rx";
464 pinctrl-0 = <&hsuart_p 461 pinctrl-0 = <&hsuart_pins>;
465 pinctrl-names = "defau 462 pinctrl-names = "default";
466 status = "disabled"; 463 status = "disabled";
467 }; 464 };
468 465
469 blsp1_uart5: serial@78b3000 { 466 blsp1_uart5: serial@78b3000 {
470 compatible = "qcom,msm 467 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
471 reg = <0x078b3000 0x20 468 reg = <0x078b3000 0x200>;
472 interrupts = <GIC_SPI 469 interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
473 clocks = <&gcc GCC_BLS 470 clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>,
474 <&gcc GCC_BLS 471 <&gcc GCC_BLSP1_AHB_CLK>;
475 clock-names = "core", 472 clock-names = "core", "iface";
476 pinctrl-0 = <&serial_4 473 pinctrl-0 = <&serial_4_pins>;
477 pinctrl-names = "defau 474 pinctrl-names = "default";
478 status = "disabled"; 475 status = "disabled";
479 }; 476 };
480 477
481 blsp1_uart6: serial@78b4000 { <<
482 compatible = "qcom,msm <<
483 reg = <0x078b4000 0x20 <<
484 interrupts = <GIC_SPI <<
485 clocks = <&gcc GCC_BLS <<
486 <&gcc GCC_BLS <<
487 clock-names = "core", <<
488 pinctrl-0 = <&serial_5 <<
489 pinctrl-names = "defau <<
490 status = "disabled"; <<
491 }; <<
492 <<
493 blsp1_spi1: spi@78b5000 { 478 blsp1_spi1: spi@78b5000 {
494 compatible = "qcom,spi 479 compatible = "qcom,spi-qup-v2.2.1";
495 #address-cells = <1>; 480 #address-cells = <1>;
496 #size-cells = <0>; 481 #size-cells = <0>;
497 reg = <0x078b5000 0x60 482 reg = <0x078b5000 0x600>;
498 interrupts = <GIC_SPI 483 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
499 clocks = <&gcc GCC_BLS 484 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
500 <&gcc GCC_BLSP 485 <&gcc GCC_BLSP1_AHB_CLK>;
501 clock-names = "core", 486 clock-names = "core", "iface";
502 dmas = <&blsp_dma 12>, 487 dmas = <&blsp_dma 12>, <&blsp_dma 13>;
503 dma-names = "tx", "rx" 488 dma-names = "tx", "rx";
504 pinctrl-0 = <&spi_0_pi 489 pinctrl-0 = <&spi_0_pins>;
505 pinctrl-names = "defau 490 pinctrl-names = "default";
506 status = "disabled"; 491 status = "disabled";
507 }; 492 };
508 493
509 blsp1_i2c2: i2c@78b6000 { 494 blsp1_i2c2: i2c@78b6000 {
510 compatible = "qcom,i2c 495 compatible = "qcom,i2c-qup-v2.2.1";
511 #address-cells = <1>; 496 #address-cells = <1>;
512 #size-cells = <0>; 497 #size-cells = <0>;
513 reg = <0x078b6000 0x60 498 reg = <0x078b6000 0x600>;
514 interrupts = <GIC_SPI 499 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
515 clocks = <&gcc GCC_BLS 500 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
516 <&gcc GCC_BLS 501 <&gcc GCC_BLSP1_AHB_CLK>;
517 clock-names = "core", 502 clock-names = "core", "iface";
518 clock-frequency = <400 503 clock-frequency = <400000>;
519 dmas = <&blsp_dma 14>, 504 dmas = <&blsp_dma 14>, <&blsp_dma 15>;
520 dma-names = "tx", "rx" 505 dma-names = "tx", "rx";
521 pinctrl-0 = <&i2c_0_pi 506 pinctrl-0 = <&i2c_0_pins>;
522 pinctrl-names = "defau 507 pinctrl-names = "default";
523 status = "disabled"; 508 status = "disabled";
524 }; 509 };
525 510
526 blsp1_i2c3: i2c@78b7000 { 511 blsp1_i2c3: i2c@78b7000 {
527 compatible = "qcom,i2c 512 compatible = "qcom,i2c-qup-v2.2.1";
528 #address-cells = <1>; 513 #address-cells = <1>;
529 #size-cells = <0>; 514 #size-cells = <0>;
530 reg = <0x078b7000 0x60 515 reg = <0x078b7000 0x600>;
531 interrupts = <GIC_SPI 516 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
532 clocks = <&gcc GCC_BLS 517 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
533 <&gcc GCC_BLS 518 <&gcc GCC_BLSP1_AHB_CLK>;
534 clock-names = "core", 519 clock-names = "core", "iface";
535 clock-frequency = <100 520 clock-frequency = <100000>;
536 dmas = <&blsp_dma 16>, 521 dmas = <&blsp_dma 16>, <&blsp_dma 17>;
537 dma-names = "tx", "rx" 522 dma-names = "tx", "rx";
538 status = "disabled"; 523 status = "disabled";
539 }; 524 };
540 525
541 blsp1_spi4: spi@78b8000 { <<
542 compatible = "qcom,spi <<
543 #address-cells = <1>; <<
544 #size-cells = <0>; <<
545 reg = <0x78b8000 0x600 <<
546 interrupts = <GIC_SPI <<
547 clocks = <&gcc GCC_BLS <<
548 <&gcc GCC_BLS <<
549 clock-names = "core", <<
550 dmas = <&blsp_dma 18>, <<
551 dma-names = "tx", "rx" <<
552 status = "disabled"; <<
553 }; <<
554 <<
555 blsp1_i2c5: i2c@78b9000 { 526 blsp1_i2c5: i2c@78b9000 {
556 compatible = "qcom,i2c 527 compatible = "qcom,i2c-qup-v2.2.1";
557 #address-cells = <1>; 528 #address-cells = <1>;
558 #size-cells = <0>; 529 #size-cells = <0>;
559 reg = <0x78b9000 0x600 530 reg = <0x78b9000 0x600>;
560 interrupts = <GIC_SPI 531 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
561 clocks = <&gcc GCC_BLS 532 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
562 <&gcc GCC_BLS 533 <&gcc GCC_BLSP1_AHB_CLK>;
563 clock-names = "core", 534 clock-names = "core", "iface";
564 clock-frequency = <400 535 clock-frequency = <400000>;
565 dmas = <&blsp_dma 20>, 536 dmas = <&blsp_dma 20>, <&blsp_dma 21>;
566 dma-names = "tx", "rx" 537 dma-names = "tx", "rx";
567 status = "disabled"; 538 status = "disabled";
568 }; 539 };
569 540
570 blsp1_spi5: spi@78b9000 { 541 blsp1_spi5: spi@78b9000 {
571 compatible = "qcom,spi 542 compatible = "qcom,spi-qup-v2.2.1";
572 #address-cells = <1>; 543 #address-cells = <1>;
573 #size-cells = <0>; 544 #size-cells = <0>;
574 reg = <0x78b9000 0x600 545 reg = <0x78b9000 0x600>;
575 interrupts = <GIC_SPI 546 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
576 clocks = <&gcc GCC_BLS 547 clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
577 <&gcc GCC_BLS 548 <&gcc GCC_BLSP1_AHB_CLK>;
578 clock-names = "core", 549 clock-names = "core", "iface";
579 dmas = <&blsp_dma 20>, 550 dmas = <&blsp_dma 20>, <&blsp_dma 21>;
580 dma-names = "tx", "rx" 551 dma-names = "tx", "rx";
581 status = "disabled"; 552 status = "disabled";
582 }; 553 };
583 554
584 blsp1_i2c6: i2c@78ba000 { 555 blsp1_i2c6: i2c@78ba000 {
585 compatible = "qcom,i2c 556 compatible = "qcom,i2c-qup-v2.2.1";
586 #address-cells = <1>; 557 #address-cells = <1>;
587 #size-cells = <0>; 558 #size-cells = <0>;
588 reg = <0x078ba000 0x60 559 reg = <0x078ba000 0x600>;
589 interrupts = <GIC_SPI 560 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
590 clocks = <&gcc GCC_BLS 561 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
591 <&gcc GCC_BLS 562 <&gcc GCC_BLSP1_AHB_CLK>;
592 clock-names = "core", 563 clock-names = "core", "iface";
593 clock-frequency = <100 564 clock-frequency = <100000>;
594 dmas = <&blsp_dma 22>, 565 dmas = <&blsp_dma 22>, <&blsp_dma 23>;
595 dma-names = "tx", "rx" 566 dma-names = "tx", "rx";
596 status = "disabled"; 567 status = "disabled";
597 }; 568 };
598 569
599 qpic_bam: dma-controller@79840 570 qpic_bam: dma-controller@7984000 {
600 compatible = "qcom,bam 571 compatible = "qcom,bam-v1.7.0";
601 reg = <0x07984000 0x1a 572 reg = <0x07984000 0x1a000>;
602 interrupts = <GIC_SPI 573 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
603 clocks = <&gcc GCC_QPI 574 clocks = <&gcc GCC_QPIC_AHB_CLK>;
604 clock-names = "bam_clk 575 clock-names = "bam_clk";
605 #dma-cells = <1>; 576 #dma-cells = <1>;
606 qcom,ee = <0>; 577 qcom,ee = <0>;
607 status = "disabled"; 578 status = "disabled";
608 }; 579 };
609 580
610 qpic_nand: nand-controller@79b 581 qpic_nand: nand-controller@79b0000 {
611 compatible = "qcom,ipq 582 compatible = "qcom,ipq8074-nand";
612 reg = <0x079b0000 0x10 583 reg = <0x079b0000 0x10000>;
613 #address-cells = <1>; 584 #address-cells = <1>;
614 #size-cells = <0>; 585 #size-cells = <0>;
615 clocks = <&gcc GCC_QPI 586 clocks = <&gcc GCC_QPIC_CLK>,
616 <&gcc GCC_QPI 587 <&gcc GCC_QPIC_AHB_CLK>;
617 clock-names = "core", 588 clock-names = "core", "aon";
618 589
619 dmas = <&qpic_bam 0>, 590 dmas = <&qpic_bam 0>,
620 <&qpic_bam 1>, 591 <&qpic_bam 1>,
621 <&qpic_bam 2>; 592 <&qpic_bam 2>;
622 dma-names = "tx", "rx" 593 dma-names = "tx", "rx", "cmd";
623 pinctrl-0 = <&qpic_pin 594 pinctrl-0 = <&qpic_pins>;
624 pinctrl-names = "defau 595 pinctrl-names = "default";
625 status = "disabled"; 596 status = "disabled";
626 }; 597 };
627 598
628 usb_0: usb@8af8800 { 599 usb_0: usb@8af8800 {
629 compatible = "qcom,ipq 600 compatible = "qcom,ipq8074-dwc3", "qcom,dwc3";
630 reg = <0x08af8800 0x40 601 reg = <0x08af8800 0x400>;
631 #address-cells = <1>; 602 #address-cells = <1>;
632 #size-cells = <1>; 603 #size-cells = <1>;
633 ranges; 604 ranges;
634 605
635 clocks = <&gcc GCC_SYS 606 clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
636 <&gcc GCC_USB0 607 <&gcc GCC_USB0_MASTER_CLK>,
637 <&gcc GCC_USB0 608 <&gcc GCC_USB0_SLEEP_CLK>,
638 <&gcc GCC_USB0 609 <&gcc GCC_USB0_MOCK_UTMI_CLK>;
639 clock-names = "cfg_noc 610 clock-names = "cfg_noc",
640 "core", 611 "core",
641 "sleep", 612 "sleep",
642 "mock_utmi"; 613 "mock_utmi";
643 614
644 assigned-clocks = <&gc 615 assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
645 <&gc 616 <&gcc GCC_USB0_MASTER_CLK>,
646 <&gc 617 <&gcc GCC_USB0_MOCK_UTMI_CLK>;
647 assigned-clock-rates = 618 assigned-clock-rates = <133330000>,
648 619 <133330000>,
649 620 <19200000>;
650 621
651 interrupts = <GIC_SPI <<
652 <GIC_SPI <<
653 <GIC_SPI <<
654 interrupt-names = "pwr <<
655 "qus <<
656 "ss_ <<
657 <<
658 power-domains = <&gcc 622 power-domains = <&gcc USB0_GDSC>;
659 623
660 resets = <&gcc GCC_USB 624 resets = <&gcc GCC_USB0_BCR>;
661 status = "disabled"; 625 status = "disabled";
662 626
663 dwc_0: usb@8a00000 { 627 dwc_0: usb@8a00000 {
664 compatible = " 628 compatible = "snps,dwc3";
665 reg = <0x8a000 629 reg = <0x8a00000 0xcd00>;
666 interrupts = < 630 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
667 phys = <&qusb_ !! 631 phys = <&qusb_phy_0>, <&usb0_ssphy>;
668 phy-names = "u 632 phy-names = "usb2-phy", "usb3-phy";
669 snps,parkmode- <<
670 snps,is-utmi-l 633 snps,is-utmi-l1-suspend;
671 snps,hird-thre 634 snps,hird-threshold = /bits/ 8 <0x0>;
672 snps,dis_u2_su 635 snps,dis_u2_susphy_quirk;
673 snps,dis_u3_su 636 snps,dis_u3_susphy_quirk;
674 dr_mode = "hos 637 dr_mode = "host";
675 }; 638 };
676 }; 639 };
677 640
678 usb_1: usb@8cf8800 { 641 usb_1: usb@8cf8800 {
679 compatible = "qcom,ipq 642 compatible = "qcom,ipq8074-dwc3", "qcom,dwc3";
680 reg = <0x08cf8800 0x40 643 reg = <0x08cf8800 0x400>;
681 #address-cells = <1>; 644 #address-cells = <1>;
682 #size-cells = <1>; 645 #size-cells = <1>;
683 ranges; 646 ranges;
684 647
685 clocks = <&gcc GCC_SYS 648 clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>,
686 <&gcc GCC_USB1 649 <&gcc GCC_USB1_MASTER_CLK>,
687 <&gcc GCC_USB1 650 <&gcc GCC_USB1_SLEEP_CLK>,
688 <&gcc GCC_USB1 651 <&gcc GCC_USB1_MOCK_UTMI_CLK>;
689 clock-names = "cfg_noc 652 clock-names = "cfg_noc",
690 "core", 653 "core",
691 "sleep", 654 "sleep",
692 "mock_utmi"; 655 "mock_utmi";
693 656
694 assigned-clocks = <&gc 657 assigned-clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>,
695 <&gc 658 <&gcc GCC_USB1_MASTER_CLK>,
696 <&gc 659 <&gcc GCC_USB1_MOCK_UTMI_CLK>;
697 assigned-clock-rates = 660 assigned-clock-rates = <133330000>,
698 661 <133330000>,
699 662 <19200000>;
700 663
701 interrupts = <GIC_SPI <<
702 <GIC_SPI <<
703 <GIC_SPI <<
704 interrupt-names = "pwr <<
705 "qus <<
706 "ss_ <<
707 <<
708 power-domains = <&gcc 664 power-domains = <&gcc USB1_GDSC>;
709 665
710 resets = <&gcc GCC_USB 666 resets = <&gcc GCC_USB1_BCR>;
711 status = "disabled"; 667 status = "disabled";
712 668
713 dwc_1: usb@8c00000 { 669 dwc_1: usb@8c00000 {
714 compatible = " 670 compatible = "snps,dwc3";
715 reg = <0x8c000 671 reg = <0x8c00000 0xcd00>;
716 interrupts = < 672 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
717 phys = <&qusb_ !! 673 phys = <&qusb_phy_1>, <&usb1_ssphy>;
718 phy-names = "u 674 phy-names = "usb2-phy", "usb3-phy";
719 snps,parkmode- <<
720 snps,is-utmi-l 675 snps,is-utmi-l1-suspend;
721 snps,hird-thre 676 snps,hird-threshold = /bits/ 8 <0x0>;
722 snps,dis_u2_su 677 snps,dis_u2_susphy_quirk;
723 snps,dis_u3_su 678 snps,dis_u3_susphy_quirk;
724 dr_mode = "hos 679 dr_mode = "host";
725 }; 680 };
726 }; 681 };
727 682
728 intc: interrupt-controller@b00 683 intc: interrupt-controller@b000000 {
729 compatible = "qcom,msm 684 compatible = "qcom,msm-qgic2";
730 #address-cells = <1>; 685 #address-cells = <1>;
731 #size-cells = <1>; 686 #size-cells = <1>;
732 interrupt-controller; 687 interrupt-controller;
733 #interrupt-cells = <3> 688 #interrupt-cells = <3>;
734 reg = <0x0b000000 0x10 689 reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
735 ranges = <0 0xb00a000 690 ranges = <0 0xb00a000 0xffd>;
736 691
737 v2m@0 { 692 v2m@0 {
738 compatible = " 693 compatible = "arm,gic-v2m-frame";
739 msi-controller 694 msi-controller;
740 reg = <0x0 0xf 695 reg = <0x0 0xffd>;
741 }; 696 };
742 }; 697 };
743 698
744 watchdog: watchdog@b017000 { 699 watchdog: watchdog@b017000 {
745 compatible = "qcom,kps 700 compatible = "qcom,kpss-wdt";
746 reg = <0xb017000 0x100 701 reg = <0xb017000 0x1000>;
747 interrupts = <GIC_SPI 702 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
748 clocks = <&sleep_clk>; 703 clocks = <&sleep_clk>;
749 timeout-sec = <30>; 704 timeout-sec = <30>;
750 }; 705 };
751 706
752 apcs_glb: mailbox@b111000 { 707 apcs_glb: mailbox@b111000 {
753 compatible = "qcom,ipq 708 compatible = "qcom,ipq8074-apcs-apps-global",
754 "qcom,ipq 709 "qcom,ipq6018-apcs-apps-global";
755 reg = <0x0b111000 0x10 710 reg = <0x0b111000 0x1000>;
756 clocks = <&a53pll>, <& !! 711 clocks = <&a53pll>, <&xo>;
757 clock-names = "pll", " !! 712 clock-names = "pll", "xo";
758 713
759 #clock-cells = <1>; 714 #clock-cells = <1>;
760 #mbox-cells = <1>; 715 #mbox-cells = <1>;
761 }; 716 };
762 717
763 a53pll: clock@b116000 { 718 a53pll: clock@b116000 {
764 compatible = "qcom,ipq 719 compatible = "qcom,ipq8074-a53pll";
765 reg = <0x0b116000 0x40 720 reg = <0x0b116000 0x40>;
766 #clock-cells = <0>; 721 #clock-cells = <0>;
767 clocks = <&xo>; 722 clocks = <&xo>;
768 clock-names = "xo"; 723 clock-names = "xo";
769 }; 724 };
770 725
771 timer@b120000 { 726 timer@b120000 {
772 #address-cells = <1>; 727 #address-cells = <1>;
773 #size-cells = <1>; 728 #size-cells = <1>;
774 ranges; 729 ranges;
775 compatible = "arm,armv 730 compatible = "arm,armv7-timer-mem";
776 reg = <0x0b120000 0x10 731 reg = <0x0b120000 0x1000>;
777 732
778 frame@b120000 { 733 frame@b120000 {
779 frame-number = 734 frame-number = <0>;
780 interrupts = < 735 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
781 < 736 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
782 reg = <0x0b121 737 reg = <0x0b121000 0x1000>,
783 <0x0b122 738 <0x0b122000 0x1000>;
784 }; 739 };
785 740
786 frame@b123000 { 741 frame@b123000 {
787 frame-number = 742 frame-number = <1>;
788 interrupts = < 743 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
789 reg = <0x0b123 744 reg = <0x0b123000 0x1000>;
790 status = "disa 745 status = "disabled";
791 }; 746 };
792 747
793 frame@b124000 { 748 frame@b124000 {
794 frame-number = 749 frame-number = <2>;
795 interrupts = < 750 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
796 reg = <0x0b124 751 reg = <0x0b124000 0x1000>;
797 status = "disa 752 status = "disabled";
798 }; 753 };
799 754
800 frame@b125000 { 755 frame@b125000 {
801 frame-number = 756 frame-number = <3>;
802 interrupts = < 757 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
803 reg = <0x0b125 758 reg = <0x0b125000 0x1000>;
804 status = "disa 759 status = "disabled";
805 }; 760 };
806 761
807 frame@b126000 { 762 frame@b126000 {
808 frame-number = 763 frame-number = <4>;
809 interrupts = < 764 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
810 reg = <0x0b126 765 reg = <0x0b126000 0x1000>;
811 status = "disa 766 status = "disabled";
812 }; 767 };
813 768
814 frame@b127000 { 769 frame@b127000 {
815 frame-number = 770 frame-number = <5>;
816 interrupts = < 771 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
817 reg = <0x0b127 772 reg = <0x0b127000 0x1000>;
818 status = "disa 773 status = "disabled";
819 }; 774 };
820 775
821 frame@b128000 { 776 frame@b128000 {
822 frame-number = 777 frame-number = <6>;
823 interrupts = < 778 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
824 reg = <0x0b128 779 reg = <0x0b128000 0x1000>;
825 status = "disa 780 status = "disabled";
826 }; 781 };
827 }; 782 };
828 783
829 pcie1: pcie@10000000 { !! 784 pcie1: pci@10000000 {
830 compatible = "qcom,pci 785 compatible = "qcom,pcie-ipq8074";
831 reg = <0x10000000 0xf1 786 reg = <0x10000000 0xf1d>,
832 <0x10000f20 0xa8 787 <0x10000f20 0xa8>,
833 <0x00088000 0x20 788 <0x00088000 0x2000>,
834 <0x10100000 0x10 789 <0x10100000 0x1000>;
835 reg-names = "dbi", "el 790 reg-names = "dbi", "elbi", "parf", "config";
836 device_type = "pci"; 791 device_type = "pci";
837 linux,pci-domain = <1> 792 linux,pci-domain = <1>;
838 bus-range = <0x00 0xff 793 bus-range = <0x00 0xff>;
839 num-lanes = <1>; 794 num-lanes = <1>;
840 max-link-speed = <2>; 795 max-link-speed = <2>;
841 #address-cells = <3>; 796 #address-cells = <3>;
842 #size-cells = <2>; 797 #size-cells = <2>;
843 798
844 phys = <&pcie_qmp1>; 799 phys = <&pcie_qmp1>;
845 phy-names = "pciephy"; 800 phy-names = "pciephy";
846 801
847 ranges = <0x81000000 0 802 ranges = <0x81000000 0x0 0x00000000 0x10200000 0x0 0x10000>, /* I/O */
848 <0x82000000 0 803 <0x82000000 0x0 0x10220000 0x10220000 0x0 0xfde0000>; /* MEM */
849 804
850 interrupts = <GIC_SPI 805 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
851 interrupt-names = "msi 806 interrupt-names = "msi";
852 #interrupt-cells = <1> 807 #interrupt-cells = <1>;
853 interrupt-map-mask = < 808 interrupt-map-mask = <0 0 0 0x7>;
854 interrupt-map = <0 0 0 809 interrupt-map = <0 0 0 1 &intc 0 0 142
855 IRQ_T 810 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
856 <0 0 0 811 <0 0 0 2 &intc 0 0 143
857 IRQ_T 812 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
858 <0 0 0 813 <0 0 0 3 &intc 0 0 144
859 IRQ_T 814 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
860 <0 0 0 815 <0 0 0 4 &intc 0 0 145
861 IRQ_T 816 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
862 817
863 clocks = <&gcc GCC_SYS 818 clocks = <&gcc GCC_SYS_NOC_PCIE1_AXI_CLK>,
864 <&gcc GCC_PCI 819 <&gcc GCC_PCIE1_AXI_M_CLK>,
865 <&gcc GCC_PCI 820 <&gcc GCC_PCIE1_AXI_S_CLK>,
866 <&gcc GCC_PCI 821 <&gcc GCC_PCIE1_AHB_CLK>,
867 <&gcc GCC_PCI 822 <&gcc GCC_PCIE1_AUX_CLK>;
868 clock-names = "iface", 823 clock-names = "iface",
869 "axi_m", 824 "axi_m",
870 "axi_s", 825 "axi_s",
871 "ahb", 826 "ahb",
872 "aux"; 827 "aux";
873 resets = <&gcc GCC_PCI 828 resets = <&gcc GCC_PCIE1_PIPE_ARES>,
874 <&gcc GCC_PCI 829 <&gcc GCC_PCIE1_SLEEP_ARES>,
875 <&gcc GCC_PCI 830 <&gcc GCC_PCIE1_CORE_STICKY_ARES>,
876 <&gcc GCC_PCI 831 <&gcc GCC_PCIE1_AXI_MASTER_ARES>,
877 <&gcc GCC_PCI 832 <&gcc GCC_PCIE1_AXI_SLAVE_ARES>,
878 <&gcc GCC_PCI 833 <&gcc GCC_PCIE1_AHB_ARES>,
879 <&gcc GCC_PCI 834 <&gcc GCC_PCIE1_AXI_MASTER_STICKY_ARES>;
880 reset-names = "pipe", 835 reset-names = "pipe",
881 "sleep", 836 "sleep",
882 "sticky" 837 "sticky",
883 "axi_m", 838 "axi_m",
884 "axi_s", 839 "axi_s",
885 "ahb", 840 "ahb",
886 "axi_m_s 841 "axi_m_sticky";
887 status = "disabled"; 842 status = "disabled";
888 <<
889 pcie@0 { <<
890 device_type = <<
891 reg = <0x0 0x0 <<
892 bus-range = <0 <<
893 <<
894 #address-cells <<
895 #size-cells = <<
896 ranges; <<
897 }; <<
898 }; 843 };
899 844
900 pcie0: pcie@20000000 { !! 845 pcie0: pci@20000000 {
901 compatible = "qcom,pci 846 compatible = "qcom,pcie-ipq8074-gen3";
902 reg = <0x20000000 0xf1 847 reg = <0x20000000 0xf1d>,
903 <0x20000f20 0xa8 848 <0x20000f20 0xa8>,
904 <0x20001000 0x10 849 <0x20001000 0x1000>,
905 <0x00080000 0x40 850 <0x00080000 0x4000>,
906 <0x20100000 0x10 851 <0x20100000 0x1000>;
907 reg-names = "dbi", "el 852 reg-names = "dbi", "elbi", "atu", "parf", "config";
908 device_type = "pci"; 853 device_type = "pci";
909 linux,pci-domain = <0> 854 linux,pci-domain = <0>;
910 bus-range = <0x00 0xff 855 bus-range = <0x00 0xff>;
911 num-lanes = <1>; 856 num-lanes = <1>;
912 max-link-speed = <3>; 857 max-link-speed = <3>;
913 #address-cells = <3>; 858 #address-cells = <3>;
914 #size-cells = <2>; 859 #size-cells = <2>;
915 860
916 phys = <&pcie_qmp0>; 861 phys = <&pcie_qmp0>;
917 phy-names = "pciephy"; 862 phy-names = "pciephy";
918 863
919 ranges = <0x81000000 0 864 ranges = <0x81000000 0x0 0x00000000 0x20200000 0x0 0x10000>, /* I/O */
920 <0x82000000 0 865 <0x82000000 0x0 0x20220000 0x20220000 0x0 0xfde0000>; /* MEM */
921 866
922 interrupts = <GIC_SPI 867 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
923 interrupt-names = "msi 868 interrupt-names = "msi";
924 #interrupt-cells = <1> 869 #interrupt-cells = <1>;
925 interrupt-map-mask = < 870 interrupt-map-mask = <0 0 0 0x7>;
926 interrupt-map = <0 0 0 871 interrupt-map = <0 0 0 1 &intc 0 0 75
927 IRQ_T 872 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
928 <0 0 0 873 <0 0 0 2 &intc 0 0 78
929 IRQ_T 874 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
930 <0 0 0 875 <0 0 0 3 &intc 0 0 79
931 IRQ_T 876 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
932 <0 0 0 877 <0 0 0 4 &intc 0 0 83
933 IRQ_T 878 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
934 879
935 clocks = <&gcc GCC_SYS 880 clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
936 <&gcc GCC_PCI 881 <&gcc GCC_PCIE0_AXI_M_CLK>,
937 <&gcc GCC_PCI 882 <&gcc GCC_PCIE0_AXI_S_CLK>,
938 <&gcc GCC_PCI 883 <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>,
939 <&gcc GCC_PCI 884 <&gcc GCC_PCIE0_RCHNG_CLK>;
940 clock-names = "iface", 885 clock-names = "iface",
941 "axi_m", 886 "axi_m",
942 "axi_s", 887 "axi_s",
943 "axi_bri 888 "axi_bridge",
944 "rchng"; 889 "rchng";
945 890
946 resets = <&gcc GCC_PCI 891 resets = <&gcc GCC_PCIE0_PIPE_ARES>,
947 <&gcc GCC_PCI 892 <&gcc GCC_PCIE0_SLEEP_ARES>,
948 <&gcc GCC_PCI 893 <&gcc GCC_PCIE0_CORE_STICKY_ARES>,
949 <&gcc GCC_PCI 894 <&gcc GCC_PCIE0_AXI_MASTER_ARES>,
950 <&gcc GCC_PCI 895 <&gcc GCC_PCIE0_AXI_SLAVE_ARES>,
951 <&gcc GCC_PCI 896 <&gcc GCC_PCIE0_AHB_ARES>,
952 <&gcc GCC_PCI 897 <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>,
953 <&gcc GCC_PCI 898 <&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>;
954 reset-names = "pipe", 899 reset-names = "pipe",
955 "sleep", 900 "sleep",
956 "sticky" 901 "sticky",
957 "axi_m", 902 "axi_m",
958 "axi_s", 903 "axi_s",
959 "ahb", 904 "ahb",
960 "axi_m_s 905 "axi_m_sticky",
961 "axi_s_s 906 "axi_s_sticky";
962 status = "disabled"; 907 status = "disabled";
963 <<
964 pcie@0 { <<
965 device_type = <<
966 reg = <0x0 0x0 <<
967 bus-range = <0 <<
968 <<
969 #address-cells <<
970 #size-cells = <<
971 ranges; <<
972 }; <<
973 }; 908 };
974 }; 909 };
975 910
976 timer { 911 timer {
977 compatible = "arm,armv8-timer" 912 compatible = "arm,armv8-timer";
978 interrupts = <GIC_PPI 2 (GIC_C 913 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
979 <GIC_PPI 3 (GIC_C 914 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
980 <GIC_PPI 4 (GIC_C 915 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
981 <GIC_PPI 1 (GIC_C 916 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
982 }; 917 };
983 918
984 thermal-zones { 919 thermal-zones {
985 nss-top-thermal { 920 nss-top-thermal {
986 polling-delay-passive 921 polling-delay-passive = <250>;
>> 922 polling-delay = <1000>;
987 923
988 thermal-sensors = <&ts 924 thermal-sensors = <&tsens 4>;
989 925
990 trips { 926 trips {
991 nss-top-crit { 927 nss-top-crit {
992 temper 928 temperature = <110000>;
993 hyster 929 hysteresis = <1000>;
994 type = 930 type = "critical";
995 }; 931 };
996 }; 932 };
997 }; 933 };
998 934
999 nss0-thermal { 935 nss0-thermal {
1000 polling-delay-passive 936 polling-delay-passive = <250>;
>> 937 polling-delay = <1000>;
1001 938
1002 thermal-sensors = <&t 939 thermal-sensors = <&tsens 5>;
1003 940
1004 trips { 941 trips {
1005 nss-0-crit { 942 nss-0-crit {
1006 tempe 943 temperature = <110000>;
1007 hyste 944 hysteresis = <1000>;
1008 type 945 type = "critical";
1009 }; 946 };
1010 }; 947 };
1011 }; 948 };
1012 949
1013 nss1-thermal { 950 nss1-thermal {
1014 polling-delay-passive 951 polling-delay-passive = <250>;
>> 952 polling-delay = <1000>;
1015 953
1016 thermal-sensors = <&t 954 thermal-sensors = <&tsens 6>;
1017 955
1018 trips { 956 trips {
1019 nss-1-crit { 957 nss-1-crit {
1020 tempe 958 temperature = <110000>;
1021 hyste 959 hysteresis = <1000>;
1022 type 960 type = "critical";
1023 }; 961 };
1024 }; 962 };
1025 }; 963 };
1026 964
1027 wcss-phya0-thermal { 965 wcss-phya0-thermal {
1028 polling-delay-passive 966 polling-delay-passive = <250>;
>> 967 polling-delay = <1000>;
1029 968
1030 thermal-sensors = <&t 969 thermal-sensors = <&tsens 7>;
1031 970
1032 trips { 971 trips {
1033 wcss-phya0-cr 972 wcss-phya0-crit {
1034 tempe 973 temperature = <110000>;
1035 hyste 974 hysteresis = <1000>;
1036 type 975 type = "critical";
1037 }; 976 };
1038 }; 977 };
1039 }; 978 };
1040 979
1041 wcss-phya1-thermal { 980 wcss-phya1-thermal {
1042 polling-delay-passive 981 polling-delay-passive = <250>;
>> 982 polling-delay = <1000>;
1043 983
1044 thermal-sensors = <&t 984 thermal-sensors = <&tsens 8>;
1045 985
1046 trips { 986 trips {
1047 wcss-phya1-cr 987 wcss-phya1-crit {
1048 tempe 988 temperature = <110000>;
1049 hyste 989 hysteresis = <1000>;
1050 type 990 type = "critical";
1051 }; 991 };
1052 }; 992 };
1053 }; 993 };
1054 994
1055 cpu0_thermal: cpu0-thermal { 995 cpu0_thermal: cpu0-thermal {
1056 polling-delay-passive 996 polling-delay-passive = <250>;
>> 997 polling-delay = <1000>;
1057 998
1058 thermal-sensors = <&t 999 thermal-sensors = <&tsens 9>;
1059 1000
1060 trips { 1001 trips {
1061 cpu0-crit { 1002 cpu0-crit {
1062 tempe 1003 temperature = <110000>;
1063 hyste 1004 hysteresis = <1000>;
1064 type 1005 type = "critical";
1065 }; 1006 };
1066 }; 1007 };
1067 }; 1008 };
1068 1009
1069 cpu1_thermal: cpu1-thermal { 1010 cpu1_thermal: cpu1-thermal {
1070 polling-delay-passive 1011 polling-delay-passive = <250>;
>> 1012 polling-delay = <1000>;
1071 1013
1072 thermal-sensors = <&t 1014 thermal-sensors = <&tsens 10>;
1073 1015
1074 trips { 1016 trips {
1075 cpu1-crit { 1017 cpu1-crit {
1076 tempe 1018 temperature = <110000>;
1077 hyste 1019 hysteresis = <1000>;
1078 type 1020 type = "critical";
1079 }; 1021 };
1080 }; 1022 };
1081 }; 1023 };
1082 1024
1083 cpu2_thermal: cpu2-thermal { 1025 cpu2_thermal: cpu2-thermal {
1084 polling-delay-passive 1026 polling-delay-passive = <250>;
>> 1027 polling-delay = <1000>;
1085 1028
1086 thermal-sensors = <&t 1029 thermal-sensors = <&tsens 11>;
1087 1030
1088 trips { 1031 trips {
1089 cpu2-crit { 1032 cpu2-crit {
1090 tempe 1033 temperature = <110000>;
1091 hyste 1034 hysteresis = <1000>;
1092 type 1035 type = "critical";
1093 }; 1036 };
1094 }; 1037 };
1095 }; 1038 };
1096 1039
1097 cpu3_thermal: cpu3-thermal { 1040 cpu3_thermal: cpu3-thermal {
1098 polling-delay-passive 1041 polling-delay-passive = <250>;
>> 1042 polling-delay = <1000>;
1099 1043
1100 thermal-sensors = <&t 1044 thermal-sensors = <&tsens 12>;
1101 1045
1102 trips { 1046 trips {
1103 cpu3-crit { 1047 cpu3-crit {
1104 tempe 1048 temperature = <110000>;
1105 hyste 1049 hysteresis = <1000>;
1106 type 1050 type = "critical";
1107 }; 1051 };
1108 }; 1052 };
1109 }; 1053 };
1110 1054
1111 cluster_thermal: cluster-ther 1055 cluster_thermal: cluster-thermal {
1112 polling-delay-passive 1056 polling-delay-passive = <250>;
>> 1057 polling-delay = <1000>;
1113 1058
1114 thermal-sensors = <&t 1059 thermal-sensors = <&tsens 13>;
1115 1060
1116 trips { 1061 trips {
1117 cluster-crit 1062 cluster-crit {
1118 tempe 1063 temperature = <110000>;
1119 hyste 1064 hysteresis = <1000>;
1120 type 1065 type = "critical";
1121 }; 1066 };
1122 }; 1067 };
1123 }; 1068 };
1124 1069
1125 wcss-phyb0-thermal { 1070 wcss-phyb0-thermal {
1126 polling-delay-passive 1071 polling-delay-passive = <250>;
>> 1072 polling-delay = <1000>;
1127 1073
1128 thermal-sensors = <&t 1074 thermal-sensors = <&tsens 14>;
1129 1075
1130 trips { 1076 trips {
1131 wcss-phyb0-cr 1077 wcss-phyb0-crit {
1132 tempe 1078 temperature = <110000>;
1133 hyste 1079 hysteresis = <1000>;
1134 type 1080 type = "critical";
1135 }; 1081 };
1136 }; 1082 };
1137 }; 1083 };
1138 1084
1139 wcss-phyb1-thermal { 1085 wcss-phyb1-thermal {
1140 polling-delay-passive 1086 polling-delay-passive = <250>;
>> 1087 polling-delay = <1000>;
1141 1088
1142 thermal-sensors = <&t 1089 thermal-sensors = <&tsens 15>;
1143 1090
1144 trips { 1091 trips {
1145 wcss-phyb1-cr 1092 wcss-phyb1-crit {
1146 tempe 1093 temperature = <110000>;
1147 hyste 1094 hysteresis = <1000>;
1148 type 1095 type = "critical";
1149 }; 1096 };
1150 }; 1097 };
1151 }; 1098 };
1152 }; 1099 };
1153 }; 1100 };
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