1 // SPDX-License-Identifier: GPL-2.0-only 1 // SPDX-License-Identifier: GPL-2.0-only
2 /* 2 /*
3 * Copyright (c) 2017, The Linux Foundation. A 3 * Copyright (c) 2017, The Linux Foundation. All rights reserved.
4 */ 4 */
5 5
6 #include <dt-bindings/interrupt-controller/arm 6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,gcc-ipq8074.h 7 #include <dt-bindings/clock/qcom,gcc-ipq8074.h>
8 8
9 / { 9 / {
10 #address-cells = <2>; 10 #address-cells = <2>;
11 #size-cells = <2>; 11 #size-cells = <2>;
12 12
13 model = "Qualcomm Technologies, Inc. I 13 model = "Qualcomm Technologies, Inc. IPQ8074";
14 compatible = "qcom,ipq8074"; 14 compatible = "qcom,ipq8074";
15 interrupt-parent = <&intc>; 15 interrupt-parent = <&intc>;
16 16
17 clocks { 17 clocks {
18 sleep_clk: sleep_clk { 18 sleep_clk: sleep_clk {
19 compatible = "fixed-cl 19 compatible = "fixed-clock";
20 clock-frequency = <327 20 clock-frequency = <32768>;
21 #clock-cells = <0>; 21 #clock-cells = <0>;
22 }; 22 };
23 23
24 xo: xo { 24 xo: xo {
25 compatible = "fixed-cl 25 compatible = "fixed-clock";
26 clock-frequency = <192 26 clock-frequency = <19200000>;
27 #clock-cells = <0>; 27 #clock-cells = <0>;
28 }; 28 };
29 }; 29 };
30 30
31 cpus { 31 cpus {
32 #address-cells = <1>; 32 #address-cells = <1>;
33 #size-cells = <0>; 33 #size-cells = <0>;
34 34
35 CPU0: cpu@0 { 35 CPU0: cpu@0 {
36 device_type = "cpu"; 36 device_type = "cpu";
37 compatible = "arm,cort 37 compatible = "arm,cortex-a53";
38 reg = <0x0>; 38 reg = <0x0>;
39 next-level-cache = <&L 39 next-level-cache = <&L2_0>;
40 enable-method = "psci" 40 enable-method = "psci";
41 }; 41 };
42 42
43 CPU1: cpu@1 { 43 CPU1: cpu@1 {
44 device_type = "cpu"; 44 device_type = "cpu";
45 compatible = "arm,cort 45 compatible = "arm,cortex-a53";
46 enable-method = "psci" 46 enable-method = "psci";
47 reg = <0x1>; 47 reg = <0x1>;
48 next-level-cache = <&L 48 next-level-cache = <&L2_0>;
49 }; 49 };
50 50
51 CPU2: cpu@2 { 51 CPU2: cpu@2 {
52 device_type = "cpu"; 52 device_type = "cpu";
53 compatible = "arm,cort 53 compatible = "arm,cortex-a53";
54 enable-method = "psci" 54 enable-method = "psci";
55 reg = <0x2>; 55 reg = <0x2>;
56 next-level-cache = <&L 56 next-level-cache = <&L2_0>;
57 }; 57 };
58 58
59 CPU3: cpu@3 { 59 CPU3: cpu@3 {
60 device_type = "cpu"; 60 device_type = "cpu";
61 compatible = "arm,cort 61 compatible = "arm,cortex-a53";
62 enable-method = "psci" 62 enable-method = "psci";
63 reg = <0x3>; 63 reg = <0x3>;
64 next-level-cache = <&L 64 next-level-cache = <&L2_0>;
65 }; 65 };
66 66
67 L2_0: l2-cache { 67 L2_0: l2-cache {
68 compatible = "cache"; 68 compatible = "cache";
69 cache-level = <2>; 69 cache-level = <2>;
70 cache-unified; 70 cache-unified;
71 }; 71 };
72 }; 72 };
73 73
74 pmu { 74 pmu {
75 compatible = "arm,cortex-a53-p 75 compatible = "arm,cortex-a53-pmu";
76 interrupts = <GIC_PPI 7 (GIC_C 76 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
77 }; 77 };
78 78
79 psci { 79 psci {
80 compatible = "arm,psci-1.0"; 80 compatible = "arm,psci-1.0";
81 method = "smc"; 81 method = "smc";
82 }; 82 };
83 83
84 reserved-memory { 84 reserved-memory {
85 #address-cells = <2>; 85 #address-cells = <2>;
86 #size-cells = <2>; 86 #size-cells = <2>;
87 ranges; 87 ranges;
88 88
89 bootloader@4a600000 { 89 bootloader@4a600000 {
90 reg = <0x0 0x4a600000 90 reg = <0x0 0x4a600000 0x0 0x400000>;
91 no-map; 91 no-map;
92 }; 92 };
93 93
94 sbl@4aa00000 { 94 sbl@4aa00000 {
95 reg = <0x0 0x4aa00000 95 reg = <0x0 0x4aa00000 0x0 0x100000>;
96 no-map; 96 no-map;
97 }; 97 };
98 98
99 smem@4ab00000 { 99 smem@4ab00000 {
100 compatible = "qcom,sme 100 compatible = "qcom,smem";
101 reg = <0x0 0x4ab00000 101 reg = <0x0 0x4ab00000 0x0 0x100000>;
102 no-map; 102 no-map;
103 103
104 hwlocks = <&tcsr_mutex 104 hwlocks = <&tcsr_mutex 3>;
105 }; 105 };
106 106
107 memory@4ac00000 { 107 memory@4ac00000 {
108 reg = <0x0 0x4ac00000 108 reg = <0x0 0x4ac00000 0x0 0x400000>;
109 no-map; 109 no-map;
110 }; 110 };
111 }; 111 };
112 112
113 firmware { 113 firmware {
114 scm { 114 scm {
115 compatible = "qcom,scm 115 compatible = "qcom,scm-ipq8074", "qcom,scm";
116 qcom,dload-mode = <&tc 116 qcom,dload-mode = <&tcsr 0x6100>;
117 }; 117 };
118 }; 118 };
119 119
120 soc: soc@0 { 120 soc: soc@0 {
121 #address-cells = <1>; 121 #address-cells = <1>;
122 #size-cells = <1>; 122 #size-cells = <1>;
123 ranges = <0 0 0 0xffffffff>; 123 ranges = <0 0 0 0xffffffff>;
124 compatible = "simple-bus"; 124 compatible = "simple-bus";
125 125
126 ssphy_1: phy@58000 { 126 ssphy_1: phy@58000 {
127 compatible = "qcom,ipq 127 compatible = "qcom,ipq8074-qmp-usb3-phy";
128 reg = <0x00058000 0x10 128 reg = <0x00058000 0x1000>;
129 129
130 clocks = <&gcc GCC_USB 130 clocks = <&gcc GCC_USB1_AUX_CLK>,
131 <&xo>, 131 <&xo>,
132 <&gcc GCC_USB 132 <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
133 <&gcc GCC_USB 133 <&gcc GCC_USB1_PIPE_CLK>;
134 clock-names = "aux", 134 clock-names = "aux",
135 "ref", 135 "ref",
136 "cfg_ahb 136 "cfg_ahb",
137 "pipe"; 137 "pipe";
138 clock-output-names = " 138 clock-output-names = "usb3phy_1_cc_pipe_clk";
139 #clock-cells = <0>; 139 #clock-cells = <0>;
140 #phy-cells = <0>; 140 #phy-cells = <0>;
141 141
142 resets = <&gcc GCC_USB 142 resets = <&gcc GCC_USB1_PHY_BCR>,
143 <&gcc GCC_USB 143 <&gcc GCC_USB3PHY_1_PHY_BCR>;
144 reset-names = "phy", 144 reset-names = "phy",
145 "phy_phy 145 "phy_phy";
146 146
147 status = "disabled"; 147 status = "disabled";
148 }; 148 };
149 149
150 qusb_phy_1: phy@59000 { 150 qusb_phy_1: phy@59000 {
151 compatible = "qcom,ipq 151 compatible = "qcom,ipq8074-qusb2-phy";
152 reg = <0x00059000 0x18 152 reg = <0x00059000 0x180>;
153 #phy-cells = <0>; 153 #phy-cells = <0>;
154 154
155 clocks = <&gcc GCC_USB 155 clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
156 <&xo>; 156 <&xo>;
157 clock-names = "cfg_ahb 157 clock-names = "cfg_ahb", "ref";
158 158
159 resets = <&gcc GCC_QUS 159 resets = <&gcc GCC_QUSB2_1_PHY_BCR>;
160 status = "disabled"; 160 status = "disabled";
161 }; 161 };
162 162
163 ssphy_0: phy@78000 { 163 ssphy_0: phy@78000 {
164 compatible = "qcom,ipq 164 compatible = "qcom,ipq8074-qmp-usb3-phy";
165 reg = <0x00078000 0x10 165 reg = <0x00078000 0x1000>;
166 166
167 clocks = <&gcc GCC_USB 167 clocks = <&gcc GCC_USB0_AUX_CLK>,
168 <&xo>, 168 <&xo>,
169 <&gcc GCC_USB 169 <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
170 <&gcc GCC_USB 170 <&gcc GCC_USB0_PIPE_CLK>;
171 clock-names = "aux", 171 clock-names = "aux",
172 "ref", 172 "ref",
173 "cfg_ahb 173 "cfg_ahb",
174 "pipe"; 174 "pipe";
175 clock-output-names = " 175 clock-output-names = "usb3phy_0_cc_pipe_clk";
176 #clock-cells = <0>; 176 #clock-cells = <0>;
177 #phy-cells = <0>; 177 #phy-cells = <0>;
178 178
179 resets = <&gcc GCC_USB 179 resets = <&gcc GCC_USB0_PHY_BCR>,
180 <&gcc GCC_USB 180 <&gcc GCC_USB3PHY_0_PHY_BCR>;
181 reset-names = "phy", 181 reset-names = "phy",
182 "phy_phy 182 "phy_phy";
183 183
184 status = "disabled"; 184 status = "disabled";
185 }; 185 };
186 186
187 qusb_phy_0: phy@79000 { 187 qusb_phy_0: phy@79000 {
188 compatible = "qcom,ipq 188 compatible = "qcom,ipq8074-qusb2-phy";
189 reg = <0x00079000 0x18 189 reg = <0x00079000 0x180>;
190 #phy-cells = <0>; 190 #phy-cells = <0>;
191 191
192 clocks = <&gcc GCC_USB 192 clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
193 <&xo>; 193 <&xo>;
194 clock-names = "cfg_ahb 194 clock-names = "cfg_ahb", "ref";
195 195
196 resets = <&gcc GCC_QUS 196 resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
197 status = "disabled"; 197 status = "disabled";
198 }; 198 };
199 199
200 pcie_qmp0: phy@84000 { 200 pcie_qmp0: phy@84000 {
201 compatible = "qcom,ipq 201 compatible = "qcom,ipq8074-qmp-gen3-pcie-phy";
202 reg = <0x00084000 0x10 202 reg = <0x00084000 0x1000>;
203 203
204 clocks = <&gcc GCC_PCI 204 clocks = <&gcc GCC_PCIE0_AUX_CLK>,
205 <&gcc GCC_PCI 205 <&gcc GCC_PCIE0_AHB_CLK>,
206 <&gcc GCC_PCI 206 <&gcc GCC_PCIE0_PIPE_CLK>;
207 clock-names = "aux", 207 clock-names = "aux",
208 "cfg_ahb 208 "cfg_ahb",
209 "pipe"; 209 "pipe";
210 210
211 clock-output-names = " 211 clock-output-names = "pcie20_phy0_pipe_clk";
212 #clock-cells = <0>; 212 #clock-cells = <0>;
213 213
214 #phy-cells = <0>; 214 #phy-cells = <0>;
215 215
216 resets = <&gcc GCC_PCI 216 resets = <&gcc GCC_PCIE0_PHY_BCR>,
217 <&gcc GCC_PCI 217 <&gcc GCC_PCIE0PHY_PHY_BCR>;
218 reset-names = "phy", 218 reset-names = "phy",
219 "common" 219 "common";
220 status = "disabled"; 220 status = "disabled";
221 }; 221 };
222 222
223 pcie_qmp1: phy@8e000 { 223 pcie_qmp1: phy@8e000 {
224 compatible = "qcom,ipq 224 compatible = "qcom,ipq8074-qmp-pcie-phy";
225 reg = <0x0008e000 0x10 225 reg = <0x0008e000 0x1000>;
226 226
227 clocks = <&gcc GCC_PCI 227 clocks = <&gcc GCC_PCIE1_AUX_CLK>,
228 <&gcc GCC_PCI 228 <&gcc GCC_PCIE1_AHB_CLK>,
229 <&gcc GCC_PCI 229 <&gcc GCC_PCIE1_PIPE_CLK>;
230 clock-names = "aux", 230 clock-names = "aux",
231 "cfg_ahb 231 "cfg_ahb",
232 "pipe"; 232 "pipe";
233 233
234 clock-output-names = " 234 clock-output-names = "pcie20_phy1_pipe_clk";
235 #clock-cells = <0>; 235 #clock-cells = <0>;
236 236
237 #phy-cells = <0>; 237 #phy-cells = <0>;
238 238
239 resets = <&gcc GCC_PCI 239 resets = <&gcc GCC_PCIE1_PHY_BCR>,
240 <&gcc GCC_PCI 240 <&gcc GCC_PCIE1PHY_PHY_BCR>;
241 reset-names = "phy", 241 reset-names = "phy",
242 "common" 242 "common";
243 status = "disabled"; 243 status = "disabled";
244 }; 244 };
245 245
246 mdio: mdio@90000 { 246 mdio: mdio@90000 {
247 compatible = "qcom,ipq 247 compatible = "qcom,ipq8074-mdio", "qcom,ipq4019-mdio";
248 reg = <0x00090000 0x64 248 reg = <0x00090000 0x64>;
249 #address-cells = <1>; 249 #address-cells = <1>;
250 #size-cells = <0>; 250 #size-cells = <0>;
251 251
252 clocks = <&gcc GCC_MDI 252 clocks = <&gcc GCC_MDIO_AHB_CLK>;
253 clock-names = "gcc_mdi 253 clock-names = "gcc_mdio_ahb_clk";
254 254
255 clock-frequency = <625 <<
256 <<
257 status = "disabled"; 255 status = "disabled";
258 }; 256 };
259 257
260 qfprom: efuse@a4000 { 258 qfprom: efuse@a4000 {
261 compatible = "qcom,ipq 259 compatible = "qcom,ipq8074-qfprom", "qcom,qfprom";
262 reg = <0x000a4000 0x20 260 reg = <0x000a4000 0x2000>;
263 #address-cells = <1>; 261 #address-cells = <1>;
264 #size-cells = <1>; 262 #size-cells = <1>;
265 }; 263 };
266 264
267 prng: rng@e3000 { 265 prng: rng@e3000 {
268 compatible = "qcom,prn 266 compatible = "qcom,prng-ee";
269 reg = <0x000e3000 0x10 267 reg = <0x000e3000 0x1000>;
270 clocks = <&gcc GCC_PRN 268 clocks = <&gcc GCC_PRNG_AHB_CLK>;
271 clock-names = "core"; 269 clock-names = "core";
272 status = "disabled"; 270 status = "disabled";
273 }; 271 };
274 272
275 tsens: thermal-sensor@4a9000 { 273 tsens: thermal-sensor@4a9000 {
276 compatible = "qcom,ipq 274 compatible = "qcom,ipq8074-tsens";
277 reg = <0x4a9000 0x1000 275 reg = <0x4a9000 0x1000>, /* TM */
278 <0x4a8000 0x1000 276 <0x4a8000 0x1000>; /* SROT */
279 interrupts = <GIC_SPI 277 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
280 interrupt-names = "com 278 interrupt-names = "combined";
281 #qcom,sensors = <16>; 279 #qcom,sensors = <16>;
282 #thermal-sensor-cells 280 #thermal-sensor-cells = <1>;
283 }; 281 };
284 282
285 cryptobam: dma-controller@7040 283 cryptobam: dma-controller@704000 {
286 compatible = "qcom,bam 284 compatible = "qcom,bam-v1.7.0";
287 reg = <0x00704000 0x20 285 reg = <0x00704000 0x20000>;
288 interrupts = <GIC_SPI 286 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
289 clocks = <&gcc GCC_CRY 287 clocks = <&gcc GCC_CRYPTO_AHB_CLK>;
290 clock-names = "bam_clk 288 clock-names = "bam_clk";
291 #dma-cells = <1>; 289 #dma-cells = <1>;
292 qcom,ee = <1>; 290 qcom,ee = <1>;
293 qcom,controlled-remote 291 qcom,controlled-remotely;
294 status = "disabled"; 292 status = "disabled";
295 }; 293 };
296 294
297 crypto: crypto@73a000 { 295 crypto: crypto@73a000 {
298 compatible = "qcom,cry 296 compatible = "qcom,crypto-v5.1";
299 reg = <0x0073a000 0x60 297 reg = <0x0073a000 0x6000>;
300 clocks = <&gcc GCC_CRY 298 clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
301 <&gcc GCC_CRY 299 <&gcc GCC_CRYPTO_AXI_CLK>,
302 <&gcc GCC_CRY 300 <&gcc GCC_CRYPTO_CLK>;
303 clock-names = "iface", 301 clock-names = "iface", "bus", "core";
304 dmas = <&cryptobam 2>, 302 dmas = <&cryptobam 2>, <&cryptobam 3>;
305 dma-names = "rx", "tx" 303 dma-names = "rx", "tx";
306 status = "disabled"; 304 status = "disabled";
307 }; 305 };
308 306
309 tlmm: pinctrl@1000000 { 307 tlmm: pinctrl@1000000 {
310 compatible = "qcom,ipq 308 compatible = "qcom,ipq8074-pinctrl";
311 reg = <0x01000000 0x30 309 reg = <0x01000000 0x300000>;
312 interrupts = <GIC_SPI 310 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
313 gpio-controller; 311 gpio-controller;
314 gpio-ranges = <&tlmm 0 312 gpio-ranges = <&tlmm 0 0 70>;
315 #gpio-cells = <2>; 313 #gpio-cells = <2>;
316 interrupt-controller; 314 interrupt-controller;
317 #interrupt-cells = <2> 315 #interrupt-cells = <2>;
318 316
319 serial_4_pins: serial4 317 serial_4_pins: serial4-state {
320 pins = "gpio23 318 pins = "gpio23", "gpio24";
321 function = "bl 319 function = "blsp4_uart1";
322 drive-strength 320 drive-strength = <8>;
323 bias-disable; 321 bias-disable;
324 }; 322 };
325 323
326 serial_5_pins: serial5 <<
327 pins = "gpio9" <<
328 function = "bl <<
329 drive-strength <<
330 bias-disable; <<
331 }; <<
332 <<
333 i2c_0_pins: i2c-0-stat 324 i2c_0_pins: i2c-0-state {
334 pins = "gpio42 325 pins = "gpio42", "gpio43";
335 function = "bl 326 function = "blsp1_i2c";
336 drive-strength 327 drive-strength = <8>;
337 bias-disable; 328 bias-disable;
338 }; 329 };
339 330
340 spi_0_pins: spi-0-stat 331 spi_0_pins: spi-0-state {
341 pins = "gpio38 332 pins = "gpio38", "gpio39", "gpio40", "gpio41";
342 function = "bl 333 function = "blsp0_spi";
343 drive-strength 334 drive-strength = <8>;
344 bias-disable; 335 bias-disable;
345 }; 336 };
346 337
347 hsuart_pins: hsuart-st 338 hsuart_pins: hsuart-state {
348 pins = "gpio46 339 pins = "gpio46", "gpio47", "gpio48", "gpio49";
349 function = "bl 340 function = "blsp2_uart";
350 drive-strength 341 drive-strength = <8>;
351 bias-disable; 342 bias-disable;
352 }; 343 };
353 344
354 qpic_pins: qpic-state 345 qpic_pins: qpic-state {
355 pins = "gpio1" 346 pins = "gpio1", "gpio3", "gpio4",
356 "gpio5" 347 "gpio5", "gpio6", "gpio7",
357 "gpio8" 348 "gpio8", "gpio10", "gpio11",
358 "gpio12 349 "gpio12", "gpio13", "gpio14",
359 "gpio15 !! 350 "gpio15", "gpio16", "gpio17";
360 function = "qp 351 function = "qpic";
361 drive-strength 352 drive-strength = <8>;
362 bias-disable; 353 bias-disable;
363 }; 354 };
364 }; 355 };
365 356
366 gcc: clock-controller@1800000 !! 357 gcc: gcc@1800000 {
367 compatible = "qcom,gcc 358 compatible = "qcom,gcc-ipq8074";
368 reg = <0x01800000 0x80 359 reg = <0x01800000 0x80000>;
369 clocks = <&xo>, 360 clocks = <&xo>,
370 <&sleep_clk>, 361 <&sleep_clk>,
371 <&pcie_qmp0>, 362 <&pcie_qmp0>,
372 <&pcie_qmp1>; 363 <&pcie_qmp1>;
373 clock-names = "xo", 364 clock-names = "xo",
374 "sleep_c 365 "sleep_clk",
375 "pcie0_p 366 "pcie0_pipe",
376 "pcie1_p 367 "pcie1_pipe";
377 #clock-cells = <1>; 368 #clock-cells = <1>;
378 #power-domain-cells = 369 #power-domain-cells = <1>;
379 #reset-cells = <1>; 370 #reset-cells = <1>;
380 }; 371 };
381 372
382 tcsr_mutex: hwlock@1905000 { 373 tcsr_mutex: hwlock@1905000 {
383 compatible = "qcom,tcs 374 compatible = "qcom,tcsr-mutex";
384 reg = <0x01905000 0x20 375 reg = <0x01905000 0x20000>;
385 #hwlock-cells = <1>; 376 #hwlock-cells = <1>;
386 }; 377 };
387 378
388 tcsr: syscon@1937000 { 379 tcsr: syscon@1937000 {
389 compatible = "qcom,tcs 380 compatible = "qcom,tcsr-ipq8074", "syscon";
390 reg = <0x01937000 0x21 381 reg = <0x01937000 0x21000>;
391 }; 382 };
392 383
393 spmi_bus: spmi@200f000 { 384 spmi_bus: spmi@200f000 {
394 compatible = "qcom,spm 385 compatible = "qcom,spmi-pmic-arb";
395 reg = <0x0200f000 0x00 386 reg = <0x0200f000 0x001000>,
396 <0x02400000 0x80 387 <0x02400000 0x800000>,
397 <0x02c00000 0x80 388 <0x02c00000 0x800000>,
398 <0x03800000 0x20 389 <0x03800000 0x200000>,
399 <0x0200a000 0x00 390 <0x0200a000 0x000700>;
400 reg-names = "core", "c 391 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
401 interrupts = <GIC_SPI 392 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
402 interrupt-names = "per 393 interrupt-names = "periph_irq";
403 qcom,ee = <0>; 394 qcom,ee = <0>;
404 qcom,channel = <0>; 395 qcom,channel = <0>;
405 #address-cells = <2>; 396 #address-cells = <2>;
406 #size-cells = <0>; 397 #size-cells = <0>;
407 interrupt-controller; 398 interrupt-controller;
408 #interrupt-cells = <4> 399 #interrupt-cells = <4>;
409 }; 400 };
410 401
411 sdhc_1: mmc@7824900 { 402 sdhc_1: mmc@7824900 {
412 compatible = "qcom,ipq 403 compatible = "qcom,ipq8074-sdhci", "qcom,sdhci-msm-v4";
413 reg = <0x7824900 0x500 404 reg = <0x7824900 0x500>, <0x7824000 0x800>;
414 reg-names = "hc", "cor 405 reg-names = "hc", "core";
415 406
416 interrupts = <GIC_SPI 407 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
417 <GIC_SPI 408 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
418 interrupt-names = "hc_ 409 interrupt-names = "hc_irq", "pwr_irq";
419 410
420 clocks = <&gcc GCC_SDC 411 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
421 <&gcc GCC_SDC 412 <&gcc GCC_SDCC1_APPS_CLK>,
422 <&xo>; 413 <&xo>;
423 clock-names = "iface", 414 clock-names = "iface", "core", "xo";
424 resets = <&gcc GCC_SDC 415 resets = <&gcc GCC_SDCC1_BCR>;
425 max-frequency = <38400 416 max-frequency = <384000000>;
426 mmc-ddr-1_8v; 417 mmc-ddr-1_8v;
427 mmc-hs200-1_8v; 418 mmc-hs200-1_8v;
428 mmc-hs400-1_8v; 419 mmc-hs400-1_8v;
429 bus-width = <8>; 420 bus-width = <8>;
430 421
431 status = "disabled"; 422 status = "disabled";
432 }; 423 };
433 424
434 blsp_dma: dma-controller@78840 425 blsp_dma: dma-controller@7884000 {
435 compatible = "qcom,bam 426 compatible = "qcom,bam-v1.7.0";
436 reg = <0x07884000 0x2b 427 reg = <0x07884000 0x2b000>;
437 interrupts = <GIC_SPI 428 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
438 clocks = <&gcc GCC_BLS 429 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
439 clock-names = "bam_clk 430 clock-names = "bam_clk";
440 #dma-cells = <1>; 431 #dma-cells = <1>;
441 qcom,ee = <0>; 432 qcom,ee = <0>;
442 }; 433 };
443 434
444 blsp1_uart1: serial@78af000 { 435 blsp1_uart1: serial@78af000 {
445 compatible = "qcom,msm 436 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
446 reg = <0x078af000 0x20 437 reg = <0x078af000 0x200>;
447 interrupts = <GIC_SPI 438 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
448 clocks = <&gcc GCC_BLS 439 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
449 <&gcc GCC_BLS 440 <&gcc GCC_BLSP1_AHB_CLK>;
450 clock-names = "core", 441 clock-names = "core", "iface";
451 status = "disabled"; 442 status = "disabled";
452 }; 443 };
453 444
454 blsp1_uart3: serial@78b1000 { 445 blsp1_uart3: serial@78b1000 {
455 compatible = "qcom,msm 446 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
456 reg = <0x078b1000 0x20 447 reg = <0x078b1000 0x200>;
457 interrupts = <GIC_SPI 448 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
458 clocks = <&gcc GCC_BLS 449 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
459 <&gcc GCC_BLSP 450 <&gcc GCC_BLSP1_AHB_CLK>;
460 clock-names = "core", 451 clock-names = "core", "iface";
461 dmas = <&blsp_dma 4>, 452 dmas = <&blsp_dma 4>,
462 <&blsp_dma 5>; 453 <&blsp_dma 5>;
463 dma-names = "tx", "rx" 454 dma-names = "tx", "rx";
464 pinctrl-0 = <&hsuart_p 455 pinctrl-0 = <&hsuart_pins>;
465 pinctrl-names = "defau 456 pinctrl-names = "default";
466 status = "disabled"; 457 status = "disabled";
467 }; 458 };
468 459
469 blsp1_uart5: serial@78b3000 { 460 blsp1_uart5: serial@78b3000 {
470 compatible = "qcom,msm 461 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
471 reg = <0x078b3000 0x20 462 reg = <0x078b3000 0x200>;
472 interrupts = <GIC_SPI 463 interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
473 clocks = <&gcc GCC_BLS 464 clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>,
474 <&gcc GCC_BLS 465 <&gcc GCC_BLSP1_AHB_CLK>;
475 clock-names = "core", 466 clock-names = "core", "iface";
476 pinctrl-0 = <&serial_4 467 pinctrl-0 = <&serial_4_pins>;
477 pinctrl-names = "defau 468 pinctrl-names = "default";
478 status = "disabled"; 469 status = "disabled";
479 }; 470 };
480 471
481 blsp1_uart6: serial@78b4000 { <<
482 compatible = "qcom,msm <<
483 reg = <0x078b4000 0x20 <<
484 interrupts = <GIC_SPI <<
485 clocks = <&gcc GCC_BLS <<
486 <&gcc GCC_BLS <<
487 clock-names = "core", <<
488 pinctrl-0 = <&serial_5 <<
489 pinctrl-names = "defau <<
490 status = "disabled"; <<
491 }; <<
492 <<
493 blsp1_spi1: spi@78b5000 { 472 blsp1_spi1: spi@78b5000 {
494 compatible = "qcom,spi 473 compatible = "qcom,spi-qup-v2.2.1";
495 #address-cells = <1>; 474 #address-cells = <1>;
496 #size-cells = <0>; 475 #size-cells = <0>;
497 reg = <0x078b5000 0x60 476 reg = <0x078b5000 0x600>;
498 interrupts = <GIC_SPI 477 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
499 clocks = <&gcc GCC_BLS 478 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
500 <&gcc GCC_BLSP 479 <&gcc GCC_BLSP1_AHB_CLK>;
501 clock-names = "core", 480 clock-names = "core", "iface";
502 dmas = <&blsp_dma 12>, 481 dmas = <&blsp_dma 12>, <&blsp_dma 13>;
503 dma-names = "tx", "rx" 482 dma-names = "tx", "rx";
504 pinctrl-0 = <&spi_0_pi 483 pinctrl-0 = <&spi_0_pins>;
505 pinctrl-names = "defau 484 pinctrl-names = "default";
506 status = "disabled"; 485 status = "disabled";
507 }; 486 };
508 487
509 blsp1_i2c2: i2c@78b6000 { 488 blsp1_i2c2: i2c@78b6000 {
510 compatible = "qcom,i2c 489 compatible = "qcom,i2c-qup-v2.2.1";
511 #address-cells = <1>; 490 #address-cells = <1>;
512 #size-cells = <0>; 491 #size-cells = <0>;
513 reg = <0x078b6000 0x60 492 reg = <0x078b6000 0x600>;
514 interrupts = <GIC_SPI 493 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
515 clocks = <&gcc GCC_BLS 494 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
516 <&gcc GCC_BLS 495 <&gcc GCC_BLSP1_AHB_CLK>;
517 clock-names = "core", 496 clock-names = "core", "iface";
518 clock-frequency = <400 497 clock-frequency = <400000>;
519 dmas = <&blsp_dma 14>, 498 dmas = <&blsp_dma 14>, <&blsp_dma 15>;
520 dma-names = "tx", "rx" 499 dma-names = "tx", "rx";
521 pinctrl-0 = <&i2c_0_pi 500 pinctrl-0 = <&i2c_0_pins>;
522 pinctrl-names = "defau 501 pinctrl-names = "default";
523 status = "disabled"; 502 status = "disabled";
524 }; 503 };
525 504
526 blsp1_i2c3: i2c@78b7000 { 505 blsp1_i2c3: i2c@78b7000 {
527 compatible = "qcom,i2c 506 compatible = "qcom,i2c-qup-v2.2.1";
528 #address-cells = <1>; 507 #address-cells = <1>;
529 #size-cells = <0>; 508 #size-cells = <0>;
530 reg = <0x078b7000 0x60 509 reg = <0x078b7000 0x600>;
531 interrupts = <GIC_SPI 510 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
532 clocks = <&gcc GCC_BLS 511 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
533 <&gcc GCC_BLS 512 <&gcc GCC_BLSP1_AHB_CLK>;
534 clock-names = "core", 513 clock-names = "core", "iface";
535 clock-frequency = <100 514 clock-frequency = <100000>;
536 dmas = <&blsp_dma 16>, 515 dmas = <&blsp_dma 16>, <&blsp_dma 17>;
537 dma-names = "tx", "rx" 516 dma-names = "tx", "rx";
538 status = "disabled"; 517 status = "disabled";
539 }; 518 };
540 519
541 blsp1_spi4: spi@78b8000 { 520 blsp1_spi4: spi@78b8000 {
542 compatible = "qcom,spi 521 compatible = "qcom,spi-qup-v2.2.1";
543 #address-cells = <1>; 522 #address-cells = <1>;
544 #size-cells = <0>; 523 #size-cells = <0>;
545 reg = <0x78b8000 0x600 524 reg = <0x78b8000 0x600>;
546 interrupts = <GIC_SPI 525 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
547 clocks = <&gcc GCC_BLS 526 clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
548 <&gcc GCC_BLS 527 <&gcc GCC_BLSP1_AHB_CLK>;
549 clock-names = "core", 528 clock-names = "core", "iface";
550 dmas = <&blsp_dma 18>, 529 dmas = <&blsp_dma 18>, <&blsp_dma 19>;
551 dma-names = "tx", "rx" 530 dma-names = "tx", "rx";
552 status = "disabled"; 531 status = "disabled";
553 }; 532 };
554 533
555 blsp1_i2c5: i2c@78b9000 { 534 blsp1_i2c5: i2c@78b9000 {
556 compatible = "qcom,i2c 535 compatible = "qcom,i2c-qup-v2.2.1";
557 #address-cells = <1>; 536 #address-cells = <1>;
558 #size-cells = <0>; 537 #size-cells = <0>;
559 reg = <0x78b9000 0x600 538 reg = <0x78b9000 0x600>;
560 interrupts = <GIC_SPI 539 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
561 clocks = <&gcc GCC_BLS 540 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
562 <&gcc GCC_BLS 541 <&gcc GCC_BLSP1_AHB_CLK>;
563 clock-names = "core", 542 clock-names = "core", "iface";
564 clock-frequency = <400 543 clock-frequency = <400000>;
565 dmas = <&blsp_dma 20>, 544 dmas = <&blsp_dma 20>, <&blsp_dma 21>;
566 dma-names = "tx", "rx" 545 dma-names = "tx", "rx";
567 status = "disabled"; 546 status = "disabled";
568 }; 547 };
569 548
570 blsp1_spi5: spi@78b9000 { 549 blsp1_spi5: spi@78b9000 {
571 compatible = "qcom,spi 550 compatible = "qcom,spi-qup-v2.2.1";
572 #address-cells = <1>; 551 #address-cells = <1>;
573 #size-cells = <0>; 552 #size-cells = <0>;
574 reg = <0x78b9000 0x600 553 reg = <0x78b9000 0x600>;
575 interrupts = <GIC_SPI 554 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
576 clocks = <&gcc GCC_BLS 555 clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
577 <&gcc GCC_BLS 556 <&gcc GCC_BLSP1_AHB_CLK>;
578 clock-names = "core", 557 clock-names = "core", "iface";
579 dmas = <&blsp_dma 20>, 558 dmas = <&blsp_dma 20>, <&blsp_dma 21>;
580 dma-names = "tx", "rx" 559 dma-names = "tx", "rx";
581 status = "disabled"; 560 status = "disabled";
582 }; 561 };
583 562
584 blsp1_i2c6: i2c@78ba000 { 563 blsp1_i2c6: i2c@78ba000 {
585 compatible = "qcom,i2c 564 compatible = "qcom,i2c-qup-v2.2.1";
586 #address-cells = <1>; 565 #address-cells = <1>;
587 #size-cells = <0>; 566 #size-cells = <0>;
588 reg = <0x078ba000 0x60 567 reg = <0x078ba000 0x600>;
589 interrupts = <GIC_SPI 568 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
590 clocks = <&gcc GCC_BLS 569 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
591 <&gcc GCC_BLS 570 <&gcc GCC_BLSP1_AHB_CLK>;
592 clock-names = "core", 571 clock-names = "core", "iface";
593 clock-frequency = <100 572 clock-frequency = <100000>;
594 dmas = <&blsp_dma 22>, 573 dmas = <&blsp_dma 22>, <&blsp_dma 23>;
595 dma-names = "tx", "rx" 574 dma-names = "tx", "rx";
596 status = "disabled"; 575 status = "disabled";
597 }; 576 };
598 577
599 qpic_bam: dma-controller@79840 578 qpic_bam: dma-controller@7984000 {
600 compatible = "qcom,bam 579 compatible = "qcom,bam-v1.7.0";
601 reg = <0x07984000 0x1a 580 reg = <0x07984000 0x1a000>;
602 interrupts = <GIC_SPI 581 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
603 clocks = <&gcc GCC_QPI 582 clocks = <&gcc GCC_QPIC_AHB_CLK>;
604 clock-names = "bam_clk 583 clock-names = "bam_clk";
605 #dma-cells = <1>; 584 #dma-cells = <1>;
606 qcom,ee = <0>; 585 qcom,ee = <0>;
607 status = "disabled"; 586 status = "disabled";
608 }; 587 };
609 588
610 qpic_nand: nand-controller@79b 589 qpic_nand: nand-controller@79b0000 {
611 compatible = "qcom,ipq 590 compatible = "qcom,ipq8074-nand";
612 reg = <0x079b0000 0x10 591 reg = <0x079b0000 0x10000>;
613 #address-cells = <1>; 592 #address-cells = <1>;
614 #size-cells = <0>; 593 #size-cells = <0>;
615 clocks = <&gcc GCC_QPI 594 clocks = <&gcc GCC_QPIC_CLK>,
616 <&gcc GCC_QPI 595 <&gcc GCC_QPIC_AHB_CLK>;
617 clock-names = "core", 596 clock-names = "core", "aon";
618 597
619 dmas = <&qpic_bam 0>, 598 dmas = <&qpic_bam 0>,
620 <&qpic_bam 1>, 599 <&qpic_bam 1>,
621 <&qpic_bam 2>; 600 <&qpic_bam 2>;
622 dma-names = "tx", "rx" 601 dma-names = "tx", "rx", "cmd";
623 pinctrl-0 = <&qpic_pin 602 pinctrl-0 = <&qpic_pins>;
624 pinctrl-names = "defau 603 pinctrl-names = "default";
625 status = "disabled"; 604 status = "disabled";
626 }; 605 };
627 606
628 usb_0: usb@8af8800 { 607 usb_0: usb@8af8800 {
629 compatible = "qcom,ipq 608 compatible = "qcom,ipq8074-dwc3", "qcom,dwc3";
630 reg = <0x08af8800 0x40 609 reg = <0x08af8800 0x400>;
631 #address-cells = <1>; 610 #address-cells = <1>;
632 #size-cells = <1>; 611 #size-cells = <1>;
633 ranges; 612 ranges;
634 613
635 clocks = <&gcc GCC_SYS 614 clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
636 <&gcc GCC_USB0 615 <&gcc GCC_USB0_MASTER_CLK>,
637 <&gcc GCC_USB0 616 <&gcc GCC_USB0_SLEEP_CLK>,
638 <&gcc GCC_USB0 617 <&gcc GCC_USB0_MOCK_UTMI_CLK>;
639 clock-names = "cfg_noc 618 clock-names = "cfg_noc",
640 "core", 619 "core",
641 "sleep", 620 "sleep",
642 "mock_utmi"; 621 "mock_utmi";
643 622
644 assigned-clocks = <&gc 623 assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
645 <&gc 624 <&gcc GCC_USB0_MASTER_CLK>,
646 <&gc 625 <&gcc GCC_USB0_MOCK_UTMI_CLK>;
647 assigned-clock-rates = 626 assigned-clock-rates = <133330000>,
648 627 <133330000>,
649 628 <19200000>;
650 629
651 interrupts = <GIC_SPI <<
652 <GIC_SPI <<
653 <GIC_SPI <<
654 interrupt-names = "pwr <<
655 "qus <<
656 "ss_ <<
657 <<
658 power-domains = <&gcc 630 power-domains = <&gcc USB0_GDSC>;
659 631
660 resets = <&gcc GCC_USB 632 resets = <&gcc GCC_USB0_BCR>;
661 status = "disabled"; 633 status = "disabled";
662 634
663 dwc_0: usb@8a00000 { 635 dwc_0: usb@8a00000 {
664 compatible = " 636 compatible = "snps,dwc3";
665 reg = <0x8a000 637 reg = <0x8a00000 0xcd00>;
666 interrupts = < 638 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
667 phys = <&qusb_ 639 phys = <&qusb_phy_0>, <&ssphy_0>;
668 phy-names = "u 640 phy-names = "usb2-phy", "usb3-phy";
669 snps,parkmode- <<
670 snps,is-utmi-l 641 snps,is-utmi-l1-suspend;
671 snps,hird-thre 642 snps,hird-threshold = /bits/ 8 <0x0>;
672 snps,dis_u2_su 643 snps,dis_u2_susphy_quirk;
673 snps,dis_u3_su 644 snps,dis_u3_susphy_quirk;
674 dr_mode = "hos 645 dr_mode = "host";
675 }; 646 };
676 }; 647 };
677 648
678 usb_1: usb@8cf8800 { 649 usb_1: usb@8cf8800 {
679 compatible = "qcom,ipq 650 compatible = "qcom,ipq8074-dwc3", "qcom,dwc3";
680 reg = <0x08cf8800 0x40 651 reg = <0x08cf8800 0x400>;
681 #address-cells = <1>; 652 #address-cells = <1>;
682 #size-cells = <1>; 653 #size-cells = <1>;
683 ranges; 654 ranges;
684 655
685 clocks = <&gcc GCC_SYS 656 clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>,
686 <&gcc GCC_USB1 657 <&gcc GCC_USB1_MASTER_CLK>,
687 <&gcc GCC_USB1 658 <&gcc GCC_USB1_SLEEP_CLK>,
688 <&gcc GCC_USB1 659 <&gcc GCC_USB1_MOCK_UTMI_CLK>;
689 clock-names = "cfg_noc 660 clock-names = "cfg_noc",
690 "core", 661 "core",
691 "sleep", 662 "sleep",
692 "mock_utmi"; 663 "mock_utmi";
693 664
694 assigned-clocks = <&gc 665 assigned-clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>,
695 <&gc 666 <&gcc GCC_USB1_MASTER_CLK>,
696 <&gc 667 <&gcc GCC_USB1_MOCK_UTMI_CLK>;
697 assigned-clock-rates = 668 assigned-clock-rates = <133330000>,
698 669 <133330000>,
699 670 <19200000>;
700 671
701 interrupts = <GIC_SPI <<
702 <GIC_SPI <<
703 <GIC_SPI <<
704 interrupt-names = "pwr <<
705 "qus <<
706 "ss_ <<
707 <<
708 power-domains = <&gcc 672 power-domains = <&gcc USB1_GDSC>;
709 673
710 resets = <&gcc GCC_USB 674 resets = <&gcc GCC_USB1_BCR>;
711 status = "disabled"; 675 status = "disabled";
712 676
713 dwc_1: usb@8c00000 { 677 dwc_1: usb@8c00000 {
714 compatible = " 678 compatible = "snps,dwc3";
715 reg = <0x8c000 679 reg = <0x8c00000 0xcd00>;
716 interrupts = < 680 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
717 phys = <&qusb_ 681 phys = <&qusb_phy_1>, <&ssphy_1>;
718 phy-names = "u 682 phy-names = "usb2-phy", "usb3-phy";
719 snps,parkmode- <<
720 snps,is-utmi-l 683 snps,is-utmi-l1-suspend;
721 snps,hird-thre 684 snps,hird-threshold = /bits/ 8 <0x0>;
722 snps,dis_u2_su 685 snps,dis_u2_susphy_quirk;
723 snps,dis_u3_su 686 snps,dis_u3_susphy_quirk;
724 dr_mode = "hos 687 dr_mode = "host";
725 }; 688 };
726 }; 689 };
727 690
728 intc: interrupt-controller@b00 691 intc: interrupt-controller@b000000 {
729 compatible = "qcom,msm 692 compatible = "qcom,msm-qgic2";
730 #address-cells = <1>; 693 #address-cells = <1>;
731 #size-cells = <1>; 694 #size-cells = <1>;
732 interrupt-controller; 695 interrupt-controller;
733 #interrupt-cells = <3> 696 #interrupt-cells = <3>;
734 reg = <0x0b000000 0x10 697 reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
735 ranges = <0 0xb00a000 698 ranges = <0 0xb00a000 0xffd>;
736 699
737 v2m@0 { 700 v2m@0 {
738 compatible = " 701 compatible = "arm,gic-v2m-frame";
739 msi-controller 702 msi-controller;
740 reg = <0x0 0xf 703 reg = <0x0 0xffd>;
741 }; 704 };
742 }; 705 };
743 706
744 watchdog: watchdog@b017000 { 707 watchdog: watchdog@b017000 {
745 compatible = "qcom,kps 708 compatible = "qcom,kpss-wdt";
746 reg = <0xb017000 0x100 709 reg = <0xb017000 0x1000>;
747 interrupts = <GIC_SPI 710 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
748 clocks = <&sleep_clk>; 711 clocks = <&sleep_clk>;
749 timeout-sec = <30>; 712 timeout-sec = <30>;
750 }; 713 };
751 714
752 apcs_glb: mailbox@b111000 { 715 apcs_glb: mailbox@b111000 {
753 compatible = "qcom,ipq 716 compatible = "qcom,ipq8074-apcs-apps-global",
754 "qcom,ipq 717 "qcom,ipq6018-apcs-apps-global";
755 reg = <0x0b111000 0x10 718 reg = <0x0b111000 0x1000>;
756 clocks = <&a53pll>, <& 719 clocks = <&a53pll>, <&xo>, <&gcc GPLL0>;
757 clock-names = "pll", " 720 clock-names = "pll", "xo", "gpll0";
758 721
759 #clock-cells = <1>; 722 #clock-cells = <1>;
760 #mbox-cells = <1>; 723 #mbox-cells = <1>;
761 }; 724 };
762 725
763 a53pll: clock@b116000 { 726 a53pll: clock@b116000 {
764 compatible = "qcom,ipq 727 compatible = "qcom,ipq8074-a53pll";
765 reg = <0x0b116000 0x40 728 reg = <0x0b116000 0x40>;
766 #clock-cells = <0>; 729 #clock-cells = <0>;
767 clocks = <&xo>; 730 clocks = <&xo>;
768 clock-names = "xo"; 731 clock-names = "xo";
769 }; 732 };
770 733
771 timer@b120000 { 734 timer@b120000 {
772 #address-cells = <1>; 735 #address-cells = <1>;
773 #size-cells = <1>; 736 #size-cells = <1>;
774 ranges; 737 ranges;
775 compatible = "arm,armv 738 compatible = "arm,armv7-timer-mem";
776 reg = <0x0b120000 0x10 739 reg = <0x0b120000 0x1000>;
777 740
778 frame@b120000 { 741 frame@b120000 {
779 frame-number = 742 frame-number = <0>;
780 interrupts = < 743 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
781 < 744 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
782 reg = <0x0b121 745 reg = <0x0b121000 0x1000>,
783 <0x0b122 746 <0x0b122000 0x1000>;
784 }; 747 };
785 748
786 frame@b123000 { 749 frame@b123000 {
787 frame-number = 750 frame-number = <1>;
788 interrupts = < 751 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
789 reg = <0x0b123 752 reg = <0x0b123000 0x1000>;
790 status = "disa 753 status = "disabled";
791 }; 754 };
792 755
793 frame@b124000 { 756 frame@b124000 {
794 frame-number = 757 frame-number = <2>;
795 interrupts = < 758 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
796 reg = <0x0b124 759 reg = <0x0b124000 0x1000>;
797 status = "disa 760 status = "disabled";
798 }; 761 };
799 762
800 frame@b125000 { 763 frame@b125000 {
801 frame-number = 764 frame-number = <3>;
802 interrupts = < 765 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
803 reg = <0x0b125 766 reg = <0x0b125000 0x1000>;
804 status = "disa 767 status = "disabled";
805 }; 768 };
806 769
807 frame@b126000 { 770 frame@b126000 {
808 frame-number = 771 frame-number = <4>;
809 interrupts = < 772 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
810 reg = <0x0b126 773 reg = <0x0b126000 0x1000>;
811 status = "disa 774 status = "disabled";
812 }; 775 };
813 776
814 frame@b127000 { 777 frame@b127000 {
815 frame-number = 778 frame-number = <5>;
816 interrupts = < 779 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
817 reg = <0x0b127 780 reg = <0x0b127000 0x1000>;
818 status = "disa 781 status = "disabled";
819 }; 782 };
820 783
821 frame@b128000 { 784 frame@b128000 {
822 frame-number = 785 frame-number = <6>;
823 interrupts = < 786 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
824 reg = <0x0b128 787 reg = <0x0b128000 0x1000>;
825 status = "disa 788 status = "disabled";
826 }; 789 };
827 }; 790 };
828 791
829 pcie1: pcie@10000000 { 792 pcie1: pcie@10000000 {
830 compatible = "qcom,pci 793 compatible = "qcom,pcie-ipq8074";
831 reg = <0x10000000 0xf1 794 reg = <0x10000000 0xf1d>,
832 <0x10000f20 0xa8 795 <0x10000f20 0xa8>,
833 <0x00088000 0x20 796 <0x00088000 0x2000>,
834 <0x10100000 0x10 797 <0x10100000 0x1000>;
835 reg-names = "dbi", "el 798 reg-names = "dbi", "elbi", "parf", "config";
836 device_type = "pci"; 799 device_type = "pci";
837 linux,pci-domain = <1> 800 linux,pci-domain = <1>;
838 bus-range = <0x00 0xff 801 bus-range = <0x00 0xff>;
839 num-lanes = <1>; 802 num-lanes = <1>;
840 max-link-speed = <2>; 803 max-link-speed = <2>;
841 #address-cells = <3>; 804 #address-cells = <3>;
842 #size-cells = <2>; 805 #size-cells = <2>;
843 806
844 phys = <&pcie_qmp1>; 807 phys = <&pcie_qmp1>;
845 phy-names = "pciephy"; 808 phy-names = "pciephy";
846 809
847 ranges = <0x81000000 0 810 ranges = <0x81000000 0x0 0x00000000 0x10200000 0x0 0x10000>, /* I/O */
848 <0x82000000 0 811 <0x82000000 0x0 0x10220000 0x10220000 0x0 0xfde0000>; /* MEM */
849 812
850 interrupts = <GIC_SPI 813 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
851 interrupt-names = "msi 814 interrupt-names = "msi";
852 #interrupt-cells = <1> 815 #interrupt-cells = <1>;
853 interrupt-map-mask = < 816 interrupt-map-mask = <0 0 0 0x7>;
854 interrupt-map = <0 0 0 817 interrupt-map = <0 0 0 1 &intc 0 0 142
855 IRQ_T 818 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
856 <0 0 0 819 <0 0 0 2 &intc 0 0 143
857 IRQ_T 820 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
858 <0 0 0 821 <0 0 0 3 &intc 0 0 144
859 IRQ_T 822 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
860 <0 0 0 823 <0 0 0 4 &intc 0 0 145
861 IRQ_T 824 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
862 825
863 clocks = <&gcc GCC_SYS 826 clocks = <&gcc GCC_SYS_NOC_PCIE1_AXI_CLK>,
864 <&gcc GCC_PCI 827 <&gcc GCC_PCIE1_AXI_M_CLK>,
865 <&gcc GCC_PCI 828 <&gcc GCC_PCIE1_AXI_S_CLK>,
866 <&gcc GCC_PCI 829 <&gcc GCC_PCIE1_AHB_CLK>,
867 <&gcc GCC_PCI 830 <&gcc GCC_PCIE1_AUX_CLK>;
868 clock-names = "iface", 831 clock-names = "iface",
869 "axi_m", 832 "axi_m",
870 "axi_s", 833 "axi_s",
871 "ahb", 834 "ahb",
872 "aux"; 835 "aux";
873 resets = <&gcc GCC_PCI 836 resets = <&gcc GCC_PCIE1_PIPE_ARES>,
874 <&gcc GCC_PCI 837 <&gcc GCC_PCIE1_SLEEP_ARES>,
875 <&gcc GCC_PCI 838 <&gcc GCC_PCIE1_CORE_STICKY_ARES>,
876 <&gcc GCC_PCI 839 <&gcc GCC_PCIE1_AXI_MASTER_ARES>,
877 <&gcc GCC_PCI 840 <&gcc GCC_PCIE1_AXI_SLAVE_ARES>,
878 <&gcc GCC_PCI 841 <&gcc GCC_PCIE1_AHB_ARES>,
879 <&gcc GCC_PCI 842 <&gcc GCC_PCIE1_AXI_MASTER_STICKY_ARES>;
880 reset-names = "pipe", 843 reset-names = "pipe",
881 "sleep", 844 "sleep",
882 "sticky" 845 "sticky",
883 "axi_m", 846 "axi_m",
884 "axi_s", 847 "axi_s",
885 "ahb", 848 "ahb",
886 "axi_m_s 849 "axi_m_sticky";
887 status = "disabled"; 850 status = "disabled";
888 <<
889 pcie@0 { <<
890 device_type = <<
891 reg = <0x0 0x0 <<
892 bus-range = <0 <<
893 <<
894 #address-cells <<
895 #size-cells = <<
896 ranges; <<
897 }; <<
898 }; 851 };
899 852
900 pcie0: pcie@20000000 { 853 pcie0: pcie@20000000 {
901 compatible = "qcom,pci 854 compatible = "qcom,pcie-ipq8074-gen3";
902 reg = <0x20000000 0xf1 855 reg = <0x20000000 0xf1d>,
903 <0x20000f20 0xa8 856 <0x20000f20 0xa8>,
904 <0x20001000 0x10 857 <0x20001000 0x1000>,
905 <0x00080000 0x40 858 <0x00080000 0x4000>,
906 <0x20100000 0x10 859 <0x20100000 0x1000>;
907 reg-names = "dbi", "el 860 reg-names = "dbi", "elbi", "atu", "parf", "config";
908 device_type = "pci"; 861 device_type = "pci";
909 linux,pci-domain = <0> 862 linux,pci-domain = <0>;
910 bus-range = <0x00 0xff 863 bus-range = <0x00 0xff>;
911 num-lanes = <1>; 864 num-lanes = <1>;
912 max-link-speed = <3>; 865 max-link-speed = <3>;
913 #address-cells = <3>; 866 #address-cells = <3>;
914 #size-cells = <2>; 867 #size-cells = <2>;
915 868
916 phys = <&pcie_qmp0>; 869 phys = <&pcie_qmp0>;
917 phy-names = "pciephy"; 870 phy-names = "pciephy";
918 871
919 ranges = <0x81000000 0 872 ranges = <0x81000000 0x0 0x00000000 0x20200000 0x0 0x10000>, /* I/O */
920 <0x82000000 0 873 <0x82000000 0x0 0x20220000 0x20220000 0x0 0xfde0000>; /* MEM */
921 874
922 interrupts = <GIC_SPI 875 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
923 interrupt-names = "msi 876 interrupt-names = "msi";
924 #interrupt-cells = <1> 877 #interrupt-cells = <1>;
925 interrupt-map-mask = < 878 interrupt-map-mask = <0 0 0 0x7>;
926 interrupt-map = <0 0 0 879 interrupt-map = <0 0 0 1 &intc 0 0 75
927 IRQ_T 880 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
928 <0 0 0 881 <0 0 0 2 &intc 0 0 78
929 IRQ_T 882 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
930 <0 0 0 883 <0 0 0 3 &intc 0 0 79
931 IRQ_T 884 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
932 <0 0 0 885 <0 0 0 4 &intc 0 0 83
933 IRQ_T 886 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
934 887
935 clocks = <&gcc GCC_SYS 888 clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
936 <&gcc GCC_PCI 889 <&gcc GCC_PCIE0_AXI_M_CLK>,
937 <&gcc GCC_PCI 890 <&gcc GCC_PCIE0_AXI_S_CLK>,
938 <&gcc GCC_PCI 891 <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>,
939 <&gcc GCC_PCI 892 <&gcc GCC_PCIE0_RCHNG_CLK>;
940 clock-names = "iface", 893 clock-names = "iface",
941 "axi_m", 894 "axi_m",
942 "axi_s", 895 "axi_s",
943 "axi_bri 896 "axi_bridge",
944 "rchng"; 897 "rchng";
945 898
946 resets = <&gcc GCC_PCI 899 resets = <&gcc GCC_PCIE0_PIPE_ARES>,
947 <&gcc GCC_PCI 900 <&gcc GCC_PCIE0_SLEEP_ARES>,
948 <&gcc GCC_PCI 901 <&gcc GCC_PCIE0_CORE_STICKY_ARES>,
949 <&gcc GCC_PCI 902 <&gcc GCC_PCIE0_AXI_MASTER_ARES>,
950 <&gcc GCC_PCI 903 <&gcc GCC_PCIE0_AXI_SLAVE_ARES>,
951 <&gcc GCC_PCI 904 <&gcc GCC_PCIE0_AHB_ARES>,
952 <&gcc GCC_PCI 905 <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>,
953 <&gcc GCC_PCI 906 <&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>;
954 reset-names = "pipe", 907 reset-names = "pipe",
955 "sleep", 908 "sleep",
956 "sticky" 909 "sticky",
957 "axi_m", 910 "axi_m",
958 "axi_s", 911 "axi_s",
959 "ahb", 912 "ahb",
960 "axi_m_s 913 "axi_m_sticky",
961 "axi_s_s 914 "axi_s_sticky";
962 status = "disabled"; 915 status = "disabled";
963 <<
964 pcie@0 { <<
965 device_type = <<
966 reg = <0x0 0x0 <<
967 bus-range = <0 <<
968 <<
969 #address-cells <<
970 #size-cells = <<
971 ranges; <<
972 }; <<
973 }; 916 };
974 }; 917 };
975 918
976 timer { 919 timer {
977 compatible = "arm,armv8-timer" 920 compatible = "arm,armv8-timer";
978 interrupts = <GIC_PPI 2 (GIC_C 921 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
979 <GIC_PPI 3 (GIC_C 922 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
980 <GIC_PPI 4 (GIC_C 923 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
981 <GIC_PPI 1 (GIC_C 924 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
982 }; 925 };
983 926
984 thermal-zones { 927 thermal-zones {
985 nss-top-thermal { 928 nss-top-thermal {
986 polling-delay-passive 929 polling-delay-passive = <250>;
>> 930 polling-delay = <1000>;
987 931
988 thermal-sensors = <&ts 932 thermal-sensors = <&tsens 4>;
989 933
990 trips { 934 trips {
991 nss-top-crit { 935 nss-top-crit {
992 temper 936 temperature = <110000>;
993 hyster 937 hysteresis = <1000>;
994 type = 938 type = "critical";
995 }; 939 };
996 }; 940 };
997 }; 941 };
998 942
999 nss0-thermal { 943 nss0-thermal {
1000 polling-delay-passive 944 polling-delay-passive = <250>;
>> 945 polling-delay = <1000>;
1001 946
1002 thermal-sensors = <&t 947 thermal-sensors = <&tsens 5>;
1003 948
1004 trips { 949 trips {
1005 nss-0-crit { 950 nss-0-crit {
1006 tempe 951 temperature = <110000>;
1007 hyste 952 hysteresis = <1000>;
1008 type 953 type = "critical";
1009 }; 954 };
1010 }; 955 };
1011 }; 956 };
1012 957
1013 nss1-thermal { 958 nss1-thermal {
1014 polling-delay-passive 959 polling-delay-passive = <250>;
>> 960 polling-delay = <1000>;
1015 961
1016 thermal-sensors = <&t 962 thermal-sensors = <&tsens 6>;
1017 963
1018 trips { 964 trips {
1019 nss-1-crit { 965 nss-1-crit {
1020 tempe 966 temperature = <110000>;
1021 hyste 967 hysteresis = <1000>;
1022 type 968 type = "critical";
1023 }; 969 };
1024 }; 970 };
1025 }; 971 };
1026 972
1027 wcss-phya0-thermal { 973 wcss-phya0-thermal {
1028 polling-delay-passive 974 polling-delay-passive = <250>;
>> 975 polling-delay = <1000>;
1029 976
1030 thermal-sensors = <&t 977 thermal-sensors = <&tsens 7>;
1031 978
1032 trips { 979 trips {
1033 wcss-phya0-cr 980 wcss-phya0-crit {
1034 tempe 981 temperature = <110000>;
1035 hyste 982 hysteresis = <1000>;
1036 type 983 type = "critical";
1037 }; 984 };
1038 }; 985 };
1039 }; 986 };
1040 987
1041 wcss-phya1-thermal { 988 wcss-phya1-thermal {
1042 polling-delay-passive 989 polling-delay-passive = <250>;
>> 990 polling-delay = <1000>;
1043 991
1044 thermal-sensors = <&t 992 thermal-sensors = <&tsens 8>;
1045 993
1046 trips { 994 trips {
1047 wcss-phya1-cr 995 wcss-phya1-crit {
1048 tempe 996 temperature = <110000>;
1049 hyste 997 hysteresis = <1000>;
1050 type 998 type = "critical";
1051 }; 999 };
1052 }; 1000 };
1053 }; 1001 };
1054 1002
1055 cpu0_thermal: cpu0-thermal { 1003 cpu0_thermal: cpu0-thermal {
1056 polling-delay-passive 1004 polling-delay-passive = <250>;
>> 1005 polling-delay = <1000>;
1057 1006
1058 thermal-sensors = <&t 1007 thermal-sensors = <&tsens 9>;
1059 1008
1060 trips { 1009 trips {
1061 cpu0-crit { 1010 cpu0-crit {
1062 tempe 1011 temperature = <110000>;
1063 hyste 1012 hysteresis = <1000>;
1064 type 1013 type = "critical";
1065 }; 1014 };
1066 }; 1015 };
1067 }; 1016 };
1068 1017
1069 cpu1_thermal: cpu1-thermal { 1018 cpu1_thermal: cpu1-thermal {
1070 polling-delay-passive 1019 polling-delay-passive = <250>;
>> 1020 polling-delay = <1000>;
1071 1021
1072 thermal-sensors = <&t 1022 thermal-sensors = <&tsens 10>;
1073 1023
1074 trips { 1024 trips {
1075 cpu1-crit { 1025 cpu1-crit {
1076 tempe 1026 temperature = <110000>;
1077 hyste 1027 hysteresis = <1000>;
1078 type 1028 type = "critical";
1079 }; 1029 };
1080 }; 1030 };
1081 }; 1031 };
1082 1032
1083 cpu2_thermal: cpu2-thermal { 1033 cpu2_thermal: cpu2-thermal {
1084 polling-delay-passive 1034 polling-delay-passive = <250>;
>> 1035 polling-delay = <1000>;
1085 1036
1086 thermal-sensors = <&t 1037 thermal-sensors = <&tsens 11>;
1087 1038
1088 trips { 1039 trips {
1089 cpu2-crit { 1040 cpu2-crit {
1090 tempe 1041 temperature = <110000>;
1091 hyste 1042 hysteresis = <1000>;
1092 type 1043 type = "critical";
1093 }; 1044 };
1094 }; 1045 };
1095 }; 1046 };
1096 1047
1097 cpu3_thermal: cpu3-thermal { 1048 cpu3_thermal: cpu3-thermal {
1098 polling-delay-passive 1049 polling-delay-passive = <250>;
>> 1050 polling-delay = <1000>;
1099 1051
1100 thermal-sensors = <&t 1052 thermal-sensors = <&tsens 12>;
1101 1053
1102 trips { 1054 trips {
1103 cpu3-crit { 1055 cpu3-crit {
1104 tempe 1056 temperature = <110000>;
1105 hyste 1057 hysteresis = <1000>;
1106 type 1058 type = "critical";
1107 }; 1059 };
1108 }; 1060 };
1109 }; 1061 };
1110 1062
1111 cluster_thermal: cluster-ther 1063 cluster_thermal: cluster-thermal {
1112 polling-delay-passive 1064 polling-delay-passive = <250>;
>> 1065 polling-delay = <1000>;
1113 1066
1114 thermal-sensors = <&t 1067 thermal-sensors = <&tsens 13>;
1115 1068
1116 trips { 1069 trips {
1117 cluster-crit 1070 cluster-crit {
1118 tempe 1071 temperature = <110000>;
1119 hyste 1072 hysteresis = <1000>;
1120 type 1073 type = "critical";
1121 }; 1074 };
1122 }; 1075 };
1123 }; 1076 };
1124 1077
1125 wcss-phyb0-thermal { 1078 wcss-phyb0-thermal {
1126 polling-delay-passive 1079 polling-delay-passive = <250>;
>> 1080 polling-delay = <1000>;
1127 1081
1128 thermal-sensors = <&t 1082 thermal-sensors = <&tsens 14>;
1129 1083
1130 trips { 1084 trips {
1131 wcss-phyb0-cr 1085 wcss-phyb0-crit {
1132 tempe 1086 temperature = <110000>;
1133 hyste 1087 hysteresis = <1000>;
1134 type 1088 type = "critical";
1135 }; 1089 };
1136 }; 1090 };
1137 }; 1091 };
1138 1092
1139 wcss-phyb1-thermal { 1093 wcss-phyb1-thermal {
1140 polling-delay-passive 1094 polling-delay-passive = <250>;
>> 1095 polling-delay = <1000>;
1141 1096
1142 thermal-sensors = <&t 1097 thermal-sensors = <&tsens 15>;
1143 1098
1144 trips { 1099 trips {
1145 wcss-phyb1-cr 1100 wcss-phyb1-crit {
1146 tempe 1101 temperature = <110000>;
1147 hyste 1102 hysteresis = <1000>;
1148 type 1103 type = "critical";
1149 }; 1104 };
1150 }; 1105 };
1151 }; 1106 };
1152 }; 1107 };
1153 }; 1108 };
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