1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3
2 /*
3 * IPQ9574 SoC device tree source
4 *
5 * Copyright (c) 2020-2021 The Linux Foundatio
6 * Copyright (c) 2023, Qualcomm Innovation Cen
7 */
8
9 #include <dt-bindings/clock/qcom,apss-ipq.h>
10 #include <dt-bindings/clock/qcom,ipq9574-gcc.h
11 #include <dt-bindings/interconnect/qcom,ipq957
12 #include <dt-bindings/interrupt-controller/arm
13 #include <dt-bindings/reset/qcom,ipq9574-gcc.h
14 #include <dt-bindings/thermal/thermal.h>
15
16 / {
17 interrupt-parent = <&intc>;
18 #address-cells = <2>;
19 #size-cells = <2>;
20
21 clocks {
22 sleep_clk: sleep-clk {
23 compatible = "fixed-cl
24 #clock-cells = <0>;
25 };
26
27 xo_board_clk: xo-board-clk {
28 compatible = "fixed-cl
29 #clock-cells = <0>;
30 };
31 };
32
33 cpus {
34 #address-cells = <1>;
35 #size-cells = <0>;
36
37 CPU0: cpu@0 {
38 device_type = "cpu";
39 compatible = "arm,cort
40 reg = <0x0>;
41 enable-method = "psci"
42 next-level-cache = <&L
43 clocks = <&apcs_glb AP
44 clock-names = "cpu";
45 operating-points-v2 =
46 cpu-supply = <&ipq9574
47 #cooling-cells = <2>;
48 };
49
50 CPU1: cpu@1 {
51 device_type = "cpu";
52 compatible = "arm,cort
53 reg = <0x1>;
54 enable-method = "psci"
55 next-level-cache = <&L
56 clocks = <&apcs_glb AP
57 clock-names = "cpu";
58 operating-points-v2 =
59 cpu-supply = <&ipq9574
60 #cooling-cells = <2>;
61 };
62
63 CPU2: cpu@2 {
64 device_type = "cpu";
65 compatible = "arm,cort
66 reg = <0x2>;
67 enable-method = "psci"
68 next-level-cache = <&L
69 clocks = <&apcs_glb AP
70 clock-names = "cpu";
71 operating-points-v2 =
72 cpu-supply = <&ipq9574
73 #cooling-cells = <2>;
74 };
75
76 CPU3: cpu@3 {
77 device_type = "cpu";
78 compatible = "arm,cort
79 reg = <0x3>;
80 enable-method = "psci"
81 next-level-cache = <&L
82 clocks = <&apcs_glb AP
83 clock-names = "cpu";
84 operating-points-v2 =
85 cpu-supply = <&ipq9574
86 #cooling-cells = <2>;
87 };
88
89 L2_0: l2-cache {
90 compatible = "cache";
91 cache-level = <2>;
92 cache-unified;
93 };
94 };
95
96 firmware {
97 scm {
98 compatible = "qcom,scm
99 qcom,dload-mode = <&tc
100 };
101 };
102
103 memory@40000000 {
104 device_type = "memory";
105 /* We expect the bootloader to
106 reg = <0x0 0x40000000 0x0 0x0>
107 };
108
109 cpu_opp_table: opp-table-cpu {
110 compatible = "operating-points
111 opp-shared;
112 nvmem-cells = <&cpu_speed_bin>
113
114 opp-936000000 {
115 opp-hz = /bits/ 64 <93
116 opp-microvolt = <72500
117 opp-supported-hw = <0x
118 clock-latency-ns = <20
119 };
120
121 opp-1104000000 {
122 opp-hz = /bits/ 64 <11
123 opp-microvolt = <78750
124 opp-supported-hw = <0x
125 clock-latency-ns = <20
126 };
127
128 opp-1200000000 {
129 opp-hz = /bits/ 64 <12
130 opp-microvolt = <86250
131 opp-supported-hw = <0x
132 clock-latency-ns = <20
133 };
134
135 opp-1416000000 {
136 opp-hz = /bits/ 64 <14
137 opp-microvolt = <86250
138 opp-supported-hw = <0x
139 clock-latency-ns = <20
140 };
141
142 opp-1488000000 {
143 opp-hz = /bits/ 64 <14
144 opp-microvolt = <92500
145 opp-supported-hw = <0x
146 clock-latency-ns = <20
147 };
148
149 opp-1800000000 {
150 opp-hz = /bits/ 64 <18
151 opp-microvolt = <98750
152 opp-supported-hw = <0x
153 clock-latency-ns = <20
154 };
155
156 opp-2208000000 {
157 opp-hz = /bits/ 64 <22
158 opp-microvolt = <10625
159 opp-supported-hw = <0x
160 clock-latency-ns = <20
161 };
162 };
163
164 pmu {
165 compatible = "arm,cortex-a73-p
166 interrupts = <GIC_PPI 7 (GIC_C
167 };
168
169 psci {
170 compatible = "arm,psci-1.0";
171 method = "smc";
172 };
173
174 rpm: remoteproc {
175 compatible = "qcom,ipq9574-rpm
176
177 glink-edge {
178 compatible = "qcom,gli
179 interrupts = <GIC_SPI
180 qcom,rpm-msg-ram = <&r
181 mboxes = <&apcs_glb 0>
182
183 rpm_requests: rpm-requ
184 compatible = "
185 qcom,glink-cha
186 };
187 };
188 };
189
190 reserved-memory {
191 #address-cells = <2>;
192 #size-cells = <2>;
193 ranges;
194
195 bootloader@4a100000 {
196 reg = <0x0 0x4a100000
197 no-map;
198 };
199
200 sbl@4a500000 {
201 reg = <0x0 0x4a500000
202 no-map;
203 };
204
205 tz_region: tz@4a600000 {
206 reg = <0x0 0x4a600000
207 no-map;
208 };
209
210 smem@4aa00000 {
211 compatible = "qcom,sme
212 reg = <0x0 0x4aa00000
213 hwlocks = <&tcsr_mutex
214 no-map;
215 };
216 };
217
218 soc: soc@0 {
219 compatible = "simple-bus";
220 #address-cells = <1>;
221 #size-cells = <1>;
222 ranges = <0 0 0 0xffffffff>;
223
224 rpm_msg_ram: sram@60000 {
225 compatible = "qcom,rpm
226 reg = <0x00060000 0x60
227 };
228
229 rng: rng@e3000 {
230 compatible = "qcom,prn
231 reg = <0x000e3000 0x10
232 clocks = <&gcc GCC_PRN
233 clock-names = "core";
234 };
235
236 mdio: mdio@90000 {
237 compatible = "qcom,ip
238 reg = <0x00090000 0x64
239 #address-cells = <1>;
240 #size-cells = <0>;
241 clocks = <&gcc GCC_MDI
242 clock-names = "gcc_mdi
243 status = "disabled";
244 };
245
246 qfprom: efuse@a4000 {
247 compatible = "qcom,ipq
248 reg = <0x000a4000 0x5a
249 #address-cells = <1>;
250 #size-cells = <1>;
251
252 cpu_speed_bin: cpu-spe
253 reg = <0x15 0x
254 bits = <7 2>;
255 };
256 };
257
258 cryptobam: dma-controller@7040
259 compatible = "qcom,bam
260 reg = <0x00704000 0x20
261 interrupts = <GIC_SPI
262 #dma-cells = <1>;
263 qcom,ee = <1>;
264 qcom,controlled-remote
265 };
266
267 crypto: crypto@73a000 {
268 compatible = "qcom,ipq
269 reg = <0x0073a000 0x60
270 clocks = <&gcc GCC_CRY
271 <&gcc GCC_CRY
272 <&gcc GCC_CRY
273 clock-names = "iface",
274 dmas = <&cryptobam 2>,
275 dma-names = "rx", "tx"
276 };
277
278 tsens: thermal-sensor@4a9000 {
279 compatible = "qcom,ipq
280 reg = <0x004a9000 0x10
281 <0x004a8000 0x10
282 interrupts = <GIC_SPI
283 interrupt-names = "com
284 #qcom,sensors = <16>;
285 #thermal-sensor-cells
286 };
287
288 tlmm: pinctrl@1000000 {
289 compatible = "qcom,ipq
290 reg = <0x01000000 0x30
291 interrupts = <GIC_SPI
292 gpio-controller;
293 #gpio-cells = <2>;
294 gpio-ranges = <&tlmm 0
295 interrupt-controller;
296 #interrupt-cells = <2>
297
298 uart2_pins: uart2-stat
299 pins = "gpio34
300 function = "bl
301 drive-strength
302 bias-disable;
303 };
304 };
305
306 gcc: clock-controller@1800000
307 compatible = "qcom,ipq
308 reg = <0x01800000 0x80
309 clocks = <&xo_board_cl
310 <&sleep_clk>,
311 <0>,
312 <0>,
313 <0>,
314 <0>,
315 <0>,
316 <0>;
317 #clock-cells = <1>;
318 #reset-cells = <1>;
319 #interconnect-cells =
320 };
321
322 tcsr_mutex: hwlock@1905000 {
323 compatible = "qcom,tcs
324 reg = <0x01905000 0x20
325 #hwlock-cells = <1>;
326 };
327
328 tcsr: syscon@1937000 {
329 compatible = "qcom,tcs
330 reg = <0x01937000 0x21
331 };
332
333 sdhc_1: mmc@7804000 {
334 compatible = "qcom,ipq
335 reg = <0x07804000 0x10
336 <0x07805000 0x10
337 <0x07808000 0x20
338 reg-names = "hc", "cqh
339
340 interrupts = <GIC_SPI
341 <GIC_SPI
342 interrupt-names = "hc_
343
344 clocks = <&gcc GCC_SDC
345 <&gcc GCC_SDC
346 <&xo_board_cl
347 <&gcc GCC_SDC
348 clock-names = "iface",
349 non-removable;
350 supports-cqe;
351 status = "disabled";
352 };
353
354 blsp_dma: dma-controller@78840
355 compatible = "qcom,bam
356 reg = <0x07884000 0x2b
357 interrupts = <GIC_SPI
358 clocks = <&gcc GCC_BLS
359 clock-names = "bam_clk
360 #dma-cells = <1>;
361 qcom,ee = <0>;
362 };
363
364 blsp1_uart0: serial@78af000 {
365 compatible = "qcom,msm
366 reg = <0x078af000 0x20
367 interrupts = <GIC_SPI
368 clocks = <&gcc GCC_BLS
369 <&gcc GCC_BLS
370 clock-names = "core",
371 status = "disabled";
372 };
373
374 blsp1_uart1: serial@78b0000 {
375 compatible = "qcom,msm
376 reg = <0x078b0000 0x20
377 interrupts = <GIC_SPI
378 clocks = <&gcc GCC_BLS
379 <&gcc GCC_BLS
380 clock-names = "core",
381 status = "disabled";
382 };
383
384 blsp1_uart2: serial@78b1000 {
385 compatible = "qcom,msm
386 reg = <0x078b1000 0x20
387 interrupts = <GIC_SPI
388 clocks = <&gcc GCC_BLS
389 <&gcc GCC_BLS
390 clock-names = "core",
391 status = "disabled";
392 };
393
394 blsp1_uart3: serial@78b2000 {
395 compatible = "qcom,msm
396 reg = <0x078b2000 0x20
397 interrupts = <GIC_SPI
398 clocks = <&gcc GCC_BLS
399 <&gcc GCC_BLS
400 clock-names = "core",
401 status = "disabled";
402 };
403
404 blsp1_uart4: serial@78b3000 {
405 compatible = "qcom,msm
406 reg = <0x078b3000 0x20
407 interrupts = <GIC_SPI
408 clocks = <&gcc GCC_BLS
409 <&gcc GCC_BLS
410 clock-names = "core",
411 status = "disabled";
412 };
413
414 blsp1_uart5: serial@78b4000 {
415 compatible = "qcom,msm
416 reg = <0x078b4000 0x20
417 interrupts = <GIC_SPI
418 clocks = <&gcc GCC_BLS
419 <&gcc GCC_BLS
420 clock-names = "core",
421 status = "disabled";
422 };
423
424 blsp1_spi0: spi@78b5000 {
425 compatible = "qcom,spi
426 reg = <0x078b5000 0x60
427 #address-cells = <1>;
428 #size-cells = <0>;
429 interrupts = <GIC_SPI
430 clocks = <&gcc GCC_BLS
431 <&gcc GCC_BLS
432 clock-names = "core",
433 dmas = <&blsp_dma 12>,
434 dma-names = "tx", "rx"
435 status = "disabled";
436 };
437
438 blsp1_i2c1: i2c@78b6000 {
439 compatible = "qcom,i2c
440 reg = <0x078b6000 0x60
441 #address-cells = <1>;
442 #size-cells = <0>;
443 interrupts = <GIC_SPI
444 clocks = <&gcc GCC_BLS
445 <&gcc GCC_BLS
446 clock-names = "core",
447 assigned-clocks = <&gc
448 assigned-clock-rates =
449 dmas = <&blsp_dma 14>,
450 dma-names = "tx", "rx"
451 status = "disabled";
452 };
453
454 blsp1_spi1: spi@78b6000 {
455 compatible = "qcom,spi
456 reg = <0x078b6000 0x60
457 #address-cells = <1>;
458 #size-cells = <0>;
459 interrupts = <GIC_SPI
460 clocks = <&gcc GCC_BLS
461 <&gcc GCC_BLS
462 clock-names = "core",
463 dmas = <&blsp_dma 14>,
464 dma-names = "tx", "rx"
465 status = "disabled";
466 };
467
468 blsp1_i2c2: i2c@78b7000 {
469 compatible = "qcom,i2c
470 reg = <0x078b7000 0x60
471 #address-cells = <1>;
472 #size-cells = <0>;
473 interrupts = <GIC_SPI
474 clocks = <&gcc GCC_BLS
475 <&gcc GCC_BLS
476 clock-names = "core",
477 assigned-clocks = <&gc
478 assigned-clock-rates =
479 dmas = <&blsp_dma 16>,
480 dma-names = "tx", "rx"
481 status = "disabled";
482 };
483
484 blsp1_spi2: spi@78b7000 {
485 compatible = "qcom,spi
486 reg = <0x078b7000 0x60
487 #address-cells = <1>;
488 #size-cells = <0>;
489 interrupts = <GIC_SPI
490 clocks = <&gcc GCC_BLS
491 <&gcc GCC_BLS
492 clock-names = "core",
493 dmas = <&blsp_dma 16>,
494 dma-names = "tx", "rx"
495 status = "disabled";
496 };
497
498 blsp1_i2c3: i2c@78b8000 {
499 compatible = "qcom,i2c
500 reg = <0x078b8000 0x60
501 #address-cells = <1>;
502 #size-cells = <0>;
503 interrupts = <GIC_SPI
504 clocks = <&gcc GCC_BLS
505 <&gcc GCC_BLS
506 clock-names = "core",
507 assigned-clocks = <&gc
508 assigned-clock-rates =
509 dmas = <&blsp_dma 18>,
510 dma-names = "tx", "rx"
511 status = "disabled";
512 };
513
514 blsp1_spi3: spi@78b8000 {
515 compatible = "qcom,spi
516 reg = <0x078b8000 0x60
517 #address-cells = <1>;
518 #size-cells = <0>;
519 interrupts = <GIC_SPI
520 spi-max-frequency = <5
521 clocks = <&gcc GCC_BLS
522 <&gcc GCC_BLS
523 clock-names = "core",
524 dmas = <&blsp_dma 18>,
525 dma-names = "tx", "rx"
526 status = "disabled";
527 };
528
529 blsp1_i2c4: i2c@78b9000 {
530 compatible = "qcom,i2c
531 reg = <0x078b9000 0x60
532 #address-cells = <1>;
533 #size-cells = <0>;
534 interrupts = <GIC_SPI
535 clocks = <&gcc GCC_BLS
536 <&gcc GCC_BLS
537 clock-names = "core",
538 assigned-clocks = <&gc
539 assigned-clock-rates =
540 dmas = <&blsp_dma 20>,
541 dma-names = "tx", "rx"
542 status = "disabled";
543 };
544
545 blsp1_spi4: spi@78b9000 {
546 compatible = "qcom,spi
547 reg = <0x078b9000 0x60
548 #address-cells = <1>;
549 #size-cells = <0>;
550 interrupts = <GIC_SPI
551 clocks = <&gcc GCC_BLS
552 <&gcc GCC_BLS
553 clock-names = "core",
554 dmas = <&blsp_dma 20>,
555 dma-names = "tx", "rx"
556 status = "disabled";
557 };
558
559 usb_0_qusbphy: phy@7b000 {
560 compatible = "qcom,ipq
561 reg = <0x0007b000 0x18
562 #phy-cells = <0>;
563
564 clocks = <&gcc GCC_USB
565 <&xo_board_cl
566 clock-names = "cfg_ahb
567 "ref";
568
569 resets = <&gcc GCC_QUS
570 status = "disabled";
571 };
572
573 usb_0_qmpphy: phy@7d000 {
574 compatible = "qcom,ipq
575 reg = <0x0007d000 0xa0
576 #phy-cells = <0>;
577
578 clocks = <&gcc GCC_USB
579 <&xo_board_cl
580 <&gcc GCC_USB
581 <&gcc GCC_USB
582 clock-names = "aux",
583 "ref",
584 "cfg_ahb
585 "pipe";
586
587 resets = <&gcc GCC_USB
588 <&gcc GCC_USB
589 reset-names = "phy",
590 "phy_phy
591
592 #clock-cells = <0>;
593 clock-output-names = "
594
595 status = "disabled";
596 };
597
598 usb3: usb@8af8800 {
599 compatible = "qcom,ipq
600 reg = <0x08af8800 0x40
601 #address-cells = <1>;
602 #size-cells = <1>;
603 ranges;
604
605 clocks = <&gcc GCC_SNO
606 <&gcc GCC_USB
607 <&gcc GCC_ANO
608 <&gcc GCC_USB
609 <&gcc GCC_USB
610
611 clock-names = "cfg_noc
612 "core",
613 "iface",
614 "sleep",
615 "mock_ut
616
617 assigned-clocks = <&gc
618 <&gc
619 assigned-clock-rates =
620
621
622 interrupts-extended =
623 interrupt-names = "pwr
624
625 resets = <&gcc GCC_USB
626 status = "disabled";
627
628 usb_0_dwc3: usb@8a0000
629 compatible = "
630 reg = <0x8a000
631 clocks = <&gcc
632 clock-names =
633 interrupts = <
634 phys = <&usb_0
635 phy-names = "u
636 tx-fifo-resize
637 snps,is-utmi-l
638 snps,hird-thre
639 snps,dis_u2_su
640 snps,dis_u3_su
641 };
642 };
643
644 intc: interrupt-controller@b00
645 compatible = "qcom,msm
646 reg = <0x0b000000 0x10
647 <0x0b002000 0x20
648 <0x0b001000 0x10
649 <0x0b004000 0x20
650 #address-cells = <1>;
651 #size-cells = <1>;
652 interrupt-controller;
653 #interrupt-cells = <3>
654 interrupts = <GIC_PPI
655 ranges = <0 0x0b00c000
656
657 v2m0: v2m@0 {
658 compatible = "
659 reg = <0x00000
660 msi-controller
661 };
662
663 v2m1: v2m@1000 {
664 compatible = "
665 reg = <0x00001
666 msi-controller
667 };
668
669 v2m2: v2m@2000 {
670 compatible = "
671 reg = <0x00002
672 msi-controller
673 };
674 };
675
676 watchdog: watchdog@b017000 {
677 compatible = "qcom,aps
678 reg = <0x0b017000 0x10
679 interrupts = <GIC_SPI
680 clocks = <&sleep_clk>;
681 timeout-sec = <30>;
682 };
683
684 apcs_glb: mailbox@b111000 {
685 compatible = "qcom,ipq
686 "qcom,ipq
687 reg = <0x0b111000 0x10
688 #clock-cells = <1>;
689 clocks = <&a73pll>, <&
690 clock-names = "pll", "
691 #mbox-cells = <1>;
692 };
693
694 a73pll: clock@b116000 {
695 compatible = "qcom,ipq
696 reg = <0x0b116000 0x40
697 #clock-cells = <0>;
698 clocks = <&xo_board_cl
699 clock-names = "xo";
700 };
701
702 timer@b120000 {
703 compatible = "arm,armv
704 reg = <0x0b120000 0x10
705 #address-cells = <1>;
706 #size-cells = <1>;
707 ranges;
708
709 frame@b120000 {
710 reg = <0x0b121
711 <0x0b122
712 frame-number =
713 interrupts = <
714 <
715 };
716
717 frame@b123000 {
718 reg = <0x0b123
719 frame-number =
720 interrupts = <
721 status = "disa
722 };
723
724 frame@b124000 {
725 reg = <0x0b124
726 frame-number =
727 interrupts = <
728 status = "disa
729 };
730
731 frame@b125000 {
732 reg = <0x0b125
733 frame-number =
734 interrupts = <
735 status = "disa
736 };
737
738 frame@b126000 {
739 reg = <0x0b126
740 frame-number =
741 interrupts = <
742 status = "disa
743 };
744
745 frame@b127000 {
746 reg = <0x0b127
747 frame-number =
748 interrupts = <
749 status = "disa
750 };
751
752 frame@b128000 {
753 reg = <0x0b128
754 frame-number =
755 interrupts = <
756 status = "disa
757 };
758 };
759 };
760
761 thermal-zones {
762 nss-top-thermal {
763 thermal-sensors = <&ts
764
765 trips {
766 nss-top-critic
767 temper
768 hyster
769 type =
770 };
771 };
772 };
773
774 ubi-0-thermal {
775 thermal-sensors = <&ts
776
777 trips {
778 ubi_0-critical
779 temper
780 hyster
781 type =
782 };
783 };
784 };
785
786 ubi-1-thermal {
787 thermal-sensors = <&ts
788
789 trips {
790 ubi_1-critical
791 temper
792 hyster
793 type =
794 };
795 };
796 };
797
798 ubi-2-thermal {
799 thermal-sensors = <&ts
800
801 trips {
802 ubi_2-critical
803 temper
804 hyster
805 type =
806 };
807 };
808 };
809
810 ubi-3-thermal {
811 thermal-sensors = <&ts
812
813 trips {
814 ubi_3-critical
815 temper
816 hyster
817 type =
818 };
819 };
820 };
821
822 cpuss0-thermal {
823 thermal-sensors = <&ts
824
825 trips {
826 cpu-critical {
827 temper
828 hyster
829 type =
830 };
831 };
832 };
833
834 cpuss1-thermal {
835 thermal-sensors = <&ts
836
837 trips {
838 cpu-critical {
839 temper
840 hyster
841 type =
842 };
843 };
844 };
845
846 cpu0-thermal {
847 thermal-sensors = <&ts
848
849 trips {
850 cpu0_crit: cpu
851 temper
852 hyster
853 type =
854 };
855
856 cpu0_alert: cp
857 temper
858 hyster
859 type =
860 };
861 };
862
863 cooling-maps {
864 map0 {
865 trip =
866 coolin
867
868
869
870 };
871 };
872 };
873
874 cpu1-thermal {
875 thermal-sensors = <&ts
876
877 trips {
878 cpu1_crit: cpu
879 temper
880 hyster
881 type =
882 };
883
884 cpu1_alert: cp
885 temper
886 hyster
887 type =
888 };
889 };
890
891 cooling-maps {
892 map0 {
893 trip =
894 coolin
895
896
897
898 };
899 };
900 };
901
902 cpu2-thermal {
903 thermal-sensors = <&ts
904
905 trips {
906 cpu2_crit: cpu
907 temper
908 hyster
909 type =
910 };
911
912 cpu2_alert: cp
913 temper
914 hyster
915 type =
916 };
917 };
918
919 cooling-maps {
920 map0 {
921 trip =
922 coolin
923
924
925
926 };
927 };
928 };
929
930 cpu3-thermal {
931 thermal-sensors = <&ts
932
933 trips {
934 cpu3_crit: cpu
935 temper
936 hyster
937 type =
938 };
939
940 cpu3_alert: cp
941 temper
942 hyster
943 type =
944 };
945 };
946
947 cooling-maps {
948 map0 {
949 trip =
950 coolin
951
952
953
954 };
955 };
956 };
957
958 wcss-phyb-thermal {
959 thermal-sensors = <&ts
960
961 trips {
962 wcss_phyb-crit
963 temper
964 hyster
965 type =
966 };
967 };
968 };
969
970 top-glue-thermal {
971 thermal-sensors = <&ts
972
973 trips {
974 top_glue-criti
975 temper
976 hyster
977 type =
978 };
979 };
980 };
981 };
982
983 timer {
984 compatible = "arm,armv8-timer"
985 interrupts = <GIC_PPI 2 (GIC_C
986 <GIC_PPI 3 (GIC_C
987 <GIC_PPI 4 (GIC_C
988 <GIC_PPI 1 (GIC_C
989 };
990 };
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