1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3 1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2 /* 2 /*
3 * IPQ9574 SoC device tree source 3 * IPQ9574 SoC device tree source
4 * 4 *
5 * Copyright (c) 2020-2021 The Linux Foundatio 5 * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
6 * Copyright (c) 2023, Qualcomm Innovation Cen 6 * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
7 */ 7 */
8 8
9 #include <dt-bindings/clock/qcom,apss-ipq.h> 9 #include <dt-bindings/clock/qcom,apss-ipq.h>
10 #include <dt-bindings/clock/qcom,ipq9574-gcc.h 10 #include <dt-bindings/clock/qcom,ipq9574-gcc.h>
11 #include <dt-bindings/interconnect/qcom,ipq957 <<
12 #include <dt-bindings/interrupt-controller/arm 11 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/reset/qcom,ipq9574-gcc.h 12 #include <dt-bindings/reset/qcom,ipq9574-gcc.h>
14 #include <dt-bindings/thermal/thermal.h> 13 #include <dt-bindings/thermal/thermal.h>
15 14
16 / { 15 / {
17 interrupt-parent = <&intc>; 16 interrupt-parent = <&intc>;
18 #address-cells = <2>; 17 #address-cells = <2>;
19 #size-cells = <2>; 18 #size-cells = <2>;
20 19
21 clocks { 20 clocks {
22 sleep_clk: sleep-clk { 21 sleep_clk: sleep-clk {
23 compatible = "fixed-cl 22 compatible = "fixed-clock";
24 #clock-cells = <0>; 23 #clock-cells = <0>;
25 }; 24 };
26 25
27 xo_board_clk: xo-board-clk { 26 xo_board_clk: xo-board-clk {
28 compatible = "fixed-cl 27 compatible = "fixed-clock";
29 #clock-cells = <0>; 28 #clock-cells = <0>;
30 }; 29 };
31 }; 30 };
32 31
33 cpus { 32 cpus {
34 #address-cells = <1>; 33 #address-cells = <1>;
35 #size-cells = <0>; 34 #size-cells = <0>;
36 35
37 CPU0: cpu@0 { 36 CPU0: cpu@0 {
38 device_type = "cpu"; 37 device_type = "cpu";
39 compatible = "arm,cort 38 compatible = "arm,cortex-a73";
40 reg = <0x0>; 39 reg = <0x0>;
41 enable-method = "psci" 40 enable-method = "psci";
42 next-level-cache = <&L 41 next-level-cache = <&L2_0>;
43 clocks = <&apcs_glb AP 42 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
44 clock-names = "cpu"; 43 clock-names = "cpu";
45 operating-points-v2 = 44 operating-points-v2 = <&cpu_opp_table>;
46 cpu-supply = <&ipq9574 45 cpu-supply = <&ipq9574_s1>;
47 #cooling-cells = <2>; 46 #cooling-cells = <2>;
48 }; 47 };
49 48
50 CPU1: cpu@1 { 49 CPU1: cpu@1 {
51 device_type = "cpu"; 50 device_type = "cpu";
52 compatible = "arm,cort 51 compatible = "arm,cortex-a73";
53 reg = <0x1>; 52 reg = <0x1>;
54 enable-method = "psci" 53 enable-method = "psci";
55 next-level-cache = <&L 54 next-level-cache = <&L2_0>;
56 clocks = <&apcs_glb AP 55 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
57 clock-names = "cpu"; 56 clock-names = "cpu";
58 operating-points-v2 = 57 operating-points-v2 = <&cpu_opp_table>;
59 cpu-supply = <&ipq9574 58 cpu-supply = <&ipq9574_s1>;
60 #cooling-cells = <2>; 59 #cooling-cells = <2>;
61 }; 60 };
62 61
63 CPU2: cpu@2 { 62 CPU2: cpu@2 {
64 device_type = "cpu"; 63 device_type = "cpu";
65 compatible = "arm,cort 64 compatible = "arm,cortex-a73";
66 reg = <0x2>; 65 reg = <0x2>;
67 enable-method = "psci" 66 enable-method = "psci";
68 next-level-cache = <&L 67 next-level-cache = <&L2_0>;
69 clocks = <&apcs_glb AP 68 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
70 clock-names = "cpu"; 69 clock-names = "cpu";
71 operating-points-v2 = 70 operating-points-v2 = <&cpu_opp_table>;
72 cpu-supply = <&ipq9574 71 cpu-supply = <&ipq9574_s1>;
73 #cooling-cells = <2>; 72 #cooling-cells = <2>;
74 }; 73 };
75 74
76 CPU3: cpu@3 { 75 CPU3: cpu@3 {
77 device_type = "cpu"; 76 device_type = "cpu";
78 compatible = "arm,cort 77 compatible = "arm,cortex-a73";
79 reg = <0x3>; 78 reg = <0x3>;
80 enable-method = "psci" 79 enable-method = "psci";
81 next-level-cache = <&L 80 next-level-cache = <&L2_0>;
82 clocks = <&apcs_glb AP 81 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
83 clock-names = "cpu"; 82 clock-names = "cpu";
84 operating-points-v2 = 83 operating-points-v2 = <&cpu_opp_table>;
85 cpu-supply = <&ipq9574 84 cpu-supply = <&ipq9574_s1>;
86 #cooling-cells = <2>; 85 #cooling-cells = <2>;
87 }; 86 };
88 87
89 L2_0: l2-cache { 88 L2_0: l2-cache {
90 compatible = "cache"; 89 compatible = "cache";
91 cache-level = <2>; 90 cache-level = <2>;
92 cache-unified; 91 cache-unified;
93 }; 92 };
94 }; 93 };
95 94
96 firmware { 95 firmware {
97 scm { 96 scm {
98 compatible = "qcom,scm 97 compatible = "qcom,scm-ipq9574", "qcom,scm";
99 qcom,dload-mode = <&tc 98 qcom,dload-mode = <&tcsr 0x6100>;
100 }; 99 };
101 }; 100 };
102 101
103 memory@40000000 { 102 memory@40000000 {
104 device_type = "memory"; 103 device_type = "memory";
105 /* We expect the bootloader to 104 /* We expect the bootloader to fill in the size */
106 reg = <0x0 0x40000000 0x0 0x0> 105 reg = <0x0 0x40000000 0x0 0x0>;
107 }; 106 };
108 107
109 cpu_opp_table: opp-table-cpu { 108 cpu_opp_table: opp-table-cpu {
110 compatible = "operating-points 109 compatible = "operating-points-v2-kryo-cpu";
111 opp-shared; 110 opp-shared;
112 nvmem-cells = <&cpu_speed_bin> 111 nvmem-cells = <&cpu_speed_bin>;
113 112
114 opp-936000000 { 113 opp-936000000 {
115 opp-hz = /bits/ 64 <93 114 opp-hz = /bits/ 64 <936000000>;
116 opp-microvolt = <72500 115 opp-microvolt = <725000>;
117 opp-supported-hw = <0x 116 opp-supported-hw = <0xf>;
118 clock-latency-ns = <20 117 clock-latency-ns = <200000>;
119 }; 118 };
120 119
121 opp-1104000000 { 120 opp-1104000000 {
122 opp-hz = /bits/ 64 <11 121 opp-hz = /bits/ 64 <1104000000>;
123 opp-microvolt = <78750 122 opp-microvolt = <787500>;
124 opp-supported-hw = <0x 123 opp-supported-hw = <0xf>;
125 clock-latency-ns = <20 124 clock-latency-ns = <200000>;
126 }; 125 };
127 126
128 opp-1200000000 { 127 opp-1200000000 {
129 opp-hz = /bits/ 64 <12 128 opp-hz = /bits/ 64 <1200000000>;
130 opp-microvolt = <86250 129 opp-microvolt = <862500>;
131 opp-supported-hw = <0x 130 opp-supported-hw = <0xf>;
132 clock-latency-ns = <20 131 clock-latency-ns = <200000>;
133 }; 132 };
134 133
135 opp-1416000000 { 134 opp-1416000000 {
136 opp-hz = /bits/ 64 <14 135 opp-hz = /bits/ 64 <1416000000>;
137 opp-microvolt = <86250 136 opp-microvolt = <862500>;
138 opp-supported-hw = <0x 137 opp-supported-hw = <0x7>;
139 clock-latency-ns = <20 138 clock-latency-ns = <200000>;
140 }; 139 };
141 140
142 opp-1488000000 { 141 opp-1488000000 {
143 opp-hz = /bits/ 64 <14 142 opp-hz = /bits/ 64 <1488000000>;
144 opp-microvolt = <92500 143 opp-microvolt = <925000>;
145 opp-supported-hw = <0x 144 opp-supported-hw = <0x7>;
146 clock-latency-ns = <20 145 clock-latency-ns = <200000>;
147 }; 146 };
148 147
149 opp-1800000000 { 148 opp-1800000000 {
150 opp-hz = /bits/ 64 <18 149 opp-hz = /bits/ 64 <1800000000>;
151 opp-microvolt = <98750 150 opp-microvolt = <987500>;
152 opp-supported-hw = <0x 151 opp-supported-hw = <0x5>;
153 clock-latency-ns = <20 152 clock-latency-ns = <200000>;
154 }; 153 };
155 154
156 opp-2208000000 { 155 opp-2208000000 {
157 opp-hz = /bits/ 64 <22 156 opp-hz = /bits/ 64 <2208000000>;
158 opp-microvolt = <10625 157 opp-microvolt = <1062500>;
159 opp-supported-hw = <0x 158 opp-supported-hw = <0x1>;
160 clock-latency-ns = <20 159 clock-latency-ns = <200000>;
161 }; 160 };
162 }; 161 };
163 162
164 pmu { 163 pmu {
165 compatible = "arm,cortex-a73-p 164 compatible = "arm,cortex-a73-pmu";
166 interrupts = <GIC_PPI 7 (GIC_C 165 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
167 }; 166 };
168 167
169 psci { 168 psci {
170 compatible = "arm,psci-1.0"; 169 compatible = "arm,psci-1.0";
171 method = "smc"; 170 method = "smc";
172 }; 171 };
173 172
174 rpm: remoteproc { 173 rpm: remoteproc {
175 compatible = "qcom,ipq9574-rpm 174 compatible = "qcom,ipq9574-rpm-proc", "qcom,rpm-proc";
176 175
177 glink-edge { 176 glink-edge {
178 compatible = "qcom,gli 177 compatible = "qcom,glink-rpm";
179 interrupts = <GIC_SPI 178 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
180 qcom,rpm-msg-ram = <&r 179 qcom,rpm-msg-ram = <&rpm_msg_ram>;
181 mboxes = <&apcs_glb 0> 180 mboxes = <&apcs_glb 0>;
182 181
183 rpm_requests: rpm-requ 182 rpm_requests: rpm-requests {
184 compatible = " !! 183 compatible = "qcom,rpm-ipq9574";
185 qcom,glink-cha 184 qcom,glink-channels = "rpm_requests";
186 }; 185 };
187 }; 186 };
188 }; 187 };
189 188
190 reserved-memory { 189 reserved-memory {
191 #address-cells = <2>; 190 #address-cells = <2>;
192 #size-cells = <2>; 191 #size-cells = <2>;
193 ranges; 192 ranges;
194 193
195 bootloader@4a100000 { 194 bootloader@4a100000 {
196 reg = <0x0 0x4a100000 195 reg = <0x0 0x4a100000 0x0 0x400000>;
197 no-map; 196 no-map;
198 }; 197 };
199 198
200 sbl@4a500000 { 199 sbl@4a500000 {
201 reg = <0x0 0x4a500000 200 reg = <0x0 0x4a500000 0x0 0x100000>;
202 no-map; 201 no-map;
203 }; 202 };
204 203
205 tz_region: tz@4a600000 { 204 tz_region: tz@4a600000 {
206 reg = <0x0 0x4a600000 205 reg = <0x0 0x4a600000 0x0 0x400000>;
207 no-map; 206 no-map;
208 }; 207 };
209 208
210 smem@4aa00000 { 209 smem@4aa00000 {
211 compatible = "qcom,sme 210 compatible = "qcom,smem";
212 reg = <0x0 0x4aa00000 211 reg = <0x0 0x4aa00000 0x0 0x100000>;
213 hwlocks = <&tcsr_mutex 212 hwlocks = <&tcsr_mutex 3>;
214 no-map; 213 no-map;
215 }; 214 };
216 }; 215 };
217 216
218 soc: soc@0 { 217 soc: soc@0 {
219 compatible = "simple-bus"; 218 compatible = "simple-bus";
220 #address-cells = <1>; 219 #address-cells = <1>;
221 #size-cells = <1>; 220 #size-cells = <1>;
222 ranges = <0 0 0 0xffffffff>; 221 ranges = <0 0 0 0xffffffff>;
223 222
224 rpm_msg_ram: sram@60000 { 223 rpm_msg_ram: sram@60000 {
225 compatible = "qcom,rpm 224 compatible = "qcom,rpm-msg-ram";
226 reg = <0x00060000 0x60 225 reg = <0x00060000 0x6000>;
227 }; 226 };
228 227
229 rng: rng@e3000 { 228 rng: rng@e3000 {
230 compatible = "qcom,prn 229 compatible = "qcom,prng-ee";
231 reg = <0x000e3000 0x10 230 reg = <0x000e3000 0x1000>;
232 clocks = <&gcc GCC_PRN 231 clocks = <&gcc GCC_PRNG_AHB_CLK>;
233 clock-names = "core"; 232 clock-names = "core";
234 }; 233 };
235 234
236 mdio: mdio@90000 { <<
237 compatible = "qcom,ip <<
238 reg = <0x00090000 0x64 <<
239 #address-cells = <1>; <<
240 #size-cells = <0>; <<
241 clocks = <&gcc GCC_MDI <<
242 clock-names = "gcc_mdi <<
243 status = "disabled"; <<
244 }; <<
245 <<
246 qfprom: efuse@a4000 { 235 qfprom: efuse@a4000 {
247 compatible = "qcom,ipq 236 compatible = "qcom,ipq9574-qfprom", "qcom,qfprom";
248 reg = <0x000a4000 0x5a 237 reg = <0x000a4000 0x5a1>;
249 #address-cells = <1>; 238 #address-cells = <1>;
250 #size-cells = <1>; 239 #size-cells = <1>;
251 240
252 cpu_speed_bin: cpu-spe 241 cpu_speed_bin: cpu-speed-bin@15 {
253 reg = <0x15 0x 242 reg = <0x15 0x2>;
254 bits = <7 2>; 243 bits = <7 2>;
255 }; 244 };
256 }; 245 };
257 246
258 cryptobam: dma-controller@7040 247 cryptobam: dma-controller@704000 {
259 compatible = "qcom,bam 248 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
260 reg = <0x00704000 0x20 249 reg = <0x00704000 0x20000>;
261 interrupts = <GIC_SPI 250 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
262 #dma-cells = <1>; 251 #dma-cells = <1>;
263 qcom,ee = <1>; 252 qcom,ee = <1>;
264 qcom,controlled-remote 253 qcom,controlled-remotely;
265 }; 254 };
266 255
267 crypto: crypto@73a000 { 256 crypto: crypto@73a000 {
268 compatible = "qcom,ipq 257 compatible = "qcom,ipq9574-qce", "qcom,ipq4019-qce", "qcom,qce";
269 reg = <0x0073a000 0x60 258 reg = <0x0073a000 0x6000>;
270 clocks = <&gcc GCC_CRY 259 clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
271 <&gcc GCC_CRY 260 <&gcc GCC_CRYPTO_AXI_CLK>,
272 <&gcc GCC_CRY 261 <&gcc GCC_CRYPTO_CLK>;
273 clock-names = "iface", 262 clock-names = "iface", "bus", "core";
274 dmas = <&cryptobam 2>, 263 dmas = <&cryptobam 2>, <&cryptobam 3>;
275 dma-names = "rx", "tx" 264 dma-names = "rx", "tx";
276 }; 265 };
277 266
278 tsens: thermal-sensor@4a9000 { 267 tsens: thermal-sensor@4a9000 {
279 compatible = "qcom,ipq 268 compatible = "qcom,ipq9574-tsens", "qcom,ipq8074-tsens";
280 reg = <0x004a9000 0x10 269 reg = <0x004a9000 0x1000>,
281 <0x004a8000 0x10 270 <0x004a8000 0x1000>;
282 interrupts = <GIC_SPI 271 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
283 interrupt-names = "com 272 interrupt-names = "combined";
284 #qcom,sensors = <16>; 273 #qcom,sensors = <16>;
285 #thermal-sensor-cells 274 #thermal-sensor-cells = <1>;
286 }; 275 };
287 276
288 tlmm: pinctrl@1000000 { 277 tlmm: pinctrl@1000000 {
289 compatible = "qcom,ipq 278 compatible = "qcom,ipq9574-tlmm";
290 reg = <0x01000000 0x30 279 reg = <0x01000000 0x300000>;
291 interrupts = <GIC_SPI 280 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
292 gpio-controller; 281 gpio-controller;
293 #gpio-cells = <2>; 282 #gpio-cells = <2>;
294 gpio-ranges = <&tlmm 0 283 gpio-ranges = <&tlmm 0 0 65>;
295 interrupt-controller; 284 interrupt-controller;
296 #interrupt-cells = <2> 285 #interrupt-cells = <2>;
297 286
298 uart2_pins: uart2-stat 287 uart2_pins: uart2-state {
299 pins = "gpio34 288 pins = "gpio34", "gpio35";
300 function = "bl 289 function = "blsp2_uart";
301 drive-strength 290 drive-strength = <8>;
302 bias-disable; 291 bias-disable;
303 }; 292 };
304 }; 293 };
305 294
306 gcc: clock-controller@1800000 295 gcc: clock-controller@1800000 {
307 compatible = "qcom,ipq 296 compatible = "qcom,ipq9574-gcc";
308 reg = <0x01800000 0x80 297 reg = <0x01800000 0x80000>;
309 clocks = <&xo_board_cl 298 clocks = <&xo_board_clk>,
310 <&sleep_clk>, 299 <&sleep_clk>,
311 <0>, 300 <0>,
312 <0>, 301 <0>,
313 <0>, 302 <0>,
314 <0>, 303 <0>,
315 <0>, 304 <0>,
316 <0>; 305 <0>;
317 #clock-cells = <1>; 306 #clock-cells = <1>;
318 #reset-cells = <1>; 307 #reset-cells = <1>;
319 #interconnect-cells = !! 308 #power-domain-cells = <1>;
320 }; 309 };
321 310
322 tcsr_mutex: hwlock@1905000 { 311 tcsr_mutex: hwlock@1905000 {
323 compatible = "qcom,tcs 312 compatible = "qcom,tcsr-mutex";
324 reg = <0x01905000 0x20 313 reg = <0x01905000 0x20000>;
325 #hwlock-cells = <1>; 314 #hwlock-cells = <1>;
326 }; 315 };
327 316
328 tcsr: syscon@1937000 { 317 tcsr: syscon@1937000 {
329 compatible = "qcom,tcs 318 compatible = "qcom,tcsr-ipq9574", "syscon";
330 reg = <0x01937000 0x21 319 reg = <0x01937000 0x21000>;
331 }; 320 };
332 321
333 sdhc_1: mmc@7804000 { 322 sdhc_1: mmc@7804000 {
334 compatible = "qcom,ipq 323 compatible = "qcom,ipq9574-sdhci", "qcom,sdhci-msm-v5";
335 reg = <0x07804000 0x10 324 reg = <0x07804000 0x1000>,
336 <0x07805000 0x10 325 <0x07805000 0x1000>,
337 <0x07808000 0x20 326 <0x07808000 0x2000>;
338 reg-names = "hc", "cqh 327 reg-names = "hc", "cqhci", "ice";
339 328
340 interrupts = <GIC_SPI 329 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
341 <GIC_SPI 330 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
342 interrupt-names = "hc_ 331 interrupt-names = "hc_irq", "pwr_irq";
343 332
344 clocks = <&gcc GCC_SDC 333 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
345 <&gcc GCC_SDC 334 <&gcc GCC_SDCC1_APPS_CLK>,
346 <&xo_board_cl 335 <&xo_board_clk>,
347 <&gcc GCC_SDC 336 <&gcc GCC_SDCC1_ICE_CORE_CLK>;
348 clock-names = "iface", 337 clock-names = "iface", "core", "xo", "ice";
349 non-removable; 338 non-removable;
350 supports-cqe; 339 supports-cqe;
351 status = "disabled"; 340 status = "disabled";
352 }; 341 };
353 342
354 blsp_dma: dma-controller@78840 343 blsp_dma: dma-controller@7884000 {
355 compatible = "qcom,bam 344 compatible = "qcom,bam-v1.7.0";
356 reg = <0x07884000 0x2b 345 reg = <0x07884000 0x2b000>;
357 interrupts = <GIC_SPI 346 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
358 clocks = <&gcc GCC_BLS 347 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
359 clock-names = "bam_clk 348 clock-names = "bam_clk";
360 #dma-cells = <1>; 349 #dma-cells = <1>;
361 qcom,ee = <0>; 350 qcom,ee = <0>;
362 }; 351 };
363 352
364 blsp1_uart0: serial@78af000 { 353 blsp1_uart0: serial@78af000 {
365 compatible = "qcom,msm 354 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
366 reg = <0x078af000 0x20 355 reg = <0x078af000 0x200>;
367 interrupts = <GIC_SPI 356 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
368 clocks = <&gcc GCC_BLS 357 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
369 <&gcc GCC_BLS 358 <&gcc GCC_BLSP1_AHB_CLK>;
370 clock-names = "core", 359 clock-names = "core", "iface";
371 status = "disabled"; 360 status = "disabled";
372 }; 361 };
373 362
374 blsp1_uart1: serial@78b0000 { 363 blsp1_uart1: serial@78b0000 {
375 compatible = "qcom,msm 364 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
376 reg = <0x078b0000 0x20 365 reg = <0x078b0000 0x200>;
377 interrupts = <GIC_SPI 366 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
378 clocks = <&gcc GCC_BLS 367 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
379 <&gcc GCC_BLS 368 <&gcc GCC_BLSP1_AHB_CLK>;
380 clock-names = "core", 369 clock-names = "core", "iface";
381 status = "disabled"; 370 status = "disabled";
382 }; 371 };
383 372
384 blsp1_uart2: serial@78b1000 { 373 blsp1_uart2: serial@78b1000 {
385 compatible = "qcom,msm 374 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
386 reg = <0x078b1000 0x20 375 reg = <0x078b1000 0x200>;
387 interrupts = <GIC_SPI 376 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
388 clocks = <&gcc GCC_BLS 377 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
389 <&gcc GCC_BLS 378 <&gcc GCC_BLSP1_AHB_CLK>;
390 clock-names = "core", 379 clock-names = "core", "iface";
391 status = "disabled"; 380 status = "disabled";
392 }; 381 };
393 382
394 blsp1_uart3: serial@78b2000 { 383 blsp1_uart3: serial@78b2000 {
395 compatible = "qcom,msm 384 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
396 reg = <0x078b2000 0x20 385 reg = <0x078b2000 0x200>;
397 interrupts = <GIC_SPI 386 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
398 clocks = <&gcc GCC_BLS 387 clocks = <&gcc GCC_BLSP1_UART4_APPS_CLK>,
399 <&gcc GCC_BLS 388 <&gcc GCC_BLSP1_AHB_CLK>;
400 clock-names = "core", 389 clock-names = "core", "iface";
401 status = "disabled"; 390 status = "disabled";
402 }; 391 };
403 392
404 blsp1_uart4: serial@78b3000 { 393 blsp1_uart4: serial@78b3000 {
405 compatible = "qcom,msm 394 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
406 reg = <0x078b3000 0x20 395 reg = <0x078b3000 0x200>;
407 interrupts = <GIC_SPI 396 interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
408 clocks = <&gcc GCC_BLS 397 clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>,
409 <&gcc GCC_BLS 398 <&gcc GCC_BLSP1_AHB_CLK>;
410 clock-names = "core", 399 clock-names = "core", "iface";
411 status = "disabled"; 400 status = "disabled";
412 }; 401 };
413 402
414 blsp1_uart5: serial@78b4000 { 403 blsp1_uart5: serial@78b4000 {
415 compatible = "qcom,msm 404 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
416 reg = <0x078b4000 0x20 405 reg = <0x078b4000 0x200>;
417 interrupts = <GIC_SPI 406 interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>;
418 clocks = <&gcc GCC_BLS 407 clocks = <&gcc GCC_BLSP1_UART6_APPS_CLK>,
419 <&gcc GCC_BLS 408 <&gcc GCC_BLSP1_AHB_CLK>;
420 clock-names = "core", 409 clock-names = "core", "iface";
421 status = "disabled"; 410 status = "disabled";
422 }; 411 };
423 412
424 blsp1_spi0: spi@78b5000 { 413 blsp1_spi0: spi@78b5000 {
425 compatible = "qcom,spi 414 compatible = "qcom,spi-qup-v2.2.1";
426 reg = <0x078b5000 0x60 415 reg = <0x078b5000 0x600>;
427 #address-cells = <1>; 416 #address-cells = <1>;
428 #size-cells = <0>; 417 #size-cells = <0>;
429 interrupts = <GIC_SPI 418 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
430 clocks = <&gcc GCC_BLS 419 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
431 <&gcc GCC_BLS 420 <&gcc GCC_BLSP1_AHB_CLK>;
432 clock-names = "core", 421 clock-names = "core", "iface";
433 dmas = <&blsp_dma 12>, 422 dmas = <&blsp_dma 12>, <&blsp_dma 13>;
434 dma-names = "tx", "rx" 423 dma-names = "tx", "rx";
435 status = "disabled"; 424 status = "disabled";
436 }; 425 };
437 426
438 blsp1_i2c1: i2c@78b6000 { 427 blsp1_i2c1: i2c@78b6000 {
439 compatible = "qcom,i2c 428 compatible = "qcom,i2c-qup-v2.2.1";
440 reg = <0x078b6000 0x60 429 reg = <0x078b6000 0x600>;
441 #address-cells = <1>; 430 #address-cells = <1>;
442 #size-cells = <0>; 431 #size-cells = <0>;
443 interrupts = <GIC_SPI 432 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
444 clocks = <&gcc GCC_BLS 433 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
445 <&gcc GCC_BLS 434 <&gcc GCC_BLSP1_AHB_CLK>;
446 clock-names = "core", 435 clock-names = "core", "iface";
447 assigned-clocks = <&gc 436 assigned-clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
448 assigned-clock-rates = 437 assigned-clock-rates = <50000000>;
449 dmas = <&blsp_dma 14>, 438 dmas = <&blsp_dma 14>, <&blsp_dma 15>;
450 dma-names = "tx", "rx" 439 dma-names = "tx", "rx";
451 status = "disabled"; 440 status = "disabled";
452 }; 441 };
453 442
454 blsp1_spi1: spi@78b6000 { 443 blsp1_spi1: spi@78b6000 {
455 compatible = "qcom,spi 444 compatible = "qcom,spi-qup-v2.2.1";
456 reg = <0x078b6000 0x60 445 reg = <0x078b6000 0x600>;
457 #address-cells = <1>; 446 #address-cells = <1>;
458 #size-cells = <0>; 447 #size-cells = <0>;
459 interrupts = <GIC_SPI 448 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
460 clocks = <&gcc GCC_BLS 449 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
461 <&gcc GCC_BLS 450 <&gcc GCC_BLSP1_AHB_CLK>;
462 clock-names = "core", 451 clock-names = "core", "iface";
463 dmas = <&blsp_dma 14>, 452 dmas = <&blsp_dma 14>, <&blsp_dma 15>;
464 dma-names = "tx", "rx" 453 dma-names = "tx", "rx";
465 status = "disabled"; 454 status = "disabled";
466 }; 455 };
467 456
468 blsp1_i2c2: i2c@78b7000 { 457 blsp1_i2c2: i2c@78b7000 {
469 compatible = "qcom,i2c 458 compatible = "qcom,i2c-qup-v2.2.1";
470 reg = <0x078b7000 0x60 459 reg = <0x078b7000 0x600>;
471 #address-cells = <1>; 460 #address-cells = <1>;
472 #size-cells = <0>; 461 #size-cells = <0>;
473 interrupts = <GIC_SPI 462 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
474 clocks = <&gcc GCC_BLS 463 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
475 <&gcc GCC_BLS 464 <&gcc GCC_BLSP1_AHB_CLK>;
476 clock-names = "core", 465 clock-names = "core", "iface";
477 assigned-clocks = <&gc 466 assigned-clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
478 assigned-clock-rates = 467 assigned-clock-rates = <50000000>;
479 dmas = <&blsp_dma 16>, 468 dmas = <&blsp_dma 16>, <&blsp_dma 17>;
480 dma-names = "tx", "rx" 469 dma-names = "tx", "rx";
481 status = "disabled"; 470 status = "disabled";
482 }; 471 };
483 472
484 blsp1_spi2: spi@78b7000 { 473 blsp1_spi2: spi@78b7000 {
485 compatible = "qcom,spi 474 compatible = "qcom,spi-qup-v2.2.1";
486 reg = <0x078b7000 0x60 475 reg = <0x078b7000 0x600>;
487 #address-cells = <1>; 476 #address-cells = <1>;
488 #size-cells = <0>; 477 #size-cells = <0>;
489 interrupts = <GIC_SPI 478 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
490 clocks = <&gcc GCC_BLS 479 clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
491 <&gcc GCC_BLS 480 <&gcc GCC_BLSP1_AHB_CLK>;
492 clock-names = "core", 481 clock-names = "core", "iface";
493 dmas = <&blsp_dma 16>, 482 dmas = <&blsp_dma 16>, <&blsp_dma 17>;
494 dma-names = "tx", "rx" 483 dma-names = "tx", "rx";
495 status = "disabled"; 484 status = "disabled";
496 }; 485 };
497 486
498 blsp1_i2c3: i2c@78b8000 { 487 blsp1_i2c3: i2c@78b8000 {
499 compatible = "qcom,i2c 488 compatible = "qcom,i2c-qup-v2.2.1";
500 reg = <0x078b8000 0x60 489 reg = <0x078b8000 0x600>;
501 #address-cells = <1>; 490 #address-cells = <1>;
502 #size-cells = <0>; 491 #size-cells = <0>;
503 interrupts = <GIC_SPI 492 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
504 clocks = <&gcc GCC_BLS 493 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
505 <&gcc GCC_BLS 494 <&gcc GCC_BLSP1_AHB_CLK>;
506 clock-names = "core", 495 clock-names = "core", "iface";
507 assigned-clocks = <&gc 496 assigned-clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
508 assigned-clock-rates = 497 assigned-clock-rates = <50000000>;
509 dmas = <&blsp_dma 18>, 498 dmas = <&blsp_dma 18>, <&blsp_dma 19>;
510 dma-names = "tx", "rx" 499 dma-names = "tx", "rx";
511 status = "disabled"; 500 status = "disabled";
512 }; 501 };
513 502
514 blsp1_spi3: spi@78b8000 { 503 blsp1_spi3: spi@78b8000 {
515 compatible = "qcom,spi 504 compatible = "qcom,spi-qup-v2.2.1";
516 reg = <0x078b8000 0x60 505 reg = <0x078b8000 0x600>;
517 #address-cells = <1>; 506 #address-cells = <1>;
518 #size-cells = <0>; 507 #size-cells = <0>;
519 interrupts = <GIC_SPI 508 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
520 spi-max-frequency = <5 509 spi-max-frequency = <50000000>;
521 clocks = <&gcc GCC_BLS 510 clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
522 <&gcc GCC_BLS 511 <&gcc GCC_BLSP1_AHB_CLK>;
523 clock-names = "core", 512 clock-names = "core", "iface";
524 dmas = <&blsp_dma 18>, 513 dmas = <&blsp_dma 18>, <&blsp_dma 19>;
525 dma-names = "tx", "rx" 514 dma-names = "tx", "rx";
526 status = "disabled"; 515 status = "disabled";
527 }; 516 };
528 517
529 blsp1_i2c4: i2c@78b9000 { 518 blsp1_i2c4: i2c@78b9000 {
530 compatible = "qcom,i2c 519 compatible = "qcom,i2c-qup-v2.2.1";
531 reg = <0x078b9000 0x60 520 reg = <0x078b9000 0x600>;
532 #address-cells = <1>; 521 #address-cells = <1>;
533 #size-cells = <0>; 522 #size-cells = <0>;
534 interrupts = <GIC_SPI 523 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
535 clocks = <&gcc GCC_BLS 524 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
536 <&gcc GCC_BLS 525 <&gcc GCC_BLSP1_AHB_CLK>;
537 clock-names = "core", 526 clock-names = "core", "iface";
538 assigned-clocks = <&gc 527 assigned-clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>;
539 assigned-clock-rates = 528 assigned-clock-rates = <50000000>;
540 dmas = <&blsp_dma 20>, 529 dmas = <&blsp_dma 20>, <&blsp_dma 21>;
541 dma-names = "tx", "rx" 530 dma-names = "tx", "rx";
542 status = "disabled"; 531 status = "disabled";
543 }; 532 };
544 533
545 blsp1_spi4: spi@78b9000 { 534 blsp1_spi4: spi@78b9000 {
546 compatible = "qcom,spi 535 compatible = "qcom,spi-qup-v2.2.1";
547 reg = <0x078b9000 0x60 536 reg = <0x078b9000 0x600>;
548 #address-cells = <1>; 537 #address-cells = <1>;
549 #size-cells = <0>; 538 #size-cells = <0>;
550 interrupts = <GIC_SPI 539 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
551 clocks = <&gcc GCC_BLS 540 clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
552 <&gcc GCC_BLS 541 <&gcc GCC_BLSP1_AHB_CLK>;
553 clock-names = "core", 542 clock-names = "core", "iface";
554 dmas = <&blsp_dma 20>, 543 dmas = <&blsp_dma 20>, <&blsp_dma 21>;
555 dma-names = "tx", "rx" 544 dma-names = "tx", "rx";
556 status = "disabled"; 545 status = "disabled";
557 }; 546 };
558 547
559 usb_0_qusbphy: phy@7b000 { 548 usb_0_qusbphy: phy@7b000 {
560 compatible = "qcom,ipq 549 compatible = "qcom,ipq9574-qusb2-phy";
561 reg = <0x0007b000 0x18 550 reg = <0x0007b000 0x180>;
562 #phy-cells = <0>; 551 #phy-cells = <0>;
563 552
564 clocks = <&gcc GCC_USB 553 clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
565 <&xo_board_cl 554 <&xo_board_clk>;
566 clock-names = "cfg_ahb 555 clock-names = "cfg_ahb",
567 "ref"; 556 "ref";
568 557
569 resets = <&gcc GCC_QUS 558 resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
570 status = "disabled"; 559 status = "disabled";
571 }; 560 };
572 561
573 usb_0_qmpphy: phy@7d000 { 562 usb_0_qmpphy: phy@7d000 {
574 compatible = "qcom,ipq 563 compatible = "qcom,ipq9574-qmp-usb3-phy";
575 reg = <0x0007d000 0xa0 564 reg = <0x0007d000 0xa00>;
576 #phy-cells = <0>; 565 #phy-cells = <0>;
577 566
578 clocks = <&gcc GCC_USB 567 clocks = <&gcc GCC_USB0_AUX_CLK>,
579 <&xo_board_cl 568 <&xo_board_clk>,
580 <&gcc GCC_USB 569 <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
581 <&gcc GCC_USB 570 <&gcc GCC_USB0_PIPE_CLK>;
582 clock-names = "aux", 571 clock-names = "aux",
583 "ref", 572 "ref",
584 "cfg_ahb 573 "cfg_ahb",
585 "pipe"; 574 "pipe";
586 575
587 resets = <&gcc GCC_USB 576 resets = <&gcc GCC_USB0_PHY_BCR>,
588 <&gcc GCC_USB 577 <&gcc GCC_USB3PHY_0_PHY_BCR>;
589 reset-names = "phy", 578 reset-names = "phy",
590 "phy_phy 579 "phy_phy";
591 580
592 #clock-cells = <0>; 581 #clock-cells = <0>;
593 clock-output-names = " 582 clock-output-names = "usb0_pipe_clk";
594 583
595 status = "disabled"; 584 status = "disabled";
596 }; 585 };
597 586
598 usb3: usb@8af8800 { 587 usb3: usb@8af8800 {
599 compatible = "qcom,ipq 588 compatible = "qcom,ipq9574-dwc3", "qcom,dwc3";
600 reg = <0x08af8800 0x40 589 reg = <0x08af8800 0x400>;
601 #address-cells = <1>; 590 #address-cells = <1>;
602 #size-cells = <1>; 591 #size-cells = <1>;
603 ranges; 592 ranges;
604 593
605 clocks = <&gcc GCC_SNO 594 clocks = <&gcc GCC_SNOC_USB_CLK>,
606 <&gcc GCC_USB 595 <&gcc GCC_USB0_MASTER_CLK>,
607 <&gcc GCC_ANO 596 <&gcc GCC_ANOC_USB_AXI_CLK>,
608 <&gcc GCC_USB 597 <&gcc GCC_USB0_SLEEP_CLK>,
609 <&gcc GCC_USB 598 <&gcc GCC_USB0_MOCK_UTMI_CLK>;
610 599
611 clock-names = "cfg_noc 600 clock-names = "cfg_noc",
612 "core", 601 "core",
613 "iface", 602 "iface",
614 "sleep", 603 "sleep",
615 "mock_ut 604 "mock_utmi";
616 605
617 assigned-clocks = <&gc 606 assigned-clocks = <&gcc GCC_USB0_MASTER_CLK>,
618 <&gc 607 <&gcc GCC_USB0_MOCK_UTMI_CLK>;
619 assigned-clock-rates = 608 assigned-clock-rates = <200000000>,
620 609 <24000000>;
621 610
622 interrupts-extended = 611 interrupts-extended = <&intc GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
623 interrupt-names = "pwr 612 interrupt-names = "pwr_event";
624 613
625 resets = <&gcc GCC_USB 614 resets = <&gcc GCC_USB_BCR>;
626 status = "disabled"; 615 status = "disabled";
627 616
628 usb_0_dwc3: usb@8a0000 617 usb_0_dwc3: usb@8a00000 {
629 compatible = " 618 compatible = "snps,dwc3";
630 reg = <0x8a000 619 reg = <0x8a00000 0xcd00>;
631 clocks = <&gcc 620 clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>;
632 clock-names = 621 clock-names = "ref";
633 interrupts = < 622 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
634 phys = <&usb_0 623 phys = <&usb_0_qusbphy>, <&usb_0_qmpphy>;
635 phy-names = "u 624 phy-names = "usb2-phy", "usb3-phy";
636 tx-fifo-resize 625 tx-fifo-resize;
637 snps,is-utmi-l 626 snps,is-utmi-l1-suspend;
638 snps,hird-thre 627 snps,hird-threshold = /bits/ 8 <0x0>;
639 snps,dis_u2_su 628 snps,dis_u2_susphy_quirk;
640 snps,dis_u3_su 629 snps,dis_u3_susphy_quirk;
641 }; 630 };
642 }; 631 };
643 632
644 intc: interrupt-controller@b00 633 intc: interrupt-controller@b000000 {
645 compatible = "qcom,msm 634 compatible = "qcom,msm-qgic2";
646 reg = <0x0b000000 0x10 635 reg = <0x0b000000 0x1000>, /* GICD */
647 <0x0b002000 0x20 636 <0x0b002000 0x2000>, /* GICC */
648 <0x0b001000 0x10 637 <0x0b001000 0x1000>, /* GICH */
649 <0x0b004000 0x20 638 <0x0b004000 0x2000>; /* GICV */
650 #address-cells = <1>; 639 #address-cells = <1>;
651 #size-cells = <1>; 640 #size-cells = <1>;
652 interrupt-controller; 641 interrupt-controller;
653 #interrupt-cells = <3> 642 #interrupt-cells = <3>;
654 interrupts = <GIC_PPI 643 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
655 ranges = <0 0x0b00c000 644 ranges = <0 0x0b00c000 0x3000>;
656 645
657 v2m0: v2m@0 { 646 v2m0: v2m@0 {
658 compatible = " 647 compatible = "arm,gic-v2m-frame";
659 reg = <0x00000 648 reg = <0x00000000 0xffd>;
660 msi-controller 649 msi-controller;
661 }; 650 };
662 651
663 v2m1: v2m@1000 { 652 v2m1: v2m@1000 {
664 compatible = " 653 compatible = "arm,gic-v2m-frame";
665 reg = <0x00001 654 reg = <0x00001000 0xffd>;
666 msi-controller 655 msi-controller;
667 }; 656 };
668 657
669 v2m2: v2m@2000 { 658 v2m2: v2m@2000 {
670 compatible = " 659 compatible = "arm,gic-v2m-frame";
671 reg = <0x00002 660 reg = <0x00002000 0xffd>;
672 msi-controller 661 msi-controller;
673 }; 662 };
674 }; 663 };
675 664
676 watchdog: watchdog@b017000 { 665 watchdog: watchdog@b017000 {
677 compatible = "qcom,aps 666 compatible = "qcom,apss-wdt-ipq9574", "qcom,kpss-wdt";
678 reg = <0x0b017000 0x10 667 reg = <0x0b017000 0x1000>;
679 interrupts = <GIC_SPI 668 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
680 clocks = <&sleep_clk>; 669 clocks = <&sleep_clk>;
681 timeout-sec = <30>; 670 timeout-sec = <30>;
682 }; 671 };
683 672
684 apcs_glb: mailbox@b111000 { 673 apcs_glb: mailbox@b111000 {
685 compatible = "qcom,ipq 674 compatible = "qcom,ipq9574-apcs-apps-global",
686 "qcom,ipq 675 "qcom,ipq6018-apcs-apps-global";
687 reg = <0x0b111000 0x10 676 reg = <0x0b111000 0x1000>;
688 #clock-cells = <1>; 677 #clock-cells = <1>;
689 clocks = <&a73pll>, <& 678 clocks = <&a73pll>, <&xo_board_clk>, <&gcc GPLL0>;
690 clock-names = "pll", " 679 clock-names = "pll", "xo", "gpll0";
691 #mbox-cells = <1>; 680 #mbox-cells = <1>;
692 }; 681 };
693 682
694 a73pll: clock@b116000 { 683 a73pll: clock@b116000 {
695 compatible = "qcom,ipq 684 compatible = "qcom,ipq9574-a73pll";
696 reg = <0x0b116000 0x40 685 reg = <0x0b116000 0x40>;
697 #clock-cells = <0>; 686 #clock-cells = <0>;
698 clocks = <&xo_board_cl 687 clocks = <&xo_board_clk>;
699 clock-names = "xo"; 688 clock-names = "xo";
700 }; 689 };
701 690
702 timer@b120000 { 691 timer@b120000 {
703 compatible = "arm,armv 692 compatible = "arm,armv7-timer-mem";
704 reg = <0x0b120000 0x10 693 reg = <0x0b120000 0x1000>;
705 #address-cells = <1>; 694 #address-cells = <1>;
706 #size-cells = <1>; 695 #size-cells = <1>;
707 ranges; 696 ranges;
708 697
709 frame@b120000 { 698 frame@b120000 {
710 reg = <0x0b121 699 reg = <0x0b121000 0x1000>,
711 <0x0b122 700 <0x0b122000 0x1000>;
712 frame-number = 701 frame-number = <0>;
713 interrupts = < 702 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
714 < 703 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
715 }; 704 };
716 705
717 frame@b123000 { 706 frame@b123000 {
718 reg = <0x0b123 707 reg = <0x0b123000 0x1000>;
719 frame-number = 708 frame-number = <1>;
720 interrupts = < 709 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
721 status = "disa 710 status = "disabled";
722 }; 711 };
723 712
724 frame@b124000 { 713 frame@b124000 {
725 reg = <0x0b124 714 reg = <0x0b124000 0x1000>;
726 frame-number = 715 frame-number = <2>;
727 interrupts = < 716 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
728 status = "disa 717 status = "disabled";
729 }; 718 };
730 719
731 frame@b125000 { 720 frame@b125000 {
732 reg = <0x0b125 721 reg = <0x0b125000 0x1000>;
733 frame-number = 722 frame-number = <3>;
734 interrupts = < 723 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
735 status = "disa 724 status = "disabled";
736 }; 725 };
737 726
738 frame@b126000 { 727 frame@b126000 {
739 reg = <0x0b126 728 reg = <0x0b126000 0x1000>;
740 frame-number = 729 frame-number = <4>;
741 interrupts = < 730 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
742 status = "disa 731 status = "disabled";
743 }; 732 };
744 733
745 frame@b127000 { 734 frame@b127000 {
746 reg = <0x0b127 735 reg = <0x0b127000 0x1000>;
747 frame-number = 736 frame-number = <5>;
748 interrupts = < 737 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
749 status = "disa 738 status = "disabled";
750 }; 739 };
751 740
752 frame@b128000 { 741 frame@b128000 {
753 reg = <0x0b128 742 reg = <0x0b128000 0x1000>;
754 frame-number = 743 frame-number = <6>;
755 interrupts = < 744 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
756 status = "disa 745 status = "disabled";
757 }; 746 };
758 }; 747 };
759 }; 748 };
760 749
761 thermal-zones { 750 thermal-zones {
762 nss-top-thermal { 751 nss-top-thermal {
>> 752 polling-delay-passive = <0>;
>> 753 polling-delay = <0>;
763 thermal-sensors = <&ts 754 thermal-sensors = <&tsens 3>;
764 755
765 trips { 756 trips {
766 nss-top-critic 757 nss-top-critical {
767 temper 758 temperature = <125000>;
768 hyster 759 hysteresis = <1000>;
769 type = 760 type = "critical";
770 }; 761 };
771 }; 762 };
772 }; 763 };
773 764
774 ubi-0-thermal { 765 ubi-0-thermal {
>> 766 polling-delay-passive = <0>;
>> 767 polling-delay = <0>;
775 thermal-sensors = <&ts 768 thermal-sensors = <&tsens 4>;
776 769
777 trips { 770 trips {
778 ubi_0-critical 771 ubi_0-critical {
779 temper 772 temperature = <125000>;
780 hyster 773 hysteresis = <1000>;
781 type = 774 type = "critical";
782 }; 775 };
783 }; 776 };
784 }; 777 };
785 778
786 ubi-1-thermal { 779 ubi-1-thermal {
>> 780 polling-delay-passive = <0>;
>> 781 polling-delay = <0>;
787 thermal-sensors = <&ts 782 thermal-sensors = <&tsens 5>;
788 783
789 trips { 784 trips {
790 ubi_1-critical 785 ubi_1-critical {
791 temper 786 temperature = <125000>;
792 hyster 787 hysteresis = <1000>;
793 type = 788 type = "critical";
794 }; 789 };
795 }; 790 };
796 }; 791 };
797 792
798 ubi-2-thermal { 793 ubi-2-thermal {
>> 794 polling-delay-passive = <0>;
>> 795 polling-delay = <0>;
799 thermal-sensors = <&ts 796 thermal-sensors = <&tsens 6>;
800 797
801 trips { 798 trips {
802 ubi_2-critical 799 ubi_2-critical {
803 temper 800 temperature = <125000>;
804 hyster 801 hysteresis = <1000>;
805 type = 802 type = "critical";
806 }; 803 };
807 }; 804 };
808 }; 805 };
809 806
810 ubi-3-thermal { 807 ubi-3-thermal {
>> 808 polling-delay-passive = <0>;
>> 809 polling-delay = <0>;
811 thermal-sensors = <&ts 810 thermal-sensors = <&tsens 7>;
812 811
813 trips { 812 trips {
814 ubi_3-critical 813 ubi_3-critical {
815 temper 814 temperature = <125000>;
816 hyster 815 hysteresis = <1000>;
817 type = 816 type = "critical";
818 }; 817 };
819 }; 818 };
820 }; 819 };
821 820
822 cpuss0-thermal { 821 cpuss0-thermal {
>> 822 polling-delay-passive = <0>;
>> 823 polling-delay = <0>;
823 thermal-sensors = <&ts 824 thermal-sensors = <&tsens 8>;
824 825
825 trips { 826 trips {
826 cpu-critical { 827 cpu-critical {
827 temper 828 temperature = <125000>;
828 hyster 829 hysteresis = <1000>;
829 type = 830 type = "critical";
830 }; 831 };
831 }; 832 };
832 }; 833 };
833 834
834 cpuss1-thermal { 835 cpuss1-thermal {
>> 836 polling-delay-passive = <0>;
>> 837 polling-delay = <0>;
835 thermal-sensors = <&ts 838 thermal-sensors = <&tsens 9>;
836 839
837 trips { 840 trips {
838 cpu-critical { 841 cpu-critical {
839 temper 842 temperature = <125000>;
840 hyster 843 hysteresis = <1000>;
841 type = 844 type = "critical";
842 }; 845 };
843 }; 846 };
844 }; 847 };
845 848
846 cpu0-thermal { 849 cpu0-thermal {
>> 850 polling-delay-passive = <0>;
>> 851 polling-delay = <0>;
847 thermal-sensors = <&ts 852 thermal-sensors = <&tsens 10>;
848 853
849 trips { 854 trips {
850 cpu0_crit: cpu 855 cpu0_crit: cpu-critical {
851 temper 856 temperature = <120000>;
852 hyster 857 hysteresis = <10000>;
853 type = 858 type = "critical";
854 }; 859 };
855 860
856 cpu0_alert: cp 861 cpu0_alert: cpu-passive {
857 temper 862 temperature = <110000>;
858 hyster 863 hysteresis = <1000>;
859 type = 864 type = "passive";
860 }; 865 };
861 }; 866 };
862 867
863 cooling-maps { 868 cooling-maps {
864 map0 { 869 map0 {
865 trip = 870 trip = <&cpu0_alert>;
866 coolin 871 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
867 872 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
868 873 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
869 874 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
870 }; 875 };
871 }; 876 };
872 }; 877 };
873 878
874 cpu1-thermal { 879 cpu1-thermal {
>> 880 polling-delay-passive = <0>;
>> 881 polling-delay = <0>;
875 thermal-sensors = <&ts 882 thermal-sensors = <&tsens 11>;
876 883
877 trips { 884 trips {
878 cpu1_crit: cpu 885 cpu1_crit: cpu-critical {
879 temper 886 temperature = <120000>;
880 hyster 887 hysteresis = <10000>;
881 type = 888 type = "critical";
882 }; 889 };
883 890
884 cpu1_alert: cp 891 cpu1_alert: cpu-passive {
885 temper 892 temperature = <110000>;
886 hyster 893 hysteresis = <1000>;
887 type = 894 type = "passive";
888 }; 895 };
889 }; 896 };
890 897
891 cooling-maps { 898 cooling-maps {
892 map0 { 899 map0 {
893 trip = 900 trip = <&cpu1_alert>;
894 coolin 901 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
895 902 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
896 903 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
897 904 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
898 }; 905 };
899 }; 906 };
900 }; 907 };
901 908
902 cpu2-thermal { 909 cpu2-thermal {
>> 910 polling-delay-passive = <0>;
>> 911 polling-delay = <0>;
903 thermal-sensors = <&ts 912 thermal-sensors = <&tsens 12>;
904 913
905 trips { 914 trips {
906 cpu2_crit: cpu 915 cpu2_crit: cpu-critical {
907 temper 916 temperature = <120000>;
908 hyster 917 hysteresis = <10000>;
909 type = 918 type = "critical";
910 }; 919 };
911 920
912 cpu2_alert: cp 921 cpu2_alert: cpu-passive {
913 temper 922 temperature = <110000>;
914 hyster 923 hysteresis = <1000>;
915 type = 924 type = "passive";
916 }; 925 };
917 }; 926 };
918 927
919 cooling-maps { 928 cooling-maps {
920 map0 { 929 map0 {
921 trip = 930 trip = <&cpu2_alert>;
922 coolin 931 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
923 932 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
924 933 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
925 934 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
926 }; 935 };
927 }; 936 };
928 }; 937 };
929 938
930 cpu3-thermal { 939 cpu3-thermal {
>> 940 polling-delay-passive = <0>;
>> 941 polling-delay = <0>;
931 thermal-sensors = <&ts 942 thermal-sensors = <&tsens 13>;
932 943
933 trips { 944 trips {
934 cpu3_crit: cpu 945 cpu3_crit: cpu-critical {
935 temper 946 temperature = <120000>;
936 hyster 947 hysteresis = <10000>;
937 type = 948 type = "critical";
938 }; 949 };
939 950
940 cpu3_alert: cp 951 cpu3_alert: cpu-passive {
941 temper 952 temperature = <110000>;
942 hyster 953 hysteresis = <1000>;
943 type = 954 type = "passive";
944 }; 955 };
945 }; 956 };
946 957
947 cooling-maps { 958 cooling-maps {
948 map0 { 959 map0 {
949 trip = 960 trip = <&cpu3_alert>;
950 coolin 961 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
951 962 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
952 963 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
953 964 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
954 }; 965 };
955 }; 966 };
956 }; 967 };
957 968
958 wcss-phyb-thermal { 969 wcss-phyb-thermal {
>> 970 polling-delay-passive = <0>;
>> 971 polling-delay = <0>;
959 thermal-sensors = <&ts 972 thermal-sensors = <&tsens 14>;
960 973
961 trips { 974 trips {
962 wcss_phyb-crit 975 wcss_phyb-critical {
963 temper 976 temperature = <125000>;
964 hyster 977 hysteresis = <1000>;
965 type = 978 type = "critical";
966 }; 979 };
967 }; 980 };
968 }; 981 };
969 982
970 top-glue-thermal { 983 top-glue-thermal {
>> 984 polling-delay-passive = <0>;
>> 985 polling-delay = <0>;
971 thermal-sensors = <&ts 986 thermal-sensors = <&tsens 15>;
972 987
973 trips { 988 trips {
974 top_glue-criti 989 top_glue-critical {
975 temper 990 temperature = <125000>;
976 hyster 991 hysteresis = <1000>;
977 type = 992 type = "critical";
978 }; 993 };
979 }; 994 };
980 }; 995 };
981 }; 996 };
982 997
983 timer { 998 timer {
984 compatible = "arm,armv8-timer" 999 compatible = "arm,armv8-timer";
985 interrupts = <GIC_PPI 2 (GIC_C 1000 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
986 <GIC_PPI 3 (GIC_C 1001 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
987 <GIC_PPI 4 (GIC_C 1002 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
988 <GIC_PPI 1 (GIC_C 1003 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
989 }; 1004 };
990 }; 1005 };
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