1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3 1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2 /* 2 /*
3 * IPQ9574 SoC device tree source 3 * IPQ9574 SoC device tree source
4 * 4 *
5 * Copyright (c) 2020-2021 The Linux Foundatio 5 * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
6 * Copyright (c) 2023, Qualcomm Innovation Cen 6 * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
7 */ 7 */
8 8
9 #include <dt-bindings/clock/qcom,apss-ipq.h> 9 #include <dt-bindings/clock/qcom,apss-ipq.h>
10 #include <dt-bindings/clock/qcom,ipq9574-gcc.h 10 #include <dt-bindings/clock/qcom,ipq9574-gcc.h>
11 #include <dt-bindings/interconnect/qcom,ipq957 11 #include <dt-bindings/interconnect/qcom,ipq9574.h>
12 #include <dt-bindings/interrupt-controller/arm 12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/reset/qcom,ipq9574-gcc.h 13 #include <dt-bindings/reset/qcom,ipq9574-gcc.h>
14 #include <dt-bindings/thermal/thermal.h> 14 #include <dt-bindings/thermal/thermal.h>
15 15
16 / { 16 / {
17 interrupt-parent = <&intc>; 17 interrupt-parent = <&intc>;
18 #address-cells = <2>; 18 #address-cells = <2>;
19 #size-cells = <2>; 19 #size-cells = <2>;
20 20
21 clocks { 21 clocks {
22 sleep_clk: sleep-clk { 22 sleep_clk: sleep-clk {
23 compatible = "fixed-cl 23 compatible = "fixed-clock";
24 #clock-cells = <0>; 24 #clock-cells = <0>;
25 }; 25 };
26 26
27 xo_board_clk: xo-board-clk { 27 xo_board_clk: xo-board-clk {
28 compatible = "fixed-cl 28 compatible = "fixed-clock";
29 #clock-cells = <0>; 29 #clock-cells = <0>;
30 }; 30 };
31 }; 31 };
32 32
33 cpus { 33 cpus {
34 #address-cells = <1>; 34 #address-cells = <1>;
35 #size-cells = <0>; 35 #size-cells = <0>;
36 36
37 CPU0: cpu@0 { 37 CPU0: cpu@0 {
38 device_type = "cpu"; 38 device_type = "cpu";
39 compatible = "arm,cort 39 compatible = "arm,cortex-a73";
40 reg = <0x0>; 40 reg = <0x0>;
41 enable-method = "psci" 41 enable-method = "psci";
42 next-level-cache = <&L 42 next-level-cache = <&L2_0>;
43 clocks = <&apcs_glb AP 43 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
44 clock-names = "cpu"; 44 clock-names = "cpu";
45 operating-points-v2 = 45 operating-points-v2 = <&cpu_opp_table>;
46 cpu-supply = <&ipq9574 46 cpu-supply = <&ipq9574_s1>;
47 #cooling-cells = <2>; 47 #cooling-cells = <2>;
48 }; 48 };
49 49
50 CPU1: cpu@1 { 50 CPU1: cpu@1 {
51 device_type = "cpu"; 51 device_type = "cpu";
52 compatible = "arm,cort 52 compatible = "arm,cortex-a73";
53 reg = <0x1>; 53 reg = <0x1>;
54 enable-method = "psci" 54 enable-method = "psci";
55 next-level-cache = <&L 55 next-level-cache = <&L2_0>;
56 clocks = <&apcs_glb AP 56 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
57 clock-names = "cpu"; 57 clock-names = "cpu";
58 operating-points-v2 = 58 operating-points-v2 = <&cpu_opp_table>;
59 cpu-supply = <&ipq9574 59 cpu-supply = <&ipq9574_s1>;
60 #cooling-cells = <2>; 60 #cooling-cells = <2>;
61 }; 61 };
62 62
63 CPU2: cpu@2 { 63 CPU2: cpu@2 {
64 device_type = "cpu"; 64 device_type = "cpu";
65 compatible = "arm,cort 65 compatible = "arm,cortex-a73";
66 reg = <0x2>; 66 reg = <0x2>;
67 enable-method = "psci" 67 enable-method = "psci";
68 next-level-cache = <&L 68 next-level-cache = <&L2_0>;
69 clocks = <&apcs_glb AP 69 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
70 clock-names = "cpu"; 70 clock-names = "cpu";
71 operating-points-v2 = 71 operating-points-v2 = <&cpu_opp_table>;
72 cpu-supply = <&ipq9574 72 cpu-supply = <&ipq9574_s1>;
73 #cooling-cells = <2>; 73 #cooling-cells = <2>;
74 }; 74 };
75 75
76 CPU3: cpu@3 { 76 CPU3: cpu@3 {
77 device_type = "cpu"; 77 device_type = "cpu";
78 compatible = "arm,cort 78 compatible = "arm,cortex-a73";
79 reg = <0x3>; 79 reg = <0x3>;
80 enable-method = "psci" 80 enable-method = "psci";
81 next-level-cache = <&L 81 next-level-cache = <&L2_0>;
82 clocks = <&apcs_glb AP 82 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
83 clock-names = "cpu"; 83 clock-names = "cpu";
84 operating-points-v2 = 84 operating-points-v2 = <&cpu_opp_table>;
85 cpu-supply = <&ipq9574 85 cpu-supply = <&ipq9574_s1>;
86 #cooling-cells = <2>; 86 #cooling-cells = <2>;
87 }; 87 };
88 88
89 L2_0: l2-cache { 89 L2_0: l2-cache {
90 compatible = "cache"; 90 compatible = "cache";
91 cache-level = <2>; 91 cache-level = <2>;
92 cache-unified; 92 cache-unified;
93 }; 93 };
94 }; 94 };
95 95
96 firmware { 96 firmware {
97 scm { 97 scm {
98 compatible = "qcom,scm 98 compatible = "qcom,scm-ipq9574", "qcom,scm";
99 qcom,dload-mode = <&tc 99 qcom,dload-mode = <&tcsr 0x6100>;
100 }; 100 };
101 }; 101 };
102 102
103 memory@40000000 { 103 memory@40000000 {
104 device_type = "memory"; 104 device_type = "memory";
105 /* We expect the bootloader to 105 /* We expect the bootloader to fill in the size */
106 reg = <0x0 0x40000000 0x0 0x0> 106 reg = <0x0 0x40000000 0x0 0x0>;
107 }; 107 };
108 108
109 cpu_opp_table: opp-table-cpu { 109 cpu_opp_table: opp-table-cpu {
110 compatible = "operating-points 110 compatible = "operating-points-v2-kryo-cpu";
111 opp-shared; 111 opp-shared;
112 nvmem-cells = <&cpu_speed_bin> 112 nvmem-cells = <&cpu_speed_bin>;
113 113
114 opp-936000000 { 114 opp-936000000 {
115 opp-hz = /bits/ 64 <93 115 opp-hz = /bits/ 64 <936000000>;
116 opp-microvolt = <72500 116 opp-microvolt = <725000>;
117 opp-supported-hw = <0x 117 opp-supported-hw = <0xf>;
118 clock-latency-ns = <20 118 clock-latency-ns = <200000>;
119 }; 119 };
120 120
121 opp-1104000000 { 121 opp-1104000000 {
122 opp-hz = /bits/ 64 <11 122 opp-hz = /bits/ 64 <1104000000>;
123 opp-microvolt = <78750 123 opp-microvolt = <787500>;
124 opp-supported-hw = <0x 124 opp-supported-hw = <0xf>;
125 clock-latency-ns = <20 125 clock-latency-ns = <200000>;
126 }; 126 };
127 127
128 opp-1200000000 { 128 opp-1200000000 {
129 opp-hz = /bits/ 64 <12 129 opp-hz = /bits/ 64 <1200000000>;
130 opp-microvolt = <86250 130 opp-microvolt = <862500>;
131 opp-supported-hw = <0x 131 opp-supported-hw = <0xf>;
132 clock-latency-ns = <20 132 clock-latency-ns = <200000>;
133 }; 133 };
134 134
135 opp-1416000000 { 135 opp-1416000000 {
136 opp-hz = /bits/ 64 <14 136 opp-hz = /bits/ 64 <1416000000>;
137 opp-microvolt = <86250 137 opp-microvolt = <862500>;
138 opp-supported-hw = <0x 138 opp-supported-hw = <0x7>;
139 clock-latency-ns = <20 139 clock-latency-ns = <200000>;
140 }; 140 };
141 141
142 opp-1488000000 { 142 opp-1488000000 {
143 opp-hz = /bits/ 64 <14 143 opp-hz = /bits/ 64 <1488000000>;
144 opp-microvolt = <92500 144 opp-microvolt = <925000>;
145 opp-supported-hw = <0x 145 opp-supported-hw = <0x7>;
146 clock-latency-ns = <20 146 clock-latency-ns = <200000>;
147 }; 147 };
148 148
149 opp-1800000000 { 149 opp-1800000000 {
150 opp-hz = /bits/ 64 <18 150 opp-hz = /bits/ 64 <1800000000>;
151 opp-microvolt = <98750 151 opp-microvolt = <987500>;
152 opp-supported-hw = <0x 152 opp-supported-hw = <0x5>;
153 clock-latency-ns = <20 153 clock-latency-ns = <200000>;
154 }; 154 };
155 155
156 opp-2208000000 { 156 opp-2208000000 {
157 opp-hz = /bits/ 64 <22 157 opp-hz = /bits/ 64 <2208000000>;
158 opp-microvolt = <10625 158 opp-microvolt = <1062500>;
159 opp-supported-hw = <0x 159 opp-supported-hw = <0x1>;
160 clock-latency-ns = <20 160 clock-latency-ns = <200000>;
161 }; 161 };
162 }; 162 };
163 163
164 pmu { 164 pmu {
165 compatible = "arm,cortex-a73-p 165 compatible = "arm,cortex-a73-pmu";
166 interrupts = <GIC_PPI 7 (GIC_C 166 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
167 }; 167 };
168 168
169 psci { 169 psci {
170 compatible = "arm,psci-1.0"; 170 compatible = "arm,psci-1.0";
171 method = "smc"; 171 method = "smc";
172 }; 172 };
173 173
174 rpm: remoteproc { 174 rpm: remoteproc {
175 compatible = "qcom,ipq9574-rpm 175 compatible = "qcom,ipq9574-rpm-proc", "qcom,rpm-proc";
176 176
177 glink-edge { 177 glink-edge {
178 compatible = "qcom,gli 178 compatible = "qcom,glink-rpm";
179 interrupts = <GIC_SPI 179 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
180 qcom,rpm-msg-ram = <&r 180 qcom,rpm-msg-ram = <&rpm_msg_ram>;
181 mboxes = <&apcs_glb 0> 181 mboxes = <&apcs_glb 0>;
182 182
183 rpm_requests: rpm-requ 183 rpm_requests: rpm-requests {
184 compatible = " !! 184 compatible = "qcom,rpm-ipq9574";
185 qcom,glink-cha 185 qcom,glink-channels = "rpm_requests";
186 }; 186 };
187 }; 187 };
188 }; 188 };
189 189
190 reserved-memory { 190 reserved-memory {
191 #address-cells = <2>; 191 #address-cells = <2>;
192 #size-cells = <2>; 192 #size-cells = <2>;
193 ranges; 193 ranges;
194 194
195 bootloader@4a100000 { 195 bootloader@4a100000 {
196 reg = <0x0 0x4a100000 196 reg = <0x0 0x4a100000 0x0 0x400000>;
197 no-map; 197 no-map;
198 }; 198 };
199 199
200 sbl@4a500000 { 200 sbl@4a500000 {
201 reg = <0x0 0x4a500000 201 reg = <0x0 0x4a500000 0x0 0x100000>;
202 no-map; 202 no-map;
203 }; 203 };
204 204
205 tz_region: tz@4a600000 { 205 tz_region: tz@4a600000 {
206 reg = <0x0 0x4a600000 206 reg = <0x0 0x4a600000 0x0 0x400000>;
207 no-map; 207 no-map;
208 }; 208 };
209 209
210 smem@4aa00000 { 210 smem@4aa00000 {
211 compatible = "qcom,sme 211 compatible = "qcom,smem";
212 reg = <0x0 0x4aa00000 212 reg = <0x0 0x4aa00000 0x0 0x100000>;
213 hwlocks = <&tcsr_mutex 213 hwlocks = <&tcsr_mutex 3>;
214 no-map; 214 no-map;
215 }; 215 };
216 }; 216 };
217 217
218 soc: soc@0 { 218 soc: soc@0 {
219 compatible = "simple-bus"; 219 compatible = "simple-bus";
220 #address-cells = <1>; 220 #address-cells = <1>;
221 #size-cells = <1>; 221 #size-cells = <1>;
222 ranges = <0 0 0 0xffffffff>; 222 ranges = <0 0 0 0xffffffff>;
223 223
224 rpm_msg_ram: sram@60000 { 224 rpm_msg_ram: sram@60000 {
225 compatible = "qcom,rpm 225 compatible = "qcom,rpm-msg-ram";
226 reg = <0x00060000 0x60 226 reg = <0x00060000 0x6000>;
227 }; 227 };
228 228
229 rng: rng@e3000 { 229 rng: rng@e3000 {
230 compatible = "qcom,prn 230 compatible = "qcom,prng-ee";
231 reg = <0x000e3000 0x10 231 reg = <0x000e3000 0x1000>;
232 clocks = <&gcc GCC_PRN 232 clocks = <&gcc GCC_PRNG_AHB_CLK>;
233 clock-names = "core"; 233 clock-names = "core";
234 }; 234 };
235 235
236 mdio: mdio@90000 { 236 mdio: mdio@90000 {
237 compatible = "qcom,ip 237 compatible = "qcom,ipq9574-mdio", "qcom,ipq4019-mdio";
238 reg = <0x00090000 0x64 238 reg = <0x00090000 0x64>;
239 #address-cells = <1>; 239 #address-cells = <1>;
240 #size-cells = <0>; 240 #size-cells = <0>;
241 clocks = <&gcc GCC_MDI 241 clocks = <&gcc GCC_MDIO_AHB_CLK>;
242 clock-names = "gcc_mdi 242 clock-names = "gcc_mdio_ahb_clk";
243 status = "disabled"; 243 status = "disabled";
244 }; 244 };
245 245
246 qfprom: efuse@a4000 { 246 qfprom: efuse@a4000 {
247 compatible = "qcom,ipq 247 compatible = "qcom,ipq9574-qfprom", "qcom,qfprom";
248 reg = <0x000a4000 0x5a 248 reg = <0x000a4000 0x5a1>;
249 #address-cells = <1>; 249 #address-cells = <1>;
250 #size-cells = <1>; 250 #size-cells = <1>;
251 251
252 cpu_speed_bin: cpu-spe 252 cpu_speed_bin: cpu-speed-bin@15 {
253 reg = <0x15 0x 253 reg = <0x15 0x2>;
254 bits = <7 2>; 254 bits = <7 2>;
255 }; 255 };
256 }; 256 };
257 257
258 cryptobam: dma-controller@7040 258 cryptobam: dma-controller@704000 {
259 compatible = "qcom,bam 259 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
260 reg = <0x00704000 0x20 260 reg = <0x00704000 0x20000>;
261 interrupts = <GIC_SPI 261 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
262 #dma-cells = <1>; 262 #dma-cells = <1>;
263 qcom,ee = <1>; 263 qcom,ee = <1>;
264 qcom,controlled-remote 264 qcom,controlled-remotely;
265 }; 265 };
266 266
267 crypto: crypto@73a000 { 267 crypto: crypto@73a000 {
268 compatible = "qcom,ipq 268 compatible = "qcom,ipq9574-qce", "qcom,ipq4019-qce", "qcom,qce";
269 reg = <0x0073a000 0x60 269 reg = <0x0073a000 0x6000>;
270 clocks = <&gcc GCC_CRY 270 clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
271 <&gcc GCC_CRY 271 <&gcc GCC_CRYPTO_AXI_CLK>,
272 <&gcc GCC_CRY 272 <&gcc GCC_CRYPTO_CLK>;
273 clock-names = "iface", 273 clock-names = "iface", "bus", "core";
274 dmas = <&cryptobam 2>, 274 dmas = <&cryptobam 2>, <&cryptobam 3>;
275 dma-names = "rx", "tx" 275 dma-names = "rx", "tx";
276 }; 276 };
277 277
278 tsens: thermal-sensor@4a9000 { 278 tsens: thermal-sensor@4a9000 {
279 compatible = "qcom,ipq 279 compatible = "qcom,ipq9574-tsens", "qcom,ipq8074-tsens";
280 reg = <0x004a9000 0x10 280 reg = <0x004a9000 0x1000>,
281 <0x004a8000 0x10 281 <0x004a8000 0x1000>;
282 interrupts = <GIC_SPI 282 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
283 interrupt-names = "com 283 interrupt-names = "combined";
284 #qcom,sensors = <16>; 284 #qcom,sensors = <16>;
285 #thermal-sensor-cells 285 #thermal-sensor-cells = <1>;
286 }; 286 };
287 287
288 tlmm: pinctrl@1000000 { 288 tlmm: pinctrl@1000000 {
289 compatible = "qcom,ipq 289 compatible = "qcom,ipq9574-tlmm";
290 reg = <0x01000000 0x30 290 reg = <0x01000000 0x300000>;
291 interrupts = <GIC_SPI 291 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
292 gpio-controller; 292 gpio-controller;
293 #gpio-cells = <2>; 293 #gpio-cells = <2>;
294 gpio-ranges = <&tlmm 0 294 gpio-ranges = <&tlmm 0 0 65>;
295 interrupt-controller; 295 interrupt-controller;
296 #interrupt-cells = <2> 296 #interrupt-cells = <2>;
297 297
298 uart2_pins: uart2-stat 298 uart2_pins: uart2-state {
299 pins = "gpio34 299 pins = "gpio34", "gpio35";
300 function = "bl 300 function = "blsp2_uart";
301 drive-strength 301 drive-strength = <8>;
302 bias-disable; 302 bias-disable;
303 }; 303 };
304 }; 304 };
305 305
306 gcc: clock-controller@1800000 306 gcc: clock-controller@1800000 {
307 compatible = "qcom,ipq 307 compatible = "qcom,ipq9574-gcc";
308 reg = <0x01800000 0x80 308 reg = <0x01800000 0x80000>;
309 clocks = <&xo_board_cl 309 clocks = <&xo_board_clk>,
310 <&sleep_clk>, 310 <&sleep_clk>,
311 <0>, 311 <0>,
312 <0>, 312 <0>,
313 <0>, 313 <0>,
314 <0>, 314 <0>,
315 <0>, 315 <0>,
316 <0>; 316 <0>;
317 #clock-cells = <1>; 317 #clock-cells = <1>;
318 #reset-cells = <1>; 318 #reset-cells = <1>;
319 #interconnect-cells = 319 #interconnect-cells = <1>;
320 }; 320 };
321 321
322 tcsr_mutex: hwlock@1905000 { 322 tcsr_mutex: hwlock@1905000 {
323 compatible = "qcom,tcs 323 compatible = "qcom,tcsr-mutex";
324 reg = <0x01905000 0x20 324 reg = <0x01905000 0x20000>;
325 #hwlock-cells = <1>; 325 #hwlock-cells = <1>;
326 }; 326 };
327 327
328 tcsr: syscon@1937000 { 328 tcsr: syscon@1937000 {
329 compatible = "qcom,tcs 329 compatible = "qcom,tcsr-ipq9574", "syscon";
330 reg = <0x01937000 0x21 330 reg = <0x01937000 0x21000>;
331 }; 331 };
332 332
333 sdhc_1: mmc@7804000 { 333 sdhc_1: mmc@7804000 {
334 compatible = "qcom,ipq 334 compatible = "qcom,ipq9574-sdhci", "qcom,sdhci-msm-v5";
335 reg = <0x07804000 0x10 335 reg = <0x07804000 0x1000>,
336 <0x07805000 0x10 336 <0x07805000 0x1000>,
337 <0x07808000 0x20 337 <0x07808000 0x2000>;
338 reg-names = "hc", "cqh 338 reg-names = "hc", "cqhci", "ice";
339 339
340 interrupts = <GIC_SPI 340 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
341 <GIC_SPI 341 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
342 interrupt-names = "hc_ 342 interrupt-names = "hc_irq", "pwr_irq";
343 343
344 clocks = <&gcc GCC_SDC 344 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
345 <&gcc GCC_SDC 345 <&gcc GCC_SDCC1_APPS_CLK>,
346 <&xo_board_cl 346 <&xo_board_clk>,
347 <&gcc GCC_SDC 347 <&gcc GCC_SDCC1_ICE_CORE_CLK>;
348 clock-names = "iface", 348 clock-names = "iface", "core", "xo", "ice";
349 non-removable; 349 non-removable;
350 supports-cqe; 350 supports-cqe;
351 status = "disabled"; 351 status = "disabled";
352 }; 352 };
353 353
354 blsp_dma: dma-controller@78840 354 blsp_dma: dma-controller@7884000 {
355 compatible = "qcom,bam 355 compatible = "qcom,bam-v1.7.0";
356 reg = <0x07884000 0x2b 356 reg = <0x07884000 0x2b000>;
357 interrupts = <GIC_SPI 357 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
358 clocks = <&gcc GCC_BLS 358 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
359 clock-names = "bam_clk 359 clock-names = "bam_clk";
360 #dma-cells = <1>; 360 #dma-cells = <1>;
361 qcom,ee = <0>; 361 qcom,ee = <0>;
362 }; 362 };
363 363
364 blsp1_uart0: serial@78af000 { 364 blsp1_uart0: serial@78af000 {
365 compatible = "qcom,msm 365 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
366 reg = <0x078af000 0x20 366 reg = <0x078af000 0x200>;
367 interrupts = <GIC_SPI 367 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
368 clocks = <&gcc GCC_BLS 368 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
369 <&gcc GCC_BLS 369 <&gcc GCC_BLSP1_AHB_CLK>;
370 clock-names = "core", 370 clock-names = "core", "iface";
371 status = "disabled"; 371 status = "disabled";
372 }; 372 };
373 373
374 blsp1_uart1: serial@78b0000 { 374 blsp1_uart1: serial@78b0000 {
375 compatible = "qcom,msm 375 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
376 reg = <0x078b0000 0x20 376 reg = <0x078b0000 0x200>;
377 interrupts = <GIC_SPI 377 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
378 clocks = <&gcc GCC_BLS 378 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
379 <&gcc GCC_BLS 379 <&gcc GCC_BLSP1_AHB_CLK>;
380 clock-names = "core", 380 clock-names = "core", "iface";
381 status = "disabled"; 381 status = "disabled";
382 }; 382 };
383 383
384 blsp1_uart2: serial@78b1000 { 384 blsp1_uart2: serial@78b1000 {
385 compatible = "qcom,msm 385 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
386 reg = <0x078b1000 0x20 386 reg = <0x078b1000 0x200>;
387 interrupts = <GIC_SPI 387 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
388 clocks = <&gcc GCC_BLS 388 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
389 <&gcc GCC_BLS 389 <&gcc GCC_BLSP1_AHB_CLK>;
390 clock-names = "core", 390 clock-names = "core", "iface";
391 status = "disabled"; 391 status = "disabled";
392 }; 392 };
393 393
394 blsp1_uart3: serial@78b2000 { 394 blsp1_uart3: serial@78b2000 {
395 compatible = "qcom,msm 395 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
396 reg = <0x078b2000 0x20 396 reg = <0x078b2000 0x200>;
397 interrupts = <GIC_SPI 397 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
398 clocks = <&gcc GCC_BLS 398 clocks = <&gcc GCC_BLSP1_UART4_APPS_CLK>,
399 <&gcc GCC_BLS 399 <&gcc GCC_BLSP1_AHB_CLK>;
400 clock-names = "core", 400 clock-names = "core", "iface";
401 status = "disabled"; 401 status = "disabled";
402 }; 402 };
403 403
404 blsp1_uart4: serial@78b3000 { 404 blsp1_uart4: serial@78b3000 {
405 compatible = "qcom,msm 405 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
406 reg = <0x078b3000 0x20 406 reg = <0x078b3000 0x200>;
407 interrupts = <GIC_SPI 407 interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
408 clocks = <&gcc GCC_BLS 408 clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>,
409 <&gcc GCC_BLS 409 <&gcc GCC_BLSP1_AHB_CLK>;
410 clock-names = "core", 410 clock-names = "core", "iface";
411 status = "disabled"; 411 status = "disabled";
412 }; 412 };
413 413
414 blsp1_uart5: serial@78b4000 { 414 blsp1_uart5: serial@78b4000 {
415 compatible = "qcom,msm 415 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
416 reg = <0x078b4000 0x20 416 reg = <0x078b4000 0x200>;
417 interrupts = <GIC_SPI 417 interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>;
418 clocks = <&gcc GCC_BLS 418 clocks = <&gcc GCC_BLSP1_UART6_APPS_CLK>,
419 <&gcc GCC_BLS 419 <&gcc GCC_BLSP1_AHB_CLK>;
420 clock-names = "core", 420 clock-names = "core", "iface";
421 status = "disabled"; 421 status = "disabled";
422 }; 422 };
423 423
424 blsp1_spi0: spi@78b5000 { 424 blsp1_spi0: spi@78b5000 {
425 compatible = "qcom,spi 425 compatible = "qcom,spi-qup-v2.2.1";
426 reg = <0x078b5000 0x60 426 reg = <0x078b5000 0x600>;
427 #address-cells = <1>; 427 #address-cells = <1>;
428 #size-cells = <0>; 428 #size-cells = <0>;
429 interrupts = <GIC_SPI 429 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
430 clocks = <&gcc GCC_BLS 430 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
431 <&gcc GCC_BLS 431 <&gcc GCC_BLSP1_AHB_CLK>;
432 clock-names = "core", 432 clock-names = "core", "iface";
433 dmas = <&blsp_dma 12>, 433 dmas = <&blsp_dma 12>, <&blsp_dma 13>;
434 dma-names = "tx", "rx" 434 dma-names = "tx", "rx";
435 status = "disabled"; 435 status = "disabled";
436 }; 436 };
437 437
438 blsp1_i2c1: i2c@78b6000 { 438 blsp1_i2c1: i2c@78b6000 {
439 compatible = "qcom,i2c 439 compatible = "qcom,i2c-qup-v2.2.1";
440 reg = <0x078b6000 0x60 440 reg = <0x078b6000 0x600>;
441 #address-cells = <1>; 441 #address-cells = <1>;
442 #size-cells = <0>; 442 #size-cells = <0>;
443 interrupts = <GIC_SPI 443 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
444 clocks = <&gcc GCC_BLS 444 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
445 <&gcc GCC_BLS 445 <&gcc GCC_BLSP1_AHB_CLK>;
446 clock-names = "core", 446 clock-names = "core", "iface";
447 assigned-clocks = <&gc 447 assigned-clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
448 assigned-clock-rates = 448 assigned-clock-rates = <50000000>;
449 dmas = <&blsp_dma 14>, 449 dmas = <&blsp_dma 14>, <&blsp_dma 15>;
450 dma-names = "tx", "rx" 450 dma-names = "tx", "rx";
451 status = "disabled"; 451 status = "disabled";
452 }; 452 };
453 453
454 blsp1_spi1: spi@78b6000 { 454 blsp1_spi1: spi@78b6000 {
455 compatible = "qcom,spi 455 compatible = "qcom,spi-qup-v2.2.1";
456 reg = <0x078b6000 0x60 456 reg = <0x078b6000 0x600>;
457 #address-cells = <1>; 457 #address-cells = <1>;
458 #size-cells = <0>; 458 #size-cells = <0>;
459 interrupts = <GIC_SPI 459 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
460 clocks = <&gcc GCC_BLS 460 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
461 <&gcc GCC_BLS 461 <&gcc GCC_BLSP1_AHB_CLK>;
462 clock-names = "core", 462 clock-names = "core", "iface";
463 dmas = <&blsp_dma 14>, 463 dmas = <&blsp_dma 14>, <&blsp_dma 15>;
464 dma-names = "tx", "rx" 464 dma-names = "tx", "rx";
465 status = "disabled"; 465 status = "disabled";
466 }; 466 };
467 467
468 blsp1_i2c2: i2c@78b7000 { 468 blsp1_i2c2: i2c@78b7000 {
469 compatible = "qcom,i2c 469 compatible = "qcom,i2c-qup-v2.2.1";
470 reg = <0x078b7000 0x60 470 reg = <0x078b7000 0x600>;
471 #address-cells = <1>; 471 #address-cells = <1>;
472 #size-cells = <0>; 472 #size-cells = <0>;
473 interrupts = <GIC_SPI 473 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
474 clocks = <&gcc GCC_BLS 474 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
475 <&gcc GCC_BLS 475 <&gcc GCC_BLSP1_AHB_CLK>;
476 clock-names = "core", 476 clock-names = "core", "iface";
477 assigned-clocks = <&gc 477 assigned-clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
478 assigned-clock-rates = 478 assigned-clock-rates = <50000000>;
479 dmas = <&blsp_dma 16>, 479 dmas = <&blsp_dma 16>, <&blsp_dma 17>;
480 dma-names = "tx", "rx" 480 dma-names = "tx", "rx";
481 status = "disabled"; 481 status = "disabled";
482 }; 482 };
483 483
484 blsp1_spi2: spi@78b7000 { 484 blsp1_spi2: spi@78b7000 {
485 compatible = "qcom,spi 485 compatible = "qcom,spi-qup-v2.2.1";
486 reg = <0x078b7000 0x60 486 reg = <0x078b7000 0x600>;
487 #address-cells = <1>; 487 #address-cells = <1>;
488 #size-cells = <0>; 488 #size-cells = <0>;
489 interrupts = <GIC_SPI 489 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
490 clocks = <&gcc GCC_BLS 490 clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
491 <&gcc GCC_BLS 491 <&gcc GCC_BLSP1_AHB_CLK>;
492 clock-names = "core", 492 clock-names = "core", "iface";
493 dmas = <&blsp_dma 16>, 493 dmas = <&blsp_dma 16>, <&blsp_dma 17>;
494 dma-names = "tx", "rx" 494 dma-names = "tx", "rx";
495 status = "disabled"; 495 status = "disabled";
496 }; 496 };
497 497
498 blsp1_i2c3: i2c@78b8000 { 498 blsp1_i2c3: i2c@78b8000 {
499 compatible = "qcom,i2c 499 compatible = "qcom,i2c-qup-v2.2.1";
500 reg = <0x078b8000 0x60 500 reg = <0x078b8000 0x600>;
501 #address-cells = <1>; 501 #address-cells = <1>;
502 #size-cells = <0>; 502 #size-cells = <0>;
503 interrupts = <GIC_SPI 503 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
504 clocks = <&gcc GCC_BLS 504 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
505 <&gcc GCC_BLS 505 <&gcc GCC_BLSP1_AHB_CLK>;
506 clock-names = "core", 506 clock-names = "core", "iface";
507 assigned-clocks = <&gc 507 assigned-clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
508 assigned-clock-rates = 508 assigned-clock-rates = <50000000>;
509 dmas = <&blsp_dma 18>, 509 dmas = <&blsp_dma 18>, <&blsp_dma 19>;
510 dma-names = "tx", "rx" 510 dma-names = "tx", "rx";
511 status = "disabled"; 511 status = "disabled";
512 }; 512 };
513 513
514 blsp1_spi3: spi@78b8000 { 514 blsp1_spi3: spi@78b8000 {
515 compatible = "qcom,spi 515 compatible = "qcom,spi-qup-v2.2.1";
516 reg = <0x078b8000 0x60 516 reg = <0x078b8000 0x600>;
517 #address-cells = <1>; 517 #address-cells = <1>;
518 #size-cells = <0>; 518 #size-cells = <0>;
519 interrupts = <GIC_SPI 519 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
520 spi-max-frequency = <5 520 spi-max-frequency = <50000000>;
521 clocks = <&gcc GCC_BLS 521 clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
522 <&gcc GCC_BLS 522 <&gcc GCC_BLSP1_AHB_CLK>;
523 clock-names = "core", 523 clock-names = "core", "iface";
524 dmas = <&blsp_dma 18>, 524 dmas = <&blsp_dma 18>, <&blsp_dma 19>;
525 dma-names = "tx", "rx" 525 dma-names = "tx", "rx";
526 status = "disabled"; 526 status = "disabled";
527 }; 527 };
528 528
529 blsp1_i2c4: i2c@78b9000 { 529 blsp1_i2c4: i2c@78b9000 {
530 compatible = "qcom,i2c 530 compatible = "qcom,i2c-qup-v2.2.1";
531 reg = <0x078b9000 0x60 531 reg = <0x078b9000 0x600>;
532 #address-cells = <1>; 532 #address-cells = <1>;
533 #size-cells = <0>; 533 #size-cells = <0>;
534 interrupts = <GIC_SPI 534 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
535 clocks = <&gcc GCC_BLS 535 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
536 <&gcc GCC_BLS 536 <&gcc GCC_BLSP1_AHB_CLK>;
537 clock-names = "core", 537 clock-names = "core", "iface";
538 assigned-clocks = <&gc 538 assigned-clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>;
539 assigned-clock-rates = 539 assigned-clock-rates = <50000000>;
540 dmas = <&blsp_dma 20>, 540 dmas = <&blsp_dma 20>, <&blsp_dma 21>;
541 dma-names = "tx", "rx" 541 dma-names = "tx", "rx";
542 status = "disabled"; 542 status = "disabled";
543 }; 543 };
544 544
545 blsp1_spi4: spi@78b9000 { 545 blsp1_spi4: spi@78b9000 {
546 compatible = "qcom,spi 546 compatible = "qcom,spi-qup-v2.2.1";
547 reg = <0x078b9000 0x60 547 reg = <0x078b9000 0x600>;
548 #address-cells = <1>; 548 #address-cells = <1>;
549 #size-cells = <0>; 549 #size-cells = <0>;
550 interrupts = <GIC_SPI 550 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
551 clocks = <&gcc GCC_BLS 551 clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
552 <&gcc GCC_BLS 552 <&gcc GCC_BLSP1_AHB_CLK>;
553 clock-names = "core", 553 clock-names = "core", "iface";
554 dmas = <&blsp_dma 20>, 554 dmas = <&blsp_dma 20>, <&blsp_dma 21>;
555 dma-names = "tx", "rx" 555 dma-names = "tx", "rx";
556 status = "disabled"; 556 status = "disabled";
557 }; 557 };
558 558
559 usb_0_qusbphy: phy@7b000 { 559 usb_0_qusbphy: phy@7b000 {
560 compatible = "qcom,ipq 560 compatible = "qcom,ipq9574-qusb2-phy";
561 reg = <0x0007b000 0x18 561 reg = <0x0007b000 0x180>;
562 #phy-cells = <0>; 562 #phy-cells = <0>;
563 563
564 clocks = <&gcc GCC_USB 564 clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
565 <&xo_board_cl 565 <&xo_board_clk>;
566 clock-names = "cfg_ahb 566 clock-names = "cfg_ahb",
567 "ref"; 567 "ref";
568 568
569 resets = <&gcc GCC_QUS 569 resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
570 status = "disabled"; 570 status = "disabled";
571 }; 571 };
572 572
573 usb_0_qmpphy: phy@7d000 { 573 usb_0_qmpphy: phy@7d000 {
574 compatible = "qcom,ipq 574 compatible = "qcom,ipq9574-qmp-usb3-phy";
575 reg = <0x0007d000 0xa0 575 reg = <0x0007d000 0xa00>;
576 #phy-cells = <0>; 576 #phy-cells = <0>;
577 577
578 clocks = <&gcc GCC_USB 578 clocks = <&gcc GCC_USB0_AUX_CLK>,
579 <&xo_board_cl 579 <&xo_board_clk>,
580 <&gcc GCC_USB 580 <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
581 <&gcc GCC_USB 581 <&gcc GCC_USB0_PIPE_CLK>;
582 clock-names = "aux", 582 clock-names = "aux",
583 "ref", 583 "ref",
584 "cfg_ahb 584 "cfg_ahb",
585 "pipe"; 585 "pipe";
586 586
587 resets = <&gcc GCC_USB 587 resets = <&gcc GCC_USB0_PHY_BCR>,
588 <&gcc GCC_USB 588 <&gcc GCC_USB3PHY_0_PHY_BCR>;
589 reset-names = "phy", 589 reset-names = "phy",
590 "phy_phy 590 "phy_phy";
591 591
592 #clock-cells = <0>; 592 #clock-cells = <0>;
593 clock-output-names = " 593 clock-output-names = "usb0_pipe_clk";
594 594
595 status = "disabled"; 595 status = "disabled";
596 }; 596 };
597 597
598 usb3: usb@8af8800 { 598 usb3: usb@8af8800 {
599 compatible = "qcom,ipq 599 compatible = "qcom,ipq9574-dwc3", "qcom,dwc3";
600 reg = <0x08af8800 0x40 600 reg = <0x08af8800 0x400>;
601 #address-cells = <1>; 601 #address-cells = <1>;
602 #size-cells = <1>; 602 #size-cells = <1>;
603 ranges; 603 ranges;
604 604
605 clocks = <&gcc GCC_SNO 605 clocks = <&gcc GCC_SNOC_USB_CLK>,
606 <&gcc GCC_USB 606 <&gcc GCC_USB0_MASTER_CLK>,
607 <&gcc GCC_ANO 607 <&gcc GCC_ANOC_USB_AXI_CLK>,
608 <&gcc GCC_USB 608 <&gcc GCC_USB0_SLEEP_CLK>,
609 <&gcc GCC_USB 609 <&gcc GCC_USB0_MOCK_UTMI_CLK>;
610 610
611 clock-names = "cfg_noc 611 clock-names = "cfg_noc",
612 "core", 612 "core",
613 "iface", 613 "iface",
614 "sleep", 614 "sleep",
615 "mock_ut 615 "mock_utmi";
616 616
617 assigned-clocks = <&gc 617 assigned-clocks = <&gcc GCC_USB0_MASTER_CLK>,
618 <&gc 618 <&gcc GCC_USB0_MOCK_UTMI_CLK>;
619 assigned-clock-rates = 619 assigned-clock-rates = <200000000>,
620 620 <24000000>;
621 621
622 interrupts-extended = 622 interrupts-extended = <&intc GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
623 interrupt-names = "pwr 623 interrupt-names = "pwr_event";
624 624
625 resets = <&gcc GCC_USB 625 resets = <&gcc GCC_USB_BCR>;
626 status = "disabled"; 626 status = "disabled";
627 627
628 usb_0_dwc3: usb@8a0000 628 usb_0_dwc3: usb@8a00000 {
629 compatible = " 629 compatible = "snps,dwc3";
630 reg = <0x8a000 630 reg = <0x8a00000 0xcd00>;
631 clocks = <&gcc 631 clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>;
632 clock-names = 632 clock-names = "ref";
633 interrupts = < 633 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
634 phys = <&usb_0 634 phys = <&usb_0_qusbphy>, <&usb_0_qmpphy>;
635 phy-names = "u 635 phy-names = "usb2-phy", "usb3-phy";
636 tx-fifo-resize 636 tx-fifo-resize;
637 snps,is-utmi-l 637 snps,is-utmi-l1-suspend;
638 snps,hird-thre 638 snps,hird-threshold = /bits/ 8 <0x0>;
639 snps,dis_u2_su 639 snps,dis_u2_susphy_quirk;
640 snps,dis_u3_su 640 snps,dis_u3_susphy_quirk;
641 }; 641 };
642 }; 642 };
643 643
644 intc: interrupt-controller@b00 644 intc: interrupt-controller@b000000 {
645 compatible = "qcom,msm 645 compatible = "qcom,msm-qgic2";
646 reg = <0x0b000000 0x10 646 reg = <0x0b000000 0x1000>, /* GICD */
647 <0x0b002000 0x20 647 <0x0b002000 0x2000>, /* GICC */
648 <0x0b001000 0x10 648 <0x0b001000 0x1000>, /* GICH */
649 <0x0b004000 0x20 649 <0x0b004000 0x2000>; /* GICV */
650 #address-cells = <1>; 650 #address-cells = <1>;
651 #size-cells = <1>; 651 #size-cells = <1>;
652 interrupt-controller; 652 interrupt-controller;
653 #interrupt-cells = <3> 653 #interrupt-cells = <3>;
654 interrupts = <GIC_PPI 654 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
655 ranges = <0 0x0b00c000 655 ranges = <0 0x0b00c000 0x3000>;
656 656
657 v2m0: v2m@0 { 657 v2m0: v2m@0 {
658 compatible = " 658 compatible = "arm,gic-v2m-frame";
659 reg = <0x00000 659 reg = <0x00000000 0xffd>;
660 msi-controller 660 msi-controller;
661 }; 661 };
662 662
663 v2m1: v2m@1000 { 663 v2m1: v2m@1000 {
664 compatible = " 664 compatible = "arm,gic-v2m-frame";
665 reg = <0x00001 665 reg = <0x00001000 0xffd>;
666 msi-controller 666 msi-controller;
667 }; 667 };
668 668
669 v2m2: v2m@2000 { 669 v2m2: v2m@2000 {
670 compatible = " 670 compatible = "arm,gic-v2m-frame";
671 reg = <0x00002 671 reg = <0x00002000 0xffd>;
672 msi-controller 672 msi-controller;
673 }; 673 };
674 }; 674 };
675 675
676 watchdog: watchdog@b017000 { 676 watchdog: watchdog@b017000 {
677 compatible = "qcom,aps 677 compatible = "qcom,apss-wdt-ipq9574", "qcom,kpss-wdt";
678 reg = <0x0b017000 0x10 678 reg = <0x0b017000 0x1000>;
679 interrupts = <GIC_SPI 679 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
680 clocks = <&sleep_clk>; 680 clocks = <&sleep_clk>;
681 timeout-sec = <30>; 681 timeout-sec = <30>;
682 }; 682 };
683 683
684 apcs_glb: mailbox@b111000 { 684 apcs_glb: mailbox@b111000 {
685 compatible = "qcom,ipq 685 compatible = "qcom,ipq9574-apcs-apps-global",
686 "qcom,ipq 686 "qcom,ipq6018-apcs-apps-global";
687 reg = <0x0b111000 0x10 687 reg = <0x0b111000 0x1000>;
688 #clock-cells = <1>; 688 #clock-cells = <1>;
689 clocks = <&a73pll>, <& 689 clocks = <&a73pll>, <&xo_board_clk>, <&gcc GPLL0>;
690 clock-names = "pll", " 690 clock-names = "pll", "xo", "gpll0";
691 #mbox-cells = <1>; 691 #mbox-cells = <1>;
692 }; 692 };
693 693
694 a73pll: clock@b116000 { 694 a73pll: clock@b116000 {
695 compatible = "qcom,ipq 695 compatible = "qcom,ipq9574-a73pll";
696 reg = <0x0b116000 0x40 696 reg = <0x0b116000 0x40>;
697 #clock-cells = <0>; 697 #clock-cells = <0>;
698 clocks = <&xo_board_cl 698 clocks = <&xo_board_clk>;
699 clock-names = "xo"; 699 clock-names = "xo";
700 }; 700 };
701 701
702 timer@b120000 { 702 timer@b120000 {
703 compatible = "arm,armv 703 compatible = "arm,armv7-timer-mem";
704 reg = <0x0b120000 0x10 704 reg = <0x0b120000 0x1000>;
705 #address-cells = <1>; 705 #address-cells = <1>;
706 #size-cells = <1>; 706 #size-cells = <1>;
707 ranges; 707 ranges;
708 708
709 frame@b120000 { 709 frame@b120000 {
710 reg = <0x0b121 710 reg = <0x0b121000 0x1000>,
711 <0x0b122 711 <0x0b122000 0x1000>;
712 frame-number = 712 frame-number = <0>;
713 interrupts = < 713 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
714 < 714 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
715 }; 715 };
716 716
717 frame@b123000 { 717 frame@b123000 {
718 reg = <0x0b123 718 reg = <0x0b123000 0x1000>;
719 frame-number = 719 frame-number = <1>;
720 interrupts = < 720 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
721 status = "disa 721 status = "disabled";
722 }; 722 };
723 723
724 frame@b124000 { 724 frame@b124000 {
725 reg = <0x0b124 725 reg = <0x0b124000 0x1000>;
726 frame-number = 726 frame-number = <2>;
727 interrupts = < 727 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
728 status = "disa 728 status = "disabled";
729 }; 729 };
730 730
731 frame@b125000 { 731 frame@b125000 {
732 reg = <0x0b125 732 reg = <0x0b125000 0x1000>;
733 frame-number = 733 frame-number = <3>;
734 interrupts = < 734 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
735 status = "disa 735 status = "disabled";
736 }; 736 };
737 737
738 frame@b126000 { 738 frame@b126000 {
739 reg = <0x0b126 739 reg = <0x0b126000 0x1000>;
740 frame-number = 740 frame-number = <4>;
741 interrupts = < 741 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
742 status = "disa 742 status = "disabled";
743 }; 743 };
744 744
745 frame@b127000 { 745 frame@b127000 {
746 reg = <0x0b127 746 reg = <0x0b127000 0x1000>;
747 frame-number = 747 frame-number = <5>;
748 interrupts = < 748 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
749 status = "disa 749 status = "disabled";
750 }; 750 };
751 751
752 frame@b128000 { 752 frame@b128000 {
753 reg = <0x0b128 753 reg = <0x0b128000 0x1000>;
754 frame-number = 754 frame-number = <6>;
755 interrupts = < 755 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
756 status = "disa 756 status = "disabled";
757 }; 757 };
758 }; 758 };
759 }; 759 };
760 760
761 thermal-zones { 761 thermal-zones {
762 nss-top-thermal { 762 nss-top-thermal {
763 thermal-sensors = <&ts 763 thermal-sensors = <&tsens 3>;
764 764
765 trips { 765 trips {
766 nss-top-critic 766 nss-top-critical {
767 temper 767 temperature = <125000>;
768 hyster 768 hysteresis = <1000>;
769 type = 769 type = "critical";
770 }; 770 };
771 }; 771 };
772 }; 772 };
773 773
774 ubi-0-thermal { 774 ubi-0-thermal {
775 thermal-sensors = <&ts 775 thermal-sensors = <&tsens 4>;
776 776
777 trips { 777 trips {
778 ubi_0-critical 778 ubi_0-critical {
779 temper 779 temperature = <125000>;
780 hyster 780 hysteresis = <1000>;
781 type = 781 type = "critical";
782 }; 782 };
783 }; 783 };
784 }; 784 };
785 785
786 ubi-1-thermal { 786 ubi-1-thermal {
787 thermal-sensors = <&ts 787 thermal-sensors = <&tsens 5>;
788 788
789 trips { 789 trips {
790 ubi_1-critical 790 ubi_1-critical {
791 temper 791 temperature = <125000>;
792 hyster 792 hysteresis = <1000>;
793 type = 793 type = "critical";
794 }; 794 };
795 }; 795 };
796 }; 796 };
797 797
798 ubi-2-thermal { 798 ubi-2-thermal {
799 thermal-sensors = <&ts 799 thermal-sensors = <&tsens 6>;
800 800
801 trips { 801 trips {
802 ubi_2-critical 802 ubi_2-critical {
803 temper 803 temperature = <125000>;
804 hyster 804 hysteresis = <1000>;
805 type = 805 type = "critical";
806 }; 806 };
807 }; 807 };
808 }; 808 };
809 809
810 ubi-3-thermal { 810 ubi-3-thermal {
811 thermal-sensors = <&ts 811 thermal-sensors = <&tsens 7>;
812 812
813 trips { 813 trips {
814 ubi_3-critical 814 ubi_3-critical {
815 temper 815 temperature = <125000>;
816 hyster 816 hysteresis = <1000>;
817 type = 817 type = "critical";
818 }; 818 };
819 }; 819 };
820 }; 820 };
821 821
822 cpuss0-thermal { 822 cpuss0-thermal {
823 thermal-sensors = <&ts 823 thermal-sensors = <&tsens 8>;
824 824
825 trips { 825 trips {
826 cpu-critical { 826 cpu-critical {
827 temper 827 temperature = <125000>;
828 hyster 828 hysteresis = <1000>;
829 type = 829 type = "critical";
830 }; 830 };
831 }; 831 };
832 }; 832 };
833 833
834 cpuss1-thermal { 834 cpuss1-thermal {
835 thermal-sensors = <&ts 835 thermal-sensors = <&tsens 9>;
836 836
837 trips { 837 trips {
838 cpu-critical { 838 cpu-critical {
839 temper 839 temperature = <125000>;
840 hyster 840 hysteresis = <1000>;
841 type = 841 type = "critical";
842 }; 842 };
843 }; 843 };
844 }; 844 };
845 845
846 cpu0-thermal { 846 cpu0-thermal {
847 thermal-sensors = <&ts 847 thermal-sensors = <&tsens 10>;
848 848
849 trips { 849 trips {
850 cpu0_crit: cpu 850 cpu0_crit: cpu-critical {
851 temper 851 temperature = <120000>;
852 hyster 852 hysteresis = <10000>;
853 type = 853 type = "critical";
854 }; 854 };
855 855
856 cpu0_alert: cp 856 cpu0_alert: cpu-passive {
857 temper 857 temperature = <110000>;
858 hyster 858 hysteresis = <1000>;
859 type = 859 type = "passive";
860 }; 860 };
861 }; 861 };
862 862
863 cooling-maps { 863 cooling-maps {
864 map0 { 864 map0 {
865 trip = 865 trip = <&cpu0_alert>;
866 coolin 866 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
867 867 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
868 868 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
869 869 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
870 }; 870 };
871 }; 871 };
872 }; 872 };
873 873
874 cpu1-thermal { 874 cpu1-thermal {
875 thermal-sensors = <&ts 875 thermal-sensors = <&tsens 11>;
876 876
877 trips { 877 trips {
878 cpu1_crit: cpu 878 cpu1_crit: cpu-critical {
879 temper 879 temperature = <120000>;
880 hyster 880 hysteresis = <10000>;
881 type = 881 type = "critical";
882 }; 882 };
883 883
884 cpu1_alert: cp 884 cpu1_alert: cpu-passive {
885 temper 885 temperature = <110000>;
886 hyster 886 hysteresis = <1000>;
887 type = 887 type = "passive";
888 }; 888 };
889 }; 889 };
890 890
891 cooling-maps { 891 cooling-maps {
892 map0 { 892 map0 {
893 trip = 893 trip = <&cpu1_alert>;
894 coolin 894 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
895 895 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
896 896 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
897 897 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
898 }; 898 };
899 }; 899 };
900 }; 900 };
901 901
902 cpu2-thermal { 902 cpu2-thermal {
903 thermal-sensors = <&ts 903 thermal-sensors = <&tsens 12>;
904 904
905 trips { 905 trips {
906 cpu2_crit: cpu 906 cpu2_crit: cpu-critical {
907 temper 907 temperature = <120000>;
908 hyster 908 hysteresis = <10000>;
909 type = 909 type = "critical";
910 }; 910 };
911 911
912 cpu2_alert: cp 912 cpu2_alert: cpu-passive {
913 temper 913 temperature = <110000>;
914 hyster 914 hysteresis = <1000>;
915 type = 915 type = "passive";
916 }; 916 };
917 }; 917 };
918 918
919 cooling-maps { 919 cooling-maps {
920 map0 { 920 map0 {
921 trip = 921 trip = <&cpu2_alert>;
922 coolin 922 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
923 923 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
924 924 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
925 925 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
926 }; 926 };
927 }; 927 };
928 }; 928 };
929 929
930 cpu3-thermal { 930 cpu3-thermal {
931 thermal-sensors = <&ts 931 thermal-sensors = <&tsens 13>;
932 932
933 trips { 933 trips {
934 cpu3_crit: cpu 934 cpu3_crit: cpu-critical {
935 temper 935 temperature = <120000>;
936 hyster 936 hysteresis = <10000>;
937 type = 937 type = "critical";
938 }; 938 };
939 939
940 cpu3_alert: cp 940 cpu3_alert: cpu-passive {
941 temper 941 temperature = <110000>;
942 hyster 942 hysteresis = <1000>;
943 type = 943 type = "passive";
944 }; 944 };
945 }; 945 };
946 946
947 cooling-maps { 947 cooling-maps {
948 map0 { 948 map0 {
949 trip = 949 trip = <&cpu3_alert>;
950 coolin 950 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
951 951 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
952 952 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
953 953 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
954 }; 954 };
955 }; 955 };
956 }; 956 };
957 957
958 wcss-phyb-thermal { 958 wcss-phyb-thermal {
959 thermal-sensors = <&ts 959 thermal-sensors = <&tsens 14>;
960 960
961 trips { 961 trips {
962 wcss_phyb-crit 962 wcss_phyb-critical {
963 temper 963 temperature = <125000>;
964 hyster 964 hysteresis = <1000>;
965 type = 965 type = "critical";
966 }; 966 };
967 }; 967 };
968 }; 968 };
969 969
970 top-glue-thermal { 970 top-glue-thermal {
971 thermal-sensors = <&ts 971 thermal-sensors = <&tsens 15>;
972 972
973 trips { 973 trips {
974 top_glue-criti 974 top_glue-critical {
975 temper 975 temperature = <125000>;
976 hyster 976 hysteresis = <1000>;
977 type = 977 type = "critical";
978 }; 978 };
979 }; 979 };
980 }; 980 };
981 }; 981 };
982 982
983 timer { 983 timer {
984 compatible = "arm,armv8-timer" 984 compatible = "arm,armv8-timer";
985 interrupts = <GIC_PPI 2 (GIC_C 985 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
986 <GIC_PPI 3 (GIC_C 986 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
987 <GIC_PPI 4 (GIC_C 987 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
988 <GIC_PPI 1 (GIC_C 988 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
989 }; 989 };
990 }; 990 };
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