1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3 1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2 /* 2 /*
3 * IPQ9574 SoC device tree source 3 * IPQ9574 SoC device tree source
4 * 4 *
5 * Copyright (c) 2020-2021 The Linux Foundatio 5 * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
6 * Copyright (c) 2023, Qualcomm Innovation Cen 6 * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
7 */ 7 */
8 8
9 #include <dt-bindings/clock/qcom,apss-ipq.h> 9 #include <dt-bindings/clock/qcom,apss-ipq.h>
10 #include <dt-bindings/clock/qcom,ipq9574-gcc.h 10 #include <dt-bindings/clock/qcom,ipq9574-gcc.h>
11 #include <dt-bindings/interconnect/qcom,ipq957 <<
12 #include <dt-bindings/interrupt-controller/arm 11 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/reset/qcom,ipq9574-gcc.h 12 #include <dt-bindings/reset/qcom,ipq9574-gcc.h>
14 #include <dt-bindings/thermal/thermal.h> <<
15 13
16 / { 14 / {
17 interrupt-parent = <&intc>; 15 interrupt-parent = <&intc>;
18 #address-cells = <2>; 16 #address-cells = <2>;
19 #size-cells = <2>; 17 #size-cells = <2>;
20 18
21 clocks { 19 clocks {
22 sleep_clk: sleep-clk { 20 sleep_clk: sleep-clk {
23 compatible = "fixed-cl 21 compatible = "fixed-clock";
24 #clock-cells = <0>; 22 #clock-cells = <0>;
25 }; 23 };
26 24
27 xo_board_clk: xo-board-clk { 25 xo_board_clk: xo-board-clk {
28 compatible = "fixed-cl 26 compatible = "fixed-clock";
29 #clock-cells = <0>; 27 #clock-cells = <0>;
30 }; 28 };
31 }; 29 };
32 30
33 cpus { 31 cpus {
34 #address-cells = <1>; 32 #address-cells = <1>;
35 #size-cells = <0>; 33 #size-cells = <0>;
36 34
37 CPU0: cpu@0 { 35 CPU0: cpu@0 {
38 device_type = "cpu"; 36 device_type = "cpu";
39 compatible = "arm,cort 37 compatible = "arm,cortex-a73";
40 reg = <0x0>; 38 reg = <0x0>;
41 enable-method = "psci" 39 enable-method = "psci";
42 next-level-cache = <&L 40 next-level-cache = <&L2_0>;
43 clocks = <&apcs_glb AP 41 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
44 clock-names = "cpu"; 42 clock-names = "cpu";
45 operating-points-v2 = 43 operating-points-v2 = <&cpu_opp_table>;
46 cpu-supply = <&ipq9574 44 cpu-supply = <&ipq9574_s1>;
47 #cooling-cells = <2>; <<
48 }; 45 };
49 46
50 CPU1: cpu@1 { 47 CPU1: cpu@1 {
51 device_type = "cpu"; 48 device_type = "cpu";
52 compatible = "arm,cort 49 compatible = "arm,cortex-a73";
53 reg = <0x1>; 50 reg = <0x1>;
54 enable-method = "psci" 51 enable-method = "psci";
55 next-level-cache = <&L 52 next-level-cache = <&L2_0>;
56 clocks = <&apcs_glb AP 53 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
57 clock-names = "cpu"; 54 clock-names = "cpu";
58 operating-points-v2 = 55 operating-points-v2 = <&cpu_opp_table>;
59 cpu-supply = <&ipq9574 56 cpu-supply = <&ipq9574_s1>;
60 #cooling-cells = <2>; <<
61 }; 57 };
62 58
63 CPU2: cpu@2 { 59 CPU2: cpu@2 {
64 device_type = "cpu"; 60 device_type = "cpu";
65 compatible = "arm,cort 61 compatible = "arm,cortex-a73";
66 reg = <0x2>; 62 reg = <0x2>;
67 enable-method = "psci" 63 enable-method = "psci";
68 next-level-cache = <&L 64 next-level-cache = <&L2_0>;
69 clocks = <&apcs_glb AP 65 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
70 clock-names = "cpu"; 66 clock-names = "cpu";
71 operating-points-v2 = 67 operating-points-v2 = <&cpu_opp_table>;
72 cpu-supply = <&ipq9574 68 cpu-supply = <&ipq9574_s1>;
73 #cooling-cells = <2>; <<
74 }; 69 };
75 70
76 CPU3: cpu@3 { 71 CPU3: cpu@3 {
77 device_type = "cpu"; 72 device_type = "cpu";
78 compatible = "arm,cort 73 compatible = "arm,cortex-a73";
79 reg = <0x3>; 74 reg = <0x3>;
80 enable-method = "psci" 75 enable-method = "psci";
81 next-level-cache = <&L 76 next-level-cache = <&L2_0>;
82 clocks = <&apcs_glb AP 77 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
83 clock-names = "cpu"; 78 clock-names = "cpu";
84 operating-points-v2 = 79 operating-points-v2 = <&cpu_opp_table>;
85 cpu-supply = <&ipq9574 80 cpu-supply = <&ipq9574_s1>;
86 #cooling-cells = <2>; <<
87 }; 81 };
88 82
89 L2_0: l2-cache { 83 L2_0: l2-cache {
90 compatible = "cache"; 84 compatible = "cache";
91 cache-level = <2>; 85 cache-level = <2>;
92 cache-unified; 86 cache-unified;
93 }; 87 };
94 }; 88 };
95 89
96 firmware { 90 firmware {
97 scm { 91 scm {
98 compatible = "qcom,scm 92 compatible = "qcom,scm-ipq9574", "qcom,scm";
99 qcom,dload-mode = <&tc 93 qcom,dload-mode = <&tcsr 0x6100>;
100 }; 94 };
101 }; 95 };
102 96
103 memory@40000000 { 97 memory@40000000 {
104 device_type = "memory"; 98 device_type = "memory";
105 /* We expect the bootloader to 99 /* We expect the bootloader to fill in the size */
106 reg = <0x0 0x40000000 0x0 0x0> 100 reg = <0x0 0x40000000 0x0 0x0>;
107 }; 101 };
108 102
109 cpu_opp_table: opp-table-cpu { 103 cpu_opp_table: opp-table-cpu {
110 compatible = "operating-points !! 104 compatible = "operating-points-v2";
111 opp-shared; 105 opp-shared;
112 nvmem-cells = <&cpu_speed_bin> <<
113 106
114 opp-936000000 { 107 opp-936000000 {
115 opp-hz = /bits/ 64 <93 108 opp-hz = /bits/ 64 <936000000>;
116 opp-microvolt = <72500 109 opp-microvolt = <725000>;
117 opp-supported-hw = <0x <<
118 clock-latency-ns = <20 110 clock-latency-ns = <200000>;
119 }; 111 };
120 112
121 opp-1104000000 { 113 opp-1104000000 {
122 opp-hz = /bits/ 64 <11 114 opp-hz = /bits/ 64 <1104000000>;
123 opp-microvolt = <78750 115 opp-microvolt = <787500>;
124 opp-supported-hw = <0x <<
125 clock-latency-ns = <20 <<
126 }; <<
127 <<
128 opp-1200000000 { <<
129 opp-hz = /bits/ 64 <12 <<
130 opp-microvolt = <86250 <<
131 opp-supported-hw = <0x <<
132 clock-latency-ns = <20 116 clock-latency-ns = <200000>;
133 }; 117 };
134 118
135 opp-1416000000 { 119 opp-1416000000 {
136 opp-hz = /bits/ 64 <14 120 opp-hz = /bits/ 64 <1416000000>;
137 opp-microvolt = <86250 121 opp-microvolt = <862500>;
138 opp-supported-hw = <0x <<
139 clock-latency-ns = <20 122 clock-latency-ns = <200000>;
140 }; 123 };
141 124
142 opp-1488000000 { 125 opp-1488000000 {
143 opp-hz = /bits/ 64 <14 126 opp-hz = /bits/ 64 <1488000000>;
144 opp-microvolt = <92500 127 opp-microvolt = <925000>;
145 opp-supported-hw = <0x <<
146 clock-latency-ns = <20 128 clock-latency-ns = <200000>;
147 }; 129 };
148 130
149 opp-1800000000 { 131 opp-1800000000 {
150 opp-hz = /bits/ 64 <18 132 opp-hz = /bits/ 64 <1800000000>;
151 opp-microvolt = <98750 133 opp-microvolt = <987500>;
152 opp-supported-hw = <0x <<
153 clock-latency-ns = <20 134 clock-latency-ns = <200000>;
154 }; 135 };
155 136
156 opp-2208000000 { 137 opp-2208000000 {
157 opp-hz = /bits/ 64 <22 138 opp-hz = /bits/ 64 <2208000000>;
158 opp-microvolt = <10625 139 opp-microvolt = <1062500>;
159 opp-supported-hw = <0x <<
160 clock-latency-ns = <20 140 clock-latency-ns = <200000>;
161 }; 141 };
162 }; 142 };
163 143
164 pmu { 144 pmu {
165 compatible = "arm,cortex-a73-p 145 compatible = "arm,cortex-a73-pmu";
166 interrupts = <GIC_PPI 7 (GIC_C 146 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
167 }; 147 };
168 148
169 psci { 149 psci {
170 compatible = "arm,psci-1.0"; 150 compatible = "arm,psci-1.0";
171 method = "smc"; 151 method = "smc";
172 }; 152 };
173 153
174 rpm: remoteproc { <<
175 compatible = "qcom,ipq9574-rpm <<
176 <<
177 glink-edge { <<
178 compatible = "qcom,gli <<
179 interrupts = <GIC_SPI <<
180 qcom,rpm-msg-ram = <&r <<
181 mboxes = <&apcs_glb 0> <<
182 <<
183 rpm_requests: rpm-requ <<
184 compatible = " <<
185 qcom,glink-cha <<
186 }; <<
187 }; <<
188 }; <<
189 <<
190 reserved-memory { 154 reserved-memory {
191 #address-cells = <2>; 155 #address-cells = <2>;
192 #size-cells = <2>; 156 #size-cells = <2>;
193 ranges; 157 ranges;
194 158
195 bootloader@4a100000 { 159 bootloader@4a100000 {
196 reg = <0x0 0x4a100000 160 reg = <0x0 0x4a100000 0x0 0x400000>;
197 no-map; 161 no-map;
198 }; 162 };
199 163
200 sbl@4a500000 { 164 sbl@4a500000 {
201 reg = <0x0 0x4a500000 165 reg = <0x0 0x4a500000 0x0 0x100000>;
202 no-map; 166 no-map;
203 }; 167 };
204 168
205 tz_region: tz@4a600000 { 169 tz_region: tz@4a600000 {
206 reg = <0x0 0x4a600000 170 reg = <0x0 0x4a600000 0x0 0x400000>;
207 no-map; 171 no-map;
208 }; 172 };
209 173
210 smem@4aa00000 { 174 smem@4aa00000 {
211 compatible = "qcom,sme 175 compatible = "qcom,smem";
212 reg = <0x0 0x4aa00000 176 reg = <0x0 0x4aa00000 0x0 0x100000>;
213 hwlocks = <&tcsr_mutex 177 hwlocks = <&tcsr_mutex 3>;
214 no-map; 178 no-map;
215 }; 179 };
216 }; 180 };
217 181
>> 182 rpm-glink {
>> 183 compatible = "qcom,glink-rpm";
>> 184 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
>> 185 qcom,rpm-msg-ram = <&rpm_msg_ram>;
>> 186 mboxes = <&apcs_glb 0>;
>> 187
>> 188 rpm_requests: rpm-requests {
>> 189 compatible = "qcom,rpm-ipq9574";
>> 190 qcom,glink-channels = "rpm_requests";
>> 191 };
>> 192 };
>> 193
218 soc: soc@0 { 194 soc: soc@0 {
219 compatible = "simple-bus"; 195 compatible = "simple-bus";
220 #address-cells = <1>; 196 #address-cells = <1>;
221 #size-cells = <1>; 197 #size-cells = <1>;
222 ranges = <0 0 0 0xffffffff>; 198 ranges = <0 0 0 0xffffffff>;
223 199
224 rpm_msg_ram: sram@60000 { 200 rpm_msg_ram: sram@60000 {
225 compatible = "qcom,rpm 201 compatible = "qcom,rpm-msg-ram";
226 reg = <0x00060000 0x60 202 reg = <0x00060000 0x6000>;
227 }; 203 };
228 204
229 rng: rng@e3000 { 205 rng: rng@e3000 {
230 compatible = "qcom,prn 206 compatible = "qcom,prng-ee";
231 reg = <0x000e3000 0x10 207 reg = <0x000e3000 0x1000>;
232 clocks = <&gcc GCC_PRN 208 clocks = <&gcc GCC_PRNG_AHB_CLK>;
233 clock-names = "core"; 209 clock-names = "core";
234 }; 210 };
235 211
236 mdio: mdio@90000 { <<
237 compatible = "qcom,ip <<
238 reg = <0x00090000 0x64 <<
239 #address-cells = <1>; <<
240 #size-cells = <0>; <<
241 clocks = <&gcc GCC_MDI <<
242 clock-names = "gcc_mdi <<
243 status = "disabled"; <<
244 }; <<
245 <<
246 qfprom: efuse@a4000 { 212 qfprom: efuse@a4000 {
247 compatible = "qcom,ipq 213 compatible = "qcom,ipq9574-qfprom", "qcom,qfprom";
248 reg = <0x000a4000 0x5a 214 reg = <0x000a4000 0x5a1>;
249 #address-cells = <1>; 215 #address-cells = <1>;
250 #size-cells = <1>; 216 #size-cells = <1>;
251 <<
252 cpu_speed_bin: cpu-spe <<
253 reg = <0x15 0x <<
254 bits = <7 2>; <<
255 }; <<
256 }; 217 };
257 218
258 cryptobam: dma-controller@7040 219 cryptobam: dma-controller@704000 {
259 compatible = "qcom,bam 220 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
260 reg = <0x00704000 0x20 221 reg = <0x00704000 0x20000>;
261 interrupts = <GIC_SPI 222 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
262 #dma-cells = <1>; 223 #dma-cells = <1>;
263 qcom,ee = <1>; 224 qcom,ee = <1>;
264 qcom,controlled-remote 225 qcom,controlled-remotely;
265 }; 226 };
266 227
267 crypto: crypto@73a000 { 228 crypto: crypto@73a000 {
268 compatible = "qcom,ipq 229 compatible = "qcom,ipq9574-qce", "qcom,ipq4019-qce", "qcom,qce";
269 reg = <0x0073a000 0x60 230 reg = <0x0073a000 0x6000>;
270 clocks = <&gcc GCC_CRY 231 clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
271 <&gcc GCC_CRY 232 <&gcc GCC_CRYPTO_AXI_CLK>,
272 <&gcc GCC_CRY 233 <&gcc GCC_CRYPTO_CLK>;
273 clock-names = "iface", 234 clock-names = "iface", "bus", "core";
274 dmas = <&cryptobam 2>, 235 dmas = <&cryptobam 2>, <&cryptobam 3>;
275 dma-names = "rx", "tx" 236 dma-names = "rx", "tx";
276 }; 237 };
277 238
278 tsens: thermal-sensor@4a9000 { 239 tsens: thermal-sensor@4a9000 {
279 compatible = "qcom,ipq 240 compatible = "qcom,ipq9574-tsens", "qcom,ipq8074-tsens";
280 reg = <0x004a9000 0x10 241 reg = <0x004a9000 0x1000>,
281 <0x004a8000 0x10 242 <0x004a8000 0x1000>;
282 interrupts = <GIC_SPI 243 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
283 interrupt-names = "com 244 interrupt-names = "combined";
284 #qcom,sensors = <16>; 245 #qcom,sensors = <16>;
285 #thermal-sensor-cells 246 #thermal-sensor-cells = <1>;
286 }; 247 };
287 248
288 tlmm: pinctrl@1000000 { 249 tlmm: pinctrl@1000000 {
289 compatible = "qcom,ipq 250 compatible = "qcom,ipq9574-tlmm";
290 reg = <0x01000000 0x30 251 reg = <0x01000000 0x300000>;
291 interrupts = <GIC_SPI 252 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
292 gpio-controller; 253 gpio-controller;
293 #gpio-cells = <2>; 254 #gpio-cells = <2>;
294 gpio-ranges = <&tlmm 0 255 gpio-ranges = <&tlmm 0 0 65>;
295 interrupt-controller; 256 interrupt-controller;
296 #interrupt-cells = <2> 257 #interrupt-cells = <2>;
297 258
298 uart2_pins: uart2-stat 259 uart2_pins: uart2-state {
299 pins = "gpio34 260 pins = "gpio34", "gpio35";
300 function = "bl 261 function = "blsp2_uart";
301 drive-strength 262 drive-strength = <8>;
302 bias-disable; 263 bias-disable;
303 }; 264 };
304 }; 265 };
305 266
306 gcc: clock-controller@1800000 267 gcc: clock-controller@1800000 {
307 compatible = "qcom,ipq 268 compatible = "qcom,ipq9574-gcc";
308 reg = <0x01800000 0x80 269 reg = <0x01800000 0x80000>;
309 clocks = <&xo_board_cl 270 clocks = <&xo_board_clk>,
310 <&sleep_clk>, 271 <&sleep_clk>,
311 <0>, 272 <0>,
312 <0>, 273 <0>,
313 <0>, 274 <0>,
314 <0>, 275 <0>,
315 <0>, 276 <0>,
316 <0>; 277 <0>;
317 #clock-cells = <1>; 278 #clock-cells = <1>;
318 #reset-cells = <1>; 279 #reset-cells = <1>;
319 #interconnect-cells = !! 280 #power-domain-cells = <1>;
320 }; 281 };
321 282
322 tcsr_mutex: hwlock@1905000 { 283 tcsr_mutex: hwlock@1905000 {
323 compatible = "qcom,tcs 284 compatible = "qcom,tcsr-mutex";
324 reg = <0x01905000 0x20 285 reg = <0x01905000 0x20000>;
325 #hwlock-cells = <1>; 286 #hwlock-cells = <1>;
326 }; 287 };
327 288
328 tcsr: syscon@1937000 { 289 tcsr: syscon@1937000 {
329 compatible = "qcom,tcs 290 compatible = "qcom,tcsr-ipq9574", "syscon";
330 reg = <0x01937000 0x21 291 reg = <0x01937000 0x21000>;
331 }; 292 };
332 293
333 sdhc_1: mmc@7804000 { 294 sdhc_1: mmc@7804000 {
334 compatible = "qcom,ipq 295 compatible = "qcom,ipq9574-sdhci", "qcom,sdhci-msm-v5";
335 reg = <0x07804000 0x10 !! 296 reg = <0x07804000 0x1000>, <0x07805000 0x1000>;
336 <0x07805000 0x10 !! 297 reg-names = "hc", "cqhci";
337 <0x07808000 0x20 <<
338 reg-names = "hc", "cqh <<
339 298
340 interrupts = <GIC_SPI 299 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
341 <GIC_SPI 300 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
342 interrupt-names = "hc_ 301 interrupt-names = "hc_irq", "pwr_irq";
343 302
344 clocks = <&gcc GCC_SDC 303 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
345 <&gcc GCC_SDC 304 <&gcc GCC_SDCC1_APPS_CLK>,
346 <&xo_board_cl !! 305 <&xo_board_clk>;
347 <&gcc GCC_SDC !! 306 clock-names = "iface", "core", "xo";
348 clock-names = "iface", <<
349 non-removable; 307 non-removable;
350 supports-cqe; <<
351 status = "disabled"; 308 status = "disabled";
352 }; 309 };
353 310
354 blsp_dma: dma-controller@78840 311 blsp_dma: dma-controller@7884000 {
355 compatible = "qcom,bam 312 compatible = "qcom,bam-v1.7.0";
356 reg = <0x07884000 0x2b 313 reg = <0x07884000 0x2b000>;
357 interrupts = <GIC_SPI 314 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
358 clocks = <&gcc GCC_BLS 315 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
359 clock-names = "bam_clk 316 clock-names = "bam_clk";
360 #dma-cells = <1>; 317 #dma-cells = <1>;
361 qcom,ee = <0>; 318 qcom,ee = <0>;
362 }; 319 };
363 320
364 blsp1_uart0: serial@78af000 { 321 blsp1_uart0: serial@78af000 {
365 compatible = "qcom,msm 322 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
366 reg = <0x078af000 0x20 323 reg = <0x078af000 0x200>;
367 interrupts = <GIC_SPI 324 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
368 clocks = <&gcc GCC_BLS 325 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
369 <&gcc GCC_BLS 326 <&gcc GCC_BLSP1_AHB_CLK>;
370 clock-names = "core", 327 clock-names = "core", "iface";
371 status = "disabled"; 328 status = "disabled";
372 }; 329 };
373 330
374 blsp1_uart1: serial@78b0000 { 331 blsp1_uart1: serial@78b0000 {
375 compatible = "qcom,msm 332 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
376 reg = <0x078b0000 0x20 333 reg = <0x078b0000 0x200>;
377 interrupts = <GIC_SPI 334 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
378 clocks = <&gcc GCC_BLS 335 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
379 <&gcc GCC_BLS 336 <&gcc GCC_BLSP1_AHB_CLK>;
380 clock-names = "core", 337 clock-names = "core", "iface";
381 status = "disabled"; 338 status = "disabled";
382 }; 339 };
383 340
384 blsp1_uart2: serial@78b1000 { 341 blsp1_uart2: serial@78b1000 {
385 compatible = "qcom,msm 342 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
386 reg = <0x078b1000 0x20 343 reg = <0x078b1000 0x200>;
387 interrupts = <GIC_SPI 344 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
388 clocks = <&gcc GCC_BLS 345 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
389 <&gcc GCC_BLS 346 <&gcc GCC_BLSP1_AHB_CLK>;
390 clock-names = "core", 347 clock-names = "core", "iface";
391 status = "disabled"; 348 status = "disabled";
392 }; 349 };
393 350
394 blsp1_uart3: serial@78b2000 { 351 blsp1_uart3: serial@78b2000 {
395 compatible = "qcom,msm 352 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
396 reg = <0x078b2000 0x20 353 reg = <0x078b2000 0x200>;
397 interrupts = <GIC_SPI 354 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
398 clocks = <&gcc GCC_BLS 355 clocks = <&gcc GCC_BLSP1_UART4_APPS_CLK>,
399 <&gcc GCC_BLS 356 <&gcc GCC_BLSP1_AHB_CLK>;
400 clock-names = "core", 357 clock-names = "core", "iface";
401 status = "disabled"; 358 status = "disabled";
402 }; 359 };
403 360
404 blsp1_uart4: serial@78b3000 { 361 blsp1_uart4: serial@78b3000 {
405 compatible = "qcom,msm 362 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
406 reg = <0x078b3000 0x20 363 reg = <0x078b3000 0x200>;
407 interrupts = <GIC_SPI 364 interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
408 clocks = <&gcc GCC_BLS 365 clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>,
409 <&gcc GCC_BLS 366 <&gcc GCC_BLSP1_AHB_CLK>;
410 clock-names = "core", 367 clock-names = "core", "iface";
411 status = "disabled"; 368 status = "disabled";
412 }; 369 };
413 370
414 blsp1_uart5: serial@78b4000 { 371 blsp1_uart5: serial@78b4000 {
415 compatible = "qcom,msm 372 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
416 reg = <0x078b4000 0x20 373 reg = <0x078b4000 0x200>;
417 interrupts = <GIC_SPI 374 interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>;
418 clocks = <&gcc GCC_BLS 375 clocks = <&gcc GCC_BLSP1_UART6_APPS_CLK>,
419 <&gcc GCC_BLS 376 <&gcc GCC_BLSP1_AHB_CLK>;
420 clock-names = "core", 377 clock-names = "core", "iface";
421 status = "disabled"; 378 status = "disabled";
422 }; 379 };
423 380
424 blsp1_spi0: spi@78b5000 { 381 blsp1_spi0: spi@78b5000 {
425 compatible = "qcom,spi 382 compatible = "qcom,spi-qup-v2.2.1";
426 reg = <0x078b5000 0x60 383 reg = <0x078b5000 0x600>;
427 #address-cells = <1>; 384 #address-cells = <1>;
428 #size-cells = <0>; 385 #size-cells = <0>;
429 interrupts = <GIC_SPI 386 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
430 clocks = <&gcc GCC_BLS 387 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
431 <&gcc GCC_BLS 388 <&gcc GCC_BLSP1_AHB_CLK>;
432 clock-names = "core", 389 clock-names = "core", "iface";
433 dmas = <&blsp_dma 12>, 390 dmas = <&blsp_dma 12>, <&blsp_dma 13>;
434 dma-names = "tx", "rx" 391 dma-names = "tx", "rx";
435 status = "disabled"; 392 status = "disabled";
436 }; 393 };
437 394
438 blsp1_i2c1: i2c@78b6000 { 395 blsp1_i2c1: i2c@78b6000 {
439 compatible = "qcom,i2c 396 compatible = "qcom,i2c-qup-v2.2.1";
440 reg = <0x078b6000 0x60 397 reg = <0x078b6000 0x600>;
441 #address-cells = <1>; 398 #address-cells = <1>;
442 #size-cells = <0>; 399 #size-cells = <0>;
443 interrupts = <GIC_SPI 400 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
444 clocks = <&gcc GCC_BLS 401 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
445 <&gcc GCC_BLS 402 <&gcc GCC_BLSP1_AHB_CLK>;
446 clock-names = "core", 403 clock-names = "core", "iface";
447 assigned-clocks = <&gc <<
448 assigned-clock-rates = <<
449 dmas = <&blsp_dma 14>, 404 dmas = <&blsp_dma 14>, <&blsp_dma 15>;
450 dma-names = "tx", "rx" 405 dma-names = "tx", "rx";
451 status = "disabled"; 406 status = "disabled";
452 }; 407 };
453 408
454 blsp1_spi1: spi@78b6000 { 409 blsp1_spi1: spi@78b6000 {
455 compatible = "qcom,spi 410 compatible = "qcom,spi-qup-v2.2.1";
456 reg = <0x078b6000 0x60 411 reg = <0x078b6000 0x600>;
457 #address-cells = <1>; 412 #address-cells = <1>;
458 #size-cells = <0>; 413 #size-cells = <0>;
459 interrupts = <GIC_SPI 414 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
460 clocks = <&gcc GCC_BLS 415 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
461 <&gcc GCC_BLS 416 <&gcc GCC_BLSP1_AHB_CLK>;
462 clock-names = "core", 417 clock-names = "core", "iface";
463 dmas = <&blsp_dma 14>, 418 dmas = <&blsp_dma 14>, <&blsp_dma 15>;
464 dma-names = "tx", "rx" 419 dma-names = "tx", "rx";
465 status = "disabled"; 420 status = "disabled";
466 }; 421 };
467 422
468 blsp1_i2c2: i2c@78b7000 { 423 blsp1_i2c2: i2c@78b7000 {
469 compatible = "qcom,i2c 424 compatible = "qcom,i2c-qup-v2.2.1";
470 reg = <0x078b7000 0x60 425 reg = <0x078b7000 0x600>;
471 #address-cells = <1>; 426 #address-cells = <1>;
472 #size-cells = <0>; 427 #size-cells = <0>;
473 interrupts = <GIC_SPI 428 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
474 clocks = <&gcc GCC_BLS 429 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
475 <&gcc GCC_BLS 430 <&gcc GCC_BLSP1_AHB_CLK>;
476 clock-names = "core", 431 clock-names = "core", "iface";
477 assigned-clocks = <&gc <<
478 assigned-clock-rates = <<
479 dmas = <&blsp_dma 16>, 432 dmas = <&blsp_dma 16>, <&blsp_dma 17>;
480 dma-names = "tx", "rx" 433 dma-names = "tx", "rx";
481 status = "disabled"; 434 status = "disabled";
482 }; 435 };
483 436
484 blsp1_spi2: spi@78b7000 { 437 blsp1_spi2: spi@78b7000 {
485 compatible = "qcom,spi 438 compatible = "qcom,spi-qup-v2.2.1";
486 reg = <0x078b7000 0x60 439 reg = <0x078b7000 0x600>;
487 #address-cells = <1>; 440 #address-cells = <1>;
488 #size-cells = <0>; 441 #size-cells = <0>;
489 interrupts = <GIC_SPI 442 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
490 clocks = <&gcc GCC_BLS 443 clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
491 <&gcc GCC_BLS 444 <&gcc GCC_BLSP1_AHB_CLK>;
492 clock-names = "core", 445 clock-names = "core", "iface";
493 dmas = <&blsp_dma 16>, 446 dmas = <&blsp_dma 16>, <&blsp_dma 17>;
494 dma-names = "tx", "rx" 447 dma-names = "tx", "rx";
495 status = "disabled"; 448 status = "disabled";
496 }; 449 };
497 450
498 blsp1_i2c3: i2c@78b8000 { 451 blsp1_i2c3: i2c@78b8000 {
499 compatible = "qcom,i2c 452 compatible = "qcom,i2c-qup-v2.2.1";
500 reg = <0x078b8000 0x60 453 reg = <0x078b8000 0x600>;
501 #address-cells = <1>; 454 #address-cells = <1>;
502 #size-cells = <0>; 455 #size-cells = <0>;
503 interrupts = <GIC_SPI 456 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
504 clocks = <&gcc GCC_BLS 457 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
505 <&gcc GCC_BLS 458 <&gcc GCC_BLSP1_AHB_CLK>;
506 clock-names = "core", 459 clock-names = "core", "iface";
507 assigned-clocks = <&gc <<
508 assigned-clock-rates = <<
509 dmas = <&blsp_dma 18>, 460 dmas = <&blsp_dma 18>, <&blsp_dma 19>;
510 dma-names = "tx", "rx" 461 dma-names = "tx", "rx";
511 status = "disabled"; 462 status = "disabled";
512 }; 463 };
513 464
514 blsp1_spi3: spi@78b8000 { 465 blsp1_spi3: spi@78b8000 {
515 compatible = "qcom,spi 466 compatible = "qcom,spi-qup-v2.2.1";
516 reg = <0x078b8000 0x60 467 reg = <0x078b8000 0x600>;
517 #address-cells = <1>; 468 #address-cells = <1>;
518 #size-cells = <0>; 469 #size-cells = <0>;
519 interrupts = <GIC_SPI 470 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
520 spi-max-frequency = <5 471 spi-max-frequency = <50000000>;
521 clocks = <&gcc GCC_BLS 472 clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
522 <&gcc GCC_BLS 473 <&gcc GCC_BLSP1_AHB_CLK>;
523 clock-names = "core", 474 clock-names = "core", "iface";
524 dmas = <&blsp_dma 18>, 475 dmas = <&blsp_dma 18>, <&blsp_dma 19>;
525 dma-names = "tx", "rx" 476 dma-names = "tx", "rx";
526 status = "disabled"; 477 status = "disabled";
527 }; 478 };
528 479
529 blsp1_i2c4: i2c@78b9000 { 480 blsp1_i2c4: i2c@78b9000 {
530 compatible = "qcom,i2c 481 compatible = "qcom,i2c-qup-v2.2.1";
531 reg = <0x078b9000 0x60 482 reg = <0x078b9000 0x600>;
532 #address-cells = <1>; 483 #address-cells = <1>;
533 #size-cells = <0>; 484 #size-cells = <0>;
534 interrupts = <GIC_SPI 485 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
535 clocks = <&gcc GCC_BLS 486 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
536 <&gcc GCC_BLS 487 <&gcc GCC_BLSP1_AHB_CLK>;
537 clock-names = "core", 488 clock-names = "core", "iface";
538 assigned-clocks = <&gc <<
539 assigned-clock-rates = <<
540 dmas = <&blsp_dma 20>, 489 dmas = <&blsp_dma 20>, <&blsp_dma 21>;
541 dma-names = "tx", "rx" 490 dma-names = "tx", "rx";
542 status = "disabled"; 491 status = "disabled";
543 }; 492 };
544 493
545 blsp1_spi4: spi@78b9000 { 494 blsp1_spi4: spi@78b9000 {
546 compatible = "qcom,spi 495 compatible = "qcom,spi-qup-v2.2.1";
547 reg = <0x078b9000 0x60 496 reg = <0x078b9000 0x600>;
548 #address-cells = <1>; 497 #address-cells = <1>;
549 #size-cells = <0>; 498 #size-cells = <0>;
550 interrupts = <GIC_SPI 499 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
551 clocks = <&gcc GCC_BLS 500 clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
552 <&gcc GCC_BLS 501 <&gcc GCC_BLSP1_AHB_CLK>;
553 clock-names = "core", 502 clock-names = "core", "iface";
554 dmas = <&blsp_dma 20>, 503 dmas = <&blsp_dma 20>, <&blsp_dma 21>;
555 dma-names = "tx", "rx" 504 dma-names = "tx", "rx";
556 status = "disabled"; 505 status = "disabled";
557 }; 506 };
558 507
559 usb_0_qusbphy: phy@7b000 { <<
560 compatible = "qcom,ipq <<
561 reg = <0x0007b000 0x18 <<
562 #phy-cells = <0>; <<
563 <<
564 clocks = <&gcc GCC_USB <<
565 <&xo_board_cl <<
566 clock-names = "cfg_ahb <<
567 "ref"; <<
568 <<
569 resets = <&gcc GCC_QUS <<
570 status = "disabled"; <<
571 }; <<
572 <<
573 usb_0_qmpphy: phy@7d000 { <<
574 compatible = "qcom,ipq <<
575 reg = <0x0007d000 0xa0 <<
576 #phy-cells = <0>; <<
577 <<
578 clocks = <&gcc GCC_USB <<
579 <&xo_board_cl <<
580 <&gcc GCC_USB <<
581 <&gcc GCC_USB <<
582 clock-names = "aux", <<
583 "ref", <<
584 "cfg_ahb <<
585 "pipe"; <<
586 <<
587 resets = <&gcc GCC_USB <<
588 <&gcc GCC_USB <<
589 reset-names = "phy", <<
590 "phy_phy <<
591 <<
592 #clock-cells = <0>; <<
593 clock-output-names = " <<
594 <<
595 status = "disabled"; <<
596 }; <<
597 <<
598 usb3: usb@8af8800 { <<
599 compatible = "qcom,ipq <<
600 reg = <0x08af8800 0x40 <<
601 #address-cells = <1>; <<
602 #size-cells = <1>; <<
603 ranges; <<
604 <<
605 clocks = <&gcc GCC_SNO <<
606 <&gcc GCC_USB <<
607 <&gcc GCC_ANO <<
608 <&gcc GCC_USB <<
609 <&gcc GCC_USB <<
610 <<
611 clock-names = "cfg_noc <<
612 "core", <<
613 "iface", <<
614 "sleep", <<
615 "mock_ut <<
616 <<
617 assigned-clocks = <&gc <<
618 <&gc <<
619 assigned-clock-rates = <<
620 <<
621 <<
622 interrupts-extended = <<
623 interrupt-names = "pwr <<
624 <<
625 resets = <&gcc GCC_USB <<
626 status = "disabled"; <<
627 <<
628 usb_0_dwc3: usb@8a0000 <<
629 compatible = " <<
630 reg = <0x8a000 <<
631 clocks = <&gcc <<
632 clock-names = <<
633 interrupts = < <<
634 phys = <&usb_0 <<
635 phy-names = "u <<
636 tx-fifo-resize <<
637 snps,is-utmi-l <<
638 snps,hird-thre <<
639 snps,dis_u2_su <<
640 snps,dis_u3_su <<
641 }; <<
642 }; <<
643 <<
644 intc: interrupt-controller@b00 508 intc: interrupt-controller@b000000 {
645 compatible = "qcom,msm 509 compatible = "qcom,msm-qgic2";
646 reg = <0x0b000000 0x10 510 reg = <0x0b000000 0x1000>, /* GICD */
647 <0x0b002000 0x20 511 <0x0b002000 0x2000>, /* GICC */
648 <0x0b001000 0x10 512 <0x0b001000 0x1000>, /* GICH */
649 <0x0b004000 0x20 513 <0x0b004000 0x2000>; /* GICV */
650 #address-cells = <1>; 514 #address-cells = <1>;
651 #size-cells = <1>; 515 #size-cells = <1>;
652 interrupt-controller; 516 interrupt-controller;
653 #interrupt-cells = <3> 517 #interrupt-cells = <3>;
654 interrupts = <GIC_PPI 518 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
655 ranges = <0 0x0b00c000 519 ranges = <0 0x0b00c000 0x3000>;
656 520
657 v2m0: v2m@0 { 521 v2m0: v2m@0 {
658 compatible = " 522 compatible = "arm,gic-v2m-frame";
659 reg = <0x00000 523 reg = <0x00000000 0xffd>;
660 msi-controller 524 msi-controller;
661 }; 525 };
662 526
663 v2m1: v2m@1000 { 527 v2m1: v2m@1000 {
664 compatible = " 528 compatible = "arm,gic-v2m-frame";
665 reg = <0x00001 529 reg = <0x00001000 0xffd>;
666 msi-controller 530 msi-controller;
667 }; 531 };
668 532
669 v2m2: v2m@2000 { 533 v2m2: v2m@2000 {
670 compatible = " 534 compatible = "arm,gic-v2m-frame";
671 reg = <0x00002 535 reg = <0x00002000 0xffd>;
672 msi-controller 536 msi-controller;
673 }; 537 };
674 }; 538 };
675 539
676 watchdog: watchdog@b017000 { 540 watchdog: watchdog@b017000 {
677 compatible = "qcom,aps 541 compatible = "qcom,apss-wdt-ipq9574", "qcom,kpss-wdt";
678 reg = <0x0b017000 0x10 542 reg = <0x0b017000 0x1000>;
679 interrupts = <GIC_SPI 543 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
680 clocks = <&sleep_clk>; 544 clocks = <&sleep_clk>;
681 timeout-sec = <30>; 545 timeout-sec = <30>;
682 }; 546 };
683 547
684 apcs_glb: mailbox@b111000 { 548 apcs_glb: mailbox@b111000 {
685 compatible = "qcom,ipq 549 compatible = "qcom,ipq9574-apcs-apps-global",
686 "qcom,ipq 550 "qcom,ipq6018-apcs-apps-global";
687 reg = <0x0b111000 0x10 551 reg = <0x0b111000 0x1000>;
688 #clock-cells = <1>; 552 #clock-cells = <1>;
689 clocks = <&a73pll>, <& !! 553 clocks = <&a73pll>, <&xo_board_clk>;
690 clock-names = "pll", " !! 554 clock-names = "pll", "xo";
691 #mbox-cells = <1>; 555 #mbox-cells = <1>;
692 }; 556 };
693 557
694 a73pll: clock@b116000 { 558 a73pll: clock@b116000 {
695 compatible = "qcom,ipq 559 compatible = "qcom,ipq9574-a73pll";
696 reg = <0x0b116000 0x40 560 reg = <0x0b116000 0x40>;
697 #clock-cells = <0>; 561 #clock-cells = <0>;
698 clocks = <&xo_board_cl 562 clocks = <&xo_board_clk>;
699 clock-names = "xo"; 563 clock-names = "xo";
700 }; 564 };
701 565
702 timer@b120000 { 566 timer@b120000 {
703 compatible = "arm,armv 567 compatible = "arm,armv7-timer-mem";
704 reg = <0x0b120000 0x10 568 reg = <0x0b120000 0x1000>;
705 #address-cells = <1>; 569 #address-cells = <1>;
706 #size-cells = <1>; 570 #size-cells = <1>;
707 ranges; 571 ranges;
708 572
709 frame@b120000 { 573 frame@b120000 {
710 reg = <0x0b121 574 reg = <0x0b121000 0x1000>,
711 <0x0b122 575 <0x0b122000 0x1000>;
712 frame-number = 576 frame-number = <0>;
713 interrupts = < 577 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
714 < 578 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
715 }; 579 };
716 580
717 frame@b123000 { 581 frame@b123000 {
718 reg = <0x0b123 582 reg = <0x0b123000 0x1000>;
719 frame-number = 583 frame-number = <1>;
720 interrupts = < 584 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
721 status = "disa 585 status = "disabled";
722 }; 586 };
723 587
724 frame@b124000 { 588 frame@b124000 {
725 reg = <0x0b124 589 reg = <0x0b124000 0x1000>;
726 frame-number = 590 frame-number = <2>;
727 interrupts = < 591 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
728 status = "disa 592 status = "disabled";
729 }; 593 };
730 594
731 frame@b125000 { 595 frame@b125000 {
732 reg = <0x0b125 596 reg = <0x0b125000 0x1000>;
733 frame-number = 597 frame-number = <3>;
734 interrupts = < 598 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
735 status = "disa 599 status = "disabled";
736 }; 600 };
737 601
738 frame@b126000 { 602 frame@b126000 {
739 reg = <0x0b126 603 reg = <0x0b126000 0x1000>;
740 frame-number = 604 frame-number = <4>;
741 interrupts = < 605 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
742 status = "disa 606 status = "disabled";
743 }; 607 };
744 608
745 frame@b127000 { 609 frame@b127000 {
746 reg = <0x0b127 610 reg = <0x0b127000 0x1000>;
747 frame-number = 611 frame-number = <5>;
748 interrupts = < 612 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
749 status = "disa 613 status = "disabled";
750 }; 614 };
751 615
752 frame@b128000 { 616 frame@b128000 {
753 reg = <0x0b128 617 reg = <0x0b128000 0x1000>;
754 frame-number = 618 frame-number = <6>;
755 interrupts = < 619 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
756 status = "disa 620 status = "disabled";
757 }; 621 };
758 }; 622 };
759 }; 623 };
760 624
761 thermal-zones { 625 thermal-zones {
762 nss-top-thermal { 626 nss-top-thermal {
>> 627 polling-delay-passive = <0>;
>> 628 polling-delay = <0>;
763 thermal-sensors = <&ts 629 thermal-sensors = <&tsens 3>;
764 630
765 trips { 631 trips {
766 nss-top-critic 632 nss-top-critical {
767 temper 633 temperature = <125000>;
768 hyster 634 hysteresis = <1000>;
769 type = 635 type = "critical";
770 }; 636 };
771 }; 637 };
772 }; 638 };
773 639
774 ubi-0-thermal { 640 ubi-0-thermal {
>> 641 polling-delay-passive = <0>;
>> 642 polling-delay = <0>;
775 thermal-sensors = <&ts 643 thermal-sensors = <&tsens 4>;
776 644
777 trips { 645 trips {
778 ubi_0-critical 646 ubi_0-critical {
779 temper 647 temperature = <125000>;
780 hyster 648 hysteresis = <1000>;
781 type = 649 type = "critical";
782 }; 650 };
783 }; 651 };
784 }; 652 };
785 653
786 ubi-1-thermal { 654 ubi-1-thermal {
>> 655 polling-delay-passive = <0>;
>> 656 polling-delay = <0>;
787 thermal-sensors = <&ts 657 thermal-sensors = <&tsens 5>;
788 658
789 trips { 659 trips {
790 ubi_1-critical 660 ubi_1-critical {
791 temper 661 temperature = <125000>;
792 hyster 662 hysteresis = <1000>;
793 type = 663 type = "critical";
794 }; 664 };
795 }; 665 };
796 }; 666 };
797 667
798 ubi-2-thermal { 668 ubi-2-thermal {
>> 669 polling-delay-passive = <0>;
>> 670 polling-delay = <0>;
799 thermal-sensors = <&ts 671 thermal-sensors = <&tsens 6>;
800 672
801 trips { 673 trips {
802 ubi_2-critical 674 ubi_2-critical {
803 temper 675 temperature = <125000>;
804 hyster 676 hysteresis = <1000>;
805 type = 677 type = "critical";
806 }; 678 };
807 }; 679 };
808 }; 680 };
809 681
810 ubi-3-thermal { 682 ubi-3-thermal {
>> 683 polling-delay-passive = <0>;
>> 684 polling-delay = <0>;
811 thermal-sensors = <&ts 685 thermal-sensors = <&tsens 7>;
812 686
813 trips { 687 trips {
814 ubi_3-critical 688 ubi_3-critical {
815 temper 689 temperature = <125000>;
816 hyster 690 hysteresis = <1000>;
817 type = 691 type = "critical";
818 }; 692 };
819 }; 693 };
820 }; 694 };
821 695
822 cpuss0-thermal { 696 cpuss0-thermal {
>> 697 polling-delay-passive = <0>;
>> 698 polling-delay = <0>;
823 thermal-sensors = <&ts 699 thermal-sensors = <&tsens 8>;
824 700
825 trips { 701 trips {
826 cpu-critical { 702 cpu-critical {
827 temper 703 temperature = <125000>;
828 hyster 704 hysteresis = <1000>;
829 type = 705 type = "critical";
830 }; 706 };
831 }; 707 };
832 }; 708 };
833 709
834 cpuss1-thermal { 710 cpuss1-thermal {
>> 711 polling-delay-passive = <0>;
>> 712 polling-delay = <0>;
835 thermal-sensors = <&ts 713 thermal-sensors = <&tsens 9>;
836 714
837 trips { 715 trips {
838 cpu-critical { 716 cpu-critical {
839 temper 717 temperature = <125000>;
840 hyster 718 hysteresis = <1000>;
841 type = 719 type = "critical";
842 }; 720 };
843 }; 721 };
844 }; 722 };
845 723
846 cpu0-thermal { 724 cpu0-thermal {
>> 725 polling-delay-passive = <0>;
>> 726 polling-delay = <0>;
847 thermal-sensors = <&ts 727 thermal-sensors = <&tsens 10>;
848 728
849 trips { 729 trips {
850 cpu0_crit: cpu !! 730 cpu-critical {
851 temper 731 temperature = <120000>;
852 hyster 732 hysteresis = <10000>;
853 type = 733 type = "critical";
854 }; 734 };
855 735
856 cpu0_alert: cp !! 736 cpu-passive {
857 temper 737 temperature = <110000>;
858 hyster 738 hysteresis = <1000>;
859 type = 739 type = "passive";
860 }; 740 };
861 }; 741 };
862 <<
863 cooling-maps { <<
864 map0 { <<
865 trip = <<
866 coolin <<
867 <<
868 <<
869 <<
870 }; <<
871 }; <<
872 }; 742 };
873 743
874 cpu1-thermal { 744 cpu1-thermal {
>> 745 polling-delay-passive = <0>;
>> 746 polling-delay = <0>;
875 thermal-sensors = <&ts 747 thermal-sensors = <&tsens 11>;
876 748
877 trips { 749 trips {
878 cpu1_crit: cpu !! 750 cpu-critical {
879 temper 751 temperature = <120000>;
880 hyster 752 hysteresis = <10000>;
881 type = 753 type = "critical";
882 }; 754 };
883 755
884 cpu1_alert: cp !! 756 cpu-passive {
885 temper 757 temperature = <110000>;
886 hyster 758 hysteresis = <1000>;
887 type = 759 type = "passive";
888 }; 760 };
889 }; 761 };
890 <<
891 cooling-maps { <<
892 map0 { <<
893 trip = <<
894 coolin <<
895 <<
896 <<
897 <<
898 }; <<
899 }; <<
900 }; 762 };
901 763
902 cpu2-thermal { 764 cpu2-thermal {
>> 765 polling-delay-passive = <0>;
>> 766 polling-delay = <0>;
903 thermal-sensors = <&ts 767 thermal-sensors = <&tsens 12>;
904 768
905 trips { 769 trips {
906 cpu2_crit: cpu !! 770 cpu-critical {
907 temper 771 temperature = <120000>;
908 hyster 772 hysteresis = <10000>;
909 type = 773 type = "critical";
910 }; 774 };
911 775
912 cpu2_alert: cp !! 776 cpu-passive {
913 temper 777 temperature = <110000>;
914 hyster 778 hysteresis = <1000>;
915 type = 779 type = "passive";
916 }; 780 };
917 }; 781 };
918 <<
919 cooling-maps { <<
920 map0 { <<
921 trip = <<
922 coolin <<
923 <<
924 <<
925 <<
926 }; <<
927 }; <<
928 }; 782 };
929 783
930 cpu3-thermal { 784 cpu3-thermal {
>> 785 polling-delay-passive = <0>;
>> 786 polling-delay = <0>;
931 thermal-sensors = <&ts 787 thermal-sensors = <&tsens 13>;
932 788
933 trips { 789 trips {
934 cpu3_crit: cpu !! 790 cpu-critical {
935 temper 791 temperature = <120000>;
936 hyster 792 hysteresis = <10000>;
937 type = 793 type = "critical";
938 }; 794 };
939 795
940 cpu3_alert: cp !! 796 cpu-passive {
941 temper 797 temperature = <110000>;
942 hyster 798 hysteresis = <1000>;
943 type = 799 type = "passive";
944 }; 800 };
945 }; 801 };
946 <<
947 cooling-maps { <<
948 map0 { <<
949 trip = <<
950 coolin <<
951 <<
952 <<
953 <<
954 }; <<
955 }; <<
956 }; 802 };
957 803
958 wcss-phyb-thermal { 804 wcss-phyb-thermal {
>> 805 polling-delay-passive = <0>;
>> 806 polling-delay = <0>;
959 thermal-sensors = <&ts 807 thermal-sensors = <&tsens 14>;
960 808
961 trips { 809 trips {
962 wcss_phyb-crit 810 wcss_phyb-critical {
963 temper 811 temperature = <125000>;
964 hyster 812 hysteresis = <1000>;
965 type = 813 type = "critical";
966 }; 814 };
967 }; 815 };
968 }; 816 };
969 817
970 top-glue-thermal { 818 top-glue-thermal {
>> 819 polling-delay-passive = <0>;
>> 820 polling-delay = <0>;
971 thermal-sensors = <&ts 821 thermal-sensors = <&tsens 15>;
972 822
973 trips { 823 trips {
974 top_glue-criti 824 top_glue-critical {
975 temper 825 temperature = <125000>;
976 hyster 826 hysteresis = <1000>;
977 type = 827 type = "critical";
978 }; 828 };
979 }; 829 };
980 }; 830 };
981 }; 831 };
982 832
983 timer { 833 timer {
984 compatible = "arm,armv8-timer" 834 compatible = "arm,armv8-timer";
985 interrupts = <GIC_PPI 2 (GIC_C 835 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
986 <GIC_PPI 3 (GIC_C 836 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
987 <GIC_PPI 4 (GIC_C 837 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
988 <GIC_PPI 1 (GIC_C 838 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
989 }; 839 };
990 }; 840 };
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