1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3 1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2 /* 2 /*
3 * IPQ9574 SoC device tree source 3 * IPQ9574 SoC device tree source
4 * 4 *
5 * Copyright (c) 2020-2021 The Linux Foundatio 5 * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
6 * Copyright (c) 2023, Qualcomm Innovation Cen 6 * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
7 */ 7 */
8 8
9 #include <dt-bindings/clock/qcom,apss-ipq.h> 9 #include <dt-bindings/clock/qcom,apss-ipq.h>
10 #include <dt-bindings/clock/qcom,ipq9574-gcc.h 10 #include <dt-bindings/clock/qcom,ipq9574-gcc.h>
11 #include <dt-bindings/interconnect/qcom,ipq957 <<
12 #include <dt-bindings/interrupt-controller/arm 11 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/reset/qcom,ipq9574-gcc.h 12 #include <dt-bindings/reset/qcom,ipq9574-gcc.h>
14 #include <dt-bindings/thermal/thermal.h> 13 #include <dt-bindings/thermal/thermal.h>
15 14
16 / { 15 / {
17 interrupt-parent = <&intc>; 16 interrupt-parent = <&intc>;
18 #address-cells = <2>; 17 #address-cells = <2>;
19 #size-cells = <2>; 18 #size-cells = <2>;
20 19
21 clocks { 20 clocks {
22 sleep_clk: sleep-clk { 21 sleep_clk: sleep-clk {
23 compatible = "fixed-cl 22 compatible = "fixed-clock";
24 #clock-cells = <0>; 23 #clock-cells = <0>;
25 }; 24 };
26 25
27 xo_board_clk: xo-board-clk { 26 xo_board_clk: xo-board-clk {
28 compatible = "fixed-cl 27 compatible = "fixed-clock";
29 #clock-cells = <0>; 28 #clock-cells = <0>;
30 }; 29 };
31 }; 30 };
32 31
33 cpus { 32 cpus {
34 #address-cells = <1>; 33 #address-cells = <1>;
35 #size-cells = <0>; 34 #size-cells = <0>;
36 35
37 CPU0: cpu@0 { 36 CPU0: cpu@0 {
38 device_type = "cpu"; 37 device_type = "cpu";
39 compatible = "arm,cort 38 compatible = "arm,cortex-a73";
40 reg = <0x0>; 39 reg = <0x0>;
41 enable-method = "psci" 40 enable-method = "psci";
42 next-level-cache = <&L 41 next-level-cache = <&L2_0>;
43 clocks = <&apcs_glb AP 42 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
44 clock-names = "cpu"; 43 clock-names = "cpu";
45 operating-points-v2 = 44 operating-points-v2 = <&cpu_opp_table>;
46 cpu-supply = <&ipq9574 45 cpu-supply = <&ipq9574_s1>;
47 #cooling-cells = <2>; 46 #cooling-cells = <2>;
48 }; 47 };
49 48
50 CPU1: cpu@1 { 49 CPU1: cpu@1 {
51 device_type = "cpu"; 50 device_type = "cpu";
52 compatible = "arm,cort 51 compatible = "arm,cortex-a73";
53 reg = <0x1>; 52 reg = <0x1>;
54 enable-method = "psci" 53 enable-method = "psci";
55 next-level-cache = <&L 54 next-level-cache = <&L2_0>;
56 clocks = <&apcs_glb AP 55 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
57 clock-names = "cpu"; 56 clock-names = "cpu";
58 operating-points-v2 = 57 operating-points-v2 = <&cpu_opp_table>;
59 cpu-supply = <&ipq9574 58 cpu-supply = <&ipq9574_s1>;
60 #cooling-cells = <2>; 59 #cooling-cells = <2>;
61 }; 60 };
62 61
63 CPU2: cpu@2 { 62 CPU2: cpu@2 {
64 device_type = "cpu"; 63 device_type = "cpu";
65 compatible = "arm,cort 64 compatible = "arm,cortex-a73";
66 reg = <0x2>; 65 reg = <0x2>;
67 enable-method = "psci" 66 enable-method = "psci";
68 next-level-cache = <&L 67 next-level-cache = <&L2_0>;
69 clocks = <&apcs_glb AP 68 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
70 clock-names = "cpu"; 69 clock-names = "cpu";
71 operating-points-v2 = 70 operating-points-v2 = <&cpu_opp_table>;
72 cpu-supply = <&ipq9574 71 cpu-supply = <&ipq9574_s1>;
73 #cooling-cells = <2>; 72 #cooling-cells = <2>;
74 }; 73 };
75 74
76 CPU3: cpu@3 { 75 CPU3: cpu@3 {
77 device_type = "cpu"; 76 device_type = "cpu";
78 compatible = "arm,cort 77 compatible = "arm,cortex-a73";
79 reg = <0x3>; 78 reg = <0x3>;
80 enable-method = "psci" 79 enable-method = "psci";
81 next-level-cache = <&L 80 next-level-cache = <&L2_0>;
82 clocks = <&apcs_glb AP 81 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
83 clock-names = "cpu"; 82 clock-names = "cpu";
84 operating-points-v2 = 83 operating-points-v2 = <&cpu_opp_table>;
85 cpu-supply = <&ipq9574 84 cpu-supply = <&ipq9574_s1>;
86 #cooling-cells = <2>; 85 #cooling-cells = <2>;
87 }; 86 };
88 87
89 L2_0: l2-cache { 88 L2_0: l2-cache {
90 compatible = "cache"; 89 compatible = "cache";
91 cache-level = <2>; 90 cache-level = <2>;
92 cache-unified; 91 cache-unified;
93 }; 92 };
94 }; 93 };
95 94
96 firmware { 95 firmware {
97 scm { 96 scm {
98 compatible = "qcom,scm 97 compatible = "qcom,scm-ipq9574", "qcom,scm";
99 qcom,dload-mode = <&tc 98 qcom,dload-mode = <&tcsr 0x6100>;
100 }; 99 };
101 }; 100 };
102 101
103 memory@40000000 { 102 memory@40000000 {
104 device_type = "memory"; 103 device_type = "memory";
105 /* We expect the bootloader to 104 /* We expect the bootloader to fill in the size */
106 reg = <0x0 0x40000000 0x0 0x0> 105 reg = <0x0 0x40000000 0x0 0x0>;
107 }; 106 };
108 107
109 cpu_opp_table: opp-table-cpu { 108 cpu_opp_table: opp-table-cpu {
110 compatible = "operating-points !! 109 compatible = "operating-points-v2";
111 opp-shared; 110 opp-shared;
112 nvmem-cells = <&cpu_speed_bin> <<
113 111
114 opp-936000000 { 112 opp-936000000 {
115 opp-hz = /bits/ 64 <93 113 opp-hz = /bits/ 64 <936000000>;
116 opp-microvolt = <72500 114 opp-microvolt = <725000>;
117 opp-supported-hw = <0x <<
118 clock-latency-ns = <20 115 clock-latency-ns = <200000>;
119 }; 116 };
120 117
121 opp-1104000000 { 118 opp-1104000000 {
122 opp-hz = /bits/ 64 <11 119 opp-hz = /bits/ 64 <1104000000>;
123 opp-microvolt = <78750 120 opp-microvolt = <787500>;
124 opp-supported-hw = <0x <<
125 clock-latency-ns = <20 <<
126 }; <<
127 <<
128 opp-1200000000 { <<
129 opp-hz = /bits/ 64 <12 <<
130 opp-microvolt = <86250 <<
131 opp-supported-hw = <0x <<
132 clock-latency-ns = <20 121 clock-latency-ns = <200000>;
133 }; 122 };
134 123
135 opp-1416000000 { 124 opp-1416000000 {
136 opp-hz = /bits/ 64 <14 125 opp-hz = /bits/ 64 <1416000000>;
137 opp-microvolt = <86250 126 opp-microvolt = <862500>;
138 opp-supported-hw = <0x <<
139 clock-latency-ns = <20 127 clock-latency-ns = <200000>;
140 }; 128 };
141 129
142 opp-1488000000 { 130 opp-1488000000 {
143 opp-hz = /bits/ 64 <14 131 opp-hz = /bits/ 64 <1488000000>;
144 opp-microvolt = <92500 132 opp-microvolt = <925000>;
145 opp-supported-hw = <0x <<
146 clock-latency-ns = <20 133 clock-latency-ns = <200000>;
147 }; 134 };
148 135
149 opp-1800000000 { 136 opp-1800000000 {
150 opp-hz = /bits/ 64 <18 137 opp-hz = /bits/ 64 <1800000000>;
151 opp-microvolt = <98750 138 opp-microvolt = <987500>;
152 opp-supported-hw = <0x <<
153 clock-latency-ns = <20 139 clock-latency-ns = <200000>;
154 }; 140 };
155 141
156 opp-2208000000 { 142 opp-2208000000 {
157 opp-hz = /bits/ 64 <22 143 opp-hz = /bits/ 64 <2208000000>;
158 opp-microvolt = <10625 144 opp-microvolt = <1062500>;
159 opp-supported-hw = <0x <<
160 clock-latency-ns = <20 145 clock-latency-ns = <200000>;
161 }; 146 };
162 }; 147 };
163 148
164 pmu { 149 pmu {
165 compatible = "arm,cortex-a73-p 150 compatible = "arm,cortex-a73-pmu";
166 interrupts = <GIC_PPI 7 (GIC_C 151 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
167 }; 152 };
168 153
169 psci { 154 psci {
170 compatible = "arm,psci-1.0"; 155 compatible = "arm,psci-1.0";
171 method = "smc"; 156 method = "smc";
172 }; 157 };
173 158
174 rpm: remoteproc { 159 rpm: remoteproc {
175 compatible = "qcom,ipq9574-rpm 160 compatible = "qcom,ipq9574-rpm-proc", "qcom,rpm-proc";
176 161
177 glink-edge { 162 glink-edge {
178 compatible = "qcom,gli 163 compatible = "qcom,glink-rpm";
179 interrupts = <GIC_SPI 164 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
180 qcom,rpm-msg-ram = <&r 165 qcom,rpm-msg-ram = <&rpm_msg_ram>;
181 mboxes = <&apcs_glb 0> 166 mboxes = <&apcs_glb 0>;
182 167
183 rpm_requests: rpm-requ 168 rpm_requests: rpm-requests {
184 compatible = " !! 169 compatible = "qcom,rpm-ipq9574";
185 qcom,glink-cha 170 qcom,glink-channels = "rpm_requests";
186 }; 171 };
187 }; 172 };
188 }; 173 };
189 174
190 reserved-memory { 175 reserved-memory {
191 #address-cells = <2>; 176 #address-cells = <2>;
192 #size-cells = <2>; 177 #size-cells = <2>;
193 ranges; 178 ranges;
194 179
195 bootloader@4a100000 { 180 bootloader@4a100000 {
196 reg = <0x0 0x4a100000 181 reg = <0x0 0x4a100000 0x0 0x400000>;
197 no-map; 182 no-map;
198 }; 183 };
199 184
200 sbl@4a500000 { 185 sbl@4a500000 {
201 reg = <0x0 0x4a500000 186 reg = <0x0 0x4a500000 0x0 0x100000>;
202 no-map; 187 no-map;
203 }; 188 };
204 189
205 tz_region: tz@4a600000 { 190 tz_region: tz@4a600000 {
206 reg = <0x0 0x4a600000 191 reg = <0x0 0x4a600000 0x0 0x400000>;
207 no-map; 192 no-map;
208 }; 193 };
209 194
210 smem@4aa00000 { 195 smem@4aa00000 {
211 compatible = "qcom,sme 196 compatible = "qcom,smem";
212 reg = <0x0 0x4aa00000 197 reg = <0x0 0x4aa00000 0x0 0x100000>;
213 hwlocks = <&tcsr_mutex 198 hwlocks = <&tcsr_mutex 3>;
214 no-map; 199 no-map;
215 }; 200 };
216 }; 201 };
217 202
218 soc: soc@0 { 203 soc: soc@0 {
219 compatible = "simple-bus"; 204 compatible = "simple-bus";
220 #address-cells = <1>; 205 #address-cells = <1>;
221 #size-cells = <1>; 206 #size-cells = <1>;
222 ranges = <0 0 0 0xffffffff>; 207 ranges = <0 0 0 0xffffffff>;
223 208
224 rpm_msg_ram: sram@60000 { 209 rpm_msg_ram: sram@60000 {
225 compatible = "qcom,rpm 210 compatible = "qcom,rpm-msg-ram";
226 reg = <0x00060000 0x60 211 reg = <0x00060000 0x6000>;
227 }; 212 };
228 213
229 rng: rng@e3000 { 214 rng: rng@e3000 {
230 compatible = "qcom,prn 215 compatible = "qcom,prng-ee";
231 reg = <0x000e3000 0x10 216 reg = <0x000e3000 0x1000>;
232 clocks = <&gcc GCC_PRN 217 clocks = <&gcc GCC_PRNG_AHB_CLK>;
233 clock-names = "core"; 218 clock-names = "core";
234 }; 219 };
235 220
236 mdio: mdio@90000 { <<
237 compatible = "qcom,ip <<
238 reg = <0x00090000 0x64 <<
239 #address-cells = <1>; <<
240 #size-cells = <0>; <<
241 clocks = <&gcc GCC_MDI <<
242 clock-names = "gcc_mdi <<
243 status = "disabled"; <<
244 }; <<
245 <<
246 qfprom: efuse@a4000 { 221 qfprom: efuse@a4000 {
247 compatible = "qcom,ipq 222 compatible = "qcom,ipq9574-qfprom", "qcom,qfprom";
248 reg = <0x000a4000 0x5a 223 reg = <0x000a4000 0x5a1>;
249 #address-cells = <1>; 224 #address-cells = <1>;
250 #size-cells = <1>; 225 #size-cells = <1>;
251 <<
252 cpu_speed_bin: cpu-spe <<
253 reg = <0x15 0x <<
254 bits = <7 2>; <<
255 }; <<
256 }; 226 };
257 227
258 cryptobam: dma-controller@7040 228 cryptobam: dma-controller@704000 {
259 compatible = "qcom,bam 229 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
260 reg = <0x00704000 0x20 230 reg = <0x00704000 0x20000>;
261 interrupts = <GIC_SPI 231 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
262 #dma-cells = <1>; 232 #dma-cells = <1>;
263 qcom,ee = <1>; 233 qcom,ee = <1>;
264 qcom,controlled-remote 234 qcom,controlled-remotely;
265 }; 235 };
266 236
267 crypto: crypto@73a000 { 237 crypto: crypto@73a000 {
268 compatible = "qcom,ipq 238 compatible = "qcom,ipq9574-qce", "qcom,ipq4019-qce", "qcom,qce";
269 reg = <0x0073a000 0x60 239 reg = <0x0073a000 0x6000>;
270 clocks = <&gcc GCC_CRY 240 clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
271 <&gcc GCC_CRY 241 <&gcc GCC_CRYPTO_AXI_CLK>,
272 <&gcc GCC_CRY 242 <&gcc GCC_CRYPTO_CLK>;
273 clock-names = "iface", 243 clock-names = "iface", "bus", "core";
274 dmas = <&cryptobam 2>, 244 dmas = <&cryptobam 2>, <&cryptobam 3>;
275 dma-names = "rx", "tx" 245 dma-names = "rx", "tx";
276 }; 246 };
277 247
278 tsens: thermal-sensor@4a9000 { 248 tsens: thermal-sensor@4a9000 {
279 compatible = "qcom,ipq 249 compatible = "qcom,ipq9574-tsens", "qcom,ipq8074-tsens";
280 reg = <0x004a9000 0x10 250 reg = <0x004a9000 0x1000>,
281 <0x004a8000 0x10 251 <0x004a8000 0x1000>;
282 interrupts = <GIC_SPI 252 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
283 interrupt-names = "com 253 interrupt-names = "combined";
284 #qcom,sensors = <16>; 254 #qcom,sensors = <16>;
285 #thermal-sensor-cells 255 #thermal-sensor-cells = <1>;
286 }; 256 };
287 257
288 tlmm: pinctrl@1000000 { 258 tlmm: pinctrl@1000000 {
289 compatible = "qcom,ipq 259 compatible = "qcom,ipq9574-tlmm";
290 reg = <0x01000000 0x30 260 reg = <0x01000000 0x300000>;
291 interrupts = <GIC_SPI 261 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
292 gpio-controller; 262 gpio-controller;
293 #gpio-cells = <2>; 263 #gpio-cells = <2>;
294 gpio-ranges = <&tlmm 0 264 gpio-ranges = <&tlmm 0 0 65>;
295 interrupt-controller; 265 interrupt-controller;
296 #interrupt-cells = <2> 266 #interrupt-cells = <2>;
297 267
298 uart2_pins: uart2-stat 268 uart2_pins: uart2-state {
299 pins = "gpio34 269 pins = "gpio34", "gpio35";
300 function = "bl 270 function = "blsp2_uart";
301 drive-strength 271 drive-strength = <8>;
302 bias-disable; 272 bias-disable;
303 }; 273 };
304 }; 274 };
305 275
306 gcc: clock-controller@1800000 276 gcc: clock-controller@1800000 {
307 compatible = "qcom,ipq 277 compatible = "qcom,ipq9574-gcc";
308 reg = <0x01800000 0x80 278 reg = <0x01800000 0x80000>;
309 clocks = <&xo_board_cl 279 clocks = <&xo_board_clk>,
310 <&sleep_clk>, 280 <&sleep_clk>,
311 <0>, 281 <0>,
312 <0>, 282 <0>,
313 <0>, 283 <0>,
314 <0>, 284 <0>,
315 <0>, 285 <0>,
316 <0>; 286 <0>;
317 #clock-cells = <1>; 287 #clock-cells = <1>;
318 #reset-cells = <1>; 288 #reset-cells = <1>;
319 #interconnect-cells = !! 289 #power-domain-cells = <1>;
320 }; 290 };
321 291
322 tcsr_mutex: hwlock@1905000 { 292 tcsr_mutex: hwlock@1905000 {
323 compatible = "qcom,tcs 293 compatible = "qcom,tcsr-mutex";
324 reg = <0x01905000 0x20 294 reg = <0x01905000 0x20000>;
325 #hwlock-cells = <1>; 295 #hwlock-cells = <1>;
326 }; 296 };
327 297
328 tcsr: syscon@1937000 { 298 tcsr: syscon@1937000 {
329 compatible = "qcom,tcs 299 compatible = "qcom,tcsr-ipq9574", "syscon";
330 reg = <0x01937000 0x21 300 reg = <0x01937000 0x21000>;
331 }; 301 };
332 302
333 sdhc_1: mmc@7804000 { 303 sdhc_1: mmc@7804000 {
334 compatible = "qcom,ipq 304 compatible = "qcom,ipq9574-sdhci", "qcom,sdhci-msm-v5";
335 reg = <0x07804000 0x10 !! 305 reg = <0x07804000 0x1000>, <0x07805000 0x1000>;
336 <0x07805000 0x10 !! 306 reg-names = "hc", "cqhci";
337 <0x07808000 0x20 <<
338 reg-names = "hc", "cqh <<
339 307
340 interrupts = <GIC_SPI 308 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
341 <GIC_SPI 309 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
342 interrupt-names = "hc_ 310 interrupt-names = "hc_irq", "pwr_irq";
343 311
344 clocks = <&gcc GCC_SDC 312 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
345 <&gcc GCC_SDC 313 <&gcc GCC_SDCC1_APPS_CLK>,
346 <&xo_board_cl !! 314 <&xo_board_clk>;
347 <&gcc GCC_SDC !! 315 clock-names = "iface", "core", "xo";
348 clock-names = "iface", <<
349 non-removable; 316 non-removable;
350 supports-cqe; <<
351 status = "disabled"; 317 status = "disabled";
352 }; 318 };
353 319
354 blsp_dma: dma-controller@78840 320 blsp_dma: dma-controller@7884000 {
355 compatible = "qcom,bam 321 compatible = "qcom,bam-v1.7.0";
356 reg = <0x07884000 0x2b 322 reg = <0x07884000 0x2b000>;
357 interrupts = <GIC_SPI 323 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
358 clocks = <&gcc GCC_BLS 324 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
359 clock-names = "bam_clk 325 clock-names = "bam_clk";
360 #dma-cells = <1>; 326 #dma-cells = <1>;
361 qcom,ee = <0>; 327 qcom,ee = <0>;
362 }; 328 };
363 329
364 blsp1_uart0: serial@78af000 { 330 blsp1_uart0: serial@78af000 {
365 compatible = "qcom,msm 331 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
366 reg = <0x078af000 0x20 332 reg = <0x078af000 0x200>;
367 interrupts = <GIC_SPI 333 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
368 clocks = <&gcc GCC_BLS 334 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
369 <&gcc GCC_BLS 335 <&gcc GCC_BLSP1_AHB_CLK>;
370 clock-names = "core", 336 clock-names = "core", "iface";
371 status = "disabled"; 337 status = "disabled";
372 }; 338 };
373 339
374 blsp1_uart1: serial@78b0000 { 340 blsp1_uart1: serial@78b0000 {
375 compatible = "qcom,msm 341 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
376 reg = <0x078b0000 0x20 342 reg = <0x078b0000 0x200>;
377 interrupts = <GIC_SPI 343 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
378 clocks = <&gcc GCC_BLS 344 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
379 <&gcc GCC_BLS 345 <&gcc GCC_BLSP1_AHB_CLK>;
380 clock-names = "core", 346 clock-names = "core", "iface";
381 status = "disabled"; 347 status = "disabled";
382 }; 348 };
383 349
384 blsp1_uart2: serial@78b1000 { 350 blsp1_uart2: serial@78b1000 {
385 compatible = "qcom,msm 351 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
386 reg = <0x078b1000 0x20 352 reg = <0x078b1000 0x200>;
387 interrupts = <GIC_SPI 353 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
388 clocks = <&gcc GCC_BLS 354 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
389 <&gcc GCC_BLS 355 <&gcc GCC_BLSP1_AHB_CLK>;
390 clock-names = "core", 356 clock-names = "core", "iface";
391 status = "disabled"; 357 status = "disabled";
392 }; 358 };
393 359
394 blsp1_uart3: serial@78b2000 { 360 blsp1_uart3: serial@78b2000 {
395 compatible = "qcom,msm 361 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
396 reg = <0x078b2000 0x20 362 reg = <0x078b2000 0x200>;
397 interrupts = <GIC_SPI 363 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
398 clocks = <&gcc GCC_BLS 364 clocks = <&gcc GCC_BLSP1_UART4_APPS_CLK>,
399 <&gcc GCC_BLS 365 <&gcc GCC_BLSP1_AHB_CLK>;
400 clock-names = "core", 366 clock-names = "core", "iface";
401 status = "disabled"; 367 status = "disabled";
402 }; 368 };
403 369
404 blsp1_uart4: serial@78b3000 { 370 blsp1_uart4: serial@78b3000 {
405 compatible = "qcom,msm 371 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
406 reg = <0x078b3000 0x20 372 reg = <0x078b3000 0x200>;
407 interrupts = <GIC_SPI 373 interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
408 clocks = <&gcc GCC_BLS 374 clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>,
409 <&gcc GCC_BLS 375 <&gcc GCC_BLSP1_AHB_CLK>;
410 clock-names = "core", 376 clock-names = "core", "iface";
411 status = "disabled"; 377 status = "disabled";
412 }; 378 };
413 379
414 blsp1_uart5: serial@78b4000 { 380 blsp1_uart5: serial@78b4000 {
415 compatible = "qcom,msm 381 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
416 reg = <0x078b4000 0x20 382 reg = <0x078b4000 0x200>;
417 interrupts = <GIC_SPI 383 interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>;
418 clocks = <&gcc GCC_BLS 384 clocks = <&gcc GCC_BLSP1_UART6_APPS_CLK>,
419 <&gcc GCC_BLS 385 <&gcc GCC_BLSP1_AHB_CLK>;
420 clock-names = "core", 386 clock-names = "core", "iface";
421 status = "disabled"; 387 status = "disabled";
422 }; 388 };
423 389
424 blsp1_spi0: spi@78b5000 { 390 blsp1_spi0: spi@78b5000 {
425 compatible = "qcom,spi 391 compatible = "qcom,spi-qup-v2.2.1";
426 reg = <0x078b5000 0x60 392 reg = <0x078b5000 0x600>;
427 #address-cells = <1>; 393 #address-cells = <1>;
428 #size-cells = <0>; 394 #size-cells = <0>;
429 interrupts = <GIC_SPI 395 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
430 clocks = <&gcc GCC_BLS 396 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
431 <&gcc GCC_BLS 397 <&gcc GCC_BLSP1_AHB_CLK>;
432 clock-names = "core", 398 clock-names = "core", "iface";
433 dmas = <&blsp_dma 12>, 399 dmas = <&blsp_dma 12>, <&blsp_dma 13>;
434 dma-names = "tx", "rx" 400 dma-names = "tx", "rx";
435 status = "disabled"; 401 status = "disabled";
436 }; 402 };
437 403
438 blsp1_i2c1: i2c@78b6000 { 404 blsp1_i2c1: i2c@78b6000 {
439 compatible = "qcom,i2c 405 compatible = "qcom,i2c-qup-v2.2.1";
440 reg = <0x078b6000 0x60 406 reg = <0x078b6000 0x600>;
441 #address-cells = <1>; 407 #address-cells = <1>;
442 #size-cells = <0>; 408 #size-cells = <0>;
443 interrupts = <GIC_SPI 409 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
444 clocks = <&gcc GCC_BLS 410 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
445 <&gcc GCC_BLS 411 <&gcc GCC_BLSP1_AHB_CLK>;
446 clock-names = "core", 412 clock-names = "core", "iface";
447 assigned-clocks = <&gc 413 assigned-clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
448 assigned-clock-rates = 414 assigned-clock-rates = <50000000>;
449 dmas = <&blsp_dma 14>, 415 dmas = <&blsp_dma 14>, <&blsp_dma 15>;
450 dma-names = "tx", "rx" 416 dma-names = "tx", "rx";
451 status = "disabled"; 417 status = "disabled";
452 }; 418 };
453 419
454 blsp1_spi1: spi@78b6000 { 420 blsp1_spi1: spi@78b6000 {
455 compatible = "qcom,spi 421 compatible = "qcom,spi-qup-v2.2.1";
456 reg = <0x078b6000 0x60 422 reg = <0x078b6000 0x600>;
457 #address-cells = <1>; 423 #address-cells = <1>;
458 #size-cells = <0>; 424 #size-cells = <0>;
459 interrupts = <GIC_SPI 425 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
460 clocks = <&gcc GCC_BLS 426 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
461 <&gcc GCC_BLS 427 <&gcc GCC_BLSP1_AHB_CLK>;
462 clock-names = "core", 428 clock-names = "core", "iface";
463 dmas = <&blsp_dma 14>, 429 dmas = <&blsp_dma 14>, <&blsp_dma 15>;
464 dma-names = "tx", "rx" 430 dma-names = "tx", "rx";
465 status = "disabled"; 431 status = "disabled";
466 }; 432 };
467 433
468 blsp1_i2c2: i2c@78b7000 { 434 blsp1_i2c2: i2c@78b7000 {
469 compatible = "qcom,i2c 435 compatible = "qcom,i2c-qup-v2.2.1";
470 reg = <0x078b7000 0x60 436 reg = <0x078b7000 0x600>;
471 #address-cells = <1>; 437 #address-cells = <1>;
472 #size-cells = <0>; 438 #size-cells = <0>;
473 interrupts = <GIC_SPI 439 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
474 clocks = <&gcc GCC_BLS 440 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
475 <&gcc GCC_BLS 441 <&gcc GCC_BLSP1_AHB_CLK>;
476 clock-names = "core", 442 clock-names = "core", "iface";
477 assigned-clocks = <&gc 443 assigned-clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
478 assigned-clock-rates = 444 assigned-clock-rates = <50000000>;
479 dmas = <&blsp_dma 16>, 445 dmas = <&blsp_dma 16>, <&blsp_dma 17>;
480 dma-names = "tx", "rx" 446 dma-names = "tx", "rx";
481 status = "disabled"; 447 status = "disabled";
482 }; 448 };
483 449
484 blsp1_spi2: spi@78b7000 { 450 blsp1_spi2: spi@78b7000 {
485 compatible = "qcom,spi 451 compatible = "qcom,spi-qup-v2.2.1";
486 reg = <0x078b7000 0x60 452 reg = <0x078b7000 0x600>;
487 #address-cells = <1>; 453 #address-cells = <1>;
488 #size-cells = <0>; 454 #size-cells = <0>;
489 interrupts = <GIC_SPI 455 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
490 clocks = <&gcc GCC_BLS 456 clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
491 <&gcc GCC_BLS 457 <&gcc GCC_BLSP1_AHB_CLK>;
492 clock-names = "core", 458 clock-names = "core", "iface";
493 dmas = <&blsp_dma 16>, 459 dmas = <&blsp_dma 16>, <&blsp_dma 17>;
494 dma-names = "tx", "rx" 460 dma-names = "tx", "rx";
495 status = "disabled"; 461 status = "disabled";
496 }; 462 };
497 463
498 blsp1_i2c3: i2c@78b8000 { 464 blsp1_i2c3: i2c@78b8000 {
499 compatible = "qcom,i2c 465 compatible = "qcom,i2c-qup-v2.2.1";
500 reg = <0x078b8000 0x60 466 reg = <0x078b8000 0x600>;
501 #address-cells = <1>; 467 #address-cells = <1>;
502 #size-cells = <0>; 468 #size-cells = <0>;
503 interrupts = <GIC_SPI 469 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
504 clocks = <&gcc GCC_BLS 470 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
505 <&gcc GCC_BLS 471 <&gcc GCC_BLSP1_AHB_CLK>;
506 clock-names = "core", 472 clock-names = "core", "iface";
507 assigned-clocks = <&gc 473 assigned-clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
508 assigned-clock-rates = 474 assigned-clock-rates = <50000000>;
509 dmas = <&blsp_dma 18>, 475 dmas = <&blsp_dma 18>, <&blsp_dma 19>;
510 dma-names = "tx", "rx" 476 dma-names = "tx", "rx";
511 status = "disabled"; 477 status = "disabled";
512 }; 478 };
513 479
514 blsp1_spi3: spi@78b8000 { 480 blsp1_spi3: spi@78b8000 {
515 compatible = "qcom,spi 481 compatible = "qcom,spi-qup-v2.2.1";
516 reg = <0x078b8000 0x60 482 reg = <0x078b8000 0x600>;
517 #address-cells = <1>; 483 #address-cells = <1>;
518 #size-cells = <0>; 484 #size-cells = <0>;
519 interrupts = <GIC_SPI 485 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
520 spi-max-frequency = <5 486 spi-max-frequency = <50000000>;
521 clocks = <&gcc GCC_BLS 487 clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
522 <&gcc GCC_BLS 488 <&gcc GCC_BLSP1_AHB_CLK>;
523 clock-names = "core", 489 clock-names = "core", "iface";
524 dmas = <&blsp_dma 18>, 490 dmas = <&blsp_dma 18>, <&blsp_dma 19>;
525 dma-names = "tx", "rx" 491 dma-names = "tx", "rx";
526 status = "disabled"; 492 status = "disabled";
527 }; 493 };
528 494
529 blsp1_i2c4: i2c@78b9000 { 495 blsp1_i2c4: i2c@78b9000 {
530 compatible = "qcom,i2c 496 compatible = "qcom,i2c-qup-v2.2.1";
531 reg = <0x078b9000 0x60 497 reg = <0x078b9000 0x600>;
532 #address-cells = <1>; 498 #address-cells = <1>;
533 #size-cells = <0>; 499 #size-cells = <0>;
534 interrupts = <GIC_SPI 500 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
535 clocks = <&gcc GCC_BLS 501 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
536 <&gcc GCC_BLS 502 <&gcc GCC_BLSP1_AHB_CLK>;
537 clock-names = "core", 503 clock-names = "core", "iface";
538 assigned-clocks = <&gc 504 assigned-clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>;
539 assigned-clock-rates = 505 assigned-clock-rates = <50000000>;
540 dmas = <&blsp_dma 20>, 506 dmas = <&blsp_dma 20>, <&blsp_dma 21>;
541 dma-names = "tx", "rx" 507 dma-names = "tx", "rx";
542 status = "disabled"; 508 status = "disabled";
543 }; 509 };
544 510
545 blsp1_spi4: spi@78b9000 { 511 blsp1_spi4: spi@78b9000 {
546 compatible = "qcom,spi 512 compatible = "qcom,spi-qup-v2.2.1";
547 reg = <0x078b9000 0x60 513 reg = <0x078b9000 0x600>;
548 #address-cells = <1>; 514 #address-cells = <1>;
549 #size-cells = <0>; 515 #size-cells = <0>;
550 interrupts = <GIC_SPI 516 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
551 clocks = <&gcc GCC_BLS 517 clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
552 <&gcc GCC_BLS 518 <&gcc GCC_BLSP1_AHB_CLK>;
553 clock-names = "core", 519 clock-names = "core", "iface";
554 dmas = <&blsp_dma 20>, 520 dmas = <&blsp_dma 20>, <&blsp_dma 21>;
555 dma-names = "tx", "rx" 521 dma-names = "tx", "rx";
556 status = "disabled"; 522 status = "disabled";
557 }; 523 };
558 524
559 usb_0_qusbphy: phy@7b000 { 525 usb_0_qusbphy: phy@7b000 {
560 compatible = "qcom,ipq 526 compatible = "qcom,ipq9574-qusb2-phy";
561 reg = <0x0007b000 0x18 527 reg = <0x0007b000 0x180>;
562 #phy-cells = <0>; 528 #phy-cells = <0>;
563 529
564 clocks = <&gcc GCC_USB 530 clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
565 <&xo_board_cl 531 <&xo_board_clk>;
566 clock-names = "cfg_ahb 532 clock-names = "cfg_ahb",
567 "ref"; 533 "ref";
568 534
569 resets = <&gcc GCC_QUS 535 resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
570 status = "disabled"; 536 status = "disabled";
571 }; 537 };
572 538
573 usb_0_qmpphy: phy@7d000 { 539 usb_0_qmpphy: phy@7d000 {
574 compatible = "qcom,ipq 540 compatible = "qcom,ipq9574-qmp-usb3-phy";
575 reg = <0x0007d000 0xa0 541 reg = <0x0007d000 0xa00>;
576 #phy-cells = <0>; 542 #phy-cells = <0>;
577 543
578 clocks = <&gcc GCC_USB 544 clocks = <&gcc GCC_USB0_AUX_CLK>,
579 <&xo_board_cl 545 <&xo_board_clk>,
580 <&gcc GCC_USB 546 <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
581 <&gcc GCC_USB 547 <&gcc GCC_USB0_PIPE_CLK>;
582 clock-names = "aux", 548 clock-names = "aux",
583 "ref", 549 "ref",
584 "cfg_ahb 550 "cfg_ahb",
585 "pipe"; 551 "pipe";
586 552
587 resets = <&gcc GCC_USB 553 resets = <&gcc GCC_USB0_PHY_BCR>,
588 <&gcc GCC_USB 554 <&gcc GCC_USB3PHY_0_PHY_BCR>;
589 reset-names = "phy", 555 reset-names = "phy",
590 "phy_phy 556 "phy_phy";
591 557
592 #clock-cells = <0>; 558 #clock-cells = <0>;
593 clock-output-names = " 559 clock-output-names = "usb0_pipe_clk";
594 560
595 status = "disabled"; 561 status = "disabled";
596 }; 562 };
597 563
598 usb3: usb@8af8800 { 564 usb3: usb@8af8800 {
599 compatible = "qcom,ipq 565 compatible = "qcom,ipq9574-dwc3", "qcom,dwc3";
600 reg = <0x08af8800 0x40 566 reg = <0x08af8800 0x400>;
601 #address-cells = <1>; 567 #address-cells = <1>;
602 #size-cells = <1>; 568 #size-cells = <1>;
603 ranges; 569 ranges;
604 570
605 clocks = <&gcc GCC_SNO 571 clocks = <&gcc GCC_SNOC_USB_CLK>,
606 <&gcc GCC_USB 572 <&gcc GCC_USB0_MASTER_CLK>,
607 <&gcc GCC_ANO 573 <&gcc GCC_ANOC_USB_AXI_CLK>,
608 <&gcc GCC_USB 574 <&gcc GCC_USB0_SLEEP_CLK>,
609 <&gcc GCC_USB 575 <&gcc GCC_USB0_MOCK_UTMI_CLK>;
610 576
611 clock-names = "cfg_noc 577 clock-names = "cfg_noc",
612 "core", 578 "core",
613 "iface", 579 "iface",
614 "sleep", 580 "sleep",
615 "mock_ut 581 "mock_utmi";
616 582
617 assigned-clocks = <&gc 583 assigned-clocks = <&gcc GCC_USB0_MASTER_CLK>,
618 <&gc 584 <&gcc GCC_USB0_MOCK_UTMI_CLK>;
619 assigned-clock-rates = 585 assigned-clock-rates = <200000000>,
620 586 <24000000>;
621 587
622 interrupts-extended = 588 interrupts-extended = <&intc GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
623 interrupt-names = "pwr 589 interrupt-names = "pwr_event";
624 590
625 resets = <&gcc GCC_USB 591 resets = <&gcc GCC_USB_BCR>;
626 status = "disabled"; 592 status = "disabled";
627 593
628 usb_0_dwc3: usb@8a0000 594 usb_0_dwc3: usb@8a00000 {
629 compatible = " 595 compatible = "snps,dwc3";
630 reg = <0x8a000 596 reg = <0x8a00000 0xcd00>;
631 clocks = <&gcc 597 clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>;
632 clock-names = 598 clock-names = "ref";
633 interrupts = < 599 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
634 phys = <&usb_0 600 phys = <&usb_0_qusbphy>, <&usb_0_qmpphy>;
635 phy-names = "u 601 phy-names = "usb2-phy", "usb3-phy";
636 tx-fifo-resize 602 tx-fifo-resize;
637 snps,is-utmi-l 603 snps,is-utmi-l1-suspend;
638 snps,hird-thre 604 snps,hird-threshold = /bits/ 8 <0x0>;
639 snps,dis_u2_su 605 snps,dis_u2_susphy_quirk;
640 snps,dis_u3_su 606 snps,dis_u3_susphy_quirk;
641 }; 607 };
642 }; 608 };
643 609
644 intc: interrupt-controller@b00 610 intc: interrupt-controller@b000000 {
645 compatible = "qcom,msm 611 compatible = "qcom,msm-qgic2";
646 reg = <0x0b000000 0x10 612 reg = <0x0b000000 0x1000>, /* GICD */
647 <0x0b002000 0x20 613 <0x0b002000 0x2000>, /* GICC */
648 <0x0b001000 0x10 614 <0x0b001000 0x1000>, /* GICH */
649 <0x0b004000 0x20 615 <0x0b004000 0x2000>; /* GICV */
650 #address-cells = <1>; 616 #address-cells = <1>;
651 #size-cells = <1>; 617 #size-cells = <1>;
652 interrupt-controller; 618 interrupt-controller;
653 #interrupt-cells = <3> 619 #interrupt-cells = <3>;
654 interrupts = <GIC_PPI 620 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
655 ranges = <0 0x0b00c000 621 ranges = <0 0x0b00c000 0x3000>;
656 622
657 v2m0: v2m@0 { 623 v2m0: v2m@0 {
658 compatible = " 624 compatible = "arm,gic-v2m-frame";
659 reg = <0x00000 625 reg = <0x00000000 0xffd>;
660 msi-controller 626 msi-controller;
661 }; 627 };
662 628
663 v2m1: v2m@1000 { 629 v2m1: v2m@1000 {
664 compatible = " 630 compatible = "arm,gic-v2m-frame";
665 reg = <0x00001 631 reg = <0x00001000 0xffd>;
666 msi-controller 632 msi-controller;
667 }; 633 };
668 634
669 v2m2: v2m@2000 { 635 v2m2: v2m@2000 {
670 compatible = " 636 compatible = "arm,gic-v2m-frame";
671 reg = <0x00002 637 reg = <0x00002000 0xffd>;
672 msi-controller 638 msi-controller;
673 }; 639 };
674 }; 640 };
675 641
676 watchdog: watchdog@b017000 { 642 watchdog: watchdog@b017000 {
677 compatible = "qcom,aps 643 compatible = "qcom,apss-wdt-ipq9574", "qcom,kpss-wdt";
678 reg = <0x0b017000 0x10 644 reg = <0x0b017000 0x1000>;
679 interrupts = <GIC_SPI 645 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
680 clocks = <&sleep_clk>; 646 clocks = <&sleep_clk>;
681 timeout-sec = <30>; 647 timeout-sec = <30>;
682 }; 648 };
683 649
684 apcs_glb: mailbox@b111000 { 650 apcs_glb: mailbox@b111000 {
685 compatible = "qcom,ipq 651 compatible = "qcom,ipq9574-apcs-apps-global",
686 "qcom,ipq 652 "qcom,ipq6018-apcs-apps-global";
687 reg = <0x0b111000 0x10 653 reg = <0x0b111000 0x1000>;
688 #clock-cells = <1>; 654 #clock-cells = <1>;
689 clocks = <&a73pll>, <& !! 655 clocks = <&a73pll>, <&xo_board_clk>;
690 clock-names = "pll", " !! 656 clock-names = "pll", "xo";
691 #mbox-cells = <1>; 657 #mbox-cells = <1>;
692 }; 658 };
693 659
694 a73pll: clock@b116000 { 660 a73pll: clock@b116000 {
695 compatible = "qcom,ipq 661 compatible = "qcom,ipq9574-a73pll";
696 reg = <0x0b116000 0x40 662 reg = <0x0b116000 0x40>;
697 #clock-cells = <0>; 663 #clock-cells = <0>;
698 clocks = <&xo_board_cl 664 clocks = <&xo_board_clk>;
699 clock-names = "xo"; 665 clock-names = "xo";
700 }; 666 };
701 667
702 timer@b120000 { 668 timer@b120000 {
703 compatible = "arm,armv 669 compatible = "arm,armv7-timer-mem";
704 reg = <0x0b120000 0x10 670 reg = <0x0b120000 0x1000>;
705 #address-cells = <1>; 671 #address-cells = <1>;
706 #size-cells = <1>; 672 #size-cells = <1>;
707 ranges; 673 ranges;
708 674
709 frame@b120000 { 675 frame@b120000 {
710 reg = <0x0b121 676 reg = <0x0b121000 0x1000>,
711 <0x0b122 677 <0x0b122000 0x1000>;
712 frame-number = 678 frame-number = <0>;
713 interrupts = < 679 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
714 < 680 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
715 }; 681 };
716 682
717 frame@b123000 { 683 frame@b123000 {
718 reg = <0x0b123 684 reg = <0x0b123000 0x1000>;
719 frame-number = 685 frame-number = <1>;
720 interrupts = < 686 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
721 status = "disa 687 status = "disabled";
722 }; 688 };
723 689
724 frame@b124000 { 690 frame@b124000 {
725 reg = <0x0b124 691 reg = <0x0b124000 0x1000>;
726 frame-number = 692 frame-number = <2>;
727 interrupts = < 693 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
728 status = "disa 694 status = "disabled";
729 }; 695 };
730 696
731 frame@b125000 { 697 frame@b125000 {
732 reg = <0x0b125 698 reg = <0x0b125000 0x1000>;
733 frame-number = 699 frame-number = <3>;
734 interrupts = < 700 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
735 status = "disa 701 status = "disabled";
736 }; 702 };
737 703
738 frame@b126000 { 704 frame@b126000 {
739 reg = <0x0b126 705 reg = <0x0b126000 0x1000>;
740 frame-number = 706 frame-number = <4>;
741 interrupts = < 707 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
742 status = "disa 708 status = "disabled";
743 }; 709 };
744 710
745 frame@b127000 { 711 frame@b127000 {
746 reg = <0x0b127 712 reg = <0x0b127000 0x1000>;
747 frame-number = 713 frame-number = <5>;
748 interrupts = < 714 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
749 status = "disa 715 status = "disabled";
750 }; 716 };
751 717
752 frame@b128000 { 718 frame@b128000 {
753 reg = <0x0b128 719 reg = <0x0b128000 0x1000>;
754 frame-number = 720 frame-number = <6>;
755 interrupts = < 721 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
756 status = "disa 722 status = "disabled";
757 }; 723 };
758 }; 724 };
759 }; 725 };
760 726
761 thermal-zones { 727 thermal-zones {
762 nss-top-thermal { 728 nss-top-thermal {
>> 729 polling-delay-passive = <0>;
>> 730 polling-delay = <0>;
763 thermal-sensors = <&ts 731 thermal-sensors = <&tsens 3>;
764 732
765 trips { 733 trips {
766 nss-top-critic 734 nss-top-critical {
767 temper 735 temperature = <125000>;
768 hyster 736 hysteresis = <1000>;
769 type = 737 type = "critical";
770 }; 738 };
771 }; 739 };
772 }; 740 };
773 741
774 ubi-0-thermal { 742 ubi-0-thermal {
>> 743 polling-delay-passive = <0>;
>> 744 polling-delay = <0>;
775 thermal-sensors = <&ts 745 thermal-sensors = <&tsens 4>;
776 746
777 trips { 747 trips {
778 ubi_0-critical 748 ubi_0-critical {
779 temper 749 temperature = <125000>;
780 hyster 750 hysteresis = <1000>;
781 type = 751 type = "critical";
782 }; 752 };
783 }; 753 };
784 }; 754 };
785 755
786 ubi-1-thermal { 756 ubi-1-thermal {
>> 757 polling-delay-passive = <0>;
>> 758 polling-delay = <0>;
787 thermal-sensors = <&ts 759 thermal-sensors = <&tsens 5>;
788 760
789 trips { 761 trips {
790 ubi_1-critical 762 ubi_1-critical {
791 temper 763 temperature = <125000>;
792 hyster 764 hysteresis = <1000>;
793 type = 765 type = "critical";
794 }; 766 };
795 }; 767 };
796 }; 768 };
797 769
798 ubi-2-thermal { 770 ubi-2-thermal {
>> 771 polling-delay-passive = <0>;
>> 772 polling-delay = <0>;
799 thermal-sensors = <&ts 773 thermal-sensors = <&tsens 6>;
800 774
801 trips { 775 trips {
802 ubi_2-critical 776 ubi_2-critical {
803 temper 777 temperature = <125000>;
804 hyster 778 hysteresis = <1000>;
805 type = 779 type = "critical";
806 }; 780 };
807 }; 781 };
808 }; 782 };
809 783
810 ubi-3-thermal { 784 ubi-3-thermal {
>> 785 polling-delay-passive = <0>;
>> 786 polling-delay = <0>;
811 thermal-sensors = <&ts 787 thermal-sensors = <&tsens 7>;
812 788
813 trips { 789 trips {
814 ubi_3-critical 790 ubi_3-critical {
815 temper 791 temperature = <125000>;
816 hyster 792 hysteresis = <1000>;
817 type = 793 type = "critical";
818 }; 794 };
819 }; 795 };
820 }; 796 };
821 797
822 cpuss0-thermal { 798 cpuss0-thermal {
>> 799 polling-delay-passive = <0>;
>> 800 polling-delay = <0>;
823 thermal-sensors = <&ts 801 thermal-sensors = <&tsens 8>;
824 802
825 trips { 803 trips {
826 cpu-critical { 804 cpu-critical {
827 temper 805 temperature = <125000>;
828 hyster 806 hysteresis = <1000>;
829 type = 807 type = "critical";
830 }; 808 };
831 }; 809 };
832 }; 810 };
833 811
834 cpuss1-thermal { 812 cpuss1-thermal {
>> 813 polling-delay-passive = <0>;
>> 814 polling-delay = <0>;
835 thermal-sensors = <&ts 815 thermal-sensors = <&tsens 9>;
836 816
837 trips { 817 trips {
838 cpu-critical { 818 cpu-critical {
839 temper 819 temperature = <125000>;
840 hyster 820 hysteresis = <1000>;
841 type = 821 type = "critical";
842 }; 822 };
843 }; 823 };
844 }; 824 };
845 825
846 cpu0-thermal { 826 cpu0-thermal {
>> 827 polling-delay-passive = <0>;
>> 828 polling-delay = <0>;
847 thermal-sensors = <&ts 829 thermal-sensors = <&tsens 10>;
848 830
849 trips { 831 trips {
850 cpu0_crit: cpu 832 cpu0_crit: cpu-critical {
851 temper 833 temperature = <120000>;
852 hyster 834 hysteresis = <10000>;
853 type = 835 type = "critical";
854 }; 836 };
855 837
856 cpu0_alert: cp 838 cpu0_alert: cpu-passive {
857 temper 839 temperature = <110000>;
858 hyster 840 hysteresis = <1000>;
859 type = 841 type = "passive";
860 }; 842 };
861 }; 843 };
862 844
863 cooling-maps { 845 cooling-maps {
864 map0 { 846 map0 {
865 trip = 847 trip = <&cpu0_alert>;
866 coolin 848 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
867 849 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
868 850 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
869 851 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
870 }; 852 };
871 }; 853 };
872 }; 854 };
873 855
874 cpu1-thermal { 856 cpu1-thermal {
>> 857 polling-delay-passive = <0>;
>> 858 polling-delay = <0>;
875 thermal-sensors = <&ts 859 thermal-sensors = <&tsens 11>;
876 860
877 trips { 861 trips {
878 cpu1_crit: cpu 862 cpu1_crit: cpu-critical {
879 temper 863 temperature = <120000>;
880 hyster 864 hysteresis = <10000>;
881 type = 865 type = "critical";
882 }; 866 };
883 867
884 cpu1_alert: cp 868 cpu1_alert: cpu-passive {
885 temper 869 temperature = <110000>;
886 hyster 870 hysteresis = <1000>;
887 type = 871 type = "passive";
888 }; 872 };
889 }; 873 };
890 874
891 cooling-maps { 875 cooling-maps {
892 map0 { 876 map0 {
893 trip = 877 trip = <&cpu1_alert>;
894 coolin 878 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
895 879 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
896 880 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
897 881 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
898 }; 882 };
899 }; 883 };
900 }; 884 };
901 885
902 cpu2-thermal { 886 cpu2-thermal {
>> 887 polling-delay-passive = <0>;
>> 888 polling-delay = <0>;
903 thermal-sensors = <&ts 889 thermal-sensors = <&tsens 12>;
904 890
905 trips { 891 trips {
906 cpu2_crit: cpu 892 cpu2_crit: cpu-critical {
907 temper 893 temperature = <120000>;
908 hyster 894 hysteresis = <10000>;
909 type = 895 type = "critical";
910 }; 896 };
911 897
912 cpu2_alert: cp 898 cpu2_alert: cpu-passive {
913 temper 899 temperature = <110000>;
914 hyster 900 hysteresis = <1000>;
915 type = 901 type = "passive";
916 }; 902 };
917 }; 903 };
918 904
919 cooling-maps { 905 cooling-maps {
920 map0 { 906 map0 {
921 trip = 907 trip = <&cpu2_alert>;
922 coolin 908 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
923 909 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
924 910 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
925 911 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
926 }; 912 };
927 }; 913 };
928 }; 914 };
929 915
930 cpu3-thermal { 916 cpu3-thermal {
>> 917 polling-delay-passive = <0>;
>> 918 polling-delay = <0>;
931 thermal-sensors = <&ts 919 thermal-sensors = <&tsens 13>;
932 920
933 trips { 921 trips {
934 cpu3_crit: cpu 922 cpu3_crit: cpu-critical {
935 temper 923 temperature = <120000>;
936 hyster 924 hysteresis = <10000>;
937 type = 925 type = "critical";
938 }; 926 };
939 927
940 cpu3_alert: cp 928 cpu3_alert: cpu-passive {
941 temper 929 temperature = <110000>;
942 hyster 930 hysteresis = <1000>;
943 type = 931 type = "passive";
944 }; 932 };
945 }; 933 };
946 934
947 cooling-maps { 935 cooling-maps {
948 map0 { 936 map0 {
949 trip = 937 trip = <&cpu3_alert>;
950 coolin 938 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
951 939 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
952 940 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
953 941 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
954 }; 942 };
955 }; 943 };
956 }; 944 };
957 945
958 wcss-phyb-thermal { 946 wcss-phyb-thermal {
>> 947 polling-delay-passive = <0>;
>> 948 polling-delay = <0>;
959 thermal-sensors = <&ts 949 thermal-sensors = <&tsens 14>;
960 950
961 trips { 951 trips {
962 wcss_phyb-crit 952 wcss_phyb-critical {
963 temper 953 temperature = <125000>;
964 hyster 954 hysteresis = <1000>;
965 type = 955 type = "critical";
966 }; 956 };
967 }; 957 };
968 }; 958 };
969 959
970 top-glue-thermal { 960 top-glue-thermal {
>> 961 polling-delay-passive = <0>;
>> 962 polling-delay = <0>;
971 thermal-sensors = <&ts 963 thermal-sensors = <&tsens 15>;
972 964
973 trips { 965 trips {
974 top_glue-criti 966 top_glue-critical {
975 temper 967 temperature = <125000>;
976 hyster 968 hysteresis = <1000>;
977 type = 969 type = "critical";
978 }; 970 };
979 }; 971 };
980 }; 972 };
981 }; 973 };
982 974
983 timer { 975 timer {
984 compatible = "arm,armv8-timer" 976 compatible = "arm,armv8-timer";
985 interrupts = <GIC_PPI 2 (GIC_C 977 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
986 <GIC_PPI 3 (GIC_C 978 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
987 <GIC_PPI 4 (GIC_C 979 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
988 <GIC_PPI 1 (GIC_C 980 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
989 }; 981 };
990 }; 982 };
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