1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3 1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2 /* 2 /*
3 * IPQ9574 SoC device tree source 3 * IPQ9574 SoC device tree source
4 * 4 *
5 * Copyright (c) 2020-2021 The Linux Foundatio 5 * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
6 * Copyright (c) 2023, Qualcomm Innovation Cen 6 * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
7 */ 7 */
8 8
9 #include <dt-bindings/clock/qcom,apss-ipq.h> 9 #include <dt-bindings/clock/qcom,apss-ipq.h>
10 #include <dt-bindings/clock/qcom,ipq9574-gcc.h 10 #include <dt-bindings/clock/qcom,ipq9574-gcc.h>
11 #include <dt-bindings/interconnect/qcom,ipq957 <<
12 #include <dt-bindings/interrupt-controller/arm 11 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/reset/qcom,ipq9574-gcc.h 12 #include <dt-bindings/reset/qcom,ipq9574-gcc.h>
14 #include <dt-bindings/thermal/thermal.h> 13 #include <dt-bindings/thermal/thermal.h>
15 14
16 / { 15 / {
17 interrupt-parent = <&intc>; 16 interrupt-parent = <&intc>;
18 #address-cells = <2>; 17 #address-cells = <2>;
19 #size-cells = <2>; 18 #size-cells = <2>;
20 19
21 clocks { 20 clocks {
22 sleep_clk: sleep-clk { 21 sleep_clk: sleep-clk {
23 compatible = "fixed-cl 22 compatible = "fixed-clock";
24 #clock-cells = <0>; 23 #clock-cells = <0>;
25 }; 24 };
26 25
27 xo_board_clk: xo-board-clk { 26 xo_board_clk: xo-board-clk {
28 compatible = "fixed-cl 27 compatible = "fixed-clock";
29 #clock-cells = <0>; 28 #clock-cells = <0>;
30 }; 29 };
31 }; 30 };
32 31
33 cpus { 32 cpus {
34 #address-cells = <1>; 33 #address-cells = <1>;
35 #size-cells = <0>; 34 #size-cells = <0>;
36 35
37 CPU0: cpu@0 { 36 CPU0: cpu@0 {
38 device_type = "cpu"; 37 device_type = "cpu";
39 compatible = "arm,cort 38 compatible = "arm,cortex-a73";
40 reg = <0x0>; 39 reg = <0x0>;
41 enable-method = "psci" 40 enable-method = "psci";
42 next-level-cache = <&L 41 next-level-cache = <&L2_0>;
43 clocks = <&apcs_glb AP 42 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
44 clock-names = "cpu"; 43 clock-names = "cpu";
45 operating-points-v2 = 44 operating-points-v2 = <&cpu_opp_table>;
46 cpu-supply = <&ipq9574 45 cpu-supply = <&ipq9574_s1>;
47 #cooling-cells = <2>; 46 #cooling-cells = <2>;
48 }; 47 };
49 48
50 CPU1: cpu@1 { 49 CPU1: cpu@1 {
51 device_type = "cpu"; 50 device_type = "cpu";
52 compatible = "arm,cort 51 compatible = "arm,cortex-a73";
53 reg = <0x1>; 52 reg = <0x1>;
54 enable-method = "psci" 53 enable-method = "psci";
55 next-level-cache = <&L 54 next-level-cache = <&L2_0>;
56 clocks = <&apcs_glb AP 55 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
57 clock-names = "cpu"; 56 clock-names = "cpu";
58 operating-points-v2 = 57 operating-points-v2 = <&cpu_opp_table>;
59 cpu-supply = <&ipq9574 58 cpu-supply = <&ipq9574_s1>;
60 #cooling-cells = <2>; 59 #cooling-cells = <2>;
61 }; 60 };
62 61
63 CPU2: cpu@2 { 62 CPU2: cpu@2 {
64 device_type = "cpu"; 63 device_type = "cpu";
65 compatible = "arm,cort 64 compatible = "arm,cortex-a73";
66 reg = <0x2>; 65 reg = <0x2>;
67 enable-method = "psci" 66 enable-method = "psci";
68 next-level-cache = <&L 67 next-level-cache = <&L2_0>;
69 clocks = <&apcs_glb AP 68 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
70 clock-names = "cpu"; 69 clock-names = "cpu";
71 operating-points-v2 = 70 operating-points-v2 = <&cpu_opp_table>;
72 cpu-supply = <&ipq9574 71 cpu-supply = <&ipq9574_s1>;
73 #cooling-cells = <2>; 72 #cooling-cells = <2>;
74 }; 73 };
75 74
76 CPU3: cpu@3 { 75 CPU3: cpu@3 {
77 device_type = "cpu"; 76 device_type = "cpu";
78 compatible = "arm,cort 77 compatible = "arm,cortex-a73";
79 reg = <0x3>; 78 reg = <0x3>;
80 enable-method = "psci" 79 enable-method = "psci";
81 next-level-cache = <&L 80 next-level-cache = <&L2_0>;
82 clocks = <&apcs_glb AP 81 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
83 clock-names = "cpu"; 82 clock-names = "cpu";
84 operating-points-v2 = 83 operating-points-v2 = <&cpu_opp_table>;
85 cpu-supply = <&ipq9574 84 cpu-supply = <&ipq9574_s1>;
86 #cooling-cells = <2>; 85 #cooling-cells = <2>;
87 }; 86 };
88 87
89 L2_0: l2-cache { 88 L2_0: l2-cache {
90 compatible = "cache"; 89 compatible = "cache";
91 cache-level = <2>; 90 cache-level = <2>;
92 cache-unified; 91 cache-unified;
93 }; 92 };
94 }; 93 };
95 94
96 firmware { 95 firmware {
97 scm { 96 scm {
98 compatible = "qcom,scm 97 compatible = "qcom,scm-ipq9574", "qcom,scm";
99 qcom,dload-mode = <&tc 98 qcom,dload-mode = <&tcsr 0x6100>;
100 }; 99 };
101 }; 100 };
102 101
103 memory@40000000 { 102 memory@40000000 {
104 device_type = "memory"; 103 device_type = "memory";
105 /* We expect the bootloader to 104 /* We expect the bootloader to fill in the size */
106 reg = <0x0 0x40000000 0x0 0x0> 105 reg = <0x0 0x40000000 0x0 0x0>;
107 }; 106 };
108 107
109 cpu_opp_table: opp-table-cpu { 108 cpu_opp_table: opp-table-cpu {
110 compatible = "operating-points 109 compatible = "operating-points-v2-kryo-cpu";
111 opp-shared; 110 opp-shared;
112 nvmem-cells = <&cpu_speed_bin> 111 nvmem-cells = <&cpu_speed_bin>;
113 112
114 opp-936000000 { 113 opp-936000000 {
115 opp-hz = /bits/ 64 <93 114 opp-hz = /bits/ 64 <936000000>;
116 opp-microvolt = <72500 115 opp-microvolt = <725000>;
117 opp-supported-hw = <0x 116 opp-supported-hw = <0xf>;
118 clock-latency-ns = <20 117 clock-latency-ns = <200000>;
119 }; 118 };
120 119
121 opp-1104000000 { 120 opp-1104000000 {
122 opp-hz = /bits/ 64 <11 121 opp-hz = /bits/ 64 <1104000000>;
123 opp-microvolt = <78750 122 opp-microvolt = <787500>;
124 opp-supported-hw = <0x 123 opp-supported-hw = <0xf>;
125 clock-latency-ns = <20 124 clock-latency-ns = <200000>;
126 }; 125 };
127 126
128 opp-1200000000 { 127 opp-1200000000 {
129 opp-hz = /bits/ 64 <12 128 opp-hz = /bits/ 64 <1200000000>;
130 opp-microvolt = <86250 129 opp-microvolt = <862500>;
131 opp-supported-hw = <0x 130 opp-supported-hw = <0xf>;
132 clock-latency-ns = <20 131 clock-latency-ns = <200000>;
133 }; 132 };
134 133
135 opp-1416000000 { 134 opp-1416000000 {
136 opp-hz = /bits/ 64 <14 135 opp-hz = /bits/ 64 <1416000000>;
137 opp-microvolt = <86250 136 opp-microvolt = <862500>;
138 opp-supported-hw = <0x 137 opp-supported-hw = <0x7>;
139 clock-latency-ns = <20 138 clock-latency-ns = <200000>;
140 }; 139 };
141 140
142 opp-1488000000 { 141 opp-1488000000 {
143 opp-hz = /bits/ 64 <14 142 opp-hz = /bits/ 64 <1488000000>;
144 opp-microvolt = <92500 143 opp-microvolt = <925000>;
145 opp-supported-hw = <0x 144 opp-supported-hw = <0x7>;
146 clock-latency-ns = <20 145 clock-latency-ns = <200000>;
147 }; 146 };
148 147
149 opp-1800000000 { 148 opp-1800000000 {
150 opp-hz = /bits/ 64 <18 149 opp-hz = /bits/ 64 <1800000000>;
151 opp-microvolt = <98750 150 opp-microvolt = <987500>;
152 opp-supported-hw = <0x 151 opp-supported-hw = <0x5>;
153 clock-latency-ns = <20 152 clock-latency-ns = <200000>;
154 }; 153 };
155 154
156 opp-2208000000 { 155 opp-2208000000 {
157 opp-hz = /bits/ 64 <22 156 opp-hz = /bits/ 64 <2208000000>;
158 opp-microvolt = <10625 157 opp-microvolt = <1062500>;
159 opp-supported-hw = <0x 158 opp-supported-hw = <0x1>;
160 clock-latency-ns = <20 159 clock-latency-ns = <200000>;
161 }; 160 };
162 }; 161 };
163 162
164 pmu { 163 pmu {
165 compatible = "arm,cortex-a73-p 164 compatible = "arm,cortex-a73-pmu";
166 interrupts = <GIC_PPI 7 (GIC_C 165 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
167 }; 166 };
168 167
169 psci { 168 psci {
170 compatible = "arm,psci-1.0"; 169 compatible = "arm,psci-1.0";
171 method = "smc"; 170 method = "smc";
172 }; 171 };
173 172
174 rpm: remoteproc { 173 rpm: remoteproc {
175 compatible = "qcom,ipq9574-rpm 174 compatible = "qcom,ipq9574-rpm-proc", "qcom,rpm-proc";
176 175
177 glink-edge { 176 glink-edge {
178 compatible = "qcom,gli 177 compatible = "qcom,glink-rpm";
179 interrupts = <GIC_SPI 178 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
180 qcom,rpm-msg-ram = <&r 179 qcom,rpm-msg-ram = <&rpm_msg_ram>;
181 mboxes = <&apcs_glb 0> 180 mboxes = <&apcs_glb 0>;
182 181
183 rpm_requests: rpm-requ 182 rpm_requests: rpm-requests {
184 compatible = " !! 183 compatible = "qcom,rpm-ipq9574";
185 qcom,glink-cha 184 qcom,glink-channels = "rpm_requests";
186 }; 185 };
187 }; 186 };
188 }; 187 };
189 188
190 reserved-memory { 189 reserved-memory {
191 #address-cells = <2>; 190 #address-cells = <2>;
192 #size-cells = <2>; 191 #size-cells = <2>;
193 ranges; 192 ranges;
194 193
195 bootloader@4a100000 { 194 bootloader@4a100000 {
196 reg = <0x0 0x4a100000 195 reg = <0x0 0x4a100000 0x0 0x400000>;
197 no-map; 196 no-map;
198 }; 197 };
199 198
200 sbl@4a500000 { 199 sbl@4a500000 {
201 reg = <0x0 0x4a500000 200 reg = <0x0 0x4a500000 0x0 0x100000>;
202 no-map; 201 no-map;
203 }; 202 };
204 203
205 tz_region: tz@4a600000 { 204 tz_region: tz@4a600000 {
206 reg = <0x0 0x4a600000 205 reg = <0x0 0x4a600000 0x0 0x400000>;
207 no-map; 206 no-map;
208 }; 207 };
209 208
210 smem@4aa00000 { 209 smem@4aa00000 {
211 compatible = "qcom,sme 210 compatible = "qcom,smem";
212 reg = <0x0 0x4aa00000 211 reg = <0x0 0x4aa00000 0x0 0x100000>;
213 hwlocks = <&tcsr_mutex 212 hwlocks = <&tcsr_mutex 3>;
214 no-map; 213 no-map;
215 }; 214 };
216 }; 215 };
217 216
218 soc: soc@0 { 217 soc: soc@0 {
219 compatible = "simple-bus"; 218 compatible = "simple-bus";
220 #address-cells = <1>; 219 #address-cells = <1>;
221 #size-cells = <1>; 220 #size-cells = <1>;
222 ranges = <0 0 0 0xffffffff>; 221 ranges = <0 0 0 0xffffffff>;
223 222
224 rpm_msg_ram: sram@60000 { 223 rpm_msg_ram: sram@60000 {
225 compatible = "qcom,rpm 224 compatible = "qcom,rpm-msg-ram";
226 reg = <0x00060000 0x60 225 reg = <0x00060000 0x6000>;
227 }; 226 };
228 227
229 rng: rng@e3000 { 228 rng: rng@e3000 {
230 compatible = "qcom,prn 229 compatible = "qcom,prng-ee";
231 reg = <0x000e3000 0x10 230 reg = <0x000e3000 0x1000>;
232 clocks = <&gcc GCC_PRN 231 clocks = <&gcc GCC_PRNG_AHB_CLK>;
233 clock-names = "core"; 232 clock-names = "core";
234 }; 233 };
235 234
236 mdio: mdio@90000 { <<
237 compatible = "qcom,ip <<
238 reg = <0x00090000 0x64 <<
239 #address-cells = <1>; <<
240 #size-cells = <0>; <<
241 clocks = <&gcc GCC_MDI <<
242 clock-names = "gcc_mdi <<
243 status = "disabled"; <<
244 }; <<
245 <<
246 qfprom: efuse@a4000 { 235 qfprom: efuse@a4000 {
247 compatible = "qcom,ipq 236 compatible = "qcom,ipq9574-qfprom", "qcom,qfprom";
248 reg = <0x000a4000 0x5a 237 reg = <0x000a4000 0x5a1>;
249 #address-cells = <1>; 238 #address-cells = <1>;
250 #size-cells = <1>; 239 #size-cells = <1>;
251 240
252 cpu_speed_bin: cpu-spe 241 cpu_speed_bin: cpu-speed-bin@15 {
253 reg = <0x15 0x 242 reg = <0x15 0x2>;
254 bits = <7 2>; 243 bits = <7 2>;
255 }; 244 };
256 }; 245 };
257 246
258 cryptobam: dma-controller@7040 247 cryptobam: dma-controller@704000 {
259 compatible = "qcom,bam 248 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
260 reg = <0x00704000 0x20 249 reg = <0x00704000 0x20000>;
261 interrupts = <GIC_SPI 250 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
262 #dma-cells = <1>; 251 #dma-cells = <1>;
263 qcom,ee = <1>; 252 qcom,ee = <1>;
264 qcom,controlled-remote 253 qcom,controlled-remotely;
265 }; 254 };
266 255
267 crypto: crypto@73a000 { 256 crypto: crypto@73a000 {
268 compatible = "qcom,ipq 257 compatible = "qcom,ipq9574-qce", "qcom,ipq4019-qce", "qcom,qce";
269 reg = <0x0073a000 0x60 258 reg = <0x0073a000 0x6000>;
270 clocks = <&gcc GCC_CRY 259 clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
271 <&gcc GCC_CRY 260 <&gcc GCC_CRYPTO_AXI_CLK>,
272 <&gcc GCC_CRY 261 <&gcc GCC_CRYPTO_CLK>;
273 clock-names = "iface", 262 clock-names = "iface", "bus", "core";
274 dmas = <&cryptobam 2>, 263 dmas = <&cryptobam 2>, <&cryptobam 3>;
275 dma-names = "rx", "tx" 264 dma-names = "rx", "tx";
276 }; 265 };
277 266
278 tsens: thermal-sensor@4a9000 { 267 tsens: thermal-sensor@4a9000 {
279 compatible = "qcom,ipq 268 compatible = "qcom,ipq9574-tsens", "qcom,ipq8074-tsens";
280 reg = <0x004a9000 0x10 269 reg = <0x004a9000 0x1000>,
281 <0x004a8000 0x10 270 <0x004a8000 0x1000>;
282 interrupts = <GIC_SPI 271 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
283 interrupt-names = "com 272 interrupt-names = "combined";
284 #qcom,sensors = <16>; 273 #qcom,sensors = <16>;
285 #thermal-sensor-cells 274 #thermal-sensor-cells = <1>;
286 }; 275 };
287 276
288 tlmm: pinctrl@1000000 { 277 tlmm: pinctrl@1000000 {
289 compatible = "qcom,ipq 278 compatible = "qcom,ipq9574-tlmm";
290 reg = <0x01000000 0x30 279 reg = <0x01000000 0x300000>;
291 interrupts = <GIC_SPI 280 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
292 gpio-controller; 281 gpio-controller;
293 #gpio-cells = <2>; 282 #gpio-cells = <2>;
294 gpio-ranges = <&tlmm 0 283 gpio-ranges = <&tlmm 0 0 65>;
295 interrupt-controller; 284 interrupt-controller;
296 #interrupt-cells = <2> 285 #interrupt-cells = <2>;
297 286
298 uart2_pins: uart2-stat 287 uart2_pins: uart2-state {
299 pins = "gpio34 288 pins = "gpio34", "gpio35";
300 function = "bl 289 function = "blsp2_uart";
301 drive-strength 290 drive-strength = <8>;
302 bias-disable; 291 bias-disable;
303 }; 292 };
304 }; 293 };
305 294
306 gcc: clock-controller@1800000 295 gcc: clock-controller@1800000 {
307 compatible = "qcom,ipq 296 compatible = "qcom,ipq9574-gcc";
308 reg = <0x01800000 0x80 297 reg = <0x01800000 0x80000>;
309 clocks = <&xo_board_cl 298 clocks = <&xo_board_clk>,
310 <&sleep_clk>, 299 <&sleep_clk>,
311 <0>, 300 <0>,
312 <0>, 301 <0>,
313 <0>, 302 <0>,
314 <0>, 303 <0>,
315 <0>, 304 <0>,
316 <0>; 305 <0>;
317 #clock-cells = <1>; 306 #clock-cells = <1>;
318 #reset-cells = <1>; 307 #reset-cells = <1>;
319 #interconnect-cells = !! 308 #power-domain-cells = <1>;
320 }; 309 };
321 310
322 tcsr_mutex: hwlock@1905000 { 311 tcsr_mutex: hwlock@1905000 {
323 compatible = "qcom,tcs 312 compatible = "qcom,tcsr-mutex";
324 reg = <0x01905000 0x20 313 reg = <0x01905000 0x20000>;
325 #hwlock-cells = <1>; 314 #hwlock-cells = <1>;
326 }; 315 };
327 316
328 tcsr: syscon@1937000 { 317 tcsr: syscon@1937000 {
329 compatible = "qcom,tcs 318 compatible = "qcom,tcsr-ipq9574", "syscon";
330 reg = <0x01937000 0x21 319 reg = <0x01937000 0x21000>;
331 }; 320 };
332 321
333 sdhc_1: mmc@7804000 { 322 sdhc_1: mmc@7804000 {
334 compatible = "qcom,ipq 323 compatible = "qcom,ipq9574-sdhci", "qcom,sdhci-msm-v5";
335 reg = <0x07804000 0x10 !! 324 reg = <0x07804000 0x1000>, <0x07805000 0x1000>;
336 <0x07805000 0x10 !! 325 reg-names = "hc", "cqhci";
337 <0x07808000 0x20 <<
338 reg-names = "hc", "cqh <<
339 326
340 interrupts = <GIC_SPI 327 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
341 <GIC_SPI 328 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
342 interrupt-names = "hc_ 329 interrupt-names = "hc_irq", "pwr_irq";
343 330
344 clocks = <&gcc GCC_SDC 331 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
345 <&gcc GCC_SDC 332 <&gcc GCC_SDCC1_APPS_CLK>,
346 <&xo_board_cl !! 333 <&xo_board_clk>;
347 <&gcc GCC_SDC !! 334 clock-names = "iface", "core", "xo";
348 clock-names = "iface", <<
349 non-removable; 335 non-removable;
350 supports-cqe; <<
351 status = "disabled"; 336 status = "disabled";
352 }; 337 };
353 338
354 blsp_dma: dma-controller@78840 339 blsp_dma: dma-controller@7884000 {
355 compatible = "qcom,bam 340 compatible = "qcom,bam-v1.7.0";
356 reg = <0x07884000 0x2b 341 reg = <0x07884000 0x2b000>;
357 interrupts = <GIC_SPI 342 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
358 clocks = <&gcc GCC_BLS 343 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
359 clock-names = "bam_clk 344 clock-names = "bam_clk";
360 #dma-cells = <1>; 345 #dma-cells = <1>;
361 qcom,ee = <0>; 346 qcom,ee = <0>;
362 }; 347 };
363 348
364 blsp1_uart0: serial@78af000 { 349 blsp1_uart0: serial@78af000 {
365 compatible = "qcom,msm 350 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
366 reg = <0x078af000 0x20 351 reg = <0x078af000 0x200>;
367 interrupts = <GIC_SPI 352 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
368 clocks = <&gcc GCC_BLS 353 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
369 <&gcc GCC_BLS 354 <&gcc GCC_BLSP1_AHB_CLK>;
370 clock-names = "core", 355 clock-names = "core", "iface";
371 status = "disabled"; 356 status = "disabled";
372 }; 357 };
373 358
374 blsp1_uart1: serial@78b0000 { 359 blsp1_uart1: serial@78b0000 {
375 compatible = "qcom,msm 360 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
376 reg = <0x078b0000 0x20 361 reg = <0x078b0000 0x200>;
377 interrupts = <GIC_SPI 362 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
378 clocks = <&gcc GCC_BLS 363 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
379 <&gcc GCC_BLS 364 <&gcc GCC_BLSP1_AHB_CLK>;
380 clock-names = "core", 365 clock-names = "core", "iface";
381 status = "disabled"; 366 status = "disabled";
382 }; 367 };
383 368
384 blsp1_uart2: serial@78b1000 { 369 blsp1_uart2: serial@78b1000 {
385 compatible = "qcom,msm 370 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
386 reg = <0x078b1000 0x20 371 reg = <0x078b1000 0x200>;
387 interrupts = <GIC_SPI 372 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
388 clocks = <&gcc GCC_BLS 373 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
389 <&gcc GCC_BLS 374 <&gcc GCC_BLSP1_AHB_CLK>;
390 clock-names = "core", 375 clock-names = "core", "iface";
391 status = "disabled"; 376 status = "disabled";
392 }; 377 };
393 378
394 blsp1_uart3: serial@78b2000 { 379 blsp1_uart3: serial@78b2000 {
395 compatible = "qcom,msm 380 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
396 reg = <0x078b2000 0x20 381 reg = <0x078b2000 0x200>;
397 interrupts = <GIC_SPI 382 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
398 clocks = <&gcc GCC_BLS 383 clocks = <&gcc GCC_BLSP1_UART4_APPS_CLK>,
399 <&gcc GCC_BLS 384 <&gcc GCC_BLSP1_AHB_CLK>;
400 clock-names = "core", 385 clock-names = "core", "iface";
401 status = "disabled"; 386 status = "disabled";
402 }; 387 };
403 388
404 blsp1_uart4: serial@78b3000 { 389 blsp1_uart4: serial@78b3000 {
405 compatible = "qcom,msm 390 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
406 reg = <0x078b3000 0x20 391 reg = <0x078b3000 0x200>;
407 interrupts = <GIC_SPI 392 interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
408 clocks = <&gcc GCC_BLS 393 clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>,
409 <&gcc GCC_BLS 394 <&gcc GCC_BLSP1_AHB_CLK>;
410 clock-names = "core", 395 clock-names = "core", "iface";
411 status = "disabled"; 396 status = "disabled";
412 }; 397 };
413 398
414 blsp1_uart5: serial@78b4000 { 399 blsp1_uart5: serial@78b4000 {
415 compatible = "qcom,msm 400 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
416 reg = <0x078b4000 0x20 401 reg = <0x078b4000 0x200>;
417 interrupts = <GIC_SPI 402 interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>;
418 clocks = <&gcc GCC_BLS 403 clocks = <&gcc GCC_BLSP1_UART6_APPS_CLK>,
419 <&gcc GCC_BLS 404 <&gcc GCC_BLSP1_AHB_CLK>;
420 clock-names = "core", 405 clock-names = "core", "iface";
421 status = "disabled"; 406 status = "disabled";
422 }; 407 };
423 408
424 blsp1_spi0: spi@78b5000 { 409 blsp1_spi0: spi@78b5000 {
425 compatible = "qcom,spi 410 compatible = "qcom,spi-qup-v2.2.1";
426 reg = <0x078b5000 0x60 411 reg = <0x078b5000 0x600>;
427 #address-cells = <1>; 412 #address-cells = <1>;
428 #size-cells = <0>; 413 #size-cells = <0>;
429 interrupts = <GIC_SPI 414 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
430 clocks = <&gcc GCC_BLS 415 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
431 <&gcc GCC_BLS 416 <&gcc GCC_BLSP1_AHB_CLK>;
432 clock-names = "core", 417 clock-names = "core", "iface";
433 dmas = <&blsp_dma 12>, 418 dmas = <&blsp_dma 12>, <&blsp_dma 13>;
434 dma-names = "tx", "rx" 419 dma-names = "tx", "rx";
435 status = "disabled"; 420 status = "disabled";
436 }; 421 };
437 422
438 blsp1_i2c1: i2c@78b6000 { 423 blsp1_i2c1: i2c@78b6000 {
439 compatible = "qcom,i2c 424 compatible = "qcom,i2c-qup-v2.2.1";
440 reg = <0x078b6000 0x60 425 reg = <0x078b6000 0x600>;
441 #address-cells = <1>; 426 #address-cells = <1>;
442 #size-cells = <0>; 427 #size-cells = <0>;
443 interrupts = <GIC_SPI 428 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
444 clocks = <&gcc GCC_BLS 429 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
445 <&gcc GCC_BLS 430 <&gcc GCC_BLSP1_AHB_CLK>;
446 clock-names = "core", 431 clock-names = "core", "iface";
447 assigned-clocks = <&gc 432 assigned-clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
448 assigned-clock-rates = 433 assigned-clock-rates = <50000000>;
449 dmas = <&blsp_dma 14>, 434 dmas = <&blsp_dma 14>, <&blsp_dma 15>;
450 dma-names = "tx", "rx" 435 dma-names = "tx", "rx";
451 status = "disabled"; 436 status = "disabled";
452 }; 437 };
453 438
454 blsp1_spi1: spi@78b6000 { 439 blsp1_spi1: spi@78b6000 {
455 compatible = "qcom,spi 440 compatible = "qcom,spi-qup-v2.2.1";
456 reg = <0x078b6000 0x60 441 reg = <0x078b6000 0x600>;
457 #address-cells = <1>; 442 #address-cells = <1>;
458 #size-cells = <0>; 443 #size-cells = <0>;
459 interrupts = <GIC_SPI 444 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
460 clocks = <&gcc GCC_BLS 445 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
461 <&gcc GCC_BLS 446 <&gcc GCC_BLSP1_AHB_CLK>;
462 clock-names = "core", 447 clock-names = "core", "iface";
463 dmas = <&blsp_dma 14>, 448 dmas = <&blsp_dma 14>, <&blsp_dma 15>;
464 dma-names = "tx", "rx" 449 dma-names = "tx", "rx";
465 status = "disabled"; 450 status = "disabled";
466 }; 451 };
467 452
468 blsp1_i2c2: i2c@78b7000 { 453 blsp1_i2c2: i2c@78b7000 {
469 compatible = "qcom,i2c 454 compatible = "qcom,i2c-qup-v2.2.1";
470 reg = <0x078b7000 0x60 455 reg = <0x078b7000 0x600>;
471 #address-cells = <1>; 456 #address-cells = <1>;
472 #size-cells = <0>; 457 #size-cells = <0>;
473 interrupts = <GIC_SPI 458 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
474 clocks = <&gcc GCC_BLS 459 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
475 <&gcc GCC_BLS 460 <&gcc GCC_BLSP1_AHB_CLK>;
476 clock-names = "core", 461 clock-names = "core", "iface";
477 assigned-clocks = <&gc 462 assigned-clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
478 assigned-clock-rates = 463 assigned-clock-rates = <50000000>;
479 dmas = <&blsp_dma 16>, 464 dmas = <&blsp_dma 16>, <&blsp_dma 17>;
480 dma-names = "tx", "rx" 465 dma-names = "tx", "rx";
481 status = "disabled"; 466 status = "disabled";
482 }; 467 };
483 468
484 blsp1_spi2: spi@78b7000 { 469 blsp1_spi2: spi@78b7000 {
485 compatible = "qcom,spi 470 compatible = "qcom,spi-qup-v2.2.1";
486 reg = <0x078b7000 0x60 471 reg = <0x078b7000 0x600>;
487 #address-cells = <1>; 472 #address-cells = <1>;
488 #size-cells = <0>; 473 #size-cells = <0>;
489 interrupts = <GIC_SPI 474 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
490 clocks = <&gcc GCC_BLS 475 clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
491 <&gcc GCC_BLS 476 <&gcc GCC_BLSP1_AHB_CLK>;
492 clock-names = "core", 477 clock-names = "core", "iface";
493 dmas = <&blsp_dma 16>, 478 dmas = <&blsp_dma 16>, <&blsp_dma 17>;
494 dma-names = "tx", "rx" 479 dma-names = "tx", "rx";
495 status = "disabled"; 480 status = "disabled";
496 }; 481 };
497 482
498 blsp1_i2c3: i2c@78b8000 { 483 blsp1_i2c3: i2c@78b8000 {
499 compatible = "qcom,i2c 484 compatible = "qcom,i2c-qup-v2.2.1";
500 reg = <0x078b8000 0x60 485 reg = <0x078b8000 0x600>;
501 #address-cells = <1>; 486 #address-cells = <1>;
502 #size-cells = <0>; 487 #size-cells = <0>;
503 interrupts = <GIC_SPI 488 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
504 clocks = <&gcc GCC_BLS 489 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
505 <&gcc GCC_BLS 490 <&gcc GCC_BLSP1_AHB_CLK>;
506 clock-names = "core", 491 clock-names = "core", "iface";
507 assigned-clocks = <&gc 492 assigned-clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
508 assigned-clock-rates = 493 assigned-clock-rates = <50000000>;
509 dmas = <&blsp_dma 18>, 494 dmas = <&blsp_dma 18>, <&blsp_dma 19>;
510 dma-names = "tx", "rx" 495 dma-names = "tx", "rx";
511 status = "disabled"; 496 status = "disabled";
512 }; 497 };
513 498
514 blsp1_spi3: spi@78b8000 { 499 blsp1_spi3: spi@78b8000 {
515 compatible = "qcom,spi 500 compatible = "qcom,spi-qup-v2.2.1";
516 reg = <0x078b8000 0x60 501 reg = <0x078b8000 0x600>;
517 #address-cells = <1>; 502 #address-cells = <1>;
518 #size-cells = <0>; 503 #size-cells = <0>;
519 interrupts = <GIC_SPI 504 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
520 spi-max-frequency = <5 505 spi-max-frequency = <50000000>;
521 clocks = <&gcc GCC_BLS 506 clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
522 <&gcc GCC_BLS 507 <&gcc GCC_BLSP1_AHB_CLK>;
523 clock-names = "core", 508 clock-names = "core", "iface";
524 dmas = <&blsp_dma 18>, 509 dmas = <&blsp_dma 18>, <&blsp_dma 19>;
525 dma-names = "tx", "rx" 510 dma-names = "tx", "rx";
526 status = "disabled"; 511 status = "disabled";
527 }; 512 };
528 513
529 blsp1_i2c4: i2c@78b9000 { 514 blsp1_i2c4: i2c@78b9000 {
530 compatible = "qcom,i2c 515 compatible = "qcom,i2c-qup-v2.2.1";
531 reg = <0x078b9000 0x60 516 reg = <0x078b9000 0x600>;
532 #address-cells = <1>; 517 #address-cells = <1>;
533 #size-cells = <0>; 518 #size-cells = <0>;
534 interrupts = <GIC_SPI 519 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
535 clocks = <&gcc GCC_BLS 520 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
536 <&gcc GCC_BLS 521 <&gcc GCC_BLSP1_AHB_CLK>;
537 clock-names = "core", 522 clock-names = "core", "iface";
538 assigned-clocks = <&gc 523 assigned-clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>;
539 assigned-clock-rates = 524 assigned-clock-rates = <50000000>;
540 dmas = <&blsp_dma 20>, 525 dmas = <&blsp_dma 20>, <&blsp_dma 21>;
541 dma-names = "tx", "rx" 526 dma-names = "tx", "rx";
542 status = "disabled"; 527 status = "disabled";
543 }; 528 };
544 529
545 blsp1_spi4: spi@78b9000 { 530 blsp1_spi4: spi@78b9000 {
546 compatible = "qcom,spi 531 compatible = "qcom,spi-qup-v2.2.1";
547 reg = <0x078b9000 0x60 532 reg = <0x078b9000 0x600>;
548 #address-cells = <1>; 533 #address-cells = <1>;
549 #size-cells = <0>; 534 #size-cells = <0>;
550 interrupts = <GIC_SPI 535 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
551 clocks = <&gcc GCC_BLS 536 clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
552 <&gcc GCC_BLS 537 <&gcc GCC_BLSP1_AHB_CLK>;
553 clock-names = "core", 538 clock-names = "core", "iface";
554 dmas = <&blsp_dma 20>, 539 dmas = <&blsp_dma 20>, <&blsp_dma 21>;
555 dma-names = "tx", "rx" 540 dma-names = "tx", "rx";
556 status = "disabled"; 541 status = "disabled";
557 }; 542 };
558 543
559 usb_0_qusbphy: phy@7b000 { 544 usb_0_qusbphy: phy@7b000 {
560 compatible = "qcom,ipq 545 compatible = "qcom,ipq9574-qusb2-phy";
561 reg = <0x0007b000 0x18 546 reg = <0x0007b000 0x180>;
562 #phy-cells = <0>; 547 #phy-cells = <0>;
563 548
564 clocks = <&gcc GCC_USB 549 clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
565 <&xo_board_cl 550 <&xo_board_clk>;
566 clock-names = "cfg_ahb 551 clock-names = "cfg_ahb",
567 "ref"; 552 "ref";
568 553
569 resets = <&gcc GCC_QUS 554 resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
570 status = "disabled"; 555 status = "disabled";
571 }; 556 };
572 557
573 usb_0_qmpphy: phy@7d000 { 558 usb_0_qmpphy: phy@7d000 {
574 compatible = "qcom,ipq 559 compatible = "qcom,ipq9574-qmp-usb3-phy";
575 reg = <0x0007d000 0xa0 560 reg = <0x0007d000 0xa00>;
576 #phy-cells = <0>; 561 #phy-cells = <0>;
577 562
578 clocks = <&gcc GCC_USB 563 clocks = <&gcc GCC_USB0_AUX_CLK>,
579 <&xo_board_cl 564 <&xo_board_clk>,
580 <&gcc GCC_USB 565 <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
581 <&gcc GCC_USB 566 <&gcc GCC_USB0_PIPE_CLK>;
582 clock-names = "aux", 567 clock-names = "aux",
583 "ref", 568 "ref",
584 "cfg_ahb 569 "cfg_ahb",
585 "pipe"; 570 "pipe";
586 571
587 resets = <&gcc GCC_USB 572 resets = <&gcc GCC_USB0_PHY_BCR>,
588 <&gcc GCC_USB 573 <&gcc GCC_USB3PHY_0_PHY_BCR>;
589 reset-names = "phy", 574 reset-names = "phy",
590 "phy_phy 575 "phy_phy";
591 576
592 #clock-cells = <0>; 577 #clock-cells = <0>;
593 clock-output-names = " 578 clock-output-names = "usb0_pipe_clk";
594 579
595 status = "disabled"; 580 status = "disabled";
596 }; 581 };
597 582
598 usb3: usb@8af8800 { 583 usb3: usb@8af8800 {
599 compatible = "qcom,ipq 584 compatible = "qcom,ipq9574-dwc3", "qcom,dwc3";
600 reg = <0x08af8800 0x40 585 reg = <0x08af8800 0x400>;
601 #address-cells = <1>; 586 #address-cells = <1>;
602 #size-cells = <1>; 587 #size-cells = <1>;
603 ranges; 588 ranges;
604 589
605 clocks = <&gcc GCC_SNO 590 clocks = <&gcc GCC_SNOC_USB_CLK>,
606 <&gcc GCC_USB 591 <&gcc GCC_USB0_MASTER_CLK>,
607 <&gcc GCC_ANO 592 <&gcc GCC_ANOC_USB_AXI_CLK>,
608 <&gcc GCC_USB 593 <&gcc GCC_USB0_SLEEP_CLK>,
609 <&gcc GCC_USB 594 <&gcc GCC_USB0_MOCK_UTMI_CLK>;
610 595
611 clock-names = "cfg_noc 596 clock-names = "cfg_noc",
612 "core", 597 "core",
613 "iface", 598 "iface",
614 "sleep", 599 "sleep",
615 "mock_ut 600 "mock_utmi";
616 601
617 assigned-clocks = <&gc 602 assigned-clocks = <&gcc GCC_USB0_MASTER_CLK>,
618 <&gc 603 <&gcc GCC_USB0_MOCK_UTMI_CLK>;
619 assigned-clock-rates = 604 assigned-clock-rates = <200000000>,
620 605 <24000000>;
621 606
622 interrupts-extended = 607 interrupts-extended = <&intc GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
623 interrupt-names = "pwr 608 interrupt-names = "pwr_event";
624 609
625 resets = <&gcc GCC_USB 610 resets = <&gcc GCC_USB_BCR>;
626 status = "disabled"; 611 status = "disabled";
627 612
628 usb_0_dwc3: usb@8a0000 613 usb_0_dwc3: usb@8a00000 {
629 compatible = " 614 compatible = "snps,dwc3";
630 reg = <0x8a000 615 reg = <0x8a00000 0xcd00>;
631 clocks = <&gcc 616 clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>;
632 clock-names = 617 clock-names = "ref";
633 interrupts = < 618 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
634 phys = <&usb_0 619 phys = <&usb_0_qusbphy>, <&usb_0_qmpphy>;
635 phy-names = "u 620 phy-names = "usb2-phy", "usb3-phy";
636 tx-fifo-resize 621 tx-fifo-resize;
637 snps,is-utmi-l 622 snps,is-utmi-l1-suspend;
638 snps,hird-thre 623 snps,hird-threshold = /bits/ 8 <0x0>;
639 snps,dis_u2_su 624 snps,dis_u2_susphy_quirk;
640 snps,dis_u3_su 625 snps,dis_u3_susphy_quirk;
641 }; 626 };
642 }; 627 };
643 628
644 intc: interrupt-controller@b00 629 intc: interrupt-controller@b000000 {
645 compatible = "qcom,msm 630 compatible = "qcom,msm-qgic2";
646 reg = <0x0b000000 0x10 631 reg = <0x0b000000 0x1000>, /* GICD */
647 <0x0b002000 0x20 632 <0x0b002000 0x2000>, /* GICC */
648 <0x0b001000 0x10 633 <0x0b001000 0x1000>, /* GICH */
649 <0x0b004000 0x20 634 <0x0b004000 0x2000>; /* GICV */
650 #address-cells = <1>; 635 #address-cells = <1>;
651 #size-cells = <1>; 636 #size-cells = <1>;
652 interrupt-controller; 637 interrupt-controller;
653 #interrupt-cells = <3> 638 #interrupt-cells = <3>;
654 interrupts = <GIC_PPI 639 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
655 ranges = <0 0x0b00c000 640 ranges = <0 0x0b00c000 0x3000>;
656 641
657 v2m0: v2m@0 { 642 v2m0: v2m@0 {
658 compatible = " 643 compatible = "arm,gic-v2m-frame";
659 reg = <0x00000 644 reg = <0x00000000 0xffd>;
660 msi-controller 645 msi-controller;
661 }; 646 };
662 647
663 v2m1: v2m@1000 { 648 v2m1: v2m@1000 {
664 compatible = " 649 compatible = "arm,gic-v2m-frame";
665 reg = <0x00001 650 reg = <0x00001000 0xffd>;
666 msi-controller 651 msi-controller;
667 }; 652 };
668 653
669 v2m2: v2m@2000 { 654 v2m2: v2m@2000 {
670 compatible = " 655 compatible = "arm,gic-v2m-frame";
671 reg = <0x00002 656 reg = <0x00002000 0xffd>;
672 msi-controller 657 msi-controller;
673 }; 658 };
674 }; 659 };
675 660
676 watchdog: watchdog@b017000 { 661 watchdog: watchdog@b017000 {
677 compatible = "qcom,aps 662 compatible = "qcom,apss-wdt-ipq9574", "qcom,kpss-wdt";
678 reg = <0x0b017000 0x10 663 reg = <0x0b017000 0x1000>;
679 interrupts = <GIC_SPI 664 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
680 clocks = <&sleep_clk>; 665 clocks = <&sleep_clk>;
681 timeout-sec = <30>; 666 timeout-sec = <30>;
682 }; 667 };
683 668
684 apcs_glb: mailbox@b111000 { 669 apcs_glb: mailbox@b111000 {
685 compatible = "qcom,ipq 670 compatible = "qcom,ipq9574-apcs-apps-global",
686 "qcom,ipq 671 "qcom,ipq6018-apcs-apps-global";
687 reg = <0x0b111000 0x10 672 reg = <0x0b111000 0x1000>;
688 #clock-cells = <1>; 673 #clock-cells = <1>;
689 clocks = <&a73pll>, <& 674 clocks = <&a73pll>, <&xo_board_clk>, <&gcc GPLL0>;
690 clock-names = "pll", " 675 clock-names = "pll", "xo", "gpll0";
691 #mbox-cells = <1>; 676 #mbox-cells = <1>;
692 }; 677 };
693 678
694 a73pll: clock@b116000 { 679 a73pll: clock@b116000 {
695 compatible = "qcom,ipq 680 compatible = "qcom,ipq9574-a73pll";
696 reg = <0x0b116000 0x40 681 reg = <0x0b116000 0x40>;
697 #clock-cells = <0>; 682 #clock-cells = <0>;
698 clocks = <&xo_board_cl 683 clocks = <&xo_board_clk>;
699 clock-names = "xo"; 684 clock-names = "xo";
700 }; 685 };
701 686
702 timer@b120000 { 687 timer@b120000 {
703 compatible = "arm,armv 688 compatible = "arm,armv7-timer-mem";
704 reg = <0x0b120000 0x10 689 reg = <0x0b120000 0x1000>;
705 #address-cells = <1>; 690 #address-cells = <1>;
706 #size-cells = <1>; 691 #size-cells = <1>;
707 ranges; 692 ranges;
708 693
709 frame@b120000 { 694 frame@b120000 {
710 reg = <0x0b121 695 reg = <0x0b121000 0x1000>,
711 <0x0b122 696 <0x0b122000 0x1000>;
712 frame-number = 697 frame-number = <0>;
713 interrupts = < 698 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
714 < 699 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
715 }; 700 };
716 701
717 frame@b123000 { 702 frame@b123000 {
718 reg = <0x0b123 703 reg = <0x0b123000 0x1000>;
719 frame-number = 704 frame-number = <1>;
720 interrupts = < 705 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
721 status = "disa 706 status = "disabled";
722 }; 707 };
723 708
724 frame@b124000 { 709 frame@b124000 {
725 reg = <0x0b124 710 reg = <0x0b124000 0x1000>;
726 frame-number = 711 frame-number = <2>;
727 interrupts = < 712 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
728 status = "disa 713 status = "disabled";
729 }; 714 };
730 715
731 frame@b125000 { 716 frame@b125000 {
732 reg = <0x0b125 717 reg = <0x0b125000 0x1000>;
733 frame-number = 718 frame-number = <3>;
734 interrupts = < 719 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
735 status = "disa 720 status = "disabled";
736 }; 721 };
737 722
738 frame@b126000 { 723 frame@b126000 {
739 reg = <0x0b126 724 reg = <0x0b126000 0x1000>;
740 frame-number = 725 frame-number = <4>;
741 interrupts = < 726 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
742 status = "disa 727 status = "disabled";
743 }; 728 };
744 729
745 frame@b127000 { 730 frame@b127000 {
746 reg = <0x0b127 731 reg = <0x0b127000 0x1000>;
747 frame-number = 732 frame-number = <5>;
748 interrupts = < 733 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
749 status = "disa 734 status = "disabled";
750 }; 735 };
751 736
752 frame@b128000 { 737 frame@b128000 {
753 reg = <0x0b128 738 reg = <0x0b128000 0x1000>;
754 frame-number = 739 frame-number = <6>;
755 interrupts = < 740 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
756 status = "disa 741 status = "disabled";
757 }; 742 };
758 }; 743 };
759 }; 744 };
760 745
761 thermal-zones { 746 thermal-zones {
762 nss-top-thermal { 747 nss-top-thermal {
>> 748 polling-delay-passive = <0>;
>> 749 polling-delay = <0>;
763 thermal-sensors = <&ts 750 thermal-sensors = <&tsens 3>;
764 751
765 trips { 752 trips {
766 nss-top-critic 753 nss-top-critical {
767 temper 754 temperature = <125000>;
768 hyster 755 hysteresis = <1000>;
769 type = 756 type = "critical";
770 }; 757 };
771 }; 758 };
772 }; 759 };
773 760
774 ubi-0-thermal { 761 ubi-0-thermal {
>> 762 polling-delay-passive = <0>;
>> 763 polling-delay = <0>;
775 thermal-sensors = <&ts 764 thermal-sensors = <&tsens 4>;
776 765
777 trips { 766 trips {
778 ubi_0-critical 767 ubi_0-critical {
779 temper 768 temperature = <125000>;
780 hyster 769 hysteresis = <1000>;
781 type = 770 type = "critical";
782 }; 771 };
783 }; 772 };
784 }; 773 };
785 774
786 ubi-1-thermal { 775 ubi-1-thermal {
>> 776 polling-delay-passive = <0>;
>> 777 polling-delay = <0>;
787 thermal-sensors = <&ts 778 thermal-sensors = <&tsens 5>;
788 779
789 trips { 780 trips {
790 ubi_1-critical 781 ubi_1-critical {
791 temper 782 temperature = <125000>;
792 hyster 783 hysteresis = <1000>;
793 type = 784 type = "critical";
794 }; 785 };
795 }; 786 };
796 }; 787 };
797 788
798 ubi-2-thermal { 789 ubi-2-thermal {
>> 790 polling-delay-passive = <0>;
>> 791 polling-delay = <0>;
799 thermal-sensors = <&ts 792 thermal-sensors = <&tsens 6>;
800 793
801 trips { 794 trips {
802 ubi_2-critical 795 ubi_2-critical {
803 temper 796 temperature = <125000>;
804 hyster 797 hysteresis = <1000>;
805 type = 798 type = "critical";
806 }; 799 };
807 }; 800 };
808 }; 801 };
809 802
810 ubi-3-thermal { 803 ubi-3-thermal {
>> 804 polling-delay-passive = <0>;
>> 805 polling-delay = <0>;
811 thermal-sensors = <&ts 806 thermal-sensors = <&tsens 7>;
812 807
813 trips { 808 trips {
814 ubi_3-critical 809 ubi_3-critical {
815 temper 810 temperature = <125000>;
816 hyster 811 hysteresis = <1000>;
817 type = 812 type = "critical";
818 }; 813 };
819 }; 814 };
820 }; 815 };
821 816
822 cpuss0-thermal { 817 cpuss0-thermal {
>> 818 polling-delay-passive = <0>;
>> 819 polling-delay = <0>;
823 thermal-sensors = <&ts 820 thermal-sensors = <&tsens 8>;
824 821
825 trips { 822 trips {
826 cpu-critical { 823 cpu-critical {
827 temper 824 temperature = <125000>;
828 hyster 825 hysteresis = <1000>;
829 type = 826 type = "critical";
830 }; 827 };
831 }; 828 };
832 }; 829 };
833 830
834 cpuss1-thermal { 831 cpuss1-thermal {
>> 832 polling-delay-passive = <0>;
>> 833 polling-delay = <0>;
835 thermal-sensors = <&ts 834 thermal-sensors = <&tsens 9>;
836 835
837 trips { 836 trips {
838 cpu-critical { 837 cpu-critical {
839 temper 838 temperature = <125000>;
840 hyster 839 hysteresis = <1000>;
841 type = 840 type = "critical";
842 }; 841 };
843 }; 842 };
844 }; 843 };
845 844
846 cpu0-thermal { 845 cpu0-thermal {
>> 846 polling-delay-passive = <0>;
>> 847 polling-delay = <0>;
847 thermal-sensors = <&ts 848 thermal-sensors = <&tsens 10>;
848 849
849 trips { 850 trips {
850 cpu0_crit: cpu 851 cpu0_crit: cpu-critical {
851 temper 852 temperature = <120000>;
852 hyster 853 hysteresis = <10000>;
853 type = 854 type = "critical";
854 }; 855 };
855 856
856 cpu0_alert: cp 857 cpu0_alert: cpu-passive {
857 temper 858 temperature = <110000>;
858 hyster 859 hysteresis = <1000>;
859 type = 860 type = "passive";
860 }; 861 };
861 }; 862 };
862 863
863 cooling-maps { 864 cooling-maps {
864 map0 { 865 map0 {
865 trip = 866 trip = <&cpu0_alert>;
866 coolin 867 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
867 868 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
868 869 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
869 870 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
870 }; 871 };
871 }; 872 };
872 }; 873 };
873 874
874 cpu1-thermal { 875 cpu1-thermal {
>> 876 polling-delay-passive = <0>;
>> 877 polling-delay = <0>;
875 thermal-sensors = <&ts 878 thermal-sensors = <&tsens 11>;
876 879
877 trips { 880 trips {
878 cpu1_crit: cpu 881 cpu1_crit: cpu-critical {
879 temper 882 temperature = <120000>;
880 hyster 883 hysteresis = <10000>;
881 type = 884 type = "critical";
882 }; 885 };
883 886
884 cpu1_alert: cp 887 cpu1_alert: cpu-passive {
885 temper 888 temperature = <110000>;
886 hyster 889 hysteresis = <1000>;
887 type = 890 type = "passive";
888 }; 891 };
889 }; 892 };
890 893
891 cooling-maps { 894 cooling-maps {
892 map0 { 895 map0 {
893 trip = 896 trip = <&cpu1_alert>;
894 coolin 897 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
895 898 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
896 899 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
897 900 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
898 }; 901 };
899 }; 902 };
900 }; 903 };
901 904
902 cpu2-thermal { 905 cpu2-thermal {
>> 906 polling-delay-passive = <0>;
>> 907 polling-delay = <0>;
903 thermal-sensors = <&ts 908 thermal-sensors = <&tsens 12>;
904 909
905 trips { 910 trips {
906 cpu2_crit: cpu 911 cpu2_crit: cpu-critical {
907 temper 912 temperature = <120000>;
908 hyster 913 hysteresis = <10000>;
909 type = 914 type = "critical";
910 }; 915 };
911 916
912 cpu2_alert: cp 917 cpu2_alert: cpu-passive {
913 temper 918 temperature = <110000>;
914 hyster 919 hysteresis = <1000>;
915 type = 920 type = "passive";
916 }; 921 };
917 }; 922 };
918 923
919 cooling-maps { 924 cooling-maps {
920 map0 { 925 map0 {
921 trip = 926 trip = <&cpu2_alert>;
922 coolin 927 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
923 928 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
924 929 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
925 930 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
926 }; 931 };
927 }; 932 };
928 }; 933 };
929 934
930 cpu3-thermal { 935 cpu3-thermal {
>> 936 polling-delay-passive = <0>;
>> 937 polling-delay = <0>;
931 thermal-sensors = <&ts 938 thermal-sensors = <&tsens 13>;
932 939
933 trips { 940 trips {
934 cpu3_crit: cpu 941 cpu3_crit: cpu-critical {
935 temper 942 temperature = <120000>;
936 hyster 943 hysteresis = <10000>;
937 type = 944 type = "critical";
938 }; 945 };
939 946
940 cpu3_alert: cp 947 cpu3_alert: cpu-passive {
941 temper 948 temperature = <110000>;
942 hyster 949 hysteresis = <1000>;
943 type = 950 type = "passive";
944 }; 951 };
945 }; 952 };
946 953
947 cooling-maps { 954 cooling-maps {
948 map0 { 955 map0 {
949 trip = 956 trip = <&cpu3_alert>;
950 coolin 957 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
951 958 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
952 959 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
953 960 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
954 }; 961 };
955 }; 962 };
956 }; 963 };
957 964
958 wcss-phyb-thermal { 965 wcss-phyb-thermal {
>> 966 polling-delay-passive = <0>;
>> 967 polling-delay = <0>;
959 thermal-sensors = <&ts 968 thermal-sensors = <&tsens 14>;
960 969
961 trips { 970 trips {
962 wcss_phyb-crit 971 wcss_phyb-critical {
963 temper 972 temperature = <125000>;
964 hyster 973 hysteresis = <1000>;
965 type = 974 type = "critical";
966 }; 975 };
967 }; 976 };
968 }; 977 };
969 978
970 top-glue-thermal { 979 top-glue-thermal {
>> 980 polling-delay-passive = <0>;
>> 981 polling-delay = <0>;
971 thermal-sensors = <&ts 982 thermal-sensors = <&tsens 15>;
972 983
973 trips { 984 trips {
974 top_glue-criti 985 top_glue-critical {
975 temper 986 temperature = <125000>;
976 hyster 987 hysteresis = <1000>;
977 type = 988 type = "critical";
978 }; 989 };
979 }; 990 };
980 }; 991 };
981 }; 992 };
982 993
983 timer { 994 timer {
984 compatible = "arm,armv8-timer" 995 compatible = "arm,armv8-timer";
985 interrupts = <GIC_PPI 2 (GIC_C 996 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
986 <GIC_PPI 3 (GIC_C 997 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
987 <GIC_PPI 4 (GIC_C 998 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
988 <GIC_PPI 1 (GIC_C 999 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
989 }; 1000 };
990 }; 1001 };
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