1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2013-2015, The Linux Foundati
4 * Copyright (c) 2020-2023, Linaro Limited
5 */
6
7 #include <dt-bindings/clock/qcom,gcc-msm8939.h
8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/interconnect/qcom,msm893
10 #include <dt-bindings/interrupt-controller/arm
11 #include <dt-bindings/power/qcom-rpmpd.h>
12 #include <dt-bindings/reset/qcom,gcc-msm8939.h
13 #include <dt-bindings/soc/qcom,apr.h>
14 #include <dt-bindings/thermal/thermal.h>
15
16 / {
17 interrupt-parent = <&intc>;
18
19 /*
20 * Stock LK wants address-cells/size-c
21 * A number of our drivers want addres
22 * hence the disparity between top-lev
23 */
24 #address-cells = <2>;
25 #size-cells = <2>;
26
27 clocks {
28 xo_board: xo-board {
29 compatible = "fixed-cl
30 #clock-cells = <0>;
31 clock-frequency = <192
32 };
33
34 sleep_clk: sleep-clk {
35 compatible = "fixed-cl
36 #clock-cells = <0>;
37 clock-frequency = <327
38 };
39 };
40
41 cpus {
42 #address-cells = <1>;
43 #size-cells = <0>;
44
45 CPU0: cpu@100 {
46 compatible = "arm,cort
47 device_type = "cpu";
48 enable-method = "spin-
49 reg = <0x100>;
50 next-level-cache = <&L
51 qcom,acc = <&acc0>;
52 qcom,saw = <&saw0>;
53 cpu-idle-states = <&CP
54 clocks = <&apcs1_mbox>
55 #cooling-cells = <2>;
56 L2_1: l2-cache {
57 compatible = "
58 cache-level =
59 cache-unified;
60 };
61 };
62
63 CPU1: cpu@101 {
64 compatible = "arm,cort
65 device_type = "cpu";
66 enable-method = "spin-
67 reg = <0x101>;
68 next-level-cache = <&L
69 qcom,acc = <&acc1>;
70 qcom,saw = <&saw1>;
71 cpu-idle-states = <&CP
72 clocks = <&apcs1_mbox>
73 #cooling-cells = <2>;
74 };
75
76 CPU2: cpu@102 {
77 compatible = "arm,cort
78 device_type = "cpu";
79 enable-method = "spin-
80 reg = <0x102>;
81 next-level-cache = <&L
82 qcom,acc = <&acc2>;
83 qcom,saw = <&saw2>;
84 cpu-idle-states = <&CP
85 clocks = <&apcs1_mbox>
86 #cooling-cells = <2>;
87 };
88
89 CPU3: cpu@103 {
90 compatible = "arm,cort
91 device_type = "cpu";
92 enable-method = "spin-
93 reg = <0x103>;
94 next-level-cache = <&L
95 qcom,acc = <&acc3>;
96 qcom,saw = <&saw3>;
97 cpu-idle-states = <&CP
98 clocks = <&apcs1_mbox>
99 #cooling-cells = <2>;
100 };
101
102 CPU4: cpu@0 {
103 compatible = "arm,cort
104 device_type = "cpu";
105 enable-method = "spin-
106 reg = <0x0>;
107 qcom,acc = <&acc4>;
108 qcom,saw = <&saw4>;
109 cpu-idle-states = <&CP
110 clocks = <&apcs0_mbox>
111 #cooling-cells = <2>;
112 next-level-cache = <&L
113 L2_0: l2-cache {
114 compatible = "
115 cache-level =
116 cache-unified;
117 };
118 };
119
120 CPU5: cpu@1 {
121 compatible = "arm,cort
122 device_type = "cpu";
123 enable-method = "spin-
124 reg = <0x1>;
125 next-level-cache = <&L
126 qcom,acc = <&acc5>;
127 qcom,saw = <&saw5>;
128 cpu-idle-states = <&CP
129 clocks = <&apcs0_mbox>
130 #cooling-cells = <2>;
131 };
132
133 CPU6: cpu@2 {
134 compatible = "arm,cort
135 device_type = "cpu";
136 enable-method = "spin-
137 reg = <0x2>;
138 next-level-cache = <&L
139 qcom,acc = <&acc6>;
140 qcom,saw = <&saw6>;
141 cpu-idle-states = <&CP
142 clocks = <&apcs0_mbox>
143 #cooling-cells = <2>;
144 };
145
146 CPU7: cpu@3 {
147 compatible = "arm,cort
148 device_type = "cpu";
149 enable-method = "spin-
150 reg = <0x3>;
151 next-level-cache = <&L
152 qcom,acc = <&acc7>;
153 qcom,saw = <&saw7>;
154 cpu-idle-states = <&CP
155 clocks = <&apcs0_mbox>
156 #cooling-cells = <2>;
157 };
158
159 idle-states {
160 CPU_SLEEP_0: cpu-sleep
161 compatible = "
162 entry-latency-
163 exit-latency-u
164 min-residency-
165 local-timer-st
166 };
167 };
168 };
169
170 /*
171 * MSM8939 has a big.LITTLE heterogene
172 * consisting of two clusters of four
173 * LITTLE cluster runs at 1.0-1.2GHz,
174 * at 1.5-1.7GHz.
175 *
176 * The enable method used here is spin
177 * of a 2nd stage boot shim such as lk
178 * spin-table, the downstream non-psci
179 * default msm8916/msm8936/msm8939 wil
180 */
181 cpu-map {
182 /* LITTLE (efficiency) cluster
183 cluster0 {
184 core0 {
185 cpu = <&CPU4>;
186 };
187
188 core1 {
189 cpu = <&CPU5>;
190 };
191
192 core2 {
193 cpu = <&CPU6>;
194 };
195
196 core3 {
197 cpu = <&CPU7>;
198 };
199 };
200
201 /* big (performance) cluster *
202 /* Boot CPU is cluster 1 core
203 cluster1 {
204 core0 {
205 cpu = <&CPU0>;
206 };
207
208 core1 {
209 cpu = <&CPU1>;
210 };
211
212 core2 {
213 cpu = <&CPU2>;
214 };
215
216 core3 {
217 cpu = <&CPU3>;
218 };
219 };
220 };
221
222 firmware {
223 scm: scm {
224 compatible = "qcom,scm
225 clocks = <&gcc GCC_CRY
226 <&gcc GCC_CRY
227 <&gcc GCC_CRY
228 clock-names = "core",
229 #reset-cells = <1>;
230
231 qcom,dload-mode = <&tc
232 };
233 };
234
235 memory@80000000 {
236 device_type = "memory";
237 /* We expect the bootloader to
238 reg = <0x0 0x80000000 0x0 0x0>
239 };
240
241 pmu {
242 compatible = "arm,cortex-a53-p
243 interrupts = <GIC_PPI 7 (GIC_C
244 };
245
246 rpm: remoteproc {
247 compatible = "qcom,msm8936-rpm
248
249 smd-edge {
250 interrupts = <GIC_SPI
251 qcom,ipc = <&apcs1_mbo
252 qcom,smd-edge = <15>;
253
254 rpm_requests: rpm-requ
255 compatible = "
256 qcom,smd-chann
257
258 rpmcc: clock-c
259 compat
260 #clock
261 clock-
262 clocks
263 };
264
265 rpmpd: power-c
266 compat
267 #power
268 operat
269
270 rpmpd_
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296 };
297 };
298 };
299 };
300 };
301
302 reserved-memory {
303 #address-cells = <2>;
304 #size-cells = <2>;
305 ranges;
306
307 tz-apps@86000000 {
308 reg = <0x0 0x86000000
309 no-map;
310 };
311
312 smem@86300000 {
313 compatible = "qcom,sme
314 reg = <0x0 0x86300000
315 no-map;
316
317 hwlocks = <&tcsr_mutex
318 qcom,rpm-msg-ram = <&r
319 };
320
321 hypervisor@86400000 {
322 reg = <0x0 0x86400000
323 no-map;
324 };
325
326 tz@86500000 {
327 reg = <0x0 0x86500000
328 no-map;
329 };
330
331 reserved@86680000 {
332 reg = <0x0 0x86680000
333 no-map;
334 };
335
336 rmtfs@86700000 {
337 compatible = "qcom,rmt
338 reg = <0x0 0x86700000
339 no-map;
340
341 qcom,client-id = <1>;
342 };
343
344 rfsa@867e0000 {
345 reg = <0x0 0x867e0000
346 no-map;
347 };
348
349 mpss_mem: mpss@86800000 {
350 /*
351 * The memory region f
352 * relocatable and cou
353 * However, many firmw
354 * loaded to some spec
355 * define reliable all
356 *
357 * alignment = <0x0 0x
358 * alloc-ranges = <0x0
359 */
360 reg = <0x0 0x86800000
361 no-map;
362 status = "disabled";
363 };
364
365 wcnss_mem: wcnss {
366 size = <0x0 0x600000>;
367 alignment = <0x0 0x100
368 alloc-ranges = <0x0 0x
369 no-map;
370 status = "disabled";
371 };
372
373 venus_mem: venus {
374 size = <0x0 0x500000>;
375 alignment = <0x0 0x100
376 alloc-ranges = <0x0 0x
377 no-map;
378 status = "disabled";
379 };
380
381 mba_mem: mba {
382 size = <0x0 0x100000>;
383 alignment = <0x0 0x100
384 alloc-ranges = <0x0 0x
385 no-map;
386 status = "disabled";
387 };
388 };
389
390 smp2p-hexagon {
391 compatible = "qcom,smp2p";
392 qcom,smem = <435>, <428>;
393
394 interrupts = <GIC_SPI 27 IRQ_T
395
396 mboxes = <&apcs1_mbox 14>;
397
398 qcom,local-pid = <0>;
399 qcom,remote-pid = <1>;
400
401 hexagon_smp2p_out: master-kern
402 qcom,entry-name = "mas
403
404 #qcom,smem-state-cells
405 };
406
407 hexagon_smp2p_in: slave-kernel
408 qcom,entry-name = "sla
409
410 interrupt-controller;
411 #interrupt-cells = <2>
412 };
413 };
414
415 smp2p-wcnss {
416 compatible = "qcom,smp2p";
417 qcom,smem = <451>, <431>;
418
419 interrupts = <GIC_SPI 143 IRQ_
420
421 mboxes = <&apcs1_mbox 18>;
422
423 qcom,local-pid = <0>;
424 qcom,remote-pid = <4>;
425
426 wcnss_smp2p_in: slave-kernel {
427 qcom,entry-name = "sla
428
429 interrupt-controller;
430 #interrupt-cells = <2>
431 };
432
433 wcnss_smp2p_out: master-kernel
434 qcom,entry-name = "mas
435
436 #qcom,smem-state-cells
437 };
438 };
439
440 smsm {
441 compatible = "qcom,smsm";
442
443 #address-cells = <1>;
444 #size-cells = <0>;
445
446 mboxes = <0>, <&apcs1_mbox 13>
447
448 apps_smsm: apps@0 {
449 reg = <0>;
450
451 #qcom,smem-state-cells
452 };
453
454 hexagon_smsm: hexagon@1 {
455 reg = <1>;
456 interrupts = <GIC_SPI
457
458 interrupt-controller;
459 #interrupt-cells = <2>
460 };
461
462 wcnss_smsm: wcnss@6 {
463 reg = <6>;
464 interrupts = <GIC_SPI
465
466 interrupt-controller;
467 #interrupt-cells = <2>
468 };
469 };
470
471 soc: soc@0 {
472 compatible = "simple-bus";
473 #address-cells = <1>;
474 #size-cells = <1>;
475 ranges = <0 0 0 0xffffffff>;
476
477 rng@22000 {
478 compatible = "qcom,prn
479 reg = <0x00022000 0x20
480 clocks = <&gcc GCC_PRN
481 clock-names = "core";
482 };
483
484 qfprom: qfprom@5c000 {
485 compatible = "qcom,msm
486 reg = <0x0005c000 0x10
487 #address-cells = <1>;
488 #size-cells = <1>;
489
490 tsens_base1: base1@a0
491 reg = <0xa0 0x
492 bits = <0 8>;
493 };
494
495 tsens_s6_p1: s6-p1@a1
496 reg = <0xa1 0x
497 bits = <0 6>;
498 };
499
500 tsens_s6_p2: s6-p2@a1
501 reg = <0xa1 0x
502 bits = <6 6>;
503 };
504
505 tsens_s7_p1: s7-p1@a2
506 reg = <0xa2 0x
507 bits = <4 6>;
508 };
509
510 tsens_s7_p2: s7-p2@a3
511 reg = <0xa3 0x
512 bits = <2 6>;
513 };
514
515 tsens_s8_p1: s8-p1@a4
516 reg = <0xa4 0x
517 bits = <0 6>;
518 };
519
520 tsens_s8_p2: s8-p2@a4
521 reg = <0xa4 0x
522 bits = <6 6>;
523 };
524
525 tsens_s9_p1: s9-p1@a5
526 reg = <0xa5 0x
527 bits = <4 6>;
528 };
529
530 tsens_s9_p2: s9-p2@a6
531 reg = <0xa6 0x
532 bits = <2 6>;
533 };
534
535 tsens_base2: base2@a7
536 reg = <0xa7 0x
537 bits = <0 8>;
538 };
539
540 tsens_mode: mode@d0 {
541 reg = <0xd0 0x
542 bits = <0 3>;
543 };
544
545 tsens_s0_p1: s0-p1@d0
546 reg = <0xd0 0x
547 bits = <3 6>;
548 };
549
550 tsens_s0_p2: s0-p1@d1
551 reg = <0xd1 0x
552 bits = <1 6>;
553 };
554
555 tsens_s1_p1: s1-p1@d1
556 reg = <0xd1 0x
557 bits = <7 6>;
558 };
559
560 tsens_s1_p2: s1-p2@d2
561 reg = <0xd2 0x
562 bits = <5 6>;
563 };
564
565 tsens_s2_p1: s2-p1@d3
566 reg = <0xd3 0x
567 bits = <3 6>;
568 };
569
570 tsens_s2_p2: s2-p2@d4
571 reg = <0xd4 0x
572 bits = <1 6>;
573 };
574
575 tsens_s3_p1: s3-p1@d4
576 reg = <0xd4 0x
577 bits = <7 6>;
578 };
579
580 tsens_s3_p2: s3-p2@d5
581 reg = <0xd5 0x
582 bits = <5 6>;
583 };
584
585 tsens_s5_p1: s5-p1@d6
586 reg = <0xd6 0x
587 bits = <3 6>;
588 };
589
590 tsens_s5_p2: s5-p2@d7
591 reg = <0xd7 0x
592 bits = <1 6>;
593 };
594 };
595
596 rpm_msg_ram: sram@60000 {
597 compatible = "qcom,rpm
598 reg = <0x00060000 0x80
599 };
600
601 bimc: interconnect@400000 {
602 compatible = "qcom,msm
603 reg = <0x00400000 0x62
604 #interconnect-cells =
605 };
606
607 tsens: thermal-sensor@4a9000 {
608 compatible = "qcom,msm
609 reg = <0x004a9000 0x10
610 <0x004a8000 0x10
611 nvmem-cells = <&tsens_
612 <&tsens_
613 <&tsens_
614 <&tsens_
615 <&tsens_
616 <&tsens_
617 <&tsens_
618 <&tsens_
619 <&tsens_
620 <&tsens_
621 <&tsens_
622 nvmem-cell-names = "mo
623 "ba
624 "s0
625 "s1
626 "s2
627 "s3
628 "s5
629 "s6
630 "s7
631 "s8
632 "s9
633 #qcom,sensors = <9>;
634 interrupts = <GIC_SPI
635 interrupt-names = "upl
636 #thermal-sensor-cells
637 };
638
639 restart@4ab000 {
640 compatible = "qcom,psh
641 reg = <0x004ab000 0x4>
642 };
643
644 pcnoc: interconnect@500000 {
645 compatible = "qcom,msm
646 reg = <0x00500000 0x11
647 #interconnect-cells =
648 };
649
650 snoc: interconnect@580000 {
651 compatible = "qcom,msm
652 reg = <0x00580000 0x14
653 #interconnect-cells =
654
655 snoc_mm: interconnect-
656 compatible = "
657 #interconnect-
658 };
659 };
660
661 tlmm: pinctrl@1000000 {
662 compatible = "qcom,msm
663 reg = <0x01000000 0x30
664 interrupts = <GIC_SPI
665 gpio-controller;
666 gpio-ranges = <&tlmm 0
667 #gpio-cells = <2>;
668 interrupt-controller;
669 #interrupt-cells = <2>
670
671 blsp_i2c1_default: bls
672 pins = "gpio2"
673 function = "bl
674 drive-strength
675 bias-disable;
676 };
677
678 blsp_i2c1_sleep: blsp-
679 pins = "gpio2"
680 function = "gp
681 drive-strength
682 bias-disable;
683 };
684
685 blsp_i2c2_default: bls
686 pins = "gpio6"
687 function = "bl
688 drive-strength
689 bias-disable;
690 };
691
692 blsp_i2c2_sleep: blsp-
693 pins = "gpio6"
694 function = "gp
695 drive-strength
696 bias-disable;
697 };
698
699 blsp_i2c3_default: bls
700 pins = "gpio10
701 function = "bl
702 drive-strength
703 bias-disable;
704 };
705
706 blsp_i2c3_sleep: blsp-
707 pins = "gpio10
708 function = "gp
709 drive-strength
710 bias-disable;
711 };
712
713 blsp_i2c4_default: bls
714 pins = "gpio14
715 function = "bl
716 drive-strength
717 bias-disable;
718 };
719
720 blsp_i2c4_sleep: blsp-
721 pins = "gpio14
722 function = "gp
723 drive-strength
724 bias-disable;
725 };
726
727 blsp_i2c5_default: bls
728 pins = "gpio18
729 function = "bl
730 drive-strength
731 bias-disable;
732 };
733
734 blsp_i2c5_sleep: blsp-
735 pins = "gpio18
736 function = "gp
737 drive-strength
738 bias-disable;
739 };
740
741 blsp_i2c6_default: bls
742 pins = "gpio22
743 function = "bl
744 drive-strength
745 bias-disable;
746 };
747
748 blsp_i2c6_sleep: blsp-
749 pins = "gpio22
750 function = "gp
751 drive-strength
752 bias-disable;
753 };
754
755 blsp_spi1_default: bls
756 spi-pins {
757 pins =
758 functi
759 drive-
760 bias-d
761 };
762
763 cs-pins {
764 pins =
765 functi
766 drive-
767 bias-d
768 output
769 };
770 };
771
772 blsp_spi1_sleep: blsp-
773 pins = "gpio0"
774 function = "gp
775 drive-strength
776 bias-pull-down
777 };
778
779 blsp_spi2_default: bls
780 spi-pins {
781 pins =
782 functi
783 drive-
784 bias-d
785 };
786
787 cs-pins {
788 pins =
789 functi
790 drive-
791 bias-d
792 output
793 };
794 };
795
796 blsp_spi2_sleep: blsp-
797 pins = "gpio4"
798 function = "gp
799 drive-strength
800 bias-pull-down
801 };
802
803 blsp_spi3_default: bls
804 spi-pins {
805 pins =
806 functi
807 drive-
808 bias-d
809 };
810
811 cs-pins {
812 pins =
813 functi
814 drive-
815 bias-d
816 output
817 };
818 };
819
820 blsp_spi3_sleep: blsp-
821 pins = "gpio8"
822 function = "gp
823 drive-strength
824 bias-pull-down
825 };
826
827 blsp_spi4_default: bls
828 spi-pins {
829 pins =
830 functi
831 drive-
832 bias-d
833 };
834
835 cs-pins {
836 pins =
837 functi
838 drive-
839 bias-d
840 output
841 };
842 };
843
844 blsp_spi4_sleep: blsp-
845 pins = "gpio12
846 function = "gp
847 drive-strength
848 bias-pull-down
849 };
850
851 blsp_spi5_default: bls
852 spi-pins {
853 pins =
854 functi
855 drive-
856 bias-d
857 };
858
859 cs-pins {
860 pins =
861 functi
862 drive-
863 bias-d
864 output
865 };
866 };
867
868 blsp_spi5_sleep: blsp-
869 pins = "gpio16
870 function = "gp
871 drive-strength
872 bias-pull-down
873 };
874
875 blsp_spi6_default: bls
876 spi-pins {
877 pins =
878 functi
879 drive-
880 bias-d
881 };
882
883 cs-pins {
884 pins =
885 functi
886 drive-
887 bias-d
888 output
889 };
890 };
891
892 blsp_spi6_sleep: blsp-
893 pins = "gpio20
894 function = "gp
895 drive-strength
896 bias-pull-down
897 };
898
899 blsp_uart1_default: bl
900 pins = "gpio0"
901 function = "bl
902 drive-strength
903 bias-disable;
904 };
905
906 blsp_uart1_sleep: blsp
907 pins = "gpio0"
908 function = "gp
909 drive-strength
910 bias-pull-down
911 };
912
913 blsp_uart2_default: bl
914 pins = "gpio4"
915 function = "bl
916 drive-strength
917 bias-disable;
918 };
919
920 blsp_uart2_sleep: blsp
921 pins = "gpio4"
922 function = "gp
923 drive-strength
924 bias-pull-down
925 };
926
927 camera_front_default:
928 pwdn-pins {
929 pins =
930 functi
931 drive-
932 bias-d
933 };
934
935 rst-pins {
936 pins =
937 functi
938 drive-
939 bias-d
940 };
941
942 mclk1-pins {
943 pins =
944 functi
945 drive-
946 bias-d
947 };
948 };
949
950 camera_rear_default: c
951 pwdn-pins {
952 pins =
953 functi
954 drive-
955 bias-d
956 };
957
958 rst-pins {
959 pins =
960 functi
961 drive-
962 bias-d
963 };
964
965 mclk0-pins {
966 pins =
967 functi
968 drive-
969 bias-d
970 };
971 };
972
973 cci0_default: cci0-def
974 pins = "gpio29
975 function = "cc
976 drive-strength
977 bias-disable;
978 };
979
980 cdc_dmic_default: cdc-
981 clk-pins {
982 pins =
983 functi
984 drive-
985 };
986
987 data-pins {
988 pins =
989 functi
990 drive-
991 };
992 };
993
994 cdc_dmic_sleep: cdc-dm
995 clk-pins {
996 pins =
997 functi
998 drive-
999 bias-d
1000 };
1001
1002 data-pins {
1003 pins
1004 funct
1005 drive
1006 bias-
1007 };
1008 };
1009
1010 cdc_pdm_default: cdc-
1011 pins = "gpio6
1012 "gpio6
1013 function = "c
1014 drive-strengt
1015 bias-disable;
1016 };
1017
1018 cdc_pdm_sleep: cdc-pd
1019 pins = "gpio6
1020 "gpio6
1021 function = "c
1022 drive-strengt
1023 bias-pull-dow
1024 };
1025
1026 pri_mi2s_default: mi2
1027 pins = "gpio1
1028 function = "p
1029 drive-strengt
1030 bias-disable;
1031 };
1032
1033 pri_mi2s_sleep: mi2s-
1034 pins = "gpio1
1035 function = "p
1036 drive-strengt
1037 bias-disable;
1038 };
1039
1040 pri_mi2s_mclk_default
1041 pins = "gpio1
1042 function = "p
1043 drive-strengt
1044 bias-disable;
1045 };
1046
1047 pri_mi2s_mclk_sleep:
1048 pins = "gpio1
1049 function = "p
1050 drive-strengt
1051 bias-disable;
1052 };
1053
1054 pri_mi2s_ws_default:
1055 pins = "gpio1
1056 function = "p
1057 drive-strengt
1058 bias-disable;
1059 };
1060
1061 pri_mi2s_ws_sleep: mi
1062 pins = "gpio1
1063 function = "p
1064 drive-strengt
1065 bias-disable;
1066 };
1067
1068 sec_mi2s_default: mi2
1069 pins = "gpio1
1070 function = "s
1071 drive-strengt
1072 bias-disable;
1073 };
1074
1075 sec_mi2s_sleep: mi2s-
1076 pins = "gpio1
1077 function = "s
1078 drive-strengt
1079 bias-disable;
1080 };
1081
1082 sdc1_default: sdc1-de
1083 clk-pins {
1084 pins
1085 bias-
1086 drive
1087 };
1088
1089 cmd-pins {
1090 pins
1091 bias-
1092 drive
1093 };
1094
1095 data-pins {
1096 pins
1097 bias-
1098 drive
1099 };
1100 };
1101
1102 sdc1_sleep: sdc1-slee
1103 clk-pins {
1104 pins
1105 bias-
1106 drive
1107 };
1108
1109 cmd-pins {
1110 pins
1111 bias-
1112 drive
1113 };
1114
1115 data-pins {
1116 pins
1117 bias-
1118 drive
1119 };
1120 };
1121
1122 sdc2_default: sdc2-de
1123 clk-pins {
1124 pins
1125 bias-
1126 drive
1127 };
1128
1129 cmd-pins {
1130 pins
1131 bias-
1132 drive
1133 };
1134
1135 data-pins {
1136 pins
1137 bias-
1138 drive
1139 };
1140 };
1141
1142 sdc2_sleep: sdc2-slee
1143 clk-pins {
1144 pins
1145 bias-
1146 drive
1147 };
1148
1149 cmd-pins {
1150 pins
1151 bias-
1152 drive
1153 };
1154
1155 data-pins {
1156 pins
1157 bias-
1158 drive
1159 };
1160 };
1161
1162 wcss_wlan_default: wc
1163 pins = "gpio4
1164 function = "w
1165 drive-strengt
1166 bias-pull-up;
1167 };
1168 };
1169
1170 gcc: clock-controller@1800000
1171 compatible = "qcom,gc
1172 reg = <0x01800000 0x8
1173 clocks = <&rpmcc RPM_
1174 <&sleep_clk>
1175 <&mdss_dsi0_
1176 <&mdss_dsi0_
1177 <0>,
1178 <0>,
1179 <0>;
1180 clock-names = "xo",
1181 "sleep_
1182 "dsi0pl
1183 "dsi0pl
1184 "ext_mc
1185 "ext_pr
1186 "ext_se
1187 #clock-cells = <1>;
1188 #reset-cells = <1>;
1189 #power-domain-cells =
1190 };
1191
1192 tcsr_mutex: hwlock@1905000 {
1193 compatible = "qcom,tc
1194 reg = <0x01905000 0x2
1195 #hwlock-cells = <1>;
1196 };
1197
1198 tcsr: syscon@1937000 {
1199 compatible = "qcom,tc
1200 reg = <0x01937000 0x3
1201 };
1202
1203 mdss: display-subsystem@1a000
1204 compatible = "qcom,md
1205 reg = <0x01a00000 0x1
1206 <0x01ac8000 0x3
1207 reg-names = "mdss_phy
1208
1209 interrupts = <GIC_SPI
1210 interrupt-controller;
1211
1212 clocks = <&gcc GCC_MD
1213 <&gcc GCC_MD
1214 <&gcc GCC_MD
1215 clock-names = "iface"
1216 "bus",
1217 "vsync"
1218
1219 power-domains = <&gcc
1220
1221 #address-cells = <1>;
1222 #size-cells = <1>;
1223 #interrupt-cells = <1
1224 ranges;
1225
1226 status = "disabled";
1227
1228 mdss_mdp: display-con
1229 compatible =
1230 reg = <0x01a0
1231 reg-names = "
1232
1233 interrupt-par
1234 interrupts =
1235
1236 clocks = <&gc
1237 <&gc
1238 <&gc
1239 <&gc
1240 clock-names =
1241
1242
1243
1244
1245 iommus = <&ap
1246
1247 interconnects
1248
1249 interconnect-
1250
1251 ports {
1252 #addr
1253 #size
1254
1255 port@
1256
1257
1258
1259
1260 };
1261
1262 port@
1263
1264
1265
1266
1267 };
1268 };
1269 };
1270
1271 mdss_dsi0: dsi@1a9800
1272 compatible =
1273
1274 reg = <0x01a9
1275 reg-names = "
1276
1277 interrupt-par
1278 interrupts =
1279
1280 clocks = <&gc
1281 <&gc
1282 <&gc
1283 <&gc
1284 <&gc
1285 <&gc
1286 clock-names =
1287
1288
1289
1290
1291
1292 assigned-cloc
1293
1294 assigned-cloc
1295
1296
1297 phys = <&mdss
1298 status = "dis
1299
1300 #address-cell
1301 #size-cells =
1302
1303 ports {
1304 #addr
1305 #size
1306
1307 port@
1308
1309
1310
1311
1312 };
1313
1314 port@
1315
1316
1317
1318 };
1319 };
1320 };
1321
1322 mdss_dsi0_phy: phy@1a
1323 compatible =
1324 reg = <0x01a9
1325 <0x01a9
1326 <0x01a9
1327 reg-names = "
1328 "
1329 "
1330
1331 clocks = <&gc
1332 <&rp
1333 clock-names =
1334
1335 #clock-cells
1336 #phy-cells =
1337 status = "dis
1338 };
1339
1340 mdss_dsi1: dsi@1aa000
1341 compatible =
1342
1343 reg = <0x01aa
1344 reg-names = "
1345
1346 interrupt-par
1347 interrupts =
1348
1349 clocks = <&gc
1350 <&gc
1351 <&gc
1352 <&gc
1353 <&gc
1354 <&gc
1355 clock-names =
1356
1357
1358
1359
1360
1361 assigned-cloc
1362
1363 assigned-cloc
1364
1365 phys = <&mdss
1366 status = "dis
1367
1368 ports {
1369 #addr
1370 #size
1371
1372 port@
1373
1374
1375
1376
1377 };
1378
1379 port@
1380
1381
1382
1383 };
1384 };
1385 };
1386
1387 mdss_dsi1_phy: phy@1a
1388 compatible =
1389 reg = <0x01aa
1390 <0x01aa
1391 <0x01aa
1392 reg-names = "
1393 "
1394 "
1395
1396 clocks = <&gc
1397 <&rp
1398 clock-names =
1399
1400 #clock-cells
1401 #phy-cells =
1402 status = "dis
1403 };
1404 };
1405
1406 gpu: gpu@1c00000 {
1407 compatible = "qcom,ad
1408 reg = <0x01c00000 0x1
1409 reg-names = "kgsl_3d0
1410 interrupts = <GIC_SPI
1411 interrupt-names = "kg
1412 clock-names = "core",
1413 "iface"
1414 "mem",
1415 "mem_if
1416 "alt_me
1417 "gfx3d"
1418 "rbbmti
1419 clocks = <&gcc GCC_OX
1420 <&gcc GCC_OX
1421 <&gcc GCC_OX
1422 <&gcc GCC_BI
1423 <&gcc GCC_BI
1424 <&gcc GFX3D_
1425 <&gcc GCC_OX
1426 power-domains = <&gcc
1427 operating-points-v2 =
1428 iommus = <&gpu_iommu
1429 #cooling-cells = <2>;
1430
1431 status = "disabled";
1432
1433 opp_table: opp-table
1434 compatible =
1435
1436 opp-550000000
1437 opp-h
1438 };
1439
1440 opp-465000000
1441 opp-h
1442 };
1443
1444 opp-400000000
1445 opp-h
1446 };
1447
1448 opp-220000000
1449 opp-h
1450 };
1451
1452 opp-19200000
1453 opp-h
1454 };
1455 };
1456 };
1457
1458 apps_iommu: iommu@1ef0000 {
1459 compatible = "qcom,ms
1460 reg = <0x01ef0000 0x3
1461 ranges = <0 0x01e2000
1462 clocks = <&gcc GCC_SM
1463 <&gcc GCC_AP
1464 clock-names = "iface"
1465 #address-cells = <1>;
1466 #size-cells = <1>;
1467 #iommu-cells = <1>;
1468 qcom,iommu-secure-id
1469
1470 /* mdp_0: */
1471 iommu-ctx@4000 {
1472 compatible =
1473 reg = <0x4000
1474 interrupts =
1475 };
1476
1477 /* venus_ns: */
1478 iommu-ctx@5000 {
1479 compatible =
1480 reg = <0x5000
1481 interrupts =
1482 };
1483 };
1484
1485 gpu_iommu: iommu@1f08000 {
1486 compatible = "qcom,ms
1487 ranges = <0 0x1f08000
1488 clocks = <&gcc GCC_SM
1489 <&gcc GCC_GF
1490 <&gcc GCC_GF
1491 clock-names = "iface"
1492 #address-cells = <1>;
1493 #size-cells = <1>;
1494 #iommu-cells = <1>;
1495 qcom,iommu-secure-id
1496
1497 /* gfx3d_user: */
1498 iommu-ctx@1000 {
1499 compatible =
1500 reg = <0x1000
1501 interrupts =
1502 };
1503
1504 /* gfx3d_priv: */
1505 iommu-ctx@2000 {
1506 compatible =
1507 reg = <0x2000
1508 interrupts =
1509 };
1510 };
1511
1512 spmi_bus: spmi@200f000 {
1513 compatible = "qcom,sp
1514 reg = <0x0200f000 0x0
1515 <0x02400000 0x4
1516 <0x02c00000 0x4
1517 <0x03800000 0x2
1518 <0x0200a000 0x0
1519 reg-names = "core", "
1520 interrupt-names = "pe
1521 interrupts = <GIC_SPI
1522 qcom,ee = <0>;
1523 qcom,channel = <0>;
1524 #address-cells = <2>;
1525 #size-cells = <0>;
1526 interrupt-controller;
1527 #interrupt-cells = <4
1528 };
1529
1530 bam_dmux_dma: dma-controller@
1531 compatible = "qcom,ba
1532 reg = <0x04044000 0x1
1533 interrupts = <GIC_SPI
1534 #dma-cells = <1>;
1535 qcom,ee = <0>;
1536
1537 num-channels = <6>;
1538 qcom,num-ees = <1>;
1539 qcom,powered-remotely
1540
1541 status = "disabled";
1542 };
1543
1544 mpss: remoteproc@4080000 {
1545 compatible = "qcom,ms
1546 reg = <0x04080000 0x1
1547 reg-names = "qdsp6",
1548 interrupts-extended =
1549
1550
1551
1552
1553 interrupt-names = "wd
1554 "fa
1555 "re
1556 "ha
1557 "st
1558 clocks = <&gcc GCC_MS
1559 <&gcc GCC_MS
1560 <&gcc GCC_BO
1561 <&rpmcc RPM_
1562 clock-names = "iface"
1563 "bus",
1564 "mem",
1565 "xo";
1566 power-domains = <&rpm
1567 <&rpm
1568 power-domain-names =
1569 qcom,smem-states = <&
1570 qcom,smem-state-names
1571 resets = <&scm 0>;
1572 reset-names = "mss_re
1573 qcom,halt-regs = <&tc
1574 status = "disabled";
1575
1576 bam_dmux: bam-dmux {
1577 compatible =
1578
1579 interrupt-par
1580 interrupts =
1581 interrupt-nam
1582
1583 qcom,smem-sta
1584 qcom,smem-sta
1585
1586 dmas = <&bam_
1587 dma-names = "
1588
1589 status = "dis
1590 };
1591
1592 mba {
1593 memory-region
1594 };
1595
1596 mpss {
1597 memory-region
1598 };
1599
1600 smd-edge {
1601 interrupts =
1602
1603 qcom,smd-edge
1604 mboxes = <&ap
1605 qcom,remote-p
1606
1607 label = "hexa
1608
1609 apr: apr {
1610 compa
1611 qcom,
1612 qcom,
1613 #addr
1614 #size
1615 statu
1616
1617 q6cor
1618
1619
1620 };
1621
1622 q6afe
1623
1624
1625
1626
1627
1628
1629
1630
1631
1632 };
1633
1634 q6asm
1635
1636
1637
1638
1639
1640
1641
1642
1643
1644 };
1645
1646 q6adm
1647
1648
1649
1650
1651
1652
1653
1654 };
1655 };
1656 };
1657 };
1658
1659 sound: sound@7702000 {
1660 compatible = "qcom,ap
1661 reg = <0x07702000 0x4
1662 <0x07702004 0x4
1663 reg-names = "mic-iomu
1664 status = "disabled";
1665 };
1666
1667 lpass: audio-controller@77080
1668 compatible = "qcom,ap
1669 reg = <0x07708000 0x1
1670 reg-names = "lpass-lp
1671 interrupts = <GIC_SPI
1672 interrupt-names = "lp
1673 clocks = <&gcc GCC_UL
1674 <&gcc GCC_UL
1675 <&gcc GCC_UL
1676 <&gcc GCC_UL
1677 <&gcc GCC_UL
1678 <&gcc GCC_UL
1679 <&gcc GCC_UL
1680 clock-names = "ahbix-
1681 "mi2s-b
1682 "mi2s-b
1683 "mi2s-b
1684 "mi2s-b
1685 "pcnoc-
1686 "pcnoc-
1687 #sound-dai-cells = <1
1688 #address-cells = <1>;
1689 #size-cells = <0>;
1690 status = "disabled";
1691 };
1692
1693 lpass_codec: audio-codec@771c
1694 compatible = "qcom,ms
1695 reg = <0x0771c000 0x4
1696 clocks = <&gcc GCC_UL
1697 <&gcc GCC_CO
1698 clock-names = "ahbix-
1699 #sound-dai-cells = <1
1700 status = "disabled";
1701 };
1702
1703 sdhc_1: mmc@7824900 {
1704 compatible = "qcom,ms
1705 reg = <0x07824900 0x1
1706 reg-names = "hc", "co
1707
1708 interrupts = <GIC_SPI
1709 <GIC_SPI
1710 interrupt-names = "hc
1711 clocks = <&gcc GCC_SD
1712 <&gcc GCC_SD
1713 <&rpmcc RPM_
1714 clock-names = "iface"
1715 resets = <&gcc GCC_SD
1716 pinctrl-0 = <&sdc1_de
1717 pinctrl-1 = <&sdc1_sl
1718 pinctrl-names = "defa
1719 mmc-ddr-1_8v;
1720 bus-width = <8>;
1721 non-removable;
1722 status = "disabled";
1723 };
1724
1725 sdhc_2: mmc@7864900 {
1726 compatible = "qcom,ms
1727 reg = <0x07864900 0x1
1728 reg-names = "hc", "co
1729
1730 interrupts = <GIC_SPI
1731 <GIC_SPI
1732 interrupt-names = "hc
1733 clocks = <&gcc GCC_SD
1734 <&gcc GCC_SD
1735 <&rpmcc RPM_
1736 clock-names = "iface"
1737 resets = <&gcc GCC_SD
1738 pinctrl-0 = <&sdc2_de
1739 pinctrl-1 = <&sdc2_sl
1740 pinctrl-names = "defa
1741 bus-width = <4>;
1742 status = "disabled";
1743 };
1744
1745 blsp_dma: dma-controller@7884
1746 compatible = "qcom,ba
1747 reg = <0x07884000 0x2
1748 interrupts = <GIC_SPI
1749 clocks = <&gcc GCC_BL
1750 clock-names = "bam_cl
1751 #dma-cells = <1>;
1752 qcom,ee = <0>;
1753 qcom,controlled-remot
1754 };
1755
1756 blsp_uart1: serial@78af000 {
1757 compatible = "qcom,ms
1758 reg = <0x078af000 0x2
1759 interrupts = <GIC_SPI
1760 clocks = <&gcc GCC_BL
1761 clock-names = "core",
1762 dmas = <&blsp_dma 0>,
1763 dma-names = "tx", "rx
1764 pinctrl-0 = <&blsp_ua
1765 pinctrl-1 = <&blsp_ua
1766 pinctrl-names = "defa
1767 status = "disabled";
1768 };
1769
1770 blsp_uart2: serial@78b0000 {
1771 compatible = "qcom,ms
1772 reg = <0x078b0000 0x2
1773 interrupts = <GIC_SPI
1774 clocks = <&gcc GCC_BL
1775 clock-names = "core",
1776 dmas = <&blsp_dma 2>,
1777 dma-names = "tx", "rx
1778 pinctrl-0 = <&blsp_ua
1779 pinctrl-1 = <&blsp_ua
1780 pinctrl-names = "defa
1781 status = "disabled";
1782 };
1783
1784 blsp_i2c1: i2c@78b5000 {
1785 compatible = "qcom,i2
1786 reg = <0x078b5000 0x5
1787 interrupts = <GIC_SPI
1788 clocks = <&gcc GCC_BL
1789 <&gcc GCC_BL
1790 clock-names = "core",
1791 dmas = <&blsp_dma 4>,
1792 dma-names = "tx", "rx
1793 pinctrl-0 = <&blsp_i2
1794 pinctrl-1 = <&blsp_i2
1795 pinctrl-names = "defa
1796 #address-cells = <1>;
1797 #size-cells = <0>;
1798 status = "disabled";
1799 };
1800
1801 blsp_spi1: spi@78b5000 {
1802 compatible = "qcom,sp
1803 reg = <0x078b5000 0x5
1804 interrupts = <GIC_SPI
1805 clocks = <&gcc GCC_BL
1806 <&gcc GCC_BL
1807 clock-names = "core",
1808 dmas = <&blsp_dma 4>,
1809 dma-names = "tx", "rx
1810 pinctrl-0 = <&blsp_sp
1811 pinctrl-1 = <&blsp_sp
1812 pinctrl-names = "defa
1813 #address-cells = <1>;
1814 #size-cells = <0>;
1815 status = "disabled";
1816 };
1817
1818 blsp_i2c2: i2c@78b6000 {
1819 compatible = "qcom,i2
1820 reg = <0x078b6000 0x5
1821 interrupts = <GIC_SPI
1822 clocks = <&gcc GCC_BL
1823 <&gcc GCC_BL
1824 clock-names = "core",
1825 dmas = <&blsp_dma 6>,
1826 dma-names = "tx", "rx
1827 pinctrl-0 = <&blsp_i2
1828 pinctrl-1 = <&blsp_i2
1829 pinctrl-names = "defa
1830 #address-cells = <1>;
1831 #size-cells = <0>;
1832 status = "disabled";
1833 };
1834
1835 blsp_spi2: spi@78b6000 {
1836 compatible = "qcom,sp
1837 reg = <0x078b6000 0x5
1838 interrupts = <GIC_SPI
1839 clocks = <&gcc GCC_BL
1840 <&gcc GCC_BL
1841 clock-names = "core",
1842 dmas = <&blsp_dma 6>,
1843 dma-names = "tx", "rx
1844 pinctrl-0 = <&blsp_sp
1845 pinctrl-1 = <&blsp_sp
1846 pinctrl-names = "defa
1847 #address-cells = <1>;
1848 #size-cells = <0>;
1849 status = "disabled";
1850 };
1851
1852 blsp_i2c3: i2c@78b7000 {
1853 compatible = "qcom,i2
1854 reg = <0x078b7000 0x5
1855 interrupts = <GIC_SPI
1856 clocks = <&gcc GCC_BL
1857 <&gcc GCC_BL
1858 clock-names = "core",
1859 dmas = <&blsp_dma 8>,
1860 dma-names = "tx", "rx
1861 pinctrl-0 = <&blsp_i2
1862 pinctrl-1 = <&blsp_i2
1863 pinctrl-names = "defa
1864 #address-cells = <1>;
1865 #size-cells = <0>;
1866 status = "disabled";
1867 };
1868
1869 blsp_spi3: spi@78b7000 {
1870 compatible = "qcom,sp
1871 reg = <0x078b7000 0x5
1872 interrupts = <GIC_SPI
1873 clocks = <&gcc GCC_BL
1874 <&gcc GCC_BL
1875 clock-names = "core",
1876 dmas = <&blsp_dma 8>,
1877 dma-names = "tx", "rx
1878 pinctrl-0 = <&blsp_sp
1879 pinctrl-1 = <&blsp_sp
1880 pinctrl-names = "defa
1881 #address-cells = <1>;
1882 #size-cells = <0>;
1883 status = "disabled";
1884 };
1885
1886 blsp_i2c4: i2c@78b8000 {
1887 compatible = "qcom,i2
1888 reg = <0x078b8000 0x5
1889 interrupts = <GIC_SPI
1890 clocks = <&gcc GCC_BL
1891 <&gcc GCC_BL
1892 clock-names = "core",
1893 dmas = <&blsp_dma 10>
1894 dma-names = "tx", "rx
1895 pinctrl-0 = <&blsp_i2
1896 pinctrl-1 = <&blsp_i2
1897 pinctrl-names = "defa
1898 #address-cells = <1>;
1899 #size-cells = <0>;
1900 status = "disabled";
1901 };
1902
1903 blsp_spi4: spi@78b8000 {
1904 compatible = "qcom,sp
1905 reg = <0x078b8000 0x5
1906 interrupts = <GIC_SPI
1907 clocks = <&gcc GCC_BL
1908 <&gcc GCC_BL
1909 clock-names = "core",
1910 dmas = <&blsp_dma 10>
1911 dma-names = "tx", "rx
1912 pinctrl-0 = <&blsp_sp
1913 pinctrl-1 = <&blsp_sp
1914 pinctrl-names = "defa
1915 #address-cells = <1>;
1916 #size-cells = <0>;
1917 status = "disabled";
1918 };
1919
1920 blsp_i2c5: i2c@78b9000 {
1921 compatible = "qcom,i2
1922 reg = <0x078b9000 0x5
1923 interrupts = <GIC_SPI
1924 clocks = <&gcc GCC_BL
1925 <&gcc GCC_BL
1926 clock-names = "core",
1927 dmas = <&blsp_dma 12>
1928 dma-names = "tx", "rx
1929 pinctrl-0 = <&blsp_i2
1930 pinctrl-1 = <&blsp_i2
1931 pinctrl-names = "defa
1932 #address-cells = <1>;
1933 #size-cells = <0>;
1934 status = "disabled";
1935 };
1936
1937 blsp_spi5: spi@78b9000 {
1938 compatible = "qcom,sp
1939 reg = <0x078b9000 0x5
1940 interrupts = <GIC_SPI
1941 clocks = <&gcc GCC_BL
1942 <&gcc GCC_BL
1943 clock-names = "core",
1944 dmas = <&blsp_dma 12>
1945 dma-names = "tx", "rx
1946 pinctrl-0 = <&blsp_sp
1947 pinctrl-1 = <&blsp_sp
1948 pinctrl-names = "defa
1949 #address-cells = <1>;
1950 #size-cells = <0>;
1951 status = "disabled";
1952 };
1953
1954 blsp_i2c6: i2c@78ba000 {
1955 compatible = "qcom,i2
1956 reg = <0x078ba000 0x5
1957 interrupts = <GIC_SPI
1958 clocks = <&gcc GCC_BL
1959 <&gcc GCC_BL
1960 clock-names = "core",
1961 dmas = <&blsp_dma 14>
1962 dma-names = "tx", "rx
1963 pinctrl-0 = <&blsp_i2
1964 pinctrl-1 = <&blsp_i2
1965 pinctrl-names = "defa
1966 #address-cells = <1>;
1967 #size-cells = <0>;
1968 status = "disabled";
1969 };
1970
1971 blsp_spi6: spi@78ba000 {
1972 compatible = "qcom,sp
1973 reg = <0x078ba000 0x5
1974 interrupts = <GIC_SPI
1975 clocks = <&gcc GCC_BL
1976 <&gcc GCC_BL
1977 clock-names = "core",
1978 dmas = <&blsp_dma 14>
1979 dma-names = "tx", "rx
1980 pinctrl-0 = <&blsp_sp
1981 pinctrl-1 = <&blsp_sp
1982 pinctrl-names = "defa
1983 #address-cells = <1>;
1984 #size-cells = <0>;
1985 status = "disabled";
1986 };
1987
1988 usb: usb@78d9000 {
1989 compatible = "qcom,ci
1990 reg = <0x078d9000 0x2
1991 <0x078d9200 0x2
1992 interrupts = <GIC_SPI
1993 <GIC_SPI
1994 clocks = <&gcc GCC_US
1995 <&gcc GCC_US
1996 clock-names = "iface"
1997 assigned-clocks = <&g
1998 assigned-clock-rates
1999 resets = <&gcc GCC_US
2000 reset-names = "core";
2001 #reset-cells = <1>;
2002 phy_type = "ulpi";
2003 dr_mode = "otg";
2004 adp-disable;
2005 hnp-disable;
2006 srp-disable;
2007 ahb-burst-config = <0
2008 phy-names = "usb-phy"
2009 phys = <&usb_hs_phy>;
2010 status = "disabled";
2011
2012 ulpi {
2013 usb_hs_phy: p
2014 compa
2015
2016 clock
2017
2018 clock
2019 reset
2020 reset
2021 #phy-
2022 qcom,
2023
2024
2025
2026 };
2027 };
2028 };
2029
2030 wcnss: remoteproc@a204000 {
2031 compatible = "qcom,pr
2032 interrupts-extended =
2033
2034
2035
2036
2037 interrupt-names = "wd
2038 "fa
2039 "re
2040 "ha
2041 "st
2042 reg = <0x0a204000 0x2
2043 <0x0a202000 0x1
2044 <0x0a21b000 0x3
2045 reg-names = "ccu", "d
2046
2047 memory-region = <&wcn
2048
2049 power-domains = <&rpm
2050 <&rpm
2051 power-domain-names =
2052
2053 qcom,smem-states = <&
2054 qcom,smem-state-names
2055
2056 pinctrl-names = "defa
2057 pinctrl-0 = <&wcss_wl
2058
2059 status = "disabled";
2060
2061 wcnss_iris: iris {
2062 /* Separate c
2063 clocks = <&rp
2064 clock-names =
2065 };
2066
2067 smd-edge {
2068 interrupts =
2069 mboxes = <&ap
2070 qcom,smd-edge
2071 qcom,remote-p
2072
2073 label = "pron
2074
2075 wcnss {
2076 compa
2077 qcom,
2078
2079 qcom,
2080
2081 wcnss
2082
2083 };
2084
2085 wcnss
2086
2087
2088
2089
2090
2091
2092
2093
2094
2095
2096 };
2097 };
2098 };
2099 };
2100
2101 intc: interrupt-controller@b0
2102 compatible = "qcom,ms
2103 reg = <0x0b000000 0x1
2104 <0x0b001000 0x1
2105 interrupt-controller;
2106 #interrupt-cells = <3
2107 interrupts = <GIC_PPI
2108 };
2109
2110 apcs1_mbox: mailbox@b011000 {
2111 compatible = "qcom,ms
2112 reg = <0x0b011000 0x1
2113 clocks = <&a53pll_c1>
2114 clock-names = "pll",
2115 #clock-cells = <0>;
2116 assigned-clocks = <&a
2117 assigned-clock-rates
2118 #mbox-cells = <1>;
2119 };
2120
2121 a53pll_c1: clock@b016000 {
2122 compatible = "qcom,ms
2123 reg = <0x0b016000 0x4
2124 #clock-cells = <0>;
2125 };
2126
2127 acc0: clock-controller@b08800
2128 compatible = "qcom,kp
2129 reg = <0x0b088000 0x1
2130 };
2131
2132 saw0: power-manager@b089000 {
2133 compatible = "qcom,ms
2134 reg = <0x0b089000 0x1
2135 };
2136
2137 acc1: clock-controller@b09800
2138 compatible = "qcom,kp
2139 reg = <0x0b098000 0x1
2140 };
2141
2142 saw1: power-manager@b099000 {
2143 compatible = "qcom,ms
2144 reg = <0x0b099000 0x1
2145 };
2146
2147 acc2: clock-controller@b0a800
2148 compatible = "qcom,kp
2149 reg = <0x0b0a8000 0x1
2150 };
2151
2152 saw2: power-manager@b0a9000 {
2153 compatible = "qcom,ms
2154 reg = <0x0b0a9000 0x1
2155 };
2156
2157 acc3: clock-controller@b0b800
2158 compatible = "qcom,kp
2159 reg = <0x0b0b8000 0x1
2160 };
2161
2162 saw3: power-manager@b0b9000 {
2163 compatible = "qcom,ms
2164 reg = <0x0b0b9000 0x1
2165 };
2166
2167 apcs0_mbox: mailbox@b111000 {
2168 compatible = "qcom,ms
2169 reg = <0x0b111000 0x1
2170 clocks = <&a53pll_c0>
2171 clock-names = "pll",
2172 #clock-cells = <0>;
2173 #mbox-cells = <1>;
2174 };
2175
2176 a53pll_c0: clock@b116000 {
2177 compatible = "qcom,ms
2178 reg = <0x0b116000 0x4
2179 #clock-cells = <0>;
2180 };
2181
2182 timer@b120000 {
2183 compatible = "arm,arm
2184 reg = <0x0b120000 0x1
2185 #address-cells = <1>;
2186 #size-cells = <1>;
2187 ranges;
2188 /* Necessary because
2189 clock-frequency = <19
2190
2191 frame@b121000 {
2192 reg = <0x0b12
2193 <0x0b12
2194 interrupts =
2195
2196 frame-number
2197 };
2198
2199 frame@b123000 {
2200 reg = <0x0b12
2201 interrupts =
2202 frame-number
2203 status = "dis
2204 };
2205
2206 frame@b124000 {
2207 reg = <0x0b12
2208 interrupts =
2209 frame-number
2210 status = "dis
2211 };
2212
2213 frame@b125000 {
2214 reg = <0x0b12
2215 interrupts =
2216 frame-number
2217 status = "dis
2218 };
2219
2220 frame@b126000 {
2221 reg = <0x0b12
2222 interrupts =
2223 frame-number
2224 status = "dis
2225 };
2226
2227 frame@b127000 {
2228 reg = <0x0b12
2229 interrupts =
2230 frame-number
2231 status = "dis
2232 };
2233
2234 frame@b128000 {
2235 reg = <0x0b12
2236 interrupts =
2237 frame-number
2238 status = "dis
2239 };
2240 };
2241
2242 acc4: clock-controller@b18800
2243 compatible = "qcom,kp
2244 reg = <0x0b188000 0x1
2245 };
2246
2247 saw4: power-manager@b189000 {
2248 compatible = "qcom,ms
2249 reg = <0x0b189000 0x1
2250 };
2251
2252 acc5: clock-controller@b19800
2253 compatible = "qcom,kp
2254 reg = <0x0b198000 0x1
2255 };
2256
2257 saw5: power-manager@b199000 {
2258 compatible = "qcom,ms
2259 reg = <0x0b199000 0x1
2260 };
2261
2262 acc6: clock-controller@b1a800
2263 compatible = "qcom,kp
2264 reg = <0x0b1a8000 0x1
2265 };
2266
2267 saw6: power-manager@b1a9000 {
2268 compatible = "qcom,ms
2269 reg = <0x0b1a9000 0x1
2270 };
2271
2272 acc7: clock-controller@b1b800
2273 compatible = "qcom,kp
2274 reg = <0x0b1b8000 0x1
2275 };
2276
2277 saw7: power-manager@b1b9000 {
2278 compatible = "qcom,ms
2279 reg = <0x0b1b9000 0x1
2280 };
2281
2282 a53pll_cci: clock@b1d0000 {
2283 compatible = "qcom,ms
2284 reg = <0x0b1d0000 0x4
2285 #clock-cells = <0>;
2286 };
2287
2288 apcs2: mailbox@b1d1000 {
2289 compatible = "qcom,ms
2290 reg = <0x0b1d1000 0x1
2291 clocks = <&a53pll_cci
2292 clock-names = "pll",
2293 #clock-cells = <0>;
2294 #mbox-cells = <1>;
2295 };
2296 };
2297
2298 thermal_zones: thermal-zones {
2299 cpu0-thermal {
2300 polling-delay-passive
2301
2302 thermal-sensors = <&t
2303
2304 trips {
2305 cpu0_alert: t
2306 tempe
2307 hyste
2308 type
2309 };
2310
2311 cpu0_crit: tr
2312 tempe
2313 hyste
2314 type
2315 };
2316 };
2317
2318 cooling-maps {
2319 map0 {
2320 trip
2321 cooli
2322
2323
2324
2325 };
2326 };
2327 };
2328
2329 cpu1-thermal {
2330 polling-delay-passive
2331
2332 thermal-sensors = <&t
2333
2334 trips {
2335 cpu1_alert: t
2336 tempe
2337 hyste
2338 type
2339 };
2340
2341 cpu1_crit: tr
2342 tempe
2343 hyste
2344 type
2345 };
2346 };
2347
2348 cooling-maps {
2349 map0 {
2350 trip
2351 cooli
2352
2353
2354
2355 };
2356 };
2357 };
2358
2359 cpu2-thermal {
2360 polling-delay-passive
2361
2362 thermal-sensors = <&t
2363
2364 trips {
2365 cpu2_alert: t
2366 tempe
2367 hyste
2368 type
2369 };
2370
2371 cpu2_crit: tr
2372 tempe
2373 hyste
2374 type
2375 };
2376 };
2377
2378 cooling-maps {
2379 map0 {
2380 trip
2381 cooli
2382
2383
2384
2385 };
2386 };
2387 };
2388
2389 cpu3-thermal {
2390 polling-delay-passive
2391
2392 thermal-sensors = <&t
2393
2394 trips {
2395 cpu3_alert: t
2396 tempe
2397 hyste
2398 type
2399 };
2400
2401 cpu3_crit: tr
2402 tempe
2403 hyste
2404 type
2405 };
2406 };
2407
2408 cooling-maps {
2409 map0 {
2410 trip
2411 cooli
2412
2413
2414
2415 };
2416 };
2417 };
2418
2419 cpu4567-thermal {
2420 polling-delay-passive
2421
2422 thermal-sensors = <&t
2423
2424 trips {
2425 cpu4567_alert
2426 tempe
2427 hyste
2428 type
2429 };
2430
2431 cpu4567_crit:
2432 tempe
2433 hyste
2434 type
2435 };
2436 };
2437
2438 cooling-maps {
2439 map0 {
2440 trip
2441 cooli
2442
2443
2444
2445 };
2446 };
2447 };
2448
2449 gpu-thermal {
2450 polling-delay-passive
2451
2452 thermal-sensors = <&t
2453
2454 cooling-maps {
2455 map0 {
2456 trip
2457 cooli
2458 };
2459 };
2460
2461 trips {
2462 gpu_alert0: t
2463 tempe
2464 hyste
2465 type
2466 };
2467
2468 gpu_crit: gpu
2469 tempe
2470 hyste
2471 type
2472 };
2473 };
2474 };
2475
2476 modem1-thermal {
2477 polling-delay-passive
2478
2479 thermal-sensors = <&t
2480
2481 trips {
2482 modem1_alert0
2483 tempe
2484 hyste
2485 type
2486 };
2487 };
2488 };
2489
2490 modem2-thermal {
2491 polling-delay-passive
2492
2493 thermal-sensors = <&t
2494
2495 trips {
2496 modem2_alert0
2497 tempe
2498 hyste
2499 type
2500 };
2501 };
2502 };
2503
2504 camera-thermal {
2505 polling-delay-passive
2506
2507 thermal-sensors = <&t
2508
2509 trips {
2510 cam_alert0: t
2511 tempe
2512 hyste
2513 type
2514 };
2515 };
2516 };
2517 };
2518
2519 timer {
2520 compatible = "arm,armv8-timer
2521 interrupts = <GIC_PPI 2 (GIC_
2522 <GIC_PPI 3 (GIC_
2523 <GIC_PPI 4 (GIC_
2524 <GIC_PPI 1 (GIC_
2525 };
2526 };
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