1 // SPDX-License-Identifier: GPL-2.0-only 1 // SPDX-License-Identifier: GPL-2.0-only
2 /* 2 /*
3 * Copyright (c) 2013-2015, The Linux Foundati 3 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2020-2023, Linaro Limited 4 * Copyright (c) 2020-2023, Linaro Limited
5 */ 5 */
6 6
7 #include <dt-bindings/clock/qcom,gcc-msm8939.h 7 #include <dt-bindings/clock/qcom,gcc-msm8939.h>
8 #include <dt-bindings/clock/qcom,rpmcc.h> 8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/interconnect/qcom,msm893 9 #include <dt-bindings/interconnect/qcom,msm8939.h>
10 #include <dt-bindings/interrupt-controller/arm 10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/power/qcom-rpmpd.h> 11 #include <dt-bindings/power/qcom-rpmpd.h>
12 #include <dt-bindings/reset/qcom,gcc-msm8939.h 12 #include <dt-bindings/reset/qcom,gcc-msm8939.h>
13 #include <dt-bindings/soc/qcom,apr.h> <<
14 #include <dt-bindings/thermal/thermal.h> 13 #include <dt-bindings/thermal/thermal.h>
15 14
16 / { 15 / {
17 interrupt-parent = <&intc>; 16 interrupt-parent = <&intc>;
18 17
19 /* 18 /*
20 * Stock LK wants address-cells/size-c 19 * Stock LK wants address-cells/size-cells = 2
21 * A number of our drivers want addres 20 * A number of our drivers want address/size cells = 1
22 * hence the disparity between top-lev 21 * hence the disparity between top-level and /soc below.
23 */ 22 */
24 #address-cells = <2>; 23 #address-cells = <2>;
25 #size-cells = <2>; 24 #size-cells = <2>;
26 25
27 clocks { 26 clocks {
28 xo_board: xo-board { 27 xo_board: xo-board {
29 compatible = "fixed-cl 28 compatible = "fixed-clock";
30 #clock-cells = <0>; 29 #clock-cells = <0>;
31 clock-frequency = <192 30 clock-frequency = <19200000>;
32 }; 31 };
33 32
34 sleep_clk: sleep-clk { 33 sleep_clk: sleep-clk {
35 compatible = "fixed-cl 34 compatible = "fixed-clock";
36 #clock-cells = <0>; 35 #clock-cells = <0>;
37 clock-frequency = <327 36 clock-frequency = <32768>;
38 }; 37 };
39 }; 38 };
40 39
41 cpus { 40 cpus {
42 #address-cells = <1>; 41 #address-cells = <1>;
43 #size-cells = <0>; 42 #size-cells = <0>;
44 43
45 CPU0: cpu@100 { 44 CPU0: cpu@100 {
46 compatible = "arm,cort 45 compatible = "arm,cortex-a53";
47 device_type = "cpu"; 46 device_type = "cpu";
48 enable-method = "spin- 47 enable-method = "spin-table";
49 reg = <0x100>; 48 reg = <0x100>;
50 next-level-cache = <&L 49 next-level-cache = <&L2_1>;
51 qcom,acc = <&acc0>; 50 qcom,acc = <&acc0>;
52 qcom,saw = <&saw0>; 51 qcom,saw = <&saw0>;
53 cpu-idle-states = <&CP 52 cpu-idle-states = <&CPU_SLEEP_0>;
54 clocks = <&apcs1_mbox> 53 clocks = <&apcs1_mbox>;
55 #cooling-cells = <2>; 54 #cooling-cells = <2>;
56 L2_1: l2-cache { 55 L2_1: l2-cache {
57 compatible = " 56 compatible = "cache";
58 cache-level = 57 cache-level = <2>;
59 cache-unified; 58 cache-unified;
60 }; 59 };
61 }; 60 };
62 61
63 CPU1: cpu@101 { 62 CPU1: cpu@101 {
64 compatible = "arm,cort 63 compatible = "arm,cortex-a53";
65 device_type = "cpu"; 64 device_type = "cpu";
66 enable-method = "spin- 65 enable-method = "spin-table";
67 reg = <0x101>; 66 reg = <0x101>;
68 next-level-cache = <&L 67 next-level-cache = <&L2_1>;
69 qcom,acc = <&acc1>; 68 qcom,acc = <&acc1>;
70 qcom,saw = <&saw1>; 69 qcom,saw = <&saw1>;
71 cpu-idle-states = <&CP 70 cpu-idle-states = <&CPU_SLEEP_0>;
72 clocks = <&apcs1_mbox> 71 clocks = <&apcs1_mbox>;
73 #cooling-cells = <2>; 72 #cooling-cells = <2>;
74 }; 73 };
75 74
76 CPU2: cpu@102 { 75 CPU2: cpu@102 {
77 compatible = "arm,cort 76 compatible = "arm,cortex-a53";
78 device_type = "cpu"; 77 device_type = "cpu";
79 enable-method = "spin- 78 enable-method = "spin-table";
80 reg = <0x102>; 79 reg = <0x102>;
81 next-level-cache = <&L 80 next-level-cache = <&L2_1>;
82 qcom,acc = <&acc2>; 81 qcom,acc = <&acc2>;
83 qcom,saw = <&saw2>; 82 qcom,saw = <&saw2>;
84 cpu-idle-states = <&CP 83 cpu-idle-states = <&CPU_SLEEP_0>;
85 clocks = <&apcs1_mbox> 84 clocks = <&apcs1_mbox>;
86 #cooling-cells = <2>; 85 #cooling-cells = <2>;
87 }; 86 };
88 87
89 CPU3: cpu@103 { 88 CPU3: cpu@103 {
90 compatible = "arm,cort 89 compatible = "arm,cortex-a53";
91 device_type = "cpu"; 90 device_type = "cpu";
92 enable-method = "spin- 91 enable-method = "spin-table";
93 reg = <0x103>; 92 reg = <0x103>;
94 next-level-cache = <&L 93 next-level-cache = <&L2_1>;
95 qcom,acc = <&acc3>; 94 qcom,acc = <&acc3>;
96 qcom,saw = <&saw3>; 95 qcom,saw = <&saw3>;
97 cpu-idle-states = <&CP 96 cpu-idle-states = <&CPU_SLEEP_0>;
98 clocks = <&apcs1_mbox> 97 clocks = <&apcs1_mbox>;
99 #cooling-cells = <2>; 98 #cooling-cells = <2>;
100 }; 99 };
101 100
102 CPU4: cpu@0 { 101 CPU4: cpu@0 {
103 compatible = "arm,cort 102 compatible = "arm,cortex-a53";
104 device_type = "cpu"; 103 device_type = "cpu";
105 enable-method = "spin- 104 enable-method = "spin-table";
106 reg = <0x0>; 105 reg = <0x0>;
107 qcom,acc = <&acc4>; 106 qcom,acc = <&acc4>;
108 qcom,saw = <&saw4>; 107 qcom,saw = <&saw4>;
109 cpu-idle-states = <&CP 108 cpu-idle-states = <&CPU_SLEEP_0>;
110 clocks = <&apcs0_mbox> 109 clocks = <&apcs0_mbox>;
111 #cooling-cells = <2>; 110 #cooling-cells = <2>;
112 next-level-cache = <&L 111 next-level-cache = <&L2_0>;
113 L2_0: l2-cache { 112 L2_0: l2-cache {
114 compatible = " 113 compatible = "cache";
115 cache-level = 114 cache-level = <2>;
116 cache-unified; 115 cache-unified;
117 }; 116 };
118 }; 117 };
119 118
120 CPU5: cpu@1 { 119 CPU5: cpu@1 {
121 compatible = "arm,cort 120 compatible = "arm,cortex-a53";
122 device_type = "cpu"; 121 device_type = "cpu";
123 enable-method = "spin- 122 enable-method = "spin-table";
124 reg = <0x1>; 123 reg = <0x1>;
125 next-level-cache = <&L 124 next-level-cache = <&L2_0>;
126 qcom,acc = <&acc5>; 125 qcom,acc = <&acc5>;
127 qcom,saw = <&saw5>; 126 qcom,saw = <&saw5>;
128 cpu-idle-states = <&CP 127 cpu-idle-states = <&CPU_SLEEP_0>;
129 clocks = <&apcs0_mbox> 128 clocks = <&apcs0_mbox>;
130 #cooling-cells = <2>; 129 #cooling-cells = <2>;
131 }; 130 };
132 131
133 CPU6: cpu@2 { 132 CPU6: cpu@2 {
134 compatible = "arm,cort 133 compatible = "arm,cortex-a53";
135 device_type = "cpu"; 134 device_type = "cpu";
136 enable-method = "spin- 135 enable-method = "spin-table";
137 reg = <0x2>; 136 reg = <0x2>;
138 next-level-cache = <&L 137 next-level-cache = <&L2_0>;
139 qcom,acc = <&acc6>; 138 qcom,acc = <&acc6>;
140 qcom,saw = <&saw6>; 139 qcom,saw = <&saw6>;
141 cpu-idle-states = <&CP 140 cpu-idle-states = <&CPU_SLEEP_0>;
142 clocks = <&apcs0_mbox> 141 clocks = <&apcs0_mbox>;
143 #cooling-cells = <2>; 142 #cooling-cells = <2>;
144 }; 143 };
145 144
146 CPU7: cpu@3 { 145 CPU7: cpu@3 {
147 compatible = "arm,cort 146 compatible = "arm,cortex-a53";
148 device_type = "cpu"; 147 device_type = "cpu";
149 enable-method = "spin- 148 enable-method = "spin-table";
150 reg = <0x3>; 149 reg = <0x3>;
151 next-level-cache = <&L 150 next-level-cache = <&L2_0>;
152 qcom,acc = <&acc7>; 151 qcom,acc = <&acc7>;
153 qcom,saw = <&saw7>; 152 qcom,saw = <&saw7>;
154 cpu-idle-states = <&CP 153 cpu-idle-states = <&CPU_SLEEP_0>;
155 clocks = <&apcs0_mbox> 154 clocks = <&apcs0_mbox>;
156 #cooling-cells = <2>; 155 #cooling-cells = <2>;
157 }; 156 };
158 157
159 idle-states { 158 idle-states {
160 CPU_SLEEP_0: cpu-sleep 159 CPU_SLEEP_0: cpu-sleep-0 {
161 compatible = " 160 compatible = "arm,idle-state";
162 entry-latency- 161 entry-latency-us = <130>;
163 exit-latency-u 162 exit-latency-us = <150>;
164 min-residency- 163 min-residency-us = <2000>;
165 local-timer-st 164 local-timer-stop;
166 }; 165 };
167 }; 166 };
168 }; 167 };
169 168
170 /* 169 /*
171 * MSM8939 has a big.LITTLE heterogene 170 * MSM8939 has a big.LITTLE heterogeneous computing architecture,
172 * consisting of two clusters of four 171 * consisting of two clusters of four ARM Cortex-A53s each. The
173 * LITTLE cluster runs at 1.0-1.2GHz, 172 * LITTLE cluster runs at 1.0-1.2GHz, and the big cluster runs
174 * at 1.5-1.7GHz. 173 * at 1.5-1.7GHz.
175 * 174 *
176 * The enable method used here is spin 175 * The enable method used here is spin-table which presupposes use
177 * of a 2nd stage boot shim such as lk 176 * of a 2nd stage boot shim such as lk2nd to have installed a
178 * spin-table, the downstream non-psci 177 * spin-table, the downstream non-psci/non-spin-table method that
179 * default msm8916/msm8936/msm8939 wil 178 * default msm8916/msm8936/msm8939 will not be supported upstream.
180 */ 179 */
181 cpu-map { 180 cpu-map {
182 /* LITTLE (efficiency) cluster 181 /* LITTLE (efficiency) cluster */
183 cluster0 { 182 cluster0 {
184 core0 { 183 core0 {
185 cpu = <&CPU4>; 184 cpu = <&CPU4>;
186 }; 185 };
187 186
188 core1 { 187 core1 {
189 cpu = <&CPU5>; 188 cpu = <&CPU5>;
190 }; 189 };
191 190
192 core2 { 191 core2 {
193 cpu = <&CPU6>; 192 cpu = <&CPU6>;
194 }; 193 };
195 194
196 core3 { 195 core3 {
197 cpu = <&CPU7>; 196 cpu = <&CPU7>;
198 }; 197 };
199 }; 198 };
200 199
201 /* big (performance) cluster * 200 /* big (performance) cluster */
202 /* Boot CPU is cluster 1 core 201 /* Boot CPU is cluster 1 core 0 */
203 cluster1 { 202 cluster1 {
204 core0 { 203 core0 {
205 cpu = <&CPU0>; 204 cpu = <&CPU0>;
206 }; 205 };
207 206
208 core1 { 207 core1 {
209 cpu = <&CPU1>; 208 cpu = <&CPU1>;
210 }; 209 };
211 210
212 core2 { 211 core2 {
213 cpu = <&CPU2>; 212 cpu = <&CPU2>;
214 }; 213 };
215 214
216 core3 { 215 core3 {
217 cpu = <&CPU3>; 216 cpu = <&CPU3>;
218 }; 217 };
219 }; 218 };
220 }; 219 };
221 220
222 firmware { 221 firmware {
223 scm: scm { 222 scm: scm {
224 compatible = "qcom,scm 223 compatible = "qcom,scm-msm8916", "qcom,scm";
225 clocks = <&gcc GCC_CRY 224 clocks = <&gcc GCC_CRYPTO_CLK>,
226 <&gcc GCC_CRY 225 <&gcc GCC_CRYPTO_AXI_CLK>,
227 <&gcc GCC_CRY 226 <&gcc GCC_CRYPTO_AHB_CLK>;
228 clock-names = "core", 227 clock-names = "core", "bus", "iface";
229 #reset-cells = <1>; 228 #reset-cells = <1>;
230 229
231 qcom,dload-mode = <&tc 230 qcom,dload-mode = <&tcsr 0x6100>;
232 }; 231 };
233 }; 232 };
234 233
235 memory@80000000 { 234 memory@80000000 {
236 device_type = "memory"; 235 device_type = "memory";
237 /* We expect the bootloader to 236 /* We expect the bootloader to fill in the reg */
238 reg = <0x0 0x80000000 0x0 0x0> 237 reg = <0x0 0x80000000 0x0 0x0>;
239 }; 238 };
240 239
241 pmu { 240 pmu {
242 compatible = "arm,cortex-a53-p 241 compatible = "arm,cortex-a53-pmu";
243 interrupts = <GIC_PPI 7 (GIC_C 242 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
244 }; 243 };
245 244
246 rpm: remoteproc { <<
247 compatible = "qcom,msm8936-rpm <<
248 <<
249 smd-edge { <<
250 interrupts = <GIC_SPI <<
251 qcom,ipc = <&apcs1_mbo <<
252 qcom,smd-edge = <15>; <<
253 <<
254 rpm_requests: rpm-requ <<
255 compatible = " <<
256 qcom,smd-chann <<
257 <<
258 rpmcc: clock-c <<
259 compat <<
260 #clock <<
261 clock- <<
262 clocks <<
263 }; <<
264 <<
265 rpmpd: power-c <<
266 compat <<
267 #power <<
268 operat <<
269 <<
270 rpmpd_ <<
271 <<
272 <<
273 <<
274 <<
275 <<
276 <<
277 <<
278 <<
279 <<
280 <<
281 <<
282 <<
283 <<
284 <<
285 <<
286 <<
287 <<
288 <<
289 <<
290 <<
291 <<
292 <<
293 <<
294 <<
295 <<
296 }; <<
297 }; <<
298 }; <<
299 }; <<
300 }; <<
301 <<
302 reserved-memory { 245 reserved-memory {
303 #address-cells = <2>; 246 #address-cells = <2>;
304 #size-cells = <2>; 247 #size-cells = <2>;
305 ranges; 248 ranges;
306 249
307 tz-apps@86000000 { 250 tz-apps@86000000 {
308 reg = <0x0 0x86000000 251 reg = <0x0 0x86000000 0x0 0x300000>;
309 no-map; 252 no-map;
310 }; 253 };
311 254
312 smem@86300000 { 255 smem@86300000 {
313 compatible = "qcom,sme 256 compatible = "qcom,smem";
314 reg = <0x0 0x86300000 257 reg = <0x0 0x86300000 0x0 0x100000>;
315 no-map; 258 no-map;
316 259
317 hwlocks = <&tcsr_mutex 260 hwlocks = <&tcsr_mutex 3>;
318 qcom,rpm-msg-ram = <&r 261 qcom,rpm-msg-ram = <&rpm_msg_ram>;
319 }; 262 };
320 263
321 hypervisor@86400000 { 264 hypervisor@86400000 {
322 reg = <0x0 0x86400000 265 reg = <0x0 0x86400000 0x0 0x100000>;
323 no-map; 266 no-map;
324 }; 267 };
325 268
326 tz@86500000 { 269 tz@86500000 {
327 reg = <0x0 0x86500000 270 reg = <0x0 0x86500000 0x0 0x180000>;
328 no-map; 271 no-map;
329 }; 272 };
330 273
331 reserved@86680000 { 274 reserved@86680000 {
332 reg = <0x0 0x86680000 275 reg = <0x0 0x86680000 0x0 0x80000>;
333 no-map; 276 no-map;
334 }; 277 };
335 278
336 rmtfs@86700000 { 279 rmtfs@86700000 {
337 compatible = "qcom,rmt 280 compatible = "qcom,rmtfs-mem";
338 reg = <0x0 0x86700000 281 reg = <0x0 0x86700000 0x0 0xe0000>;
339 no-map; 282 no-map;
340 283
341 qcom,client-id = <1>; 284 qcom,client-id = <1>;
342 }; 285 };
343 286
344 rfsa@867e0000 { 287 rfsa@867e0000 {
345 reg = <0x0 0x867e0000 288 reg = <0x0 0x867e0000 0x0 0x20000>;
346 no-map; 289 no-map;
347 }; 290 };
348 291
349 mpss_mem: mpss@86800000 { 292 mpss_mem: mpss@86800000 {
350 /* !! 293 reg = <0x0 0x86800000 0x0 0x5500000>;
351 * The memory region f <<
352 * relocatable and cou <<
353 * However, many firmw <<
354 * loaded to some spec <<
355 * define reliable all <<
356 * <<
357 * alignment = <0x0 0x <<
358 * alloc-ranges = <0x0 <<
359 */ <<
360 reg = <0x0 0x86800000 <<
361 no-map; 294 no-map;
362 status = "disabled"; <<
363 }; 295 };
364 296
365 wcnss_mem: wcnss { !! 297 wcnss_mem: wcnss@8bd00000 {
366 size = <0x0 0x600000>; !! 298 reg = <0x0 0x8bd00000 0x0 0x600000>;
367 alignment = <0x0 0x100 <<
368 alloc-ranges = <0x0 0x <<
369 no-map; 299 no-map;
370 status = "disabled"; <<
371 }; 300 };
372 301
373 venus_mem: venus { !! 302 venus_mem: venus@8c300000 {
374 size = <0x0 0x500000>; !! 303 reg = <0x0 0x8c300000 0x0 0x800000>;
375 alignment = <0x0 0x100 <<
376 alloc-ranges = <0x0 0x <<
377 no-map; 304 no-map;
378 status = "disabled"; <<
379 }; 305 };
380 306
381 mba_mem: mba { !! 307 mba_mem: mba@8cb00000 {
382 size = <0x0 0x100000>; !! 308 reg = <0x0 0x8cb00000 0x0 0x100000>;
383 alignment = <0x0 0x100 <<
384 alloc-ranges = <0x0 0x <<
385 no-map; 309 no-map;
386 status = "disabled"; !! 310 };
>> 311 };
>> 312
>> 313 smd {
>> 314 compatible = "qcom,smd";
>> 315
>> 316 rpm {
>> 317 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
>> 318 qcom,ipc = <&apcs1_mbox 8 0>;
>> 319 qcom,smd-edge = <15>;
>> 320
>> 321 rpm_requests: rpm-requests {
>> 322 compatible = "qcom,rpm-msm8936";
>> 323 qcom,smd-channels = "rpm_requests";
>> 324
>> 325 rpmcc: clock-controller {
>> 326 compatible = "qcom,rpmcc-msm8936", "qcom,rpmcc";
>> 327 #clock-cells = <1>;
>> 328 clock-names = "xo";
>> 329 clocks = <&xo_board>;
>> 330 };
>> 331
>> 332 rpmpd: power-controller {
>> 333 compatible = "qcom,msm8939-rpmpd";
>> 334 #power-domain-cells = <1>;
>> 335 operating-points-v2 = <&rpmpd_opp_table>;
>> 336
>> 337 rpmpd_opp_table: opp-table {
>> 338 compatible = "operating-points-v2";
>> 339
>> 340 rpmpd_opp_ret: opp1 {
>> 341 opp-level = <1>;
>> 342 };
>> 343
>> 344 rpmpd_opp_svs_krait: opp2 {
>> 345 opp-level = <2>;
>> 346 };
>> 347
>> 348 rpmpd_opp_svs_soc: opp3 {
>> 349 opp-level = <3>;
>> 350 };
>> 351
>> 352 rpmpd_opp_nom: opp4 {
>> 353 opp-level = <4>;
>> 354 };
>> 355
>> 356 rpmpd_opp_turbo: opp5 {
>> 357 opp-level = <5>;
>> 358 };
>> 359
>> 360 rpmpd_opp_super_turbo: opp6 {
>> 361 opp-level = <6>;
>> 362 };
>> 363 };
>> 364 };
>> 365 };
387 }; 366 };
388 }; 367 };
389 368
390 smp2p-hexagon { 369 smp2p-hexagon {
391 compatible = "qcom,smp2p"; 370 compatible = "qcom,smp2p";
392 qcom,smem = <435>, <428>; 371 qcom,smem = <435>, <428>;
393 372
394 interrupts = <GIC_SPI 27 IRQ_T 373 interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>;
395 374
396 mboxes = <&apcs1_mbox 14>; 375 mboxes = <&apcs1_mbox 14>;
397 376
398 qcom,local-pid = <0>; 377 qcom,local-pid = <0>;
399 qcom,remote-pid = <1>; 378 qcom,remote-pid = <1>;
400 379
401 hexagon_smp2p_out: master-kern 380 hexagon_smp2p_out: master-kernel {
402 qcom,entry-name = "mas 381 qcom,entry-name = "master-kernel";
403 382
404 #qcom,smem-state-cells 383 #qcom,smem-state-cells = <1>;
405 }; 384 };
406 385
407 hexagon_smp2p_in: slave-kernel 386 hexagon_smp2p_in: slave-kernel {
408 qcom,entry-name = "sla 387 qcom,entry-name = "slave-kernel";
409 388
410 interrupt-controller; 389 interrupt-controller;
411 #interrupt-cells = <2> 390 #interrupt-cells = <2>;
>> 391 #address-cells = <0>;
>> 392 #size-cells = <0>;
412 }; 393 };
413 }; 394 };
414 395
415 smp2p-wcnss { 396 smp2p-wcnss {
416 compatible = "qcom,smp2p"; 397 compatible = "qcom,smp2p";
417 qcom,smem = <451>, <431>; 398 qcom,smem = <451>, <431>;
418 399
419 interrupts = <GIC_SPI 143 IRQ_ 400 interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>;
420 401
421 mboxes = <&apcs1_mbox 18>; 402 mboxes = <&apcs1_mbox 18>;
422 403
423 qcom,local-pid = <0>; 404 qcom,local-pid = <0>;
424 qcom,remote-pid = <4>; 405 qcom,remote-pid = <4>;
425 406
426 wcnss_smp2p_in: slave-kernel { 407 wcnss_smp2p_in: slave-kernel {
427 qcom,entry-name = "sla 408 qcom,entry-name = "slave-kernel";
428 409
429 interrupt-controller; 410 interrupt-controller;
430 #interrupt-cells = <2> 411 #interrupt-cells = <2>;
431 }; 412 };
432 413
433 wcnss_smp2p_out: master-kernel 414 wcnss_smp2p_out: master-kernel {
434 qcom,entry-name = "mas 415 qcom,entry-name = "master-kernel";
435 416
436 #qcom,smem-state-cells 417 #qcom,smem-state-cells = <1>;
437 }; 418 };
438 }; 419 };
439 420
440 smsm { 421 smsm {
441 compatible = "qcom,smsm"; 422 compatible = "qcom,smsm";
442 423
443 #address-cells = <1>; 424 #address-cells = <1>;
444 #size-cells = <0>; 425 #size-cells = <0>;
445 426
446 mboxes = <0>, <&apcs1_mbox 13> !! 427 qcom,ipc-1 = <&apcs1_mbox 8 13>;
>> 428 qcom,ipc-3 = <&apcs1_mbox 8 19>;
447 429
448 apps_smsm: apps@0 { 430 apps_smsm: apps@0 {
449 reg = <0>; 431 reg = <0>;
450 432
451 #qcom,smem-state-cells 433 #qcom,smem-state-cells = <1>;
452 }; 434 };
453 435
454 hexagon_smsm: hexagon@1 { 436 hexagon_smsm: hexagon@1 {
455 reg = <1>; 437 reg = <1>;
456 interrupts = <GIC_SPI 438 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
457 439
458 interrupt-controller; 440 interrupt-controller;
459 #interrupt-cells = <2> 441 #interrupt-cells = <2>;
460 }; 442 };
461 443
462 wcnss_smsm: wcnss@6 { 444 wcnss_smsm: wcnss@6 {
463 reg = <6>; 445 reg = <6>;
464 interrupts = <GIC_SPI 446 interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>;
465 447
466 interrupt-controller; 448 interrupt-controller;
467 #interrupt-cells = <2> 449 #interrupt-cells = <2>;
468 }; 450 };
469 }; 451 };
470 452
471 soc: soc@0 { 453 soc: soc@0 {
472 compatible = "simple-bus"; 454 compatible = "simple-bus";
473 #address-cells = <1>; 455 #address-cells = <1>;
474 #size-cells = <1>; 456 #size-cells = <1>;
475 ranges = <0 0 0 0xffffffff>; 457 ranges = <0 0 0 0xffffffff>;
476 458
477 rng@22000 { 459 rng@22000 {
478 compatible = "qcom,prn 460 compatible = "qcom,prng";
479 reg = <0x00022000 0x20 461 reg = <0x00022000 0x200>;
480 clocks = <&gcc GCC_PRN 462 clocks = <&gcc GCC_PRNG_AHB_CLK>;
481 clock-names = "core"; 463 clock-names = "core";
482 }; 464 };
483 465
484 qfprom: qfprom@5c000 { 466 qfprom: qfprom@5c000 {
485 compatible = "qcom,msm 467 compatible = "qcom,msm8916-qfprom", "qcom,qfprom";
486 reg = <0x0005c000 0x10 468 reg = <0x0005c000 0x1000>;
487 #address-cells = <1>; 469 #address-cells = <1>;
488 #size-cells = <1>; 470 #size-cells = <1>;
489 471
490 tsens_base1: base1@a0 472 tsens_base1: base1@a0 {
491 reg = <0xa0 0x 473 reg = <0xa0 0x1>;
492 bits = <0 8>; 474 bits = <0 8>;
493 }; 475 };
494 476
495 tsens_s6_p1: s6-p1@a1 477 tsens_s6_p1: s6-p1@a1 {
496 reg = <0xa1 0x 478 reg = <0xa1 0x1>;
497 bits = <0 6>; 479 bits = <0 6>;
498 }; 480 };
499 481
500 tsens_s6_p2: s6-p2@a1 482 tsens_s6_p2: s6-p2@a1 {
501 reg = <0xa1 0x 483 reg = <0xa1 0x2>;
502 bits = <6 6>; 484 bits = <6 6>;
503 }; 485 };
504 486
505 tsens_s7_p1: s7-p1@a2 487 tsens_s7_p1: s7-p1@a2 {
506 reg = <0xa2 0x 488 reg = <0xa2 0x2>;
507 bits = <4 6>; 489 bits = <4 6>;
508 }; 490 };
509 491
510 tsens_s7_p2: s7-p2@a3 492 tsens_s7_p2: s7-p2@a3 {
511 reg = <0xa3 0x 493 reg = <0xa3 0x1>;
512 bits = <2 6>; 494 bits = <2 6>;
513 }; 495 };
514 496
515 tsens_s8_p1: s8-p1@a4 497 tsens_s8_p1: s8-p1@a4 {
516 reg = <0xa4 0x 498 reg = <0xa4 0x1>;
517 bits = <0 6>; 499 bits = <0 6>;
518 }; 500 };
519 501
520 tsens_s8_p2: s8-p2@a4 502 tsens_s8_p2: s8-p2@a4 {
521 reg = <0xa4 0x 503 reg = <0xa4 0x2>;
522 bits = <6 6>; 504 bits = <6 6>;
523 }; 505 };
524 506
525 tsens_s9_p1: s9-p1@a5 507 tsens_s9_p1: s9-p1@a5 {
526 reg = <0xa5 0x 508 reg = <0xa5 0x2>;
527 bits = <4 6>; 509 bits = <4 6>;
528 }; 510 };
529 511
530 tsens_s9_p2: s9-p2@a6 512 tsens_s9_p2: s9-p2@a6 {
531 reg = <0xa6 0x 513 reg = <0xa6 0x1>;
532 bits = <2 6>; 514 bits = <2 6>;
533 }; 515 };
534 516
535 tsens_base2: base2@a7 517 tsens_base2: base2@a7 {
536 reg = <0xa7 0x 518 reg = <0xa7 0x1>;
537 bits = <0 8>; 519 bits = <0 8>;
538 }; 520 };
539 521
540 tsens_mode: mode@d0 { 522 tsens_mode: mode@d0 {
541 reg = <0xd0 0x 523 reg = <0xd0 0x1>;
542 bits = <0 3>; 524 bits = <0 3>;
543 }; 525 };
544 526
545 tsens_s0_p1: s0-p1@d0 527 tsens_s0_p1: s0-p1@d0 {
546 reg = <0xd0 0x 528 reg = <0xd0 0x2>;
547 bits = <3 6>; 529 bits = <3 6>;
548 }; 530 };
549 531
550 tsens_s0_p2: s0-p1@d1 532 tsens_s0_p2: s0-p1@d1 {
551 reg = <0xd1 0x 533 reg = <0xd1 0x1>;
552 bits = <1 6>; 534 bits = <1 6>;
553 }; 535 };
554 536
555 tsens_s1_p1: s1-p1@d1 537 tsens_s1_p1: s1-p1@d1 {
556 reg = <0xd1 0x 538 reg = <0xd1 0x2>;
557 bits = <7 6>; 539 bits = <7 6>;
558 }; 540 };
559 541
560 tsens_s1_p2: s1-p2@d2 542 tsens_s1_p2: s1-p2@d2 {
561 reg = <0xd2 0x 543 reg = <0xd2 0x2>;
562 bits = <5 6>; 544 bits = <5 6>;
563 }; 545 };
564 546
565 tsens_s2_p1: s2-p1@d3 547 tsens_s2_p1: s2-p1@d3 {
566 reg = <0xd3 0x 548 reg = <0xd3 0x2>;
567 bits = <3 6>; 549 bits = <3 6>;
568 }; 550 };
569 551
570 tsens_s2_p2: s2-p2@d4 552 tsens_s2_p2: s2-p2@d4 {
571 reg = <0xd4 0x 553 reg = <0xd4 0x1>;
572 bits = <1 6>; 554 bits = <1 6>;
573 }; 555 };
574 556
575 tsens_s3_p1: s3-p1@d4 557 tsens_s3_p1: s3-p1@d4 {
576 reg = <0xd4 0x 558 reg = <0xd4 0x2>;
577 bits = <7 6>; 559 bits = <7 6>;
578 }; 560 };
579 561
580 tsens_s3_p2: s3-p2@d5 562 tsens_s3_p2: s3-p2@d5 {
581 reg = <0xd5 0x 563 reg = <0xd5 0x2>;
582 bits = <5 6>; 564 bits = <5 6>;
583 }; 565 };
584 566
585 tsens_s5_p1: s5-p1@d6 567 tsens_s5_p1: s5-p1@d6 {
586 reg = <0xd6 0x 568 reg = <0xd6 0x2>;
587 bits = <3 6>; 569 bits = <3 6>;
588 }; 570 };
589 571
590 tsens_s5_p2: s5-p2@d7 572 tsens_s5_p2: s5-p2@d7 {
591 reg = <0xd7 0x 573 reg = <0xd7 0x1>;
592 bits = <1 6>; 574 bits = <1 6>;
593 }; 575 };
594 }; 576 };
595 577
596 rpm_msg_ram: sram@60000 { 578 rpm_msg_ram: sram@60000 {
597 compatible = "qcom,rpm 579 compatible = "qcom,rpm-msg-ram";
598 reg = <0x00060000 0x80 580 reg = <0x00060000 0x8000>;
599 }; 581 };
600 582
601 bimc: interconnect@400000 { 583 bimc: interconnect@400000 {
602 compatible = "qcom,msm 584 compatible = "qcom,msm8939-bimc";
603 reg = <0x00400000 0x62 585 reg = <0x00400000 0x62000>;
>> 586 clock-names = "bus", "bus_a";
>> 587 clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
>> 588 <&rpmcc RPM_SMD_BIMC_A_CLK>;
604 #interconnect-cells = 589 #interconnect-cells = <1>;
605 }; 590 };
606 591
607 tsens: thermal-sensor@4a9000 { 592 tsens: thermal-sensor@4a9000 {
608 compatible = "qcom,msm 593 compatible = "qcom,msm8939-tsens", "qcom,tsens-v0_1";
609 reg = <0x004a9000 0x10 594 reg = <0x004a9000 0x1000>, /* TM */
610 <0x004a8000 0x10 595 <0x004a8000 0x1000>; /* SROT */
611 nvmem-cells = <&tsens_ 596 nvmem-cells = <&tsens_mode>,
612 <&tsens_ 597 <&tsens_base1>, <&tsens_base2>,
613 <&tsens_ 598 <&tsens_s0_p1>, <&tsens_s0_p2>,
614 <&tsens_ 599 <&tsens_s1_p1>, <&tsens_s1_p2>,
615 <&tsens_ 600 <&tsens_s2_p1>, <&tsens_s2_p2>,
616 <&tsens_ 601 <&tsens_s3_p1>, <&tsens_s3_p2>,
617 <&tsens_ 602 <&tsens_s5_p1>, <&tsens_s5_p2>,
618 <&tsens_ 603 <&tsens_s6_p1>, <&tsens_s6_p2>,
619 <&tsens_ 604 <&tsens_s7_p1>, <&tsens_s7_p2>,
620 <&tsens_ 605 <&tsens_s8_p1>, <&tsens_s8_p2>,
621 <&tsens_ 606 <&tsens_s9_p1>, <&tsens_s9_p2>;
622 nvmem-cell-names = "mo 607 nvmem-cell-names = "mode",
623 "ba 608 "base1", "base2",
624 "s0 609 "s0_p1", "s0_p2",
625 "s1 610 "s1_p1", "s1_p2",
626 "s2 611 "s2_p1", "s2_p2",
627 "s3 612 "s3_p1", "s3_p2",
628 "s5 613 "s5_p1", "s5_p2",
629 "s6 614 "s6_p1", "s6_p2",
630 "s7 615 "s7_p1", "s7_p2",
631 "s8 616 "s8_p1", "s8_p2",
632 "s9 617 "s9_p1", "s9_p2";
633 #qcom,sensors = <9>; 618 #qcom,sensors = <9>;
634 interrupts = <GIC_SPI 619 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
635 interrupt-names = "upl 620 interrupt-names = "uplow";
636 #thermal-sensor-cells 621 #thermal-sensor-cells = <1>;
637 }; 622 };
638 623
639 restart@4ab000 { 624 restart@4ab000 {
640 compatible = "qcom,psh 625 compatible = "qcom,pshold";
641 reg = <0x004ab000 0x4> 626 reg = <0x004ab000 0x4>;
642 }; 627 };
643 628
644 pcnoc: interconnect@500000 { 629 pcnoc: interconnect@500000 {
645 compatible = "qcom,msm 630 compatible = "qcom,msm8939-pcnoc";
646 reg = <0x00500000 0x11 631 reg = <0x00500000 0x11000>;
>> 632 clock-names = "bus", "bus_a";
>> 633 clocks = <&rpmcc RPM_SMD_PCNOC_CLK>,
>> 634 <&rpmcc RPM_SMD_PCNOC_A_CLK>;
647 #interconnect-cells = 635 #interconnect-cells = <1>;
648 }; 636 };
649 637
650 snoc: interconnect@580000 { 638 snoc: interconnect@580000 {
651 compatible = "qcom,msm 639 compatible = "qcom,msm8939-snoc";
652 reg = <0x00580000 0x14 640 reg = <0x00580000 0x14080>;
>> 641 clock-names = "bus", "bus_a";
>> 642 clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
>> 643 <&rpmcc RPM_SMD_SNOC_A_CLK>;
653 #interconnect-cells = 644 #interconnect-cells = <1>;
654 645
655 snoc_mm: interconnect- 646 snoc_mm: interconnect-snoc {
656 compatible = " 647 compatible = "qcom,msm8939-snoc-mm";
>> 648 clock-names = "bus", "bus_a";
>> 649 clocks = <&rpmcc RPM_SMD_SYSMMNOC_CLK>,
>> 650 <&rpmcc RPM_SMD_SYSMMNOC_A_CLK>;
657 #interconnect- 651 #interconnect-cells = <1>;
658 }; 652 };
659 }; 653 };
660 654
661 tlmm: pinctrl@1000000 { 655 tlmm: pinctrl@1000000 {
662 compatible = "qcom,msm 656 compatible = "qcom,msm8916-pinctrl";
663 reg = <0x01000000 0x30 657 reg = <0x01000000 0x300000>;
664 interrupts = <GIC_SPI 658 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
665 gpio-controller; 659 gpio-controller;
666 gpio-ranges = <&tlmm 0 660 gpio-ranges = <&tlmm 0 0 122>;
667 #gpio-cells = <2>; 661 #gpio-cells = <2>;
668 interrupt-controller; 662 interrupt-controller;
669 #interrupt-cells = <2> 663 #interrupt-cells = <2>;
670 664
671 blsp_i2c1_default: bls 665 blsp_i2c1_default: blsp-i2c1-default-state {
672 pins = "gpio2" 666 pins = "gpio2", "gpio3";
673 function = "bl 667 function = "blsp_i2c1";
674 drive-strength 668 drive-strength = <2>;
675 bias-disable; 669 bias-disable;
676 }; 670 };
677 671
678 blsp_i2c1_sleep: blsp- 672 blsp_i2c1_sleep: blsp-i2c1-sleep-state {
679 pins = "gpio2" 673 pins = "gpio2", "gpio3";
680 function = "gp 674 function = "gpio";
681 drive-strength 675 drive-strength = <2>;
682 bias-disable; 676 bias-disable;
683 }; 677 };
684 678
685 blsp_i2c2_default: bls 679 blsp_i2c2_default: blsp-i2c2-default-state {
686 pins = "gpio6" 680 pins = "gpio6", "gpio7";
687 function = "bl 681 function = "blsp_i2c2";
688 drive-strength 682 drive-strength = <2>;
689 bias-disable; 683 bias-disable;
690 }; 684 };
691 685
692 blsp_i2c2_sleep: blsp- 686 blsp_i2c2_sleep: blsp-i2c2-sleep-state {
693 pins = "gpio6" 687 pins = "gpio6", "gpio7";
694 function = "gp 688 function = "gpio";
695 drive-strength 689 drive-strength = <2>;
696 bias-disable; 690 bias-disable;
697 }; 691 };
698 692
699 blsp_i2c3_default: bls 693 blsp_i2c3_default: blsp-i2c3-default-state {
700 pins = "gpio10 694 pins = "gpio10", "gpio11";
701 function = "bl 695 function = "blsp_i2c3";
702 drive-strength 696 drive-strength = <2>;
703 bias-disable; 697 bias-disable;
704 }; 698 };
705 699
706 blsp_i2c3_sleep: blsp- 700 blsp_i2c3_sleep: blsp-i2c3-sleep-state {
707 pins = "gpio10 701 pins = "gpio10", "gpio11";
708 function = "gp 702 function = "gpio";
709 drive-strength 703 drive-strength = <2>;
710 bias-disable; 704 bias-disable;
711 }; 705 };
712 706
713 blsp_i2c4_default: bls 707 blsp_i2c4_default: blsp-i2c4-default-state {
714 pins = "gpio14 708 pins = "gpio14", "gpio15";
715 function = "bl 709 function = "blsp_i2c4";
716 drive-strength 710 drive-strength = <2>;
717 bias-disable; 711 bias-disable;
718 }; 712 };
719 713
720 blsp_i2c4_sleep: blsp- 714 blsp_i2c4_sleep: blsp-i2c4-sleep-state {
721 pins = "gpio14 715 pins = "gpio14", "gpio15";
722 function = "gp 716 function = "gpio";
723 drive-strength 717 drive-strength = <2>;
724 bias-disable; 718 bias-disable;
725 }; 719 };
726 720
727 blsp_i2c5_default: bls 721 blsp_i2c5_default: blsp-i2c5-default-state {
728 pins = "gpio18 722 pins = "gpio18", "gpio19";
729 function = "bl 723 function = "blsp_i2c5";
730 drive-strength 724 drive-strength = <2>;
731 bias-disable; 725 bias-disable;
732 }; 726 };
733 727
734 blsp_i2c5_sleep: blsp- 728 blsp_i2c5_sleep: blsp-i2c5-sleep-state {
735 pins = "gpio18 729 pins = "gpio18", "gpio19";
736 function = "gp 730 function = "gpio";
737 drive-strength 731 drive-strength = <2>;
738 bias-disable; 732 bias-disable;
739 }; 733 };
740 734
741 blsp_i2c6_default: bls 735 blsp_i2c6_default: blsp-i2c6-default-state {
742 pins = "gpio22 736 pins = "gpio22", "gpio23";
743 function = "bl 737 function = "blsp_i2c6";
744 drive-strength 738 drive-strength = <2>;
745 bias-disable; 739 bias-disable;
746 }; 740 };
747 741
748 blsp_i2c6_sleep: blsp- 742 blsp_i2c6_sleep: blsp-i2c6-sleep-state {
749 pins = "gpio22 743 pins = "gpio22", "gpio23";
750 function = "gp 744 function = "gpio";
751 drive-strength 745 drive-strength = <2>;
752 bias-disable; 746 bias-disable;
753 }; 747 };
754 748
755 blsp_spi1_default: bls 749 blsp_spi1_default: blsp-spi1-default-state {
756 spi-pins { 750 spi-pins {
757 pins = 751 pins = "gpio0", "gpio1", "gpio3";
758 functi 752 function = "blsp_spi1";
759 drive- 753 drive-strength = <12>;
760 bias-d 754 bias-disable;
761 }; 755 };
762 756
763 cs-pins { 757 cs-pins {
764 pins = 758 pins = "gpio2";
765 functi 759 function = "gpio";
766 drive- 760 drive-strength = <16>;
767 bias-d 761 bias-disable;
768 output 762 output-high;
769 }; 763 };
770 }; 764 };
771 765
772 blsp_spi1_sleep: blsp- 766 blsp_spi1_sleep: blsp-spi1-sleep-state {
773 pins = "gpio0" 767 pins = "gpio0", "gpio1", "gpio2", "gpio3";
774 function = "gp 768 function = "gpio";
775 drive-strength 769 drive-strength = <2>;
776 bias-pull-down 770 bias-pull-down;
777 }; 771 };
778 772
779 blsp_spi2_default: bls 773 blsp_spi2_default: blsp-spi2-default-state {
780 spi-pins { 774 spi-pins {
781 pins = 775 pins = "gpio4", "gpio5", "gpio7";
782 functi 776 function = "blsp_spi2";
783 drive- 777 drive-strength = <12>;
784 bias-d 778 bias-disable;
785 }; 779 };
786 780
787 cs-pins { 781 cs-pins {
788 pins = 782 pins = "gpio6";
789 functi 783 function = "gpio";
790 drive- 784 drive-strength = <16>;
791 bias-d 785 bias-disable;
792 output 786 output-high;
793 }; 787 };
794 }; 788 };
795 789
796 blsp_spi2_sleep: blsp- 790 blsp_spi2_sleep: blsp-spi2-sleep-state {
797 pins = "gpio4" 791 pins = "gpio4", "gpio5", "gpio6", "gpio7";
798 function = "gp 792 function = "gpio";
799 drive-strength 793 drive-strength = <2>;
800 bias-pull-down 794 bias-pull-down;
801 }; 795 };
802 796
803 blsp_spi3_default: bls 797 blsp_spi3_default: blsp-spi3-default-state {
804 spi-pins { 798 spi-pins {
805 pins = 799 pins = "gpio8", "gpio9", "gpio11";
806 functi 800 function = "blsp_spi3";
807 drive- 801 drive-strength = <12>;
808 bias-d 802 bias-disable;
809 }; 803 };
810 804
811 cs-pins { 805 cs-pins {
812 pins = 806 pins = "gpio10";
813 functi 807 function = "gpio";
814 drive- 808 drive-strength = <16>;
815 bias-d 809 bias-disable;
816 output 810 output-high;
817 }; 811 };
818 }; 812 };
819 813
820 blsp_spi3_sleep: blsp- 814 blsp_spi3_sleep: blsp-spi3-sleep-state {
821 pins = "gpio8" 815 pins = "gpio8", "gpio9", "gpio10", "gpio11";
822 function = "gp 816 function = "gpio";
823 drive-strength 817 drive-strength = <2>;
824 bias-pull-down 818 bias-pull-down;
825 }; 819 };
826 820
827 blsp_spi4_default: bls 821 blsp_spi4_default: blsp-spi4-default-state {
828 spi-pins { 822 spi-pins {
829 pins = 823 pins = "gpio12", "gpio13", "gpio15";
830 functi 824 function = "blsp_spi4";
831 drive- 825 drive-strength = <12>;
832 bias-d 826 bias-disable;
833 }; 827 };
834 828
835 cs-pins { 829 cs-pins {
836 pins = 830 pins = "gpio14";
837 functi 831 function = "gpio";
838 drive- 832 drive-strength = <16>;
839 bias-d 833 bias-disable;
840 output 834 output-high;
841 }; 835 };
842 }; 836 };
843 837
844 blsp_spi4_sleep: blsp- 838 blsp_spi4_sleep: blsp-spi4-sleep-state {
845 pins = "gpio12 839 pins = "gpio12", "gpio13", "gpio14", "gpio15";
846 function = "gp 840 function = "gpio";
847 drive-strength 841 drive-strength = <2>;
848 bias-pull-down 842 bias-pull-down;
849 }; 843 };
850 844
851 blsp_spi5_default: bls 845 blsp_spi5_default: blsp-spi5-default-state {
852 spi-pins { 846 spi-pins {
853 pins = 847 pins = "gpio16", "gpio17", "gpio19";
854 functi 848 function = "blsp_spi5";
855 drive- 849 drive-strength = <12>;
856 bias-d 850 bias-disable;
857 }; 851 };
858 852
859 cs-pins { 853 cs-pins {
860 pins = 854 pins = "gpio18";
861 functi 855 function = "gpio";
862 drive- 856 drive-strength = <16>;
863 bias-d 857 bias-disable;
864 output 858 output-high;
865 }; 859 };
866 }; 860 };
867 861
868 blsp_spi5_sleep: blsp- 862 blsp_spi5_sleep: blsp-spi5-sleep-state {
869 pins = "gpio16 863 pins = "gpio16", "gpio17", "gpio18", "gpio19";
870 function = "gp 864 function = "gpio";
871 drive-strength 865 drive-strength = <2>;
872 bias-pull-down 866 bias-pull-down;
873 }; 867 };
874 868
875 blsp_spi6_default: bls 869 blsp_spi6_default: blsp-spi6-default-state {
876 spi-pins { 870 spi-pins {
877 pins = 871 pins = "gpio20", "gpio21", "gpio23";
878 functi 872 function = "blsp_spi6";
879 drive- 873 drive-strength = <12>;
880 bias-d 874 bias-disable;
881 }; 875 };
882 876
883 cs-pins { 877 cs-pins {
884 pins = 878 pins = "gpio22";
885 functi 879 function = "gpio";
886 drive- 880 drive-strength = <16>;
887 bias-d 881 bias-disable;
888 output 882 output-high;
889 }; 883 };
890 }; 884 };
891 885
892 blsp_spi6_sleep: blsp- 886 blsp_spi6_sleep: blsp-spi6-sleep-state {
893 pins = "gpio20 887 pins = "gpio20", "gpio21", "gpio22", "gpio23";
894 function = "gp 888 function = "gpio";
895 drive-strength 889 drive-strength = <2>;
896 bias-pull-down 890 bias-pull-down;
897 }; 891 };
898 892
899 blsp_uart1_default: bl 893 blsp_uart1_default: blsp-uart1-default-state {
900 pins = "gpio0" 894 pins = "gpio0", "gpio1", "gpio2", "gpio3";
901 function = "bl 895 function = "blsp_uart1";
902 drive-strength 896 drive-strength = <16>;
903 bias-disable; 897 bias-disable;
904 }; 898 };
905 899
906 blsp_uart1_sleep: blsp 900 blsp_uart1_sleep: blsp-uart1-sleep-state {
907 pins = "gpio0" 901 pins = "gpio0", "gpio1", "gpio2", "gpio3";
908 function = "gp 902 function = "gpio";
909 drive-strength 903 drive-strength = <2>;
910 bias-pull-down 904 bias-pull-down;
911 }; 905 };
912 906
913 blsp_uart2_default: bl 907 blsp_uart2_default: blsp-uart2-default-state {
914 pins = "gpio4" 908 pins = "gpio4", "gpio5";
915 function = "bl 909 function = "blsp_uart2";
916 drive-strength 910 drive-strength = <16>;
917 bias-disable; 911 bias-disable;
918 }; 912 };
919 913
920 blsp_uart2_sleep: blsp 914 blsp_uart2_sleep: blsp-uart2-sleep-state {
921 pins = "gpio4" 915 pins = "gpio4", "gpio5";
922 function = "gp 916 function = "gpio";
923 drive-strength 917 drive-strength = <2>;
924 bias-pull-down 918 bias-pull-down;
925 }; 919 };
926 920
927 camera_front_default: 921 camera_front_default: camera-front-default-state {
928 pwdn-pins { 922 pwdn-pins {
929 pins = 923 pins = "gpio33";
930 functi 924 function = "gpio";
931 drive- 925 drive-strength = <16>;
932 bias-d 926 bias-disable;
933 }; 927 };
934 928
935 rst-pins { 929 rst-pins {
936 pins = 930 pins = "gpio28";
937 functi 931 function = "gpio";
938 drive- 932 drive-strength = <16>;
939 bias-d 933 bias-disable;
940 }; 934 };
941 935
942 mclk1-pins { 936 mclk1-pins {
943 pins = 937 pins = "gpio27";
944 functi 938 function = "cam_mclk1";
945 drive- 939 drive-strength = <16>;
946 bias-d 940 bias-disable;
947 }; 941 };
948 }; 942 };
949 943
950 camera_rear_default: c 944 camera_rear_default: camera-rear-default-state {
951 pwdn-pins { 945 pwdn-pins {
952 pins = 946 pins = "gpio34";
953 functi 947 function = "gpio";
954 drive- 948 drive-strength = <16>;
955 bias-d 949 bias-disable;
956 }; 950 };
957 951
958 rst-pins { 952 rst-pins {
959 pins = 953 pins = "gpio35";
960 functi 954 function = "gpio";
961 drive- 955 drive-strength = <16>;
962 bias-d 956 bias-disable;
963 }; 957 };
964 958
965 mclk0-pins { 959 mclk0-pins {
966 pins = 960 pins = "gpio26";
967 functi 961 function = "cam_mclk0";
968 drive- 962 drive-strength = <16>;
969 bias-d 963 bias-disable;
970 }; 964 };
971 }; 965 };
972 966
973 cci0_default: cci0-def 967 cci0_default: cci0-default-state {
974 pins = "gpio29 968 pins = "gpio29", "gpio30";
975 function = "cc 969 function = "cci_i2c";
976 drive-strength 970 drive-strength = <16>;
977 bias-disable; 971 bias-disable;
978 }; 972 };
979 973
980 cdc_dmic_default: cdc- 974 cdc_dmic_default: cdc-dmic-default-state {
981 clk-pins { 975 clk-pins {
982 pins = 976 pins = "gpio0";
983 functi 977 function = "dmic0_clk";
984 drive- 978 drive-strength = <8>;
985 }; 979 };
986 980
987 data-pins { 981 data-pins {
988 pins = 982 pins = "gpio1";
989 functi 983 function = "dmic0_data";
990 drive- 984 drive-strength = <8>;
991 }; 985 };
992 }; 986 };
993 987
994 cdc_dmic_sleep: cdc-dm 988 cdc_dmic_sleep: cdc-dmic-sleep-state {
995 clk-pins { 989 clk-pins {
996 pins = 990 pins = "gpio0";
997 functi 991 function = "dmic0_clk";
998 drive- 992 drive-strength = <2>;
999 bias-d 993 bias-disable;
1000 }; 994 };
1001 995
1002 data-pins { 996 data-pins {
1003 pins 997 pins = "gpio1";
1004 funct 998 function = "dmic0_data";
1005 drive 999 drive-strength = <2>;
1006 bias- 1000 bias-disable;
1007 }; 1001 };
1008 }; 1002 };
1009 1003
1010 cdc_pdm_default: cdc- 1004 cdc_pdm_default: cdc-pdm-default-state {
1011 pins = "gpio6 1005 pins = "gpio63", "gpio64", "gpio65", "gpio66",
1012 "gpio6 1006 "gpio67", "gpio68";
1013 function = "c 1007 function = "cdc_pdm0";
1014 drive-strengt 1008 drive-strength = <8>;
1015 bias-disable; 1009 bias-disable;
1016 }; 1010 };
1017 1011
1018 cdc_pdm_sleep: cdc-pd 1012 cdc_pdm_sleep: cdc-pdm-sleep-state {
1019 pins = "gpio6 1013 pins = "gpio63", "gpio64", "gpio65", "gpio66",
1020 "gpio6 1014 "gpio67", "gpio68";
1021 function = "c 1015 function = "cdc_pdm0";
1022 drive-strengt 1016 drive-strength = <2>;
1023 bias-pull-dow 1017 bias-pull-down;
1024 }; 1018 };
1025 1019
1026 pri_mi2s_default: mi2 1020 pri_mi2s_default: mi2s-pri-default-state {
1027 pins = "gpio1 1021 pins = "gpio113", "gpio114", "gpio115", "gpio116";
1028 function = "p 1022 function = "pri_mi2s";
1029 drive-strengt 1023 drive-strength = <8>;
1030 bias-disable; 1024 bias-disable;
1031 }; 1025 };
1032 1026
1033 pri_mi2s_sleep: mi2s- 1027 pri_mi2s_sleep: mi2s-pri-sleep-state {
1034 pins = "gpio1 1028 pins = "gpio113", "gpio114", "gpio115", "gpio116";
1035 function = "p 1029 function = "pri_mi2s";
1036 drive-strengt 1030 drive-strength = <2>;
1037 bias-disable; 1031 bias-disable;
1038 }; 1032 };
1039 1033
1040 pri_mi2s_mclk_default 1034 pri_mi2s_mclk_default: mi2s-pri-mclk-default-state {
1041 pins = "gpio1 1035 pins = "gpio116";
1042 function = "p 1036 function = "pri_mi2s";
1043 drive-strengt 1037 drive-strength = <8>;
1044 bias-disable; 1038 bias-disable;
1045 }; 1039 };
1046 1040
1047 pri_mi2s_mclk_sleep: 1041 pri_mi2s_mclk_sleep: mi2s-pri-mclk-sleep-state {
1048 pins = "gpio1 1042 pins = "gpio116";
1049 function = "p 1043 function = "pri_mi2s";
1050 drive-strengt 1044 drive-strength = <2>;
1051 bias-disable; 1045 bias-disable;
1052 }; 1046 };
1053 1047
1054 pri_mi2s_ws_default: 1048 pri_mi2s_ws_default: mi2s-pri-ws-default-state {
1055 pins = "gpio1 1049 pins = "gpio110";
1056 function = "p 1050 function = "pri_mi2s_ws";
1057 drive-strengt 1051 drive-strength = <8>;
1058 bias-disable; 1052 bias-disable;
1059 }; 1053 };
1060 1054
1061 pri_mi2s_ws_sleep: mi 1055 pri_mi2s_ws_sleep: mi2s-pri-ws-sleep-state {
1062 pins = "gpio1 1056 pins = "gpio110";
1063 function = "p 1057 function = "pri_mi2s_ws";
1064 drive-strengt 1058 drive-strength = <2>;
1065 bias-disable; 1059 bias-disable;
1066 }; 1060 };
1067 1061
1068 sec_mi2s_default: mi2 1062 sec_mi2s_default: mi2s-sec-default-state {
1069 pins = "gpio1 1063 pins = "gpio112", "gpio117", "gpio118", "gpio119";
1070 function = "s 1064 function = "sec_mi2s";
1071 drive-strengt 1065 drive-strength = <8>;
1072 bias-disable; 1066 bias-disable;
1073 }; 1067 };
1074 1068
1075 sec_mi2s_sleep: mi2s- 1069 sec_mi2s_sleep: mi2s-sec-sleep-state {
1076 pins = "gpio1 1070 pins = "gpio112", "gpio117", "gpio118", "gpio119";
1077 function = "s 1071 function = "sec_mi2s";
1078 drive-strengt 1072 drive-strength = <2>;
1079 bias-disable; 1073 bias-disable;
1080 }; 1074 };
1081 1075
1082 sdc1_default: sdc1-de 1076 sdc1_default: sdc1-default-state {
1083 clk-pins { 1077 clk-pins {
1084 pins 1078 pins = "sdc1_clk";
1085 bias- 1079 bias-disable;
1086 drive 1080 drive-strength = <16>;
1087 }; 1081 };
1088 1082
1089 cmd-pins { 1083 cmd-pins {
1090 pins 1084 pins = "sdc1_cmd";
1091 bias- 1085 bias-pull-up;
1092 drive 1086 drive-strength = <10>;
1093 }; 1087 };
1094 1088
1095 data-pins { 1089 data-pins {
1096 pins 1090 pins = "sdc1_data";
1097 bias- 1091 bias-pull-up;
1098 drive 1092 drive-strength = <10>;
1099 }; 1093 };
1100 }; 1094 };
1101 1095
1102 sdc1_sleep: sdc1-slee 1096 sdc1_sleep: sdc1-sleep-state {
1103 clk-pins { 1097 clk-pins {
1104 pins 1098 pins = "sdc1_clk";
1105 bias- 1099 bias-disable;
1106 drive 1100 drive-strength = <2>;
1107 }; 1101 };
1108 1102
1109 cmd-pins { 1103 cmd-pins {
1110 pins 1104 pins = "sdc1_cmd";
1111 bias- 1105 bias-pull-up;
1112 drive 1106 drive-strength = <2>;
1113 }; 1107 };
1114 1108
1115 data-pins { 1109 data-pins {
1116 pins 1110 pins = "sdc1_data";
1117 bias- 1111 bias-pull-up;
1118 drive 1112 drive-strength = <2>;
1119 }; 1113 };
1120 }; 1114 };
1121 1115
1122 sdc2_default: sdc2-de 1116 sdc2_default: sdc2-default-state {
1123 clk-pins { 1117 clk-pins {
1124 pins 1118 pins = "sdc2_clk";
1125 bias- 1119 bias-disable;
1126 drive 1120 drive-strength = <16>;
1127 }; 1121 };
1128 1122
1129 cmd-pins { 1123 cmd-pins {
1130 pins 1124 pins = "sdc2_cmd";
1131 bias- 1125 bias-pull-up;
1132 drive 1126 drive-strength = <10>;
1133 }; 1127 };
1134 1128
1135 data-pins { 1129 data-pins {
1136 pins 1130 pins = "sdc2_data";
1137 bias- 1131 bias-pull-up;
1138 drive 1132 drive-strength = <10>;
1139 }; 1133 };
1140 }; 1134 };
1141 1135
1142 sdc2_sleep: sdc2-slee 1136 sdc2_sleep: sdc2-sleep-state {
1143 clk-pins { 1137 clk-pins {
1144 pins 1138 pins = "sdc2_clk";
1145 bias- 1139 bias-disable;
1146 drive 1140 drive-strength = <2>;
1147 }; 1141 };
1148 1142
1149 cmd-pins { 1143 cmd-pins {
1150 pins 1144 pins = "sdc2_cmd";
1151 bias- 1145 bias-pull-up;
1152 drive 1146 drive-strength = <2>;
1153 }; 1147 };
1154 1148
1155 data-pins { 1149 data-pins {
1156 pins 1150 pins = "sdc2_data";
1157 bias- 1151 bias-pull-up;
1158 drive 1152 drive-strength = <2>;
1159 }; 1153 };
1160 }; 1154 };
1161 1155
1162 wcss_wlan_default: wc 1156 wcss_wlan_default: wcss-wlan-default-state {
1163 pins = "gpio4 1157 pins = "gpio40", "gpio41", "gpio42", "gpio43", "gpio44";
1164 function = "w 1158 function = "wcss_wlan";
1165 drive-strengt 1159 drive-strength = <6>;
1166 bias-pull-up; 1160 bias-pull-up;
1167 }; 1161 };
1168 }; 1162 };
1169 1163
1170 gcc: clock-controller@1800000 1164 gcc: clock-controller@1800000 {
1171 compatible = "qcom,gc 1165 compatible = "qcom,gcc-msm8939";
1172 reg = <0x01800000 0x8 1166 reg = <0x01800000 0x80000>;
1173 clocks = <&rpmcc RPM_ 1167 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
1174 <&sleep_clk> 1168 <&sleep_clk>,
1175 <&mdss_dsi0_ 1169 <&mdss_dsi0_phy 1>,
1176 <&mdss_dsi0_ 1170 <&mdss_dsi0_phy 0>,
1177 <0>, 1171 <0>,
1178 <0>, 1172 <0>,
1179 <0>; 1173 <0>;
1180 clock-names = "xo", 1174 clock-names = "xo",
1181 "sleep_ 1175 "sleep_clk",
1182 "dsi0pl 1176 "dsi0pll",
1183 "dsi0pl 1177 "dsi0pllbyte",
1184 "ext_mc 1178 "ext_mclk",
1185 "ext_pr 1179 "ext_pri_i2s",
1186 "ext_se 1180 "ext_sec_i2s";
1187 #clock-cells = <1>; 1181 #clock-cells = <1>;
1188 #reset-cells = <1>; 1182 #reset-cells = <1>;
1189 #power-domain-cells = 1183 #power-domain-cells = <1>;
1190 }; 1184 };
1191 1185
1192 tcsr_mutex: hwlock@1905000 { 1186 tcsr_mutex: hwlock@1905000 {
1193 compatible = "qcom,tc 1187 compatible = "qcom,tcsr-mutex";
1194 reg = <0x01905000 0x2 1188 reg = <0x01905000 0x20000>;
1195 #hwlock-cells = <1>; 1189 #hwlock-cells = <1>;
1196 }; 1190 };
1197 1191
1198 tcsr: syscon@1937000 { 1192 tcsr: syscon@1937000 {
1199 compatible = "qcom,tc 1193 compatible = "qcom,tcsr-msm8916", "syscon";
1200 reg = <0x01937000 0x3 1194 reg = <0x01937000 0x30000>;
1201 }; 1195 };
1202 1196
1203 mdss: display-subsystem@1a000 1197 mdss: display-subsystem@1a00000 {
1204 compatible = "qcom,md 1198 compatible = "qcom,mdss";
1205 reg = <0x01a00000 0x1 1199 reg = <0x01a00000 0x1000>,
1206 <0x01ac8000 0x3 1200 <0x01ac8000 0x3000>;
1207 reg-names = "mdss_phy 1201 reg-names = "mdss_phys", "vbif_phys";
1208 1202
1209 interrupts = <GIC_SPI 1203 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1210 interrupt-controller; 1204 interrupt-controller;
1211 1205
1212 clocks = <&gcc GCC_MD 1206 clocks = <&gcc GCC_MDSS_AHB_CLK>,
1213 <&gcc GCC_MD 1207 <&gcc GCC_MDSS_AXI_CLK>,
1214 <&gcc GCC_MD 1208 <&gcc GCC_MDSS_VSYNC_CLK>;
1215 clock-names = "iface" 1209 clock-names = "iface",
1216 "bus", 1210 "bus",
1217 "vsync" 1211 "vsync";
1218 1212
1219 power-domains = <&gcc 1213 power-domains = <&gcc MDSS_GDSC>;
1220 1214
1221 #address-cells = <1>; 1215 #address-cells = <1>;
1222 #size-cells = <1>; 1216 #size-cells = <1>;
1223 #interrupt-cells = <1 1217 #interrupt-cells = <1>;
1224 ranges; 1218 ranges;
1225 1219
1226 status = "disabled"; 1220 status = "disabled";
1227 1221
1228 mdss_mdp: display-con 1222 mdss_mdp: display-controller@1a01000 {
1229 compatible = 1223 compatible = "qcom,mdp5";
1230 reg = <0x01a0 1224 reg = <0x01a01000 0x89000>;
1231 reg-names = " 1225 reg-names = "mdp_phys";
1232 1226
1233 interrupt-par 1227 interrupt-parent = <&mdss>;
1234 interrupts = 1228 interrupts = <0>;
1235 1229
1236 clocks = <&gc 1230 clocks = <&gcc GCC_MDSS_AHB_CLK>,
1237 <&gc 1231 <&gcc GCC_MDSS_AXI_CLK>,
1238 <&gc 1232 <&gcc GCC_MDSS_MDP_CLK>,
1239 <&gc 1233 <&gcc GCC_MDSS_VSYNC_CLK>;
1240 clock-names = 1234 clock-names = "iface",
1241 1235 "bus",
1242 1236 "core",
1243 1237 "vsync";
1244 1238
1245 iommus = <&ap 1239 iommus = <&apps_iommu 4>;
1246 1240
1247 interconnects 1241 interconnects = <&snoc_mm MASTER_MDP_PORT0 &bimc SLAVE_EBI_CH0>,
1248 1242 <&snoc_mm MASTER_MDP_PORT1 &bimc SLAVE_EBI_CH0>;
1249 interconnect- 1243 interconnect-names = "mdp0-mem", "mdp1-mem";
1250 1244
1251 ports { 1245 ports {
1252 #addr 1246 #address-cells = <1>;
1253 #size 1247 #size-cells = <0>;
1254 1248
1255 port@ 1249 port@0 {
1256 1250 reg = <0>;
1257 1251 mdss_mdp_intf1_out: endpoint {
1258 1252 remote-endpoint = <&mdss_dsi0_in>;
1259 1253 };
1260 }; 1254 };
1261 1255
1262 port@ 1256 port@1 {
1263 1257 reg = <1>;
1264 1258 mdss_mdp_intf2_out: endpoint {
1265 1259 remote-endpoint = <&mdss_dsi1_in>;
1266 1260 };
1267 }; 1261 };
1268 }; 1262 };
1269 }; 1263 };
1270 1264
1271 mdss_dsi0: dsi@1a9800 1265 mdss_dsi0: dsi@1a98000 {
1272 compatible = 1266 compatible = "qcom,msm8916-dsi-ctrl",
1273 1267 "qcom,mdss-dsi-ctrl";
1274 reg = <0x01a9 1268 reg = <0x01a98000 0x25c>;
1275 reg-names = " 1269 reg-names = "dsi_ctrl";
1276 1270
1277 interrupt-par 1271 interrupt-parent = <&mdss>;
1278 interrupts = 1272 interrupts = <4>;
1279 1273
1280 clocks = <&gc 1274 clocks = <&gcc GCC_MDSS_MDP_CLK>,
1281 <&gc 1275 <&gcc GCC_MDSS_AHB_CLK>,
1282 <&gc 1276 <&gcc GCC_MDSS_AXI_CLK>,
1283 <&gc 1277 <&gcc GCC_MDSS_BYTE0_CLK>,
1284 <&gc 1278 <&gcc GCC_MDSS_PCLK0_CLK>,
1285 <&gc 1279 <&gcc GCC_MDSS_ESC0_CLK>;
1286 clock-names = 1280 clock-names = "mdp_core",
1287 1281 "iface",
1288 1282 "bus",
1289 1283 "byte",
1290 1284 "pixel",
1291 1285 "core";
1292 assigned-cloc 1286 assigned-clocks = <&gcc BYTE0_CLK_SRC>,
1293 1287 <&gcc PCLK0_CLK_SRC>;
1294 assigned-cloc 1288 assigned-clock-parents = <&mdss_dsi0_phy 0>,
1295 1289 <&mdss_dsi0_phy 1>;
1296 1290
1297 phys = <&mdss 1291 phys = <&mdss_dsi0_phy>;
1298 status = "dis 1292 status = "disabled";
1299 1293
1300 #address-cell 1294 #address-cells = <1>;
1301 #size-cells = 1295 #size-cells = <0>;
1302 1296
1303 ports { 1297 ports {
1304 #addr 1298 #address-cells = <1>;
1305 #size 1299 #size-cells = <0>;
1306 1300
1307 port@ 1301 port@0 {
1308 1302 reg = <0>;
1309 1303 mdss_dsi0_in: endpoint {
1310 1304 remote-endpoint = <&mdss_mdp_intf1_out>;
1311 1305 };
1312 }; 1306 };
1313 1307
1314 port@ 1308 port@1 {
1315 1309 reg = <1>;
1316 1310 mdss_dsi0_out: endpoint {
1317 1311 };
1318 }; 1312 };
1319 }; 1313 };
1320 }; 1314 };
1321 1315
1322 mdss_dsi0_phy: phy@1a 1316 mdss_dsi0_phy: phy@1a98300 {
1323 compatible = 1317 compatible = "qcom,dsi-phy-28nm-lp";
1324 reg = <0x01a9 1318 reg = <0x01a98300 0xd4>,
1325 <0x01a9 1319 <0x01a98500 0x280>,
1326 <0x01a9 1320 <0x01a98780 0x30>;
1327 reg-names = " 1321 reg-names = "dsi_pll",
1328 " 1322 "dsi_phy",
1329 " 1323 "dsi_phy_regulator";
1330 1324
1331 clocks = <&gc 1325 clocks = <&gcc GCC_MDSS_AHB_CLK>,
1332 <&rp 1326 <&rpmcc RPM_SMD_XO_CLK_SRC>;
1333 clock-names = 1327 clock-names = "iface", "ref";
1334 1328
1335 #clock-cells 1329 #clock-cells = <1>;
1336 #phy-cells = 1330 #phy-cells = <0>;
1337 status = "dis 1331 status = "disabled";
1338 }; 1332 };
1339 1333
1340 mdss_dsi1: dsi@1aa000 1334 mdss_dsi1: dsi@1aa0000 {
1341 compatible = 1335 compatible = "qcom,msm8916-dsi-ctrl",
1342 1336 "qcom,mdss-dsi-ctrl";
1343 reg = <0x01aa 1337 reg = <0x01aa0000 0x25c>;
1344 reg-names = " 1338 reg-names = "dsi_ctrl";
1345 1339
1346 interrupt-par 1340 interrupt-parent = <&mdss>;
1347 interrupts = 1341 interrupts = <5>;
1348 1342
1349 clocks = <&gc 1343 clocks = <&gcc GCC_MDSS_MDP_CLK>,
1350 <&gc 1344 <&gcc GCC_MDSS_AHB_CLK>,
1351 <&gc 1345 <&gcc GCC_MDSS_AXI_CLK>,
1352 <&gc 1346 <&gcc GCC_MDSS_BYTE1_CLK>,
1353 <&gc 1347 <&gcc GCC_MDSS_PCLK1_CLK>,
1354 <&gc 1348 <&gcc GCC_MDSS_ESC1_CLK>;
1355 clock-names = 1349 clock-names = "mdp_core",
1356 1350 "iface",
1357 1351 "bus",
1358 1352 "byte",
1359 1353 "pixel",
1360 1354 "core";
1361 assigned-cloc 1355 assigned-clocks = <&gcc BYTE1_CLK_SRC>,
1362 1356 <&gcc PCLK1_CLK_SRC>;
1363 assigned-cloc 1357 assigned-clock-parents = <&mdss_dsi0_phy 0>,
1364 1358 <&mdss_dsi0_phy 1>;
1365 phys = <&mdss 1359 phys = <&mdss_dsi1_phy>;
1366 status = "dis 1360 status = "disabled";
1367 1361
1368 ports { 1362 ports {
1369 #addr 1363 #address-cells = <1>;
1370 #size 1364 #size-cells = <0>;
1371 1365
1372 port@ 1366 port@0 {
1373 1367 reg = <0>;
1374 1368 mdss_dsi1_in: endpoint {
1375 1369 remote-endpoint = <&mdss_mdp_intf2_out>;
1376 1370 };
1377 }; 1371 };
1378 1372
1379 port@ 1373 port@1 {
1380 1374 reg = <1>;
1381 1375 mdss_dsi1_out: endpoint {
1382 1376 };
1383 }; 1377 };
1384 }; 1378 };
1385 }; 1379 };
1386 1380
1387 mdss_dsi1_phy: phy@1a 1381 mdss_dsi1_phy: phy@1aa0300 {
1388 compatible = 1382 compatible = "qcom,dsi-phy-28nm-lp";
1389 reg = <0x01aa 1383 reg = <0x01aa0300 0xd4>,
1390 <0x01aa 1384 <0x01aa0500 0x280>,
1391 <0x01aa 1385 <0x01aa0780 0x30>;
1392 reg-names = " 1386 reg-names = "dsi_pll",
1393 " 1387 "dsi_phy",
1394 " 1388 "dsi_phy_regulator";
1395 1389
1396 clocks = <&gc 1390 clocks = <&gcc GCC_MDSS_AHB_CLK>,
1397 <&rp 1391 <&rpmcc RPM_SMD_XO_CLK_SRC>;
1398 clock-names = 1392 clock-names = "iface", "ref";
1399 1393
1400 #clock-cells 1394 #clock-cells = <1>;
1401 #phy-cells = 1395 #phy-cells = <0>;
1402 status = "dis 1396 status = "disabled";
1403 }; 1397 };
1404 }; 1398 };
1405 1399
1406 gpu: gpu@1c00000 { !! 1400 gpu@1c00000 {
1407 compatible = "qcom,ad 1401 compatible = "qcom,adreno-405.0", "qcom,adreno";
1408 reg = <0x01c00000 0x1 1402 reg = <0x01c00000 0x10000>;
1409 reg-names = "kgsl_3d0 1403 reg-names = "kgsl_3d0_reg_memory";
1410 interrupts = <GIC_SPI 1404 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
1411 interrupt-names = "kg 1405 interrupt-names = "kgsl_3d0_irq";
1412 clock-names = "core", 1406 clock-names = "core",
1413 "iface" 1407 "iface",
1414 "mem", 1408 "mem",
1415 "mem_if 1409 "mem_iface",
1416 "alt_me 1410 "alt_mem_iface",
1417 "gfx3d" 1411 "gfx3d",
1418 "rbbmti 1412 "rbbmtimer";
1419 clocks = <&gcc GCC_OX 1413 clocks = <&gcc GCC_OXILI_GFX3D_CLK>,
1420 <&gcc GCC_OX 1414 <&gcc GCC_OXILI_AHB_CLK>,
1421 <&gcc GCC_OX 1415 <&gcc GCC_OXILI_GMEM_CLK>,
1422 <&gcc GCC_BI 1416 <&gcc GCC_BIMC_GFX_CLK>,
1423 <&gcc GCC_BI 1417 <&gcc GCC_BIMC_GPU_CLK>,
1424 <&gcc GFX3D_ 1418 <&gcc GFX3D_CLK_SRC>,
1425 <&gcc GCC_OX 1419 <&gcc GCC_OXILI_TIMER_CLK>;
1426 power-domains = <&gcc 1420 power-domains = <&gcc OXILI_GDSC>;
1427 operating-points-v2 = 1421 operating-points-v2 = <&opp_table>;
1428 iommus = <&gpu_iommu 1422 iommus = <&gpu_iommu 1>, <&gpu_iommu 2>;
1429 #cooling-cells = <2>; <<
1430 <<
1431 status = "disabled"; <<
1432 1423
1433 opp_table: opp-table 1424 opp_table: opp-table {
1434 compatible = 1425 compatible = "operating-points-v2";
1435 1426
1436 opp-550000000 1427 opp-550000000 {
1437 opp-h 1428 opp-hz = /bits/ 64 <550000000>;
1438 }; 1429 };
1439 1430
1440 opp-465000000 1431 opp-465000000 {
1441 opp-h 1432 opp-hz = /bits/ 64 <465000000>;
1442 }; 1433 };
1443 1434
1444 opp-400000000 1435 opp-400000000 {
1445 opp-h 1436 opp-hz = /bits/ 64 <400000000>;
1446 }; 1437 };
1447 1438
1448 opp-220000000 1439 opp-220000000 {
1449 opp-h 1440 opp-hz = /bits/ 64 <220000000>;
1450 }; 1441 };
1451 1442
1452 opp-19200000 1443 opp-19200000 {
1453 opp-h 1444 opp-hz = /bits/ 64 <19200000>;
1454 }; 1445 };
1455 }; 1446 };
1456 }; 1447 };
1457 1448
1458 apps_iommu: iommu@1ef0000 { 1449 apps_iommu: iommu@1ef0000 {
1459 compatible = "qcom,ms 1450 compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
1460 reg = <0x01ef0000 0x3 1451 reg = <0x01ef0000 0x3000>;
1461 ranges = <0 0x01e2000 1452 ranges = <0 0x01e20000 0x20000>;
1462 clocks = <&gcc GCC_SM 1453 clocks = <&gcc GCC_SMMU_CFG_CLK>,
1463 <&gcc GCC_AP 1454 <&gcc GCC_APSS_TCU_CLK>;
1464 clock-names = "iface" 1455 clock-names = "iface", "bus";
1465 #address-cells = <1>; 1456 #address-cells = <1>;
1466 #size-cells = <1>; 1457 #size-cells = <1>;
1467 #iommu-cells = <1>; 1458 #iommu-cells = <1>;
1468 qcom,iommu-secure-id 1459 qcom,iommu-secure-id = <17>;
1469 1460
1470 /* mdp_0: */ 1461 /* mdp_0: */
1471 iommu-ctx@4000 { 1462 iommu-ctx@4000 {
1472 compatible = 1463 compatible = "qcom,msm-iommu-v1-ns";
1473 reg = <0x4000 1464 reg = <0x4000 0x1000>;
1474 interrupts = 1465 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
1475 }; 1466 };
1476 1467
1477 /* venus_ns: */ 1468 /* venus_ns: */
1478 iommu-ctx@5000 { 1469 iommu-ctx@5000 {
1479 compatible = 1470 compatible = "qcom,msm-iommu-v1-sec";
1480 reg = <0x5000 1471 reg = <0x5000 0x1000>;
1481 interrupts = 1472 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
1482 }; 1473 };
1483 }; 1474 };
1484 1475
1485 gpu_iommu: iommu@1f08000 { 1476 gpu_iommu: iommu@1f08000 {
1486 compatible = "qcom,ms 1477 compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
1487 ranges = <0 0x1f08000 1478 ranges = <0 0x1f08000 0x10000>;
1488 clocks = <&gcc GCC_SM 1479 clocks = <&gcc GCC_SMMU_CFG_CLK>,
1489 <&gcc GCC_GF 1480 <&gcc GCC_GFX_TCU_CLK>,
1490 <&gcc GCC_GF 1481 <&gcc GCC_GFX_TBU_CLK>;
1491 clock-names = "iface" 1482 clock-names = "iface", "bus", "tbu";
1492 #address-cells = <1>; 1483 #address-cells = <1>;
1493 #size-cells = <1>; 1484 #size-cells = <1>;
1494 #iommu-cells = <1>; 1485 #iommu-cells = <1>;
1495 qcom,iommu-secure-id 1486 qcom,iommu-secure-id = <18>;
1496 1487
1497 /* gfx3d_user: */ 1488 /* gfx3d_user: */
1498 iommu-ctx@1000 { 1489 iommu-ctx@1000 {
1499 compatible = 1490 compatible = "qcom,msm-iommu-v1-ns";
1500 reg = <0x1000 1491 reg = <0x1000 0x1000>;
1501 interrupts = 1492 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
1502 }; 1493 };
1503 1494
1504 /* gfx3d_priv: */ 1495 /* gfx3d_priv: */
1505 iommu-ctx@2000 { 1496 iommu-ctx@2000 {
1506 compatible = 1497 compatible = "qcom,msm-iommu-v1-ns";
1507 reg = <0x2000 1498 reg = <0x2000 0x1000>;
1508 interrupts = 1499 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
1509 }; 1500 };
1510 }; 1501 };
1511 1502
1512 spmi_bus: spmi@200f000 { 1503 spmi_bus: spmi@200f000 {
1513 compatible = "qcom,sp 1504 compatible = "qcom,spmi-pmic-arb";
1514 reg = <0x0200f000 0x0 1505 reg = <0x0200f000 0x001000>,
1515 <0x02400000 0x4 1506 <0x02400000 0x400000>,
1516 <0x02c00000 0x4 1507 <0x02c00000 0x400000>,
1517 <0x03800000 0x2 1508 <0x03800000 0x200000>,
1518 <0x0200a000 0x0 1509 <0x0200a000 0x002100>;
1519 reg-names = "core", " 1510 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1520 interrupt-names = "pe 1511 interrupt-names = "periph_irq";
1521 interrupts = <GIC_SPI 1512 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
1522 qcom,ee = <0>; 1513 qcom,ee = <0>;
1523 qcom,channel = <0>; 1514 qcom,channel = <0>;
1524 #address-cells = <2>; 1515 #address-cells = <2>;
1525 #size-cells = <0>; 1516 #size-cells = <0>;
1526 interrupt-controller; 1517 interrupt-controller;
1527 #interrupt-cells = <4 1518 #interrupt-cells = <4>;
1528 }; 1519 };
1529 1520
1530 bam_dmux_dma: dma-controller@ <<
1531 compatible = "qcom,ba <<
1532 reg = <0x04044000 0x1 <<
1533 interrupts = <GIC_SPI <<
1534 #dma-cells = <1>; <<
1535 qcom,ee = <0>; <<
1536 <<
1537 num-channels = <6>; <<
1538 qcom,num-ees = <1>; <<
1539 qcom,powered-remotely <<
1540 <<
1541 status = "disabled"; <<
1542 }; <<
1543 <<
1544 mpss: remoteproc@4080000 { 1521 mpss: remoteproc@4080000 {
1545 compatible = "qcom,ms 1522 compatible = "qcom,msm8916-mss-pil";
1546 reg = <0x04080000 0x1 1523 reg = <0x04080000 0x100>, <0x04020000 0x040>;
1547 reg-names = "qdsp6", 1524 reg-names = "qdsp6", "rmb";
1548 interrupts-extended = 1525 interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>,
1549 1526 <&hexagon_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1550 1527 <&hexagon_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1551 1528 <&hexagon_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1552 1529 <&hexagon_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1553 interrupt-names = "wd 1530 interrupt-names = "wdog",
1554 "fa 1531 "fatal",
1555 "re 1532 "ready",
1556 "ha 1533 "handover",
1557 "st 1534 "stop-ack";
1558 clocks = <&gcc GCC_MS 1535 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
1559 <&gcc GCC_MS 1536 <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>,
1560 <&gcc GCC_BO 1537 <&gcc GCC_BOOT_ROM_AHB_CLK>,
1561 <&rpmcc RPM_ 1538 <&rpmcc RPM_SMD_XO_CLK_SRC>;
1562 clock-names = "iface" 1539 clock-names = "iface",
1563 "bus", 1540 "bus",
1564 "mem", 1541 "mem",
1565 "xo"; 1542 "xo";
1566 power-domains = <&rpm 1543 power-domains = <&rpmpd MSM8939_VDDMDCX>,
1567 <&rpm 1544 <&rpmpd MSM8939_VDDMX>;
1568 power-domain-names = 1545 power-domain-names = "cx", "mx";
1569 qcom,smem-states = <& 1546 qcom,smem-states = <&hexagon_smp2p_out 0>;
1570 qcom,smem-state-names 1547 qcom,smem-state-names = "stop";
1571 resets = <&scm 0>; 1548 resets = <&scm 0>;
1572 reset-names = "mss_re 1549 reset-names = "mss_restart";
1573 qcom,halt-regs = <&tc 1550 qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>;
1574 status = "disabled"; 1551 status = "disabled";
1575 1552
1576 bam_dmux: bam-dmux { <<
1577 compatible = <<
1578 <<
1579 interrupt-par <<
1580 interrupts = <<
1581 interrupt-nam <<
1582 <<
1583 qcom,smem-sta <<
1584 qcom,smem-sta <<
1585 <<
1586 dmas = <&bam_ <<
1587 dma-names = " <<
1588 <<
1589 status = "dis <<
1590 }; <<
1591 <<
1592 mba { 1553 mba {
1593 memory-region 1554 memory-region = <&mba_mem>;
1594 }; 1555 };
1595 1556
1596 mpss { 1557 mpss {
1597 memory-region 1558 memory-region = <&mpss_mem>;
1598 }; 1559 };
1599 1560
1600 smd-edge { 1561 smd-edge {
1601 interrupts = 1562 interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>;
1602 1563
1603 qcom,smd-edge 1564 qcom,smd-edge = <0>;
1604 mboxes = <&ap 1565 mboxes = <&apcs1_mbox 12>;
1605 qcom,remote-p 1566 qcom,remote-pid = <1>;
1606 1567
1607 label = "hexa 1568 label = "hexagon";
1608 <<
1609 apr: apr { <<
1610 compa <<
1611 qcom, <<
1612 qcom, <<
1613 #addr <<
1614 #size <<
1615 statu <<
1616 <<
1617 q6cor <<
1618 <<
1619 <<
1620 }; <<
1621 <<
1622 q6afe <<
1623 <<
1624 <<
1625 <<
1626 <<
1627 <<
1628 <<
1629 <<
1630 <<
1631 <<
1632 }; <<
1633 <<
1634 q6asm <<
1635 <<
1636 <<
1637 <<
1638 <<
1639 <<
1640 <<
1641 <<
1642 <<
1643 <<
1644 }; <<
1645 <<
1646 q6adm <<
1647 <<
1648 <<
1649 <<
1650 <<
1651 <<
1652 <<
1653 <<
1654 }; <<
1655 }; <<
1656 }; 1569 };
1657 }; 1570 };
1658 1571
1659 sound: sound@7702000 { 1572 sound: sound@7702000 {
1660 compatible = "qcom,ap 1573 compatible = "qcom,apq8016-sbc-sndcard";
1661 reg = <0x07702000 0x4 1574 reg = <0x07702000 0x4>,
1662 <0x07702004 0x4 1575 <0x07702004 0x4>;
1663 reg-names = "mic-iomu 1576 reg-names = "mic-iomux", "spkr-iomux";
1664 status = "disabled"; 1577 status = "disabled";
1665 }; 1578 };
1666 1579
1667 lpass: audio-controller@77080 1580 lpass: audio-controller@7708000 {
1668 compatible = "qcom,ap 1581 compatible = "qcom,apq8016-lpass-cpu";
1669 reg = <0x07708000 0x1 1582 reg = <0x07708000 0x10000>;
1670 reg-names = "lpass-lp 1583 reg-names = "lpass-lpaif";
1671 interrupts = <GIC_SPI 1584 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
1672 interrupt-names = "lp 1585 interrupt-names = "lpass-irq-lpaif";
1673 clocks = <&gcc GCC_UL 1586 clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
1674 <&gcc GCC_UL 1587 <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>,
1675 <&gcc GCC_UL 1588 <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>,
1676 <&gcc GCC_UL 1589 <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>,
1677 <&gcc GCC_UL 1590 <&gcc GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK>,
1678 <&gcc GCC_UL 1591 <&gcc GCC_ULTAUDIO_PCNOC_MPORT_CLK>,
1679 <&gcc GCC_UL 1592 <&gcc GCC_ULTAUDIO_PCNOC_SWAY_CLK>;
1680 clock-names = "ahbix- 1593 clock-names = "ahbix-clk",
1681 "mi2s-b 1594 "mi2s-bit-clk0",
1682 "mi2s-b 1595 "mi2s-bit-clk1",
1683 "mi2s-b 1596 "mi2s-bit-clk2",
1684 "mi2s-b 1597 "mi2s-bit-clk3",
1685 "pcnoc- 1598 "pcnoc-mport-clk",
1686 "pcnoc- 1599 "pcnoc-sway-clk";
1687 #sound-dai-cells = <1 1600 #sound-dai-cells = <1>;
1688 #address-cells = <1>; 1601 #address-cells = <1>;
1689 #size-cells = <0>; 1602 #size-cells = <0>;
1690 status = "disabled"; 1603 status = "disabled";
1691 }; 1604 };
1692 1605
1693 lpass_codec: audio-codec@771c 1606 lpass_codec: audio-codec@771c000 {
1694 compatible = "qcom,ms 1607 compatible = "qcom,msm8916-wcd-digital-codec";
1695 reg = <0x0771c000 0x4 1608 reg = <0x0771c000 0x400>;
1696 clocks = <&gcc GCC_UL 1609 clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
1697 <&gcc GCC_CO 1610 <&gcc GCC_CODEC_DIGCODEC_CLK>;
1698 clock-names = "ahbix- 1611 clock-names = "ahbix-clk", "mclk";
1699 #sound-dai-cells = <1 1612 #sound-dai-cells = <1>;
1700 status = "disabled"; 1613 status = "disabled";
1701 }; 1614 };
1702 1615
1703 sdhc_1: mmc@7824900 { 1616 sdhc_1: mmc@7824900 {
1704 compatible = "qcom,ms 1617 compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4";
1705 reg = <0x07824900 0x1 1618 reg = <0x07824900 0x11c>, <0x07824000 0x800>;
1706 reg-names = "hc", "co 1619 reg-names = "hc", "core";
1707 1620
1708 interrupts = <GIC_SPI 1621 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1709 <GIC_SPI 1622 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
1710 interrupt-names = "hc 1623 interrupt-names = "hc_irq", "pwr_irq";
1711 clocks = <&gcc GCC_SD 1624 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
1712 <&gcc GCC_SD 1625 <&gcc GCC_SDCC1_APPS_CLK>,
1713 <&rpmcc RPM_ 1626 <&rpmcc RPM_SMD_XO_CLK_SRC>;
1714 clock-names = "iface" 1627 clock-names = "iface", "core", "xo";
1715 resets = <&gcc GCC_SD 1628 resets = <&gcc GCC_SDCC1_BCR>;
1716 pinctrl-0 = <&sdc1_de 1629 pinctrl-0 = <&sdc1_default>;
1717 pinctrl-1 = <&sdc1_sl 1630 pinctrl-1 = <&sdc1_sleep>;
1718 pinctrl-names = "defa 1631 pinctrl-names = "default", "sleep";
1719 mmc-ddr-1_8v; 1632 mmc-ddr-1_8v;
1720 bus-width = <8>; 1633 bus-width = <8>;
1721 non-removable; 1634 non-removable;
1722 status = "disabled"; 1635 status = "disabled";
1723 }; 1636 };
1724 1637
1725 sdhc_2: mmc@7864900 { 1638 sdhc_2: mmc@7864900 {
1726 compatible = "qcom,ms 1639 compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4";
1727 reg = <0x07864900 0x1 1640 reg = <0x07864900 0x11c>, <0x07864000 0x800>;
1728 reg-names = "hc", "co 1641 reg-names = "hc", "core";
1729 1642
1730 interrupts = <GIC_SPI 1643 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1731 <GIC_SPI 1644 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
1732 interrupt-names = "hc 1645 interrupt-names = "hc_irq", "pwr_irq";
1733 clocks = <&gcc GCC_SD 1646 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
1734 <&gcc GCC_SD 1647 <&gcc GCC_SDCC2_APPS_CLK>,
1735 <&rpmcc RPM_ 1648 <&rpmcc RPM_SMD_XO_CLK_SRC>;
1736 clock-names = "iface" 1649 clock-names = "iface", "core", "xo";
1737 resets = <&gcc GCC_SD 1650 resets = <&gcc GCC_SDCC2_BCR>;
1738 pinctrl-0 = <&sdc2_de 1651 pinctrl-0 = <&sdc2_default>;
1739 pinctrl-1 = <&sdc2_sl 1652 pinctrl-1 = <&sdc2_sleep>;
1740 pinctrl-names = "defa 1653 pinctrl-names = "default", "sleep";
1741 bus-width = <4>; 1654 bus-width = <4>;
1742 status = "disabled"; 1655 status = "disabled";
1743 }; 1656 };
1744 1657
1745 blsp_dma: dma-controller@7884 1658 blsp_dma: dma-controller@7884000 {
1746 compatible = "qcom,ba 1659 compatible = "qcom,bam-v1.7.0";
1747 reg = <0x07884000 0x2 1660 reg = <0x07884000 0x23000>;
1748 interrupts = <GIC_SPI 1661 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
1749 clocks = <&gcc GCC_BL 1662 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
1750 clock-names = "bam_cl 1663 clock-names = "bam_clk";
1751 #dma-cells = <1>; 1664 #dma-cells = <1>;
1752 qcom,ee = <0>; 1665 qcom,ee = <0>;
1753 qcom,controlled-remot <<
1754 }; 1666 };
1755 1667
1756 blsp_uart1: serial@78af000 { 1668 blsp_uart1: serial@78af000 {
1757 compatible = "qcom,ms 1669 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1758 reg = <0x078af000 0x2 1670 reg = <0x078af000 0x200>;
1759 interrupts = <GIC_SPI 1671 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1760 clocks = <&gcc GCC_BL 1672 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
1761 clock-names = "core", 1673 clock-names = "core", "iface";
1762 dmas = <&blsp_dma 0>, 1674 dmas = <&blsp_dma 0>, <&blsp_dma 1>;
1763 dma-names = "tx", "rx 1675 dma-names = "tx", "rx";
1764 pinctrl-0 = <&blsp_ua 1676 pinctrl-0 = <&blsp_uart1_default>;
1765 pinctrl-1 = <&blsp_ua 1677 pinctrl-1 = <&blsp_uart1_sleep>;
1766 pinctrl-names = "defa 1678 pinctrl-names = "default", "sleep";
1767 status = "disabled"; 1679 status = "disabled";
1768 }; 1680 };
1769 1681
1770 blsp_uart2: serial@78b0000 { 1682 blsp_uart2: serial@78b0000 {
1771 compatible = "qcom,ms 1683 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1772 reg = <0x078b0000 0x2 1684 reg = <0x078b0000 0x200>;
1773 interrupts = <GIC_SPI 1685 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1774 clocks = <&gcc GCC_BL 1686 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
1775 clock-names = "core", 1687 clock-names = "core", "iface";
1776 dmas = <&blsp_dma 2>, 1688 dmas = <&blsp_dma 2>, <&blsp_dma 3>;
1777 dma-names = "tx", "rx 1689 dma-names = "tx", "rx";
1778 pinctrl-0 = <&blsp_ua 1690 pinctrl-0 = <&blsp_uart2_default>;
1779 pinctrl-1 = <&blsp_ua 1691 pinctrl-1 = <&blsp_uart2_sleep>;
1780 pinctrl-names = "defa 1692 pinctrl-names = "default", "sleep";
1781 status = "disabled"; 1693 status = "disabled";
1782 }; 1694 };
1783 1695
1784 blsp_i2c1: i2c@78b5000 { 1696 blsp_i2c1: i2c@78b5000 {
1785 compatible = "qcom,i2 1697 compatible = "qcom,i2c-qup-v2.2.1";
1786 reg = <0x078b5000 0x5 1698 reg = <0x078b5000 0x500>;
1787 interrupts = <GIC_SPI 1699 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
1788 clocks = <&gcc GCC_BL 1700 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
1789 <&gcc GCC_BL 1701 <&gcc GCC_BLSP1_AHB_CLK>;
1790 clock-names = "core", 1702 clock-names = "core", "iface";
1791 dmas = <&blsp_dma 4>, 1703 dmas = <&blsp_dma 4>, <&blsp_dma 5>;
1792 dma-names = "tx", "rx 1704 dma-names = "tx", "rx";
1793 pinctrl-0 = <&blsp_i2 1705 pinctrl-0 = <&blsp_i2c1_default>;
1794 pinctrl-1 = <&blsp_i2 1706 pinctrl-1 = <&blsp_i2c1_sleep>;
1795 pinctrl-names = "defa 1707 pinctrl-names = "default", "sleep";
1796 #address-cells = <1>; 1708 #address-cells = <1>;
1797 #size-cells = <0>; 1709 #size-cells = <0>;
1798 status = "disabled"; 1710 status = "disabled";
1799 }; 1711 };
1800 1712
1801 blsp_spi1: spi@78b5000 { 1713 blsp_spi1: spi@78b5000 {
1802 compatible = "qcom,sp 1714 compatible = "qcom,spi-qup-v2.2.1";
1803 reg = <0x078b5000 0x5 1715 reg = <0x078b5000 0x500>;
1804 interrupts = <GIC_SPI 1716 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
1805 clocks = <&gcc GCC_BL 1717 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
1806 <&gcc GCC_BL 1718 <&gcc GCC_BLSP1_AHB_CLK>;
1807 clock-names = "core", 1719 clock-names = "core", "iface";
1808 dmas = <&blsp_dma 4>, 1720 dmas = <&blsp_dma 4>, <&blsp_dma 5>;
1809 dma-names = "tx", "rx 1721 dma-names = "tx", "rx";
1810 pinctrl-0 = <&blsp_sp 1722 pinctrl-0 = <&blsp_spi1_default>;
1811 pinctrl-1 = <&blsp_sp 1723 pinctrl-1 = <&blsp_spi1_sleep>;
1812 pinctrl-names = "defa 1724 pinctrl-names = "default", "sleep";
1813 #address-cells = <1>; 1725 #address-cells = <1>;
1814 #size-cells = <0>; 1726 #size-cells = <0>;
1815 status = "disabled"; 1727 status = "disabled";
1816 }; 1728 };
1817 1729
1818 blsp_i2c2: i2c@78b6000 { 1730 blsp_i2c2: i2c@78b6000 {
1819 compatible = "qcom,i2 1731 compatible = "qcom,i2c-qup-v2.2.1";
1820 reg = <0x078b6000 0x5 1732 reg = <0x078b6000 0x500>;
1821 interrupts = <GIC_SPI 1733 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1822 clocks = <&gcc GCC_BL 1734 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
1823 <&gcc GCC_BL 1735 <&gcc GCC_BLSP1_AHB_CLK>;
1824 clock-names = "core", 1736 clock-names = "core", "iface";
1825 dmas = <&blsp_dma 6>, 1737 dmas = <&blsp_dma 6>, <&blsp_dma 7>;
1826 dma-names = "tx", "rx 1738 dma-names = "tx", "rx";
1827 pinctrl-0 = <&blsp_i2 1739 pinctrl-0 = <&blsp_i2c2_default>;
1828 pinctrl-1 = <&blsp_i2 1740 pinctrl-1 = <&blsp_i2c2_sleep>;
1829 pinctrl-names = "defa 1741 pinctrl-names = "default", "sleep";
1830 #address-cells = <1>; 1742 #address-cells = <1>;
1831 #size-cells = <0>; 1743 #size-cells = <0>;
1832 status = "disabled"; 1744 status = "disabled";
1833 }; 1745 };
1834 1746
1835 blsp_spi2: spi@78b6000 { 1747 blsp_spi2: spi@78b6000 {
1836 compatible = "qcom,sp 1748 compatible = "qcom,spi-qup-v2.2.1";
1837 reg = <0x078b6000 0x5 1749 reg = <0x078b6000 0x500>;
1838 interrupts = <GIC_SPI 1750 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1839 clocks = <&gcc GCC_BL 1751 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
1840 <&gcc GCC_BL 1752 <&gcc GCC_BLSP1_AHB_CLK>;
1841 clock-names = "core", 1753 clock-names = "core", "iface";
1842 dmas = <&blsp_dma 6>, 1754 dmas = <&blsp_dma 6>, <&blsp_dma 7>;
1843 dma-names = "tx", "rx 1755 dma-names = "tx", "rx";
1844 pinctrl-0 = <&blsp_sp 1756 pinctrl-0 = <&blsp_spi2_default>;
1845 pinctrl-1 = <&blsp_sp 1757 pinctrl-1 = <&blsp_spi2_sleep>;
1846 pinctrl-names = "defa 1758 pinctrl-names = "default", "sleep";
1847 #address-cells = <1>; 1759 #address-cells = <1>;
1848 #size-cells = <0>; 1760 #size-cells = <0>;
1849 status = "disabled"; 1761 status = "disabled";
1850 }; 1762 };
1851 1763
1852 blsp_i2c3: i2c@78b7000 { 1764 blsp_i2c3: i2c@78b7000 {
1853 compatible = "qcom,i2 1765 compatible = "qcom,i2c-qup-v2.2.1";
1854 reg = <0x078b7000 0x5 1766 reg = <0x078b7000 0x500>;
1855 interrupts = <GIC_SPI 1767 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1856 clocks = <&gcc GCC_BL 1768 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
1857 <&gcc GCC_BL 1769 <&gcc GCC_BLSP1_AHB_CLK>;
1858 clock-names = "core", 1770 clock-names = "core", "iface";
1859 dmas = <&blsp_dma 8>, 1771 dmas = <&blsp_dma 8>, <&blsp_dma 9>;
1860 dma-names = "tx", "rx 1772 dma-names = "tx", "rx";
1861 pinctrl-0 = <&blsp_i2 1773 pinctrl-0 = <&blsp_i2c3_default>;
1862 pinctrl-1 = <&blsp_i2 1774 pinctrl-1 = <&blsp_i2c3_sleep>;
1863 pinctrl-names = "defa 1775 pinctrl-names = "default", "sleep";
1864 #address-cells = <1>; 1776 #address-cells = <1>;
1865 #size-cells = <0>; 1777 #size-cells = <0>;
1866 status = "disabled"; 1778 status = "disabled";
1867 }; 1779 };
1868 1780
1869 blsp_spi3: spi@78b7000 { 1781 blsp_spi3: spi@78b7000 {
1870 compatible = "qcom,sp 1782 compatible = "qcom,spi-qup-v2.2.1";
1871 reg = <0x078b7000 0x5 1783 reg = <0x078b7000 0x500>;
1872 interrupts = <GIC_SPI 1784 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1873 clocks = <&gcc GCC_BL 1785 clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
1874 <&gcc GCC_BL 1786 <&gcc GCC_BLSP1_AHB_CLK>;
1875 clock-names = "core", 1787 clock-names = "core", "iface";
1876 dmas = <&blsp_dma 8>, 1788 dmas = <&blsp_dma 8>, <&blsp_dma 9>;
1877 dma-names = "tx", "rx 1789 dma-names = "tx", "rx";
1878 pinctrl-0 = <&blsp_sp 1790 pinctrl-0 = <&blsp_spi3_default>;
1879 pinctrl-1 = <&blsp_sp 1791 pinctrl-1 = <&blsp_spi3_sleep>;
1880 pinctrl-names = "defa 1792 pinctrl-names = "default", "sleep";
1881 #address-cells = <1>; 1793 #address-cells = <1>;
1882 #size-cells = <0>; 1794 #size-cells = <0>;
1883 status = "disabled"; 1795 status = "disabled";
1884 }; 1796 };
1885 1797
1886 blsp_i2c4: i2c@78b8000 { 1798 blsp_i2c4: i2c@78b8000 {
1887 compatible = "qcom,i2 1799 compatible = "qcom,i2c-qup-v2.2.1";
1888 reg = <0x078b8000 0x5 1800 reg = <0x078b8000 0x500>;
1889 interrupts = <GIC_SPI 1801 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1890 clocks = <&gcc GCC_BL 1802 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
1891 <&gcc GCC_BL 1803 <&gcc GCC_BLSP1_AHB_CLK>;
1892 clock-names = "core", 1804 clock-names = "core", "iface";
1893 dmas = <&blsp_dma 10> 1805 dmas = <&blsp_dma 10>, <&blsp_dma 11>;
1894 dma-names = "tx", "rx 1806 dma-names = "tx", "rx";
1895 pinctrl-0 = <&blsp_i2 1807 pinctrl-0 = <&blsp_i2c4_default>;
1896 pinctrl-1 = <&blsp_i2 1808 pinctrl-1 = <&blsp_i2c4_sleep>;
1897 pinctrl-names = "defa 1809 pinctrl-names = "default", "sleep";
1898 #address-cells = <1>; 1810 #address-cells = <1>;
1899 #size-cells = <0>; 1811 #size-cells = <0>;
1900 status = "disabled"; 1812 status = "disabled";
1901 }; 1813 };
1902 1814
1903 blsp_spi4: spi@78b8000 { 1815 blsp_spi4: spi@78b8000 {
1904 compatible = "qcom,sp 1816 compatible = "qcom,spi-qup-v2.2.1";
1905 reg = <0x078b8000 0x5 1817 reg = <0x078b8000 0x500>;
1906 interrupts = <GIC_SPI 1818 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1907 clocks = <&gcc GCC_BL 1819 clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
1908 <&gcc GCC_BL 1820 <&gcc GCC_BLSP1_AHB_CLK>;
1909 clock-names = "core", 1821 clock-names = "core", "iface";
1910 dmas = <&blsp_dma 10> 1822 dmas = <&blsp_dma 10>, <&blsp_dma 11>;
1911 dma-names = "tx", "rx 1823 dma-names = "tx", "rx";
1912 pinctrl-0 = <&blsp_sp 1824 pinctrl-0 = <&blsp_spi4_default>;
1913 pinctrl-1 = <&blsp_sp 1825 pinctrl-1 = <&blsp_spi4_sleep>;
1914 pinctrl-names = "defa 1826 pinctrl-names = "default", "sleep";
1915 #address-cells = <1>; 1827 #address-cells = <1>;
1916 #size-cells = <0>; 1828 #size-cells = <0>;
1917 status = "disabled"; 1829 status = "disabled";
1918 }; 1830 };
1919 1831
1920 blsp_i2c5: i2c@78b9000 { 1832 blsp_i2c5: i2c@78b9000 {
1921 compatible = "qcom,i2 1833 compatible = "qcom,i2c-qup-v2.2.1";
1922 reg = <0x078b9000 0x5 1834 reg = <0x078b9000 0x500>;
1923 interrupts = <GIC_SPI 1835 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
1924 clocks = <&gcc GCC_BL 1836 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
1925 <&gcc GCC_BL 1837 <&gcc GCC_BLSP1_AHB_CLK>;
1926 clock-names = "core", 1838 clock-names = "core", "iface";
1927 dmas = <&blsp_dma 12> 1839 dmas = <&blsp_dma 12>, <&blsp_dma 13>;
1928 dma-names = "tx", "rx 1840 dma-names = "tx", "rx";
1929 pinctrl-0 = <&blsp_i2 1841 pinctrl-0 = <&blsp_i2c5_default>;
1930 pinctrl-1 = <&blsp_i2 1842 pinctrl-1 = <&blsp_i2c5_sleep>;
1931 pinctrl-names = "defa 1843 pinctrl-names = "default", "sleep";
1932 #address-cells = <1>; 1844 #address-cells = <1>;
1933 #size-cells = <0>; 1845 #size-cells = <0>;
1934 status = "disabled"; 1846 status = "disabled";
1935 }; 1847 };
1936 1848
1937 blsp_spi5: spi@78b9000 { 1849 blsp_spi5: spi@78b9000 {
1938 compatible = "qcom,sp 1850 compatible = "qcom,spi-qup-v2.2.1";
1939 reg = <0x078b9000 0x5 1851 reg = <0x078b9000 0x500>;
1940 interrupts = <GIC_SPI 1852 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
1941 clocks = <&gcc GCC_BL 1853 clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
1942 <&gcc GCC_BL 1854 <&gcc GCC_BLSP1_AHB_CLK>;
1943 clock-names = "core", 1855 clock-names = "core", "iface";
1944 dmas = <&blsp_dma 12> 1856 dmas = <&blsp_dma 12>, <&blsp_dma 13>;
1945 dma-names = "tx", "rx 1857 dma-names = "tx", "rx";
1946 pinctrl-0 = <&blsp_sp 1858 pinctrl-0 = <&blsp_spi5_default>;
1947 pinctrl-1 = <&blsp_sp 1859 pinctrl-1 = <&blsp_spi5_sleep>;
1948 pinctrl-names = "defa 1860 pinctrl-names = "default", "sleep";
1949 #address-cells = <1>; 1861 #address-cells = <1>;
1950 #size-cells = <0>; 1862 #size-cells = <0>;
1951 status = "disabled"; 1863 status = "disabled";
1952 }; 1864 };
1953 1865
1954 blsp_i2c6: i2c@78ba000 { 1866 blsp_i2c6: i2c@78ba000 {
1955 compatible = "qcom,i2 1867 compatible = "qcom,i2c-qup-v2.2.1";
1956 reg = <0x078ba000 0x5 1868 reg = <0x078ba000 0x500>;
1957 interrupts = <GIC_SPI 1869 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
1958 clocks = <&gcc GCC_BL 1870 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
1959 <&gcc GCC_BL 1871 <&gcc GCC_BLSP1_AHB_CLK>;
1960 clock-names = "core", 1872 clock-names = "core", "iface";
1961 dmas = <&blsp_dma 14> 1873 dmas = <&blsp_dma 14>, <&blsp_dma 15>;
1962 dma-names = "tx", "rx 1874 dma-names = "tx", "rx";
1963 pinctrl-0 = <&blsp_i2 1875 pinctrl-0 = <&blsp_i2c6_default>;
1964 pinctrl-1 = <&blsp_i2 1876 pinctrl-1 = <&blsp_i2c6_sleep>;
1965 pinctrl-names = "defa 1877 pinctrl-names = "default", "sleep";
1966 #address-cells = <1>; 1878 #address-cells = <1>;
1967 #size-cells = <0>; 1879 #size-cells = <0>;
1968 status = "disabled"; 1880 status = "disabled";
1969 }; 1881 };
1970 1882
1971 blsp_spi6: spi@78ba000 { 1883 blsp_spi6: spi@78ba000 {
1972 compatible = "qcom,sp 1884 compatible = "qcom,spi-qup-v2.2.1";
1973 reg = <0x078ba000 0x5 1885 reg = <0x078ba000 0x500>;
1974 interrupts = <GIC_SPI 1886 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
1975 clocks = <&gcc GCC_BL 1887 clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>,
1976 <&gcc GCC_BL 1888 <&gcc GCC_BLSP1_AHB_CLK>;
1977 clock-names = "core", 1889 clock-names = "core", "iface";
1978 dmas = <&blsp_dma 14> 1890 dmas = <&blsp_dma 14>, <&blsp_dma 15>;
1979 dma-names = "tx", "rx 1891 dma-names = "tx", "rx";
1980 pinctrl-0 = <&blsp_sp 1892 pinctrl-0 = <&blsp_spi6_default>;
1981 pinctrl-1 = <&blsp_sp 1893 pinctrl-1 = <&blsp_spi6_sleep>;
1982 pinctrl-names = "defa 1894 pinctrl-names = "default", "sleep";
1983 #address-cells = <1>; 1895 #address-cells = <1>;
1984 #size-cells = <0>; 1896 #size-cells = <0>;
1985 status = "disabled"; 1897 status = "disabled";
1986 }; 1898 };
1987 1899
1988 usb: usb@78d9000 { 1900 usb: usb@78d9000 {
1989 compatible = "qcom,ci 1901 compatible = "qcom,ci-hdrc";
1990 reg = <0x078d9000 0x2 1902 reg = <0x078d9000 0x200>,
1991 <0x078d9200 0x2 1903 <0x078d9200 0x200>;
1992 interrupts = <GIC_SPI 1904 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
1993 <GIC_SPI 1905 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
1994 clocks = <&gcc GCC_US 1906 clocks = <&gcc GCC_USB_HS_AHB_CLK>,
1995 <&gcc GCC_US 1907 <&gcc GCC_USB_HS_SYSTEM_CLK>;
1996 clock-names = "iface" 1908 clock-names = "iface", "core";
1997 assigned-clocks = <&g 1909 assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>;
1998 assigned-clock-rates 1910 assigned-clock-rates = <80000000>;
1999 resets = <&gcc GCC_US 1911 resets = <&gcc GCC_USB_HS_BCR>;
2000 reset-names = "core"; 1912 reset-names = "core";
2001 #reset-cells = <1>; 1913 #reset-cells = <1>;
2002 phy_type = "ulpi"; 1914 phy_type = "ulpi";
2003 dr_mode = "otg"; 1915 dr_mode = "otg";
2004 adp-disable; 1916 adp-disable;
2005 hnp-disable; 1917 hnp-disable;
2006 srp-disable; 1918 srp-disable;
2007 ahb-burst-config = <0 1919 ahb-burst-config = <0>;
2008 phy-names = "usb-phy" 1920 phy-names = "usb-phy";
2009 phys = <&usb_hs_phy>; 1921 phys = <&usb_hs_phy>;
2010 status = "disabled"; 1922 status = "disabled";
2011 1923
2012 ulpi { 1924 ulpi {
2013 usb_hs_phy: p 1925 usb_hs_phy: phy {
2014 compa 1926 compatible = "qcom,usb-hs-phy-msm8916",
2015 1927 "qcom,usb-hs-phy";
2016 clock 1928 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
2017 1929 <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
2018 clock 1930 clock-names = "ref", "sleep";
2019 reset 1931 resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>;
2020 reset 1932 reset-names = "phy", "por";
2021 #phy- 1933 #phy-cells = <0>;
2022 qcom, 1934 qcom,init-seq = /bits/ 8 <0x0 0x44>,
2023 1935 <0x1 0x6b>,
2024 1936 <0x2 0x24>,
2025 1937 <0x3 0x13>;
2026 }; 1938 };
2027 }; 1939 };
2028 }; 1940 };
2029 1941
2030 wcnss: remoteproc@a204000 { 1942 wcnss: remoteproc@a204000 {
2031 compatible = "qcom,pr 1943 compatible = "qcom,pronto-v2-pil", "qcom,pronto";
2032 interrupts-extended = 1944 interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>,
2033 1945 <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2034 1946 <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2035 1947 <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2036 1948 <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
2037 interrupt-names = "wd 1949 interrupt-names = "wdog",
2038 "fa 1950 "fatal",
2039 "re 1951 "ready",
2040 "ha 1952 "handover",
2041 "st 1953 "stop-ack";
2042 reg = <0x0a204000 0x2 1954 reg = <0x0a204000 0x2000>,
2043 <0x0a202000 0x1 1955 <0x0a202000 0x1000>,
2044 <0x0a21b000 0x3 1956 <0x0a21b000 0x3000>;
2045 reg-names = "ccu", "d 1957 reg-names = "ccu", "dxe", "pmu";
2046 1958
2047 memory-region = <&wcn 1959 memory-region = <&wcnss_mem>;
2048 1960
2049 power-domains = <&rpm 1961 power-domains = <&rpmpd MSM8939_VDDCX>,
2050 <&rpm 1962 <&rpmpd MSM8939_VDDMX>;
2051 power-domain-names = 1963 power-domain-names = "cx", "mx";
2052 1964
2053 qcom,smem-states = <& 1965 qcom,smem-states = <&wcnss_smp2p_out 0>;
2054 qcom,smem-state-names 1966 qcom,smem-state-names = "stop";
2055 1967
2056 pinctrl-names = "defa 1968 pinctrl-names = "default";
2057 pinctrl-0 = <&wcss_wl 1969 pinctrl-0 = <&wcss_wlan_default>;
2058 1970
2059 status = "disabled"; 1971 status = "disabled";
2060 1972
2061 wcnss_iris: iris { 1973 wcnss_iris: iris {
2062 /* Separate c 1974 /* Separate chip, compatible is board-specific */
2063 clocks = <&rp 1975 clocks = <&rpmcc RPM_SMD_RF_CLK2>;
2064 clock-names = 1976 clock-names = "xo";
2065 }; 1977 };
2066 1978
2067 smd-edge { 1979 smd-edge {
2068 interrupts = !! 1980 interrupts = <GIC_SPI 142 1>;
2069 mboxes = <&ap !! 1981 qcom,ipc = <&apcs1_mbox 8 17>;
2070 qcom,smd-edge 1982 qcom,smd-edge = <6>;
2071 qcom,remote-p 1983 qcom,remote-pid = <4>;
2072 1984
2073 label = "pron 1985 label = "pronto";
2074 1986
2075 wcnss { 1987 wcnss {
2076 compa 1988 compatible = "qcom,wcnss";
2077 qcom, 1989 qcom,smd-channels = "WCNSS_CTRL";
2078 1990
2079 qcom, 1991 qcom,mmio = <&wcnss>;
2080 1992
2081 wcnss 1993 wcnss_bt: bluetooth {
2082 1994 compatible = "qcom,wcnss-bt";
2083 }; 1995 };
2084 1996
2085 wcnss 1997 wcnss_wifi: wifi {
2086 1998 compatible = "qcom,wcnss-wlan";
2087 1999
2088 2000 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
2089 2001 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
2090 2002 interrupt-names = "tx", "rx";
2091 2003
2092 2004 qcom,smem-states = <&apps_smsm 10>,
2093 2005 <&apps_smsm 9>;
2094 2006 qcom,smem-state-names = "tx-enable",
2095 2007 "tx-rings-empty";
2096 }; 2008 };
2097 }; 2009 };
2098 }; 2010 };
2099 }; 2011 };
2100 2012
2101 intc: interrupt-controller@b0 2013 intc: interrupt-controller@b000000 {
2102 compatible = "qcom,ms 2014 compatible = "qcom,msm-qgic2";
2103 reg = <0x0b000000 0x1 2015 reg = <0x0b000000 0x1000>, <0x0b002000 0x2000>,
2104 <0x0b001000 0x1 2016 <0x0b001000 0x1000>, <0x0b004000 0x2000>;
2105 interrupt-controller; 2017 interrupt-controller;
2106 #interrupt-cells = <3 2018 #interrupt-cells = <3>;
2107 interrupts = <GIC_PPI 2019 interrupts = <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
2108 }; 2020 };
2109 2021
2110 apcs1_mbox: mailbox@b011000 { 2022 apcs1_mbox: mailbox@b011000 {
2111 compatible = "qcom,ms 2023 compatible = "qcom,msm8939-apcs-kpss-global", "syscon";
2112 reg = <0x0b011000 0x1 2024 reg = <0x0b011000 0x1000>;
2113 clocks = <&a53pll_c1> 2025 clocks = <&a53pll_c1>, <&gcc GPLL0_VOTE>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
2114 clock-names = "pll", 2026 clock-names = "pll", "aux", "ref";
2115 #clock-cells = <0>; 2027 #clock-cells = <0>;
2116 assigned-clocks = <&a 2028 assigned-clocks = <&apcs2>;
2117 assigned-clock-rates 2029 assigned-clock-rates = <297600000>;
2118 #mbox-cells = <1>; 2030 #mbox-cells = <1>;
2119 }; 2031 };
2120 2032
2121 a53pll_c1: clock@b016000 { 2033 a53pll_c1: clock@b016000 {
2122 compatible = "qcom,ms 2034 compatible = "qcom,msm8939-a53pll";
2123 reg = <0x0b016000 0x4 2035 reg = <0x0b016000 0x40>;
2124 #clock-cells = <0>; 2036 #clock-cells = <0>;
2125 }; 2037 };
2126 2038
2127 acc0: clock-controller@b08800 2039 acc0: clock-controller@b088000 {
2128 compatible = "qcom,kp 2040 compatible = "qcom,kpss-acc-v2";
2129 reg = <0x0b088000 0x1 2041 reg = <0x0b088000 0x1000>;
2130 }; 2042 };
2131 2043
2132 saw0: power-manager@b089000 { 2044 saw0: power-manager@b089000 {
2133 compatible = "qcom,ms 2045 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
2134 reg = <0x0b089000 0x1 2046 reg = <0x0b089000 0x1000>;
2135 }; 2047 };
2136 2048
2137 acc1: clock-controller@b09800 2049 acc1: clock-controller@b098000 {
2138 compatible = "qcom,kp 2050 compatible = "qcom,kpss-acc-v2";
2139 reg = <0x0b098000 0x1 2051 reg = <0x0b098000 0x1000>;
2140 }; 2052 };
2141 2053
2142 saw1: power-manager@b099000 { 2054 saw1: power-manager@b099000 {
2143 compatible = "qcom,ms 2055 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
2144 reg = <0x0b099000 0x1 2056 reg = <0x0b099000 0x1000>;
2145 }; 2057 };
2146 2058
2147 acc2: clock-controller@b0a800 2059 acc2: clock-controller@b0a8000 {
2148 compatible = "qcom,kp 2060 compatible = "qcom,kpss-acc-v2";
2149 reg = <0x0b0a8000 0x1 2061 reg = <0x0b0a8000 0x1000>;
2150 }; 2062 };
2151 2063
2152 saw2: power-manager@b0a9000 { 2064 saw2: power-manager@b0a9000 {
2153 compatible = "qcom,ms 2065 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
2154 reg = <0x0b0a9000 0x1 2066 reg = <0x0b0a9000 0x1000>;
2155 }; 2067 };
2156 2068
2157 acc3: clock-controller@b0b800 2069 acc3: clock-controller@b0b8000 {
2158 compatible = "qcom,kp 2070 compatible = "qcom,kpss-acc-v2";
2159 reg = <0x0b0b8000 0x1 2071 reg = <0x0b0b8000 0x1000>;
2160 }; 2072 };
2161 2073
2162 saw3: power-manager@b0b9000 { 2074 saw3: power-manager@b0b9000 {
2163 compatible = "qcom,ms 2075 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
2164 reg = <0x0b0b9000 0x1 2076 reg = <0x0b0b9000 0x1000>;
2165 }; 2077 };
2166 2078
2167 apcs0_mbox: mailbox@b111000 { 2079 apcs0_mbox: mailbox@b111000 {
2168 compatible = "qcom,ms 2080 compatible = "qcom,msm8939-apcs-kpss-global", "syscon";
2169 reg = <0x0b111000 0x1 2081 reg = <0x0b111000 0x1000>;
2170 clocks = <&a53pll_c0> 2082 clocks = <&a53pll_c0>, <&gcc GPLL0_VOTE>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
2171 clock-names = "pll", 2083 clock-names = "pll", "aux", "ref";
2172 #clock-cells = <0>; 2084 #clock-cells = <0>;
2173 #mbox-cells = <1>; 2085 #mbox-cells = <1>;
2174 }; 2086 };
2175 2087
2176 a53pll_c0: clock@b116000 { 2088 a53pll_c0: clock@b116000 {
2177 compatible = "qcom,ms 2089 compatible = "qcom,msm8939-a53pll";
2178 reg = <0x0b116000 0x4 2090 reg = <0x0b116000 0x40>;
2179 #clock-cells = <0>; 2091 #clock-cells = <0>;
2180 }; 2092 };
2181 2093
2182 timer@b120000 { 2094 timer@b120000 {
2183 compatible = "arm,arm 2095 compatible = "arm,armv7-timer-mem";
2184 reg = <0x0b120000 0x1 2096 reg = <0x0b120000 0x1000>;
2185 #address-cells = <1>; 2097 #address-cells = <1>;
2186 #size-cells = <1>; 2098 #size-cells = <1>;
2187 ranges; 2099 ranges;
2188 /* Necessary because <<
2189 clock-frequency = <19 <<
2190 2100
2191 frame@b121000 { 2101 frame@b121000 {
2192 reg = <0x0b12 2102 reg = <0x0b121000 0x1000>,
2193 <0x0b12 2103 <0x0b122000 0x1000>;
2194 interrupts = 2104 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
2195 2105 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
2196 frame-number 2106 frame-number = <0>;
2197 }; 2107 };
2198 2108
2199 frame@b123000 { 2109 frame@b123000 {
2200 reg = <0x0b12 2110 reg = <0x0b123000 0x1000>;
2201 interrupts = 2111 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
2202 frame-number 2112 frame-number = <1>;
2203 status = "dis 2113 status = "disabled";
2204 }; 2114 };
2205 2115
2206 frame@b124000 { 2116 frame@b124000 {
2207 reg = <0x0b12 2117 reg = <0x0b124000 0x1000>;
2208 interrupts = 2118 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
2209 frame-number 2119 frame-number = <2>;
2210 status = "dis 2120 status = "disabled";
2211 }; 2121 };
2212 2122
2213 frame@b125000 { 2123 frame@b125000 {
2214 reg = <0x0b12 2124 reg = <0x0b125000 0x1000>;
2215 interrupts = 2125 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
2216 frame-number 2126 frame-number = <3>;
2217 status = "dis 2127 status = "disabled";
2218 }; 2128 };
2219 2129
2220 frame@b126000 { 2130 frame@b126000 {
2221 reg = <0x0b12 2131 reg = <0x0b126000 0x1000>;
2222 interrupts = 2132 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
2223 frame-number 2133 frame-number = <4>;
2224 status = "dis 2134 status = "disabled";
2225 }; 2135 };
2226 2136
2227 frame@b127000 { 2137 frame@b127000 {
2228 reg = <0x0b12 2138 reg = <0x0b127000 0x1000>;
2229 interrupts = 2139 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
2230 frame-number 2140 frame-number = <5>;
2231 status = "dis 2141 status = "disabled";
2232 }; 2142 };
2233 2143
2234 frame@b128000 { 2144 frame@b128000 {
2235 reg = <0x0b12 2145 reg = <0x0b128000 0x1000>;
2236 interrupts = 2146 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
2237 frame-number 2147 frame-number = <6>;
2238 status = "dis 2148 status = "disabled";
2239 }; 2149 };
2240 }; 2150 };
2241 2151
2242 acc4: clock-controller@b18800 2152 acc4: clock-controller@b188000 {
2243 compatible = "qcom,kp 2153 compatible = "qcom,kpss-acc-v2";
2244 reg = <0x0b188000 0x1 2154 reg = <0x0b188000 0x1000>;
2245 }; 2155 };
2246 2156
2247 saw4: power-manager@b189000 { 2157 saw4: power-manager@b189000 {
2248 compatible = "qcom,ms 2158 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
2249 reg = <0x0b189000 0x1 2159 reg = <0x0b189000 0x1000>;
2250 }; 2160 };
2251 2161
2252 acc5: clock-controller@b19800 2162 acc5: clock-controller@b198000 {
2253 compatible = "qcom,kp 2163 compatible = "qcom,kpss-acc-v2";
2254 reg = <0x0b198000 0x1 2164 reg = <0x0b198000 0x1000>;
2255 }; 2165 };
2256 2166
2257 saw5: power-manager@b199000 { 2167 saw5: power-manager@b199000 {
2258 compatible = "qcom,ms 2168 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
2259 reg = <0x0b199000 0x1 2169 reg = <0x0b199000 0x1000>;
2260 }; 2170 };
2261 2171
2262 acc6: clock-controller@b1a800 2172 acc6: clock-controller@b1a8000 {
2263 compatible = "qcom,kp 2173 compatible = "qcom,kpss-acc-v2";
2264 reg = <0x0b1a8000 0x1 2174 reg = <0x0b1a8000 0x1000>;
2265 }; 2175 };
2266 2176
2267 saw6: power-manager@b1a9000 { 2177 saw6: power-manager@b1a9000 {
2268 compatible = "qcom,ms 2178 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
2269 reg = <0x0b1a9000 0x1 2179 reg = <0x0b1a9000 0x1000>;
2270 }; 2180 };
2271 2181
2272 acc7: clock-controller@b1b800 2182 acc7: clock-controller@b1b8000 {
2273 compatible = "qcom,kp 2183 compatible = "qcom,kpss-acc-v2";
2274 reg = <0x0b1b8000 0x1 2184 reg = <0x0b1b8000 0x1000>;
2275 }; 2185 };
2276 2186
2277 saw7: power-manager@b1b9000 { 2187 saw7: power-manager@b1b9000 {
2278 compatible = "qcom,ms 2188 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
2279 reg = <0x0b1b9000 0x1 2189 reg = <0x0b1b9000 0x1000>;
2280 }; 2190 };
2281 2191
2282 a53pll_cci: clock@b1d0000 { 2192 a53pll_cci: clock@b1d0000 {
2283 compatible = "qcom,ms 2193 compatible = "qcom,msm8939-a53pll";
2284 reg = <0x0b1d0000 0x4 2194 reg = <0x0b1d0000 0x40>;
2285 #clock-cells = <0>; 2195 #clock-cells = <0>;
2286 }; 2196 };
2287 2197
2288 apcs2: mailbox@b1d1000 { 2198 apcs2: mailbox@b1d1000 {
2289 compatible = "qcom,ms 2199 compatible = "qcom,msm8939-apcs-kpss-global", "syscon";
2290 reg = <0x0b1d1000 0x1 2200 reg = <0x0b1d1000 0x1000>;
2291 clocks = <&a53pll_cci 2201 clocks = <&a53pll_cci>, <&gcc GPLL0_VOTE>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
2292 clock-names = "pll", 2202 clock-names = "pll", "aux", "ref";
2293 #clock-cells = <0>; 2203 #clock-cells = <0>;
2294 #mbox-cells = <1>; 2204 #mbox-cells = <1>;
2295 }; 2205 };
2296 }; 2206 };
2297 2207
2298 thermal_zones: thermal-zones { 2208 thermal_zones: thermal-zones {
2299 cpu0-thermal { 2209 cpu0-thermal {
2300 polling-delay-passive 2210 polling-delay-passive = <250>;
>> 2211 polling-delay = <1000>;
2301 2212
2302 thermal-sensors = <&t 2213 thermal-sensors = <&tsens 5>;
2303 2214
2304 trips { 2215 trips {
2305 cpu0_alert: t 2216 cpu0_alert: trip0 {
2306 tempe 2217 temperature = <75000>;
2307 hyste 2218 hysteresis = <2000>;
2308 type 2219 type = "passive";
2309 }; 2220 };
2310 2221
2311 cpu0_crit: tr 2222 cpu0_crit: trip1 {
2312 tempe 2223 temperature = <115000>;
2313 hyste 2224 hysteresis = <0>;
2314 type 2225 type = "critical";
2315 }; 2226 };
2316 }; 2227 };
2317 2228
2318 cooling-maps { 2229 cooling-maps {
2319 map0 { 2230 map0 {
2320 trip 2231 trip = <&cpu0_alert>;
2321 cooli 2232 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2322 2233 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2323 2234 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2324 2235 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2325 }; 2236 };
2326 }; 2237 };
2327 }; 2238 };
2328 2239
2329 cpu1-thermal { 2240 cpu1-thermal {
2330 polling-delay-passive 2241 polling-delay-passive = <250>;
>> 2242 polling-delay = <1000>;
2331 2243
2332 thermal-sensors = <&t 2244 thermal-sensors = <&tsens 6>;
2333 2245
2334 trips { 2246 trips {
2335 cpu1_alert: t 2247 cpu1_alert: trip0 {
2336 tempe 2248 temperature = <75000>;
2337 hyste 2249 hysteresis = <2000>;
2338 type 2250 type = "passive";
2339 }; 2251 };
2340 2252
2341 cpu1_crit: tr 2253 cpu1_crit: trip1 {
2342 tempe 2254 temperature = <110000>;
2343 hyste 2255 hysteresis = <2000>;
2344 type 2256 type = "critical";
2345 }; 2257 };
2346 }; 2258 };
2347 2259
2348 cooling-maps { 2260 cooling-maps {
2349 map0 { 2261 map0 {
2350 trip 2262 trip = <&cpu1_alert>;
2351 cooli 2263 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2352 2264 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2353 2265 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2354 2266 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2355 }; 2267 };
2356 }; 2268 };
2357 }; 2269 };
2358 2270
2359 cpu2-thermal { 2271 cpu2-thermal {
2360 polling-delay-passive 2272 polling-delay-passive = <250>;
>> 2273 polling-delay = <1000>;
2361 2274
2362 thermal-sensors = <&t 2275 thermal-sensors = <&tsens 7>;
2363 2276
2364 trips { 2277 trips {
2365 cpu2_alert: t 2278 cpu2_alert: trip0 {
2366 tempe 2279 temperature = <75000>;
2367 hyste 2280 hysteresis = <2000>;
2368 type 2281 type = "passive";
2369 }; 2282 };
2370 2283
2371 cpu2_crit: tr 2284 cpu2_crit: trip1 {
2372 tempe 2285 temperature = <110000>;
2373 hyste 2286 hysteresis = <2000>;
2374 type 2287 type = "critical";
2375 }; 2288 };
2376 }; 2289 };
2377 2290
2378 cooling-maps { 2291 cooling-maps {
2379 map0 { 2292 map0 {
2380 trip 2293 trip = <&cpu2_alert>;
2381 cooli 2294 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2382 2295 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2383 2296 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2384 2297 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2385 }; 2298 };
2386 }; 2299 };
2387 }; 2300 };
2388 2301
2389 cpu3-thermal { 2302 cpu3-thermal {
2390 polling-delay-passive 2303 polling-delay-passive = <250>;
>> 2304 polling-delay = <1000>;
2391 2305
2392 thermal-sensors = <&t 2306 thermal-sensors = <&tsens 8>;
2393 2307
2394 trips { 2308 trips {
2395 cpu3_alert: t 2309 cpu3_alert: trip0 {
2396 tempe 2310 temperature = <75000>;
2397 hyste 2311 hysteresis = <2000>;
2398 type 2312 type = "passive";
2399 }; 2313 };
2400 2314
2401 cpu3_crit: tr 2315 cpu3_crit: trip1 {
2402 tempe 2316 temperature = <110000>;
2403 hyste 2317 hysteresis = <2000>;
2404 type 2318 type = "critical";
2405 }; 2319 };
2406 }; 2320 };
2407 2321
2408 cooling-maps { 2322 cooling-maps {
2409 map0 { 2323 map0 {
2410 trip 2324 trip = <&cpu3_alert>;
2411 cooli 2325 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2412 2326 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2413 2327 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2414 2328 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2415 }; 2329 };
2416 }; 2330 };
2417 }; 2331 };
2418 2332
2419 cpu4567-thermal { 2333 cpu4567-thermal {
2420 polling-delay-passive 2334 polling-delay-passive = <250>;
>> 2335 polling-delay = <1000>;
2421 2336
2422 thermal-sensors = <&t 2337 thermal-sensors = <&tsens 9>;
2423 2338
2424 trips { 2339 trips {
2425 cpu4567_alert 2340 cpu4567_alert: trip0 {
2426 tempe 2341 temperature = <75000>;
2427 hyste 2342 hysteresis = <2000>;
2428 type 2343 type = "passive";
2429 }; 2344 };
2430 2345
2431 cpu4567_crit: 2346 cpu4567_crit: trip1 {
2432 tempe 2347 temperature = <110000>;
2433 hyste 2348 hysteresis = <2000>;
2434 type 2349 type = "critical";
2435 }; 2350 };
2436 }; 2351 };
2437 2352
2438 cooling-maps { 2353 cooling-maps {
2439 map0 { 2354 map0 {
2440 trip 2355 trip = <&cpu4567_alert>;
2441 cooli 2356 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2442 2357 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2443 2358 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2444 2359 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2445 }; 2360 };
2446 }; 2361 };
2447 }; 2362 };
2448 2363
2449 gpu-thermal { 2364 gpu-thermal {
2450 polling-delay-passive 2365 polling-delay-passive = <250>;
>> 2366 polling-delay = <1000>;
2451 2367
2452 thermal-sensors = <&t 2368 thermal-sensors = <&tsens 3>;
2453 2369
2454 cooling-maps { <<
2455 map0 { <<
2456 trip <<
2457 cooli <<
2458 }; <<
2459 }; <<
2460 <<
2461 trips { 2370 trips {
2462 gpu_alert0: t 2371 gpu_alert0: trip-point0 {
2463 tempe 2372 temperature = <75000>;
2464 hyste 2373 hysteresis = <2000>;
2465 type 2374 type = "passive";
2466 }; 2375 };
2467 2376
2468 gpu_crit: gpu !! 2377 gpu_crit: gpu_crit {
2469 tempe 2378 temperature = <95000>;
2470 hyste 2379 hysteresis = <2000>;
2471 type 2380 type = "critical";
2472 }; 2381 };
2473 }; 2382 };
2474 }; 2383 };
2475 2384
2476 modem1-thermal { 2385 modem1-thermal {
2477 polling-delay-passive 2386 polling-delay-passive = <250>;
>> 2387 polling-delay = <1000>;
2478 2388
2479 thermal-sensors = <&t 2389 thermal-sensors = <&tsens 0>;
2480 2390
2481 trips { 2391 trips {
2482 modem1_alert0 2392 modem1_alert0: trip-point0 {
2483 tempe 2393 temperature = <85000>;
2484 hyste 2394 hysteresis = <2000>;
2485 type 2395 type = "hot";
2486 }; 2396 };
2487 }; 2397 };
2488 }; 2398 };
2489 2399
2490 modem2-thermal { 2400 modem2-thermal {
2491 polling-delay-passive 2401 polling-delay-passive = <250>;
>> 2402 polling-delay = <1000>;
2492 2403
2493 thermal-sensors = <&t 2404 thermal-sensors = <&tsens 2>;
2494 2405
2495 trips { 2406 trips {
2496 modem2_alert0 2407 modem2_alert0: trip-point0 {
2497 tempe 2408 temperature = <85000>;
2498 hyste 2409 hysteresis = <2000>;
2499 type 2410 type = "hot";
2500 }; 2411 };
2501 }; 2412 };
2502 }; 2413 };
2503 2414
2504 camera-thermal { 2415 camera-thermal {
2505 polling-delay-passive 2416 polling-delay-passive = <250>;
>> 2417 polling-delay = <1000>;
2506 2418
2507 thermal-sensors = <&t 2419 thermal-sensors = <&tsens 1>;
2508 2420
2509 trips { 2421 trips {
2510 cam_alert0: t 2422 cam_alert0: trip-point0 {
2511 tempe 2423 temperature = <75000>;
2512 hyste 2424 hysteresis = <2000>;
2513 type 2425 type = "hot";
2514 }; 2426 };
2515 }; 2427 };
2516 }; 2428 };
2517 }; 2429 };
2518 2430
2519 timer { 2431 timer {
2520 compatible = "arm,armv8-timer 2432 compatible = "arm,armv8-timer";
2521 interrupts = <GIC_PPI 2 (GIC_ 2433 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
2522 <GIC_PPI 3 (GIC_ 2434 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
2523 <GIC_PPI 4 (GIC_ 2435 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
2524 <GIC_PPI 1 (GIC_ 2436 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
2525 }; 2437 };
2526 }; 2438 };
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