1 // SPDX-License-Identifier: GPL-2.0-only 1 // SPDX-License-Identifier: GPL-2.0-only
2 /* 2 /*
3 * Copyright (c) 2013-2015, The Linux Foundati 3 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2020-2023, Linaro Limited 4 * Copyright (c) 2020-2023, Linaro Limited
5 */ 5 */
6 6
7 #include <dt-bindings/clock/qcom,gcc-msm8939.h 7 #include <dt-bindings/clock/qcom,gcc-msm8939.h>
8 #include <dt-bindings/clock/qcom,rpmcc.h> 8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/interconnect/qcom,msm893 9 #include <dt-bindings/interconnect/qcom,msm8939.h>
10 #include <dt-bindings/interrupt-controller/arm 10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/power/qcom-rpmpd.h> 11 #include <dt-bindings/power/qcom-rpmpd.h>
12 #include <dt-bindings/reset/qcom,gcc-msm8939.h 12 #include <dt-bindings/reset/qcom,gcc-msm8939.h>
13 #include <dt-bindings/soc/qcom,apr.h> <<
14 #include <dt-bindings/thermal/thermal.h> 13 #include <dt-bindings/thermal/thermal.h>
15 14
16 / { 15 / {
17 interrupt-parent = <&intc>; 16 interrupt-parent = <&intc>;
18 17
19 /* 18 /*
20 * Stock LK wants address-cells/size-c 19 * Stock LK wants address-cells/size-cells = 2
21 * A number of our drivers want addres 20 * A number of our drivers want address/size cells = 1
22 * hence the disparity between top-lev 21 * hence the disparity between top-level and /soc below.
23 */ 22 */
24 #address-cells = <2>; 23 #address-cells = <2>;
25 #size-cells = <2>; 24 #size-cells = <2>;
26 25
27 clocks { 26 clocks {
28 xo_board: xo-board { 27 xo_board: xo-board {
29 compatible = "fixed-cl 28 compatible = "fixed-clock";
30 #clock-cells = <0>; 29 #clock-cells = <0>;
31 clock-frequency = <192 30 clock-frequency = <19200000>;
32 }; 31 };
33 32
34 sleep_clk: sleep-clk { 33 sleep_clk: sleep-clk {
35 compatible = "fixed-cl 34 compatible = "fixed-clock";
36 #clock-cells = <0>; 35 #clock-cells = <0>;
37 clock-frequency = <327 36 clock-frequency = <32768>;
38 }; 37 };
39 }; 38 };
40 39
41 cpus { 40 cpus {
42 #address-cells = <1>; 41 #address-cells = <1>;
43 #size-cells = <0>; 42 #size-cells = <0>;
44 43
45 CPU0: cpu@100 { 44 CPU0: cpu@100 {
46 compatible = "arm,cort 45 compatible = "arm,cortex-a53";
47 device_type = "cpu"; 46 device_type = "cpu";
48 enable-method = "spin- 47 enable-method = "spin-table";
49 reg = <0x100>; 48 reg = <0x100>;
50 next-level-cache = <&L 49 next-level-cache = <&L2_1>;
51 qcom,acc = <&acc0>; 50 qcom,acc = <&acc0>;
52 qcom,saw = <&saw0>; 51 qcom,saw = <&saw0>;
53 cpu-idle-states = <&CP 52 cpu-idle-states = <&CPU_SLEEP_0>;
54 clocks = <&apcs1_mbox> 53 clocks = <&apcs1_mbox>;
55 #cooling-cells = <2>; 54 #cooling-cells = <2>;
56 L2_1: l2-cache { 55 L2_1: l2-cache {
57 compatible = " 56 compatible = "cache";
58 cache-level = 57 cache-level = <2>;
59 cache-unified; 58 cache-unified;
60 }; 59 };
61 }; 60 };
62 61
63 CPU1: cpu@101 { 62 CPU1: cpu@101 {
64 compatible = "arm,cort 63 compatible = "arm,cortex-a53";
65 device_type = "cpu"; 64 device_type = "cpu";
66 enable-method = "spin- 65 enable-method = "spin-table";
67 reg = <0x101>; 66 reg = <0x101>;
68 next-level-cache = <&L 67 next-level-cache = <&L2_1>;
69 qcom,acc = <&acc1>; 68 qcom,acc = <&acc1>;
70 qcom,saw = <&saw1>; 69 qcom,saw = <&saw1>;
71 cpu-idle-states = <&CP 70 cpu-idle-states = <&CPU_SLEEP_0>;
72 clocks = <&apcs1_mbox> 71 clocks = <&apcs1_mbox>;
73 #cooling-cells = <2>; 72 #cooling-cells = <2>;
74 }; 73 };
75 74
76 CPU2: cpu@102 { 75 CPU2: cpu@102 {
77 compatible = "arm,cort 76 compatible = "arm,cortex-a53";
78 device_type = "cpu"; 77 device_type = "cpu";
79 enable-method = "spin- 78 enable-method = "spin-table";
80 reg = <0x102>; 79 reg = <0x102>;
81 next-level-cache = <&L 80 next-level-cache = <&L2_1>;
82 qcom,acc = <&acc2>; 81 qcom,acc = <&acc2>;
83 qcom,saw = <&saw2>; 82 qcom,saw = <&saw2>;
84 cpu-idle-states = <&CP 83 cpu-idle-states = <&CPU_SLEEP_0>;
85 clocks = <&apcs1_mbox> 84 clocks = <&apcs1_mbox>;
86 #cooling-cells = <2>; 85 #cooling-cells = <2>;
87 }; 86 };
88 87
89 CPU3: cpu@103 { 88 CPU3: cpu@103 {
90 compatible = "arm,cort 89 compatible = "arm,cortex-a53";
91 device_type = "cpu"; 90 device_type = "cpu";
92 enable-method = "spin- 91 enable-method = "spin-table";
93 reg = <0x103>; 92 reg = <0x103>;
94 next-level-cache = <&L 93 next-level-cache = <&L2_1>;
95 qcom,acc = <&acc3>; 94 qcom,acc = <&acc3>;
96 qcom,saw = <&saw3>; 95 qcom,saw = <&saw3>;
97 cpu-idle-states = <&CP 96 cpu-idle-states = <&CPU_SLEEP_0>;
98 clocks = <&apcs1_mbox> 97 clocks = <&apcs1_mbox>;
99 #cooling-cells = <2>; 98 #cooling-cells = <2>;
100 }; 99 };
101 100
102 CPU4: cpu@0 { 101 CPU4: cpu@0 {
103 compatible = "arm,cort 102 compatible = "arm,cortex-a53";
104 device_type = "cpu"; 103 device_type = "cpu";
105 enable-method = "spin- 104 enable-method = "spin-table";
106 reg = <0x0>; 105 reg = <0x0>;
107 qcom,acc = <&acc4>; 106 qcom,acc = <&acc4>;
108 qcom,saw = <&saw4>; 107 qcom,saw = <&saw4>;
109 cpu-idle-states = <&CP 108 cpu-idle-states = <&CPU_SLEEP_0>;
110 clocks = <&apcs0_mbox> 109 clocks = <&apcs0_mbox>;
111 #cooling-cells = <2>; 110 #cooling-cells = <2>;
112 next-level-cache = <&L 111 next-level-cache = <&L2_0>;
113 L2_0: l2-cache { 112 L2_0: l2-cache {
114 compatible = " 113 compatible = "cache";
115 cache-level = 114 cache-level = <2>;
116 cache-unified; 115 cache-unified;
117 }; 116 };
118 }; 117 };
119 118
120 CPU5: cpu@1 { 119 CPU5: cpu@1 {
121 compatible = "arm,cort 120 compatible = "arm,cortex-a53";
122 device_type = "cpu"; 121 device_type = "cpu";
123 enable-method = "spin- 122 enable-method = "spin-table";
124 reg = <0x1>; 123 reg = <0x1>;
125 next-level-cache = <&L 124 next-level-cache = <&L2_0>;
126 qcom,acc = <&acc5>; 125 qcom,acc = <&acc5>;
127 qcom,saw = <&saw5>; 126 qcom,saw = <&saw5>;
128 cpu-idle-states = <&CP 127 cpu-idle-states = <&CPU_SLEEP_0>;
129 clocks = <&apcs0_mbox> 128 clocks = <&apcs0_mbox>;
130 #cooling-cells = <2>; 129 #cooling-cells = <2>;
131 }; 130 };
132 131
133 CPU6: cpu@2 { 132 CPU6: cpu@2 {
134 compatible = "arm,cort 133 compatible = "arm,cortex-a53";
135 device_type = "cpu"; 134 device_type = "cpu";
136 enable-method = "spin- 135 enable-method = "spin-table";
137 reg = <0x2>; 136 reg = <0x2>;
138 next-level-cache = <&L 137 next-level-cache = <&L2_0>;
139 qcom,acc = <&acc6>; 138 qcom,acc = <&acc6>;
140 qcom,saw = <&saw6>; 139 qcom,saw = <&saw6>;
141 cpu-idle-states = <&CP 140 cpu-idle-states = <&CPU_SLEEP_0>;
142 clocks = <&apcs0_mbox> 141 clocks = <&apcs0_mbox>;
143 #cooling-cells = <2>; 142 #cooling-cells = <2>;
144 }; 143 };
145 144
146 CPU7: cpu@3 { 145 CPU7: cpu@3 {
147 compatible = "arm,cort 146 compatible = "arm,cortex-a53";
148 device_type = "cpu"; 147 device_type = "cpu";
149 enable-method = "spin- 148 enable-method = "spin-table";
150 reg = <0x3>; 149 reg = <0x3>;
151 next-level-cache = <&L 150 next-level-cache = <&L2_0>;
152 qcom,acc = <&acc7>; 151 qcom,acc = <&acc7>;
153 qcom,saw = <&saw7>; 152 qcom,saw = <&saw7>;
154 cpu-idle-states = <&CP 153 cpu-idle-states = <&CPU_SLEEP_0>;
155 clocks = <&apcs0_mbox> 154 clocks = <&apcs0_mbox>;
156 #cooling-cells = <2>; 155 #cooling-cells = <2>;
157 }; 156 };
158 157
159 idle-states { 158 idle-states {
160 CPU_SLEEP_0: cpu-sleep 159 CPU_SLEEP_0: cpu-sleep-0 {
161 compatible = " 160 compatible = "arm,idle-state";
162 entry-latency- 161 entry-latency-us = <130>;
163 exit-latency-u 162 exit-latency-us = <150>;
164 min-residency- 163 min-residency-us = <2000>;
165 local-timer-st 164 local-timer-stop;
166 }; 165 };
167 }; 166 };
168 }; 167 };
169 168
170 /* 169 /*
171 * MSM8939 has a big.LITTLE heterogene 170 * MSM8939 has a big.LITTLE heterogeneous computing architecture,
172 * consisting of two clusters of four 171 * consisting of two clusters of four ARM Cortex-A53s each. The
173 * LITTLE cluster runs at 1.0-1.2GHz, 172 * LITTLE cluster runs at 1.0-1.2GHz, and the big cluster runs
174 * at 1.5-1.7GHz. 173 * at 1.5-1.7GHz.
175 * 174 *
176 * The enable method used here is spin 175 * The enable method used here is spin-table which presupposes use
177 * of a 2nd stage boot shim such as lk 176 * of a 2nd stage boot shim such as lk2nd to have installed a
178 * spin-table, the downstream non-psci 177 * spin-table, the downstream non-psci/non-spin-table method that
179 * default msm8916/msm8936/msm8939 wil 178 * default msm8916/msm8936/msm8939 will not be supported upstream.
180 */ 179 */
181 cpu-map { 180 cpu-map {
182 /* LITTLE (efficiency) cluster 181 /* LITTLE (efficiency) cluster */
183 cluster0 { 182 cluster0 {
184 core0 { 183 core0 {
185 cpu = <&CPU4>; 184 cpu = <&CPU4>;
186 }; 185 };
187 186
188 core1 { 187 core1 {
189 cpu = <&CPU5>; 188 cpu = <&CPU5>;
190 }; 189 };
191 190
192 core2 { 191 core2 {
193 cpu = <&CPU6>; 192 cpu = <&CPU6>;
194 }; 193 };
195 194
196 core3 { 195 core3 {
197 cpu = <&CPU7>; 196 cpu = <&CPU7>;
198 }; 197 };
199 }; 198 };
200 199
201 /* big (performance) cluster * 200 /* big (performance) cluster */
202 /* Boot CPU is cluster 1 core 201 /* Boot CPU is cluster 1 core 0 */
203 cluster1 { 202 cluster1 {
204 core0 { 203 core0 {
205 cpu = <&CPU0>; 204 cpu = <&CPU0>;
206 }; 205 };
207 206
208 core1 { 207 core1 {
209 cpu = <&CPU1>; 208 cpu = <&CPU1>;
210 }; 209 };
211 210
212 core2 { 211 core2 {
213 cpu = <&CPU2>; 212 cpu = <&CPU2>;
214 }; 213 };
215 214
216 core3 { 215 core3 {
217 cpu = <&CPU3>; 216 cpu = <&CPU3>;
218 }; 217 };
219 }; 218 };
220 }; 219 };
221 220
222 firmware { 221 firmware {
223 scm: scm { 222 scm: scm {
224 compatible = "qcom,scm 223 compatible = "qcom,scm-msm8916", "qcom,scm";
225 clocks = <&gcc GCC_CRY 224 clocks = <&gcc GCC_CRYPTO_CLK>,
226 <&gcc GCC_CRY 225 <&gcc GCC_CRYPTO_AXI_CLK>,
227 <&gcc GCC_CRY 226 <&gcc GCC_CRYPTO_AHB_CLK>;
228 clock-names = "core", 227 clock-names = "core", "bus", "iface";
229 #reset-cells = <1>; 228 #reset-cells = <1>;
230 229
231 qcom,dload-mode = <&tc 230 qcom,dload-mode = <&tcsr 0x6100>;
232 }; 231 };
233 }; 232 };
234 233
235 memory@80000000 { 234 memory@80000000 {
236 device_type = "memory"; 235 device_type = "memory";
237 /* We expect the bootloader to 236 /* We expect the bootloader to fill in the reg */
238 reg = <0x0 0x80000000 0x0 0x0> 237 reg = <0x0 0x80000000 0x0 0x0>;
239 }; 238 };
240 239
241 pmu { 240 pmu {
242 compatible = "arm,cortex-a53-p 241 compatible = "arm,cortex-a53-pmu";
243 interrupts = <GIC_PPI 7 (GIC_C 242 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
244 }; 243 };
245 244
246 rpm: remoteproc { 245 rpm: remoteproc {
247 compatible = "qcom,msm8936-rpm 246 compatible = "qcom,msm8936-rpm-proc", "qcom,rpm-proc";
248 247
249 smd-edge { 248 smd-edge {
250 interrupts = <GIC_SPI 249 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
251 qcom,ipc = <&apcs1_mbo 250 qcom,ipc = <&apcs1_mbox 8 0>;
252 qcom,smd-edge = <15>; 251 qcom,smd-edge = <15>;
253 252
254 rpm_requests: rpm-requ 253 rpm_requests: rpm-requests {
255 compatible = " !! 254 compatible = "qcom,rpm-msm8936";
256 qcom,smd-chann 255 qcom,smd-channels = "rpm_requests";
257 256
258 rpmcc: clock-c 257 rpmcc: clock-controller {
259 compat 258 compatible = "qcom,rpmcc-msm8936", "qcom,rpmcc";
260 #clock 259 #clock-cells = <1>;
261 clock- 260 clock-names = "xo";
262 clocks 261 clocks = <&xo_board>;
263 }; 262 };
264 263
265 rpmpd: power-c 264 rpmpd: power-controller {
266 compat 265 compatible = "qcom,msm8939-rpmpd";
267 #power 266 #power-domain-cells = <1>;
268 operat 267 operating-points-v2 = <&rpmpd_opp_table>;
269 268
270 rpmpd_ 269 rpmpd_opp_table: opp-table {
271 270 compatible = "operating-points-v2";
272 271
273 272 rpmpd_opp_ret: opp1 {
274 273 opp-level = <1>;
275 274 };
276 275
277 276 rpmpd_opp_svs_krait: opp2 {
278 277 opp-level = <2>;
279 278 };
280 279
281 280 rpmpd_opp_svs_soc: opp3 {
282 281 opp-level = <3>;
283 282 };
284 283
285 284 rpmpd_opp_nom: opp4 {
286 285 opp-level = <4>;
287 286 };
288 287
289 288 rpmpd_opp_turbo: opp5 {
290 289 opp-level = <5>;
291 290 };
292 291
293 292 rpmpd_opp_super_turbo: opp6 {
294 293 opp-level = <6>;
295 294 };
296 }; 295 };
297 }; 296 };
298 }; 297 };
299 }; 298 };
300 }; 299 };
301 300
302 reserved-memory { 301 reserved-memory {
303 #address-cells = <2>; 302 #address-cells = <2>;
304 #size-cells = <2>; 303 #size-cells = <2>;
305 ranges; 304 ranges;
306 305
307 tz-apps@86000000 { 306 tz-apps@86000000 {
308 reg = <0x0 0x86000000 307 reg = <0x0 0x86000000 0x0 0x300000>;
309 no-map; 308 no-map;
310 }; 309 };
311 310
312 smem@86300000 { 311 smem@86300000 {
313 compatible = "qcom,sme 312 compatible = "qcom,smem";
314 reg = <0x0 0x86300000 313 reg = <0x0 0x86300000 0x0 0x100000>;
315 no-map; 314 no-map;
316 315
317 hwlocks = <&tcsr_mutex 316 hwlocks = <&tcsr_mutex 3>;
318 qcom,rpm-msg-ram = <&r 317 qcom,rpm-msg-ram = <&rpm_msg_ram>;
319 }; 318 };
320 319
321 hypervisor@86400000 { 320 hypervisor@86400000 {
322 reg = <0x0 0x86400000 321 reg = <0x0 0x86400000 0x0 0x100000>;
323 no-map; 322 no-map;
324 }; 323 };
325 324
326 tz@86500000 { 325 tz@86500000 {
327 reg = <0x0 0x86500000 326 reg = <0x0 0x86500000 0x0 0x180000>;
328 no-map; 327 no-map;
329 }; 328 };
330 329
331 reserved@86680000 { 330 reserved@86680000 {
332 reg = <0x0 0x86680000 331 reg = <0x0 0x86680000 0x0 0x80000>;
333 no-map; 332 no-map;
334 }; 333 };
335 334
336 rmtfs@86700000 { 335 rmtfs@86700000 {
337 compatible = "qcom,rmt 336 compatible = "qcom,rmtfs-mem";
338 reg = <0x0 0x86700000 337 reg = <0x0 0x86700000 0x0 0xe0000>;
339 no-map; 338 no-map;
340 339
341 qcom,client-id = <1>; 340 qcom,client-id = <1>;
342 }; 341 };
343 342
344 rfsa@867e0000 { 343 rfsa@867e0000 {
345 reg = <0x0 0x867e0000 344 reg = <0x0 0x867e0000 0x0 0x20000>;
346 no-map; 345 no-map;
347 }; 346 };
348 347
349 mpss_mem: mpss@86800000 { 348 mpss_mem: mpss@86800000 {
350 /* !! 349 reg = <0x0 0x86800000 0x0 0x5500000>;
351 * The memory region f <<
352 * relocatable and cou <<
353 * However, many firmw <<
354 * loaded to some spec <<
355 * define reliable all <<
356 * <<
357 * alignment = <0x0 0x <<
358 * alloc-ranges = <0x0 <<
359 */ <<
360 reg = <0x0 0x86800000 <<
361 no-map; 350 no-map;
362 status = "disabled"; <<
363 }; 351 };
364 352
365 wcnss_mem: wcnss { !! 353 wcnss_mem: wcnss@8bd00000 {
366 size = <0x0 0x600000>; !! 354 reg = <0x0 0x8bd00000 0x0 0x600000>;
367 alignment = <0x0 0x100 <<
368 alloc-ranges = <0x0 0x <<
369 no-map; 355 no-map;
370 status = "disabled"; <<
371 }; 356 };
372 357
373 venus_mem: venus { !! 358 venus_mem: venus@8c300000 {
374 size = <0x0 0x500000>; !! 359 reg = <0x0 0x8c300000 0x0 0x800000>;
375 alignment = <0x0 0x100 <<
376 alloc-ranges = <0x0 0x <<
377 no-map; 360 no-map;
378 status = "disabled"; <<
379 }; 361 };
380 362
381 mba_mem: mba { !! 363 mba_mem: mba@8cb00000 {
382 size = <0x0 0x100000>; !! 364 reg = <0x0 0x8cb00000 0x0 0x100000>;
383 alignment = <0x0 0x100 <<
384 alloc-ranges = <0x0 0x <<
385 no-map; 365 no-map;
386 status = "disabled"; <<
387 }; 366 };
388 }; 367 };
389 368
390 smp2p-hexagon { 369 smp2p-hexagon {
391 compatible = "qcom,smp2p"; 370 compatible = "qcom,smp2p";
392 qcom,smem = <435>, <428>; 371 qcom,smem = <435>, <428>;
393 372
394 interrupts = <GIC_SPI 27 IRQ_T 373 interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>;
395 374
396 mboxes = <&apcs1_mbox 14>; 375 mboxes = <&apcs1_mbox 14>;
397 376
398 qcom,local-pid = <0>; 377 qcom,local-pid = <0>;
399 qcom,remote-pid = <1>; 378 qcom,remote-pid = <1>;
400 379
401 hexagon_smp2p_out: master-kern 380 hexagon_smp2p_out: master-kernel {
402 qcom,entry-name = "mas 381 qcom,entry-name = "master-kernel";
403 382
404 #qcom,smem-state-cells 383 #qcom,smem-state-cells = <1>;
405 }; 384 };
406 385
407 hexagon_smp2p_in: slave-kernel 386 hexagon_smp2p_in: slave-kernel {
408 qcom,entry-name = "sla 387 qcom,entry-name = "slave-kernel";
409 388
410 interrupt-controller; 389 interrupt-controller;
411 #interrupt-cells = <2> 390 #interrupt-cells = <2>;
412 }; 391 };
413 }; 392 };
414 393
415 smp2p-wcnss { 394 smp2p-wcnss {
416 compatible = "qcom,smp2p"; 395 compatible = "qcom,smp2p";
417 qcom,smem = <451>, <431>; 396 qcom,smem = <451>, <431>;
418 397
419 interrupts = <GIC_SPI 143 IRQ_ 398 interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>;
420 399
421 mboxes = <&apcs1_mbox 18>; 400 mboxes = <&apcs1_mbox 18>;
422 401
423 qcom,local-pid = <0>; 402 qcom,local-pid = <0>;
424 qcom,remote-pid = <4>; 403 qcom,remote-pid = <4>;
425 404
426 wcnss_smp2p_in: slave-kernel { 405 wcnss_smp2p_in: slave-kernel {
427 qcom,entry-name = "sla 406 qcom,entry-name = "slave-kernel";
428 407
429 interrupt-controller; 408 interrupt-controller;
430 #interrupt-cells = <2> 409 #interrupt-cells = <2>;
431 }; 410 };
432 411
433 wcnss_smp2p_out: master-kernel 412 wcnss_smp2p_out: master-kernel {
434 qcom,entry-name = "mas 413 qcom,entry-name = "master-kernel";
435 414
436 #qcom,smem-state-cells 415 #qcom,smem-state-cells = <1>;
437 }; 416 };
438 }; 417 };
439 418
440 smsm { 419 smsm {
441 compatible = "qcom,smsm"; 420 compatible = "qcom,smsm";
442 421
443 #address-cells = <1>; 422 #address-cells = <1>;
444 #size-cells = <0>; 423 #size-cells = <0>;
445 424
446 mboxes = <0>, <&apcs1_mbox 13> !! 425 qcom,ipc-1 = <&apcs1_mbox 8 13>;
>> 426 qcom,ipc-3 = <&apcs1_mbox 8 19>;
447 427
448 apps_smsm: apps@0 { 428 apps_smsm: apps@0 {
449 reg = <0>; 429 reg = <0>;
450 430
451 #qcom,smem-state-cells 431 #qcom,smem-state-cells = <1>;
452 }; 432 };
453 433
454 hexagon_smsm: hexagon@1 { 434 hexagon_smsm: hexagon@1 {
455 reg = <1>; 435 reg = <1>;
456 interrupts = <GIC_SPI 436 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
457 437
458 interrupt-controller; 438 interrupt-controller;
459 #interrupt-cells = <2> 439 #interrupt-cells = <2>;
460 }; 440 };
461 441
462 wcnss_smsm: wcnss@6 { 442 wcnss_smsm: wcnss@6 {
463 reg = <6>; 443 reg = <6>;
464 interrupts = <GIC_SPI 444 interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>;
465 445
466 interrupt-controller; 446 interrupt-controller;
467 #interrupt-cells = <2> 447 #interrupt-cells = <2>;
468 }; 448 };
469 }; 449 };
470 450
471 soc: soc@0 { 451 soc: soc@0 {
472 compatible = "simple-bus"; 452 compatible = "simple-bus";
473 #address-cells = <1>; 453 #address-cells = <1>;
474 #size-cells = <1>; 454 #size-cells = <1>;
475 ranges = <0 0 0 0xffffffff>; 455 ranges = <0 0 0 0xffffffff>;
476 456
477 rng@22000 { 457 rng@22000 {
478 compatible = "qcom,prn 458 compatible = "qcom,prng";
479 reg = <0x00022000 0x20 459 reg = <0x00022000 0x200>;
480 clocks = <&gcc GCC_PRN 460 clocks = <&gcc GCC_PRNG_AHB_CLK>;
481 clock-names = "core"; 461 clock-names = "core";
482 }; 462 };
483 463
484 qfprom: qfprom@5c000 { 464 qfprom: qfprom@5c000 {
485 compatible = "qcom,msm 465 compatible = "qcom,msm8916-qfprom", "qcom,qfprom";
486 reg = <0x0005c000 0x10 466 reg = <0x0005c000 0x1000>;
487 #address-cells = <1>; 467 #address-cells = <1>;
488 #size-cells = <1>; 468 #size-cells = <1>;
489 469
490 tsens_base1: base1@a0 470 tsens_base1: base1@a0 {
491 reg = <0xa0 0x 471 reg = <0xa0 0x1>;
492 bits = <0 8>; 472 bits = <0 8>;
493 }; 473 };
494 474
495 tsens_s6_p1: s6-p1@a1 475 tsens_s6_p1: s6-p1@a1 {
496 reg = <0xa1 0x 476 reg = <0xa1 0x1>;
497 bits = <0 6>; 477 bits = <0 6>;
498 }; 478 };
499 479
500 tsens_s6_p2: s6-p2@a1 480 tsens_s6_p2: s6-p2@a1 {
501 reg = <0xa1 0x 481 reg = <0xa1 0x2>;
502 bits = <6 6>; 482 bits = <6 6>;
503 }; 483 };
504 484
505 tsens_s7_p1: s7-p1@a2 485 tsens_s7_p1: s7-p1@a2 {
506 reg = <0xa2 0x 486 reg = <0xa2 0x2>;
507 bits = <4 6>; 487 bits = <4 6>;
508 }; 488 };
509 489
510 tsens_s7_p2: s7-p2@a3 490 tsens_s7_p2: s7-p2@a3 {
511 reg = <0xa3 0x 491 reg = <0xa3 0x1>;
512 bits = <2 6>; 492 bits = <2 6>;
513 }; 493 };
514 494
515 tsens_s8_p1: s8-p1@a4 495 tsens_s8_p1: s8-p1@a4 {
516 reg = <0xa4 0x 496 reg = <0xa4 0x1>;
517 bits = <0 6>; 497 bits = <0 6>;
518 }; 498 };
519 499
520 tsens_s8_p2: s8-p2@a4 500 tsens_s8_p2: s8-p2@a4 {
521 reg = <0xa4 0x 501 reg = <0xa4 0x2>;
522 bits = <6 6>; 502 bits = <6 6>;
523 }; 503 };
524 504
525 tsens_s9_p1: s9-p1@a5 505 tsens_s9_p1: s9-p1@a5 {
526 reg = <0xa5 0x 506 reg = <0xa5 0x2>;
527 bits = <4 6>; 507 bits = <4 6>;
528 }; 508 };
529 509
530 tsens_s9_p2: s9-p2@a6 510 tsens_s9_p2: s9-p2@a6 {
531 reg = <0xa6 0x 511 reg = <0xa6 0x1>;
532 bits = <2 6>; 512 bits = <2 6>;
533 }; 513 };
534 514
535 tsens_base2: base2@a7 515 tsens_base2: base2@a7 {
536 reg = <0xa7 0x 516 reg = <0xa7 0x1>;
537 bits = <0 8>; 517 bits = <0 8>;
538 }; 518 };
539 519
540 tsens_mode: mode@d0 { 520 tsens_mode: mode@d0 {
541 reg = <0xd0 0x 521 reg = <0xd0 0x1>;
542 bits = <0 3>; 522 bits = <0 3>;
543 }; 523 };
544 524
545 tsens_s0_p1: s0-p1@d0 525 tsens_s0_p1: s0-p1@d0 {
546 reg = <0xd0 0x 526 reg = <0xd0 0x2>;
547 bits = <3 6>; 527 bits = <3 6>;
548 }; 528 };
549 529
550 tsens_s0_p2: s0-p1@d1 530 tsens_s0_p2: s0-p1@d1 {
551 reg = <0xd1 0x 531 reg = <0xd1 0x1>;
552 bits = <1 6>; 532 bits = <1 6>;
553 }; 533 };
554 534
555 tsens_s1_p1: s1-p1@d1 535 tsens_s1_p1: s1-p1@d1 {
556 reg = <0xd1 0x 536 reg = <0xd1 0x2>;
557 bits = <7 6>; 537 bits = <7 6>;
558 }; 538 };
559 539
560 tsens_s1_p2: s1-p2@d2 540 tsens_s1_p2: s1-p2@d2 {
561 reg = <0xd2 0x 541 reg = <0xd2 0x2>;
562 bits = <5 6>; 542 bits = <5 6>;
563 }; 543 };
564 544
565 tsens_s2_p1: s2-p1@d3 545 tsens_s2_p1: s2-p1@d3 {
566 reg = <0xd3 0x 546 reg = <0xd3 0x2>;
567 bits = <3 6>; 547 bits = <3 6>;
568 }; 548 };
569 549
570 tsens_s2_p2: s2-p2@d4 550 tsens_s2_p2: s2-p2@d4 {
571 reg = <0xd4 0x 551 reg = <0xd4 0x1>;
572 bits = <1 6>; 552 bits = <1 6>;
573 }; 553 };
574 554
575 tsens_s3_p1: s3-p1@d4 555 tsens_s3_p1: s3-p1@d4 {
576 reg = <0xd4 0x 556 reg = <0xd4 0x2>;
577 bits = <7 6>; 557 bits = <7 6>;
578 }; 558 };
579 559
580 tsens_s3_p2: s3-p2@d5 560 tsens_s3_p2: s3-p2@d5 {
581 reg = <0xd5 0x 561 reg = <0xd5 0x2>;
582 bits = <5 6>; 562 bits = <5 6>;
583 }; 563 };
584 564
585 tsens_s5_p1: s5-p1@d6 565 tsens_s5_p1: s5-p1@d6 {
586 reg = <0xd6 0x 566 reg = <0xd6 0x2>;
587 bits = <3 6>; 567 bits = <3 6>;
588 }; 568 };
589 569
590 tsens_s5_p2: s5-p2@d7 570 tsens_s5_p2: s5-p2@d7 {
591 reg = <0xd7 0x 571 reg = <0xd7 0x1>;
592 bits = <1 6>; 572 bits = <1 6>;
593 }; 573 };
594 }; 574 };
595 575
596 rpm_msg_ram: sram@60000 { 576 rpm_msg_ram: sram@60000 {
597 compatible = "qcom,rpm 577 compatible = "qcom,rpm-msg-ram";
598 reg = <0x00060000 0x80 578 reg = <0x00060000 0x8000>;
599 }; 579 };
600 580
601 bimc: interconnect@400000 { 581 bimc: interconnect@400000 {
602 compatible = "qcom,msm 582 compatible = "qcom,msm8939-bimc";
603 reg = <0x00400000 0x62 583 reg = <0x00400000 0x62000>;
>> 584 clock-names = "bus", "bus_a";
>> 585 clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
>> 586 <&rpmcc RPM_SMD_BIMC_A_CLK>;
604 #interconnect-cells = 587 #interconnect-cells = <1>;
605 }; 588 };
606 589
607 tsens: thermal-sensor@4a9000 { 590 tsens: thermal-sensor@4a9000 {
608 compatible = "qcom,msm 591 compatible = "qcom,msm8939-tsens", "qcom,tsens-v0_1";
609 reg = <0x004a9000 0x10 592 reg = <0x004a9000 0x1000>, /* TM */
610 <0x004a8000 0x10 593 <0x004a8000 0x1000>; /* SROT */
611 nvmem-cells = <&tsens_ 594 nvmem-cells = <&tsens_mode>,
612 <&tsens_ 595 <&tsens_base1>, <&tsens_base2>,
613 <&tsens_ 596 <&tsens_s0_p1>, <&tsens_s0_p2>,
614 <&tsens_ 597 <&tsens_s1_p1>, <&tsens_s1_p2>,
615 <&tsens_ 598 <&tsens_s2_p1>, <&tsens_s2_p2>,
616 <&tsens_ 599 <&tsens_s3_p1>, <&tsens_s3_p2>,
617 <&tsens_ 600 <&tsens_s5_p1>, <&tsens_s5_p2>,
618 <&tsens_ 601 <&tsens_s6_p1>, <&tsens_s6_p2>,
619 <&tsens_ 602 <&tsens_s7_p1>, <&tsens_s7_p2>,
620 <&tsens_ 603 <&tsens_s8_p1>, <&tsens_s8_p2>,
621 <&tsens_ 604 <&tsens_s9_p1>, <&tsens_s9_p2>;
622 nvmem-cell-names = "mo 605 nvmem-cell-names = "mode",
623 "ba 606 "base1", "base2",
624 "s0 607 "s0_p1", "s0_p2",
625 "s1 608 "s1_p1", "s1_p2",
626 "s2 609 "s2_p1", "s2_p2",
627 "s3 610 "s3_p1", "s3_p2",
628 "s5 611 "s5_p1", "s5_p2",
629 "s6 612 "s6_p1", "s6_p2",
630 "s7 613 "s7_p1", "s7_p2",
631 "s8 614 "s8_p1", "s8_p2",
632 "s9 615 "s9_p1", "s9_p2";
633 #qcom,sensors = <9>; 616 #qcom,sensors = <9>;
634 interrupts = <GIC_SPI 617 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
635 interrupt-names = "upl 618 interrupt-names = "uplow";
636 #thermal-sensor-cells 619 #thermal-sensor-cells = <1>;
637 }; 620 };
638 621
639 restart@4ab000 { 622 restart@4ab000 {
640 compatible = "qcom,psh 623 compatible = "qcom,pshold";
641 reg = <0x004ab000 0x4> 624 reg = <0x004ab000 0x4>;
642 }; 625 };
643 626
644 pcnoc: interconnect@500000 { 627 pcnoc: interconnect@500000 {
645 compatible = "qcom,msm 628 compatible = "qcom,msm8939-pcnoc";
646 reg = <0x00500000 0x11 629 reg = <0x00500000 0x11000>;
>> 630 clock-names = "bus", "bus_a";
>> 631 clocks = <&rpmcc RPM_SMD_PCNOC_CLK>,
>> 632 <&rpmcc RPM_SMD_PCNOC_A_CLK>;
647 #interconnect-cells = 633 #interconnect-cells = <1>;
648 }; 634 };
649 635
650 snoc: interconnect@580000 { 636 snoc: interconnect@580000 {
651 compatible = "qcom,msm 637 compatible = "qcom,msm8939-snoc";
652 reg = <0x00580000 0x14 638 reg = <0x00580000 0x14080>;
>> 639 clock-names = "bus", "bus_a";
>> 640 clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
>> 641 <&rpmcc RPM_SMD_SNOC_A_CLK>;
653 #interconnect-cells = 642 #interconnect-cells = <1>;
654 643
655 snoc_mm: interconnect- 644 snoc_mm: interconnect-snoc {
656 compatible = " 645 compatible = "qcom,msm8939-snoc-mm";
>> 646 clock-names = "bus", "bus_a";
>> 647 clocks = <&rpmcc RPM_SMD_SYSMMNOC_CLK>,
>> 648 <&rpmcc RPM_SMD_SYSMMNOC_A_CLK>;
657 #interconnect- 649 #interconnect-cells = <1>;
658 }; 650 };
659 }; 651 };
660 652
661 tlmm: pinctrl@1000000 { 653 tlmm: pinctrl@1000000 {
662 compatible = "qcom,msm 654 compatible = "qcom,msm8916-pinctrl";
663 reg = <0x01000000 0x30 655 reg = <0x01000000 0x300000>;
664 interrupts = <GIC_SPI 656 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
665 gpio-controller; 657 gpio-controller;
666 gpio-ranges = <&tlmm 0 658 gpio-ranges = <&tlmm 0 0 122>;
667 #gpio-cells = <2>; 659 #gpio-cells = <2>;
668 interrupt-controller; 660 interrupt-controller;
669 #interrupt-cells = <2> 661 #interrupt-cells = <2>;
670 662
671 blsp_i2c1_default: bls 663 blsp_i2c1_default: blsp-i2c1-default-state {
672 pins = "gpio2" 664 pins = "gpio2", "gpio3";
673 function = "bl 665 function = "blsp_i2c1";
674 drive-strength 666 drive-strength = <2>;
675 bias-disable; 667 bias-disable;
676 }; 668 };
677 669
678 blsp_i2c1_sleep: blsp- 670 blsp_i2c1_sleep: blsp-i2c1-sleep-state {
679 pins = "gpio2" 671 pins = "gpio2", "gpio3";
680 function = "gp 672 function = "gpio";
681 drive-strength 673 drive-strength = <2>;
682 bias-disable; 674 bias-disable;
683 }; 675 };
684 676
685 blsp_i2c2_default: bls 677 blsp_i2c2_default: blsp-i2c2-default-state {
686 pins = "gpio6" 678 pins = "gpio6", "gpio7";
687 function = "bl 679 function = "blsp_i2c2";
688 drive-strength 680 drive-strength = <2>;
689 bias-disable; 681 bias-disable;
690 }; 682 };
691 683
692 blsp_i2c2_sleep: blsp- 684 blsp_i2c2_sleep: blsp-i2c2-sleep-state {
693 pins = "gpio6" 685 pins = "gpio6", "gpio7";
694 function = "gp 686 function = "gpio";
695 drive-strength 687 drive-strength = <2>;
696 bias-disable; 688 bias-disable;
697 }; 689 };
698 690
699 blsp_i2c3_default: bls 691 blsp_i2c3_default: blsp-i2c3-default-state {
700 pins = "gpio10 692 pins = "gpio10", "gpio11";
701 function = "bl 693 function = "blsp_i2c3";
702 drive-strength 694 drive-strength = <2>;
703 bias-disable; 695 bias-disable;
704 }; 696 };
705 697
706 blsp_i2c3_sleep: blsp- 698 blsp_i2c3_sleep: blsp-i2c3-sleep-state {
707 pins = "gpio10 699 pins = "gpio10", "gpio11";
708 function = "gp 700 function = "gpio";
709 drive-strength 701 drive-strength = <2>;
710 bias-disable; 702 bias-disable;
711 }; 703 };
712 704
713 blsp_i2c4_default: bls 705 blsp_i2c4_default: blsp-i2c4-default-state {
714 pins = "gpio14 706 pins = "gpio14", "gpio15";
715 function = "bl 707 function = "blsp_i2c4";
716 drive-strength 708 drive-strength = <2>;
717 bias-disable; 709 bias-disable;
718 }; 710 };
719 711
720 blsp_i2c4_sleep: blsp- 712 blsp_i2c4_sleep: blsp-i2c4-sleep-state {
721 pins = "gpio14 713 pins = "gpio14", "gpio15";
722 function = "gp 714 function = "gpio";
723 drive-strength 715 drive-strength = <2>;
724 bias-disable; 716 bias-disable;
725 }; 717 };
726 718
727 blsp_i2c5_default: bls 719 blsp_i2c5_default: blsp-i2c5-default-state {
728 pins = "gpio18 720 pins = "gpio18", "gpio19";
729 function = "bl 721 function = "blsp_i2c5";
730 drive-strength 722 drive-strength = <2>;
731 bias-disable; 723 bias-disable;
732 }; 724 };
733 725
734 blsp_i2c5_sleep: blsp- 726 blsp_i2c5_sleep: blsp-i2c5-sleep-state {
735 pins = "gpio18 727 pins = "gpio18", "gpio19";
736 function = "gp 728 function = "gpio";
737 drive-strength 729 drive-strength = <2>;
738 bias-disable; 730 bias-disable;
739 }; 731 };
740 732
741 blsp_i2c6_default: bls 733 blsp_i2c6_default: blsp-i2c6-default-state {
742 pins = "gpio22 734 pins = "gpio22", "gpio23";
743 function = "bl 735 function = "blsp_i2c6";
744 drive-strength 736 drive-strength = <2>;
745 bias-disable; 737 bias-disable;
746 }; 738 };
747 739
748 blsp_i2c6_sleep: blsp- 740 blsp_i2c6_sleep: blsp-i2c6-sleep-state {
749 pins = "gpio22 741 pins = "gpio22", "gpio23";
750 function = "gp 742 function = "gpio";
751 drive-strength 743 drive-strength = <2>;
752 bias-disable; 744 bias-disable;
753 }; 745 };
754 746
755 blsp_spi1_default: bls 747 blsp_spi1_default: blsp-spi1-default-state {
756 spi-pins { 748 spi-pins {
757 pins = 749 pins = "gpio0", "gpio1", "gpio3";
758 functi 750 function = "blsp_spi1";
759 drive- 751 drive-strength = <12>;
760 bias-d 752 bias-disable;
761 }; 753 };
762 754
763 cs-pins { 755 cs-pins {
764 pins = 756 pins = "gpio2";
765 functi 757 function = "gpio";
766 drive- 758 drive-strength = <16>;
767 bias-d 759 bias-disable;
768 output 760 output-high;
769 }; 761 };
770 }; 762 };
771 763
772 blsp_spi1_sleep: blsp- 764 blsp_spi1_sleep: blsp-spi1-sleep-state {
773 pins = "gpio0" 765 pins = "gpio0", "gpio1", "gpio2", "gpio3";
774 function = "gp 766 function = "gpio";
775 drive-strength 767 drive-strength = <2>;
776 bias-pull-down 768 bias-pull-down;
777 }; 769 };
778 770
779 blsp_spi2_default: bls 771 blsp_spi2_default: blsp-spi2-default-state {
780 spi-pins { 772 spi-pins {
781 pins = 773 pins = "gpio4", "gpio5", "gpio7";
782 functi 774 function = "blsp_spi2";
783 drive- 775 drive-strength = <12>;
784 bias-d 776 bias-disable;
785 }; 777 };
786 778
787 cs-pins { 779 cs-pins {
788 pins = 780 pins = "gpio6";
789 functi 781 function = "gpio";
790 drive- 782 drive-strength = <16>;
791 bias-d 783 bias-disable;
792 output 784 output-high;
793 }; 785 };
794 }; 786 };
795 787
796 blsp_spi2_sleep: blsp- 788 blsp_spi2_sleep: blsp-spi2-sleep-state {
797 pins = "gpio4" 789 pins = "gpio4", "gpio5", "gpio6", "gpio7";
798 function = "gp 790 function = "gpio";
799 drive-strength 791 drive-strength = <2>;
800 bias-pull-down 792 bias-pull-down;
801 }; 793 };
802 794
803 blsp_spi3_default: bls 795 blsp_spi3_default: blsp-spi3-default-state {
804 spi-pins { 796 spi-pins {
805 pins = 797 pins = "gpio8", "gpio9", "gpio11";
806 functi 798 function = "blsp_spi3";
807 drive- 799 drive-strength = <12>;
808 bias-d 800 bias-disable;
809 }; 801 };
810 802
811 cs-pins { 803 cs-pins {
812 pins = 804 pins = "gpio10";
813 functi 805 function = "gpio";
814 drive- 806 drive-strength = <16>;
815 bias-d 807 bias-disable;
816 output 808 output-high;
817 }; 809 };
818 }; 810 };
819 811
820 blsp_spi3_sleep: blsp- 812 blsp_spi3_sleep: blsp-spi3-sleep-state {
821 pins = "gpio8" 813 pins = "gpio8", "gpio9", "gpio10", "gpio11";
822 function = "gp 814 function = "gpio";
823 drive-strength 815 drive-strength = <2>;
824 bias-pull-down 816 bias-pull-down;
825 }; 817 };
826 818
827 blsp_spi4_default: bls 819 blsp_spi4_default: blsp-spi4-default-state {
828 spi-pins { 820 spi-pins {
829 pins = 821 pins = "gpio12", "gpio13", "gpio15";
830 functi 822 function = "blsp_spi4";
831 drive- 823 drive-strength = <12>;
832 bias-d 824 bias-disable;
833 }; 825 };
834 826
835 cs-pins { 827 cs-pins {
836 pins = 828 pins = "gpio14";
837 functi 829 function = "gpio";
838 drive- 830 drive-strength = <16>;
839 bias-d 831 bias-disable;
840 output 832 output-high;
841 }; 833 };
842 }; 834 };
843 835
844 blsp_spi4_sleep: blsp- 836 blsp_spi4_sleep: blsp-spi4-sleep-state {
845 pins = "gpio12 837 pins = "gpio12", "gpio13", "gpio14", "gpio15";
846 function = "gp 838 function = "gpio";
847 drive-strength 839 drive-strength = <2>;
848 bias-pull-down 840 bias-pull-down;
849 }; 841 };
850 842
851 blsp_spi5_default: bls 843 blsp_spi5_default: blsp-spi5-default-state {
852 spi-pins { 844 spi-pins {
853 pins = 845 pins = "gpio16", "gpio17", "gpio19";
854 functi 846 function = "blsp_spi5";
855 drive- 847 drive-strength = <12>;
856 bias-d 848 bias-disable;
857 }; 849 };
858 850
859 cs-pins { 851 cs-pins {
860 pins = 852 pins = "gpio18";
861 functi 853 function = "gpio";
862 drive- 854 drive-strength = <16>;
863 bias-d 855 bias-disable;
864 output 856 output-high;
865 }; 857 };
866 }; 858 };
867 859
868 blsp_spi5_sleep: blsp- 860 blsp_spi5_sleep: blsp-spi5-sleep-state {
869 pins = "gpio16 861 pins = "gpio16", "gpio17", "gpio18", "gpio19";
870 function = "gp 862 function = "gpio";
871 drive-strength 863 drive-strength = <2>;
872 bias-pull-down 864 bias-pull-down;
873 }; 865 };
874 866
875 blsp_spi6_default: bls 867 blsp_spi6_default: blsp-spi6-default-state {
876 spi-pins { 868 spi-pins {
877 pins = 869 pins = "gpio20", "gpio21", "gpio23";
878 functi 870 function = "blsp_spi6";
879 drive- 871 drive-strength = <12>;
880 bias-d 872 bias-disable;
881 }; 873 };
882 874
883 cs-pins { 875 cs-pins {
884 pins = 876 pins = "gpio22";
885 functi 877 function = "gpio";
886 drive- 878 drive-strength = <16>;
887 bias-d 879 bias-disable;
888 output 880 output-high;
889 }; 881 };
890 }; 882 };
891 883
892 blsp_spi6_sleep: blsp- 884 blsp_spi6_sleep: blsp-spi6-sleep-state {
893 pins = "gpio20 885 pins = "gpio20", "gpio21", "gpio22", "gpio23";
894 function = "gp 886 function = "gpio";
895 drive-strength 887 drive-strength = <2>;
896 bias-pull-down 888 bias-pull-down;
897 }; 889 };
898 890
899 blsp_uart1_default: bl 891 blsp_uart1_default: blsp-uart1-default-state {
900 pins = "gpio0" 892 pins = "gpio0", "gpio1", "gpio2", "gpio3";
901 function = "bl 893 function = "blsp_uart1";
902 drive-strength 894 drive-strength = <16>;
903 bias-disable; 895 bias-disable;
904 }; 896 };
905 897
906 blsp_uart1_sleep: blsp 898 blsp_uart1_sleep: blsp-uart1-sleep-state {
907 pins = "gpio0" 899 pins = "gpio0", "gpio1", "gpio2", "gpio3";
908 function = "gp 900 function = "gpio";
909 drive-strength 901 drive-strength = <2>;
910 bias-pull-down 902 bias-pull-down;
911 }; 903 };
912 904
913 blsp_uart2_default: bl 905 blsp_uart2_default: blsp-uart2-default-state {
914 pins = "gpio4" 906 pins = "gpio4", "gpio5";
915 function = "bl 907 function = "blsp_uart2";
916 drive-strength 908 drive-strength = <16>;
917 bias-disable; 909 bias-disable;
918 }; 910 };
919 911
920 blsp_uart2_sleep: blsp 912 blsp_uart2_sleep: blsp-uart2-sleep-state {
921 pins = "gpio4" 913 pins = "gpio4", "gpio5";
922 function = "gp 914 function = "gpio";
923 drive-strength 915 drive-strength = <2>;
924 bias-pull-down 916 bias-pull-down;
925 }; 917 };
926 918
927 camera_front_default: 919 camera_front_default: camera-front-default-state {
928 pwdn-pins { 920 pwdn-pins {
929 pins = 921 pins = "gpio33";
930 functi 922 function = "gpio";
931 drive- 923 drive-strength = <16>;
932 bias-d 924 bias-disable;
933 }; 925 };
934 926
935 rst-pins { 927 rst-pins {
936 pins = 928 pins = "gpio28";
937 functi 929 function = "gpio";
938 drive- 930 drive-strength = <16>;
939 bias-d 931 bias-disable;
940 }; 932 };
941 933
942 mclk1-pins { 934 mclk1-pins {
943 pins = 935 pins = "gpio27";
944 functi 936 function = "cam_mclk1";
945 drive- 937 drive-strength = <16>;
946 bias-d 938 bias-disable;
947 }; 939 };
948 }; 940 };
949 941
950 camera_rear_default: c 942 camera_rear_default: camera-rear-default-state {
951 pwdn-pins { 943 pwdn-pins {
952 pins = 944 pins = "gpio34";
953 functi 945 function = "gpio";
954 drive- 946 drive-strength = <16>;
955 bias-d 947 bias-disable;
956 }; 948 };
957 949
958 rst-pins { 950 rst-pins {
959 pins = 951 pins = "gpio35";
960 functi 952 function = "gpio";
961 drive- 953 drive-strength = <16>;
962 bias-d 954 bias-disable;
963 }; 955 };
964 956
965 mclk0-pins { 957 mclk0-pins {
966 pins = 958 pins = "gpio26";
967 functi 959 function = "cam_mclk0";
968 drive- 960 drive-strength = <16>;
969 bias-d 961 bias-disable;
970 }; 962 };
971 }; 963 };
972 964
973 cci0_default: cci0-def 965 cci0_default: cci0-default-state {
974 pins = "gpio29 966 pins = "gpio29", "gpio30";
975 function = "cc 967 function = "cci_i2c";
976 drive-strength 968 drive-strength = <16>;
977 bias-disable; 969 bias-disable;
978 }; 970 };
979 971
980 cdc_dmic_default: cdc- 972 cdc_dmic_default: cdc-dmic-default-state {
981 clk-pins { 973 clk-pins {
982 pins = 974 pins = "gpio0";
983 functi 975 function = "dmic0_clk";
984 drive- 976 drive-strength = <8>;
985 }; 977 };
986 978
987 data-pins { 979 data-pins {
988 pins = 980 pins = "gpio1";
989 functi 981 function = "dmic0_data";
990 drive- 982 drive-strength = <8>;
991 }; 983 };
992 }; 984 };
993 985
994 cdc_dmic_sleep: cdc-dm 986 cdc_dmic_sleep: cdc-dmic-sleep-state {
995 clk-pins { 987 clk-pins {
996 pins = 988 pins = "gpio0";
997 functi 989 function = "dmic0_clk";
998 drive- 990 drive-strength = <2>;
999 bias-d 991 bias-disable;
1000 }; 992 };
1001 993
1002 data-pins { 994 data-pins {
1003 pins 995 pins = "gpio1";
1004 funct 996 function = "dmic0_data";
1005 drive 997 drive-strength = <2>;
1006 bias- 998 bias-disable;
1007 }; 999 };
1008 }; 1000 };
1009 1001
1010 cdc_pdm_default: cdc- 1002 cdc_pdm_default: cdc-pdm-default-state {
1011 pins = "gpio6 1003 pins = "gpio63", "gpio64", "gpio65", "gpio66",
1012 "gpio6 1004 "gpio67", "gpio68";
1013 function = "c 1005 function = "cdc_pdm0";
1014 drive-strengt 1006 drive-strength = <8>;
1015 bias-disable; 1007 bias-disable;
1016 }; 1008 };
1017 1009
1018 cdc_pdm_sleep: cdc-pd 1010 cdc_pdm_sleep: cdc-pdm-sleep-state {
1019 pins = "gpio6 1011 pins = "gpio63", "gpio64", "gpio65", "gpio66",
1020 "gpio6 1012 "gpio67", "gpio68";
1021 function = "c 1013 function = "cdc_pdm0";
1022 drive-strengt 1014 drive-strength = <2>;
1023 bias-pull-dow 1015 bias-pull-down;
1024 }; 1016 };
1025 1017
1026 pri_mi2s_default: mi2 1018 pri_mi2s_default: mi2s-pri-default-state {
1027 pins = "gpio1 1019 pins = "gpio113", "gpio114", "gpio115", "gpio116";
1028 function = "p 1020 function = "pri_mi2s";
1029 drive-strengt 1021 drive-strength = <8>;
1030 bias-disable; 1022 bias-disable;
1031 }; 1023 };
1032 1024
1033 pri_mi2s_sleep: mi2s- 1025 pri_mi2s_sleep: mi2s-pri-sleep-state {
1034 pins = "gpio1 1026 pins = "gpio113", "gpio114", "gpio115", "gpio116";
1035 function = "p 1027 function = "pri_mi2s";
1036 drive-strengt 1028 drive-strength = <2>;
1037 bias-disable; 1029 bias-disable;
1038 }; 1030 };
1039 1031
1040 pri_mi2s_mclk_default 1032 pri_mi2s_mclk_default: mi2s-pri-mclk-default-state {
1041 pins = "gpio1 1033 pins = "gpio116";
1042 function = "p 1034 function = "pri_mi2s";
1043 drive-strengt 1035 drive-strength = <8>;
1044 bias-disable; 1036 bias-disable;
1045 }; 1037 };
1046 1038
1047 pri_mi2s_mclk_sleep: 1039 pri_mi2s_mclk_sleep: mi2s-pri-mclk-sleep-state {
1048 pins = "gpio1 1040 pins = "gpio116";
1049 function = "p 1041 function = "pri_mi2s";
1050 drive-strengt 1042 drive-strength = <2>;
1051 bias-disable; 1043 bias-disable;
1052 }; 1044 };
1053 1045
1054 pri_mi2s_ws_default: 1046 pri_mi2s_ws_default: mi2s-pri-ws-default-state {
1055 pins = "gpio1 1047 pins = "gpio110";
1056 function = "p 1048 function = "pri_mi2s_ws";
1057 drive-strengt 1049 drive-strength = <8>;
1058 bias-disable; 1050 bias-disable;
1059 }; 1051 };
1060 1052
1061 pri_mi2s_ws_sleep: mi 1053 pri_mi2s_ws_sleep: mi2s-pri-ws-sleep-state {
1062 pins = "gpio1 1054 pins = "gpio110";
1063 function = "p 1055 function = "pri_mi2s_ws";
1064 drive-strengt 1056 drive-strength = <2>;
1065 bias-disable; 1057 bias-disable;
1066 }; 1058 };
1067 1059
1068 sec_mi2s_default: mi2 1060 sec_mi2s_default: mi2s-sec-default-state {
1069 pins = "gpio1 1061 pins = "gpio112", "gpio117", "gpio118", "gpio119";
1070 function = "s 1062 function = "sec_mi2s";
1071 drive-strengt 1063 drive-strength = <8>;
1072 bias-disable; 1064 bias-disable;
1073 }; 1065 };
1074 1066
1075 sec_mi2s_sleep: mi2s- 1067 sec_mi2s_sleep: mi2s-sec-sleep-state {
1076 pins = "gpio1 1068 pins = "gpio112", "gpio117", "gpio118", "gpio119";
1077 function = "s 1069 function = "sec_mi2s";
1078 drive-strengt 1070 drive-strength = <2>;
1079 bias-disable; 1071 bias-disable;
1080 }; 1072 };
1081 1073
1082 sdc1_default: sdc1-de 1074 sdc1_default: sdc1-default-state {
1083 clk-pins { 1075 clk-pins {
1084 pins 1076 pins = "sdc1_clk";
1085 bias- 1077 bias-disable;
1086 drive 1078 drive-strength = <16>;
1087 }; 1079 };
1088 1080
1089 cmd-pins { 1081 cmd-pins {
1090 pins 1082 pins = "sdc1_cmd";
1091 bias- 1083 bias-pull-up;
1092 drive 1084 drive-strength = <10>;
1093 }; 1085 };
1094 1086
1095 data-pins { 1087 data-pins {
1096 pins 1088 pins = "sdc1_data";
1097 bias- 1089 bias-pull-up;
1098 drive 1090 drive-strength = <10>;
1099 }; 1091 };
1100 }; 1092 };
1101 1093
1102 sdc1_sleep: sdc1-slee 1094 sdc1_sleep: sdc1-sleep-state {
1103 clk-pins { 1095 clk-pins {
1104 pins 1096 pins = "sdc1_clk";
1105 bias- 1097 bias-disable;
1106 drive 1098 drive-strength = <2>;
1107 }; 1099 };
1108 1100
1109 cmd-pins { 1101 cmd-pins {
1110 pins 1102 pins = "sdc1_cmd";
1111 bias- 1103 bias-pull-up;
1112 drive 1104 drive-strength = <2>;
1113 }; 1105 };
1114 1106
1115 data-pins { 1107 data-pins {
1116 pins 1108 pins = "sdc1_data";
1117 bias- 1109 bias-pull-up;
1118 drive 1110 drive-strength = <2>;
1119 }; 1111 };
1120 }; 1112 };
1121 1113
1122 sdc2_default: sdc2-de 1114 sdc2_default: sdc2-default-state {
1123 clk-pins { 1115 clk-pins {
1124 pins 1116 pins = "sdc2_clk";
1125 bias- 1117 bias-disable;
1126 drive 1118 drive-strength = <16>;
1127 }; 1119 };
1128 1120
1129 cmd-pins { 1121 cmd-pins {
1130 pins 1122 pins = "sdc2_cmd";
1131 bias- 1123 bias-pull-up;
1132 drive 1124 drive-strength = <10>;
1133 }; 1125 };
1134 1126
1135 data-pins { 1127 data-pins {
1136 pins 1128 pins = "sdc2_data";
1137 bias- 1129 bias-pull-up;
1138 drive 1130 drive-strength = <10>;
1139 }; 1131 };
1140 }; 1132 };
1141 1133
1142 sdc2_sleep: sdc2-slee 1134 sdc2_sleep: sdc2-sleep-state {
1143 clk-pins { 1135 clk-pins {
1144 pins 1136 pins = "sdc2_clk";
1145 bias- 1137 bias-disable;
1146 drive 1138 drive-strength = <2>;
1147 }; 1139 };
1148 1140
1149 cmd-pins { 1141 cmd-pins {
1150 pins 1142 pins = "sdc2_cmd";
1151 bias- 1143 bias-pull-up;
1152 drive 1144 drive-strength = <2>;
1153 }; 1145 };
1154 1146
1155 data-pins { 1147 data-pins {
1156 pins 1148 pins = "sdc2_data";
1157 bias- 1149 bias-pull-up;
1158 drive 1150 drive-strength = <2>;
1159 }; 1151 };
1160 }; 1152 };
1161 1153
1162 wcss_wlan_default: wc 1154 wcss_wlan_default: wcss-wlan-default-state {
1163 pins = "gpio4 1155 pins = "gpio40", "gpio41", "gpio42", "gpio43", "gpio44";
1164 function = "w 1156 function = "wcss_wlan";
1165 drive-strengt 1157 drive-strength = <6>;
1166 bias-pull-up; 1158 bias-pull-up;
1167 }; 1159 };
1168 }; 1160 };
1169 1161
1170 gcc: clock-controller@1800000 1162 gcc: clock-controller@1800000 {
1171 compatible = "qcom,gc 1163 compatible = "qcom,gcc-msm8939";
1172 reg = <0x01800000 0x8 1164 reg = <0x01800000 0x80000>;
1173 clocks = <&rpmcc RPM_ 1165 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
1174 <&sleep_clk> 1166 <&sleep_clk>,
1175 <&mdss_dsi0_ 1167 <&mdss_dsi0_phy 1>,
1176 <&mdss_dsi0_ 1168 <&mdss_dsi0_phy 0>,
1177 <0>, 1169 <0>,
1178 <0>, 1170 <0>,
1179 <0>; 1171 <0>;
1180 clock-names = "xo", 1172 clock-names = "xo",
1181 "sleep_ 1173 "sleep_clk",
1182 "dsi0pl 1174 "dsi0pll",
1183 "dsi0pl 1175 "dsi0pllbyte",
1184 "ext_mc 1176 "ext_mclk",
1185 "ext_pr 1177 "ext_pri_i2s",
1186 "ext_se 1178 "ext_sec_i2s";
1187 #clock-cells = <1>; 1179 #clock-cells = <1>;
1188 #reset-cells = <1>; 1180 #reset-cells = <1>;
1189 #power-domain-cells = 1181 #power-domain-cells = <1>;
1190 }; 1182 };
1191 1183
1192 tcsr_mutex: hwlock@1905000 { 1184 tcsr_mutex: hwlock@1905000 {
1193 compatible = "qcom,tc 1185 compatible = "qcom,tcsr-mutex";
1194 reg = <0x01905000 0x2 1186 reg = <0x01905000 0x20000>;
1195 #hwlock-cells = <1>; 1187 #hwlock-cells = <1>;
1196 }; 1188 };
1197 1189
1198 tcsr: syscon@1937000 { 1190 tcsr: syscon@1937000 {
1199 compatible = "qcom,tc 1191 compatible = "qcom,tcsr-msm8916", "syscon";
1200 reg = <0x01937000 0x3 1192 reg = <0x01937000 0x30000>;
1201 }; 1193 };
1202 1194
1203 mdss: display-subsystem@1a000 1195 mdss: display-subsystem@1a00000 {
1204 compatible = "qcom,md 1196 compatible = "qcom,mdss";
1205 reg = <0x01a00000 0x1 1197 reg = <0x01a00000 0x1000>,
1206 <0x01ac8000 0x3 1198 <0x01ac8000 0x3000>;
1207 reg-names = "mdss_phy 1199 reg-names = "mdss_phys", "vbif_phys";
1208 1200
1209 interrupts = <GIC_SPI 1201 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1210 interrupt-controller; 1202 interrupt-controller;
1211 1203
1212 clocks = <&gcc GCC_MD 1204 clocks = <&gcc GCC_MDSS_AHB_CLK>,
1213 <&gcc GCC_MD 1205 <&gcc GCC_MDSS_AXI_CLK>,
1214 <&gcc GCC_MD 1206 <&gcc GCC_MDSS_VSYNC_CLK>;
1215 clock-names = "iface" 1207 clock-names = "iface",
1216 "bus", 1208 "bus",
1217 "vsync" 1209 "vsync";
1218 1210
1219 power-domains = <&gcc 1211 power-domains = <&gcc MDSS_GDSC>;
1220 1212
1221 #address-cells = <1>; 1213 #address-cells = <1>;
1222 #size-cells = <1>; 1214 #size-cells = <1>;
1223 #interrupt-cells = <1 1215 #interrupt-cells = <1>;
1224 ranges; 1216 ranges;
1225 1217
1226 status = "disabled"; 1218 status = "disabled";
1227 1219
1228 mdss_mdp: display-con 1220 mdss_mdp: display-controller@1a01000 {
1229 compatible = 1221 compatible = "qcom,mdp5";
1230 reg = <0x01a0 1222 reg = <0x01a01000 0x89000>;
1231 reg-names = " 1223 reg-names = "mdp_phys";
1232 1224
1233 interrupt-par 1225 interrupt-parent = <&mdss>;
1234 interrupts = 1226 interrupts = <0>;
1235 1227
1236 clocks = <&gc 1228 clocks = <&gcc GCC_MDSS_AHB_CLK>,
1237 <&gc 1229 <&gcc GCC_MDSS_AXI_CLK>,
1238 <&gc 1230 <&gcc GCC_MDSS_MDP_CLK>,
1239 <&gc 1231 <&gcc GCC_MDSS_VSYNC_CLK>;
1240 clock-names = 1232 clock-names = "iface",
1241 1233 "bus",
1242 1234 "core",
1243 1235 "vsync";
1244 1236
1245 iommus = <&ap 1237 iommus = <&apps_iommu 4>;
1246 1238
1247 interconnects 1239 interconnects = <&snoc_mm MASTER_MDP_PORT0 &bimc SLAVE_EBI_CH0>,
1248 1240 <&snoc_mm MASTER_MDP_PORT1 &bimc SLAVE_EBI_CH0>;
1249 interconnect- 1241 interconnect-names = "mdp0-mem", "mdp1-mem";
1250 1242
1251 ports { 1243 ports {
1252 #addr 1244 #address-cells = <1>;
1253 #size 1245 #size-cells = <0>;
1254 1246
1255 port@ 1247 port@0 {
1256 1248 reg = <0>;
1257 1249 mdss_mdp_intf1_out: endpoint {
1258 1250 remote-endpoint = <&mdss_dsi0_in>;
1259 1251 };
1260 }; 1252 };
1261 1253
1262 port@ 1254 port@1 {
1263 1255 reg = <1>;
1264 1256 mdss_mdp_intf2_out: endpoint {
1265 1257 remote-endpoint = <&mdss_dsi1_in>;
1266 1258 };
1267 }; 1259 };
1268 }; 1260 };
1269 }; 1261 };
1270 1262
1271 mdss_dsi0: dsi@1a9800 1263 mdss_dsi0: dsi@1a98000 {
1272 compatible = 1264 compatible = "qcom,msm8916-dsi-ctrl",
1273 1265 "qcom,mdss-dsi-ctrl";
1274 reg = <0x01a9 1266 reg = <0x01a98000 0x25c>;
1275 reg-names = " 1267 reg-names = "dsi_ctrl";
1276 1268
1277 interrupt-par 1269 interrupt-parent = <&mdss>;
1278 interrupts = 1270 interrupts = <4>;
1279 1271
1280 clocks = <&gc 1272 clocks = <&gcc GCC_MDSS_MDP_CLK>,
1281 <&gc 1273 <&gcc GCC_MDSS_AHB_CLK>,
1282 <&gc 1274 <&gcc GCC_MDSS_AXI_CLK>,
1283 <&gc 1275 <&gcc GCC_MDSS_BYTE0_CLK>,
1284 <&gc 1276 <&gcc GCC_MDSS_PCLK0_CLK>,
1285 <&gc 1277 <&gcc GCC_MDSS_ESC0_CLK>;
1286 clock-names = 1278 clock-names = "mdp_core",
1287 1279 "iface",
1288 1280 "bus",
1289 1281 "byte",
1290 1282 "pixel",
1291 1283 "core";
1292 assigned-cloc 1284 assigned-clocks = <&gcc BYTE0_CLK_SRC>,
1293 1285 <&gcc PCLK0_CLK_SRC>;
1294 assigned-cloc 1286 assigned-clock-parents = <&mdss_dsi0_phy 0>,
1295 1287 <&mdss_dsi0_phy 1>;
1296 1288
1297 phys = <&mdss 1289 phys = <&mdss_dsi0_phy>;
1298 status = "dis 1290 status = "disabled";
1299 1291
1300 #address-cell 1292 #address-cells = <1>;
1301 #size-cells = 1293 #size-cells = <0>;
1302 1294
1303 ports { 1295 ports {
1304 #addr 1296 #address-cells = <1>;
1305 #size 1297 #size-cells = <0>;
1306 1298
1307 port@ 1299 port@0 {
1308 1300 reg = <0>;
1309 1301 mdss_dsi0_in: endpoint {
1310 1302 remote-endpoint = <&mdss_mdp_intf1_out>;
1311 1303 };
1312 }; 1304 };
1313 1305
1314 port@ 1306 port@1 {
1315 1307 reg = <1>;
1316 1308 mdss_dsi0_out: endpoint {
1317 1309 };
1318 }; 1310 };
1319 }; 1311 };
1320 }; 1312 };
1321 1313
1322 mdss_dsi0_phy: phy@1a 1314 mdss_dsi0_phy: phy@1a98300 {
1323 compatible = 1315 compatible = "qcom,dsi-phy-28nm-lp";
1324 reg = <0x01a9 1316 reg = <0x01a98300 0xd4>,
1325 <0x01a9 1317 <0x01a98500 0x280>,
1326 <0x01a9 1318 <0x01a98780 0x30>;
1327 reg-names = " 1319 reg-names = "dsi_pll",
1328 " 1320 "dsi_phy",
1329 " 1321 "dsi_phy_regulator";
1330 1322
1331 clocks = <&gc 1323 clocks = <&gcc GCC_MDSS_AHB_CLK>,
1332 <&rp 1324 <&rpmcc RPM_SMD_XO_CLK_SRC>;
1333 clock-names = 1325 clock-names = "iface", "ref";
1334 1326
1335 #clock-cells 1327 #clock-cells = <1>;
1336 #phy-cells = 1328 #phy-cells = <0>;
1337 status = "dis 1329 status = "disabled";
1338 }; 1330 };
1339 1331
1340 mdss_dsi1: dsi@1aa000 1332 mdss_dsi1: dsi@1aa0000 {
1341 compatible = 1333 compatible = "qcom,msm8916-dsi-ctrl",
1342 1334 "qcom,mdss-dsi-ctrl";
1343 reg = <0x01aa 1335 reg = <0x01aa0000 0x25c>;
1344 reg-names = " 1336 reg-names = "dsi_ctrl";
1345 1337
1346 interrupt-par 1338 interrupt-parent = <&mdss>;
1347 interrupts = 1339 interrupts = <5>;
1348 1340
1349 clocks = <&gc 1341 clocks = <&gcc GCC_MDSS_MDP_CLK>,
1350 <&gc 1342 <&gcc GCC_MDSS_AHB_CLK>,
1351 <&gc 1343 <&gcc GCC_MDSS_AXI_CLK>,
1352 <&gc 1344 <&gcc GCC_MDSS_BYTE1_CLK>,
1353 <&gc 1345 <&gcc GCC_MDSS_PCLK1_CLK>,
1354 <&gc 1346 <&gcc GCC_MDSS_ESC1_CLK>;
1355 clock-names = 1347 clock-names = "mdp_core",
1356 1348 "iface",
1357 1349 "bus",
1358 1350 "byte",
1359 1351 "pixel",
1360 1352 "core";
1361 assigned-cloc 1353 assigned-clocks = <&gcc BYTE1_CLK_SRC>,
1362 1354 <&gcc PCLK1_CLK_SRC>;
1363 assigned-cloc 1355 assigned-clock-parents = <&mdss_dsi0_phy 0>,
1364 1356 <&mdss_dsi0_phy 1>;
1365 phys = <&mdss 1357 phys = <&mdss_dsi1_phy>;
1366 status = "dis 1358 status = "disabled";
1367 1359
1368 ports { 1360 ports {
1369 #addr 1361 #address-cells = <1>;
1370 #size 1362 #size-cells = <0>;
1371 1363
1372 port@ 1364 port@0 {
1373 1365 reg = <0>;
1374 1366 mdss_dsi1_in: endpoint {
1375 1367 remote-endpoint = <&mdss_mdp_intf2_out>;
1376 1368 };
1377 }; 1369 };
1378 1370
1379 port@ 1371 port@1 {
1380 1372 reg = <1>;
1381 1373 mdss_dsi1_out: endpoint {
1382 1374 };
1383 }; 1375 };
1384 }; 1376 };
1385 }; 1377 };
1386 1378
1387 mdss_dsi1_phy: phy@1a 1379 mdss_dsi1_phy: phy@1aa0300 {
1388 compatible = 1380 compatible = "qcom,dsi-phy-28nm-lp";
1389 reg = <0x01aa 1381 reg = <0x01aa0300 0xd4>,
1390 <0x01aa 1382 <0x01aa0500 0x280>,
1391 <0x01aa 1383 <0x01aa0780 0x30>;
1392 reg-names = " 1384 reg-names = "dsi_pll",
1393 " 1385 "dsi_phy",
1394 " 1386 "dsi_phy_regulator";
1395 1387
1396 clocks = <&gc 1388 clocks = <&gcc GCC_MDSS_AHB_CLK>,
1397 <&rp 1389 <&rpmcc RPM_SMD_XO_CLK_SRC>;
1398 clock-names = 1390 clock-names = "iface", "ref";
1399 1391
1400 #clock-cells 1392 #clock-cells = <1>;
1401 #phy-cells = 1393 #phy-cells = <0>;
1402 status = "dis 1394 status = "disabled";
1403 }; 1395 };
1404 }; 1396 };
1405 1397
1406 gpu: gpu@1c00000 { !! 1398 gpu@1c00000 {
1407 compatible = "qcom,ad 1399 compatible = "qcom,adreno-405.0", "qcom,adreno";
1408 reg = <0x01c00000 0x1 1400 reg = <0x01c00000 0x10000>;
1409 reg-names = "kgsl_3d0 1401 reg-names = "kgsl_3d0_reg_memory";
1410 interrupts = <GIC_SPI 1402 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
1411 interrupt-names = "kg 1403 interrupt-names = "kgsl_3d0_irq";
1412 clock-names = "core", 1404 clock-names = "core",
1413 "iface" 1405 "iface",
1414 "mem", 1406 "mem",
1415 "mem_if 1407 "mem_iface",
1416 "alt_me 1408 "alt_mem_iface",
1417 "gfx3d" 1409 "gfx3d",
1418 "rbbmti 1410 "rbbmtimer";
1419 clocks = <&gcc GCC_OX 1411 clocks = <&gcc GCC_OXILI_GFX3D_CLK>,
1420 <&gcc GCC_OX 1412 <&gcc GCC_OXILI_AHB_CLK>,
1421 <&gcc GCC_OX 1413 <&gcc GCC_OXILI_GMEM_CLK>,
1422 <&gcc GCC_BI 1414 <&gcc GCC_BIMC_GFX_CLK>,
1423 <&gcc GCC_BI 1415 <&gcc GCC_BIMC_GPU_CLK>,
1424 <&gcc GFX3D_ 1416 <&gcc GFX3D_CLK_SRC>,
1425 <&gcc GCC_OX 1417 <&gcc GCC_OXILI_TIMER_CLK>;
1426 power-domains = <&gcc 1418 power-domains = <&gcc OXILI_GDSC>;
1427 operating-points-v2 = 1419 operating-points-v2 = <&opp_table>;
1428 iommus = <&gpu_iommu 1420 iommus = <&gpu_iommu 1>, <&gpu_iommu 2>;
1429 #cooling-cells = <2>; <<
1430 <<
1431 status = "disabled"; <<
1432 1421
1433 opp_table: opp-table 1422 opp_table: opp-table {
1434 compatible = 1423 compatible = "operating-points-v2";
1435 1424
1436 opp-550000000 1425 opp-550000000 {
1437 opp-h 1426 opp-hz = /bits/ 64 <550000000>;
1438 }; 1427 };
1439 1428
1440 opp-465000000 1429 opp-465000000 {
1441 opp-h 1430 opp-hz = /bits/ 64 <465000000>;
1442 }; 1431 };
1443 1432
1444 opp-400000000 1433 opp-400000000 {
1445 opp-h 1434 opp-hz = /bits/ 64 <400000000>;
1446 }; 1435 };
1447 1436
1448 opp-220000000 1437 opp-220000000 {
1449 opp-h 1438 opp-hz = /bits/ 64 <220000000>;
1450 }; 1439 };
1451 1440
1452 opp-19200000 1441 opp-19200000 {
1453 opp-h 1442 opp-hz = /bits/ 64 <19200000>;
1454 }; 1443 };
1455 }; 1444 };
1456 }; 1445 };
1457 1446
1458 apps_iommu: iommu@1ef0000 { 1447 apps_iommu: iommu@1ef0000 {
1459 compatible = "qcom,ms 1448 compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
1460 reg = <0x01ef0000 0x3 1449 reg = <0x01ef0000 0x3000>;
1461 ranges = <0 0x01e2000 1450 ranges = <0 0x01e20000 0x20000>;
1462 clocks = <&gcc GCC_SM 1451 clocks = <&gcc GCC_SMMU_CFG_CLK>,
1463 <&gcc GCC_AP 1452 <&gcc GCC_APSS_TCU_CLK>;
1464 clock-names = "iface" 1453 clock-names = "iface", "bus";
1465 #address-cells = <1>; 1454 #address-cells = <1>;
1466 #size-cells = <1>; 1455 #size-cells = <1>;
1467 #iommu-cells = <1>; 1456 #iommu-cells = <1>;
1468 qcom,iommu-secure-id 1457 qcom,iommu-secure-id = <17>;
1469 1458
1470 /* mdp_0: */ 1459 /* mdp_0: */
1471 iommu-ctx@4000 { 1460 iommu-ctx@4000 {
1472 compatible = 1461 compatible = "qcom,msm-iommu-v1-ns";
1473 reg = <0x4000 1462 reg = <0x4000 0x1000>;
1474 interrupts = 1463 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
1475 }; 1464 };
1476 1465
1477 /* venus_ns: */ 1466 /* venus_ns: */
1478 iommu-ctx@5000 { 1467 iommu-ctx@5000 {
1479 compatible = 1468 compatible = "qcom,msm-iommu-v1-sec";
1480 reg = <0x5000 1469 reg = <0x5000 0x1000>;
1481 interrupts = 1470 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
1482 }; 1471 };
1483 }; 1472 };
1484 1473
1485 gpu_iommu: iommu@1f08000 { 1474 gpu_iommu: iommu@1f08000 {
1486 compatible = "qcom,ms 1475 compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
1487 ranges = <0 0x1f08000 1476 ranges = <0 0x1f08000 0x10000>;
1488 clocks = <&gcc GCC_SM 1477 clocks = <&gcc GCC_SMMU_CFG_CLK>,
1489 <&gcc GCC_GF 1478 <&gcc GCC_GFX_TCU_CLK>,
1490 <&gcc GCC_GF 1479 <&gcc GCC_GFX_TBU_CLK>;
1491 clock-names = "iface" 1480 clock-names = "iface", "bus", "tbu";
1492 #address-cells = <1>; 1481 #address-cells = <1>;
1493 #size-cells = <1>; 1482 #size-cells = <1>;
1494 #iommu-cells = <1>; 1483 #iommu-cells = <1>;
1495 qcom,iommu-secure-id 1484 qcom,iommu-secure-id = <18>;
1496 1485
1497 /* gfx3d_user: */ 1486 /* gfx3d_user: */
1498 iommu-ctx@1000 { 1487 iommu-ctx@1000 {
1499 compatible = 1488 compatible = "qcom,msm-iommu-v1-ns";
1500 reg = <0x1000 1489 reg = <0x1000 0x1000>;
1501 interrupts = 1490 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
1502 }; 1491 };
1503 1492
1504 /* gfx3d_priv: */ 1493 /* gfx3d_priv: */
1505 iommu-ctx@2000 { 1494 iommu-ctx@2000 {
1506 compatible = 1495 compatible = "qcom,msm-iommu-v1-ns";
1507 reg = <0x2000 1496 reg = <0x2000 0x1000>;
1508 interrupts = 1497 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
1509 }; 1498 };
1510 }; 1499 };
1511 1500
1512 spmi_bus: spmi@200f000 { 1501 spmi_bus: spmi@200f000 {
1513 compatible = "qcom,sp 1502 compatible = "qcom,spmi-pmic-arb";
1514 reg = <0x0200f000 0x0 1503 reg = <0x0200f000 0x001000>,
1515 <0x02400000 0x4 1504 <0x02400000 0x400000>,
1516 <0x02c00000 0x4 1505 <0x02c00000 0x400000>,
1517 <0x03800000 0x2 1506 <0x03800000 0x200000>,
1518 <0x0200a000 0x0 1507 <0x0200a000 0x002100>;
1519 reg-names = "core", " 1508 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1520 interrupt-names = "pe 1509 interrupt-names = "periph_irq";
1521 interrupts = <GIC_SPI 1510 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
1522 qcom,ee = <0>; 1511 qcom,ee = <0>;
1523 qcom,channel = <0>; 1512 qcom,channel = <0>;
1524 #address-cells = <2>; 1513 #address-cells = <2>;
1525 #size-cells = <0>; 1514 #size-cells = <0>;
1526 interrupt-controller; 1515 interrupt-controller;
1527 #interrupt-cells = <4 1516 #interrupt-cells = <4>;
1528 }; 1517 };
1529 1518
1530 bam_dmux_dma: dma-controller@ <<
1531 compatible = "qcom,ba <<
1532 reg = <0x04044000 0x1 <<
1533 interrupts = <GIC_SPI <<
1534 #dma-cells = <1>; <<
1535 qcom,ee = <0>; <<
1536 <<
1537 num-channels = <6>; <<
1538 qcom,num-ees = <1>; <<
1539 qcom,powered-remotely <<
1540 <<
1541 status = "disabled"; <<
1542 }; <<
1543 <<
1544 mpss: remoteproc@4080000 { 1519 mpss: remoteproc@4080000 {
1545 compatible = "qcom,ms 1520 compatible = "qcom,msm8916-mss-pil";
1546 reg = <0x04080000 0x1 1521 reg = <0x04080000 0x100>, <0x04020000 0x040>;
1547 reg-names = "qdsp6", 1522 reg-names = "qdsp6", "rmb";
1548 interrupts-extended = 1523 interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>,
1549 1524 <&hexagon_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1550 1525 <&hexagon_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1551 1526 <&hexagon_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1552 1527 <&hexagon_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1553 interrupt-names = "wd 1528 interrupt-names = "wdog",
1554 "fa 1529 "fatal",
1555 "re 1530 "ready",
1556 "ha 1531 "handover",
1557 "st 1532 "stop-ack";
1558 clocks = <&gcc GCC_MS 1533 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
1559 <&gcc GCC_MS 1534 <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>,
1560 <&gcc GCC_BO 1535 <&gcc GCC_BOOT_ROM_AHB_CLK>,
1561 <&rpmcc RPM_ 1536 <&rpmcc RPM_SMD_XO_CLK_SRC>;
1562 clock-names = "iface" 1537 clock-names = "iface",
1563 "bus", 1538 "bus",
1564 "mem", 1539 "mem",
1565 "xo"; 1540 "xo";
1566 power-domains = <&rpm 1541 power-domains = <&rpmpd MSM8939_VDDMDCX>,
1567 <&rpm 1542 <&rpmpd MSM8939_VDDMX>;
1568 power-domain-names = 1543 power-domain-names = "cx", "mx";
1569 qcom,smem-states = <& 1544 qcom,smem-states = <&hexagon_smp2p_out 0>;
1570 qcom,smem-state-names 1545 qcom,smem-state-names = "stop";
1571 resets = <&scm 0>; 1546 resets = <&scm 0>;
1572 reset-names = "mss_re 1547 reset-names = "mss_restart";
1573 qcom,halt-regs = <&tc 1548 qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>;
1574 status = "disabled"; 1549 status = "disabled";
1575 1550
1576 bam_dmux: bam-dmux { <<
1577 compatible = <<
1578 <<
1579 interrupt-par <<
1580 interrupts = <<
1581 interrupt-nam <<
1582 <<
1583 qcom,smem-sta <<
1584 qcom,smem-sta <<
1585 <<
1586 dmas = <&bam_ <<
1587 dma-names = " <<
1588 <<
1589 status = "dis <<
1590 }; <<
1591 <<
1592 mba { 1551 mba {
1593 memory-region 1552 memory-region = <&mba_mem>;
1594 }; 1553 };
1595 1554
1596 mpss { 1555 mpss {
1597 memory-region 1556 memory-region = <&mpss_mem>;
1598 }; 1557 };
1599 1558
1600 smd-edge { 1559 smd-edge {
1601 interrupts = 1560 interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>;
1602 1561
1603 qcom,smd-edge 1562 qcom,smd-edge = <0>;
1604 mboxes = <&ap 1563 mboxes = <&apcs1_mbox 12>;
1605 qcom,remote-p 1564 qcom,remote-pid = <1>;
1606 1565
1607 label = "hexa 1566 label = "hexagon";
1608 <<
1609 apr: apr { <<
1610 compa <<
1611 qcom, <<
1612 qcom, <<
1613 #addr <<
1614 #size <<
1615 statu <<
1616 <<
1617 q6cor <<
1618 <<
1619 <<
1620 }; <<
1621 <<
1622 q6afe <<
1623 <<
1624 <<
1625 <<
1626 <<
1627 <<
1628 <<
1629 <<
1630 <<
1631 <<
1632 }; <<
1633 <<
1634 q6asm <<
1635 <<
1636 <<
1637 <<
1638 <<
1639 <<
1640 <<
1641 <<
1642 <<
1643 <<
1644 }; <<
1645 <<
1646 q6adm <<
1647 <<
1648 <<
1649 <<
1650 <<
1651 <<
1652 <<
1653 <<
1654 }; <<
1655 }; <<
1656 }; 1567 };
1657 }; 1568 };
1658 1569
1659 sound: sound@7702000 { 1570 sound: sound@7702000 {
1660 compatible = "qcom,ap 1571 compatible = "qcom,apq8016-sbc-sndcard";
1661 reg = <0x07702000 0x4 1572 reg = <0x07702000 0x4>,
1662 <0x07702004 0x4 1573 <0x07702004 0x4>;
1663 reg-names = "mic-iomu 1574 reg-names = "mic-iomux", "spkr-iomux";
1664 status = "disabled"; 1575 status = "disabled";
1665 }; 1576 };
1666 1577
1667 lpass: audio-controller@77080 1578 lpass: audio-controller@7708000 {
1668 compatible = "qcom,ap 1579 compatible = "qcom,apq8016-lpass-cpu";
1669 reg = <0x07708000 0x1 1580 reg = <0x07708000 0x10000>;
1670 reg-names = "lpass-lp 1581 reg-names = "lpass-lpaif";
1671 interrupts = <GIC_SPI 1582 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
1672 interrupt-names = "lp 1583 interrupt-names = "lpass-irq-lpaif";
1673 clocks = <&gcc GCC_UL 1584 clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
1674 <&gcc GCC_UL 1585 <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>,
1675 <&gcc GCC_UL 1586 <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>,
1676 <&gcc GCC_UL 1587 <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>,
1677 <&gcc GCC_UL 1588 <&gcc GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK>,
1678 <&gcc GCC_UL 1589 <&gcc GCC_ULTAUDIO_PCNOC_MPORT_CLK>,
1679 <&gcc GCC_UL 1590 <&gcc GCC_ULTAUDIO_PCNOC_SWAY_CLK>;
1680 clock-names = "ahbix- 1591 clock-names = "ahbix-clk",
1681 "mi2s-b 1592 "mi2s-bit-clk0",
1682 "mi2s-b 1593 "mi2s-bit-clk1",
1683 "mi2s-b 1594 "mi2s-bit-clk2",
1684 "mi2s-b 1595 "mi2s-bit-clk3",
1685 "pcnoc- 1596 "pcnoc-mport-clk",
1686 "pcnoc- 1597 "pcnoc-sway-clk";
1687 #sound-dai-cells = <1 1598 #sound-dai-cells = <1>;
1688 #address-cells = <1>; 1599 #address-cells = <1>;
1689 #size-cells = <0>; 1600 #size-cells = <0>;
1690 status = "disabled"; 1601 status = "disabled";
1691 }; 1602 };
1692 1603
1693 lpass_codec: audio-codec@771c 1604 lpass_codec: audio-codec@771c000 {
1694 compatible = "qcom,ms 1605 compatible = "qcom,msm8916-wcd-digital-codec";
1695 reg = <0x0771c000 0x4 1606 reg = <0x0771c000 0x400>;
1696 clocks = <&gcc GCC_UL 1607 clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
1697 <&gcc GCC_CO 1608 <&gcc GCC_CODEC_DIGCODEC_CLK>;
1698 clock-names = "ahbix- 1609 clock-names = "ahbix-clk", "mclk";
1699 #sound-dai-cells = <1 1610 #sound-dai-cells = <1>;
1700 status = "disabled"; 1611 status = "disabled";
1701 }; 1612 };
1702 1613
1703 sdhc_1: mmc@7824900 { 1614 sdhc_1: mmc@7824900 {
1704 compatible = "qcom,ms 1615 compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4";
1705 reg = <0x07824900 0x1 1616 reg = <0x07824900 0x11c>, <0x07824000 0x800>;
1706 reg-names = "hc", "co 1617 reg-names = "hc", "core";
1707 1618
1708 interrupts = <GIC_SPI 1619 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1709 <GIC_SPI 1620 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
1710 interrupt-names = "hc 1621 interrupt-names = "hc_irq", "pwr_irq";
1711 clocks = <&gcc GCC_SD 1622 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
1712 <&gcc GCC_SD 1623 <&gcc GCC_SDCC1_APPS_CLK>,
1713 <&rpmcc RPM_ 1624 <&rpmcc RPM_SMD_XO_CLK_SRC>;
1714 clock-names = "iface" 1625 clock-names = "iface", "core", "xo";
1715 resets = <&gcc GCC_SD 1626 resets = <&gcc GCC_SDCC1_BCR>;
1716 pinctrl-0 = <&sdc1_de 1627 pinctrl-0 = <&sdc1_default>;
1717 pinctrl-1 = <&sdc1_sl 1628 pinctrl-1 = <&sdc1_sleep>;
1718 pinctrl-names = "defa 1629 pinctrl-names = "default", "sleep";
1719 mmc-ddr-1_8v; 1630 mmc-ddr-1_8v;
1720 bus-width = <8>; 1631 bus-width = <8>;
1721 non-removable; 1632 non-removable;
1722 status = "disabled"; 1633 status = "disabled";
1723 }; 1634 };
1724 1635
1725 sdhc_2: mmc@7864900 { 1636 sdhc_2: mmc@7864900 {
1726 compatible = "qcom,ms 1637 compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4";
1727 reg = <0x07864900 0x1 1638 reg = <0x07864900 0x11c>, <0x07864000 0x800>;
1728 reg-names = "hc", "co 1639 reg-names = "hc", "core";
1729 1640
1730 interrupts = <GIC_SPI 1641 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1731 <GIC_SPI 1642 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
1732 interrupt-names = "hc 1643 interrupt-names = "hc_irq", "pwr_irq";
1733 clocks = <&gcc GCC_SD 1644 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
1734 <&gcc GCC_SD 1645 <&gcc GCC_SDCC2_APPS_CLK>,
1735 <&rpmcc RPM_ 1646 <&rpmcc RPM_SMD_XO_CLK_SRC>;
1736 clock-names = "iface" 1647 clock-names = "iface", "core", "xo";
1737 resets = <&gcc GCC_SD 1648 resets = <&gcc GCC_SDCC2_BCR>;
1738 pinctrl-0 = <&sdc2_de 1649 pinctrl-0 = <&sdc2_default>;
1739 pinctrl-1 = <&sdc2_sl 1650 pinctrl-1 = <&sdc2_sleep>;
1740 pinctrl-names = "defa 1651 pinctrl-names = "default", "sleep";
1741 bus-width = <4>; 1652 bus-width = <4>;
1742 status = "disabled"; 1653 status = "disabled";
1743 }; 1654 };
1744 1655
1745 blsp_dma: dma-controller@7884 1656 blsp_dma: dma-controller@7884000 {
1746 compatible = "qcom,ba 1657 compatible = "qcom,bam-v1.7.0";
1747 reg = <0x07884000 0x2 1658 reg = <0x07884000 0x23000>;
1748 interrupts = <GIC_SPI 1659 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
1749 clocks = <&gcc GCC_BL 1660 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
1750 clock-names = "bam_cl 1661 clock-names = "bam_clk";
1751 #dma-cells = <1>; 1662 #dma-cells = <1>;
1752 qcom,ee = <0>; 1663 qcom,ee = <0>;
1753 qcom,controlled-remot 1664 qcom,controlled-remotely;
1754 }; 1665 };
1755 1666
1756 blsp_uart1: serial@78af000 { 1667 blsp_uart1: serial@78af000 {
1757 compatible = "qcom,ms 1668 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1758 reg = <0x078af000 0x2 1669 reg = <0x078af000 0x200>;
1759 interrupts = <GIC_SPI 1670 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1760 clocks = <&gcc GCC_BL 1671 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
1761 clock-names = "core", 1672 clock-names = "core", "iface";
1762 dmas = <&blsp_dma 0>, 1673 dmas = <&blsp_dma 0>, <&blsp_dma 1>;
1763 dma-names = "tx", "rx 1674 dma-names = "tx", "rx";
1764 pinctrl-0 = <&blsp_ua 1675 pinctrl-0 = <&blsp_uart1_default>;
1765 pinctrl-1 = <&blsp_ua 1676 pinctrl-1 = <&blsp_uart1_sleep>;
1766 pinctrl-names = "defa 1677 pinctrl-names = "default", "sleep";
1767 status = "disabled"; 1678 status = "disabled";
1768 }; 1679 };
1769 1680
1770 blsp_uart2: serial@78b0000 { 1681 blsp_uart2: serial@78b0000 {
1771 compatible = "qcom,ms 1682 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1772 reg = <0x078b0000 0x2 1683 reg = <0x078b0000 0x200>;
1773 interrupts = <GIC_SPI 1684 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1774 clocks = <&gcc GCC_BL 1685 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
1775 clock-names = "core", 1686 clock-names = "core", "iface";
1776 dmas = <&blsp_dma 2>, 1687 dmas = <&blsp_dma 2>, <&blsp_dma 3>;
1777 dma-names = "tx", "rx 1688 dma-names = "tx", "rx";
1778 pinctrl-0 = <&blsp_ua 1689 pinctrl-0 = <&blsp_uart2_default>;
1779 pinctrl-1 = <&blsp_ua 1690 pinctrl-1 = <&blsp_uart2_sleep>;
1780 pinctrl-names = "defa 1691 pinctrl-names = "default", "sleep";
1781 status = "disabled"; 1692 status = "disabled";
1782 }; 1693 };
1783 1694
1784 blsp_i2c1: i2c@78b5000 { 1695 blsp_i2c1: i2c@78b5000 {
1785 compatible = "qcom,i2 1696 compatible = "qcom,i2c-qup-v2.2.1";
1786 reg = <0x078b5000 0x5 1697 reg = <0x078b5000 0x500>;
1787 interrupts = <GIC_SPI 1698 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
1788 clocks = <&gcc GCC_BL 1699 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
1789 <&gcc GCC_BL 1700 <&gcc GCC_BLSP1_AHB_CLK>;
1790 clock-names = "core", 1701 clock-names = "core", "iface";
1791 dmas = <&blsp_dma 4>, 1702 dmas = <&blsp_dma 4>, <&blsp_dma 5>;
1792 dma-names = "tx", "rx 1703 dma-names = "tx", "rx";
1793 pinctrl-0 = <&blsp_i2 1704 pinctrl-0 = <&blsp_i2c1_default>;
1794 pinctrl-1 = <&blsp_i2 1705 pinctrl-1 = <&blsp_i2c1_sleep>;
1795 pinctrl-names = "defa 1706 pinctrl-names = "default", "sleep";
1796 #address-cells = <1>; 1707 #address-cells = <1>;
1797 #size-cells = <0>; 1708 #size-cells = <0>;
1798 status = "disabled"; 1709 status = "disabled";
1799 }; 1710 };
1800 1711
1801 blsp_spi1: spi@78b5000 { 1712 blsp_spi1: spi@78b5000 {
1802 compatible = "qcom,sp 1713 compatible = "qcom,spi-qup-v2.2.1";
1803 reg = <0x078b5000 0x5 1714 reg = <0x078b5000 0x500>;
1804 interrupts = <GIC_SPI 1715 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
1805 clocks = <&gcc GCC_BL 1716 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
1806 <&gcc GCC_BL 1717 <&gcc GCC_BLSP1_AHB_CLK>;
1807 clock-names = "core", 1718 clock-names = "core", "iface";
1808 dmas = <&blsp_dma 4>, 1719 dmas = <&blsp_dma 4>, <&blsp_dma 5>;
1809 dma-names = "tx", "rx 1720 dma-names = "tx", "rx";
1810 pinctrl-0 = <&blsp_sp 1721 pinctrl-0 = <&blsp_spi1_default>;
1811 pinctrl-1 = <&blsp_sp 1722 pinctrl-1 = <&blsp_spi1_sleep>;
1812 pinctrl-names = "defa 1723 pinctrl-names = "default", "sleep";
1813 #address-cells = <1>; 1724 #address-cells = <1>;
1814 #size-cells = <0>; 1725 #size-cells = <0>;
1815 status = "disabled"; 1726 status = "disabled";
1816 }; 1727 };
1817 1728
1818 blsp_i2c2: i2c@78b6000 { 1729 blsp_i2c2: i2c@78b6000 {
1819 compatible = "qcom,i2 1730 compatible = "qcom,i2c-qup-v2.2.1";
1820 reg = <0x078b6000 0x5 1731 reg = <0x078b6000 0x500>;
1821 interrupts = <GIC_SPI 1732 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1822 clocks = <&gcc GCC_BL 1733 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
1823 <&gcc GCC_BL 1734 <&gcc GCC_BLSP1_AHB_CLK>;
1824 clock-names = "core", 1735 clock-names = "core", "iface";
1825 dmas = <&blsp_dma 6>, 1736 dmas = <&blsp_dma 6>, <&blsp_dma 7>;
1826 dma-names = "tx", "rx 1737 dma-names = "tx", "rx";
1827 pinctrl-0 = <&blsp_i2 1738 pinctrl-0 = <&blsp_i2c2_default>;
1828 pinctrl-1 = <&blsp_i2 1739 pinctrl-1 = <&blsp_i2c2_sleep>;
1829 pinctrl-names = "defa 1740 pinctrl-names = "default", "sleep";
1830 #address-cells = <1>; 1741 #address-cells = <1>;
1831 #size-cells = <0>; 1742 #size-cells = <0>;
1832 status = "disabled"; 1743 status = "disabled";
1833 }; 1744 };
1834 1745
1835 blsp_spi2: spi@78b6000 { 1746 blsp_spi2: spi@78b6000 {
1836 compatible = "qcom,sp 1747 compatible = "qcom,spi-qup-v2.2.1";
1837 reg = <0x078b6000 0x5 1748 reg = <0x078b6000 0x500>;
1838 interrupts = <GIC_SPI 1749 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1839 clocks = <&gcc GCC_BL 1750 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
1840 <&gcc GCC_BL 1751 <&gcc GCC_BLSP1_AHB_CLK>;
1841 clock-names = "core", 1752 clock-names = "core", "iface";
1842 dmas = <&blsp_dma 6>, 1753 dmas = <&blsp_dma 6>, <&blsp_dma 7>;
1843 dma-names = "tx", "rx 1754 dma-names = "tx", "rx";
1844 pinctrl-0 = <&blsp_sp 1755 pinctrl-0 = <&blsp_spi2_default>;
1845 pinctrl-1 = <&blsp_sp 1756 pinctrl-1 = <&blsp_spi2_sleep>;
1846 pinctrl-names = "defa 1757 pinctrl-names = "default", "sleep";
1847 #address-cells = <1>; 1758 #address-cells = <1>;
1848 #size-cells = <0>; 1759 #size-cells = <0>;
1849 status = "disabled"; 1760 status = "disabled";
1850 }; 1761 };
1851 1762
1852 blsp_i2c3: i2c@78b7000 { 1763 blsp_i2c3: i2c@78b7000 {
1853 compatible = "qcom,i2 1764 compatible = "qcom,i2c-qup-v2.2.1";
1854 reg = <0x078b7000 0x5 1765 reg = <0x078b7000 0x500>;
1855 interrupts = <GIC_SPI 1766 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1856 clocks = <&gcc GCC_BL 1767 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
1857 <&gcc GCC_BL 1768 <&gcc GCC_BLSP1_AHB_CLK>;
1858 clock-names = "core", 1769 clock-names = "core", "iface";
1859 dmas = <&blsp_dma 8>, 1770 dmas = <&blsp_dma 8>, <&blsp_dma 9>;
1860 dma-names = "tx", "rx 1771 dma-names = "tx", "rx";
1861 pinctrl-0 = <&blsp_i2 1772 pinctrl-0 = <&blsp_i2c3_default>;
1862 pinctrl-1 = <&blsp_i2 1773 pinctrl-1 = <&blsp_i2c3_sleep>;
1863 pinctrl-names = "defa 1774 pinctrl-names = "default", "sleep";
1864 #address-cells = <1>; 1775 #address-cells = <1>;
1865 #size-cells = <0>; 1776 #size-cells = <0>;
1866 status = "disabled"; 1777 status = "disabled";
1867 }; 1778 };
1868 1779
1869 blsp_spi3: spi@78b7000 { 1780 blsp_spi3: spi@78b7000 {
1870 compatible = "qcom,sp 1781 compatible = "qcom,spi-qup-v2.2.1";
1871 reg = <0x078b7000 0x5 1782 reg = <0x078b7000 0x500>;
1872 interrupts = <GIC_SPI 1783 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1873 clocks = <&gcc GCC_BL 1784 clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
1874 <&gcc GCC_BL 1785 <&gcc GCC_BLSP1_AHB_CLK>;
1875 clock-names = "core", 1786 clock-names = "core", "iface";
1876 dmas = <&blsp_dma 8>, 1787 dmas = <&blsp_dma 8>, <&blsp_dma 9>;
1877 dma-names = "tx", "rx 1788 dma-names = "tx", "rx";
1878 pinctrl-0 = <&blsp_sp 1789 pinctrl-0 = <&blsp_spi3_default>;
1879 pinctrl-1 = <&blsp_sp 1790 pinctrl-1 = <&blsp_spi3_sleep>;
1880 pinctrl-names = "defa 1791 pinctrl-names = "default", "sleep";
1881 #address-cells = <1>; 1792 #address-cells = <1>;
1882 #size-cells = <0>; 1793 #size-cells = <0>;
1883 status = "disabled"; 1794 status = "disabled";
1884 }; 1795 };
1885 1796
1886 blsp_i2c4: i2c@78b8000 { 1797 blsp_i2c4: i2c@78b8000 {
1887 compatible = "qcom,i2 1798 compatible = "qcom,i2c-qup-v2.2.1";
1888 reg = <0x078b8000 0x5 1799 reg = <0x078b8000 0x500>;
1889 interrupts = <GIC_SPI 1800 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1890 clocks = <&gcc GCC_BL 1801 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
1891 <&gcc GCC_BL 1802 <&gcc GCC_BLSP1_AHB_CLK>;
1892 clock-names = "core", 1803 clock-names = "core", "iface";
1893 dmas = <&blsp_dma 10> 1804 dmas = <&blsp_dma 10>, <&blsp_dma 11>;
1894 dma-names = "tx", "rx 1805 dma-names = "tx", "rx";
1895 pinctrl-0 = <&blsp_i2 1806 pinctrl-0 = <&blsp_i2c4_default>;
1896 pinctrl-1 = <&blsp_i2 1807 pinctrl-1 = <&blsp_i2c4_sleep>;
1897 pinctrl-names = "defa 1808 pinctrl-names = "default", "sleep";
1898 #address-cells = <1>; 1809 #address-cells = <1>;
1899 #size-cells = <0>; 1810 #size-cells = <0>;
1900 status = "disabled"; 1811 status = "disabled";
1901 }; 1812 };
1902 1813
1903 blsp_spi4: spi@78b8000 { 1814 blsp_spi4: spi@78b8000 {
1904 compatible = "qcom,sp 1815 compatible = "qcom,spi-qup-v2.2.1";
1905 reg = <0x078b8000 0x5 1816 reg = <0x078b8000 0x500>;
1906 interrupts = <GIC_SPI 1817 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1907 clocks = <&gcc GCC_BL 1818 clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
1908 <&gcc GCC_BL 1819 <&gcc GCC_BLSP1_AHB_CLK>;
1909 clock-names = "core", 1820 clock-names = "core", "iface";
1910 dmas = <&blsp_dma 10> 1821 dmas = <&blsp_dma 10>, <&blsp_dma 11>;
1911 dma-names = "tx", "rx 1822 dma-names = "tx", "rx";
1912 pinctrl-0 = <&blsp_sp 1823 pinctrl-0 = <&blsp_spi4_default>;
1913 pinctrl-1 = <&blsp_sp 1824 pinctrl-1 = <&blsp_spi4_sleep>;
1914 pinctrl-names = "defa 1825 pinctrl-names = "default", "sleep";
1915 #address-cells = <1>; 1826 #address-cells = <1>;
1916 #size-cells = <0>; 1827 #size-cells = <0>;
1917 status = "disabled"; 1828 status = "disabled";
1918 }; 1829 };
1919 1830
1920 blsp_i2c5: i2c@78b9000 { 1831 blsp_i2c5: i2c@78b9000 {
1921 compatible = "qcom,i2 1832 compatible = "qcom,i2c-qup-v2.2.1";
1922 reg = <0x078b9000 0x5 1833 reg = <0x078b9000 0x500>;
1923 interrupts = <GIC_SPI 1834 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
1924 clocks = <&gcc GCC_BL 1835 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
1925 <&gcc GCC_BL 1836 <&gcc GCC_BLSP1_AHB_CLK>;
1926 clock-names = "core", 1837 clock-names = "core", "iface";
1927 dmas = <&blsp_dma 12> 1838 dmas = <&blsp_dma 12>, <&blsp_dma 13>;
1928 dma-names = "tx", "rx 1839 dma-names = "tx", "rx";
1929 pinctrl-0 = <&blsp_i2 1840 pinctrl-0 = <&blsp_i2c5_default>;
1930 pinctrl-1 = <&blsp_i2 1841 pinctrl-1 = <&blsp_i2c5_sleep>;
1931 pinctrl-names = "defa 1842 pinctrl-names = "default", "sleep";
1932 #address-cells = <1>; 1843 #address-cells = <1>;
1933 #size-cells = <0>; 1844 #size-cells = <0>;
1934 status = "disabled"; 1845 status = "disabled";
1935 }; 1846 };
1936 1847
1937 blsp_spi5: spi@78b9000 { 1848 blsp_spi5: spi@78b9000 {
1938 compatible = "qcom,sp 1849 compatible = "qcom,spi-qup-v2.2.1";
1939 reg = <0x078b9000 0x5 1850 reg = <0x078b9000 0x500>;
1940 interrupts = <GIC_SPI 1851 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
1941 clocks = <&gcc GCC_BL 1852 clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
1942 <&gcc GCC_BL 1853 <&gcc GCC_BLSP1_AHB_CLK>;
1943 clock-names = "core", 1854 clock-names = "core", "iface";
1944 dmas = <&blsp_dma 12> 1855 dmas = <&blsp_dma 12>, <&blsp_dma 13>;
1945 dma-names = "tx", "rx 1856 dma-names = "tx", "rx";
1946 pinctrl-0 = <&blsp_sp 1857 pinctrl-0 = <&blsp_spi5_default>;
1947 pinctrl-1 = <&blsp_sp 1858 pinctrl-1 = <&blsp_spi5_sleep>;
1948 pinctrl-names = "defa 1859 pinctrl-names = "default", "sleep";
1949 #address-cells = <1>; 1860 #address-cells = <1>;
1950 #size-cells = <0>; 1861 #size-cells = <0>;
1951 status = "disabled"; 1862 status = "disabled";
1952 }; 1863 };
1953 1864
1954 blsp_i2c6: i2c@78ba000 { 1865 blsp_i2c6: i2c@78ba000 {
1955 compatible = "qcom,i2 1866 compatible = "qcom,i2c-qup-v2.2.1";
1956 reg = <0x078ba000 0x5 1867 reg = <0x078ba000 0x500>;
1957 interrupts = <GIC_SPI 1868 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
1958 clocks = <&gcc GCC_BL 1869 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
1959 <&gcc GCC_BL 1870 <&gcc GCC_BLSP1_AHB_CLK>;
1960 clock-names = "core", 1871 clock-names = "core", "iface";
1961 dmas = <&blsp_dma 14> 1872 dmas = <&blsp_dma 14>, <&blsp_dma 15>;
1962 dma-names = "tx", "rx 1873 dma-names = "tx", "rx";
1963 pinctrl-0 = <&blsp_i2 1874 pinctrl-0 = <&blsp_i2c6_default>;
1964 pinctrl-1 = <&blsp_i2 1875 pinctrl-1 = <&blsp_i2c6_sleep>;
1965 pinctrl-names = "defa 1876 pinctrl-names = "default", "sleep";
1966 #address-cells = <1>; 1877 #address-cells = <1>;
1967 #size-cells = <0>; 1878 #size-cells = <0>;
1968 status = "disabled"; 1879 status = "disabled";
1969 }; 1880 };
1970 1881
1971 blsp_spi6: spi@78ba000 { 1882 blsp_spi6: spi@78ba000 {
1972 compatible = "qcom,sp 1883 compatible = "qcom,spi-qup-v2.2.1";
1973 reg = <0x078ba000 0x5 1884 reg = <0x078ba000 0x500>;
1974 interrupts = <GIC_SPI 1885 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
1975 clocks = <&gcc GCC_BL 1886 clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>,
1976 <&gcc GCC_BL 1887 <&gcc GCC_BLSP1_AHB_CLK>;
1977 clock-names = "core", 1888 clock-names = "core", "iface";
1978 dmas = <&blsp_dma 14> 1889 dmas = <&blsp_dma 14>, <&blsp_dma 15>;
1979 dma-names = "tx", "rx 1890 dma-names = "tx", "rx";
1980 pinctrl-0 = <&blsp_sp 1891 pinctrl-0 = <&blsp_spi6_default>;
1981 pinctrl-1 = <&blsp_sp 1892 pinctrl-1 = <&blsp_spi6_sleep>;
1982 pinctrl-names = "defa 1893 pinctrl-names = "default", "sleep";
1983 #address-cells = <1>; 1894 #address-cells = <1>;
1984 #size-cells = <0>; 1895 #size-cells = <0>;
1985 status = "disabled"; 1896 status = "disabled";
1986 }; 1897 };
1987 1898
1988 usb: usb@78d9000 { 1899 usb: usb@78d9000 {
1989 compatible = "qcom,ci 1900 compatible = "qcom,ci-hdrc";
1990 reg = <0x078d9000 0x2 1901 reg = <0x078d9000 0x200>,
1991 <0x078d9200 0x2 1902 <0x078d9200 0x200>;
1992 interrupts = <GIC_SPI 1903 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
1993 <GIC_SPI 1904 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
1994 clocks = <&gcc GCC_US 1905 clocks = <&gcc GCC_USB_HS_AHB_CLK>,
1995 <&gcc GCC_US 1906 <&gcc GCC_USB_HS_SYSTEM_CLK>;
1996 clock-names = "iface" 1907 clock-names = "iface", "core";
1997 assigned-clocks = <&g 1908 assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>;
1998 assigned-clock-rates 1909 assigned-clock-rates = <80000000>;
1999 resets = <&gcc GCC_US 1910 resets = <&gcc GCC_USB_HS_BCR>;
2000 reset-names = "core"; 1911 reset-names = "core";
2001 #reset-cells = <1>; 1912 #reset-cells = <1>;
2002 phy_type = "ulpi"; 1913 phy_type = "ulpi";
2003 dr_mode = "otg"; 1914 dr_mode = "otg";
2004 adp-disable; 1915 adp-disable;
2005 hnp-disable; 1916 hnp-disable;
2006 srp-disable; 1917 srp-disable;
2007 ahb-burst-config = <0 1918 ahb-burst-config = <0>;
2008 phy-names = "usb-phy" 1919 phy-names = "usb-phy";
2009 phys = <&usb_hs_phy>; 1920 phys = <&usb_hs_phy>;
2010 status = "disabled"; 1921 status = "disabled";
2011 1922
2012 ulpi { 1923 ulpi {
2013 usb_hs_phy: p 1924 usb_hs_phy: phy {
2014 compa 1925 compatible = "qcom,usb-hs-phy-msm8916",
2015 1926 "qcom,usb-hs-phy";
2016 clock 1927 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
2017 1928 <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
2018 clock 1929 clock-names = "ref", "sleep";
2019 reset 1930 resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>;
2020 reset 1931 reset-names = "phy", "por";
2021 #phy- 1932 #phy-cells = <0>;
2022 qcom, 1933 qcom,init-seq = /bits/ 8 <0x0 0x44>,
2023 1934 <0x1 0x6b>,
2024 1935 <0x2 0x24>,
2025 1936 <0x3 0x13>;
2026 }; 1937 };
2027 }; 1938 };
2028 }; 1939 };
2029 1940
2030 wcnss: remoteproc@a204000 { 1941 wcnss: remoteproc@a204000 {
2031 compatible = "qcom,pr 1942 compatible = "qcom,pronto-v2-pil", "qcom,pronto";
2032 interrupts-extended = 1943 interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>,
2033 1944 <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2034 1945 <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2035 1946 <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2036 1947 <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
2037 interrupt-names = "wd 1948 interrupt-names = "wdog",
2038 "fa 1949 "fatal",
2039 "re 1950 "ready",
2040 "ha 1951 "handover",
2041 "st 1952 "stop-ack";
2042 reg = <0x0a204000 0x2 1953 reg = <0x0a204000 0x2000>,
2043 <0x0a202000 0x1 1954 <0x0a202000 0x1000>,
2044 <0x0a21b000 0x3 1955 <0x0a21b000 0x3000>;
2045 reg-names = "ccu", "d 1956 reg-names = "ccu", "dxe", "pmu";
2046 1957
2047 memory-region = <&wcn 1958 memory-region = <&wcnss_mem>;
2048 1959
2049 power-domains = <&rpm 1960 power-domains = <&rpmpd MSM8939_VDDCX>,
2050 <&rpm 1961 <&rpmpd MSM8939_VDDMX>;
2051 power-domain-names = 1962 power-domain-names = "cx", "mx";
2052 1963
2053 qcom,smem-states = <& 1964 qcom,smem-states = <&wcnss_smp2p_out 0>;
2054 qcom,smem-state-names 1965 qcom,smem-state-names = "stop";
2055 1966
2056 pinctrl-names = "defa 1967 pinctrl-names = "default";
2057 pinctrl-0 = <&wcss_wl 1968 pinctrl-0 = <&wcss_wlan_default>;
2058 1969
2059 status = "disabled"; 1970 status = "disabled";
2060 1971
2061 wcnss_iris: iris { 1972 wcnss_iris: iris {
2062 /* Separate c 1973 /* Separate chip, compatible is board-specific */
2063 clocks = <&rp 1974 clocks = <&rpmcc RPM_SMD_RF_CLK2>;
2064 clock-names = 1975 clock-names = "xo";
2065 }; 1976 };
2066 1977
2067 smd-edge { 1978 smd-edge {
2068 interrupts = 1979 interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>;
2069 mboxes = <&ap !! 1980 qcom,ipc = <&apcs1_mbox 8 17>;
2070 qcom,smd-edge 1981 qcom,smd-edge = <6>;
2071 qcom,remote-p 1982 qcom,remote-pid = <4>;
2072 1983
2073 label = "pron 1984 label = "pronto";
2074 1985
2075 wcnss { 1986 wcnss {
2076 compa 1987 compatible = "qcom,wcnss";
2077 qcom, 1988 qcom,smd-channels = "WCNSS_CTRL";
2078 1989
2079 qcom, 1990 qcom,mmio = <&wcnss>;
2080 1991
2081 wcnss 1992 wcnss_bt: bluetooth {
2082 1993 compatible = "qcom,wcnss-bt";
2083 }; 1994 };
2084 1995
2085 wcnss 1996 wcnss_wifi: wifi {
2086 1997 compatible = "qcom,wcnss-wlan";
2087 1998
2088 1999 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
2089 2000 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
2090 2001 interrupt-names = "tx", "rx";
2091 2002
2092 2003 qcom,smem-states = <&apps_smsm 10>,
2093 2004 <&apps_smsm 9>;
2094 2005 qcom,smem-state-names = "tx-enable",
2095 2006 "tx-rings-empty";
2096 }; 2007 };
2097 }; 2008 };
2098 }; 2009 };
2099 }; 2010 };
2100 2011
2101 intc: interrupt-controller@b0 2012 intc: interrupt-controller@b000000 {
2102 compatible = "qcom,ms 2013 compatible = "qcom,msm-qgic2";
2103 reg = <0x0b000000 0x1 2014 reg = <0x0b000000 0x1000>, <0x0b002000 0x2000>,
2104 <0x0b001000 0x1 2015 <0x0b001000 0x1000>, <0x0b004000 0x2000>;
2105 interrupt-controller; 2016 interrupt-controller;
2106 #interrupt-cells = <3 2017 #interrupt-cells = <3>;
2107 interrupts = <GIC_PPI 2018 interrupts = <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
2108 }; 2019 };
2109 2020
2110 apcs1_mbox: mailbox@b011000 { 2021 apcs1_mbox: mailbox@b011000 {
2111 compatible = "qcom,ms 2022 compatible = "qcom,msm8939-apcs-kpss-global", "syscon";
2112 reg = <0x0b011000 0x1 2023 reg = <0x0b011000 0x1000>;
2113 clocks = <&a53pll_c1> 2024 clocks = <&a53pll_c1>, <&gcc GPLL0_VOTE>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
2114 clock-names = "pll", 2025 clock-names = "pll", "aux", "ref";
2115 #clock-cells = <0>; 2026 #clock-cells = <0>;
2116 assigned-clocks = <&a 2027 assigned-clocks = <&apcs2>;
2117 assigned-clock-rates 2028 assigned-clock-rates = <297600000>;
2118 #mbox-cells = <1>; 2029 #mbox-cells = <1>;
2119 }; 2030 };
2120 2031
2121 a53pll_c1: clock@b016000 { 2032 a53pll_c1: clock@b016000 {
2122 compatible = "qcom,ms 2033 compatible = "qcom,msm8939-a53pll";
2123 reg = <0x0b016000 0x4 2034 reg = <0x0b016000 0x40>;
2124 #clock-cells = <0>; 2035 #clock-cells = <0>;
2125 }; 2036 };
2126 2037
2127 acc0: clock-controller@b08800 2038 acc0: clock-controller@b088000 {
2128 compatible = "qcom,kp 2039 compatible = "qcom,kpss-acc-v2";
2129 reg = <0x0b088000 0x1 2040 reg = <0x0b088000 0x1000>;
2130 }; 2041 };
2131 2042
2132 saw0: power-manager@b089000 { 2043 saw0: power-manager@b089000 {
2133 compatible = "qcom,ms 2044 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
2134 reg = <0x0b089000 0x1 2045 reg = <0x0b089000 0x1000>;
2135 }; 2046 };
2136 2047
2137 acc1: clock-controller@b09800 2048 acc1: clock-controller@b098000 {
2138 compatible = "qcom,kp 2049 compatible = "qcom,kpss-acc-v2";
2139 reg = <0x0b098000 0x1 2050 reg = <0x0b098000 0x1000>;
2140 }; 2051 };
2141 2052
2142 saw1: power-manager@b099000 { 2053 saw1: power-manager@b099000 {
2143 compatible = "qcom,ms 2054 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
2144 reg = <0x0b099000 0x1 2055 reg = <0x0b099000 0x1000>;
2145 }; 2056 };
2146 2057
2147 acc2: clock-controller@b0a800 2058 acc2: clock-controller@b0a8000 {
2148 compatible = "qcom,kp 2059 compatible = "qcom,kpss-acc-v2";
2149 reg = <0x0b0a8000 0x1 2060 reg = <0x0b0a8000 0x1000>;
2150 }; 2061 };
2151 2062
2152 saw2: power-manager@b0a9000 { 2063 saw2: power-manager@b0a9000 {
2153 compatible = "qcom,ms 2064 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
2154 reg = <0x0b0a9000 0x1 2065 reg = <0x0b0a9000 0x1000>;
2155 }; 2066 };
2156 2067
2157 acc3: clock-controller@b0b800 2068 acc3: clock-controller@b0b8000 {
2158 compatible = "qcom,kp 2069 compatible = "qcom,kpss-acc-v2";
2159 reg = <0x0b0b8000 0x1 2070 reg = <0x0b0b8000 0x1000>;
2160 }; 2071 };
2161 2072
2162 saw3: power-manager@b0b9000 { 2073 saw3: power-manager@b0b9000 {
2163 compatible = "qcom,ms 2074 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
2164 reg = <0x0b0b9000 0x1 2075 reg = <0x0b0b9000 0x1000>;
2165 }; 2076 };
2166 2077
2167 apcs0_mbox: mailbox@b111000 { 2078 apcs0_mbox: mailbox@b111000 {
2168 compatible = "qcom,ms 2079 compatible = "qcom,msm8939-apcs-kpss-global", "syscon";
2169 reg = <0x0b111000 0x1 2080 reg = <0x0b111000 0x1000>;
2170 clocks = <&a53pll_c0> 2081 clocks = <&a53pll_c0>, <&gcc GPLL0_VOTE>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
2171 clock-names = "pll", 2082 clock-names = "pll", "aux", "ref";
2172 #clock-cells = <0>; 2083 #clock-cells = <0>;
2173 #mbox-cells = <1>; 2084 #mbox-cells = <1>;
2174 }; 2085 };
2175 2086
2176 a53pll_c0: clock@b116000 { 2087 a53pll_c0: clock@b116000 {
2177 compatible = "qcom,ms 2088 compatible = "qcom,msm8939-a53pll";
2178 reg = <0x0b116000 0x4 2089 reg = <0x0b116000 0x40>;
2179 #clock-cells = <0>; 2090 #clock-cells = <0>;
2180 }; 2091 };
2181 2092
2182 timer@b120000 { 2093 timer@b120000 {
2183 compatible = "arm,arm 2094 compatible = "arm,armv7-timer-mem";
2184 reg = <0x0b120000 0x1 2095 reg = <0x0b120000 0x1000>;
2185 #address-cells = <1>; 2096 #address-cells = <1>;
2186 #size-cells = <1>; 2097 #size-cells = <1>;
2187 ranges; 2098 ranges;
2188 /* Necessary because <<
2189 clock-frequency = <19 <<
2190 2099
2191 frame@b121000 { 2100 frame@b121000 {
2192 reg = <0x0b12 2101 reg = <0x0b121000 0x1000>,
2193 <0x0b12 2102 <0x0b122000 0x1000>;
2194 interrupts = 2103 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
2195 2104 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
2196 frame-number 2105 frame-number = <0>;
2197 }; 2106 };
2198 2107
2199 frame@b123000 { 2108 frame@b123000 {
2200 reg = <0x0b12 2109 reg = <0x0b123000 0x1000>;
2201 interrupts = 2110 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
2202 frame-number 2111 frame-number = <1>;
2203 status = "dis 2112 status = "disabled";
2204 }; 2113 };
2205 2114
2206 frame@b124000 { 2115 frame@b124000 {
2207 reg = <0x0b12 2116 reg = <0x0b124000 0x1000>;
2208 interrupts = 2117 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
2209 frame-number 2118 frame-number = <2>;
2210 status = "dis 2119 status = "disabled";
2211 }; 2120 };
2212 2121
2213 frame@b125000 { 2122 frame@b125000 {
2214 reg = <0x0b12 2123 reg = <0x0b125000 0x1000>;
2215 interrupts = 2124 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
2216 frame-number 2125 frame-number = <3>;
2217 status = "dis 2126 status = "disabled";
2218 }; 2127 };
2219 2128
2220 frame@b126000 { 2129 frame@b126000 {
2221 reg = <0x0b12 2130 reg = <0x0b126000 0x1000>;
2222 interrupts = 2131 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
2223 frame-number 2132 frame-number = <4>;
2224 status = "dis 2133 status = "disabled";
2225 }; 2134 };
2226 2135
2227 frame@b127000 { 2136 frame@b127000 {
2228 reg = <0x0b12 2137 reg = <0x0b127000 0x1000>;
2229 interrupts = 2138 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
2230 frame-number 2139 frame-number = <5>;
2231 status = "dis 2140 status = "disabled";
2232 }; 2141 };
2233 2142
2234 frame@b128000 { 2143 frame@b128000 {
2235 reg = <0x0b12 2144 reg = <0x0b128000 0x1000>;
2236 interrupts = 2145 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
2237 frame-number 2146 frame-number = <6>;
2238 status = "dis 2147 status = "disabled";
2239 }; 2148 };
2240 }; 2149 };
2241 2150
2242 acc4: clock-controller@b18800 2151 acc4: clock-controller@b188000 {
2243 compatible = "qcom,kp 2152 compatible = "qcom,kpss-acc-v2";
2244 reg = <0x0b188000 0x1 2153 reg = <0x0b188000 0x1000>;
2245 }; 2154 };
2246 2155
2247 saw4: power-manager@b189000 { 2156 saw4: power-manager@b189000 {
2248 compatible = "qcom,ms 2157 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
2249 reg = <0x0b189000 0x1 2158 reg = <0x0b189000 0x1000>;
2250 }; 2159 };
2251 2160
2252 acc5: clock-controller@b19800 2161 acc5: clock-controller@b198000 {
2253 compatible = "qcom,kp 2162 compatible = "qcom,kpss-acc-v2";
2254 reg = <0x0b198000 0x1 2163 reg = <0x0b198000 0x1000>;
2255 }; 2164 };
2256 2165
2257 saw5: power-manager@b199000 { 2166 saw5: power-manager@b199000 {
2258 compatible = "qcom,ms 2167 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
2259 reg = <0x0b199000 0x1 2168 reg = <0x0b199000 0x1000>;
2260 }; 2169 };
2261 2170
2262 acc6: clock-controller@b1a800 2171 acc6: clock-controller@b1a8000 {
2263 compatible = "qcom,kp 2172 compatible = "qcom,kpss-acc-v2";
2264 reg = <0x0b1a8000 0x1 2173 reg = <0x0b1a8000 0x1000>;
2265 }; 2174 };
2266 2175
2267 saw6: power-manager@b1a9000 { 2176 saw6: power-manager@b1a9000 {
2268 compatible = "qcom,ms 2177 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
2269 reg = <0x0b1a9000 0x1 2178 reg = <0x0b1a9000 0x1000>;
2270 }; 2179 };
2271 2180
2272 acc7: clock-controller@b1b800 2181 acc7: clock-controller@b1b8000 {
2273 compatible = "qcom,kp 2182 compatible = "qcom,kpss-acc-v2";
2274 reg = <0x0b1b8000 0x1 2183 reg = <0x0b1b8000 0x1000>;
2275 }; 2184 };
2276 2185
2277 saw7: power-manager@b1b9000 { 2186 saw7: power-manager@b1b9000 {
2278 compatible = "qcom,ms 2187 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
2279 reg = <0x0b1b9000 0x1 2188 reg = <0x0b1b9000 0x1000>;
2280 }; 2189 };
2281 2190
2282 a53pll_cci: clock@b1d0000 { 2191 a53pll_cci: clock@b1d0000 {
2283 compatible = "qcom,ms 2192 compatible = "qcom,msm8939-a53pll";
2284 reg = <0x0b1d0000 0x4 2193 reg = <0x0b1d0000 0x40>;
2285 #clock-cells = <0>; 2194 #clock-cells = <0>;
2286 }; 2195 };
2287 2196
2288 apcs2: mailbox@b1d1000 { 2197 apcs2: mailbox@b1d1000 {
2289 compatible = "qcom,ms 2198 compatible = "qcom,msm8939-apcs-kpss-global", "syscon";
2290 reg = <0x0b1d1000 0x1 2199 reg = <0x0b1d1000 0x1000>;
2291 clocks = <&a53pll_cci 2200 clocks = <&a53pll_cci>, <&gcc GPLL0_VOTE>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
2292 clock-names = "pll", 2201 clock-names = "pll", "aux", "ref";
2293 #clock-cells = <0>; 2202 #clock-cells = <0>;
2294 #mbox-cells = <1>; 2203 #mbox-cells = <1>;
2295 }; 2204 };
2296 }; 2205 };
2297 2206
2298 thermal_zones: thermal-zones { 2207 thermal_zones: thermal-zones {
2299 cpu0-thermal { 2208 cpu0-thermal {
2300 polling-delay-passive 2209 polling-delay-passive = <250>;
>> 2210 polling-delay = <1000>;
2301 2211
2302 thermal-sensors = <&t 2212 thermal-sensors = <&tsens 5>;
2303 2213
2304 trips { 2214 trips {
2305 cpu0_alert: t 2215 cpu0_alert: trip0 {
2306 tempe 2216 temperature = <75000>;
2307 hyste 2217 hysteresis = <2000>;
2308 type 2218 type = "passive";
2309 }; 2219 };
2310 2220
2311 cpu0_crit: tr 2221 cpu0_crit: trip1 {
2312 tempe 2222 temperature = <115000>;
2313 hyste 2223 hysteresis = <0>;
2314 type 2224 type = "critical";
2315 }; 2225 };
2316 }; 2226 };
2317 2227
2318 cooling-maps { 2228 cooling-maps {
2319 map0 { 2229 map0 {
2320 trip 2230 trip = <&cpu0_alert>;
2321 cooli 2231 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2322 2232 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2323 2233 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2324 2234 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2325 }; 2235 };
2326 }; 2236 };
2327 }; 2237 };
2328 2238
2329 cpu1-thermal { 2239 cpu1-thermal {
2330 polling-delay-passive 2240 polling-delay-passive = <250>;
>> 2241 polling-delay = <1000>;
2331 2242
2332 thermal-sensors = <&t 2243 thermal-sensors = <&tsens 6>;
2333 2244
2334 trips { 2245 trips {
2335 cpu1_alert: t 2246 cpu1_alert: trip0 {
2336 tempe 2247 temperature = <75000>;
2337 hyste 2248 hysteresis = <2000>;
2338 type 2249 type = "passive";
2339 }; 2250 };
2340 2251
2341 cpu1_crit: tr 2252 cpu1_crit: trip1 {
2342 tempe 2253 temperature = <110000>;
2343 hyste 2254 hysteresis = <2000>;
2344 type 2255 type = "critical";
2345 }; 2256 };
2346 }; 2257 };
2347 2258
2348 cooling-maps { 2259 cooling-maps {
2349 map0 { 2260 map0 {
2350 trip 2261 trip = <&cpu1_alert>;
2351 cooli 2262 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2352 2263 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2353 2264 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2354 2265 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2355 }; 2266 };
2356 }; 2267 };
2357 }; 2268 };
2358 2269
2359 cpu2-thermal { 2270 cpu2-thermal {
2360 polling-delay-passive 2271 polling-delay-passive = <250>;
>> 2272 polling-delay = <1000>;
2361 2273
2362 thermal-sensors = <&t 2274 thermal-sensors = <&tsens 7>;
2363 2275
2364 trips { 2276 trips {
2365 cpu2_alert: t 2277 cpu2_alert: trip0 {
2366 tempe 2278 temperature = <75000>;
2367 hyste 2279 hysteresis = <2000>;
2368 type 2280 type = "passive";
2369 }; 2281 };
2370 2282
2371 cpu2_crit: tr 2283 cpu2_crit: trip1 {
2372 tempe 2284 temperature = <110000>;
2373 hyste 2285 hysteresis = <2000>;
2374 type 2286 type = "critical";
2375 }; 2287 };
2376 }; 2288 };
2377 2289
2378 cooling-maps { 2290 cooling-maps {
2379 map0 { 2291 map0 {
2380 trip 2292 trip = <&cpu2_alert>;
2381 cooli 2293 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2382 2294 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2383 2295 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2384 2296 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2385 }; 2297 };
2386 }; 2298 };
2387 }; 2299 };
2388 2300
2389 cpu3-thermal { 2301 cpu3-thermal {
2390 polling-delay-passive 2302 polling-delay-passive = <250>;
>> 2303 polling-delay = <1000>;
2391 2304
2392 thermal-sensors = <&t 2305 thermal-sensors = <&tsens 8>;
2393 2306
2394 trips { 2307 trips {
2395 cpu3_alert: t 2308 cpu3_alert: trip0 {
2396 tempe 2309 temperature = <75000>;
2397 hyste 2310 hysteresis = <2000>;
2398 type 2311 type = "passive";
2399 }; 2312 };
2400 2313
2401 cpu3_crit: tr 2314 cpu3_crit: trip1 {
2402 tempe 2315 temperature = <110000>;
2403 hyste 2316 hysteresis = <2000>;
2404 type 2317 type = "critical";
2405 }; 2318 };
2406 }; 2319 };
2407 2320
2408 cooling-maps { 2321 cooling-maps {
2409 map0 { 2322 map0 {
2410 trip 2323 trip = <&cpu3_alert>;
2411 cooli 2324 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2412 2325 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2413 2326 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2414 2327 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2415 }; 2328 };
2416 }; 2329 };
2417 }; 2330 };
2418 2331
2419 cpu4567-thermal { 2332 cpu4567-thermal {
2420 polling-delay-passive 2333 polling-delay-passive = <250>;
>> 2334 polling-delay = <1000>;
2421 2335
2422 thermal-sensors = <&t 2336 thermal-sensors = <&tsens 9>;
2423 2337
2424 trips { 2338 trips {
2425 cpu4567_alert 2339 cpu4567_alert: trip0 {
2426 tempe 2340 temperature = <75000>;
2427 hyste 2341 hysteresis = <2000>;
2428 type 2342 type = "passive";
2429 }; 2343 };
2430 2344
2431 cpu4567_crit: 2345 cpu4567_crit: trip1 {
2432 tempe 2346 temperature = <110000>;
2433 hyste 2347 hysteresis = <2000>;
2434 type 2348 type = "critical";
2435 }; 2349 };
2436 }; 2350 };
2437 2351
2438 cooling-maps { 2352 cooling-maps {
2439 map0 { 2353 map0 {
2440 trip 2354 trip = <&cpu4567_alert>;
2441 cooli 2355 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2442 2356 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2443 2357 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2444 2358 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2445 }; 2359 };
2446 }; 2360 };
2447 }; 2361 };
2448 2362
2449 gpu-thermal { 2363 gpu-thermal {
2450 polling-delay-passive 2364 polling-delay-passive = <250>;
>> 2365 polling-delay = <1000>;
2451 2366
2452 thermal-sensors = <&t 2367 thermal-sensors = <&tsens 3>;
2453 2368
2454 cooling-maps { <<
2455 map0 { <<
2456 trip <<
2457 cooli <<
2458 }; <<
2459 }; <<
2460 <<
2461 trips { 2369 trips {
2462 gpu_alert0: t 2370 gpu_alert0: trip-point0 {
2463 tempe 2371 temperature = <75000>;
2464 hyste 2372 hysteresis = <2000>;
2465 type 2373 type = "passive";
2466 }; 2374 };
2467 2375
2468 gpu_crit: gpu !! 2376 gpu_crit: gpu_crit {
2469 tempe 2377 temperature = <95000>;
2470 hyste 2378 hysteresis = <2000>;
2471 type 2379 type = "critical";
2472 }; 2380 };
2473 }; 2381 };
2474 }; 2382 };
2475 2383
2476 modem1-thermal { 2384 modem1-thermal {
2477 polling-delay-passive 2385 polling-delay-passive = <250>;
>> 2386 polling-delay = <1000>;
2478 2387
2479 thermal-sensors = <&t 2388 thermal-sensors = <&tsens 0>;
2480 2389
2481 trips { 2390 trips {
2482 modem1_alert0 2391 modem1_alert0: trip-point0 {
2483 tempe 2392 temperature = <85000>;
2484 hyste 2393 hysteresis = <2000>;
2485 type 2394 type = "hot";
2486 }; 2395 };
2487 }; 2396 };
2488 }; 2397 };
2489 2398
2490 modem2-thermal { 2399 modem2-thermal {
2491 polling-delay-passive 2400 polling-delay-passive = <250>;
>> 2401 polling-delay = <1000>;
2492 2402
2493 thermal-sensors = <&t 2403 thermal-sensors = <&tsens 2>;
2494 2404
2495 trips { 2405 trips {
2496 modem2_alert0 2406 modem2_alert0: trip-point0 {
2497 tempe 2407 temperature = <85000>;
2498 hyste 2408 hysteresis = <2000>;
2499 type 2409 type = "hot";
2500 }; 2410 };
2501 }; 2411 };
2502 }; 2412 };
2503 2413
2504 camera-thermal { 2414 camera-thermal {
2505 polling-delay-passive 2415 polling-delay-passive = <250>;
>> 2416 polling-delay = <1000>;
2506 2417
2507 thermal-sensors = <&t 2418 thermal-sensors = <&tsens 1>;
2508 2419
2509 trips { 2420 trips {
2510 cam_alert0: t 2421 cam_alert0: trip-point0 {
2511 tempe 2422 temperature = <75000>;
2512 hyste 2423 hysteresis = <2000>;
2513 type 2424 type = "hot";
2514 }; 2425 };
2515 }; 2426 };
2516 }; 2427 };
2517 }; 2428 };
2518 2429
2519 timer { 2430 timer {
2520 compatible = "arm,armv8-timer 2431 compatible = "arm,armv8-timer";
2521 interrupts = <GIC_PPI 2 (GIC_ 2432 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
2522 <GIC_PPI 3 (GIC_ 2433 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
2523 <GIC_PPI 4 (GIC_ 2434 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
2524 <GIC_PPI 1 (GIC_ 2435 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
2525 }; 2436 };
2526 }; 2437 };
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