1 // SPDX-License-Identifier: GPL-2.0-only 1 // SPDX-License-Identifier: GPL-2.0-only
2 /* 2 /*
3 * Copyright (c) 2013-2015, The Linux Foundati 3 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2020-2023, Linaro Limited 4 * Copyright (c) 2020-2023, Linaro Limited
5 */ 5 */
6 6
7 #include <dt-bindings/clock/qcom,gcc-msm8939.h 7 #include <dt-bindings/clock/qcom,gcc-msm8939.h>
8 #include <dt-bindings/clock/qcom,rpmcc.h> 8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/interconnect/qcom,msm893 9 #include <dt-bindings/interconnect/qcom,msm8939.h>
10 #include <dt-bindings/interrupt-controller/arm 10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/power/qcom-rpmpd.h> 11 #include <dt-bindings/power/qcom-rpmpd.h>
12 #include <dt-bindings/reset/qcom,gcc-msm8939.h 12 #include <dt-bindings/reset/qcom,gcc-msm8939.h>
13 #include <dt-bindings/soc/qcom,apr.h> <<
14 #include <dt-bindings/thermal/thermal.h> 13 #include <dt-bindings/thermal/thermal.h>
15 14
16 / { 15 / {
17 interrupt-parent = <&intc>; 16 interrupt-parent = <&intc>;
18 17
19 /* 18 /*
20 * Stock LK wants address-cells/size-c 19 * Stock LK wants address-cells/size-cells = 2
21 * A number of our drivers want addres 20 * A number of our drivers want address/size cells = 1
22 * hence the disparity between top-lev 21 * hence the disparity between top-level and /soc below.
23 */ 22 */
24 #address-cells = <2>; 23 #address-cells = <2>;
25 #size-cells = <2>; 24 #size-cells = <2>;
26 25
27 clocks { 26 clocks {
28 xo_board: xo-board { 27 xo_board: xo-board {
29 compatible = "fixed-cl 28 compatible = "fixed-clock";
30 #clock-cells = <0>; 29 #clock-cells = <0>;
31 clock-frequency = <192 30 clock-frequency = <19200000>;
32 }; 31 };
33 32
34 sleep_clk: sleep-clk { 33 sleep_clk: sleep-clk {
35 compatible = "fixed-cl 34 compatible = "fixed-clock";
36 #clock-cells = <0>; 35 #clock-cells = <0>;
37 clock-frequency = <327 36 clock-frequency = <32768>;
38 }; 37 };
39 }; 38 };
40 39
41 cpus { 40 cpus {
42 #address-cells = <1>; 41 #address-cells = <1>;
43 #size-cells = <0>; 42 #size-cells = <0>;
44 43
45 CPU0: cpu@100 { 44 CPU0: cpu@100 {
46 compatible = "arm,cort 45 compatible = "arm,cortex-a53";
47 device_type = "cpu"; 46 device_type = "cpu";
48 enable-method = "spin- 47 enable-method = "spin-table";
49 reg = <0x100>; 48 reg = <0x100>;
50 next-level-cache = <&L 49 next-level-cache = <&L2_1>;
51 qcom,acc = <&acc0>; 50 qcom,acc = <&acc0>;
52 qcom,saw = <&saw0>; 51 qcom,saw = <&saw0>;
53 cpu-idle-states = <&CP 52 cpu-idle-states = <&CPU_SLEEP_0>;
54 clocks = <&apcs1_mbox> 53 clocks = <&apcs1_mbox>;
55 #cooling-cells = <2>; 54 #cooling-cells = <2>;
56 L2_1: l2-cache { 55 L2_1: l2-cache {
57 compatible = " 56 compatible = "cache";
58 cache-level = 57 cache-level = <2>;
59 cache-unified; 58 cache-unified;
60 }; 59 };
61 }; 60 };
62 61
63 CPU1: cpu@101 { 62 CPU1: cpu@101 {
64 compatible = "arm,cort 63 compatible = "arm,cortex-a53";
65 device_type = "cpu"; 64 device_type = "cpu";
66 enable-method = "spin- 65 enable-method = "spin-table";
67 reg = <0x101>; 66 reg = <0x101>;
68 next-level-cache = <&L 67 next-level-cache = <&L2_1>;
69 qcom,acc = <&acc1>; 68 qcom,acc = <&acc1>;
70 qcom,saw = <&saw1>; 69 qcom,saw = <&saw1>;
71 cpu-idle-states = <&CP 70 cpu-idle-states = <&CPU_SLEEP_0>;
72 clocks = <&apcs1_mbox> 71 clocks = <&apcs1_mbox>;
73 #cooling-cells = <2>; 72 #cooling-cells = <2>;
74 }; 73 };
75 74
76 CPU2: cpu@102 { 75 CPU2: cpu@102 {
77 compatible = "arm,cort 76 compatible = "arm,cortex-a53";
78 device_type = "cpu"; 77 device_type = "cpu";
79 enable-method = "spin- 78 enable-method = "spin-table";
80 reg = <0x102>; 79 reg = <0x102>;
81 next-level-cache = <&L 80 next-level-cache = <&L2_1>;
82 qcom,acc = <&acc2>; 81 qcom,acc = <&acc2>;
83 qcom,saw = <&saw2>; 82 qcom,saw = <&saw2>;
84 cpu-idle-states = <&CP 83 cpu-idle-states = <&CPU_SLEEP_0>;
85 clocks = <&apcs1_mbox> 84 clocks = <&apcs1_mbox>;
86 #cooling-cells = <2>; 85 #cooling-cells = <2>;
87 }; 86 };
88 87
89 CPU3: cpu@103 { 88 CPU3: cpu@103 {
90 compatible = "arm,cort 89 compatible = "arm,cortex-a53";
91 device_type = "cpu"; 90 device_type = "cpu";
92 enable-method = "spin- 91 enable-method = "spin-table";
93 reg = <0x103>; 92 reg = <0x103>;
94 next-level-cache = <&L 93 next-level-cache = <&L2_1>;
95 qcom,acc = <&acc3>; 94 qcom,acc = <&acc3>;
96 qcom,saw = <&saw3>; 95 qcom,saw = <&saw3>;
97 cpu-idle-states = <&CP 96 cpu-idle-states = <&CPU_SLEEP_0>;
98 clocks = <&apcs1_mbox> 97 clocks = <&apcs1_mbox>;
99 #cooling-cells = <2>; 98 #cooling-cells = <2>;
100 }; 99 };
101 100
102 CPU4: cpu@0 { 101 CPU4: cpu@0 {
103 compatible = "arm,cort 102 compatible = "arm,cortex-a53";
104 device_type = "cpu"; 103 device_type = "cpu";
105 enable-method = "spin- 104 enable-method = "spin-table";
106 reg = <0x0>; 105 reg = <0x0>;
107 qcom,acc = <&acc4>; 106 qcom,acc = <&acc4>;
108 qcom,saw = <&saw4>; 107 qcom,saw = <&saw4>;
109 cpu-idle-states = <&CP 108 cpu-idle-states = <&CPU_SLEEP_0>;
110 clocks = <&apcs0_mbox> 109 clocks = <&apcs0_mbox>;
111 #cooling-cells = <2>; 110 #cooling-cells = <2>;
112 next-level-cache = <&L 111 next-level-cache = <&L2_0>;
113 L2_0: l2-cache { 112 L2_0: l2-cache {
114 compatible = " 113 compatible = "cache";
115 cache-level = 114 cache-level = <2>;
116 cache-unified; 115 cache-unified;
117 }; 116 };
118 }; 117 };
119 118
120 CPU5: cpu@1 { 119 CPU5: cpu@1 {
121 compatible = "arm,cort 120 compatible = "arm,cortex-a53";
122 device_type = "cpu"; 121 device_type = "cpu";
123 enable-method = "spin- 122 enable-method = "spin-table";
124 reg = <0x1>; 123 reg = <0x1>;
125 next-level-cache = <&L 124 next-level-cache = <&L2_0>;
126 qcom,acc = <&acc5>; 125 qcom,acc = <&acc5>;
127 qcom,saw = <&saw5>; 126 qcom,saw = <&saw5>;
128 cpu-idle-states = <&CP 127 cpu-idle-states = <&CPU_SLEEP_0>;
129 clocks = <&apcs0_mbox> 128 clocks = <&apcs0_mbox>;
130 #cooling-cells = <2>; 129 #cooling-cells = <2>;
131 }; 130 };
132 131
133 CPU6: cpu@2 { 132 CPU6: cpu@2 {
134 compatible = "arm,cort 133 compatible = "arm,cortex-a53";
135 device_type = "cpu"; 134 device_type = "cpu";
136 enable-method = "spin- 135 enable-method = "spin-table";
137 reg = <0x2>; 136 reg = <0x2>;
138 next-level-cache = <&L 137 next-level-cache = <&L2_0>;
139 qcom,acc = <&acc6>; 138 qcom,acc = <&acc6>;
140 qcom,saw = <&saw6>; 139 qcom,saw = <&saw6>;
141 cpu-idle-states = <&CP 140 cpu-idle-states = <&CPU_SLEEP_0>;
142 clocks = <&apcs0_mbox> 141 clocks = <&apcs0_mbox>;
143 #cooling-cells = <2>; 142 #cooling-cells = <2>;
144 }; 143 };
145 144
146 CPU7: cpu@3 { 145 CPU7: cpu@3 {
147 compatible = "arm,cort 146 compatible = "arm,cortex-a53";
148 device_type = "cpu"; 147 device_type = "cpu";
149 enable-method = "spin- 148 enable-method = "spin-table";
150 reg = <0x3>; 149 reg = <0x3>;
151 next-level-cache = <&L 150 next-level-cache = <&L2_0>;
152 qcom,acc = <&acc7>; 151 qcom,acc = <&acc7>;
153 qcom,saw = <&saw7>; 152 qcom,saw = <&saw7>;
154 cpu-idle-states = <&CP 153 cpu-idle-states = <&CPU_SLEEP_0>;
155 clocks = <&apcs0_mbox> 154 clocks = <&apcs0_mbox>;
156 #cooling-cells = <2>; 155 #cooling-cells = <2>;
157 }; 156 };
158 157
159 idle-states { 158 idle-states {
160 CPU_SLEEP_0: cpu-sleep 159 CPU_SLEEP_0: cpu-sleep-0 {
161 compatible = " 160 compatible = "arm,idle-state";
162 entry-latency- 161 entry-latency-us = <130>;
163 exit-latency-u 162 exit-latency-us = <150>;
164 min-residency- 163 min-residency-us = <2000>;
165 local-timer-st 164 local-timer-stop;
166 }; 165 };
167 }; 166 };
168 }; 167 };
169 168
170 /* 169 /*
171 * MSM8939 has a big.LITTLE heterogene 170 * MSM8939 has a big.LITTLE heterogeneous computing architecture,
172 * consisting of two clusters of four 171 * consisting of two clusters of four ARM Cortex-A53s each. The
173 * LITTLE cluster runs at 1.0-1.2GHz, 172 * LITTLE cluster runs at 1.0-1.2GHz, and the big cluster runs
174 * at 1.5-1.7GHz. 173 * at 1.5-1.7GHz.
175 * 174 *
176 * The enable method used here is spin 175 * The enable method used here is spin-table which presupposes use
177 * of a 2nd stage boot shim such as lk 176 * of a 2nd stage boot shim such as lk2nd to have installed a
178 * spin-table, the downstream non-psci 177 * spin-table, the downstream non-psci/non-spin-table method that
179 * default msm8916/msm8936/msm8939 wil 178 * default msm8916/msm8936/msm8939 will not be supported upstream.
180 */ 179 */
181 cpu-map { 180 cpu-map {
182 /* LITTLE (efficiency) cluster 181 /* LITTLE (efficiency) cluster */
183 cluster0 { 182 cluster0 {
184 core0 { 183 core0 {
185 cpu = <&CPU4>; 184 cpu = <&CPU4>;
186 }; 185 };
187 186
188 core1 { 187 core1 {
189 cpu = <&CPU5>; 188 cpu = <&CPU5>;
190 }; 189 };
191 190
192 core2 { 191 core2 {
193 cpu = <&CPU6>; 192 cpu = <&CPU6>;
194 }; 193 };
195 194
196 core3 { 195 core3 {
197 cpu = <&CPU7>; 196 cpu = <&CPU7>;
198 }; 197 };
199 }; 198 };
200 199
201 /* big (performance) cluster * 200 /* big (performance) cluster */
202 /* Boot CPU is cluster 1 core 201 /* Boot CPU is cluster 1 core 0 */
203 cluster1 { 202 cluster1 {
204 core0 { 203 core0 {
205 cpu = <&CPU0>; 204 cpu = <&CPU0>;
206 }; 205 };
207 206
208 core1 { 207 core1 {
209 cpu = <&CPU1>; 208 cpu = <&CPU1>;
210 }; 209 };
211 210
212 core2 { 211 core2 {
213 cpu = <&CPU2>; 212 cpu = <&CPU2>;
214 }; 213 };
215 214
216 core3 { 215 core3 {
217 cpu = <&CPU3>; 216 cpu = <&CPU3>;
218 }; 217 };
219 }; 218 };
220 }; 219 };
221 220
222 firmware { 221 firmware {
223 scm: scm { 222 scm: scm {
224 compatible = "qcom,scm 223 compatible = "qcom,scm-msm8916", "qcom,scm";
225 clocks = <&gcc GCC_CRY 224 clocks = <&gcc GCC_CRYPTO_CLK>,
226 <&gcc GCC_CRY 225 <&gcc GCC_CRYPTO_AXI_CLK>,
227 <&gcc GCC_CRY 226 <&gcc GCC_CRYPTO_AHB_CLK>;
228 clock-names = "core", 227 clock-names = "core", "bus", "iface";
229 #reset-cells = <1>; 228 #reset-cells = <1>;
230 229
231 qcom,dload-mode = <&tc 230 qcom,dload-mode = <&tcsr 0x6100>;
232 }; 231 };
233 }; 232 };
234 233
235 memory@80000000 { 234 memory@80000000 {
236 device_type = "memory"; 235 device_type = "memory";
237 /* We expect the bootloader to 236 /* We expect the bootloader to fill in the reg */
238 reg = <0x0 0x80000000 0x0 0x0> 237 reg = <0x0 0x80000000 0x0 0x0>;
239 }; 238 };
240 239
241 pmu { 240 pmu {
242 compatible = "arm,cortex-a53-p 241 compatible = "arm,cortex-a53-pmu";
243 interrupts = <GIC_PPI 7 (GIC_C 242 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
244 }; 243 };
245 244
246 rpm: remoteproc { 245 rpm: remoteproc {
247 compatible = "qcom,msm8936-rpm 246 compatible = "qcom,msm8936-rpm-proc", "qcom,rpm-proc";
248 247
249 smd-edge { 248 smd-edge {
250 interrupts = <GIC_SPI 249 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
251 qcom,ipc = <&apcs1_mbo 250 qcom,ipc = <&apcs1_mbox 8 0>;
252 qcom,smd-edge = <15>; 251 qcom,smd-edge = <15>;
253 252
254 rpm_requests: rpm-requ 253 rpm_requests: rpm-requests {
255 compatible = " !! 254 compatible = "qcom,rpm-msm8936";
256 qcom,smd-chann 255 qcom,smd-channels = "rpm_requests";
257 256
258 rpmcc: clock-c 257 rpmcc: clock-controller {
259 compat 258 compatible = "qcom,rpmcc-msm8936", "qcom,rpmcc";
260 #clock 259 #clock-cells = <1>;
261 clock- 260 clock-names = "xo";
262 clocks 261 clocks = <&xo_board>;
263 }; 262 };
264 263
265 rpmpd: power-c 264 rpmpd: power-controller {
266 compat 265 compatible = "qcom,msm8939-rpmpd";
267 #power 266 #power-domain-cells = <1>;
268 operat 267 operating-points-v2 = <&rpmpd_opp_table>;
269 268
270 rpmpd_ 269 rpmpd_opp_table: opp-table {
271 270 compatible = "operating-points-v2";
272 271
273 272 rpmpd_opp_ret: opp1 {
274 273 opp-level = <1>;
275 274 };
276 275
277 276 rpmpd_opp_svs_krait: opp2 {
278 277 opp-level = <2>;
279 278 };
280 279
281 280 rpmpd_opp_svs_soc: opp3 {
282 281 opp-level = <3>;
283 282 };
284 283
285 284 rpmpd_opp_nom: opp4 {
286 285 opp-level = <4>;
287 286 };
288 287
289 288 rpmpd_opp_turbo: opp5 {
290 289 opp-level = <5>;
291 290 };
292 291
293 292 rpmpd_opp_super_turbo: opp6 {
294 293 opp-level = <6>;
295 294 };
296 }; 295 };
297 }; 296 };
298 }; 297 };
299 }; 298 };
300 }; 299 };
301 300
302 reserved-memory { 301 reserved-memory {
303 #address-cells = <2>; 302 #address-cells = <2>;
304 #size-cells = <2>; 303 #size-cells = <2>;
305 ranges; 304 ranges;
306 305
307 tz-apps@86000000 { 306 tz-apps@86000000 {
308 reg = <0x0 0x86000000 307 reg = <0x0 0x86000000 0x0 0x300000>;
309 no-map; 308 no-map;
310 }; 309 };
311 310
312 smem@86300000 { 311 smem@86300000 {
313 compatible = "qcom,sme 312 compatible = "qcom,smem";
314 reg = <0x0 0x86300000 313 reg = <0x0 0x86300000 0x0 0x100000>;
315 no-map; 314 no-map;
316 315
317 hwlocks = <&tcsr_mutex 316 hwlocks = <&tcsr_mutex 3>;
318 qcom,rpm-msg-ram = <&r 317 qcom,rpm-msg-ram = <&rpm_msg_ram>;
319 }; 318 };
320 319
321 hypervisor@86400000 { 320 hypervisor@86400000 {
322 reg = <0x0 0x86400000 321 reg = <0x0 0x86400000 0x0 0x100000>;
323 no-map; 322 no-map;
324 }; 323 };
325 324
326 tz@86500000 { 325 tz@86500000 {
327 reg = <0x0 0x86500000 326 reg = <0x0 0x86500000 0x0 0x180000>;
328 no-map; 327 no-map;
329 }; 328 };
330 329
331 reserved@86680000 { 330 reserved@86680000 {
332 reg = <0x0 0x86680000 331 reg = <0x0 0x86680000 0x0 0x80000>;
333 no-map; 332 no-map;
334 }; 333 };
335 334
336 rmtfs@86700000 { 335 rmtfs@86700000 {
337 compatible = "qcom,rmt 336 compatible = "qcom,rmtfs-mem";
338 reg = <0x0 0x86700000 337 reg = <0x0 0x86700000 0x0 0xe0000>;
339 no-map; 338 no-map;
340 339
341 qcom,client-id = <1>; 340 qcom,client-id = <1>;
342 }; 341 };
343 342
344 rfsa@867e0000 { 343 rfsa@867e0000 {
345 reg = <0x0 0x867e0000 344 reg = <0x0 0x867e0000 0x0 0x20000>;
346 no-map; 345 no-map;
347 }; 346 };
348 347
349 mpss_mem: mpss@86800000 { 348 mpss_mem: mpss@86800000 {
350 /* 349 /*
351 * The memory region f 350 * The memory region for the mpss firmware is generally
352 * relocatable and cou 351 * relocatable and could be allocated dynamically.
353 * However, many firmw 352 * However, many firmware versions tend to fail when
354 * loaded to some spec 353 * loaded to some special addresses, so it is hard to
355 * define reliable all 354 * define reliable alloc-ranges.
356 * 355 *
357 * alignment = <0x0 0x 356 * alignment = <0x0 0x400000>;
358 * alloc-ranges = <0x0 357 * alloc-ranges = <0x0 0x86800000 0x0 0x8000000>;
359 */ 358 */
360 reg = <0x0 0x86800000 359 reg = <0x0 0x86800000 0x0 0>; /* size is device-specific */
361 no-map; 360 no-map;
362 status = "disabled"; 361 status = "disabled";
363 }; 362 };
364 363
365 wcnss_mem: wcnss { 364 wcnss_mem: wcnss {
366 size = <0x0 0x600000>; 365 size = <0x0 0x600000>;
367 alignment = <0x0 0x100 366 alignment = <0x0 0x100000>;
368 alloc-ranges = <0x0 0x 367 alloc-ranges = <0x0 0x86800000 0x0 0x8000000>;
369 no-map; 368 no-map;
370 status = "disabled"; 369 status = "disabled";
371 }; 370 };
372 371
373 venus_mem: venus { 372 venus_mem: venus {
374 size = <0x0 0x500000>; 373 size = <0x0 0x500000>;
375 alignment = <0x0 0x100 374 alignment = <0x0 0x100000>;
376 alloc-ranges = <0x0 0x 375 alloc-ranges = <0x0 0x86800000 0x0 0x8000000>;
377 no-map; 376 no-map;
378 status = "disabled"; 377 status = "disabled";
379 }; 378 };
380 379
381 mba_mem: mba { 380 mba_mem: mba {
382 size = <0x0 0x100000>; 381 size = <0x0 0x100000>;
383 alignment = <0x0 0x100 382 alignment = <0x0 0x100000>;
384 alloc-ranges = <0x0 0x 383 alloc-ranges = <0x0 0x86800000 0x0 0x8000000>;
385 no-map; 384 no-map;
386 status = "disabled"; 385 status = "disabled";
387 }; 386 };
388 }; 387 };
389 388
390 smp2p-hexagon { 389 smp2p-hexagon {
391 compatible = "qcom,smp2p"; 390 compatible = "qcom,smp2p";
392 qcom,smem = <435>, <428>; 391 qcom,smem = <435>, <428>;
393 392
394 interrupts = <GIC_SPI 27 IRQ_T 393 interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>;
395 394
396 mboxes = <&apcs1_mbox 14>; 395 mboxes = <&apcs1_mbox 14>;
397 396
398 qcom,local-pid = <0>; 397 qcom,local-pid = <0>;
399 qcom,remote-pid = <1>; 398 qcom,remote-pid = <1>;
400 399
401 hexagon_smp2p_out: master-kern 400 hexagon_smp2p_out: master-kernel {
402 qcom,entry-name = "mas 401 qcom,entry-name = "master-kernel";
403 402
404 #qcom,smem-state-cells 403 #qcom,smem-state-cells = <1>;
405 }; 404 };
406 405
407 hexagon_smp2p_in: slave-kernel 406 hexagon_smp2p_in: slave-kernel {
408 qcom,entry-name = "sla 407 qcom,entry-name = "slave-kernel";
409 408
410 interrupt-controller; 409 interrupt-controller;
411 #interrupt-cells = <2> 410 #interrupt-cells = <2>;
412 }; 411 };
413 }; 412 };
414 413
415 smp2p-wcnss { 414 smp2p-wcnss {
416 compatible = "qcom,smp2p"; 415 compatible = "qcom,smp2p";
417 qcom,smem = <451>, <431>; 416 qcom,smem = <451>, <431>;
418 417
419 interrupts = <GIC_SPI 143 IRQ_ 418 interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>;
420 419
421 mboxes = <&apcs1_mbox 18>; 420 mboxes = <&apcs1_mbox 18>;
422 421
423 qcom,local-pid = <0>; 422 qcom,local-pid = <0>;
424 qcom,remote-pid = <4>; 423 qcom,remote-pid = <4>;
425 424
426 wcnss_smp2p_in: slave-kernel { 425 wcnss_smp2p_in: slave-kernel {
427 qcom,entry-name = "sla 426 qcom,entry-name = "slave-kernel";
428 427
429 interrupt-controller; 428 interrupt-controller;
430 #interrupt-cells = <2> 429 #interrupt-cells = <2>;
431 }; 430 };
432 431
433 wcnss_smp2p_out: master-kernel 432 wcnss_smp2p_out: master-kernel {
434 qcom,entry-name = "mas 433 qcom,entry-name = "master-kernel";
435 434
436 #qcom,smem-state-cells 435 #qcom,smem-state-cells = <1>;
437 }; 436 };
438 }; 437 };
439 438
440 smsm { 439 smsm {
441 compatible = "qcom,smsm"; 440 compatible = "qcom,smsm";
442 441
443 #address-cells = <1>; 442 #address-cells = <1>;
444 #size-cells = <0>; 443 #size-cells = <0>;
445 444
446 mboxes = <0>, <&apcs1_mbox 13> !! 445 qcom,ipc-1 = <&apcs1_mbox 8 13>;
>> 446 qcom,ipc-3 = <&apcs1_mbox 8 19>;
447 447
448 apps_smsm: apps@0 { 448 apps_smsm: apps@0 {
449 reg = <0>; 449 reg = <0>;
450 450
451 #qcom,smem-state-cells 451 #qcom,smem-state-cells = <1>;
452 }; 452 };
453 453
454 hexagon_smsm: hexagon@1 { 454 hexagon_smsm: hexagon@1 {
455 reg = <1>; 455 reg = <1>;
456 interrupts = <GIC_SPI 456 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
457 457
458 interrupt-controller; 458 interrupt-controller;
459 #interrupt-cells = <2> 459 #interrupt-cells = <2>;
460 }; 460 };
461 461
462 wcnss_smsm: wcnss@6 { 462 wcnss_smsm: wcnss@6 {
463 reg = <6>; 463 reg = <6>;
464 interrupts = <GIC_SPI 464 interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>;
465 465
466 interrupt-controller; 466 interrupt-controller;
467 #interrupt-cells = <2> 467 #interrupt-cells = <2>;
468 }; 468 };
469 }; 469 };
470 470
471 soc: soc@0 { 471 soc: soc@0 {
472 compatible = "simple-bus"; 472 compatible = "simple-bus";
473 #address-cells = <1>; 473 #address-cells = <1>;
474 #size-cells = <1>; 474 #size-cells = <1>;
475 ranges = <0 0 0 0xffffffff>; 475 ranges = <0 0 0 0xffffffff>;
476 476
477 rng@22000 { 477 rng@22000 {
478 compatible = "qcom,prn 478 compatible = "qcom,prng";
479 reg = <0x00022000 0x20 479 reg = <0x00022000 0x200>;
480 clocks = <&gcc GCC_PRN 480 clocks = <&gcc GCC_PRNG_AHB_CLK>;
481 clock-names = "core"; 481 clock-names = "core";
482 }; 482 };
483 483
484 qfprom: qfprom@5c000 { 484 qfprom: qfprom@5c000 {
485 compatible = "qcom,msm 485 compatible = "qcom,msm8916-qfprom", "qcom,qfprom";
486 reg = <0x0005c000 0x10 486 reg = <0x0005c000 0x1000>;
487 #address-cells = <1>; 487 #address-cells = <1>;
488 #size-cells = <1>; 488 #size-cells = <1>;
489 489
490 tsens_base1: base1@a0 490 tsens_base1: base1@a0 {
491 reg = <0xa0 0x 491 reg = <0xa0 0x1>;
492 bits = <0 8>; 492 bits = <0 8>;
493 }; 493 };
494 494
495 tsens_s6_p1: s6-p1@a1 495 tsens_s6_p1: s6-p1@a1 {
496 reg = <0xa1 0x 496 reg = <0xa1 0x1>;
497 bits = <0 6>; 497 bits = <0 6>;
498 }; 498 };
499 499
500 tsens_s6_p2: s6-p2@a1 500 tsens_s6_p2: s6-p2@a1 {
501 reg = <0xa1 0x 501 reg = <0xa1 0x2>;
502 bits = <6 6>; 502 bits = <6 6>;
503 }; 503 };
504 504
505 tsens_s7_p1: s7-p1@a2 505 tsens_s7_p1: s7-p1@a2 {
506 reg = <0xa2 0x 506 reg = <0xa2 0x2>;
507 bits = <4 6>; 507 bits = <4 6>;
508 }; 508 };
509 509
510 tsens_s7_p2: s7-p2@a3 510 tsens_s7_p2: s7-p2@a3 {
511 reg = <0xa3 0x 511 reg = <0xa3 0x1>;
512 bits = <2 6>; 512 bits = <2 6>;
513 }; 513 };
514 514
515 tsens_s8_p1: s8-p1@a4 515 tsens_s8_p1: s8-p1@a4 {
516 reg = <0xa4 0x 516 reg = <0xa4 0x1>;
517 bits = <0 6>; 517 bits = <0 6>;
518 }; 518 };
519 519
520 tsens_s8_p2: s8-p2@a4 520 tsens_s8_p2: s8-p2@a4 {
521 reg = <0xa4 0x 521 reg = <0xa4 0x2>;
522 bits = <6 6>; 522 bits = <6 6>;
523 }; 523 };
524 524
525 tsens_s9_p1: s9-p1@a5 525 tsens_s9_p1: s9-p1@a5 {
526 reg = <0xa5 0x 526 reg = <0xa5 0x2>;
527 bits = <4 6>; 527 bits = <4 6>;
528 }; 528 };
529 529
530 tsens_s9_p2: s9-p2@a6 530 tsens_s9_p2: s9-p2@a6 {
531 reg = <0xa6 0x 531 reg = <0xa6 0x1>;
532 bits = <2 6>; 532 bits = <2 6>;
533 }; 533 };
534 534
535 tsens_base2: base2@a7 535 tsens_base2: base2@a7 {
536 reg = <0xa7 0x 536 reg = <0xa7 0x1>;
537 bits = <0 8>; 537 bits = <0 8>;
538 }; 538 };
539 539
540 tsens_mode: mode@d0 { 540 tsens_mode: mode@d0 {
541 reg = <0xd0 0x 541 reg = <0xd0 0x1>;
542 bits = <0 3>; 542 bits = <0 3>;
543 }; 543 };
544 544
545 tsens_s0_p1: s0-p1@d0 545 tsens_s0_p1: s0-p1@d0 {
546 reg = <0xd0 0x 546 reg = <0xd0 0x2>;
547 bits = <3 6>; 547 bits = <3 6>;
548 }; 548 };
549 549
550 tsens_s0_p2: s0-p1@d1 550 tsens_s0_p2: s0-p1@d1 {
551 reg = <0xd1 0x 551 reg = <0xd1 0x1>;
552 bits = <1 6>; 552 bits = <1 6>;
553 }; 553 };
554 554
555 tsens_s1_p1: s1-p1@d1 555 tsens_s1_p1: s1-p1@d1 {
556 reg = <0xd1 0x 556 reg = <0xd1 0x2>;
557 bits = <7 6>; 557 bits = <7 6>;
558 }; 558 };
559 559
560 tsens_s1_p2: s1-p2@d2 560 tsens_s1_p2: s1-p2@d2 {
561 reg = <0xd2 0x 561 reg = <0xd2 0x2>;
562 bits = <5 6>; 562 bits = <5 6>;
563 }; 563 };
564 564
565 tsens_s2_p1: s2-p1@d3 565 tsens_s2_p1: s2-p1@d3 {
566 reg = <0xd3 0x 566 reg = <0xd3 0x2>;
567 bits = <3 6>; 567 bits = <3 6>;
568 }; 568 };
569 569
570 tsens_s2_p2: s2-p2@d4 570 tsens_s2_p2: s2-p2@d4 {
571 reg = <0xd4 0x 571 reg = <0xd4 0x1>;
572 bits = <1 6>; 572 bits = <1 6>;
573 }; 573 };
574 574
575 tsens_s3_p1: s3-p1@d4 575 tsens_s3_p1: s3-p1@d4 {
576 reg = <0xd4 0x 576 reg = <0xd4 0x2>;
577 bits = <7 6>; 577 bits = <7 6>;
578 }; 578 };
579 579
580 tsens_s3_p2: s3-p2@d5 580 tsens_s3_p2: s3-p2@d5 {
581 reg = <0xd5 0x 581 reg = <0xd5 0x2>;
582 bits = <5 6>; 582 bits = <5 6>;
583 }; 583 };
584 584
585 tsens_s5_p1: s5-p1@d6 585 tsens_s5_p1: s5-p1@d6 {
586 reg = <0xd6 0x 586 reg = <0xd6 0x2>;
587 bits = <3 6>; 587 bits = <3 6>;
588 }; 588 };
589 589
590 tsens_s5_p2: s5-p2@d7 590 tsens_s5_p2: s5-p2@d7 {
591 reg = <0xd7 0x 591 reg = <0xd7 0x1>;
592 bits = <1 6>; 592 bits = <1 6>;
593 }; 593 };
594 }; 594 };
595 595
596 rpm_msg_ram: sram@60000 { 596 rpm_msg_ram: sram@60000 {
597 compatible = "qcom,rpm 597 compatible = "qcom,rpm-msg-ram";
598 reg = <0x00060000 0x80 598 reg = <0x00060000 0x8000>;
599 }; 599 };
600 600
601 bimc: interconnect@400000 { 601 bimc: interconnect@400000 {
602 compatible = "qcom,msm 602 compatible = "qcom,msm8939-bimc";
603 reg = <0x00400000 0x62 603 reg = <0x00400000 0x62000>;
>> 604 clock-names = "bus", "bus_a";
>> 605 clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
>> 606 <&rpmcc RPM_SMD_BIMC_A_CLK>;
604 #interconnect-cells = 607 #interconnect-cells = <1>;
605 }; 608 };
606 609
607 tsens: thermal-sensor@4a9000 { 610 tsens: thermal-sensor@4a9000 {
608 compatible = "qcom,msm 611 compatible = "qcom,msm8939-tsens", "qcom,tsens-v0_1";
609 reg = <0x004a9000 0x10 612 reg = <0x004a9000 0x1000>, /* TM */
610 <0x004a8000 0x10 613 <0x004a8000 0x1000>; /* SROT */
611 nvmem-cells = <&tsens_ 614 nvmem-cells = <&tsens_mode>,
612 <&tsens_ 615 <&tsens_base1>, <&tsens_base2>,
613 <&tsens_ 616 <&tsens_s0_p1>, <&tsens_s0_p2>,
614 <&tsens_ 617 <&tsens_s1_p1>, <&tsens_s1_p2>,
615 <&tsens_ 618 <&tsens_s2_p1>, <&tsens_s2_p2>,
616 <&tsens_ 619 <&tsens_s3_p1>, <&tsens_s3_p2>,
617 <&tsens_ 620 <&tsens_s5_p1>, <&tsens_s5_p2>,
618 <&tsens_ 621 <&tsens_s6_p1>, <&tsens_s6_p2>,
619 <&tsens_ 622 <&tsens_s7_p1>, <&tsens_s7_p2>,
620 <&tsens_ 623 <&tsens_s8_p1>, <&tsens_s8_p2>,
621 <&tsens_ 624 <&tsens_s9_p1>, <&tsens_s9_p2>;
622 nvmem-cell-names = "mo 625 nvmem-cell-names = "mode",
623 "ba 626 "base1", "base2",
624 "s0 627 "s0_p1", "s0_p2",
625 "s1 628 "s1_p1", "s1_p2",
626 "s2 629 "s2_p1", "s2_p2",
627 "s3 630 "s3_p1", "s3_p2",
628 "s5 631 "s5_p1", "s5_p2",
629 "s6 632 "s6_p1", "s6_p2",
630 "s7 633 "s7_p1", "s7_p2",
631 "s8 634 "s8_p1", "s8_p2",
632 "s9 635 "s9_p1", "s9_p2";
633 #qcom,sensors = <9>; 636 #qcom,sensors = <9>;
634 interrupts = <GIC_SPI 637 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
635 interrupt-names = "upl 638 interrupt-names = "uplow";
636 #thermal-sensor-cells 639 #thermal-sensor-cells = <1>;
637 }; 640 };
638 641
639 restart@4ab000 { 642 restart@4ab000 {
640 compatible = "qcom,psh 643 compatible = "qcom,pshold";
641 reg = <0x004ab000 0x4> 644 reg = <0x004ab000 0x4>;
642 }; 645 };
643 646
644 pcnoc: interconnect@500000 { 647 pcnoc: interconnect@500000 {
645 compatible = "qcom,msm 648 compatible = "qcom,msm8939-pcnoc";
646 reg = <0x00500000 0x11 649 reg = <0x00500000 0x11000>;
>> 650 clock-names = "bus", "bus_a";
>> 651 clocks = <&rpmcc RPM_SMD_PCNOC_CLK>,
>> 652 <&rpmcc RPM_SMD_PCNOC_A_CLK>;
647 #interconnect-cells = 653 #interconnect-cells = <1>;
648 }; 654 };
649 655
650 snoc: interconnect@580000 { 656 snoc: interconnect@580000 {
651 compatible = "qcom,msm 657 compatible = "qcom,msm8939-snoc";
652 reg = <0x00580000 0x14 658 reg = <0x00580000 0x14080>;
>> 659 clock-names = "bus", "bus_a";
>> 660 clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
>> 661 <&rpmcc RPM_SMD_SNOC_A_CLK>;
653 #interconnect-cells = 662 #interconnect-cells = <1>;
654 663
655 snoc_mm: interconnect- 664 snoc_mm: interconnect-snoc {
656 compatible = " 665 compatible = "qcom,msm8939-snoc-mm";
>> 666 clock-names = "bus", "bus_a";
>> 667 clocks = <&rpmcc RPM_SMD_SYSMMNOC_CLK>,
>> 668 <&rpmcc RPM_SMD_SYSMMNOC_A_CLK>;
657 #interconnect- 669 #interconnect-cells = <1>;
658 }; 670 };
659 }; 671 };
660 672
661 tlmm: pinctrl@1000000 { 673 tlmm: pinctrl@1000000 {
662 compatible = "qcom,msm 674 compatible = "qcom,msm8916-pinctrl";
663 reg = <0x01000000 0x30 675 reg = <0x01000000 0x300000>;
664 interrupts = <GIC_SPI 676 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
665 gpio-controller; 677 gpio-controller;
666 gpio-ranges = <&tlmm 0 678 gpio-ranges = <&tlmm 0 0 122>;
667 #gpio-cells = <2>; 679 #gpio-cells = <2>;
668 interrupt-controller; 680 interrupt-controller;
669 #interrupt-cells = <2> 681 #interrupt-cells = <2>;
670 682
671 blsp_i2c1_default: bls 683 blsp_i2c1_default: blsp-i2c1-default-state {
672 pins = "gpio2" 684 pins = "gpio2", "gpio3";
673 function = "bl 685 function = "blsp_i2c1";
674 drive-strength 686 drive-strength = <2>;
675 bias-disable; 687 bias-disable;
676 }; 688 };
677 689
678 blsp_i2c1_sleep: blsp- 690 blsp_i2c1_sleep: blsp-i2c1-sleep-state {
679 pins = "gpio2" 691 pins = "gpio2", "gpio3";
680 function = "gp 692 function = "gpio";
681 drive-strength 693 drive-strength = <2>;
682 bias-disable; 694 bias-disable;
683 }; 695 };
684 696
685 blsp_i2c2_default: bls 697 blsp_i2c2_default: blsp-i2c2-default-state {
686 pins = "gpio6" 698 pins = "gpio6", "gpio7";
687 function = "bl 699 function = "blsp_i2c2";
688 drive-strength 700 drive-strength = <2>;
689 bias-disable; 701 bias-disable;
690 }; 702 };
691 703
692 blsp_i2c2_sleep: blsp- 704 blsp_i2c2_sleep: blsp-i2c2-sleep-state {
693 pins = "gpio6" 705 pins = "gpio6", "gpio7";
694 function = "gp 706 function = "gpio";
695 drive-strength 707 drive-strength = <2>;
696 bias-disable; 708 bias-disable;
697 }; 709 };
698 710
699 blsp_i2c3_default: bls 711 blsp_i2c3_default: blsp-i2c3-default-state {
700 pins = "gpio10 712 pins = "gpio10", "gpio11";
701 function = "bl 713 function = "blsp_i2c3";
702 drive-strength 714 drive-strength = <2>;
703 bias-disable; 715 bias-disable;
704 }; 716 };
705 717
706 blsp_i2c3_sleep: blsp- 718 blsp_i2c3_sleep: blsp-i2c3-sleep-state {
707 pins = "gpio10 719 pins = "gpio10", "gpio11";
708 function = "gp 720 function = "gpio";
709 drive-strength 721 drive-strength = <2>;
710 bias-disable; 722 bias-disable;
711 }; 723 };
712 724
713 blsp_i2c4_default: bls 725 blsp_i2c4_default: blsp-i2c4-default-state {
714 pins = "gpio14 726 pins = "gpio14", "gpio15";
715 function = "bl 727 function = "blsp_i2c4";
716 drive-strength 728 drive-strength = <2>;
717 bias-disable; 729 bias-disable;
718 }; 730 };
719 731
720 blsp_i2c4_sleep: blsp- 732 blsp_i2c4_sleep: blsp-i2c4-sleep-state {
721 pins = "gpio14 733 pins = "gpio14", "gpio15";
722 function = "gp 734 function = "gpio";
723 drive-strength 735 drive-strength = <2>;
724 bias-disable; 736 bias-disable;
725 }; 737 };
726 738
727 blsp_i2c5_default: bls 739 blsp_i2c5_default: blsp-i2c5-default-state {
728 pins = "gpio18 740 pins = "gpio18", "gpio19";
729 function = "bl 741 function = "blsp_i2c5";
730 drive-strength 742 drive-strength = <2>;
731 bias-disable; 743 bias-disable;
732 }; 744 };
733 745
734 blsp_i2c5_sleep: blsp- 746 blsp_i2c5_sleep: blsp-i2c5-sleep-state {
735 pins = "gpio18 747 pins = "gpio18", "gpio19";
736 function = "gp 748 function = "gpio";
737 drive-strength 749 drive-strength = <2>;
738 bias-disable; 750 bias-disable;
739 }; 751 };
740 752
741 blsp_i2c6_default: bls 753 blsp_i2c6_default: blsp-i2c6-default-state {
742 pins = "gpio22 754 pins = "gpio22", "gpio23";
743 function = "bl 755 function = "blsp_i2c6";
744 drive-strength 756 drive-strength = <2>;
745 bias-disable; 757 bias-disable;
746 }; 758 };
747 759
748 blsp_i2c6_sleep: blsp- 760 blsp_i2c6_sleep: blsp-i2c6-sleep-state {
749 pins = "gpio22 761 pins = "gpio22", "gpio23";
750 function = "gp 762 function = "gpio";
751 drive-strength 763 drive-strength = <2>;
752 bias-disable; 764 bias-disable;
753 }; 765 };
754 766
755 blsp_spi1_default: bls 767 blsp_spi1_default: blsp-spi1-default-state {
756 spi-pins { 768 spi-pins {
757 pins = 769 pins = "gpio0", "gpio1", "gpio3";
758 functi 770 function = "blsp_spi1";
759 drive- 771 drive-strength = <12>;
760 bias-d 772 bias-disable;
761 }; 773 };
762 774
763 cs-pins { 775 cs-pins {
764 pins = 776 pins = "gpio2";
765 functi 777 function = "gpio";
766 drive- 778 drive-strength = <16>;
767 bias-d 779 bias-disable;
768 output 780 output-high;
769 }; 781 };
770 }; 782 };
771 783
772 blsp_spi1_sleep: blsp- 784 blsp_spi1_sleep: blsp-spi1-sleep-state {
773 pins = "gpio0" 785 pins = "gpio0", "gpio1", "gpio2", "gpio3";
774 function = "gp 786 function = "gpio";
775 drive-strength 787 drive-strength = <2>;
776 bias-pull-down 788 bias-pull-down;
777 }; 789 };
778 790
779 blsp_spi2_default: bls 791 blsp_spi2_default: blsp-spi2-default-state {
780 spi-pins { 792 spi-pins {
781 pins = 793 pins = "gpio4", "gpio5", "gpio7";
782 functi 794 function = "blsp_spi2";
783 drive- 795 drive-strength = <12>;
784 bias-d 796 bias-disable;
785 }; 797 };
786 798
787 cs-pins { 799 cs-pins {
788 pins = 800 pins = "gpio6";
789 functi 801 function = "gpio";
790 drive- 802 drive-strength = <16>;
791 bias-d 803 bias-disable;
792 output 804 output-high;
793 }; 805 };
794 }; 806 };
795 807
796 blsp_spi2_sleep: blsp- 808 blsp_spi2_sleep: blsp-spi2-sleep-state {
797 pins = "gpio4" 809 pins = "gpio4", "gpio5", "gpio6", "gpio7";
798 function = "gp 810 function = "gpio";
799 drive-strength 811 drive-strength = <2>;
800 bias-pull-down 812 bias-pull-down;
801 }; 813 };
802 814
803 blsp_spi3_default: bls 815 blsp_spi3_default: blsp-spi3-default-state {
804 spi-pins { 816 spi-pins {
805 pins = 817 pins = "gpio8", "gpio9", "gpio11";
806 functi 818 function = "blsp_spi3";
807 drive- 819 drive-strength = <12>;
808 bias-d 820 bias-disable;
809 }; 821 };
810 822
811 cs-pins { 823 cs-pins {
812 pins = 824 pins = "gpio10";
813 functi 825 function = "gpio";
814 drive- 826 drive-strength = <16>;
815 bias-d 827 bias-disable;
816 output 828 output-high;
817 }; 829 };
818 }; 830 };
819 831
820 blsp_spi3_sleep: blsp- 832 blsp_spi3_sleep: blsp-spi3-sleep-state {
821 pins = "gpio8" 833 pins = "gpio8", "gpio9", "gpio10", "gpio11";
822 function = "gp 834 function = "gpio";
823 drive-strength 835 drive-strength = <2>;
824 bias-pull-down 836 bias-pull-down;
825 }; 837 };
826 838
827 blsp_spi4_default: bls 839 blsp_spi4_default: blsp-spi4-default-state {
828 spi-pins { 840 spi-pins {
829 pins = 841 pins = "gpio12", "gpio13", "gpio15";
830 functi 842 function = "blsp_spi4";
831 drive- 843 drive-strength = <12>;
832 bias-d 844 bias-disable;
833 }; 845 };
834 846
835 cs-pins { 847 cs-pins {
836 pins = 848 pins = "gpio14";
837 functi 849 function = "gpio";
838 drive- 850 drive-strength = <16>;
839 bias-d 851 bias-disable;
840 output 852 output-high;
841 }; 853 };
842 }; 854 };
843 855
844 blsp_spi4_sleep: blsp- 856 blsp_spi4_sleep: blsp-spi4-sleep-state {
845 pins = "gpio12 857 pins = "gpio12", "gpio13", "gpio14", "gpio15";
846 function = "gp 858 function = "gpio";
847 drive-strength 859 drive-strength = <2>;
848 bias-pull-down 860 bias-pull-down;
849 }; 861 };
850 862
851 blsp_spi5_default: bls 863 blsp_spi5_default: blsp-spi5-default-state {
852 spi-pins { 864 spi-pins {
853 pins = 865 pins = "gpio16", "gpio17", "gpio19";
854 functi 866 function = "blsp_spi5";
855 drive- 867 drive-strength = <12>;
856 bias-d 868 bias-disable;
857 }; 869 };
858 870
859 cs-pins { 871 cs-pins {
860 pins = 872 pins = "gpio18";
861 functi 873 function = "gpio";
862 drive- 874 drive-strength = <16>;
863 bias-d 875 bias-disable;
864 output 876 output-high;
865 }; 877 };
866 }; 878 };
867 879
868 blsp_spi5_sleep: blsp- 880 blsp_spi5_sleep: blsp-spi5-sleep-state {
869 pins = "gpio16 881 pins = "gpio16", "gpio17", "gpio18", "gpio19";
870 function = "gp 882 function = "gpio";
871 drive-strength 883 drive-strength = <2>;
872 bias-pull-down 884 bias-pull-down;
873 }; 885 };
874 886
875 blsp_spi6_default: bls 887 blsp_spi6_default: blsp-spi6-default-state {
876 spi-pins { 888 spi-pins {
877 pins = 889 pins = "gpio20", "gpio21", "gpio23";
878 functi 890 function = "blsp_spi6";
879 drive- 891 drive-strength = <12>;
880 bias-d 892 bias-disable;
881 }; 893 };
882 894
883 cs-pins { 895 cs-pins {
884 pins = 896 pins = "gpio22";
885 functi 897 function = "gpio";
886 drive- 898 drive-strength = <16>;
887 bias-d 899 bias-disable;
888 output 900 output-high;
889 }; 901 };
890 }; 902 };
891 903
892 blsp_spi6_sleep: blsp- 904 blsp_spi6_sleep: blsp-spi6-sleep-state {
893 pins = "gpio20 905 pins = "gpio20", "gpio21", "gpio22", "gpio23";
894 function = "gp 906 function = "gpio";
895 drive-strength 907 drive-strength = <2>;
896 bias-pull-down 908 bias-pull-down;
897 }; 909 };
898 910
899 blsp_uart1_default: bl 911 blsp_uart1_default: blsp-uart1-default-state {
900 pins = "gpio0" 912 pins = "gpio0", "gpio1", "gpio2", "gpio3";
901 function = "bl 913 function = "blsp_uart1";
902 drive-strength 914 drive-strength = <16>;
903 bias-disable; 915 bias-disable;
904 }; 916 };
905 917
906 blsp_uart1_sleep: blsp 918 blsp_uart1_sleep: blsp-uart1-sleep-state {
907 pins = "gpio0" 919 pins = "gpio0", "gpio1", "gpio2", "gpio3";
908 function = "gp 920 function = "gpio";
909 drive-strength 921 drive-strength = <2>;
910 bias-pull-down 922 bias-pull-down;
911 }; 923 };
912 924
913 blsp_uart2_default: bl 925 blsp_uart2_default: blsp-uart2-default-state {
914 pins = "gpio4" 926 pins = "gpio4", "gpio5";
915 function = "bl 927 function = "blsp_uart2";
916 drive-strength 928 drive-strength = <16>;
917 bias-disable; 929 bias-disable;
918 }; 930 };
919 931
920 blsp_uart2_sleep: blsp 932 blsp_uart2_sleep: blsp-uart2-sleep-state {
921 pins = "gpio4" 933 pins = "gpio4", "gpio5";
922 function = "gp 934 function = "gpio";
923 drive-strength 935 drive-strength = <2>;
924 bias-pull-down 936 bias-pull-down;
925 }; 937 };
926 938
927 camera_front_default: 939 camera_front_default: camera-front-default-state {
928 pwdn-pins { 940 pwdn-pins {
929 pins = 941 pins = "gpio33";
930 functi 942 function = "gpio";
931 drive- 943 drive-strength = <16>;
932 bias-d 944 bias-disable;
933 }; 945 };
934 946
935 rst-pins { 947 rst-pins {
936 pins = 948 pins = "gpio28";
937 functi 949 function = "gpio";
938 drive- 950 drive-strength = <16>;
939 bias-d 951 bias-disable;
940 }; 952 };
941 953
942 mclk1-pins { 954 mclk1-pins {
943 pins = 955 pins = "gpio27";
944 functi 956 function = "cam_mclk1";
945 drive- 957 drive-strength = <16>;
946 bias-d 958 bias-disable;
947 }; 959 };
948 }; 960 };
949 961
950 camera_rear_default: c 962 camera_rear_default: camera-rear-default-state {
951 pwdn-pins { 963 pwdn-pins {
952 pins = 964 pins = "gpio34";
953 functi 965 function = "gpio";
954 drive- 966 drive-strength = <16>;
955 bias-d 967 bias-disable;
956 }; 968 };
957 969
958 rst-pins { 970 rst-pins {
959 pins = 971 pins = "gpio35";
960 functi 972 function = "gpio";
961 drive- 973 drive-strength = <16>;
962 bias-d 974 bias-disable;
963 }; 975 };
964 976
965 mclk0-pins { 977 mclk0-pins {
966 pins = 978 pins = "gpio26";
967 functi 979 function = "cam_mclk0";
968 drive- 980 drive-strength = <16>;
969 bias-d 981 bias-disable;
970 }; 982 };
971 }; 983 };
972 984
973 cci0_default: cci0-def 985 cci0_default: cci0-default-state {
974 pins = "gpio29 986 pins = "gpio29", "gpio30";
975 function = "cc 987 function = "cci_i2c";
976 drive-strength 988 drive-strength = <16>;
977 bias-disable; 989 bias-disable;
978 }; 990 };
979 991
980 cdc_dmic_default: cdc- 992 cdc_dmic_default: cdc-dmic-default-state {
981 clk-pins { 993 clk-pins {
982 pins = 994 pins = "gpio0";
983 functi 995 function = "dmic0_clk";
984 drive- 996 drive-strength = <8>;
985 }; 997 };
986 998
987 data-pins { 999 data-pins {
988 pins = 1000 pins = "gpio1";
989 functi 1001 function = "dmic0_data";
990 drive- 1002 drive-strength = <8>;
991 }; 1003 };
992 }; 1004 };
993 1005
994 cdc_dmic_sleep: cdc-dm 1006 cdc_dmic_sleep: cdc-dmic-sleep-state {
995 clk-pins { 1007 clk-pins {
996 pins = 1008 pins = "gpio0";
997 functi 1009 function = "dmic0_clk";
998 drive- 1010 drive-strength = <2>;
999 bias-d 1011 bias-disable;
1000 }; 1012 };
1001 1013
1002 data-pins { 1014 data-pins {
1003 pins 1015 pins = "gpio1";
1004 funct 1016 function = "dmic0_data";
1005 drive 1017 drive-strength = <2>;
1006 bias- 1018 bias-disable;
1007 }; 1019 };
1008 }; 1020 };
1009 1021
1010 cdc_pdm_default: cdc- 1022 cdc_pdm_default: cdc-pdm-default-state {
1011 pins = "gpio6 1023 pins = "gpio63", "gpio64", "gpio65", "gpio66",
1012 "gpio6 1024 "gpio67", "gpio68";
1013 function = "c 1025 function = "cdc_pdm0";
1014 drive-strengt 1026 drive-strength = <8>;
1015 bias-disable; 1027 bias-disable;
1016 }; 1028 };
1017 1029
1018 cdc_pdm_sleep: cdc-pd 1030 cdc_pdm_sleep: cdc-pdm-sleep-state {
1019 pins = "gpio6 1031 pins = "gpio63", "gpio64", "gpio65", "gpio66",
1020 "gpio6 1032 "gpio67", "gpio68";
1021 function = "c 1033 function = "cdc_pdm0";
1022 drive-strengt 1034 drive-strength = <2>;
1023 bias-pull-dow 1035 bias-pull-down;
1024 }; 1036 };
1025 1037
1026 pri_mi2s_default: mi2 1038 pri_mi2s_default: mi2s-pri-default-state {
1027 pins = "gpio1 1039 pins = "gpio113", "gpio114", "gpio115", "gpio116";
1028 function = "p 1040 function = "pri_mi2s";
1029 drive-strengt 1041 drive-strength = <8>;
1030 bias-disable; 1042 bias-disable;
1031 }; 1043 };
1032 1044
1033 pri_mi2s_sleep: mi2s- 1045 pri_mi2s_sleep: mi2s-pri-sleep-state {
1034 pins = "gpio1 1046 pins = "gpio113", "gpio114", "gpio115", "gpio116";
1035 function = "p 1047 function = "pri_mi2s";
1036 drive-strengt 1048 drive-strength = <2>;
1037 bias-disable; 1049 bias-disable;
1038 }; 1050 };
1039 1051
1040 pri_mi2s_mclk_default 1052 pri_mi2s_mclk_default: mi2s-pri-mclk-default-state {
1041 pins = "gpio1 1053 pins = "gpio116";
1042 function = "p 1054 function = "pri_mi2s";
1043 drive-strengt 1055 drive-strength = <8>;
1044 bias-disable; 1056 bias-disable;
1045 }; 1057 };
1046 1058
1047 pri_mi2s_mclk_sleep: 1059 pri_mi2s_mclk_sleep: mi2s-pri-mclk-sleep-state {
1048 pins = "gpio1 1060 pins = "gpio116";
1049 function = "p 1061 function = "pri_mi2s";
1050 drive-strengt 1062 drive-strength = <2>;
1051 bias-disable; 1063 bias-disable;
1052 }; 1064 };
1053 1065
1054 pri_mi2s_ws_default: 1066 pri_mi2s_ws_default: mi2s-pri-ws-default-state {
1055 pins = "gpio1 1067 pins = "gpio110";
1056 function = "p 1068 function = "pri_mi2s_ws";
1057 drive-strengt 1069 drive-strength = <8>;
1058 bias-disable; 1070 bias-disable;
1059 }; 1071 };
1060 1072
1061 pri_mi2s_ws_sleep: mi 1073 pri_mi2s_ws_sleep: mi2s-pri-ws-sleep-state {
1062 pins = "gpio1 1074 pins = "gpio110";
1063 function = "p 1075 function = "pri_mi2s_ws";
1064 drive-strengt 1076 drive-strength = <2>;
1065 bias-disable; 1077 bias-disable;
1066 }; 1078 };
1067 1079
1068 sec_mi2s_default: mi2 1080 sec_mi2s_default: mi2s-sec-default-state {
1069 pins = "gpio1 1081 pins = "gpio112", "gpio117", "gpio118", "gpio119";
1070 function = "s 1082 function = "sec_mi2s";
1071 drive-strengt 1083 drive-strength = <8>;
1072 bias-disable; 1084 bias-disable;
1073 }; 1085 };
1074 1086
1075 sec_mi2s_sleep: mi2s- 1087 sec_mi2s_sleep: mi2s-sec-sleep-state {
1076 pins = "gpio1 1088 pins = "gpio112", "gpio117", "gpio118", "gpio119";
1077 function = "s 1089 function = "sec_mi2s";
1078 drive-strengt 1090 drive-strength = <2>;
1079 bias-disable; 1091 bias-disable;
1080 }; 1092 };
1081 1093
1082 sdc1_default: sdc1-de 1094 sdc1_default: sdc1-default-state {
1083 clk-pins { 1095 clk-pins {
1084 pins 1096 pins = "sdc1_clk";
1085 bias- 1097 bias-disable;
1086 drive 1098 drive-strength = <16>;
1087 }; 1099 };
1088 1100
1089 cmd-pins { 1101 cmd-pins {
1090 pins 1102 pins = "sdc1_cmd";
1091 bias- 1103 bias-pull-up;
1092 drive 1104 drive-strength = <10>;
1093 }; 1105 };
1094 1106
1095 data-pins { 1107 data-pins {
1096 pins 1108 pins = "sdc1_data";
1097 bias- 1109 bias-pull-up;
1098 drive 1110 drive-strength = <10>;
1099 }; 1111 };
1100 }; 1112 };
1101 1113
1102 sdc1_sleep: sdc1-slee 1114 sdc1_sleep: sdc1-sleep-state {
1103 clk-pins { 1115 clk-pins {
1104 pins 1116 pins = "sdc1_clk";
1105 bias- 1117 bias-disable;
1106 drive 1118 drive-strength = <2>;
1107 }; 1119 };
1108 1120
1109 cmd-pins { 1121 cmd-pins {
1110 pins 1122 pins = "sdc1_cmd";
1111 bias- 1123 bias-pull-up;
1112 drive 1124 drive-strength = <2>;
1113 }; 1125 };
1114 1126
1115 data-pins { 1127 data-pins {
1116 pins 1128 pins = "sdc1_data";
1117 bias- 1129 bias-pull-up;
1118 drive 1130 drive-strength = <2>;
1119 }; 1131 };
1120 }; 1132 };
1121 1133
1122 sdc2_default: sdc2-de 1134 sdc2_default: sdc2-default-state {
1123 clk-pins { 1135 clk-pins {
1124 pins 1136 pins = "sdc2_clk";
1125 bias- 1137 bias-disable;
1126 drive 1138 drive-strength = <16>;
1127 }; 1139 };
1128 1140
1129 cmd-pins { 1141 cmd-pins {
1130 pins 1142 pins = "sdc2_cmd";
1131 bias- 1143 bias-pull-up;
1132 drive 1144 drive-strength = <10>;
1133 }; 1145 };
1134 1146
1135 data-pins { 1147 data-pins {
1136 pins 1148 pins = "sdc2_data";
1137 bias- 1149 bias-pull-up;
1138 drive 1150 drive-strength = <10>;
1139 }; 1151 };
1140 }; 1152 };
1141 1153
1142 sdc2_sleep: sdc2-slee 1154 sdc2_sleep: sdc2-sleep-state {
1143 clk-pins { 1155 clk-pins {
1144 pins 1156 pins = "sdc2_clk";
1145 bias- 1157 bias-disable;
1146 drive 1158 drive-strength = <2>;
1147 }; 1159 };
1148 1160
1149 cmd-pins { 1161 cmd-pins {
1150 pins 1162 pins = "sdc2_cmd";
1151 bias- 1163 bias-pull-up;
1152 drive 1164 drive-strength = <2>;
1153 }; 1165 };
1154 1166
1155 data-pins { 1167 data-pins {
1156 pins 1168 pins = "sdc2_data";
1157 bias- 1169 bias-pull-up;
1158 drive 1170 drive-strength = <2>;
1159 }; 1171 };
1160 }; 1172 };
1161 1173
1162 wcss_wlan_default: wc 1174 wcss_wlan_default: wcss-wlan-default-state {
1163 pins = "gpio4 1175 pins = "gpio40", "gpio41", "gpio42", "gpio43", "gpio44";
1164 function = "w 1176 function = "wcss_wlan";
1165 drive-strengt 1177 drive-strength = <6>;
1166 bias-pull-up; 1178 bias-pull-up;
1167 }; 1179 };
1168 }; 1180 };
1169 1181
1170 gcc: clock-controller@1800000 1182 gcc: clock-controller@1800000 {
1171 compatible = "qcom,gc 1183 compatible = "qcom,gcc-msm8939";
1172 reg = <0x01800000 0x8 1184 reg = <0x01800000 0x80000>;
1173 clocks = <&rpmcc RPM_ 1185 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
1174 <&sleep_clk> 1186 <&sleep_clk>,
1175 <&mdss_dsi0_ 1187 <&mdss_dsi0_phy 1>,
1176 <&mdss_dsi0_ 1188 <&mdss_dsi0_phy 0>,
1177 <0>, 1189 <0>,
1178 <0>, 1190 <0>,
1179 <0>; 1191 <0>;
1180 clock-names = "xo", 1192 clock-names = "xo",
1181 "sleep_ 1193 "sleep_clk",
1182 "dsi0pl 1194 "dsi0pll",
1183 "dsi0pl 1195 "dsi0pllbyte",
1184 "ext_mc 1196 "ext_mclk",
1185 "ext_pr 1197 "ext_pri_i2s",
1186 "ext_se 1198 "ext_sec_i2s";
1187 #clock-cells = <1>; 1199 #clock-cells = <1>;
1188 #reset-cells = <1>; 1200 #reset-cells = <1>;
1189 #power-domain-cells = 1201 #power-domain-cells = <1>;
1190 }; 1202 };
1191 1203
1192 tcsr_mutex: hwlock@1905000 { 1204 tcsr_mutex: hwlock@1905000 {
1193 compatible = "qcom,tc 1205 compatible = "qcom,tcsr-mutex";
1194 reg = <0x01905000 0x2 1206 reg = <0x01905000 0x20000>;
1195 #hwlock-cells = <1>; 1207 #hwlock-cells = <1>;
1196 }; 1208 };
1197 1209
1198 tcsr: syscon@1937000 { 1210 tcsr: syscon@1937000 {
1199 compatible = "qcom,tc 1211 compatible = "qcom,tcsr-msm8916", "syscon";
1200 reg = <0x01937000 0x3 1212 reg = <0x01937000 0x30000>;
1201 }; 1213 };
1202 1214
1203 mdss: display-subsystem@1a000 1215 mdss: display-subsystem@1a00000 {
1204 compatible = "qcom,md 1216 compatible = "qcom,mdss";
1205 reg = <0x01a00000 0x1 1217 reg = <0x01a00000 0x1000>,
1206 <0x01ac8000 0x3 1218 <0x01ac8000 0x3000>;
1207 reg-names = "mdss_phy 1219 reg-names = "mdss_phys", "vbif_phys";
1208 1220
1209 interrupts = <GIC_SPI 1221 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1210 interrupt-controller; 1222 interrupt-controller;
1211 1223
1212 clocks = <&gcc GCC_MD 1224 clocks = <&gcc GCC_MDSS_AHB_CLK>,
1213 <&gcc GCC_MD 1225 <&gcc GCC_MDSS_AXI_CLK>,
1214 <&gcc GCC_MD 1226 <&gcc GCC_MDSS_VSYNC_CLK>;
1215 clock-names = "iface" 1227 clock-names = "iface",
1216 "bus", 1228 "bus",
1217 "vsync" 1229 "vsync";
1218 1230
1219 power-domains = <&gcc 1231 power-domains = <&gcc MDSS_GDSC>;
1220 1232
1221 #address-cells = <1>; 1233 #address-cells = <1>;
1222 #size-cells = <1>; 1234 #size-cells = <1>;
1223 #interrupt-cells = <1 1235 #interrupt-cells = <1>;
1224 ranges; 1236 ranges;
1225 1237
1226 status = "disabled"; 1238 status = "disabled";
1227 1239
1228 mdss_mdp: display-con 1240 mdss_mdp: display-controller@1a01000 {
1229 compatible = 1241 compatible = "qcom,mdp5";
1230 reg = <0x01a0 1242 reg = <0x01a01000 0x89000>;
1231 reg-names = " 1243 reg-names = "mdp_phys";
1232 1244
1233 interrupt-par 1245 interrupt-parent = <&mdss>;
1234 interrupts = 1246 interrupts = <0>;
1235 1247
1236 clocks = <&gc 1248 clocks = <&gcc GCC_MDSS_AHB_CLK>,
1237 <&gc 1249 <&gcc GCC_MDSS_AXI_CLK>,
1238 <&gc 1250 <&gcc GCC_MDSS_MDP_CLK>,
1239 <&gc 1251 <&gcc GCC_MDSS_VSYNC_CLK>;
1240 clock-names = 1252 clock-names = "iface",
1241 1253 "bus",
1242 1254 "core",
1243 1255 "vsync";
1244 1256
1245 iommus = <&ap 1257 iommus = <&apps_iommu 4>;
1246 1258
1247 interconnects 1259 interconnects = <&snoc_mm MASTER_MDP_PORT0 &bimc SLAVE_EBI_CH0>,
1248 1260 <&snoc_mm MASTER_MDP_PORT1 &bimc SLAVE_EBI_CH0>;
1249 interconnect- 1261 interconnect-names = "mdp0-mem", "mdp1-mem";
1250 1262
1251 ports { 1263 ports {
1252 #addr 1264 #address-cells = <1>;
1253 #size 1265 #size-cells = <0>;
1254 1266
1255 port@ 1267 port@0 {
1256 1268 reg = <0>;
1257 1269 mdss_mdp_intf1_out: endpoint {
1258 1270 remote-endpoint = <&mdss_dsi0_in>;
1259 1271 };
1260 }; 1272 };
1261 1273
1262 port@ 1274 port@1 {
1263 1275 reg = <1>;
1264 1276 mdss_mdp_intf2_out: endpoint {
1265 1277 remote-endpoint = <&mdss_dsi1_in>;
1266 1278 };
1267 }; 1279 };
1268 }; 1280 };
1269 }; 1281 };
1270 1282
1271 mdss_dsi0: dsi@1a9800 1283 mdss_dsi0: dsi@1a98000 {
1272 compatible = 1284 compatible = "qcom,msm8916-dsi-ctrl",
1273 1285 "qcom,mdss-dsi-ctrl";
1274 reg = <0x01a9 1286 reg = <0x01a98000 0x25c>;
1275 reg-names = " 1287 reg-names = "dsi_ctrl";
1276 1288
1277 interrupt-par 1289 interrupt-parent = <&mdss>;
1278 interrupts = 1290 interrupts = <4>;
1279 1291
1280 clocks = <&gc 1292 clocks = <&gcc GCC_MDSS_MDP_CLK>,
1281 <&gc 1293 <&gcc GCC_MDSS_AHB_CLK>,
1282 <&gc 1294 <&gcc GCC_MDSS_AXI_CLK>,
1283 <&gc 1295 <&gcc GCC_MDSS_BYTE0_CLK>,
1284 <&gc 1296 <&gcc GCC_MDSS_PCLK0_CLK>,
1285 <&gc 1297 <&gcc GCC_MDSS_ESC0_CLK>;
1286 clock-names = 1298 clock-names = "mdp_core",
1287 1299 "iface",
1288 1300 "bus",
1289 1301 "byte",
1290 1302 "pixel",
1291 1303 "core";
1292 assigned-cloc 1304 assigned-clocks = <&gcc BYTE0_CLK_SRC>,
1293 1305 <&gcc PCLK0_CLK_SRC>;
1294 assigned-cloc 1306 assigned-clock-parents = <&mdss_dsi0_phy 0>,
1295 1307 <&mdss_dsi0_phy 1>;
1296 1308
1297 phys = <&mdss 1309 phys = <&mdss_dsi0_phy>;
1298 status = "dis 1310 status = "disabled";
1299 1311
1300 #address-cell 1312 #address-cells = <1>;
1301 #size-cells = 1313 #size-cells = <0>;
1302 1314
1303 ports { 1315 ports {
1304 #addr 1316 #address-cells = <1>;
1305 #size 1317 #size-cells = <0>;
1306 1318
1307 port@ 1319 port@0 {
1308 1320 reg = <0>;
1309 1321 mdss_dsi0_in: endpoint {
1310 1322 remote-endpoint = <&mdss_mdp_intf1_out>;
1311 1323 };
1312 }; 1324 };
1313 1325
1314 port@ 1326 port@1 {
1315 1327 reg = <1>;
1316 1328 mdss_dsi0_out: endpoint {
1317 1329 };
1318 }; 1330 };
1319 }; 1331 };
1320 }; 1332 };
1321 1333
1322 mdss_dsi0_phy: phy@1a 1334 mdss_dsi0_phy: phy@1a98300 {
1323 compatible = 1335 compatible = "qcom,dsi-phy-28nm-lp";
1324 reg = <0x01a9 1336 reg = <0x01a98300 0xd4>,
1325 <0x01a9 1337 <0x01a98500 0x280>,
1326 <0x01a9 1338 <0x01a98780 0x30>;
1327 reg-names = " 1339 reg-names = "dsi_pll",
1328 " 1340 "dsi_phy",
1329 " 1341 "dsi_phy_regulator";
1330 1342
1331 clocks = <&gc 1343 clocks = <&gcc GCC_MDSS_AHB_CLK>,
1332 <&rp 1344 <&rpmcc RPM_SMD_XO_CLK_SRC>;
1333 clock-names = 1345 clock-names = "iface", "ref";
1334 1346
1335 #clock-cells 1347 #clock-cells = <1>;
1336 #phy-cells = 1348 #phy-cells = <0>;
1337 status = "dis 1349 status = "disabled";
1338 }; 1350 };
1339 1351
1340 mdss_dsi1: dsi@1aa000 1352 mdss_dsi1: dsi@1aa0000 {
1341 compatible = 1353 compatible = "qcom,msm8916-dsi-ctrl",
1342 1354 "qcom,mdss-dsi-ctrl";
1343 reg = <0x01aa 1355 reg = <0x01aa0000 0x25c>;
1344 reg-names = " 1356 reg-names = "dsi_ctrl";
1345 1357
1346 interrupt-par 1358 interrupt-parent = <&mdss>;
1347 interrupts = 1359 interrupts = <5>;
1348 1360
1349 clocks = <&gc 1361 clocks = <&gcc GCC_MDSS_MDP_CLK>,
1350 <&gc 1362 <&gcc GCC_MDSS_AHB_CLK>,
1351 <&gc 1363 <&gcc GCC_MDSS_AXI_CLK>,
1352 <&gc 1364 <&gcc GCC_MDSS_BYTE1_CLK>,
1353 <&gc 1365 <&gcc GCC_MDSS_PCLK1_CLK>,
1354 <&gc 1366 <&gcc GCC_MDSS_ESC1_CLK>;
1355 clock-names = 1367 clock-names = "mdp_core",
1356 1368 "iface",
1357 1369 "bus",
1358 1370 "byte",
1359 1371 "pixel",
1360 1372 "core";
1361 assigned-cloc 1373 assigned-clocks = <&gcc BYTE1_CLK_SRC>,
1362 1374 <&gcc PCLK1_CLK_SRC>;
1363 assigned-cloc 1375 assigned-clock-parents = <&mdss_dsi0_phy 0>,
1364 1376 <&mdss_dsi0_phy 1>;
1365 phys = <&mdss 1377 phys = <&mdss_dsi1_phy>;
1366 status = "dis 1378 status = "disabled";
1367 1379
1368 ports { 1380 ports {
1369 #addr 1381 #address-cells = <1>;
1370 #size 1382 #size-cells = <0>;
1371 1383
1372 port@ 1384 port@0 {
1373 1385 reg = <0>;
1374 1386 mdss_dsi1_in: endpoint {
1375 1387 remote-endpoint = <&mdss_mdp_intf2_out>;
1376 1388 };
1377 }; 1389 };
1378 1390
1379 port@ 1391 port@1 {
1380 1392 reg = <1>;
1381 1393 mdss_dsi1_out: endpoint {
1382 1394 };
1383 }; 1395 };
1384 }; 1396 };
1385 }; 1397 };
1386 1398
1387 mdss_dsi1_phy: phy@1a 1399 mdss_dsi1_phy: phy@1aa0300 {
1388 compatible = 1400 compatible = "qcom,dsi-phy-28nm-lp";
1389 reg = <0x01aa 1401 reg = <0x01aa0300 0xd4>,
1390 <0x01aa 1402 <0x01aa0500 0x280>,
1391 <0x01aa 1403 <0x01aa0780 0x30>;
1392 reg-names = " 1404 reg-names = "dsi_pll",
1393 " 1405 "dsi_phy",
1394 " 1406 "dsi_phy_regulator";
1395 1407
1396 clocks = <&gc 1408 clocks = <&gcc GCC_MDSS_AHB_CLK>,
1397 <&rp 1409 <&rpmcc RPM_SMD_XO_CLK_SRC>;
1398 clock-names = 1410 clock-names = "iface", "ref";
1399 1411
1400 #clock-cells 1412 #clock-cells = <1>;
1401 #phy-cells = 1413 #phy-cells = <0>;
1402 status = "dis 1414 status = "disabled";
1403 }; 1415 };
1404 }; 1416 };
1405 1417
1406 gpu: gpu@1c00000 { 1418 gpu: gpu@1c00000 {
1407 compatible = "qcom,ad 1419 compatible = "qcom,adreno-405.0", "qcom,adreno";
1408 reg = <0x01c00000 0x1 1420 reg = <0x01c00000 0x10000>;
1409 reg-names = "kgsl_3d0 1421 reg-names = "kgsl_3d0_reg_memory";
1410 interrupts = <GIC_SPI 1422 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
1411 interrupt-names = "kg 1423 interrupt-names = "kgsl_3d0_irq";
1412 clock-names = "core", 1424 clock-names = "core",
1413 "iface" 1425 "iface",
1414 "mem", 1426 "mem",
1415 "mem_if 1427 "mem_iface",
1416 "alt_me 1428 "alt_mem_iface",
1417 "gfx3d" 1429 "gfx3d",
1418 "rbbmti 1430 "rbbmtimer";
1419 clocks = <&gcc GCC_OX 1431 clocks = <&gcc GCC_OXILI_GFX3D_CLK>,
1420 <&gcc GCC_OX 1432 <&gcc GCC_OXILI_AHB_CLK>,
1421 <&gcc GCC_OX 1433 <&gcc GCC_OXILI_GMEM_CLK>,
1422 <&gcc GCC_BI 1434 <&gcc GCC_BIMC_GFX_CLK>,
1423 <&gcc GCC_BI 1435 <&gcc GCC_BIMC_GPU_CLK>,
1424 <&gcc GFX3D_ 1436 <&gcc GFX3D_CLK_SRC>,
1425 <&gcc GCC_OX 1437 <&gcc GCC_OXILI_TIMER_CLK>;
1426 power-domains = <&gcc 1438 power-domains = <&gcc OXILI_GDSC>;
1427 operating-points-v2 = 1439 operating-points-v2 = <&opp_table>;
1428 iommus = <&gpu_iommu 1440 iommus = <&gpu_iommu 1>, <&gpu_iommu 2>;
1429 #cooling-cells = <2>; <<
1430 <<
1431 status = "disabled"; 1441 status = "disabled";
1432 1442
1433 opp_table: opp-table 1443 opp_table: opp-table {
1434 compatible = 1444 compatible = "operating-points-v2";
1435 1445
1436 opp-550000000 1446 opp-550000000 {
1437 opp-h 1447 opp-hz = /bits/ 64 <550000000>;
1438 }; 1448 };
1439 1449
1440 opp-465000000 1450 opp-465000000 {
1441 opp-h 1451 opp-hz = /bits/ 64 <465000000>;
1442 }; 1452 };
1443 1453
1444 opp-400000000 1454 opp-400000000 {
1445 opp-h 1455 opp-hz = /bits/ 64 <400000000>;
1446 }; 1456 };
1447 1457
1448 opp-220000000 1458 opp-220000000 {
1449 opp-h 1459 opp-hz = /bits/ 64 <220000000>;
1450 }; 1460 };
1451 1461
1452 opp-19200000 1462 opp-19200000 {
1453 opp-h 1463 opp-hz = /bits/ 64 <19200000>;
1454 }; 1464 };
1455 }; 1465 };
1456 }; 1466 };
1457 1467
1458 apps_iommu: iommu@1ef0000 { 1468 apps_iommu: iommu@1ef0000 {
1459 compatible = "qcom,ms 1469 compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
1460 reg = <0x01ef0000 0x3 1470 reg = <0x01ef0000 0x3000>;
1461 ranges = <0 0x01e2000 1471 ranges = <0 0x01e20000 0x20000>;
1462 clocks = <&gcc GCC_SM 1472 clocks = <&gcc GCC_SMMU_CFG_CLK>,
1463 <&gcc GCC_AP 1473 <&gcc GCC_APSS_TCU_CLK>;
1464 clock-names = "iface" 1474 clock-names = "iface", "bus";
1465 #address-cells = <1>; 1475 #address-cells = <1>;
1466 #size-cells = <1>; 1476 #size-cells = <1>;
1467 #iommu-cells = <1>; 1477 #iommu-cells = <1>;
1468 qcom,iommu-secure-id 1478 qcom,iommu-secure-id = <17>;
1469 1479
1470 /* mdp_0: */ 1480 /* mdp_0: */
1471 iommu-ctx@4000 { 1481 iommu-ctx@4000 {
1472 compatible = 1482 compatible = "qcom,msm-iommu-v1-ns";
1473 reg = <0x4000 1483 reg = <0x4000 0x1000>;
1474 interrupts = 1484 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
1475 }; 1485 };
1476 1486
1477 /* venus_ns: */ 1487 /* venus_ns: */
1478 iommu-ctx@5000 { 1488 iommu-ctx@5000 {
1479 compatible = 1489 compatible = "qcom,msm-iommu-v1-sec";
1480 reg = <0x5000 1490 reg = <0x5000 0x1000>;
1481 interrupts = 1491 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
1482 }; 1492 };
1483 }; 1493 };
1484 1494
1485 gpu_iommu: iommu@1f08000 { 1495 gpu_iommu: iommu@1f08000 {
1486 compatible = "qcom,ms 1496 compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
1487 ranges = <0 0x1f08000 1497 ranges = <0 0x1f08000 0x10000>;
1488 clocks = <&gcc GCC_SM 1498 clocks = <&gcc GCC_SMMU_CFG_CLK>,
1489 <&gcc GCC_GF 1499 <&gcc GCC_GFX_TCU_CLK>,
1490 <&gcc GCC_GF 1500 <&gcc GCC_GFX_TBU_CLK>;
1491 clock-names = "iface" 1501 clock-names = "iface", "bus", "tbu";
1492 #address-cells = <1>; 1502 #address-cells = <1>;
1493 #size-cells = <1>; 1503 #size-cells = <1>;
1494 #iommu-cells = <1>; 1504 #iommu-cells = <1>;
1495 qcom,iommu-secure-id 1505 qcom,iommu-secure-id = <18>;
1496 1506
1497 /* gfx3d_user: */ 1507 /* gfx3d_user: */
1498 iommu-ctx@1000 { 1508 iommu-ctx@1000 {
1499 compatible = 1509 compatible = "qcom,msm-iommu-v1-ns";
1500 reg = <0x1000 1510 reg = <0x1000 0x1000>;
1501 interrupts = 1511 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
1502 }; 1512 };
1503 1513
1504 /* gfx3d_priv: */ 1514 /* gfx3d_priv: */
1505 iommu-ctx@2000 { 1515 iommu-ctx@2000 {
1506 compatible = 1516 compatible = "qcom,msm-iommu-v1-ns";
1507 reg = <0x2000 1517 reg = <0x2000 0x1000>;
1508 interrupts = 1518 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
1509 }; 1519 };
1510 }; 1520 };
1511 1521
1512 spmi_bus: spmi@200f000 { 1522 spmi_bus: spmi@200f000 {
1513 compatible = "qcom,sp 1523 compatible = "qcom,spmi-pmic-arb";
1514 reg = <0x0200f000 0x0 1524 reg = <0x0200f000 0x001000>,
1515 <0x02400000 0x4 1525 <0x02400000 0x400000>,
1516 <0x02c00000 0x4 1526 <0x02c00000 0x400000>,
1517 <0x03800000 0x2 1527 <0x03800000 0x200000>,
1518 <0x0200a000 0x0 1528 <0x0200a000 0x002100>;
1519 reg-names = "core", " 1529 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1520 interrupt-names = "pe 1530 interrupt-names = "periph_irq";
1521 interrupts = <GIC_SPI 1531 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
1522 qcom,ee = <0>; 1532 qcom,ee = <0>;
1523 qcom,channel = <0>; 1533 qcom,channel = <0>;
1524 #address-cells = <2>; 1534 #address-cells = <2>;
1525 #size-cells = <0>; 1535 #size-cells = <0>;
1526 interrupt-controller; 1536 interrupt-controller;
1527 #interrupt-cells = <4 1537 #interrupt-cells = <4>;
1528 }; 1538 };
1529 1539
1530 bam_dmux_dma: dma-controller@ <<
1531 compatible = "qcom,ba <<
1532 reg = <0x04044000 0x1 <<
1533 interrupts = <GIC_SPI <<
1534 #dma-cells = <1>; <<
1535 qcom,ee = <0>; <<
1536 <<
1537 num-channels = <6>; <<
1538 qcom,num-ees = <1>; <<
1539 qcom,powered-remotely <<
1540 <<
1541 status = "disabled"; <<
1542 }; <<
1543 <<
1544 mpss: remoteproc@4080000 { 1540 mpss: remoteproc@4080000 {
1545 compatible = "qcom,ms 1541 compatible = "qcom,msm8916-mss-pil";
1546 reg = <0x04080000 0x1 1542 reg = <0x04080000 0x100>, <0x04020000 0x040>;
1547 reg-names = "qdsp6", 1543 reg-names = "qdsp6", "rmb";
1548 interrupts-extended = 1544 interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>,
1549 1545 <&hexagon_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1550 1546 <&hexagon_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1551 1547 <&hexagon_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1552 1548 <&hexagon_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1553 interrupt-names = "wd 1549 interrupt-names = "wdog",
1554 "fa 1550 "fatal",
1555 "re 1551 "ready",
1556 "ha 1552 "handover",
1557 "st 1553 "stop-ack";
1558 clocks = <&gcc GCC_MS 1554 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
1559 <&gcc GCC_MS 1555 <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>,
1560 <&gcc GCC_BO 1556 <&gcc GCC_BOOT_ROM_AHB_CLK>,
1561 <&rpmcc RPM_ 1557 <&rpmcc RPM_SMD_XO_CLK_SRC>;
1562 clock-names = "iface" 1558 clock-names = "iface",
1563 "bus", 1559 "bus",
1564 "mem", 1560 "mem",
1565 "xo"; 1561 "xo";
1566 power-domains = <&rpm 1562 power-domains = <&rpmpd MSM8939_VDDMDCX>,
1567 <&rpm 1563 <&rpmpd MSM8939_VDDMX>;
1568 power-domain-names = 1564 power-domain-names = "cx", "mx";
1569 qcom,smem-states = <& 1565 qcom,smem-states = <&hexagon_smp2p_out 0>;
1570 qcom,smem-state-names 1566 qcom,smem-state-names = "stop";
1571 resets = <&scm 0>; 1567 resets = <&scm 0>;
1572 reset-names = "mss_re 1568 reset-names = "mss_restart";
1573 qcom,halt-regs = <&tc 1569 qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>;
1574 status = "disabled"; 1570 status = "disabled";
1575 1571
1576 bam_dmux: bam-dmux { <<
1577 compatible = <<
1578 <<
1579 interrupt-par <<
1580 interrupts = <<
1581 interrupt-nam <<
1582 <<
1583 qcom,smem-sta <<
1584 qcom,smem-sta <<
1585 <<
1586 dmas = <&bam_ <<
1587 dma-names = " <<
1588 <<
1589 status = "dis <<
1590 }; <<
1591 <<
1592 mba { 1572 mba {
1593 memory-region 1573 memory-region = <&mba_mem>;
1594 }; 1574 };
1595 1575
1596 mpss { 1576 mpss {
1597 memory-region 1577 memory-region = <&mpss_mem>;
1598 }; 1578 };
1599 1579
1600 smd-edge { 1580 smd-edge {
1601 interrupts = 1581 interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>;
1602 1582
1603 qcom,smd-edge 1583 qcom,smd-edge = <0>;
1604 mboxes = <&ap 1584 mboxes = <&apcs1_mbox 12>;
1605 qcom,remote-p 1585 qcom,remote-pid = <1>;
1606 1586
1607 label = "hexa 1587 label = "hexagon";
1608 <<
1609 apr: apr { <<
1610 compa <<
1611 qcom, <<
1612 qcom, <<
1613 #addr <<
1614 #size <<
1615 statu <<
1616 <<
1617 q6cor <<
1618 <<
1619 <<
1620 }; <<
1621 <<
1622 q6afe <<
1623 <<
1624 <<
1625 <<
1626 <<
1627 <<
1628 <<
1629 <<
1630 <<
1631 <<
1632 }; <<
1633 <<
1634 q6asm <<
1635 <<
1636 <<
1637 <<
1638 <<
1639 <<
1640 <<
1641 <<
1642 <<
1643 <<
1644 }; <<
1645 <<
1646 q6adm <<
1647 <<
1648 <<
1649 <<
1650 <<
1651 <<
1652 <<
1653 <<
1654 }; <<
1655 }; <<
1656 }; 1588 };
1657 }; 1589 };
1658 1590
1659 sound: sound@7702000 { 1591 sound: sound@7702000 {
1660 compatible = "qcom,ap 1592 compatible = "qcom,apq8016-sbc-sndcard";
1661 reg = <0x07702000 0x4 1593 reg = <0x07702000 0x4>,
1662 <0x07702004 0x4 1594 <0x07702004 0x4>;
1663 reg-names = "mic-iomu 1595 reg-names = "mic-iomux", "spkr-iomux";
1664 status = "disabled"; 1596 status = "disabled";
1665 }; 1597 };
1666 1598
1667 lpass: audio-controller@77080 1599 lpass: audio-controller@7708000 {
1668 compatible = "qcom,ap 1600 compatible = "qcom,apq8016-lpass-cpu";
1669 reg = <0x07708000 0x1 1601 reg = <0x07708000 0x10000>;
1670 reg-names = "lpass-lp 1602 reg-names = "lpass-lpaif";
1671 interrupts = <GIC_SPI 1603 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
1672 interrupt-names = "lp 1604 interrupt-names = "lpass-irq-lpaif";
1673 clocks = <&gcc GCC_UL 1605 clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
1674 <&gcc GCC_UL 1606 <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>,
1675 <&gcc GCC_UL 1607 <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>,
1676 <&gcc GCC_UL 1608 <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>,
1677 <&gcc GCC_UL 1609 <&gcc GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK>,
1678 <&gcc GCC_UL 1610 <&gcc GCC_ULTAUDIO_PCNOC_MPORT_CLK>,
1679 <&gcc GCC_UL 1611 <&gcc GCC_ULTAUDIO_PCNOC_SWAY_CLK>;
1680 clock-names = "ahbix- 1612 clock-names = "ahbix-clk",
1681 "mi2s-b 1613 "mi2s-bit-clk0",
1682 "mi2s-b 1614 "mi2s-bit-clk1",
1683 "mi2s-b 1615 "mi2s-bit-clk2",
1684 "mi2s-b 1616 "mi2s-bit-clk3",
1685 "pcnoc- 1617 "pcnoc-mport-clk",
1686 "pcnoc- 1618 "pcnoc-sway-clk";
1687 #sound-dai-cells = <1 1619 #sound-dai-cells = <1>;
1688 #address-cells = <1>; 1620 #address-cells = <1>;
1689 #size-cells = <0>; 1621 #size-cells = <0>;
1690 status = "disabled"; 1622 status = "disabled";
1691 }; 1623 };
1692 1624
1693 lpass_codec: audio-codec@771c 1625 lpass_codec: audio-codec@771c000 {
1694 compatible = "qcom,ms 1626 compatible = "qcom,msm8916-wcd-digital-codec";
1695 reg = <0x0771c000 0x4 1627 reg = <0x0771c000 0x400>;
1696 clocks = <&gcc GCC_UL 1628 clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
1697 <&gcc GCC_CO 1629 <&gcc GCC_CODEC_DIGCODEC_CLK>;
1698 clock-names = "ahbix- 1630 clock-names = "ahbix-clk", "mclk";
1699 #sound-dai-cells = <1 1631 #sound-dai-cells = <1>;
1700 status = "disabled"; 1632 status = "disabled";
1701 }; 1633 };
1702 1634
1703 sdhc_1: mmc@7824900 { 1635 sdhc_1: mmc@7824900 {
1704 compatible = "qcom,ms 1636 compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4";
1705 reg = <0x07824900 0x1 1637 reg = <0x07824900 0x11c>, <0x07824000 0x800>;
1706 reg-names = "hc", "co 1638 reg-names = "hc", "core";
1707 1639
1708 interrupts = <GIC_SPI 1640 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1709 <GIC_SPI 1641 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
1710 interrupt-names = "hc 1642 interrupt-names = "hc_irq", "pwr_irq";
1711 clocks = <&gcc GCC_SD 1643 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
1712 <&gcc GCC_SD 1644 <&gcc GCC_SDCC1_APPS_CLK>,
1713 <&rpmcc RPM_ 1645 <&rpmcc RPM_SMD_XO_CLK_SRC>;
1714 clock-names = "iface" 1646 clock-names = "iface", "core", "xo";
1715 resets = <&gcc GCC_SD 1647 resets = <&gcc GCC_SDCC1_BCR>;
1716 pinctrl-0 = <&sdc1_de 1648 pinctrl-0 = <&sdc1_default>;
1717 pinctrl-1 = <&sdc1_sl 1649 pinctrl-1 = <&sdc1_sleep>;
1718 pinctrl-names = "defa 1650 pinctrl-names = "default", "sleep";
1719 mmc-ddr-1_8v; 1651 mmc-ddr-1_8v;
1720 bus-width = <8>; 1652 bus-width = <8>;
1721 non-removable; 1653 non-removable;
1722 status = "disabled"; 1654 status = "disabled";
1723 }; 1655 };
1724 1656
1725 sdhc_2: mmc@7864900 { 1657 sdhc_2: mmc@7864900 {
1726 compatible = "qcom,ms 1658 compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4";
1727 reg = <0x07864900 0x1 1659 reg = <0x07864900 0x11c>, <0x07864000 0x800>;
1728 reg-names = "hc", "co 1660 reg-names = "hc", "core";
1729 1661
1730 interrupts = <GIC_SPI 1662 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1731 <GIC_SPI 1663 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
1732 interrupt-names = "hc 1664 interrupt-names = "hc_irq", "pwr_irq";
1733 clocks = <&gcc GCC_SD 1665 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
1734 <&gcc GCC_SD 1666 <&gcc GCC_SDCC2_APPS_CLK>,
1735 <&rpmcc RPM_ 1667 <&rpmcc RPM_SMD_XO_CLK_SRC>;
1736 clock-names = "iface" 1668 clock-names = "iface", "core", "xo";
1737 resets = <&gcc GCC_SD 1669 resets = <&gcc GCC_SDCC2_BCR>;
1738 pinctrl-0 = <&sdc2_de 1670 pinctrl-0 = <&sdc2_default>;
1739 pinctrl-1 = <&sdc2_sl 1671 pinctrl-1 = <&sdc2_sleep>;
1740 pinctrl-names = "defa 1672 pinctrl-names = "default", "sleep";
1741 bus-width = <4>; 1673 bus-width = <4>;
1742 status = "disabled"; 1674 status = "disabled";
1743 }; 1675 };
1744 1676
1745 blsp_dma: dma-controller@7884 1677 blsp_dma: dma-controller@7884000 {
1746 compatible = "qcom,ba 1678 compatible = "qcom,bam-v1.7.0";
1747 reg = <0x07884000 0x2 1679 reg = <0x07884000 0x23000>;
1748 interrupts = <GIC_SPI 1680 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
1749 clocks = <&gcc GCC_BL 1681 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
1750 clock-names = "bam_cl 1682 clock-names = "bam_clk";
1751 #dma-cells = <1>; 1683 #dma-cells = <1>;
1752 qcom,ee = <0>; 1684 qcom,ee = <0>;
1753 qcom,controlled-remot 1685 qcom,controlled-remotely;
1754 }; 1686 };
1755 1687
1756 blsp_uart1: serial@78af000 { 1688 blsp_uart1: serial@78af000 {
1757 compatible = "qcom,ms 1689 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1758 reg = <0x078af000 0x2 1690 reg = <0x078af000 0x200>;
1759 interrupts = <GIC_SPI 1691 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1760 clocks = <&gcc GCC_BL 1692 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
1761 clock-names = "core", 1693 clock-names = "core", "iface";
1762 dmas = <&blsp_dma 0>, 1694 dmas = <&blsp_dma 0>, <&blsp_dma 1>;
1763 dma-names = "tx", "rx 1695 dma-names = "tx", "rx";
1764 pinctrl-0 = <&blsp_ua 1696 pinctrl-0 = <&blsp_uart1_default>;
1765 pinctrl-1 = <&blsp_ua 1697 pinctrl-1 = <&blsp_uart1_sleep>;
1766 pinctrl-names = "defa 1698 pinctrl-names = "default", "sleep";
1767 status = "disabled"; 1699 status = "disabled";
1768 }; 1700 };
1769 1701
1770 blsp_uart2: serial@78b0000 { 1702 blsp_uart2: serial@78b0000 {
1771 compatible = "qcom,ms 1703 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1772 reg = <0x078b0000 0x2 1704 reg = <0x078b0000 0x200>;
1773 interrupts = <GIC_SPI 1705 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1774 clocks = <&gcc GCC_BL 1706 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
1775 clock-names = "core", 1707 clock-names = "core", "iface";
1776 dmas = <&blsp_dma 2>, 1708 dmas = <&blsp_dma 2>, <&blsp_dma 3>;
1777 dma-names = "tx", "rx 1709 dma-names = "tx", "rx";
1778 pinctrl-0 = <&blsp_ua 1710 pinctrl-0 = <&blsp_uart2_default>;
1779 pinctrl-1 = <&blsp_ua 1711 pinctrl-1 = <&blsp_uart2_sleep>;
1780 pinctrl-names = "defa 1712 pinctrl-names = "default", "sleep";
1781 status = "disabled"; 1713 status = "disabled";
1782 }; 1714 };
1783 1715
1784 blsp_i2c1: i2c@78b5000 { 1716 blsp_i2c1: i2c@78b5000 {
1785 compatible = "qcom,i2 1717 compatible = "qcom,i2c-qup-v2.2.1";
1786 reg = <0x078b5000 0x5 1718 reg = <0x078b5000 0x500>;
1787 interrupts = <GIC_SPI 1719 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
1788 clocks = <&gcc GCC_BL 1720 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
1789 <&gcc GCC_BL 1721 <&gcc GCC_BLSP1_AHB_CLK>;
1790 clock-names = "core", 1722 clock-names = "core", "iface";
1791 dmas = <&blsp_dma 4>, 1723 dmas = <&blsp_dma 4>, <&blsp_dma 5>;
1792 dma-names = "tx", "rx 1724 dma-names = "tx", "rx";
1793 pinctrl-0 = <&blsp_i2 1725 pinctrl-0 = <&blsp_i2c1_default>;
1794 pinctrl-1 = <&blsp_i2 1726 pinctrl-1 = <&blsp_i2c1_sleep>;
1795 pinctrl-names = "defa 1727 pinctrl-names = "default", "sleep";
1796 #address-cells = <1>; 1728 #address-cells = <1>;
1797 #size-cells = <0>; 1729 #size-cells = <0>;
1798 status = "disabled"; 1730 status = "disabled";
1799 }; 1731 };
1800 1732
1801 blsp_spi1: spi@78b5000 { 1733 blsp_spi1: spi@78b5000 {
1802 compatible = "qcom,sp 1734 compatible = "qcom,spi-qup-v2.2.1";
1803 reg = <0x078b5000 0x5 1735 reg = <0x078b5000 0x500>;
1804 interrupts = <GIC_SPI 1736 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
1805 clocks = <&gcc GCC_BL 1737 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
1806 <&gcc GCC_BL 1738 <&gcc GCC_BLSP1_AHB_CLK>;
1807 clock-names = "core", 1739 clock-names = "core", "iface";
1808 dmas = <&blsp_dma 4>, 1740 dmas = <&blsp_dma 4>, <&blsp_dma 5>;
1809 dma-names = "tx", "rx 1741 dma-names = "tx", "rx";
1810 pinctrl-0 = <&blsp_sp 1742 pinctrl-0 = <&blsp_spi1_default>;
1811 pinctrl-1 = <&blsp_sp 1743 pinctrl-1 = <&blsp_spi1_sleep>;
1812 pinctrl-names = "defa 1744 pinctrl-names = "default", "sleep";
1813 #address-cells = <1>; 1745 #address-cells = <1>;
1814 #size-cells = <0>; 1746 #size-cells = <0>;
1815 status = "disabled"; 1747 status = "disabled";
1816 }; 1748 };
1817 1749
1818 blsp_i2c2: i2c@78b6000 { 1750 blsp_i2c2: i2c@78b6000 {
1819 compatible = "qcom,i2 1751 compatible = "qcom,i2c-qup-v2.2.1";
1820 reg = <0x078b6000 0x5 1752 reg = <0x078b6000 0x500>;
1821 interrupts = <GIC_SPI 1753 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1822 clocks = <&gcc GCC_BL 1754 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
1823 <&gcc GCC_BL 1755 <&gcc GCC_BLSP1_AHB_CLK>;
1824 clock-names = "core", 1756 clock-names = "core", "iface";
1825 dmas = <&blsp_dma 6>, 1757 dmas = <&blsp_dma 6>, <&blsp_dma 7>;
1826 dma-names = "tx", "rx 1758 dma-names = "tx", "rx";
1827 pinctrl-0 = <&blsp_i2 1759 pinctrl-0 = <&blsp_i2c2_default>;
1828 pinctrl-1 = <&blsp_i2 1760 pinctrl-1 = <&blsp_i2c2_sleep>;
1829 pinctrl-names = "defa 1761 pinctrl-names = "default", "sleep";
1830 #address-cells = <1>; 1762 #address-cells = <1>;
1831 #size-cells = <0>; 1763 #size-cells = <0>;
1832 status = "disabled"; 1764 status = "disabled";
1833 }; 1765 };
1834 1766
1835 blsp_spi2: spi@78b6000 { 1767 blsp_spi2: spi@78b6000 {
1836 compatible = "qcom,sp 1768 compatible = "qcom,spi-qup-v2.2.1";
1837 reg = <0x078b6000 0x5 1769 reg = <0x078b6000 0x500>;
1838 interrupts = <GIC_SPI 1770 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1839 clocks = <&gcc GCC_BL 1771 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
1840 <&gcc GCC_BL 1772 <&gcc GCC_BLSP1_AHB_CLK>;
1841 clock-names = "core", 1773 clock-names = "core", "iface";
1842 dmas = <&blsp_dma 6>, 1774 dmas = <&blsp_dma 6>, <&blsp_dma 7>;
1843 dma-names = "tx", "rx 1775 dma-names = "tx", "rx";
1844 pinctrl-0 = <&blsp_sp 1776 pinctrl-0 = <&blsp_spi2_default>;
1845 pinctrl-1 = <&blsp_sp 1777 pinctrl-1 = <&blsp_spi2_sleep>;
1846 pinctrl-names = "defa 1778 pinctrl-names = "default", "sleep";
1847 #address-cells = <1>; 1779 #address-cells = <1>;
1848 #size-cells = <0>; 1780 #size-cells = <0>;
1849 status = "disabled"; 1781 status = "disabled";
1850 }; 1782 };
1851 1783
1852 blsp_i2c3: i2c@78b7000 { 1784 blsp_i2c3: i2c@78b7000 {
1853 compatible = "qcom,i2 1785 compatible = "qcom,i2c-qup-v2.2.1";
1854 reg = <0x078b7000 0x5 1786 reg = <0x078b7000 0x500>;
1855 interrupts = <GIC_SPI 1787 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1856 clocks = <&gcc GCC_BL 1788 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
1857 <&gcc GCC_BL 1789 <&gcc GCC_BLSP1_AHB_CLK>;
1858 clock-names = "core", 1790 clock-names = "core", "iface";
1859 dmas = <&blsp_dma 8>, 1791 dmas = <&blsp_dma 8>, <&blsp_dma 9>;
1860 dma-names = "tx", "rx 1792 dma-names = "tx", "rx";
1861 pinctrl-0 = <&blsp_i2 1793 pinctrl-0 = <&blsp_i2c3_default>;
1862 pinctrl-1 = <&blsp_i2 1794 pinctrl-1 = <&blsp_i2c3_sleep>;
1863 pinctrl-names = "defa 1795 pinctrl-names = "default", "sleep";
1864 #address-cells = <1>; 1796 #address-cells = <1>;
1865 #size-cells = <0>; 1797 #size-cells = <0>;
1866 status = "disabled"; 1798 status = "disabled";
1867 }; 1799 };
1868 1800
1869 blsp_spi3: spi@78b7000 { 1801 blsp_spi3: spi@78b7000 {
1870 compatible = "qcom,sp 1802 compatible = "qcom,spi-qup-v2.2.1";
1871 reg = <0x078b7000 0x5 1803 reg = <0x078b7000 0x500>;
1872 interrupts = <GIC_SPI 1804 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1873 clocks = <&gcc GCC_BL 1805 clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
1874 <&gcc GCC_BL 1806 <&gcc GCC_BLSP1_AHB_CLK>;
1875 clock-names = "core", 1807 clock-names = "core", "iface";
1876 dmas = <&blsp_dma 8>, 1808 dmas = <&blsp_dma 8>, <&blsp_dma 9>;
1877 dma-names = "tx", "rx 1809 dma-names = "tx", "rx";
1878 pinctrl-0 = <&blsp_sp 1810 pinctrl-0 = <&blsp_spi3_default>;
1879 pinctrl-1 = <&blsp_sp 1811 pinctrl-1 = <&blsp_spi3_sleep>;
1880 pinctrl-names = "defa 1812 pinctrl-names = "default", "sleep";
1881 #address-cells = <1>; 1813 #address-cells = <1>;
1882 #size-cells = <0>; 1814 #size-cells = <0>;
1883 status = "disabled"; 1815 status = "disabled";
1884 }; 1816 };
1885 1817
1886 blsp_i2c4: i2c@78b8000 { 1818 blsp_i2c4: i2c@78b8000 {
1887 compatible = "qcom,i2 1819 compatible = "qcom,i2c-qup-v2.2.1";
1888 reg = <0x078b8000 0x5 1820 reg = <0x078b8000 0x500>;
1889 interrupts = <GIC_SPI 1821 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1890 clocks = <&gcc GCC_BL 1822 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
1891 <&gcc GCC_BL 1823 <&gcc GCC_BLSP1_AHB_CLK>;
1892 clock-names = "core", 1824 clock-names = "core", "iface";
1893 dmas = <&blsp_dma 10> 1825 dmas = <&blsp_dma 10>, <&blsp_dma 11>;
1894 dma-names = "tx", "rx 1826 dma-names = "tx", "rx";
1895 pinctrl-0 = <&blsp_i2 1827 pinctrl-0 = <&blsp_i2c4_default>;
1896 pinctrl-1 = <&blsp_i2 1828 pinctrl-1 = <&blsp_i2c4_sleep>;
1897 pinctrl-names = "defa 1829 pinctrl-names = "default", "sleep";
1898 #address-cells = <1>; 1830 #address-cells = <1>;
1899 #size-cells = <0>; 1831 #size-cells = <0>;
1900 status = "disabled"; 1832 status = "disabled";
1901 }; 1833 };
1902 1834
1903 blsp_spi4: spi@78b8000 { 1835 blsp_spi4: spi@78b8000 {
1904 compatible = "qcom,sp 1836 compatible = "qcom,spi-qup-v2.2.1";
1905 reg = <0x078b8000 0x5 1837 reg = <0x078b8000 0x500>;
1906 interrupts = <GIC_SPI 1838 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1907 clocks = <&gcc GCC_BL 1839 clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
1908 <&gcc GCC_BL 1840 <&gcc GCC_BLSP1_AHB_CLK>;
1909 clock-names = "core", 1841 clock-names = "core", "iface";
1910 dmas = <&blsp_dma 10> 1842 dmas = <&blsp_dma 10>, <&blsp_dma 11>;
1911 dma-names = "tx", "rx 1843 dma-names = "tx", "rx";
1912 pinctrl-0 = <&blsp_sp 1844 pinctrl-0 = <&blsp_spi4_default>;
1913 pinctrl-1 = <&blsp_sp 1845 pinctrl-1 = <&blsp_spi4_sleep>;
1914 pinctrl-names = "defa 1846 pinctrl-names = "default", "sleep";
1915 #address-cells = <1>; 1847 #address-cells = <1>;
1916 #size-cells = <0>; 1848 #size-cells = <0>;
1917 status = "disabled"; 1849 status = "disabled";
1918 }; 1850 };
1919 1851
1920 blsp_i2c5: i2c@78b9000 { 1852 blsp_i2c5: i2c@78b9000 {
1921 compatible = "qcom,i2 1853 compatible = "qcom,i2c-qup-v2.2.1";
1922 reg = <0x078b9000 0x5 1854 reg = <0x078b9000 0x500>;
1923 interrupts = <GIC_SPI 1855 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
1924 clocks = <&gcc GCC_BL 1856 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
1925 <&gcc GCC_BL 1857 <&gcc GCC_BLSP1_AHB_CLK>;
1926 clock-names = "core", 1858 clock-names = "core", "iface";
1927 dmas = <&blsp_dma 12> 1859 dmas = <&blsp_dma 12>, <&blsp_dma 13>;
1928 dma-names = "tx", "rx 1860 dma-names = "tx", "rx";
1929 pinctrl-0 = <&blsp_i2 1861 pinctrl-0 = <&blsp_i2c5_default>;
1930 pinctrl-1 = <&blsp_i2 1862 pinctrl-1 = <&blsp_i2c5_sleep>;
1931 pinctrl-names = "defa 1863 pinctrl-names = "default", "sleep";
1932 #address-cells = <1>; 1864 #address-cells = <1>;
1933 #size-cells = <0>; 1865 #size-cells = <0>;
1934 status = "disabled"; 1866 status = "disabled";
1935 }; 1867 };
1936 1868
1937 blsp_spi5: spi@78b9000 { 1869 blsp_spi5: spi@78b9000 {
1938 compatible = "qcom,sp 1870 compatible = "qcom,spi-qup-v2.2.1";
1939 reg = <0x078b9000 0x5 1871 reg = <0x078b9000 0x500>;
1940 interrupts = <GIC_SPI 1872 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
1941 clocks = <&gcc GCC_BL 1873 clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
1942 <&gcc GCC_BL 1874 <&gcc GCC_BLSP1_AHB_CLK>;
1943 clock-names = "core", 1875 clock-names = "core", "iface";
1944 dmas = <&blsp_dma 12> 1876 dmas = <&blsp_dma 12>, <&blsp_dma 13>;
1945 dma-names = "tx", "rx 1877 dma-names = "tx", "rx";
1946 pinctrl-0 = <&blsp_sp 1878 pinctrl-0 = <&blsp_spi5_default>;
1947 pinctrl-1 = <&blsp_sp 1879 pinctrl-1 = <&blsp_spi5_sleep>;
1948 pinctrl-names = "defa 1880 pinctrl-names = "default", "sleep";
1949 #address-cells = <1>; 1881 #address-cells = <1>;
1950 #size-cells = <0>; 1882 #size-cells = <0>;
1951 status = "disabled"; 1883 status = "disabled";
1952 }; 1884 };
1953 1885
1954 blsp_i2c6: i2c@78ba000 { 1886 blsp_i2c6: i2c@78ba000 {
1955 compatible = "qcom,i2 1887 compatible = "qcom,i2c-qup-v2.2.1";
1956 reg = <0x078ba000 0x5 1888 reg = <0x078ba000 0x500>;
1957 interrupts = <GIC_SPI 1889 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
1958 clocks = <&gcc GCC_BL 1890 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
1959 <&gcc GCC_BL 1891 <&gcc GCC_BLSP1_AHB_CLK>;
1960 clock-names = "core", 1892 clock-names = "core", "iface";
1961 dmas = <&blsp_dma 14> 1893 dmas = <&blsp_dma 14>, <&blsp_dma 15>;
1962 dma-names = "tx", "rx 1894 dma-names = "tx", "rx";
1963 pinctrl-0 = <&blsp_i2 1895 pinctrl-0 = <&blsp_i2c6_default>;
1964 pinctrl-1 = <&blsp_i2 1896 pinctrl-1 = <&blsp_i2c6_sleep>;
1965 pinctrl-names = "defa 1897 pinctrl-names = "default", "sleep";
1966 #address-cells = <1>; 1898 #address-cells = <1>;
1967 #size-cells = <0>; 1899 #size-cells = <0>;
1968 status = "disabled"; 1900 status = "disabled";
1969 }; 1901 };
1970 1902
1971 blsp_spi6: spi@78ba000 { 1903 blsp_spi6: spi@78ba000 {
1972 compatible = "qcom,sp 1904 compatible = "qcom,spi-qup-v2.2.1";
1973 reg = <0x078ba000 0x5 1905 reg = <0x078ba000 0x500>;
1974 interrupts = <GIC_SPI 1906 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
1975 clocks = <&gcc GCC_BL 1907 clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>,
1976 <&gcc GCC_BL 1908 <&gcc GCC_BLSP1_AHB_CLK>;
1977 clock-names = "core", 1909 clock-names = "core", "iface";
1978 dmas = <&blsp_dma 14> 1910 dmas = <&blsp_dma 14>, <&blsp_dma 15>;
1979 dma-names = "tx", "rx 1911 dma-names = "tx", "rx";
1980 pinctrl-0 = <&blsp_sp 1912 pinctrl-0 = <&blsp_spi6_default>;
1981 pinctrl-1 = <&blsp_sp 1913 pinctrl-1 = <&blsp_spi6_sleep>;
1982 pinctrl-names = "defa 1914 pinctrl-names = "default", "sleep";
1983 #address-cells = <1>; 1915 #address-cells = <1>;
1984 #size-cells = <0>; 1916 #size-cells = <0>;
1985 status = "disabled"; 1917 status = "disabled";
1986 }; 1918 };
1987 1919
1988 usb: usb@78d9000 { 1920 usb: usb@78d9000 {
1989 compatible = "qcom,ci 1921 compatible = "qcom,ci-hdrc";
1990 reg = <0x078d9000 0x2 1922 reg = <0x078d9000 0x200>,
1991 <0x078d9200 0x2 1923 <0x078d9200 0x200>;
1992 interrupts = <GIC_SPI 1924 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
1993 <GIC_SPI 1925 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
1994 clocks = <&gcc GCC_US 1926 clocks = <&gcc GCC_USB_HS_AHB_CLK>,
1995 <&gcc GCC_US 1927 <&gcc GCC_USB_HS_SYSTEM_CLK>;
1996 clock-names = "iface" 1928 clock-names = "iface", "core";
1997 assigned-clocks = <&g 1929 assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>;
1998 assigned-clock-rates 1930 assigned-clock-rates = <80000000>;
1999 resets = <&gcc GCC_US 1931 resets = <&gcc GCC_USB_HS_BCR>;
2000 reset-names = "core"; 1932 reset-names = "core";
2001 #reset-cells = <1>; 1933 #reset-cells = <1>;
2002 phy_type = "ulpi"; 1934 phy_type = "ulpi";
2003 dr_mode = "otg"; 1935 dr_mode = "otg";
2004 adp-disable; 1936 adp-disable;
2005 hnp-disable; 1937 hnp-disable;
2006 srp-disable; 1938 srp-disable;
2007 ahb-burst-config = <0 1939 ahb-burst-config = <0>;
2008 phy-names = "usb-phy" 1940 phy-names = "usb-phy";
2009 phys = <&usb_hs_phy>; 1941 phys = <&usb_hs_phy>;
2010 status = "disabled"; 1942 status = "disabled";
2011 1943
2012 ulpi { 1944 ulpi {
2013 usb_hs_phy: p 1945 usb_hs_phy: phy {
2014 compa 1946 compatible = "qcom,usb-hs-phy-msm8916",
2015 1947 "qcom,usb-hs-phy";
2016 clock 1948 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
2017 1949 <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
2018 clock 1950 clock-names = "ref", "sleep";
2019 reset 1951 resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>;
2020 reset 1952 reset-names = "phy", "por";
2021 #phy- 1953 #phy-cells = <0>;
2022 qcom, 1954 qcom,init-seq = /bits/ 8 <0x0 0x44>,
2023 1955 <0x1 0x6b>,
2024 1956 <0x2 0x24>,
2025 1957 <0x3 0x13>;
2026 }; 1958 };
2027 }; 1959 };
2028 }; 1960 };
2029 1961
2030 wcnss: remoteproc@a204000 { 1962 wcnss: remoteproc@a204000 {
2031 compatible = "qcom,pr 1963 compatible = "qcom,pronto-v2-pil", "qcom,pronto";
2032 interrupts-extended = 1964 interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>,
2033 1965 <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2034 1966 <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2035 1967 <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2036 1968 <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
2037 interrupt-names = "wd 1969 interrupt-names = "wdog",
2038 "fa 1970 "fatal",
2039 "re 1971 "ready",
2040 "ha 1972 "handover",
2041 "st 1973 "stop-ack";
2042 reg = <0x0a204000 0x2 1974 reg = <0x0a204000 0x2000>,
2043 <0x0a202000 0x1 1975 <0x0a202000 0x1000>,
2044 <0x0a21b000 0x3 1976 <0x0a21b000 0x3000>;
2045 reg-names = "ccu", "d 1977 reg-names = "ccu", "dxe", "pmu";
2046 1978
2047 memory-region = <&wcn 1979 memory-region = <&wcnss_mem>;
2048 1980
2049 power-domains = <&rpm 1981 power-domains = <&rpmpd MSM8939_VDDCX>,
2050 <&rpm 1982 <&rpmpd MSM8939_VDDMX>;
2051 power-domain-names = 1983 power-domain-names = "cx", "mx";
2052 1984
2053 qcom,smem-states = <& 1985 qcom,smem-states = <&wcnss_smp2p_out 0>;
2054 qcom,smem-state-names 1986 qcom,smem-state-names = "stop";
2055 1987
2056 pinctrl-names = "defa 1988 pinctrl-names = "default";
2057 pinctrl-0 = <&wcss_wl 1989 pinctrl-0 = <&wcss_wlan_default>;
2058 1990
2059 status = "disabled"; 1991 status = "disabled";
2060 1992
2061 wcnss_iris: iris { 1993 wcnss_iris: iris {
2062 /* Separate c 1994 /* Separate chip, compatible is board-specific */
2063 clocks = <&rp 1995 clocks = <&rpmcc RPM_SMD_RF_CLK2>;
2064 clock-names = 1996 clock-names = "xo";
2065 }; 1997 };
2066 1998
2067 smd-edge { 1999 smd-edge {
2068 interrupts = 2000 interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>;
2069 mboxes = <&ap !! 2001 qcom,ipc = <&apcs1_mbox 8 17>;
2070 qcom,smd-edge 2002 qcom,smd-edge = <6>;
2071 qcom,remote-p 2003 qcom,remote-pid = <4>;
2072 2004
2073 label = "pron 2005 label = "pronto";
2074 2006
2075 wcnss { 2007 wcnss {
2076 compa 2008 compatible = "qcom,wcnss";
2077 qcom, 2009 qcom,smd-channels = "WCNSS_CTRL";
2078 2010
2079 qcom, 2011 qcom,mmio = <&wcnss>;
2080 2012
2081 wcnss 2013 wcnss_bt: bluetooth {
2082 2014 compatible = "qcom,wcnss-bt";
2083 }; 2015 };
2084 2016
2085 wcnss 2017 wcnss_wifi: wifi {
2086 2018 compatible = "qcom,wcnss-wlan";
2087 2019
2088 2020 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
2089 2021 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
2090 2022 interrupt-names = "tx", "rx";
2091 2023
2092 2024 qcom,smem-states = <&apps_smsm 10>,
2093 2025 <&apps_smsm 9>;
2094 2026 qcom,smem-state-names = "tx-enable",
2095 2027 "tx-rings-empty";
2096 }; 2028 };
2097 }; 2029 };
2098 }; 2030 };
2099 }; 2031 };
2100 2032
2101 intc: interrupt-controller@b0 2033 intc: interrupt-controller@b000000 {
2102 compatible = "qcom,ms 2034 compatible = "qcom,msm-qgic2";
2103 reg = <0x0b000000 0x1 2035 reg = <0x0b000000 0x1000>, <0x0b002000 0x2000>,
2104 <0x0b001000 0x1 2036 <0x0b001000 0x1000>, <0x0b004000 0x2000>;
2105 interrupt-controller; 2037 interrupt-controller;
2106 #interrupt-cells = <3 2038 #interrupt-cells = <3>;
2107 interrupts = <GIC_PPI 2039 interrupts = <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
2108 }; 2040 };
2109 2041
2110 apcs1_mbox: mailbox@b011000 { 2042 apcs1_mbox: mailbox@b011000 {
2111 compatible = "qcom,ms 2043 compatible = "qcom,msm8939-apcs-kpss-global", "syscon";
2112 reg = <0x0b011000 0x1 2044 reg = <0x0b011000 0x1000>;
2113 clocks = <&a53pll_c1> 2045 clocks = <&a53pll_c1>, <&gcc GPLL0_VOTE>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
2114 clock-names = "pll", 2046 clock-names = "pll", "aux", "ref";
2115 #clock-cells = <0>; 2047 #clock-cells = <0>;
2116 assigned-clocks = <&a 2048 assigned-clocks = <&apcs2>;
2117 assigned-clock-rates 2049 assigned-clock-rates = <297600000>;
2118 #mbox-cells = <1>; 2050 #mbox-cells = <1>;
2119 }; 2051 };
2120 2052
2121 a53pll_c1: clock@b016000 { 2053 a53pll_c1: clock@b016000 {
2122 compatible = "qcom,ms 2054 compatible = "qcom,msm8939-a53pll";
2123 reg = <0x0b016000 0x4 2055 reg = <0x0b016000 0x40>;
2124 #clock-cells = <0>; 2056 #clock-cells = <0>;
2125 }; 2057 };
2126 2058
2127 acc0: clock-controller@b08800 2059 acc0: clock-controller@b088000 {
2128 compatible = "qcom,kp 2060 compatible = "qcom,kpss-acc-v2";
2129 reg = <0x0b088000 0x1 2061 reg = <0x0b088000 0x1000>;
2130 }; 2062 };
2131 2063
2132 saw0: power-manager@b089000 { 2064 saw0: power-manager@b089000 {
2133 compatible = "qcom,ms 2065 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
2134 reg = <0x0b089000 0x1 2066 reg = <0x0b089000 0x1000>;
2135 }; 2067 };
2136 2068
2137 acc1: clock-controller@b09800 2069 acc1: clock-controller@b098000 {
2138 compatible = "qcom,kp 2070 compatible = "qcom,kpss-acc-v2";
2139 reg = <0x0b098000 0x1 2071 reg = <0x0b098000 0x1000>;
2140 }; 2072 };
2141 2073
2142 saw1: power-manager@b099000 { 2074 saw1: power-manager@b099000 {
2143 compatible = "qcom,ms 2075 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
2144 reg = <0x0b099000 0x1 2076 reg = <0x0b099000 0x1000>;
2145 }; 2077 };
2146 2078
2147 acc2: clock-controller@b0a800 2079 acc2: clock-controller@b0a8000 {
2148 compatible = "qcom,kp 2080 compatible = "qcom,kpss-acc-v2";
2149 reg = <0x0b0a8000 0x1 2081 reg = <0x0b0a8000 0x1000>;
2150 }; 2082 };
2151 2083
2152 saw2: power-manager@b0a9000 { 2084 saw2: power-manager@b0a9000 {
2153 compatible = "qcom,ms 2085 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
2154 reg = <0x0b0a9000 0x1 2086 reg = <0x0b0a9000 0x1000>;
2155 }; 2087 };
2156 2088
2157 acc3: clock-controller@b0b800 2089 acc3: clock-controller@b0b8000 {
2158 compatible = "qcom,kp 2090 compatible = "qcom,kpss-acc-v2";
2159 reg = <0x0b0b8000 0x1 2091 reg = <0x0b0b8000 0x1000>;
2160 }; 2092 };
2161 2093
2162 saw3: power-manager@b0b9000 { 2094 saw3: power-manager@b0b9000 {
2163 compatible = "qcom,ms 2095 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
2164 reg = <0x0b0b9000 0x1 2096 reg = <0x0b0b9000 0x1000>;
2165 }; 2097 };
2166 2098
2167 apcs0_mbox: mailbox@b111000 { 2099 apcs0_mbox: mailbox@b111000 {
2168 compatible = "qcom,ms 2100 compatible = "qcom,msm8939-apcs-kpss-global", "syscon";
2169 reg = <0x0b111000 0x1 2101 reg = <0x0b111000 0x1000>;
2170 clocks = <&a53pll_c0> 2102 clocks = <&a53pll_c0>, <&gcc GPLL0_VOTE>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
2171 clock-names = "pll", 2103 clock-names = "pll", "aux", "ref";
2172 #clock-cells = <0>; 2104 #clock-cells = <0>;
2173 #mbox-cells = <1>; 2105 #mbox-cells = <1>;
2174 }; 2106 };
2175 2107
2176 a53pll_c0: clock@b116000 { 2108 a53pll_c0: clock@b116000 {
2177 compatible = "qcom,ms 2109 compatible = "qcom,msm8939-a53pll";
2178 reg = <0x0b116000 0x4 2110 reg = <0x0b116000 0x40>;
2179 #clock-cells = <0>; 2111 #clock-cells = <0>;
2180 }; 2112 };
2181 2113
2182 timer@b120000 { 2114 timer@b120000 {
2183 compatible = "arm,arm 2115 compatible = "arm,armv7-timer-mem";
2184 reg = <0x0b120000 0x1 2116 reg = <0x0b120000 0x1000>;
2185 #address-cells = <1>; 2117 #address-cells = <1>;
2186 #size-cells = <1>; 2118 #size-cells = <1>;
2187 ranges; 2119 ranges;
2188 /* Necessary because <<
2189 clock-frequency = <19 <<
2190 2120
2191 frame@b121000 { 2121 frame@b121000 {
2192 reg = <0x0b12 2122 reg = <0x0b121000 0x1000>,
2193 <0x0b12 2123 <0x0b122000 0x1000>;
2194 interrupts = 2124 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
2195 2125 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
2196 frame-number 2126 frame-number = <0>;
2197 }; 2127 };
2198 2128
2199 frame@b123000 { 2129 frame@b123000 {
2200 reg = <0x0b12 2130 reg = <0x0b123000 0x1000>;
2201 interrupts = 2131 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
2202 frame-number 2132 frame-number = <1>;
2203 status = "dis 2133 status = "disabled";
2204 }; 2134 };
2205 2135
2206 frame@b124000 { 2136 frame@b124000 {
2207 reg = <0x0b12 2137 reg = <0x0b124000 0x1000>;
2208 interrupts = 2138 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
2209 frame-number 2139 frame-number = <2>;
2210 status = "dis 2140 status = "disabled";
2211 }; 2141 };
2212 2142
2213 frame@b125000 { 2143 frame@b125000 {
2214 reg = <0x0b12 2144 reg = <0x0b125000 0x1000>;
2215 interrupts = 2145 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
2216 frame-number 2146 frame-number = <3>;
2217 status = "dis 2147 status = "disabled";
2218 }; 2148 };
2219 2149
2220 frame@b126000 { 2150 frame@b126000 {
2221 reg = <0x0b12 2151 reg = <0x0b126000 0x1000>;
2222 interrupts = 2152 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
2223 frame-number 2153 frame-number = <4>;
2224 status = "dis 2154 status = "disabled";
2225 }; 2155 };
2226 2156
2227 frame@b127000 { 2157 frame@b127000 {
2228 reg = <0x0b12 2158 reg = <0x0b127000 0x1000>;
2229 interrupts = 2159 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
2230 frame-number 2160 frame-number = <5>;
2231 status = "dis 2161 status = "disabled";
2232 }; 2162 };
2233 2163
2234 frame@b128000 { 2164 frame@b128000 {
2235 reg = <0x0b12 2165 reg = <0x0b128000 0x1000>;
2236 interrupts = 2166 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
2237 frame-number 2167 frame-number = <6>;
2238 status = "dis 2168 status = "disabled";
2239 }; 2169 };
2240 }; 2170 };
2241 2171
2242 acc4: clock-controller@b18800 2172 acc4: clock-controller@b188000 {
2243 compatible = "qcom,kp 2173 compatible = "qcom,kpss-acc-v2";
2244 reg = <0x0b188000 0x1 2174 reg = <0x0b188000 0x1000>;
2245 }; 2175 };
2246 2176
2247 saw4: power-manager@b189000 { 2177 saw4: power-manager@b189000 {
2248 compatible = "qcom,ms 2178 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
2249 reg = <0x0b189000 0x1 2179 reg = <0x0b189000 0x1000>;
2250 }; 2180 };
2251 2181
2252 acc5: clock-controller@b19800 2182 acc5: clock-controller@b198000 {
2253 compatible = "qcom,kp 2183 compatible = "qcom,kpss-acc-v2";
2254 reg = <0x0b198000 0x1 2184 reg = <0x0b198000 0x1000>;
2255 }; 2185 };
2256 2186
2257 saw5: power-manager@b199000 { 2187 saw5: power-manager@b199000 {
2258 compatible = "qcom,ms 2188 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
2259 reg = <0x0b199000 0x1 2189 reg = <0x0b199000 0x1000>;
2260 }; 2190 };
2261 2191
2262 acc6: clock-controller@b1a800 2192 acc6: clock-controller@b1a8000 {
2263 compatible = "qcom,kp 2193 compatible = "qcom,kpss-acc-v2";
2264 reg = <0x0b1a8000 0x1 2194 reg = <0x0b1a8000 0x1000>;
2265 }; 2195 };
2266 2196
2267 saw6: power-manager@b1a9000 { 2197 saw6: power-manager@b1a9000 {
2268 compatible = "qcom,ms 2198 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
2269 reg = <0x0b1a9000 0x1 2199 reg = <0x0b1a9000 0x1000>;
2270 }; 2200 };
2271 2201
2272 acc7: clock-controller@b1b800 2202 acc7: clock-controller@b1b8000 {
2273 compatible = "qcom,kp 2203 compatible = "qcom,kpss-acc-v2";
2274 reg = <0x0b1b8000 0x1 2204 reg = <0x0b1b8000 0x1000>;
2275 }; 2205 };
2276 2206
2277 saw7: power-manager@b1b9000 { 2207 saw7: power-manager@b1b9000 {
2278 compatible = "qcom,ms 2208 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
2279 reg = <0x0b1b9000 0x1 2209 reg = <0x0b1b9000 0x1000>;
2280 }; 2210 };
2281 2211
2282 a53pll_cci: clock@b1d0000 { 2212 a53pll_cci: clock@b1d0000 {
2283 compatible = "qcom,ms 2213 compatible = "qcom,msm8939-a53pll";
2284 reg = <0x0b1d0000 0x4 2214 reg = <0x0b1d0000 0x40>;
2285 #clock-cells = <0>; 2215 #clock-cells = <0>;
2286 }; 2216 };
2287 2217
2288 apcs2: mailbox@b1d1000 { 2218 apcs2: mailbox@b1d1000 {
2289 compatible = "qcom,ms 2219 compatible = "qcom,msm8939-apcs-kpss-global", "syscon";
2290 reg = <0x0b1d1000 0x1 2220 reg = <0x0b1d1000 0x1000>;
2291 clocks = <&a53pll_cci 2221 clocks = <&a53pll_cci>, <&gcc GPLL0_VOTE>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
2292 clock-names = "pll", 2222 clock-names = "pll", "aux", "ref";
2293 #clock-cells = <0>; 2223 #clock-cells = <0>;
2294 #mbox-cells = <1>; 2224 #mbox-cells = <1>;
2295 }; 2225 };
2296 }; 2226 };
2297 2227
2298 thermal_zones: thermal-zones { 2228 thermal_zones: thermal-zones {
2299 cpu0-thermal { 2229 cpu0-thermal {
2300 polling-delay-passive 2230 polling-delay-passive = <250>;
>> 2231 polling-delay = <1000>;
2301 2232
2302 thermal-sensors = <&t 2233 thermal-sensors = <&tsens 5>;
2303 2234
2304 trips { 2235 trips {
2305 cpu0_alert: t 2236 cpu0_alert: trip0 {
2306 tempe 2237 temperature = <75000>;
2307 hyste 2238 hysteresis = <2000>;
2308 type 2239 type = "passive";
2309 }; 2240 };
2310 2241
2311 cpu0_crit: tr 2242 cpu0_crit: trip1 {
2312 tempe 2243 temperature = <115000>;
2313 hyste 2244 hysteresis = <0>;
2314 type 2245 type = "critical";
2315 }; 2246 };
2316 }; 2247 };
2317 2248
2318 cooling-maps { 2249 cooling-maps {
2319 map0 { 2250 map0 {
2320 trip 2251 trip = <&cpu0_alert>;
2321 cooli 2252 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2322 2253 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2323 2254 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2324 2255 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2325 }; 2256 };
2326 }; 2257 };
2327 }; 2258 };
2328 2259
2329 cpu1-thermal { 2260 cpu1-thermal {
2330 polling-delay-passive 2261 polling-delay-passive = <250>;
>> 2262 polling-delay = <1000>;
2331 2263
2332 thermal-sensors = <&t 2264 thermal-sensors = <&tsens 6>;
2333 2265
2334 trips { 2266 trips {
2335 cpu1_alert: t 2267 cpu1_alert: trip0 {
2336 tempe 2268 temperature = <75000>;
2337 hyste 2269 hysteresis = <2000>;
2338 type 2270 type = "passive";
2339 }; 2271 };
2340 2272
2341 cpu1_crit: tr 2273 cpu1_crit: trip1 {
2342 tempe 2274 temperature = <110000>;
2343 hyste 2275 hysteresis = <2000>;
2344 type 2276 type = "critical";
2345 }; 2277 };
2346 }; 2278 };
2347 2279
2348 cooling-maps { 2280 cooling-maps {
2349 map0 { 2281 map0 {
2350 trip 2282 trip = <&cpu1_alert>;
2351 cooli 2283 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2352 2284 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2353 2285 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2354 2286 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2355 }; 2287 };
2356 }; 2288 };
2357 }; 2289 };
2358 2290
2359 cpu2-thermal { 2291 cpu2-thermal {
2360 polling-delay-passive 2292 polling-delay-passive = <250>;
>> 2293 polling-delay = <1000>;
2361 2294
2362 thermal-sensors = <&t 2295 thermal-sensors = <&tsens 7>;
2363 2296
2364 trips { 2297 trips {
2365 cpu2_alert: t 2298 cpu2_alert: trip0 {
2366 tempe 2299 temperature = <75000>;
2367 hyste 2300 hysteresis = <2000>;
2368 type 2301 type = "passive";
2369 }; 2302 };
2370 2303
2371 cpu2_crit: tr 2304 cpu2_crit: trip1 {
2372 tempe 2305 temperature = <110000>;
2373 hyste 2306 hysteresis = <2000>;
2374 type 2307 type = "critical";
2375 }; 2308 };
2376 }; 2309 };
2377 2310
2378 cooling-maps { 2311 cooling-maps {
2379 map0 { 2312 map0 {
2380 trip 2313 trip = <&cpu2_alert>;
2381 cooli 2314 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2382 2315 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2383 2316 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2384 2317 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2385 }; 2318 };
2386 }; 2319 };
2387 }; 2320 };
2388 2321
2389 cpu3-thermal { 2322 cpu3-thermal {
2390 polling-delay-passive 2323 polling-delay-passive = <250>;
>> 2324 polling-delay = <1000>;
2391 2325
2392 thermal-sensors = <&t 2326 thermal-sensors = <&tsens 8>;
2393 2327
2394 trips { 2328 trips {
2395 cpu3_alert: t 2329 cpu3_alert: trip0 {
2396 tempe 2330 temperature = <75000>;
2397 hyste 2331 hysteresis = <2000>;
2398 type 2332 type = "passive";
2399 }; 2333 };
2400 2334
2401 cpu3_crit: tr 2335 cpu3_crit: trip1 {
2402 tempe 2336 temperature = <110000>;
2403 hyste 2337 hysteresis = <2000>;
2404 type 2338 type = "critical";
2405 }; 2339 };
2406 }; 2340 };
2407 2341
2408 cooling-maps { 2342 cooling-maps {
2409 map0 { 2343 map0 {
2410 trip 2344 trip = <&cpu3_alert>;
2411 cooli 2345 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2412 2346 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2413 2347 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2414 2348 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2415 }; 2349 };
2416 }; 2350 };
2417 }; 2351 };
2418 2352
2419 cpu4567-thermal { 2353 cpu4567-thermal {
2420 polling-delay-passive 2354 polling-delay-passive = <250>;
>> 2355 polling-delay = <1000>;
2421 2356
2422 thermal-sensors = <&t 2357 thermal-sensors = <&tsens 9>;
2423 2358
2424 trips { 2359 trips {
2425 cpu4567_alert 2360 cpu4567_alert: trip0 {
2426 tempe 2361 temperature = <75000>;
2427 hyste 2362 hysteresis = <2000>;
2428 type 2363 type = "passive";
2429 }; 2364 };
2430 2365
2431 cpu4567_crit: 2366 cpu4567_crit: trip1 {
2432 tempe 2367 temperature = <110000>;
2433 hyste 2368 hysteresis = <2000>;
2434 type 2369 type = "critical";
2435 }; 2370 };
2436 }; 2371 };
2437 2372
2438 cooling-maps { 2373 cooling-maps {
2439 map0 { 2374 map0 {
2440 trip 2375 trip = <&cpu4567_alert>;
2441 cooli 2376 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2442 2377 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2443 2378 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2444 2379 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2445 }; 2380 };
2446 }; 2381 };
2447 }; 2382 };
2448 2383
2449 gpu-thermal { 2384 gpu-thermal {
2450 polling-delay-passive 2385 polling-delay-passive = <250>;
>> 2386 polling-delay = <1000>;
2451 2387
2452 thermal-sensors = <&t 2388 thermal-sensors = <&tsens 3>;
2453 2389
2454 cooling-maps { <<
2455 map0 { <<
2456 trip <<
2457 cooli <<
2458 }; <<
2459 }; <<
2460 <<
2461 trips { 2390 trips {
2462 gpu_alert0: t 2391 gpu_alert0: trip-point0 {
2463 tempe 2392 temperature = <75000>;
2464 hyste 2393 hysteresis = <2000>;
2465 type 2394 type = "passive";
2466 }; 2395 };
2467 2396
2468 gpu_crit: gpu !! 2397 gpu_crit: gpu_crit {
2469 tempe 2398 temperature = <95000>;
2470 hyste 2399 hysteresis = <2000>;
2471 type 2400 type = "critical";
2472 }; 2401 };
2473 }; 2402 };
2474 }; 2403 };
2475 2404
2476 modem1-thermal { 2405 modem1-thermal {
2477 polling-delay-passive 2406 polling-delay-passive = <250>;
>> 2407 polling-delay = <1000>;
2478 2408
2479 thermal-sensors = <&t 2409 thermal-sensors = <&tsens 0>;
2480 2410
2481 trips { 2411 trips {
2482 modem1_alert0 2412 modem1_alert0: trip-point0 {
2483 tempe 2413 temperature = <85000>;
2484 hyste 2414 hysteresis = <2000>;
2485 type 2415 type = "hot";
2486 }; 2416 };
2487 }; 2417 };
2488 }; 2418 };
2489 2419
2490 modem2-thermal { 2420 modem2-thermal {
2491 polling-delay-passive 2421 polling-delay-passive = <250>;
>> 2422 polling-delay = <1000>;
2492 2423
2493 thermal-sensors = <&t 2424 thermal-sensors = <&tsens 2>;
2494 2425
2495 trips { 2426 trips {
2496 modem2_alert0 2427 modem2_alert0: trip-point0 {
2497 tempe 2428 temperature = <85000>;
2498 hyste 2429 hysteresis = <2000>;
2499 type 2430 type = "hot";
2500 }; 2431 };
2501 }; 2432 };
2502 }; 2433 };
2503 2434
2504 camera-thermal { 2435 camera-thermal {
2505 polling-delay-passive 2436 polling-delay-passive = <250>;
>> 2437 polling-delay = <1000>;
2506 2438
2507 thermal-sensors = <&t 2439 thermal-sensors = <&tsens 1>;
2508 2440
2509 trips { 2441 trips {
2510 cam_alert0: t 2442 cam_alert0: trip-point0 {
2511 tempe 2443 temperature = <75000>;
2512 hyste 2444 hysteresis = <2000>;
2513 type 2445 type = "hot";
2514 }; 2446 };
2515 }; 2447 };
2516 }; 2448 };
2517 }; 2449 };
2518 2450
2519 timer { 2451 timer {
2520 compatible = "arm,armv8-timer 2452 compatible = "arm,armv8-timer";
2521 interrupts = <GIC_PPI 2 (GIC_ 2453 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
2522 <GIC_PPI 3 (GIC_ 2454 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
2523 <GIC_PPI 4 (GIC_ 2455 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
2524 <GIC_PPI 1 (GIC_ 2456 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
2525 }; 2457 };
2526 }; 2458 };
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