1 // SPDX-License-Identifier: GPL-2.0-only 1 // SPDX-License-Identifier: GPL-2.0-only
2 /* 2 /*
3 * Copyright (c) 2013-2015, The Linux Foundati 3 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2020-2023, Linaro Limited 4 * Copyright (c) 2020-2023, Linaro Limited
5 */ 5 */
6 6
7 #include <dt-bindings/clock/qcom,gcc-msm8939.h 7 #include <dt-bindings/clock/qcom,gcc-msm8939.h>
8 #include <dt-bindings/clock/qcom,rpmcc.h> 8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/interconnect/qcom,msm893 9 #include <dt-bindings/interconnect/qcom,msm8939.h>
10 #include <dt-bindings/interrupt-controller/arm 10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/power/qcom-rpmpd.h> 11 #include <dt-bindings/power/qcom-rpmpd.h>
12 #include <dt-bindings/reset/qcom,gcc-msm8939.h 12 #include <dt-bindings/reset/qcom,gcc-msm8939.h>
13 #include <dt-bindings/soc/qcom,apr.h> 13 #include <dt-bindings/soc/qcom,apr.h>
14 #include <dt-bindings/thermal/thermal.h> 14 #include <dt-bindings/thermal/thermal.h>
15 15
16 / { 16 / {
17 interrupt-parent = <&intc>; 17 interrupt-parent = <&intc>;
18 18
19 /* 19 /*
20 * Stock LK wants address-cells/size-c 20 * Stock LK wants address-cells/size-cells = 2
21 * A number of our drivers want addres 21 * A number of our drivers want address/size cells = 1
22 * hence the disparity between top-lev 22 * hence the disparity between top-level and /soc below.
23 */ 23 */
24 #address-cells = <2>; 24 #address-cells = <2>;
25 #size-cells = <2>; 25 #size-cells = <2>;
26 26
27 clocks { 27 clocks {
28 xo_board: xo-board { 28 xo_board: xo-board {
29 compatible = "fixed-cl 29 compatible = "fixed-clock";
30 #clock-cells = <0>; 30 #clock-cells = <0>;
31 clock-frequency = <192 31 clock-frequency = <19200000>;
32 }; 32 };
33 33
34 sleep_clk: sleep-clk { 34 sleep_clk: sleep-clk {
35 compatible = "fixed-cl 35 compatible = "fixed-clock";
36 #clock-cells = <0>; 36 #clock-cells = <0>;
37 clock-frequency = <327 37 clock-frequency = <32768>;
38 }; 38 };
39 }; 39 };
40 40
41 cpus { 41 cpus {
42 #address-cells = <1>; 42 #address-cells = <1>;
43 #size-cells = <0>; 43 #size-cells = <0>;
44 44
45 CPU0: cpu@100 { 45 CPU0: cpu@100 {
46 compatible = "arm,cort 46 compatible = "arm,cortex-a53";
47 device_type = "cpu"; 47 device_type = "cpu";
48 enable-method = "spin- 48 enable-method = "spin-table";
49 reg = <0x100>; 49 reg = <0x100>;
50 next-level-cache = <&L 50 next-level-cache = <&L2_1>;
51 qcom,acc = <&acc0>; 51 qcom,acc = <&acc0>;
52 qcom,saw = <&saw0>; 52 qcom,saw = <&saw0>;
53 cpu-idle-states = <&CP 53 cpu-idle-states = <&CPU_SLEEP_0>;
54 clocks = <&apcs1_mbox> 54 clocks = <&apcs1_mbox>;
55 #cooling-cells = <2>; 55 #cooling-cells = <2>;
56 L2_1: l2-cache { 56 L2_1: l2-cache {
57 compatible = " 57 compatible = "cache";
58 cache-level = 58 cache-level = <2>;
59 cache-unified; 59 cache-unified;
60 }; 60 };
61 }; 61 };
62 62
63 CPU1: cpu@101 { 63 CPU1: cpu@101 {
64 compatible = "arm,cort 64 compatible = "arm,cortex-a53";
65 device_type = "cpu"; 65 device_type = "cpu";
66 enable-method = "spin- 66 enable-method = "spin-table";
67 reg = <0x101>; 67 reg = <0x101>;
68 next-level-cache = <&L 68 next-level-cache = <&L2_1>;
69 qcom,acc = <&acc1>; 69 qcom,acc = <&acc1>;
70 qcom,saw = <&saw1>; 70 qcom,saw = <&saw1>;
71 cpu-idle-states = <&CP 71 cpu-idle-states = <&CPU_SLEEP_0>;
72 clocks = <&apcs1_mbox> 72 clocks = <&apcs1_mbox>;
73 #cooling-cells = <2>; 73 #cooling-cells = <2>;
74 }; 74 };
75 75
76 CPU2: cpu@102 { 76 CPU2: cpu@102 {
77 compatible = "arm,cort 77 compatible = "arm,cortex-a53";
78 device_type = "cpu"; 78 device_type = "cpu";
79 enable-method = "spin- 79 enable-method = "spin-table";
80 reg = <0x102>; 80 reg = <0x102>;
81 next-level-cache = <&L 81 next-level-cache = <&L2_1>;
82 qcom,acc = <&acc2>; 82 qcom,acc = <&acc2>;
83 qcom,saw = <&saw2>; 83 qcom,saw = <&saw2>;
84 cpu-idle-states = <&CP 84 cpu-idle-states = <&CPU_SLEEP_0>;
85 clocks = <&apcs1_mbox> 85 clocks = <&apcs1_mbox>;
86 #cooling-cells = <2>; 86 #cooling-cells = <2>;
87 }; 87 };
88 88
89 CPU3: cpu@103 { 89 CPU3: cpu@103 {
90 compatible = "arm,cort 90 compatible = "arm,cortex-a53";
91 device_type = "cpu"; 91 device_type = "cpu";
92 enable-method = "spin- 92 enable-method = "spin-table";
93 reg = <0x103>; 93 reg = <0x103>;
94 next-level-cache = <&L 94 next-level-cache = <&L2_1>;
95 qcom,acc = <&acc3>; 95 qcom,acc = <&acc3>;
96 qcom,saw = <&saw3>; 96 qcom,saw = <&saw3>;
97 cpu-idle-states = <&CP 97 cpu-idle-states = <&CPU_SLEEP_0>;
98 clocks = <&apcs1_mbox> 98 clocks = <&apcs1_mbox>;
99 #cooling-cells = <2>; 99 #cooling-cells = <2>;
100 }; 100 };
101 101
102 CPU4: cpu@0 { 102 CPU4: cpu@0 {
103 compatible = "arm,cort 103 compatible = "arm,cortex-a53";
104 device_type = "cpu"; 104 device_type = "cpu";
105 enable-method = "spin- 105 enable-method = "spin-table";
106 reg = <0x0>; 106 reg = <0x0>;
107 qcom,acc = <&acc4>; 107 qcom,acc = <&acc4>;
108 qcom,saw = <&saw4>; 108 qcom,saw = <&saw4>;
109 cpu-idle-states = <&CP 109 cpu-idle-states = <&CPU_SLEEP_0>;
110 clocks = <&apcs0_mbox> 110 clocks = <&apcs0_mbox>;
111 #cooling-cells = <2>; 111 #cooling-cells = <2>;
112 next-level-cache = <&L 112 next-level-cache = <&L2_0>;
113 L2_0: l2-cache { 113 L2_0: l2-cache {
114 compatible = " 114 compatible = "cache";
115 cache-level = 115 cache-level = <2>;
116 cache-unified; 116 cache-unified;
117 }; 117 };
118 }; 118 };
119 119
120 CPU5: cpu@1 { 120 CPU5: cpu@1 {
121 compatible = "arm,cort 121 compatible = "arm,cortex-a53";
122 device_type = "cpu"; 122 device_type = "cpu";
123 enable-method = "spin- 123 enable-method = "spin-table";
124 reg = <0x1>; 124 reg = <0x1>;
125 next-level-cache = <&L 125 next-level-cache = <&L2_0>;
126 qcom,acc = <&acc5>; 126 qcom,acc = <&acc5>;
127 qcom,saw = <&saw5>; 127 qcom,saw = <&saw5>;
128 cpu-idle-states = <&CP 128 cpu-idle-states = <&CPU_SLEEP_0>;
129 clocks = <&apcs0_mbox> 129 clocks = <&apcs0_mbox>;
130 #cooling-cells = <2>; 130 #cooling-cells = <2>;
131 }; 131 };
132 132
133 CPU6: cpu@2 { 133 CPU6: cpu@2 {
134 compatible = "arm,cort 134 compatible = "arm,cortex-a53";
135 device_type = "cpu"; 135 device_type = "cpu";
136 enable-method = "spin- 136 enable-method = "spin-table";
137 reg = <0x2>; 137 reg = <0x2>;
138 next-level-cache = <&L 138 next-level-cache = <&L2_0>;
139 qcom,acc = <&acc6>; 139 qcom,acc = <&acc6>;
140 qcom,saw = <&saw6>; 140 qcom,saw = <&saw6>;
141 cpu-idle-states = <&CP 141 cpu-idle-states = <&CPU_SLEEP_0>;
142 clocks = <&apcs0_mbox> 142 clocks = <&apcs0_mbox>;
143 #cooling-cells = <2>; 143 #cooling-cells = <2>;
144 }; 144 };
145 145
146 CPU7: cpu@3 { 146 CPU7: cpu@3 {
147 compatible = "arm,cort 147 compatible = "arm,cortex-a53";
148 device_type = "cpu"; 148 device_type = "cpu";
149 enable-method = "spin- 149 enable-method = "spin-table";
150 reg = <0x3>; 150 reg = <0x3>;
151 next-level-cache = <&L 151 next-level-cache = <&L2_0>;
152 qcom,acc = <&acc7>; 152 qcom,acc = <&acc7>;
153 qcom,saw = <&saw7>; 153 qcom,saw = <&saw7>;
154 cpu-idle-states = <&CP 154 cpu-idle-states = <&CPU_SLEEP_0>;
155 clocks = <&apcs0_mbox> 155 clocks = <&apcs0_mbox>;
156 #cooling-cells = <2>; 156 #cooling-cells = <2>;
157 }; 157 };
158 158
159 idle-states { 159 idle-states {
160 CPU_SLEEP_0: cpu-sleep 160 CPU_SLEEP_0: cpu-sleep-0 {
161 compatible = " 161 compatible = "arm,idle-state";
162 entry-latency- 162 entry-latency-us = <130>;
163 exit-latency-u 163 exit-latency-us = <150>;
164 min-residency- 164 min-residency-us = <2000>;
165 local-timer-st 165 local-timer-stop;
166 }; 166 };
167 }; 167 };
168 }; 168 };
169 169
170 /* 170 /*
171 * MSM8939 has a big.LITTLE heterogene 171 * MSM8939 has a big.LITTLE heterogeneous computing architecture,
172 * consisting of two clusters of four 172 * consisting of two clusters of four ARM Cortex-A53s each. The
173 * LITTLE cluster runs at 1.0-1.2GHz, 173 * LITTLE cluster runs at 1.0-1.2GHz, and the big cluster runs
174 * at 1.5-1.7GHz. 174 * at 1.5-1.7GHz.
175 * 175 *
176 * The enable method used here is spin 176 * The enable method used here is spin-table which presupposes use
177 * of a 2nd stage boot shim such as lk 177 * of a 2nd stage boot shim such as lk2nd to have installed a
178 * spin-table, the downstream non-psci 178 * spin-table, the downstream non-psci/non-spin-table method that
179 * default msm8916/msm8936/msm8939 wil 179 * default msm8916/msm8936/msm8939 will not be supported upstream.
180 */ 180 */
181 cpu-map { 181 cpu-map {
182 /* LITTLE (efficiency) cluster 182 /* LITTLE (efficiency) cluster */
183 cluster0 { 183 cluster0 {
184 core0 { 184 core0 {
185 cpu = <&CPU4>; 185 cpu = <&CPU4>;
186 }; 186 };
187 187
188 core1 { 188 core1 {
189 cpu = <&CPU5>; 189 cpu = <&CPU5>;
190 }; 190 };
191 191
192 core2 { 192 core2 {
193 cpu = <&CPU6>; 193 cpu = <&CPU6>;
194 }; 194 };
195 195
196 core3 { 196 core3 {
197 cpu = <&CPU7>; 197 cpu = <&CPU7>;
198 }; 198 };
199 }; 199 };
200 200
201 /* big (performance) cluster * 201 /* big (performance) cluster */
202 /* Boot CPU is cluster 1 core 202 /* Boot CPU is cluster 1 core 0 */
203 cluster1 { 203 cluster1 {
204 core0 { 204 core0 {
205 cpu = <&CPU0>; 205 cpu = <&CPU0>;
206 }; 206 };
207 207
208 core1 { 208 core1 {
209 cpu = <&CPU1>; 209 cpu = <&CPU1>;
210 }; 210 };
211 211
212 core2 { 212 core2 {
213 cpu = <&CPU2>; 213 cpu = <&CPU2>;
214 }; 214 };
215 215
216 core3 { 216 core3 {
217 cpu = <&CPU3>; 217 cpu = <&CPU3>;
218 }; 218 };
219 }; 219 };
220 }; 220 };
221 221
222 firmware { 222 firmware {
223 scm: scm { 223 scm: scm {
224 compatible = "qcom,scm 224 compatible = "qcom,scm-msm8916", "qcom,scm";
225 clocks = <&gcc GCC_CRY 225 clocks = <&gcc GCC_CRYPTO_CLK>,
226 <&gcc GCC_CRY 226 <&gcc GCC_CRYPTO_AXI_CLK>,
227 <&gcc GCC_CRY 227 <&gcc GCC_CRYPTO_AHB_CLK>;
228 clock-names = "core", 228 clock-names = "core", "bus", "iface";
229 #reset-cells = <1>; 229 #reset-cells = <1>;
230 230
231 qcom,dload-mode = <&tc 231 qcom,dload-mode = <&tcsr 0x6100>;
232 }; 232 };
233 }; 233 };
234 234
235 memory@80000000 { 235 memory@80000000 {
236 device_type = "memory"; 236 device_type = "memory";
237 /* We expect the bootloader to 237 /* We expect the bootloader to fill in the reg */
238 reg = <0x0 0x80000000 0x0 0x0> 238 reg = <0x0 0x80000000 0x0 0x0>;
239 }; 239 };
240 240
241 pmu { 241 pmu {
242 compatible = "arm,cortex-a53-p 242 compatible = "arm,cortex-a53-pmu";
243 interrupts = <GIC_PPI 7 (GIC_C 243 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
244 }; 244 };
245 245
246 rpm: remoteproc { 246 rpm: remoteproc {
247 compatible = "qcom,msm8936-rpm 247 compatible = "qcom,msm8936-rpm-proc", "qcom,rpm-proc";
248 248
249 smd-edge { 249 smd-edge {
250 interrupts = <GIC_SPI 250 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
251 qcom,ipc = <&apcs1_mbo 251 qcom,ipc = <&apcs1_mbox 8 0>;
252 qcom,smd-edge = <15>; 252 qcom,smd-edge = <15>;
253 253
254 rpm_requests: rpm-requ 254 rpm_requests: rpm-requests {
255 compatible = " !! 255 compatible = "qcom,rpm-msm8936";
256 qcom,smd-chann 256 qcom,smd-channels = "rpm_requests";
257 257
258 rpmcc: clock-c 258 rpmcc: clock-controller {
259 compat 259 compatible = "qcom,rpmcc-msm8936", "qcom,rpmcc";
260 #clock 260 #clock-cells = <1>;
261 clock- 261 clock-names = "xo";
262 clocks 262 clocks = <&xo_board>;
263 }; 263 };
264 264
265 rpmpd: power-c 265 rpmpd: power-controller {
266 compat 266 compatible = "qcom,msm8939-rpmpd";
267 #power 267 #power-domain-cells = <1>;
268 operat 268 operating-points-v2 = <&rpmpd_opp_table>;
269 269
270 rpmpd_ 270 rpmpd_opp_table: opp-table {
271 271 compatible = "operating-points-v2";
272 272
273 273 rpmpd_opp_ret: opp1 {
274 274 opp-level = <1>;
275 275 };
276 276
277 277 rpmpd_opp_svs_krait: opp2 {
278 278 opp-level = <2>;
279 279 };
280 280
281 281 rpmpd_opp_svs_soc: opp3 {
282 282 opp-level = <3>;
283 283 };
284 284
285 285 rpmpd_opp_nom: opp4 {
286 286 opp-level = <4>;
287 287 };
288 288
289 289 rpmpd_opp_turbo: opp5 {
290 290 opp-level = <5>;
291 291 };
292 292
293 293 rpmpd_opp_super_turbo: opp6 {
294 294 opp-level = <6>;
295 295 };
296 }; 296 };
297 }; 297 };
298 }; 298 };
299 }; 299 };
300 }; 300 };
301 301
302 reserved-memory { 302 reserved-memory {
303 #address-cells = <2>; 303 #address-cells = <2>;
304 #size-cells = <2>; 304 #size-cells = <2>;
305 ranges; 305 ranges;
306 306
307 tz-apps@86000000 { 307 tz-apps@86000000 {
308 reg = <0x0 0x86000000 308 reg = <0x0 0x86000000 0x0 0x300000>;
309 no-map; 309 no-map;
310 }; 310 };
311 311
312 smem@86300000 { 312 smem@86300000 {
313 compatible = "qcom,sme 313 compatible = "qcom,smem";
314 reg = <0x0 0x86300000 314 reg = <0x0 0x86300000 0x0 0x100000>;
315 no-map; 315 no-map;
316 316
317 hwlocks = <&tcsr_mutex 317 hwlocks = <&tcsr_mutex 3>;
318 qcom,rpm-msg-ram = <&r 318 qcom,rpm-msg-ram = <&rpm_msg_ram>;
319 }; 319 };
320 320
321 hypervisor@86400000 { 321 hypervisor@86400000 {
322 reg = <0x0 0x86400000 322 reg = <0x0 0x86400000 0x0 0x100000>;
323 no-map; 323 no-map;
324 }; 324 };
325 325
326 tz@86500000 { 326 tz@86500000 {
327 reg = <0x0 0x86500000 327 reg = <0x0 0x86500000 0x0 0x180000>;
328 no-map; 328 no-map;
329 }; 329 };
330 330
331 reserved@86680000 { 331 reserved@86680000 {
332 reg = <0x0 0x86680000 332 reg = <0x0 0x86680000 0x0 0x80000>;
333 no-map; 333 no-map;
334 }; 334 };
335 335
336 rmtfs@86700000 { 336 rmtfs@86700000 {
337 compatible = "qcom,rmt 337 compatible = "qcom,rmtfs-mem";
338 reg = <0x0 0x86700000 338 reg = <0x0 0x86700000 0x0 0xe0000>;
339 no-map; 339 no-map;
340 340
341 qcom,client-id = <1>; 341 qcom,client-id = <1>;
342 }; 342 };
343 343
344 rfsa@867e0000 { 344 rfsa@867e0000 {
345 reg = <0x0 0x867e0000 345 reg = <0x0 0x867e0000 0x0 0x20000>;
346 no-map; 346 no-map;
347 }; 347 };
348 348
349 mpss_mem: mpss@86800000 { 349 mpss_mem: mpss@86800000 {
350 /* 350 /*
351 * The memory region f 351 * The memory region for the mpss firmware is generally
352 * relocatable and cou 352 * relocatable and could be allocated dynamically.
353 * However, many firmw 353 * However, many firmware versions tend to fail when
354 * loaded to some spec 354 * loaded to some special addresses, so it is hard to
355 * define reliable all 355 * define reliable alloc-ranges.
356 * 356 *
357 * alignment = <0x0 0x 357 * alignment = <0x0 0x400000>;
358 * alloc-ranges = <0x0 358 * alloc-ranges = <0x0 0x86800000 0x0 0x8000000>;
359 */ 359 */
360 reg = <0x0 0x86800000 360 reg = <0x0 0x86800000 0x0 0>; /* size is device-specific */
361 no-map; 361 no-map;
362 status = "disabled"; 362 status = "disabled";
363 }; 363 };
364 364
365 wcnss_mem: wcnss { 365 wcnss_mem: wcnss {
366 size = <0x0 0x600000>; 366 size = <0x0 0x600000>;
367 alignment = <0x0 0x100 367 alignment = <0x0 0x100000>;
368 alloc-ranges = <0x0 0x 368 alloc-ranges = <0x0 0x86800000 0x0 0x8000000>;
369 no-map; 369 no-map;
370 status = "disabled"; 370 status = "disabled";
371 }; 371 };
372 372
373 venus_mem: venus { 373 venus_mem: venus {
374 size = <0x0 0x500000>; 374 size = <0x0 0x500000>;
375 alignment = <0x0 0x100 375 alignment = <0x0 0x100000>;
376 alloc-ranges = <0x0 0x 376 alloc-ranges = <0x0 0x86800000 0x0 0x8000000>;
377 no-map; 377 no-map;
378 status = "disabled"; 378 status = "disabled";
379 }; 379 };
380 380
381 mba_mem: mba { 381 mba_mem: mba {
382 size = <0x0 0x100000>; 382 size = <0x0 0x100000>;
383 alignment = <0x0 0x100 383 alignment = <0x0 0x100000>;
384 alloc-ranges = <0x0 0x 384 alloc-ranges = <0x0 0x86800000 0x0 0x8000000>;
385 no-map; 385 no-map;
386 status = "disabled"; 386 status = "disabled";
387 }; 387 };
388 }; 388 };
389 389
390 smp2p-hexagon { 390 smp2p-hexagon {
391 compatible = "qcom,smp2p"; 391 compatible = "qcom,smp2p";
392 qcom,smem = <435>, <428>; 392 qcom,smem = <435>, <428>;
393 393
394 interrupts = <GIC_SPI 27 IRQ_T 394 interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>;
395 395
396 mboxes = <&apcs1_mbox 14>; 396 mboxes = <&apcs1_mbox 14>;
397 397
398 qcom,local-pid = <0>; 398 qcom,local-pid = <0>;
399 qcom,remote-pid = <1>; 399 qcom,remote-pid = <1>;
400 400
401 hexagon_smp2p_out: master-kern 401 hexagon_smp2p_out: master-kernel {
402 qcom,entry-name = "mas 402 qcom,entry-name = "master-kernel";
403 403
404 #qcom,smem-state-cells 404 #qcom,smem-state-cells = <1>;
405 }; 405 };
406 406
407 hexagon_smp2p_in: slave-kernel 407 hexagon_smp2p_in: slave-kernel {
408 qcom,entry-name = "sla 408 qcom,entry-name = "slave-kernel";
409 409
410 interrupt-controller; 410 interrupt-controller;
411 #interrupt-cells = <2> 411 #interrupt-cells = <2>;
412 }; 412 };
413 }; 413 };
414 414
415 smp2p-wcnss { 415 smp2p-wcnss {
416 compatible = "qcom,smp2p"; 416 compatible = "qcom,smp2p";
417 qcom,smem = <451>, <431>; 417 qcom,smem = <451>, <431>;
418 418
419 interrupts = <GIC_SPI 143 IRQ_ 419 interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>;
420 420
421 mboxes = <&apcs1_mbox 18>; 421 mboxes = <&apcs1_mbox 18>;
422 422
423 qcom,local-pid = <0>; 423 qcom,local-pid = <0>;
424 qcom,remote-pid = <4>; 424 qcom,remote-pid = <4>;
425 425
426 wcnss_smp2p_in: slave-kernel { 426 wcnss_smp2p_in: slave-kernel {
427 qcom,entry-name = "sla 427 qcom,entry-name = "slave-kernel";
428 428
429 interrupt-controller; 429 interrupt-controller;
430 #interrupt-cells = <2> 430 #interrupt-cells = <2>;
431 }; 431 };
432 432
433 wcnss_smp2p_out: master-kernel 433 wcnss_smp2p_out: master-kernel {
434 qcom,entry-name = "mas 434 qcom,entry-name = "master-kernel";
435 435
436 #qcom,smem-state-cells 436 #qcom,smem-state-cells = <1>;
437 }; 437 };
438 }; 438 };
439 439
440 smsm { 440 smsm {
441 compatible = "qcom,smsm"; 441 compatible = "qcom,smsm";
442 442
443 #address-cells = <1>; 443 #address-cells = <1>;
444 #size-cells = <0>; 444 #size-cells = <0>;
445 445
446 mboxes = <0>, <&apcs1_mbox 13> !! 446 qcom,ipc-1 = <&apcs1_mbox 8 13>;
>> 447 qcom,ipc-3 = <&apcs1_mbox 8 19>;
447 448
448 apps_smsm: apps@0 { 449 apps_smsm: apps@0 {
449 reg = <0>; 450 reg = <0>;
450 451
451 #qcom,smem-state-cells 452 #qcom,smem-state-cells = <1>;
452 }; 453 };
453 454
454 hexagon_smsm: hexagon@1 { 455 hexagon_smsm: hexagon@1 {
455 reg = <1>; 456 reg = <1>;
456 interrupts = <GIC_SPI 457 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
457 458
458 interrupt-controller; 459 interrupt-controller;
459 #interrupt-cells = <2> 460 #interrupt-cells = <2>;
460 }; 461 };
461 462
462 wcnss_smsm: wcnss@6 { 463 wcnss_smsm: wcnss@6 {
463 reg = <6>; 464 reg = <6>;
464 interrupts = <GIC_SPI 465 interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>;
465 466
466 interrupt-controller; 467 interrupt-controller;
467 #interrupt-cells = <2> 468 #interrupt-cells = <2>;
468 }; 469 };
469 }; 470 };
470 471
471 soc: soc@0 { 472 soc: soc@0 {
472 compatible = "simple-bus"; 473 compatible = "simple-bus";
473 #address-cells = <1>; 474 #address-cells = <1>;
474 #size-cells = <1>; 475 #size-cells = <1>;
475 ranges = <0 0 0 0xffffffff>; 476 ranges = <0 0 0 0xffffffff>;
476 477
477 rng@22000 { 478 rng@22000 {
478 compatible = "qcom,prn 479 compatible = "qcom,prng";
479 reg = <0x00022000 0x20 480 reg = <0x00022000 0x200>;
480 clocks = <&gcc GCC_PRN 481 clocks = <&gcc GCC_PRNG_AHB_CLK>;
481 clock-names = "core"; 482 clock-names = "core";
482 }; 483 };
483 484
484 qfprom: qfprom@5c000 { 485 qfprom: qfprom@5c000 {
485 compatible = "qcom,msm 486 compatible = "qcom,msm8916-qfprom", "qcom,qfprom";
486 reg = <0x0005c000 0x10 487 reg = <0x0005c000 0x1000>;
487 #address-cells = <1>; 488 #address-cells = <1>;
488 #size-cells = <1>; 489 #size-cells = <1>;
489 490
490 tsens_base1: base1@a0 491 tsens_base1: base1@a0 {
491 reg = <0xa0 0x 492 reg = <0xa0 0x1>;
492 bits = <0 8>; 493 bits = <0 8>;
493 }; 494 };
494 495
495 tsens_s6_p1: s6-p1@a1 496 tsens_s6_p1: s6-p1@a1 {
496 reg = <0xa1 0x 497 reg = <0xa1 0x1>;
497 bits = <0 6>; 498 bits = <0 6>;
498 }; 499 };
499 500
500 tsens_s6_p2: s6-p2@a1 501 tsens_s6_p2: s6-p2@a1 {
501 reg = <0xa1 0x 502 reg = <0xa1 0x2>;
502 bits = <6 6>; 503 bits = <6 6>;
503 }; 504 };
504 505
505 tsens_s7_p1: s7-p1@a2 506 tsens_s7_p1: s7-p1@a2 {
506 reg = <0xa2 0x 507 reg = <0xa2 0x2>;
507 bits = <4 6>; 508 bits = <4 6>;
508 }; 509 };
509 510
510 tsens_s7_p2: s7-p2@a3 511 tsens_s7_p2: s7-p2@a3 {
511 reg = <0xa3 0x 512 reg = <0xa3 0x1>;
512 bits = <2 6>; 513 bits = <2 6>;
513 }; 514 };
514 515
515 tsens_s8_p1: s8-p1@a4 516 tsens_s8_p1: s8-p1@a4 {
516 reg = <0xa4 0x 517 reg = <0xa4 0x1>;
517 bits = <0 6>; 518 bits = <0 6>;
518 }; 519 };
519 520
520 tsens_s8_p2: s8-p2@a4 521 tsens_s8_p2: s8-p2@a4 {
521 reg = <0xa4 0x 522 reg = <0xa4 0x2>;
522 bits = <6 6>; 523 bits = <6 6>;
523 }; 524 };
524 525
525 tsens_s9_p1: s9-p1@a5 526 tsens_s9_p1: s9-p1@a5 {
526 reg = <0xa5 0x 527 reg = <0xa5 0x2>;
527 bits = <4 6>; 528 bits = <4 6>;
528 }; 529 };
529 530
530 tsens_s9_p2: s9-p2@a6 531 tsens_s9_p2: s9-p2@a6 {
531 reg = <0xa6 0x 532 reg = <0xa6 0x1>;
532 bits = <2 6>; 533 bits = <2 6>;
533 }; 534 };
534 535
535 tsens_base2: base2@a7 536 tsens_base2: base2@a7 {
536 reg = <0xa7 0x 537 reg = <0xa7 0x1>;
537 bits = <0 8>; 538 bits = <0 8>;
538 }; 539 };
539 540
540 tsens_mode: mode@d0 { 541 tsens_mode: mode@d0 {
541 reg = <0xd0 0x 542 reg = <0xd0 0x1>;
542 bits = <0 3>; 543 bits = <0 3>;
543 }; 544 };
544 545
545 tsens_s0_p1: s0-p1@d0 546 tsens_s0_p1: s0-p1@d0 {
546 reg = <0xd0 0x 547 reg = <0xd0 0x2>;
547 bits = <3 6>; 548 bits = <3 6>;
548 }; 549 };
549 550
550 tsens_s0_p2: s0-p1@d1 551 tsens_s0_p2: s0-p1@d1 {
551 reg = <0xd1 0x 552 reg = <0xd1 0x1>;
552 bits = <1 6>; 553 bits = <1 6>;
553 }; 554 };
554 555
555 tsens_s1_p1: s1-p1@d1 556 tsens_s1_p1: s1-p1@d1 {
556 reg = <0xd1 0x 557 reg = <0xd1 0x2>;
557 bits = <7 6>; 558 bits = <7 6>;
558 }; 559 };
559 560
560 tsens_s1_p2: s1-p2@d2 561 tsens_s1_p2: s1-p2@d2 {
561 reg = <0xd2 0x 562 reg = <0xd2 0x2>;
562 bits = <5 6>; 563 bits = <5 6>;
563 }; 564 };
564 565
565 tsens_s2_p1: s2-p1@d3 566 tsens_s2_p1: s2-p1@d3 {
566 reg = <0xd3 0x 567 reg = <0xd3 0x2>;
567 bits = <3 6>; 568 bits = <3 6>;
568 }; 569 };
569 570
570 tsens_s2_p2: s2-p2@d4 571 tsens_s2_p2: s2-p2@d4 {
571 reg = <0xd4 0x 572 reg = <0xd4 0x1>;
572 bits = <1 6>; 573 bits = <1 6>;
573 }; 574 };
574 575
575 tsens_s3_p1: s3-p1@d4 576 tsens_s3_p1: s3-p1@d4 {
576 reg = <0xd4 0x 577 reg = <0xd4 0x2>;
577 bits = <7 6>; 578 bits = <7 6>;
578 }; 579 };
579 580
580 tsens_s3_p2: s3-p2@d5 581 tsens_s3_p2: s3-p2@d5 {
581 reg = <0xd5 0x 582 reg = <0xd5 0x2>;
582 bits = <5 6>; 583 bits = <5 6>;
583 }; 584 };
584 585
585 tsens_s5_p1: s5-p1@d6 586 tsens_s5_p1: s5-p1@d6 {
586 reg = <0xd6 0x 587 reg = <0xd6 0x2>;
587 bits = <3 6>; 588 bits = <3 6>;
588 }; 589 };
589 590
590 tsens_s5_p2: s5-p2@d7 591 tsens_s5_p2: s5-p2@d7 {
591 reg = <0xd7 0x 592 reg = <0xd7 0x1>;
592 bits = <1 6>; 593 bits = <1 6>;
593 }; 594 };
594 }; 595 };
595 596
596 rpm_msg_ram: sram@60000 { 597 rpm_msg_ram: sram@60000 {
597 compatible = "qcom,rpm 598 compatible = "qcom,rpm-msg-ram";
598 reg = <0x00060000 0x80 599 reg = <0x00060000 0x8000>;
599 }; 600 };
600 601
601 bimc: interconnect@400000 { 602 bimc: interconnect@400000 {
602 compatible = "qcom,msm 603 compatible = "qcom,msm8939-bimc";
603 reg = <0x00400000 0x62 604 reg = <0x00400000 0x62000>;
604 #interconnect-cells = 605 #interconnect-cells = <1>;
605 }; 606 };
606 607
607 tsens: thermal-sensor@4a9000 { 608 tsens: thermal-sensor@4a9000 {
608 compatible = "qcom,msm 609 compatible = "qcom,msm8939-tsens", "qcom,tsens-v0_1";
609 reg = <0x004a9000 0x10 610 reg = <0x004a9000 0x1000>, /* TM */
610 <0x004a8000 0x10 611 <0x004a8000 0x1000>; /* SROT */
611 nvmem-cells = <&tsens_ 612 nvmem-cells = <&tsens_mode>,
612 <&tsens_ 613 <&tsens_base1>, <&tsens_base2>,
613 <&tsens_ 614 <&tsens_s0_p1>, <&tsens_s0_p2>,
614 <&tsens_ 615 <&tsens_s1_p1>, <&tsens_s1_p2>,
615 <&tsens_ 616 <&tsens_s2_p1>, <&tsens_s2_p2>,
616 <&tsens_ 617 <&tsens_s3_p1>, <&tsens_s3_p2>,
617 <&tsens_ 618 <&tsens_s5_p1>, <&tsens_s5_p2>,
618 <&tsens_ 619 <&tsens_s6_p1>, <&tsens_s6_p2>,
619 <&tsens_ 620 <&tsens_s7_p1>, <&tsens_s7_p2>,
620 <&tsens_ 621 <&tsens_s8_p1>, <&tsens_s8_p2>,
621 <&tsens_ 622 <&tsens_s9_p1>, <&tsens_s9_p2>;
622 nvmem-cell-names = "mo 623 nvmem-cell-names = "mode",
623 "ba 624 "base1", "base2",
624 "s0 625 "s0_p1", "s0_p2",
625 "s1 626 "s1_p1", "s1_p2",
626 "s2 627 "s2_p1", "s2_p2",
627 "s3 628 "s3_p1", "s3_p2",
628 "s5 629 "s5_p1", "s5_p2",
629 "s6 630 "s6_p1", "s6_p2",
630 "s7 631 "s7_p1", "s7_p2",
631 "s8 632 "s8_p1", "s8_p2",
632 "s9 633 "s9_p1", "s9_p2";
633 #qcom,sensors = <9>; 634 #qcom,sensors = <9>;
634 interrupts = <GIC_SPI 635 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
635 interrupt-names = "upl 636 interrupt-names = "uplow";
636 #thermal-sensor-cells 637 #thermal-sensor-cells = <1>;
637 }; 638 };
638 639
639 restart@4ab000 { 640 restart@4ab000 {
640 compatible = "qcom,psh 641 compatible = "qcom,pshold";
641 reg = <0x004ab000 0x4> 642 reg = <0x004ab000 0x4>;
642 }; 643 };
643 644
644 pcnoc: interconnect@500000 { 645 pcnoc: interconnect@500000 {
645 compatible = "qcom,msm 646 compatible = "qcom,msm8939-pcnoc";
646 reg = <0x00500000 0x11 647 reg = <0x00500000 0x11000>;
647 #interconnect-cells = 648 #interconnect-cells = <1>;
648 }; 649 };
649 650
650 snoc: interconnect@580000 { 651 snoc: interconnect@580000 {
651 compatible = "qcom,msm 652 compatible = "qcom,msm8939-snoc";
652 reg = <0x00580000 0x14 653 reg = <0x00580000 0x14080>;
653 #interconnect-cells = 654 #interconnect-cells = <1>;
654 655
655 snoc_mm: interconnect- 656 snoc_mm: interconnect-snoc {
656 compatible = " 657 compatible = "qcom,msm8939-snoc-mm";
657 #interconnect- 658 #interconnect-cells = <1>;
658 }; 659 };
659 }; 660 };
660 661
661 tlmm: pinctrl@1000000 { 662 tlmm: pinctrl@1000000 {
662 compatible = "qcom,msm 663 compatible = "qcom,msm8916-pinctrl";
663 reg = <0x01000000 0x30 664 reg = <0x01000000 0x300000>;
664 interrupts = <GIC_SPI 665 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
665 gpio-controller; 666 gpio-controller;
666 gpio-ranges = <&tlmm 0 667 gpio-ranges = <&tlmm 0 0 122>;
667 #gpio-cells = <2>; 668 #gpio-cells = <2>;
668 interrupt-controller; 669 interrupt-controller;
669 #interrupt-cells = <2> 670 #interrupt-cells = <2>;
670 671
671 blsp_i2c1_default: bls 672 blsp_i2c1_default: blsp-i2c1-default-state {
672 pins = "gpio2" 673 pins = "gpio2", "gpio3";
673 function = "bl 674 function = "blsp_i2c1";
674 drive-strength 675 drive-strength = <2>;
675 bias-disable; 676 bias-disable;
676 }; 677 };
677 678
678 blsp_i2c1_sleep: blsp- 679 blsp_i2c1_sleep: blsp-i2c1-sleep-state {
679 pins = "gpio2" 680 pins = "gpio2", "gpio3";
680 function = "gp 681 function = "gpio";
681 drive-strength 682 drive-strength = <2>;
682 bias-disable; 683 bias-disable;
683 }; 684 };
684 685
685 blsp_i2c2_default: bls 686 blsp_i2c2_default: blsp-i2c2-default-state {
686 pins = "gpio6" 687 pins = "gpio6", "gpio7";
687 function = "bl 688 function = "blsp_i2c2";
688 drive-strength 689 drive-strength = <2>;
689 bias-disable; 690 bias-disable;
690 }; 691 };
691 692
692 blsp_i2c2_sleep: blsp- 693 blsp_i2c2_sleep: blsp-i2c2-sleep-state {
693 pins = "gpio6" 694 pins = "gpio6", "gpio7";
694 function = "gp 695 function = "gpio";
695 drive-strength 696 drive-strength = <2>;
696 bias-disable; 697 bias-disable;
697 }; 698 };
698 699
699 blsp_i2c3_default: bls 700 blsp_i2c3_default: blsp-i2c3-default-state {
700 pins = "gpio10 701 pins = "gpio10", "gpio11";
701 function = "bl 702 function = "blsp_i2c3";
702 drive-strength 703 drive-strength = <2>;
703 bias-disable; 704 bias-disable;
704 }; 705 };
705 706
706 blsp_i2c3_sleep: blsp- 707 blsp_i2c3_sleep: blsp-i2c3-sleep-state {
707 pins = "gpio10 708 pins = "gpio10", "gpio11";
708 function = "gp 709 function = "gpio";
709 drive-strength 710 drive-strength = <2>;
710 bias-disable; 711 bias-disable;
711 }; 712 };
712 713
713 blsp_i2c4_default: bls 714 blsp_i2c4_default: blsp-i2c4-default-state {
714 pins = "gpio14 715 pins = "gpio14", "gpio15";
715 function = "bl 716 function = "blsp_i2c4";
716 drive-strength 717 drive-strength = <2>;
717 bias-disable; 718 bias-disable;
718 }; 719 };
719 720
720 blsp_i2c4_sleep: blsp- 721 blsp_i2c4_sleep: blsp-i2c4-sleep-state {
721 pins = "gpio14 722 pins = "gpio14", "gpio15";
722 function = "gp 723 function = "gpio";
723 drive-strength 724 drive-strength = <2>;
724 bias-disable; 725 bias-disable;
725 }; 726 };
726 727
727 blsp_i2c5_default: bls 728 blsp_i2c5_default: blsp-i2c5-default-state {
728 pins = "gpio18 729 pins = "gpio18", "gpio19";
729 function = "bl 730 function = "blsp_i2c5";
730 drive-strength 731 drive-strength = <2>;
731 bias-disable; 732 bias-disable;
732 }; 733 };
733 734
734 blsp_i2c5_sleep: blsp- 735 blsp_i2c5_sleep: blsp-i2c5-sleep-state {
735 pins = "gpio18 736 pins = "gpio18", "gpio19";
736 function = "gp 737 function = "gpio";
737 drive-strength 738 drive-strength = <2>;
738 bias-disable; 739 bias-disable;
739 }; 740 };
740 741
741 blsp_i2c6_default: bls 742 blsp_i2c6_default: blsp-i2c6-default-state {
742 pins = "gpio22 743 pins = "gpio22", "gpio23";
743 function = "bl 744 function = "blsp_i2c6";
744 drive-strength 745 drive-strength = <2>;
745 bias-disable; 746 bias-disable;
746 }; 747 };
747 748
748 blsp_i2c6_sleep: blsp- 749 blsp_i2c6_sleep: blsp-i2c6-sleep-state {
749 pins = "gpio22 750 pins = "gpio22", "gpio23";
750 function = "gp 751 function = "gpio";
751 drive-strength 752 drive-strength = <2>;
752 bias-disable; 753 bias-disable;
753 }; 754 };
754 755
755 blsp_spi1_default: bls 756 blsp_spi1_default: blsp-spi1-default-state {
756 spi-pins { 757 spi-pins {
757 pins = 758 pins = "gpio0", "gpio1", "gpio3";
758 functi 759 function = "blsp_spi1";
759 drive- 760 drive-strength = <12>;
760 bias-d 761 bias-disable;
761 }; 762 };
762 763
763 cs-pins { 764 cs-pins {
764 pins = 765 pins = "gpio2";
765 functi 766 function = "gpio";
766 drive- 767 drive-strength = <16>;
767 bias-d 768 bias-disable;
768 output 769 output-high;
769 }; 770 };
770 }; 771 };
771 772
772 blsp_spi1_sleep: blsp- 773 blsp_spi1_sleep: blsp-spi1-sleep-state {
773 pins = "gpio0" 774 pins = "gpio0", "gpio1", "gpio2", "gpio3";
774 function = "gp 775 function = "gpio";
775 drive-strength 776 drive-strength = <2>;
776 bias-pull-down 777 bias-pull-down;
777 }; 778 };
778 779
779 blsp_spi2_default: bls 780 blsp_spi2_default: blsp-spi2-default-state {
780 spi-pins { 781 spi-pins {
781 pins = 782 pins = "gpio4", "gpio5", "gpio7";
782 functi 783 function = "blsp_spi2";
783 drive- 784 drive-strength = <12>;
784 bias-d 785 bias-disable;
785 }; 786 };
786 787
787 cs-pins { 788 cs-pins {
788 pins = 789 pins = "gpio6";
789 functi 790 function = "gpio";
790 drive- 791 drive-strength = <16>;
791 bias-d 792 bias-disable;
792 output 793 output-high;
793 }; 794 };
794 }; 795 };
795 796
796 blsp_spi2_sleep: blsp- 797 blsp_spi2_sleep: blsp-spi2-sleep-state {
797 pins = "gpio4" 798 pins = "gpio4", "gpio5", "gpio6", "gpio7";
798 function = "gp 799 function = "gpio";
799 drive-strength 800 drive-strength = <2>;
800 bias-pull-down 801 bias-pull-down;
801 }; 802 };
802 803
803 blsp_spi3_default: bls 804 blsp_spi3_default: blsp-spi3-default-state {
804 spi-pins { 805 spi-pins {
805 pins = 806 pins = "gpio8", "gpio9", "gpio11";
806 functi 807 function = "blsp_spi3";
807 drive- 808 drive-strength = <12>;
808 bias-d 809 bias-disable;
809 }; 810 };
810 811
811 cs-pins { 812 cs-pins {
812 pins = 813 pins = "gpio10";
813 functi 814 function = "gpio";
814 drive- 815 drive-strength = <16>;
815 bias-d 816 bias-disable;
816 output 817 output-high;
817 }; 818 };
818 }; 819 };
819 820
820 blsp_spi3_sleep: blsp- 821 blsp_spi3_sleep: blsp-spi3-sleep-state {
821 pins = "gpio8" 822 pins = "gpio8", "gpio9", "gpio10", "gpio11";
822 function = "gp 823 function = "gpio";
823 drive-strength 824 drive-strength = <2>;
824 bias-pull-down 825 bias-pull-down;
825 }; 826 };
826 827
827 blsp_spi4_default: bls 828 blsp_spi4_default: blsp-spi4-default-state {
828 spi-pins { 829 spi-pins {
829 pins = 830 pins = "gpio12", "gpio13", "gpio15";
830 functi 831 function = "blsp_spi4";
831 drive- 832 drive-strength = <12>;
832 bias-d 833 bias-disable;
833 }; 834 };
834 835
835 cs-pins { 836 cs-pins {
836 pins = 837 pins = "gpio14";
837 functi 838 function = "gpio";
838 drive- 839 drive-strength = <16>;
839 bias-d 840 bias-disable;
840 output 841 output-high;
841 }; 842 };
842 }; 843 };
843 844
844 blsp_spi4_sleep: blsp- 845 blsp_spi4_sleep: blsp-spi4-sleep-state {
845 pins = "gpio12 846 pins = "gpio12", "gpio13", "gpio14", "gpio15";
846 function = "gp 847 function = "gpio";
847 drive-strength 848 drive-strength = <2>;
848 bias-pull-down 849 bias-pull-down;
849 }; 850 };
850 851
851 blsp_spi5_default: bls 852 blsp_spi5_default: blsp-spi5-default-state {
852 spi-pins { 853 spi-pins {
853 pins = 854 pins = "gpio16", "gpio17", "gpio19";
854 functi 855 function = "blsp_spi5";
855 drive- 856 drive-strength = <12>;
856 bias-d 857 bias-disable;
857 }; 858 };
858 859
859 cs-pins { 860 cs-pins {
860 pins = 861 pins = "gpio18";
861 functi 862 function = "gpio";
862 drive- 863 drive-strength = <16>;
863 bias-d 864 bias-disable;
864 output 865 output-high;
865 }; 866 };
866 }; 867 };
867 868
868 blsp_spi5_sleep: blsp- 869 blsp_spi5_sleep: blsp-spi5-sleep-state {
869 pins = "gpio16 870 pins = "gpio16", "gpio17", "gpio18", "gpio19";
870 function = "gp 871 function = "gpio";
871 drive-strength 872 drive-strength = <2>;
872 bias-pull-down 873 bias-pull-down;
873 }; 874 };
874 875
875 blsp_spi6_default: bls 876 blsp_spi6_default: blsp-spi6-default-state {
876 spi-pins { 877 spi-pins {
877 pins = 878 pins = "gpio20", "gpio21", "gpio23";
878 functi 879 function = "blsp_spi6";
879 drive- 880 drive-strength = <12>;
880 bias-d 881 bias-disable;
881 }; 882 };
882 883
883 cs-pins { 884 cs-pins {
884 pins = 885 pins = "gpio22";
885 functi 886 function = "gpio";
886 drive- 887 drive-strength = <16>;
887 bias-d 888 bias-disable;
888 output 889 output-high;
889 }; 890 };
890 }; 891 };
891 892
892 blsp_spi6_sleep: blsp- 893 blsp_spi6_sleep: blsp-spi6-sleep-state {
893 pins = "gpio20 894 pins = "gpio20", "gpio21", "gpio22", "gpio23";
894 function = "gp 895 function = "gpio";
895 drive-strength 896 drive-strength = <2>;
896 bias-pull-down 897 bias-pull-down;
897 }; 898 };
898 899
899 blsp_uart1_default: bl 900 blsp_uart1_default: blsp-uart1-default-state {
900 pins = "gpio0" 901 pins = "gpio0", "gpio1", "gpio2", "gpio3";
901 function = "bl 902 function = "blsp_uart1";
902 drive-strength 903 drive-strength = <16>;
903 bias-disable; 904 bias-disable;
904 }; 905 };
905 906
906 blsp_uart1_sleep: blsp 907 blsp_uart1_sleep: blsp-uart1-sleep-state {
907 pins = "gpio0" 908 pins = "gpio0", "gpio1", "gpio2", "gpio3";
908 function = "gp 909 function = "gpio";
909 drive-strength 910 drive-strength = <2>;
910 bias-pull-down 911 bias-pull-down;
911 }; 912 };
912 913
913 blsp_uart2_default: bl 914 blsp_uart2_default: blsp-uart2-default-state {
914 pins = "gpio4" 915 pins = "gpio4", "gpio5";
915 function = "bl 916 function = "blsp_uart2";
916 drive-strength 917 drive-strength = <16>;
917 bias-disable; 918 bias-disable;
918 }; 919 };
919 920
920 blsp_uart2_sleep: blsp 921 blsp_uart2_sleep: blsp-uart2-sleep-state {
921 pins = "gpio4" 922 pins = "gpio4", "gpio5";
922 function = "gp 923 function = "gpio";
923 drive-strength 924 drive-strength = <2>;
924 bias-pull-down 925 bias-pull-down;
925 }; 926 };
926 927
927 camera_front_default: 928 camera_front_default: camera-front-default-state {
928 pwdn-pins { 929 pwdn-pins {
929 pins = 930 pins = "gpio33";
930 functi 931 function = "gpio";
931 drive- 932 drive-strength = <16>;
932 bias-d 933 bias-disable;
933 }; 934 };
934 935
935 rst-pins { 936 rst-pins {
936 pins = 937 pins = "gpio28";
937 functi 938 function = "gpio";
938 drive- 939 drive-strength = <16>;
939 bias-d 940 bias-disable;
940 }; 941 };
941 942
942 mclk1-pins { 943 mclk1-pins {
943 pins = 944 pins = "gpio27";
944 functi 945 function = "cam_mclk1";
945 drive- 946 drive-strength = <16>;
946 bias-d 947 bias-disable;
947 }; 948 };
948 }; 949 };
949 950
950 camera_rear_default: c 951 camera_rear_default: camera-rear-default-state {
951 pwdn-pins { 952 pwdn-pins {
952 pins = 953 pins = "gpio34";
953 functi 954 function = "gpio";
954 drive- 955 drive-strength = <16>;
955 bias-d 956 bias-disable;
956 }; 957 };
957 958
958 rst-pins { 959 rst-pins {
959 pins = 960 pins = "gpio35";
960 functi 961 function = "gpio";
961 drive- 962 drive-strength = <16>;
962 bias-d 963 bias-disable;
963 }; 964 };
964 965
965 mclk0-pins { 966 mclk0-pins {
966 pins = 967 pins = "gpio26";
967 functi 968 function = "cam_mclk0";
968 drive- 969 drive-strength = <16>;
969 bias-d 970 bias-disable;
970 }; 971 };
971 }; 972 };
972 973
973 cci0_default: cci0-def 974 cci0_default: cci0-default-state {
974 pins = "gpio29 975 pins = "gpio29", "gpio30";
975 function = "cc 976 function = "cci_i2c";
976 drive-strength 977 drive-strength = <16>;
977 bias-disable; 978 bias-disable;
978 }; 979 };
979 980
980 cdc_dmic_default: cdc- 981 cdc_dmic_default: cdc-dmic-default-state {
981 clk-pins { 982 clk-pins {
982 pins = 983 pins = "gpio0";
983 functi 984 function = "dmic0_clk";
984 drive- 985 drive-strength = <8>;
985 }; 986 };
986 987
987 data-pins { 988 data-pins {
988 pins = 989 pins = "gpio1";
989 functi 990 function = "dmic0_data";
990 drive- 991 drive-strength = <8>;
991 }; 992 };
992 }; 993 };
993 994
994 cdc_dmic_sleep: cdc-dm 995 cdc_dmic_sleep: cdc-dmic-sleep-state {
995 clk-pins { 996 clk-pins {
996 pins = 997 pins = "gpio0";
997 functi 998 function = "dmic0_clk";
998 drive- 999 drive-strength = <2>;
999 bias-d 1000 bias-disable;
1000 }; 1001 };
1001 1002
1002 data-pins { 1003 data-pins {
1003 pins 1004 pins = "gpio1";
1004 funct 1005 function = "dmic0_data";
1005 drive 1006 drive-strength = <2>;
1006 bias- 1007 bias-disable;
1007 }; 1008 };
1008 }; 1009 };
1009 1010
1010 cdc_pdm_default: cdc- 1011 cdc_pdm_default: cdc-pdm-default-state {
1011 pins = "gpio6 1012 pins = "gpio63", "gpio64", "gpio65", "gpio66",
1012 "gpio6 1013 "gpio67", "gpio68";
1013 function = "c 1014 function = "cdc_pdm0";
1014 drive-strengt 1015 drive-strength = <8>;
1015 bias-disable; 1016 bias-disable;
1016 }; 1017 };
1017 1018
1018 cdc_pdm_sleep: cdc-pd 1019 cdc_pdm_sleep: cdc-pdm-sleep-state {
1019 pins = "gpio6 1020 pins = "gpio63", "gpio64", "gpio65", "gpio66",
1020 "gpio6 1021 "gpio67", "gpio68";
1021 function = "c 1022 function = "cdc_pdm0";
1022 drive-strengt 1023 drive-strength = <2>;
1023 bias-pull-dow 1024 bias-pull-down;
1024 }; 1025 };
1025 1026
1026 pri_mi2s_default: mi2 1027 pri_mi2s_default: mi2s-pri-default-state {
1027 pins = "gpio1 1028 pins = "gpio113", "gpio114", "gpio115", "gpio116";
1028 function = "p 1029 function = "pri_mi2s";
1029 drive-strengt 1030 drive-strength = <8>;
1030 bias-disable; 1031 bias-disable;
1031 }; 1032 };
1032 1033
1033 pri_mi2s_sleep: mi2s- 1034 pri_mi2s_sleep: mi2s-pri-sleep-state {
1034 pins = "gpio1 1035 pins = "gpio113", "gpio114", "gpio115", "gpio116";
1035 function = "p 1036 function = "pri_mi2s";
1036 drive-strengt 1037 drive-strength = <2>;
1037 bias-disable; 1038 bias-disable;
1038 }; 1039 };
1039 1040
1040 pri_mi2s_mclk_default 1041 pri_mi2s_mclk_default: mi2s-pri-mclk-default-state {
1041 pins = "gpio1 1042 pins = "gpio116";
1042 function = "p 1043 function = "pri_mi2s";
1043 drive-strengt 1044 drive-strength = <8>;
1044 bias-disable; 1045 bias-disable;
1045 }; 1046 };
1046 1047
1047 pri_mi2s_mclk_sleep: 1048 pri_mi2s_mclk_sleep: mi2s-pri-mclk-sleep-state {
1048 pins = "gpio1 1049 pins = "gpio116";
1049 function = "p 1050 function = "pri_mi2s";
1050 drive-strengt 1051 drive-strength = <2>;
1051 bias-disable; 1052 bias-disable;
1052 }; 1053 };
1053 1054
1054 pri_mi2s_ws_default: 1055 pri_mi2s_ws_default: mi2s-pri-ws-default-state {
1055 pins = "gpio1 1056 pins = "gpio110";
1056 function = "p 1057 function = "pri_mi2s_ws";
1057 drive-strengt 1058 drive-strength = <8>;
1058 bias-disable; 1059 bias-disable;
1059 }; 1060 };
1060 1061
1061 pri_mi2s_ws_sleep: mi 1062 pri_mi2s_ws_sleep: mi2s-pri-ws-sleep-state {
1062 pins = "gpio1 1063 pins = "gpio110";
1063 function = "p 1064 function = "pri_mi2s_ws";
1064 drive-strengt 1065 drive-strength = <2>;
1065 bias-disable; 1066 bias-disable;
1066 }; 1067 };
1067 1068
1068 sec_mi2s_default: mi2 1069 sec_mi2s_default: mi2s-sec-default-state {
1069 pins = "gpio1 1070 pins = "gpio112", "gpio117", "gpio118", "gpio119";
1070 function = "s 1071 function = "sec_mi2s";
1071 drive-strengt 1072 drive-strength = <8>;
1072 bias-disable; 1073 bias-disable;
1073 }; 1074 };
1074 1075
1075 sec_mi2s_sleep: mi2s- 1076 sec_mi2s_sleep: mi2s-sec-sleep-state {
1076 pins = "gpio1 1077 pins = "gpio112", "gpio117", "gpio118", "gpio119";
1077 function = "s 1078 function = "sec_mi2s";
1078 drive-strengt 1079 drive-strength = <2>;
1079 bias-disable; 1080 bias-disable;
1080 }; 1081 };
1081 1082
1082 sdc1_default: sdc1-de 1083 sdc1_default: sdc1-default-state {
1083 clk-pins { 1084 clk-pins {
1084 pins 1085 pins = "sdc1_clk";
1085 bias- 1086 bias-disable;
1086 drive 1087 drive-strength = <16>;
1087 }; 1088 };
1088 1089
1089 cmd-pins { 1090 cmd-pins {
1090 pins 1091 pins = "sdc1_cmd";
1091 bias- 1092 bias-pull-up;
1092 drive 1093 drive-strength = <10>;
1093 }; 1094 };
1094 1095
1095 data-pins { 1096 data-pins {
1096 pins 1097 pins = "sdc1_data";
1097 bias- 1098 bias-pull-up;
1098 drive 1099 drive-strength = <10>;
1099 }; 1100 };
1100 }; 1101 };
1101 1102
1102 sdc1_sleep: sdc1-slee 1103 sdc1_sleep: sdc1-sleep-state {
1103 clk-pins { 1104 clk-pins {
1104 pins 1105 pins = "sdc1_clk";
1105 bias- 1106 bias-disable;
1106 drive 1107 drive-strength = <2>;
1107 }; 1108 };
1108 1109
1109 cmd-pins { 1110 cmd-pins {
1110 pins 1111 pins = "sdc1_cmd";
1111 bias- 1112 bias-pull-up;
1112 drive 1113 drive-strength = <2>;
1113 }; 1114 };
1114 1115
1115 data-pins { 1116 data-pins {
1116 pins 1117 pins = "sdc1_data";
1117 bias- 1118 bias-pull-up;
1118 drive 1119 drive-strength = <2>;
1119 }; 1120 };
1120 }; 1121 };
1121 1122
1122 sdc2_default: sdc2-de 1123 sdc2_default: sdc2-default-state {
1123 clk-pins { 1124 clk-pins {
1124 pins 1125 pins = "sdc2_clk";
1125 bias- 1126 bias-disable;
1126 drive 1127 drive-strength = <16>;
1127 }; 1128 };
1128 1129
1129 cmd-pins { 1130 cmd-pins {
1130 pins 1131 pins = "sdc2_cmd";
1131 bias- 1132 bias-pull-up;
1132 drive 1133 drive-strength = <10>;
1133 }; 1134 };
1134 1135
1135 data-pins { 1136 data-pins {
1136 pins 1137 pins = "sdc2_data";
1137 bias- 1138 bias-pull-up;
1138 drive 1139 drive-strength = <10>;
1139 }; 1140 };
1140 }; 1141 };
1141 1142
1142 sdc2_sleep: sdc2-slee 1143 sdc2_sleep: sdc2-sleep-state {
1143 clk-pins { 1144 clk-pins {
1144 pins 1145 pins = "sdc2_clk";
1145 bias- 1146 bias-disable;
1146 drive 1147 drive-strength = <2>;
1147 }; 1148 };
1148 1149
1149 cmd-pins { 1150 cmd-pins {
1150 pins 1151 pins = "sdc2_cmd";
1151 bias- 1152 bias-pull-up;
1152 drive 1153 drive-strength = <2>;
1153 }; 1154 };
1154 1155
1155 data-pins { 1156 data-pins {
1156 pins 1157 pins = "sdc2_data";
1157 bias- 1158 bias-pull-up;
1158 drive 1159 drive-strength = <2>;
1159 }; 1160 };
1160 }; 1161 };
1161 1162
1162 wcss_wlan_default: wc 1163 wcss_wlan_default: wcss-wlan-default-state {
1163 pins = "gpio4 1164 pins = "gpio40", "gpio41", "gpio42", "gpio43", "gpio44";
1164 function = "w 1165 function = "wcss_wlan";
1165 drive-strengt 1166 drive-strength = <6>;
1166 bias-pull-up; 1167 bias-pull-up;
1167 }; 1168 };
1168 }; 1169 };
1169 1170
1170 gcc: clock-controller@1800000 1171 gcc: clock-controller@1800000 {
1171 compatible = "qcom,gc 1172 compatible = "qcom,gcc-msm8939";
1172 reg = <0x01800000 0x8 1173 reg = <0x01800000 0x80000>;
1173 clocks = <&rpmcc RPM_ 1174 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
1174 <&sleep_clk> 1175 <&sleep_clk>,
1175 <&mdss_dsi0_ 1176 <&mdss_dsi0_phy 1>,
1176 <&mdss_dsi0_ 1177 <&mdss_dsi0_phy 0>,
1177 <0>, 1178 <0>,
1178 <0>, 1179 <0>,
1179 <0>; 1180 <0>;
1180 clock-names = "xo", 1181 clock-names = "xo",
1181 "sleep_ 1182 "sleep_clk",
1182 "dsi0pl 1183 "dsi0pll",
1183 "dsi0pl 1184 "dsi0pllbyte",
1184 "ext_mc 1185 "ext_mclk",
1185 "ext_pr 1186 "ext_pri_i2s",
1186 "ext_se 1187 "ext_sec_i2s";
1187 #clock-cells = <1>; 1188 #clock-cells = <1>;
1188 #reset-cells = <1>; 1189 #reset-cells = <1>;
1189 #power-domain-cells = 1190 #power-domain-cells = <1>;
1190 }; 1191 };
1191 1192
1192 tcsr_mutex: hwlock@1905000 { 1193 tcsr_mutex: hwlock@1905000 {
1193 compatible = "qcom,tc 1194 compatible = "qcom,tcsr-mutex";
1194 reg = <0x01905000 0x2 1195 reg = <0x01905000 0x20000>;
1195 #hwlock-cells = <1>; 1196 #hwlock-cells = <1>;
1196 }; 1197 };
1197 1198
1198 tcsr: syscon@1937000 { 1199 tcsr: syscon@1937000 {
1199 compatible = "qcom,tc 1200 compatible = "qcom,tcsr-msm8916", "syscon";
1200 reg = <0x01937000 0x3 1201 reg = <0x01937000 0x30000>;
1201 }; 1202 };
1202 1203
1203 mdss: display-subsystem@1a000 1204 mdss: display-subsystem@1a00000 {
1204 compatible = "qcom,md 1205 compatible = "qcom,mdss";
1205 reg = <0x01a00000 0x1 1206 reg = <0x01a00000 0x1000>,
1206 <0x01ac8000 0x3 1207 <0x01ac8000 0x3000>;
1207 reg-names = "mdss_phy 1208 reg-names = "mdss_phys", "vbif_phys";
1208 1209
1209 interrupts = <GIC_SPI 1210 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1210 interrupt-controller; 1211 interrupt-controller;
1211 1212
1212 clocks = <&gcc GCC_MD 1213 clocks = <&gcc GCC_MDSS_AHB_CLK>,
1213 <&gcc GCC_MD 1214 <&gcc GCC_MDSS_AXI_CLK>,
1214 <&gcc GCC_MD 1215 <&gcc GCC_MDSS_VSYNC_CLK>;
1215 clock-names = "iface" 1216 clock-names = "iface",
1216 "bus", 1217 "bus",
1217 "vsync" 1218 "vsync";
1218 1219
1219 power-domains = <&gcc 1220 power-domains = <&gcc MDSS_GDSC>;
1220 1221
1221 #address-cells = <1>; 1222 #address-cells = <1>;
1222 #size-cells = <1>; 1223 #size-cells = <1>;
1223 #interrupt-cells = <1 1224 #interrupt-cells = <1>;
1224 ranges; 1225 ranges;
1225 1226
1226 status = "disabled"; 1227 status = "disabled";
1227 1228
1228 mdss_mdp: display-con 1229 mdss_mdp: display-controller@1a01000 {
1229 compatible = 1230 compatible = "qcom,mdp5";
1230 reg = <0x01a0 1231 reg = <0x01a01000 0x89000>;
1231 reg-names = " 1232 reg-names = "mdp_phys";
1232 1233
1233 interrupt-par 1234 interrupt-parent = <&mdss>;
1234 interrupts = 1235 interrupts = <0>;
1235 1236
1236 clocks = <&gc 1237 clocks = <&gcc GCC_MDSS_AHB_CLK>,
1237 <&gc 1238 <&gcc GCC_MDSS_AXI_CLK>,
1238 <&gc 1239 <&gcc GCC_MDSS_MDP_CLK>,
1239 <&gc 1240 <&gcc GCC_MDSS_VSYNC_CLK>;
1240 clock-names = 1241 clock-names = "iface",
1241 1242 "bus",
1242 1243 "core",
1243 1244 "vsync";
1244 1245
1245 iommus = <&ap 1246 iommus = <&apps_iommu 4>;
1246 1247
1247 interconnects 1248 interconnects = <&snoc_mm MASTER_MDP_PORT0 &bimc SLAVE_EBI_CH0>,
1248 1249 <&snoc_mm MASTER_MDP_PORT1 &bimc SLAVE_EBI_CH0>;
1249 interconnect- 1250 interconnect-names = "mdp0-mem", "mdp1-mem";
1250 1251
1251 ports { 1252 ports {
1252 #addr 1253 #address-cells = <1>;
1253 #size 1254 #size-cells = <0>;
1254 1255
1255 port@ 1256 port@0 {
1256 1257 reg = <0>;
1257 1258 mdss_mdp_intf1_out: endpoint {
1258 1259 remote-endpoint = <&mdss_dsi0_in>;
1259 1260 };
1260 }; 1261 };
1261 1262
1262 port@ 1263 port@1 {
1263 1264 reg = <1>;
1264 1265 mdss_mdp_intf2_out: endpoint {
1265 1266 remote-endpoint = <&mdss_dsi1_in>;
1266 1267 };
1267 }; 1268 };
1268 }; 1269 };
1269 }; 1270 };
1270 1271
1271 mdss_dsi0: dsi@1a9800 1272 mdss_dsi0: dsi@1a98000 {
1272 compatible = 1273 compatible = "qcom,msm8916-dsi-ctrl",
1273 1274 "qcom,mdss-dsi-ctrl";
1274 reg = <0x01a9 1275 reg = <0x01a98000 0x25c>;
1275 reg-names = " 1276 reg-names = "dsi_ctrl";
1276 1277
1277 interrupt-par 1278 interrupt-parent = <&mdss>;
1278 interrupts = 1279 interrupts = <4>;
1279 1280
1280 clocks = <&gc 1281 clocks = <&gcc GCC_MDSS_MDP_CLK>,
1281 <&gc 1282 <&gcc GCC_MDSS_AHB_CLK>,
1282 <&gc 1283 <&gcc GCC_MDSS_AXI_CLK>,
1283 <&gc 1284 <&gcc GCC_MDSS_BYTE0_CLK>,
1284 <&gc 1285 <&gcc GCC_MDSS_PCLK0_CLK>,
1285 <&gc 1286 <&gcc GCC_MDSS_ESC0_CLK>;
1286 clock-names = 1287 clock-names = "mdp_core",
1287 1288 "iface",
1288 1289 "bus",
1289 1290 "byte",
1290 1291 "pixel",
1291 1292 "core";
1292 assigned-cloc 1293 assigned-clocks = <&gcc BYTE0_CLK_SRC>,
1293 1294 <&gcc PCLK0_CLK_SRC>;
1294 assigned-cloc 1295 assigned-clock-parents = <&mdss_dsi0_phy 0>,
1295 1296 <&mdss_dsi0_phy 1>;
1296 1297
1297 phys = <&mdss 1298 phys = <&mdss_dsi0_phy>;
1298 status = "dis 1299 status = "disabled";
1299 1300
1300 #address-cell 1301 #address-cells = <1>;
1301 #size-cells = 1302 #size-cells = <0>;
1302 1303
1303 ports { 1304 ports {
1304 #addr 1305 #address-cells = <1>;
1305 #size 1306 #size-cells = <0>;
1306 1307
1307 port@ 1308 port@0 {
1308 1309 reg = <0>;
1309 1310 mdss_dsi0_in: endpoint {
1310 1311 remote-endpoint = <&mdss_mdp_intf1_out>;
1311 1312 };
1312 }; 1313 };
1313 1314
1314 port@ 1315 port@1 {
1315 1316 reg = <1>;
1316 1317 mdss_dsi0_out: endpoint {
1317 1318 };
1318 }; 1319 };
1319 }; 1320 };
1320 }; 1321 };
1321 1322
1322 mdss_dsi0_phy: phy@1a 1323 mdss_dsi0_phy: phy@1a98300 {
1323 compatible = 1324 compatible = "qcom,dsi-phy-28nm-lp";
1324 reg = <0x01a9 1325 reg = <0x01a98300 0xd4>,
1325 <0x01a9 1326 <0x01a98500 0x280>,
1326 <0x01a9 1327 <0x01a98780 0x30>;
1327 reg-names = " 1328 reg-names = "dsi_pll",
1328 " 1329 "dsi_phy",
1329 " 1330 "dsi_phy_regulator";
1330 1331
1331 clocks = <&gc 1332 clocks = <&gcc GCC_MDSS_AHB_CLK>,
1332 <&rp 1333 <&rpmcc RPM_SMD_XO_CLK_SRC>;
1333 clock-names = 1334 clock-names = "iface", "ref";
1334 1335
1335 #clock-cells 1336 #clock-cells = <1>;
1336 #phy-cells = 1337 #phy-cells = <0>;
1337 status = "dis 1338 status = "disabled";
1338 }; 1339 };
1339 1340
1340 mdss_dsi1: dsi@1aa000 1341 mdss_dsi1: dsi@1aa0000 {
1341 compatible = 1342 compatible = "qcom,msm8916-dsi-ctrl",
1342 1343 "qcom,mdss-dsi-ctrl";
1343 reg = <0x01aa 1344 reg = <0x01aa0000 0x25c>;
1344 reg-names = " 1345 reg-names = "dsi_ctrl";
1345 1346
1346 interrupt-par 1347 interrupt-parent = <&mdss>;
1347 interrupts = 1348 interrupts = <5>;
1348 1349
1349 clocks = <&gc 1350 clocks = <&gcc GCC_MDSS_MDP_CLK>,
1350 <&gc 1351 <&gcc GCC_MDSS_AHB_CLK>,
1351 <&gc 1352 <&gcc GCC_MDSS_AXI_CLK>,
1352 <&gc 1353 <&gcc GCC_MDSS_BYTE1_CLK>,
1353 <&gc 1354 <&gcc GCC_MDSS_PCLK1_CLK>,
1354 <&gc 1355 <&gcc GCC_MDSS_ESC1_CLK>;
1355 clock-names = 1356 clock-names = "mdp_core",
1356 1357 "iface",
1357 1358 "bus",
1358 1359 "byte",
1359 1360 "pixel",
1360 1361 "core";
1361 assigned-cloc 1362 assigned-clocks = <&gcc BYTE1_CLK_SRC>,
1362 1363 <&gcc PCLK1_CLK_SRC>;
1363 assigned-cloc 1364 assigned-clock-parents = <&mdss_dsi0_phy 0>,
1364 1365 <&mdss_dsi0_phy 1>;
1365 phys = <&mdss 1366 phys = <&mdss_dsi1_phy>;
1366 status = "dis 1367 status = "disabled";
1367 1368
1368 ports { 1369 ports {
1369 #addr 1370 #address-cells = <1>;
1370 #size 1371 #size-cells = <0>;
1371 1372
1372 port@ 1373 port@0 {
1373 1374 reg = <0>;
1374 1375 mdss_dsi1_in: endpoint {
1375 1376 remote-endpoint = <&mdss_mdp_intf2_out>;
1376 1377 };
1377 }; 1378 };
1378 1379
1379 port@ 1380 port@1 {
1380 1381 reg = <1>;
1381 1382 mdss_dsi1_out: endpoint {
1382 1383 };
1383 }; 1384 };
1384 }; 1385 };
1385 }; 1386 };
1386 1387
1387 mdss_dsi1_phy: phy@1a 1388 mdss_dsi1_phy: phy@1aa0300 {
1388 compatible = 1389 compatible = "qcom,dsi-phy-28nm-lp";
1389 reg = <0x01aa 1390 reg = <0x01aa0300 0xd4>,
1390 <0x01aa 1391 <0x01aa0500 0x280>,
1391 <0x01aa 1392 <0x01aa0780 0x30>;
1392 reg-names = " 1393 reg-names = "dsi_pll",
1393 " 1394 "dsi_phy",
1394 " 1395 "dsi_phy_regulator";
1395 1396
1396 clocks = <&gc 1397 clocks = <&gcc GCC_MDSS_AHB_CLK>,
1397 <&rp 1398 <&rpmcc RPM_SMD_XO_CLK_SRC>;
1398 clock-names = 1399 clock-names = "iface", "ref";
1399 1400
1400 #clock-cells 1401 #clock-cells = <1>;
1401 #phy-cells = 1402 #phy-cells = <0>;
1402 status = "dis 1403 status = "disabled";
1403 }; 1404 };
1404 }; 1405 };
1405 1406
1406 gpu: gpu@1c00000 { 1407 gpu: gpu@1c00000 {
1407 compatible = "qcom,ad 1408 compatible = "qcom,adreno-405.0", "qcom,adreno";
1408 reg = <0x01c00000 0x1 1409 reg = <0x01c00000 0x10000>;
1409 reg-names = "kgsl_3d0 1410 reg-names = "kgsl_3d0_reg_memory";
1410 interrupts = <GIC_SPI 1411 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
1411 interrupt-names = "kg 1412 interrupt-names = "kgsl_3d0_irq";
1412 clock-names = "core", 1413 clock-names = "core",
1413 "iface" 1414 "iface",
1414 "mem", 1415 "mem",
1415 "mem_if 1416 "mem_iface",
1416 "alt_me 1417 "alt_mem_iface",
1417 "gfx3d" 1418 "gfx3d",
1418 "rbbmti 1419 "rbbmtimer";
1419 clocks = <&gcc GCC_OX 1420 clocks = <&gcc GCC_OXILI_GFX3D_CLK>,
1420 <&gcc GCC_OX 1421 <&gcc GCC_OXILI_AHB_CLK>,
1421 <&gcc GCC_OX 1422 <&gcc GCC_OXILI_GMEM_CLK>,
1422 <&gcc GCC_BI 1423 <&gcc GCC_BIMC_GFX_CLK>,
1423 <&gcc GCC_BI 1424 <&gcc GCC_BIMC_GPU_CLK>,
1424 <&gcc GFX3D_ 1425 <&gcc GFX3D_CLK_SRC>,
1425 <&gcc GCC_OX 1426 <&gcc GCC_OXILI_TIMER_CLK>;
1426 power-domains = <&gcc 1427 power-domains = <&gcc OXILI_GDSC>;
1427 operating-points-v2 = 1428 operating-points-v2 = <&opp_table>;
1428 iommus = <&gpu_iommu 1429 iommus = <&gpu_iommu 1>, <&gpu_iommu 2>;
1429 #cooling-cells = <2>; <<
1430 <<
1431 status = "disabled"; 1430 status = "disabled";
1432 1431
1433 opp_table: opp-table 1432 opp_table: opp-table {
1434 compatible = 1433 compatible = "operating-points-v2";
1435 1434
1436 opp-550000000 1435 opp-550000000 {
1437 opp-h 1436 opp-hz = /bits/ 64 <550000000>;
1438 }; 1437 };
1439 1438
1440 opp-465000000 1439 opp-465000000 {
1441 opp-h 1440 opp-hz = /bits/ 64 <465000000>;
1442 }; 1441 };
1443 1442
1444 opp-400000000 1443 opp-400000000 {
1445 opp-h 1444 opp-hz = /bits/ 64 <400000000>;
1446 }; 1445 };
1447 1446
1448 opp-220000000 1447 opp-220000000 {
1449 opp-h 1448 opp-hz = /bits/ 64 <220000000>;
1450 }; 1449 };
1451 1450
1452 opp-19200000 1451 opp-19200000 {
1453 opp-h 1452 opp-hz = /bits/ 64 <19200000>;
1454 }; 1453 };
1455 }; 1454 };
1456 }; 1455 };
1457 1456
1458 apps_iommu: iommu@1ef0000 { 1457 apps_iommu: iommu@1ef0000 {
1459 compatible = "qcom,ms 1458 compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
1460 reg = <0x01ef0000 0x3 1459 reg = <0x01ef0000 0x3000>;
1461 ranges = <0 0x01e2000 1460 ranges = <0 0x01e20000 0x20000>;
1462 clocks = <&gcc GCC_SM 1461 clocks = <&gcc GCC_SMMU_CFG_CLK>,
1463 <&gcc GCC_AP 1462 <&gcc GCC_APSS_TCU_CLK>;
1464 clock-names = "iface" 1463 clock-names = "iface", "bus";
1465 #address-cells = <1>; 1464 #address-cells = <1>;
1466 #size-cells = <1>; 1465 #size-cells = <1>;
1467 #iommu-cells = <1>; 1466 #iommu-cells = <1>;
1468 qcom,iommu-secure-id 1467 qcom,iommu-secure-id = <17>;
1469 1468
1470 /* mdp_0: */ 1469 /* mdp_0: */
1471 iommu-ctx@4000 { 1470 iommu-ctx@4000 {
1472 compatible = 1471 compatible = "qcom,msm-iommu-v1-ns";
1473 reg = <0x4000 1472 reg = <0x4000 0x1000>;
1474 interrupts = 1473 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
1475 }; 1474 };
1476 1475
1477 /* venus_ns: */ 1476 /* venus_ns: */
1478 iommu-ctx@5000 { 1477 iommu-ctx@5000 {
1479 compatible = 1478 compatible = "qcom,msm-iommu-v1-sec";
1480 reg = <0x5000 1479 reg = <0x5000 0x1000>;
1481 interrupts = 1480 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
1482 }; 1481 };
1483 }; 1482 };
1484 1483
1485 gpu_iommu: iommu@1f08000 { 1484 gpu_iommu: iommu@1f08000 {
1486 compatible = "qcom,ms 1485 compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
1487 ranges = <0 0x1f08000 1486 ranges = <0 0x1f08000 0x10000>;
1488 clocks = <&gcc GCC_SM 1487 clocks = <&gcc GCC_SMMU_CFG_CLK>,
1489 <&gcc GCC_GF 1488 <&gcc GCC_GFX_TCU_CLK>,
1490 <&gcc GCC_GF 1489 <&gcc GCC_GFX_TBU_CLK>;
1491 clock-names = "iface" 1490 clock-names = "iface", "bus", "tbu";
1492 #address-cells = <1>; 1491 #address-cells = <1>;
1493 #size-cells = <1>; 1492 #size-cells = <1>;
1494 #iommu-cells = <1>; 1493 #iommu-cells = <1>;
1495 qcom,iommu-secure-id 1494 qcom,iommu-secure-id = <18>;
1496 1495
1497 /* gfx3d_user: */ 1496 /* gfx3d_user: */
1498 iommu-ctx@1000 { 1497 iommu-ctx@1000 {
1499 compatible = 1498 compatible = "qcom,msm-iommu-v1-ns";
1500 reg = <0x1000 1499 reg = <0x1000 0x1000>;
1501 interrupts = 1500 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
1502 }; 1501 };
1503 1502
1504 /* gfx3d_priv: */ 1503 /* gfx3d_priv: */
1505 iommu-ctx@2000 { 1504 iommu-ctx@2000 {
1506 compatible = 1505 compatible = "qcom,msm-iommu-v1-ns";
1507 reg = <0x2000 1506 reg = <0x2000 0x1000>;
1508 interrupts = 1507 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
1509 }; 1508 };
1510 }; 1509 };
1511 1510
1512 spmi_bus: spmi@200f000 { 1511 spmi_bus: spmi@200f000 {
1513 compatible = "qcom,sp 1512 compatible = "qcom,spmi-pmic-arb";
1514 reg = <0x0200f000 0x0 1513 reg = <0x0200f000 0x001000>,
1515 <0x02400000 0x4 1514 <0x02400000 0x400000>,
1516 <0x02c00000 0x4 1515 <0x02c00000 0x400000>,
1517 <0x03800000 0x2 1516 <0x03800000 0x200000>,
1518 <0x0200a000 0x0 1517 <0x0200a000 0x002100>;
1519 reg-names = "core", " 1518 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1520 interrupt-names = "pe 1519 interrupt-names = "periph_irq";
1521 interrupts = <GIC_SPI 1520 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
1522 qcom,ee = <0>; 1521 qcom,ee = <0>;
1523 qcom,channel = <0>; 1522 qcom,channel = <0>;
1524 #address-cells = <2>; 1523 #address-cells = <2>;
1525 #size-cells = <0>; 1524 #size-cells = <0>;
1526 interrupt-controller; 1525 interrupt-controller;
1527 #interrupt-cells = <4 1526 #interrupt-cells = <4>;
1528 }; 1527 };
1529 1528
1530 bam_dmux_dma: dma-controller@ 1529 bam_dmux_dma: dma-controller@4044000 {
1531 compatible = "qcom,ba 1530 compatible = "qcom,bam-v1.7.0";
1532 reg = <0x04044000 0x1 1531 reg = <0x04044000 0x19000>;
1533 interrupts = <GIC_SPI 1532 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1534 #dma-cells = <1>; 1533 #dma-cells = <1>;
1535 qcom,ee = <0>; 1534 qcom,ee = <0>;
1536 1535
1537 num-channels = <6>; 1536 num-channels = <6>;
1538 qcom,num-ees = <1>; 1537 qcom,num-ees = <1>;
1539 qcom,powered-remotely 1538 qcom,powered-remotely;
1540 1539
1541 status = "disabled"; 1540 status = "disabled";
1542 }; 1541 };
1543 1542
1544 mpss: remoteproc@4080000 { 1543 mpss: remoteproc@4080000 {
1545 compatible = "qcom,ms 1544 compatible = "qcom,msm8916-mss-pil";
1546 reg = <0x04080000 0x1 1545 reg = <0x04080000 0x100>, <0x04020000 0x040>;
1547 reg-names = "qdsp6", 1546 reg-names = "qdsp6", "rmb";
1548 interrupts-extended = 1547 interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>,
1549 1548 <&hexagon_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1550 1549 <&hexagon_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1551 1550 <&hexagon_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1552 1551 <&hexagon_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1553 interrupt-names = "wd 1552 interrupt-names = "wdog",
1554 "fa 1553 "fatal",
1555 "re 1554 "ready",
1556 "ha 1555 "handover",
1557 "st 1556 "stop-ack";
1558 clocks = <&gcc GCC_MS 1557 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
1559 <&gcc GCC_MS 1558 <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>,
1560 <&gcc GCC_BO 1559 <&gcc GCC_BOOT_ROM_AHB_CLK>,
1561 <&rpmcc RPM_ 1560 <&rpmcc RPM_SMD_XO_CLK_SRC>;
1562 clock-names = "iface" 1561 clock-names = "iface",
1563 "bus", 1562 "bus",
1564 "mem", 1563 "mem",
1565 "xo"; 1564 "xo";
1566 power-domains = <&rpm 1565 power-domains = <&rpmpd MSM8939_VDDMDCX>,
1567 <&rpm 1566 <&rpmpd MSM8939_VDDMX>;
1568 power-domain-names = 1567 power-domain-names = "cx", "mx";
1569 qcom,smem-states = <& 1568 qcom,smem-states = <&hexagon_smp2p_out 0>;
1570 qcom,smem-state-names 1569 qcom,smem-state-names = "stop";
1571 resets = <&scm 0>; 1570 resets = <&scm 0>;
1572 reset-names = "mss_re 1571 reset-names = "mss_restart";
1573 qcom,halt-regs = <&tc 1572 qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>;
1574 status = "disabled"; 1573 status = "disabled";
1575 1574
1576 bam_dmux: bam-dmux { 1575 bam_dmux: bam-dmux {
1577 compatible = 1576 compatible = "qcom,bam-dmux";
1578 1577
1579 interrupt-par 1578 interrupt-parent = <&hexagon_smsm>;
1580 interrupts = 1579 interrupts = <1 IRQ_TYPE_EDGE_BOTH>, <11 IRQ_TYPE_EDGE_BOTH>;
1581 interrupt-nam 1580 interrupt-names = "pc", "pc-ack";
1582 1581
1583 qcom,smem-sta 1582 qcom,smem-states = <&apps_smsm 1>, <&apps_smsm 11>;
1584 qcom,smem-sta 1583 qcom,smem-state-names = "pc", "pc-ack";
1585 1584
1586 dmas = <&bam_ 1585 dmas = <&bam_dmux_dma 4>, <&bam_dmux_dma 5>;
1587 dma-names = " 1586 dma-names = "tx", "rx";
1588 1587
1589 status = "dis 1588 status = "disabled";
1590 }; 1589 };
1591 1590
1592 mba { 1591 mba {
1593 memory-region 1592 memory-region = <&mba_mem>;
1594 }; 1593 };
1595 1594
1596 mpss { 1595 mpss {
1597 memory-region 1596 memory-region = <&mpss_mem>;
1598 }; 1597 };
1599 1598
1600 smd-edge { 1599 smd-edge {
1601 interrupts = 1600 interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>;
1602 1601
1603 qcom,smd-edge 1602 qcom,smd-edge = <0>;
1604 mboxes = <&ap 1603 mboxes = <&apcs1_mbox 12>;
1605 qcom,remote-p 1604 qcom,remote-pid = <1>;
1606 1605
1607 label = "hexa 1606 label = "hexagon";
1608 1607
1609 apr: apr { 1608 apr: apr {
1610 compa 1609 compatible = "qcom,apr-v2";
1611 qcom, 1610 qcom,smd-channels = "apr_audio_svc";
1612 qcom, 1611 qcom,domain = <APR_DOMAIN_ADSP>;
1613 #addr 1612 #address-cells = <1>;
1614 #size 1613 #size-cells = <0>;
1615 statu 1614 status = "disabled";
1616 1615
1617 q6cor 1616 q6core: service@3 {
1618 1617 compatible = "qcom,q6core";
1619 1618 reg = <APR_SVC_ADSP_CORE>;
1620 }; 1619 };
1621 1620
1622 q6afe 1621 q6afe: service@4 {
1623 1622 compatible = "qcom,q6afe";
1624 1623 reg = <APR_SVC_AFE>;
1625 1624
1626 1625 q6afedai: dais {
1627 1626 compatible = "qcom,q6afe-dais";
1628 1627 #address-cells = <1>;
1629 1628 #size-cells = <0>;
1630 1629 #sound-dai-cells = <1>;
1631 1630 };
1632 }; 1631 };
1633 1632
1634 q6asm 1633 q6asm: service@7 {
1635 1634 compatible = "qcom,q6asm";
1636 1635 reg = <APR_SVC_ASM>;
1637 1636
1638 1637 q6asmdai: dais {
1639 1638 compatible = "qcom,q6asm-dais";
1640 1639 #address-cells = <1>;
1641 1640 #size-cells = <0>;
1642 1641 #sound-dai-cells = <1>;
1643 1642 };
1644 }; 1643 };
1645 1644
1646 q6adm 1645 q6adm: service@8 {
1647 1646 compatible = "qcom,q6adm";
1648 1647 reg = <APR_SVC_ADM>;
1649 1648
1650 1649 q6routing: routing {
1651 1650 compatible = "qcom,q6adm-routing";
1652 1651 #sound-dai-cells = <0>;
1653 1652 };
1654 }; 1653 };
1655 }; 1654 };
1656 }; 1655 };
1657 }; 1656 };
1658 1657
1659 sound: sound@7702000 { 1658 sound: sound@7702000 {
1660 compatible = "qcom,ap 1659 compatible = "qcom,apq8016-sbc-sndcard";
1661 reg = <0x07702000 0x4 1660 reg = <0x07702000 0x4>,
1662 <0x07702004 0x4 1661 <0x07702004 0x4>;
1663 reg-names = "mic-iomu 1662 reg-names = "mic-iomux", "spkr-iomux";
1664 status = "disabled"; 1663 status = "disabled";
1665 }; 1664 };
1666 1665
1667 lpass: audio-controller@77080 1666 lpass: audio-controller@7708000 {
1668 compatible = "qcom,ap 1667 compatible = "qcom,apq8016-lpass-cpu";
1669 reg = <0x07708000 0x1 1668 reg = <0x07708000 0x10000>;
1670 reg-names = "lpass-lp 1669 reg-names = "lpass-lpaif";
1671 interrupts = <GIC_SPI 1670 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
1672 interrupt-names = "lp 1671 interrupt-names = "lpass-irq-lpaif";
1673 clocks = <&gcc GCC_UL 1672 clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
1674 <&gcc GCC_UL 1673 <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>,
1675 <&gcc GCC_UL 1674 <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>,
1676 <&gcc GCC_UL 1675 <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>,
1677 <&gcc GCC_UL 1676 <&gcc GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK>,
1678 <&gcc GCC_UL 1677 <&gcc GCC_ULTAUDIO_PCNOC_MPORT_CLK>,
1679 <&gcc GCC_UL 1678 <&gcc GCC_ULTAUDIO_PCNOC_SWAY_CLK>;
1680 clock-names = "ahbix- 1679 clock-names = "ahbix-clk",
1681 "mi2s-b 1680 "mi2s-bit-clk0",
1682 "mi2s-b 1681 "mi2s-bit-clk1",
1683 "mi2s-b 1682 "mi2s-bit-clk2",
1684 "mi2s-b 1683 "mi2s-bit-clk3",
1685 "pcnoc- 1684 "pcnoc-mport-clk",
1686 "pcnoc- 1685 "pcnoc-sway-clk";
1687 #sound-dai-cells = <1 1686 #sound-dai-cells = <1>;
1688 #address-cells = <1>; 1687 #address-cells = <1>;
1689 #size-cells = <0>; 1688 #size-cells = <0>;
1690 status = "disabled"; 1689 status = "disabled";
1691 }; 1690 };
1692 1691
1693 lpass_codec: audio-codec@771c 1692 lpass_codec: audio-codec@771c000 {
1694 compatible = "qcom,ms 1693 compatible = "qcom,msm8916-wcd-digital-codec";
1695 reg = <0x0771c000 0x4 1694 reg = <0x0771c000 0x400>;
1696 clocks = <&gcc GCC_UL 1695 clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
1697 <&gcc GCC_CO 1696 <&gcc GCC_CODEC_DIGCODEC_CLK>;
1698 clock-names = "ahbix- 1697 clock-names = "ahbix-clk", "mclk";
1699 #sound-dai-cells = <1 1698 #sound-dai-cells = <1>;
1700 status = "disabled"; 1699 status = "disabled";
1701 }; 1700 };
1702 1701
1703 sdhc_1: mmc@7824900 { 1702 sdhc_1: mmc@7824900 {
1704 compatible = "qcom,ms 1703 compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4";
1705 reg = <0x07824900 0x1 1704 reg = <0x07824900 0x11c>, <0x07824000 0x800>;
1706 reg-names = "hc", "co 1705 reg-names = "hc", "core";
1707 1706
1708 interrupts = <GIC_SPI 1707 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1709 <GIC_SPI 1708 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
1710 interrupt-names = "hc 1709 interrupt-names = "hc_irq", "pwr_irq";
1711 clocks = <&gcc GCC_SD 1710 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
1712 <&gcc GCC_SD 1711 <&gcc GCC_SDCC1_APPS_CLK>,
1713 <&rpmcc RPM_ 1712 <&rpmcc RPM_SMD_XO_CLK_SRC>;
1714 clock-names = "iface" 1713 clock-names = "iface", "core", "xo";
1715 resets = <&gcc GCC_SD 1714 resets = <&gcc GCC_SDCC1_BCR>;
1716 pinctrl-0 = <&sdc1_de 1715 pinctrl-0 = <&sdc1_default>;
1717 pinctrl-1 = <&sdc1_sl 1716 pinctrl-1 = <&sdc1_sleep>;
1718 pinctrl-names = "defa 1717 pinctrl-names = "default", "sleep";
1719 mmc-ddr-1_8v; 1718 mmc-ddr-1_8v;
1720 bus-width = <8>; 1719 bus-width = <8>;
1721 non-removable; 1720 non-removable;
1722 status = "disabled"; 1721 status = "disabled";
1723 }; 1722 };
1724 1723
1725 sdhc_2: mmc@7864900 { 1724 sdhc_2: mmc@7864900 {
1726 compatible = "qcom,ms 1725 compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4";
1727 reg = <0x07864900 0x1 1726 reg = <0x07864900 0x11c>, <0x07864000 0x800>;
1728 reg-names = "hc", "co 1727 reg-names = "hc", "core";
1729 1728
1730 interrupts = <GIC_SPI 1729 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1731 <GIC_SPI 1730 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
1732 interrupt-names = "hc 1731 interrupt-names = "hc_irq", "pwr_irq";
1733 clocks = <&gcc GCC_SD 1732 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
1734 <&gcc GCC_SD 1733 <&gcc GCC_SDCC2_APPS_CLK>,
1735 <&rpmcc RPM_ 1734 <&rpmcc RPM_SMD_XO_CLK_SRC>;
1736 clock-names = "iface" 1735 clock-names = "iface", "core", "xo";
1737 resets = <&gcc GCC_SD 1736 resets = <&gcc GCC_SDCC2_BCR>;
1738 pinctrl-0 = <&sdc2_de 1737 pinctrl-0 = <&sdc2_default>;
1739 pinctrl-1 = <&sdc2_sl 1738 pinctrl-1 = <&sdc2_sleep>;
1740 pinctrl-names = "defa 1739 pinctrl-names = "default", "sleep";
1741 bus-width = <4>; 1740 bus-width = <4>;
1742 status = "disabled"; 1741 status = "disabled";
1743 }; 1742 };
1744 1743
1745 blsp_dma: dma-controller@7884 1744 blsp_dma: dma-controller@7884000 {
1746 compatible = "qcom,ba 1745 compatible = "qcom,bam-v1.7.0";
1747 reg = <0x07884000 0x2 1746 reg = <0x07884000 0x23000>;
1748 interrupts = <GIC_SPI 1747 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
1749 clocks = <&gcc GCC_BL 1748 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
1750 clock-names = "bam_cl 1749 clock-names = "bam_clk";
1751 #dma-cells = <1>; 1750 #dma-cells = <1>;
1752 qcom,ee = <0>; 1751 qcom,ee = <0>;
1753 qcom,controlled-remot 1752 qcom,controlled-remotely;
1754 }; 1753 };
1755 1754
1756 blsp_uart1: serial@78af000 { 1755 blsp_uart1: serial@78af000 {
1757 compatible = "qcom,ms 1756 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1758 reg = <0x078af000 0x2 1757 reg = <0x078af000 0x200>;
1759 interrupts = <GIC_SPI 1758 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1760 clocks = <&gcc GCC_BL 1759 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
1761 clock-names = "core", 1760 clock-names = "core", "iface";
1762 dmas = <&blsp_dma 0>, 1761 dmas = <&blsp_dma 0>, <&blsp_dma 1>;
1763 dma-names = "tx", "rx 1762 dma-names = "tx", "rx";
1764 pinctrl-0 = <&blsp_ua 1763 pinctrl-0 = <&blsp_uart1_default>;
1765 pinctrl-1 = <&blsp_ua 1764 pinctrl-1 = <&blsp_uart1_sleep>;
1766 pinctrl-names = "defa 1765 pinctrl-names = "default", "sleep";
1767 status = "disabled"; 1766 status = "disabled";
1768 }; 1767 };
1769 1768
1770 blsp_uart2: serial@78b0000 { 1769 blsp_uart2: serial@78b0000 {
1771 compatible = "qcom,ms 1770 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1772 reg = <0x078b0000 0x2 1771 reg = <0x078b0000 0x200>;
1773 interrupts = <GIC_SPI 1772 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1774 clocks = <&gcc GCC_BL 1773 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
1775 clock-names = "core", 1774 clock-names = "core", "iface";
1776 dmas = <&blsp_dma 2>, 1775 dmas = <&blsp_dma 2>, <&blsp_dma 3>;
1777 dma-names = "tx", "rx 1776 dma-names = "tx", "rx";
1778 pinctrl-0 = <&blsp_ua 1777 pinctrl-0 = <&blsp_uart2_default>;
1779 pinctrl-1 = <&blsp_ua 1778 pinctrl-1 = <&blsp_uart2_sleep>;
1780 pinctrl-names = "defa 1779 pinctrl-names = "default", "sleep";
1781 status = "disabled"; 1780 status = "disabled";
1782 }; 1781 };
1783 1782
1784 blsp_i2c1: i2c@78b5000 { 1783 blsp_i2c1: i2c@78b5000 {
1785 compatible = "qcom,i2 1784 compatible = "qcom,i2c-qup-v2.2.1";
1786 reg = <0x078b5000 0x5 1785 reg = <0x078b5000 0x500>;
1787 interrupts = <GIC_SPI 1786 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
1788 clocks = <&gcc GCC_BL 1787 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
1789 <&gcc GCC_BL 1788 <&gcc GCC_BLSP1_AHB_CLK>;
1790 clock-names = "core", 1789 clock-names = "core", "iface";
1791 dmas = <&blsp_dma 4>, 1790 dmas = <&blsp_dma 4>, <&blsp_dma 5>;
1792 dma-names = "tx", "rx 1791 dma-names = "tx", "rx";
1793 pinctrl-0 = <&blsp_i2 1792 pinctrl-0 = <&blsp_i2c1_default>;
1794 pinctrl-1 = <&blsp_i2 1793 pinctrl-1 = <&blsp_i2c1_sleep>;
1795 pinctrl-names = "defa 1794 pinctrl-names = "default", "sleep";
1796 #address-cells = <1>; 1795 #address-cells = <1>;
1797 #size-cells = <0>; 1796 #size-cells = <0>;
1798 status = "disabled"; 1797 status = "disabled";
1799 }; 1798 };
1800 1799
1801 blsp_spi1: spi@78b5000 { 1800 blsp_spi1: spi@78b5000 {
1802 compatible = "qcom,sp 1801 compatible = "qcom,spi-qup-v2.2.1";
1803 reg = <0x078b5000 0x5 1802 reg = <0x078b5000 0x500>;
1804 interrupts = <GIC_SPI 1803 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
1805 clocks = <&gcc GCC_BL 1804 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
1806 <&gcc GCC_BL 1805 <&gcc GCC_BLSP1_AHB_CLK>;
1807 clock-names = "core", 1806 clock-names = "core", "iface";
1808 dmas = <&blsp_dma 4>, 1807 dmas = <&blsp_dma 4>, <&blsp_dma 5>;
1809 dma-names = "tx", "rx 1808 dma-names = "tx", "rx";
1810 pinctrl-0 = <&blsp_sp 1809 pinctrl-0 = <&blsp_spi1_default>;
1811 pinctrl-1 = <&blsp_sp 1810 pinctrl-1 = <&blsp_spi1_sleep>;
1812 pinctrl-names = "defa 1811 pinctrl-names = "default", "sleep";
1813 #address-cells = <1>; 1812 #address-cells = <1>;
1814 #size-cells = <0>; 1813 #size-cells = <0>;
1815 status = "disabled"; 1814 status = "disabled";
1816 }; 1815 };
1817 1816
1818 blsp_i2c2: i2c@78b6000 { 1817 blsp_i2c2: i2c@78b6000 {
1819 compatible = "qcom,i2 1818 compatible = "qcom,i2c-qup-v2.2.1";
1820 reg = <0x078b6000 0x5 1819 reg = <0x078b6000 0x500>;
1821 interrupts = <GIC_SPI 1820 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1822 clocks = <&gcc GCC_BL 1821 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
1823 <&gcc GCC_BL 1822 <&gcc GCC_BLSP1_AHB_CLK>;
1824 clock-names = "core", 1823 clock-names = "core", "iface";
1825 dmas = <&blsp_dma 6>, 1824 dmas = <&blsp_dma 6>, <&blsp_dma 7>;
1826 dma-names = "tx", "rx 1825 dma-names = "tx", "rx";
1827 pinctrl-0 = <&blsp_i2 1826 pinctrl-0 = <&blsp_i2c2_default>;
1828 pinctrl-1 = <&blsp_i2 1827 pinctrl-1 = <&blsp_i2c2_sleep>;
1829 pinctrl-names = "defa 1828 pinctrl-names = "default", "sleep";
1830 #address-cells = <1>; 1829 #address-cells = <1>;
1831 #size-cells = <0>; 1830 #size-cells = <0>;
1832 status = "disabled"; 1831 status = "disabled";
1833 }; 1832 };
1834 1833
1835 blsp_spi2: spi@78b6000 { 1834 blsp_spi2: spi@78b6000 {
1836 compatible = "qcom,sp 1835 compatible = "qcom,spi-qup-v2.2.1";
1837 reg = <0x078b6000 0x5 1836 reg = <0x078b6000 0x500>;
1838 interrupts = <GIC_SPI 1837 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1839 clocks = <&gcc GCC_BL 1838 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
1840 <&gcc GCC_BL 1839 <&gcc GCC_BLSP1_AHB_CLK>;
1841 clock-names = "core", 1840 clock-names = "core", "iface";
1842 dmas = <&blsp_dma 6>, 1841 dmas = <&blsp_dma 6>, <&blsp_dma 7>;
1843 dma-names = "tx", "rx 1842 dma-names = "tx", "rx";
1844 pinctrl-0 = <&blsp_sp 1843 pinctrl-0 = <&blsp_spi2_default>;
1845 pinctrl-1 = <&blsp_sp 1844 pinctrl-1 = <&blsp_spi2_sleep>;
1846 pinctrl-names = "defa 1845 pinctrl-names = "default", "sleep";
1847 #address-cells = <1>; 1846 #address-cells = <1>;
1848 #size-cells = <0>; 1847 #size-cells = <0>;
1849 status = "disabled"; 1848 status = "disabled";
1850 }; 1849 };
1851 1850
1852 blsp_i2c3: i2c@78b7000 { 1851 blsp_i2c3: i2c@78b7000 {
1853 compatible = "qcom,i2 1852 compatible = "qcom,i2c-qup-v2.2.1";
1854 reg = <0x078b7000 0x5 1853 reg = <0x078b7000 0x500>;
1855 interrupts = <GIC_SPI 1854 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1856 clocks = <&gcc GCC_BL 1855 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
1857 <&gcc GCC_BL 1856 <&gcc GCC_BLSP1_AHB_CLK>;
1858 clock-names = "core", 1857 clock-names = "core", "iface";
1859 dmas = <&blsp_dma 8>, 1858 dmas = <&blsp_dma 8>, <&blsp_dma 9>;
1860 dma-names = "tx", "rx 1859 dma-names = "tx", "rx";
1861 pinctrl-0 = <&blsp_i2 1860 pinctrl-0 = <&blsp_i2c3_default>;
1862 pinctrl-1 = <&blsp_i2 1861 pinctrl-1 = <&blsp_i2c3_sleep>;
1863 pinctrl-names = "defa 1862 pinctrl-names = "default", "sleep";
1864 #address-cells = <1>; 1863 #address-cells = <1>;
1865 #size-cells = <0>; 1864 #size-cells = <0>;
1866 status = "disabled"; 1865 status = "disabled";
1867 }; 1866 };
1868 1867
1869 blsp_spi3: spi@78b7000 { 1868 blsp_spi3: spi@78b7000 {
1870 compatible = "qcom,sp 1869 compatible = "qcom,spi-qup-v2.2.1";
1871 reg = <0x078b7000 0x5 1870 reg = <0x078b7000 0x500>;
1872 interrupts = <GIC_SPI 1871 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1873 clocks = <&gcc GCC_BL 1872 clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
1874 <&gcc GCC_BL 1873 <&gcc GCC_BLSP1_AHB_CLK>;
1875 clock-names = "core", 1874 clock-names = "core", "iface";
1876 dmas = <&blsp_dma 8>, 1875 dmas = <&blsp_dma 8>, <&blsp_dma 9>;
1877 dma-names = "tx", "rx 1876 dma-names = "tx", "rx";
1878 pinctrl-0 = <&blsp_sp 1877 pinctrl-0 = <&blsp_spi3_default>;
1879 pinctrl-1 = <&blsp_sp 1878 pinctrl-1 = <&blsp_spi3_sleep>;
1880 pinctrl-names = "defa 1879 pinctrl-names = "default", "sleep";
1881 #address-cells = <1>; 1880 #address-cells = <1>;
1882 #size-cells = <0>; 1881 #size-cells = <0>;
1883 status = "disabled"; 1882 status = "disabled";
1884 }; 1883 };
1885 1884
1886 blsp_i2c4: i2c@78b8000 { 1885 blsp_i2c4: i2c@78b8000 {
1887 compatible = "qcom,i2 1886 compatible = "qcom,i2c-qup-v2.2.1";
1888 reg = <0x078b8000 0x5 1887 reg = <0x078b8000 0x500>;
1889 interrupts = <GIC_SPI 1888 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1890 clocks = <&gcc GCC_BL 1889 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
1891 <&gcc GCC_BL 1890 <&gcc GCC_BLSP1_AHB_CLK>;
1892 clock-names = "core", 1891 clock-names = "core", "iface";
1893 dmas = <&blsp_dma 10> 1892 dmas = <&blsp_dma 10>, <&blsp_dma 11>;
1894 dma-names = "tx", "rx 1893 dma-names = "tx", "rx";
1895 pinctrl-0 = <&blsp_i2 1894 pinctrl-0 = <&blsp_i2c4_default>;
1896 pinctrl-1 = <&blsp_i2 1895 pinctrl-1 = <&blsp_i2c4_sleep>;
1897 pinctrl-names = "defa 1896 pinctrl-names = "default", "sleep";
1898 #address-cells = <1>; 1897 #address-cells = <1>;
1899 #size-cells = <0>; 1898 #size-cells = <0>;
1900 status = "disabled"; 1899 status = "disabled";
1901 }; 1900 };
1902 1901
1903 blsp_spi4: spi@78b8000 { 1902 blsp_spi4: spi@78b8000 {
1904 compatible = "qcom,sp 1903 compatible = "qcom,spi-qup-v2.2.1";
1905 reg = <0x078b8000 0x5 1904 reg = <0x078b8000 0x500>;
1906 interrupts = <GIC_SPI 1905 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1907 clocks = <&gcc GCC_BL 1906 clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
1908 <&gcc GCC_BL 1907 <&gcc GCC_BLSP1_AHB_CLK>;
1909 clock-names = "core", 1908 clock-names = "core", "iface";
1910 dmas = <&blsp_dma 10> 1909 dmas = <&blsp_dma 10>, <&blsp_dma 11>;
1911 dma-names = "tx", "rx 1910 dma-names = "tx", "rx";
1912 pinctrl-0 = <&blsp_sp 1911 pinctrl-0 = <&blsp_spi4_default>;
1913 pinctrl-1 = <&blsp_sp 1912 pinctrl-1 = <&blsp_spi4_sleep>;
1914 pinctrl-names = "defa 1913 pinctrl-names = "default", "sleep";
1915 #address-cells = <1>; 1914 #address-cells = <1>;
1916 #size-cells = <0>; 1915 #size-cells = <0>;
1917 status = "disabled"; 1916 status = "disabled";
1918 }; 1917 };
1919 1918
1920 blsp_i2c5: i2c@78b9000 { 1919 blsp_i2c5: i2c@78b9000 {
1921 compatible = "qcom,i2 1920 compatible = "qcom,i2c-qup-v2.2.1";
1922 reg = <0x078b9000 0x5 1921 reg = <0x078b9000 0x500>;
1923 interrupts = <GIC_SPI 1922 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
1924 clocks = <&gcc GCC_BL 1923 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
1925 <&gcc GCC_BL 1924 <&gcc GCC_BLSP1_AHB_CLK>;
1926 clock-names = "core", 1925 clock-names = "core", "iface";
1927 dmas = <&blsp_dma 12> 1926 dmas = <&blsp_dma 12>, <&blsp_dma 13>;
1928 dma-names = "tx", "rx 1927 dma-names = "tx", "rx";
1929 pinctrl-0 = <&blsp_i2 1928 pinctrl-0 = <&blsp_i2c5_default>;
1930 pinctrl-1 = <&blsp_i2 1929 pinctrl-1 = <&blsp_i2c5_sleep>;
1931 pinctrl-names = "defa 1930 pinctrl-names = "default", "sleep";
1932 #address-cells = <1>; 1931 #address-cells = <1>;
1933 #size-cells = <0>; 1932 #size-cells = <0>;
1934 status = "disabled"; 1933 status = "disabled";
1935 }; 1934 };
1936 1935
1937 blsp_spi5: spi@78b9000 { 1936 blsp_spi5: spi@78b9000 {
1938 compatible = "qcom,sp 1937 compatible = "qcom,spi-qup-v2.2.1";
1939 reg = <0x078b9000 0x5 1938 reg = <0x078b9000 0x500>;
1940 interrupts = <GIC_SPI 1939 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
1941 clocks = <&gcc GCC_BL 1940 clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
1942 <&gcc GCC_BL 1941 <&gcc GCC_BLSP1_AHB_CLK>;
1943 clock-names = "core", 1942 clock-names = "core", "iface";
1944 dmas = <&blsp_dma 12> 1943 dmas = <&blsp_dma 12>, <&blsp_dma 13>;
1945 dma-names = "tx", "rx 1944 dma-names = "tx", "rx";
1946 pinctrl-0 = <&blsp_sp 1945 pinctrl-0 = <&blsp_spi5_default>;
1947 pinctrl-1 = <&blsp_sp 1946 pinctrl-1 = <&blsp_spi5_sleep>;
1948 pinctrl-names = "defa 1947 pinctrl-names = "default", "sleep";
1949 #address-cells = <1>; 1948 #address-cells = <1>;
1950 #size-cells = <0>; 1949 #size-cells = <0>;
1951 status = "disabled"; 1950 status = "disabled";
1952 }; 1951 };
1953 1952
1954 blsp_i2c6: i2c@78ba000 { 1953 blsp_i2c6: i2c@78ba000 {
1955 compatible = "qcom,i2 1954 compatible = "qcom,i2c-qup-v2.2.1";
1956 reg = <0x078ba000 0x5 1955 reg = <0x078ba000 0x500>;
1957 interrupts = <GIC_SPI 1956 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
1958 clocks = <&gcc GCC_BL 1957 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
1959 <&gcc GCC_BL 1958 <&gcc GCC_BLSP1_AHB_CLK>;
1960 clock-names = "core", 1959 clock-names = "core", "iface";
1961 dmas = <&blsp_dma 14> 1960 dmas = <&blsp_dma 14>, <&blsp_dma 15>;
1962 dma-names = "tx", "rx 1961 dma-names = "tx", "rx";
1963 pinctrl-0 = <&blsp_i2 1962 pinctrl-0 = <&blsp_i2c6_default>;
1964 pinctrl-1 = <&blsp_i2 1963 pinctrl-1 = <&blsp_i2c6_sleep>;
1965 pinctrl-names = "defa 1964 pinctrl-names = "default", "sleep";
1966 #address-cells = <1>; 1965 #address-cells = <1>;
1967 #size-cells = <0>; 1966 #size-cells = <0>;
1968 status = "disabled"; 1967 status = "disabled";
1969 }; 1968 };
1970 1969
1971 blsp_spi6: spi@78ba000 { 1970 blsp_spi6: spi@78ba000 {
1972 compatible = "qcom,sp 1971 compatible = "qcom,spi-qup-v2.2.1";
1973 reg = <0x078ba000 0x5 1972 reg = <0x078ba000 0x500>;
1974 interrupts = <GIC_SPI 1973 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
1975 clocks = <&gcc GCC_BL 1974 clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>,
1976 <&gcc GCC_BL 1975 <&gcc GCC_BLSP1_AHB_CLK>;
1977 clock-names = "core", 1976 clock-names = "core", "iface";
1978 dmas = <&blsp_dma 14> 1977 dmas = <&blsp_dma 14>, <&blsp_dma 15>;
1979 dma-names = "tx", "rx 1978 dma-names = "tx", "rx";
1980 pinctrl-0 = <&blsp_sp 1979 pinctrl-0 = <&blsp_spi6_default>;
1981 pinctrl-1 = <&blsp_sp 1980 pinctrl-1 = <&blsp_spi6_sleep>;
1982 pinctrl-names = "defa 1981 pinctrl-names = "default", "sleep";
1983 #address-cells = <1>; 1982 #address-cells = <1>;
1984 #size-cells = <0>; 1983 #size-cells = <0>;
1985 status = "disabled"; 1984 status = "disabled";
1986 }; 1985 };
1987 1986
1988 usb: usb@78d9000 { 1987 usb: usb@78d9000 {
1989 compatible = "qcom,ci 1988 compatible = "qcom,ci-hdrc";
1990 reg = <0x078d9000 0x2 1989 reg = <0x078d9000 0x200>,
1991 <0x078d9200 0x2 1990 <0x078d9200 0x200>;
1992 interrupts = <GIC_SPI 1991 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
1993 <GIC_SPI 1992 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
1994 clocks = <&gcc GCC_US 1993 clocks = <&gcc GCC_USB_HS_AHB_CLK>,
1995 <&gcc GCC_US 1994 <&gcc GCC_USB_HS_SYSTEM_CLK>;
1996 clock-names = "iface" 1995 clock-names = "iface", "core";
1997 assigned-clocks = <&g 1996 assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>;
1998 assigned-clock-rates 1997 assigned-clock-rates = <80000000>;
1999 resets = <&gcc GCC_US 1998 resets = <&gcc GCC_USB_HS_BCR>;
2000 reset-names = "core"; 1999 reset-names = "core";
2001 #reset-cells = <1>; 2000 #reset-cells = <1>;
2002 phy_type = "ulpi"; 2001 phy_type = "ulpi";
2003 dr_mode = "otg"; 2002 dr_mode = "otg";
2004 adp-disable; 2003 adp-disable;
2005 hnp-disable; 2004 hnp-disable;
2006 srp-disable; 2005 srp-disable;
2007 ahb-burst-config = <0 2006 ahb-burst-config = <0>;
2008 phy-names = "usb-phy" 2007 phy-names = "usb-phy";
2009 phys = <&usb_hs_phy>; 2008 phys = <&usb_hs_phy>;
2010 status = "disabled"; 2009 status = "disabled";
2011 2010
2012 ulpi { 2011 ulpi {
2013 usb_hs_phy: p 2012 usb_hs_phy: phy {
2014 compa 2013 compatible = "qcom,usb-hs-phy-msm8916",
2015 2014 "qcom,usb-hs-phy";
2016 clock 2015 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
2017 2016 <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
2018 clock 2017 clock-names = "ref", "sleep";
2019 reset 2018 resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>;
2020 reset 2019 reset-names = "phy", "por";
2021 #phy- 2020 #phy-cells = <0>;
2022 qcom, 2021 qcom,init-seq = /bits/ 8 <0x0 0x44>,
2023 2022 <0x1 0x6b>,
2024 2023 <0x2 0x24>,
2025 2024 <0x3 0x13>;
2026 }; 2025 };
2027 }; 2026 };
2028 }; 2027 };
2029 2028
2030 wcnss: remoteproc@a204000 { 2029 wcnss: remoteproc@a204000 {
2031 compatible = "qcom,pr 2030 compatible = "qcom,pronto-v2-pil", "qcom,pronto";
2032 interrupts-extended = 2031 interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>,
2033 2032 <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2034 2033 <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2035 2034 <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2036 2035 <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
2037 interrupt-names = "wd 2036 interrupt-names = "wdog",
2038 "fa 2037 "fatal",
2039 "re 2038 "ready",
2040 "ha 2039 "handover",
2041 "st 2040 "stop-ack";
2042 reg = <0x0a204000 0x2 2041 reg = <0x0a204000 0x2000>,
2043 <0x0a202000 0x1 2042 <0x0a202000 0x1000>,
2044 <0x0a21b000 0x3 2043 <0x0a21b000 0x3000>;
2045 reg-names = "ccu", "d 2044 reg-names = "ccu", "dxe", "pmu";
2046 2045
2047 memory-region = <&wcn 2046 memory-region = <&wcnss_mem>;
2048 2047
2049 power-domains = <&rpm 2048 power-domains = <&rpmpd MSM8939_VDDCX>,
2050 <&rpm 2049 <&rpmpd MSM8939_VDDMX>;
2051 power-domain-names = 2050 power-domain-names = "cx", "mx";
2052 2051
2053 qcom,smem-states = <& 2052 qcom,smem-states = <&wcnss_smp2p_out 0>;
2054 qcom,smem-state-names 2053 qcom,smem-state-names = "stop";
2055 2054
2056 pinctrl-names = "defa 2055 pinctrl-names = "default";
2057 pinctrl-0 = <&wcss_wl 2056 pinctrl-0 = <&wcss_wlan_default>;
2058 2057
2059 status = "disabled"; 2058 status = "disabled";
2060 2059
2061 wcnss_iris: iris { 2060 wcnss_iris: iris {
2062 /* Separate c 2061 /* Separate chip, compatible is board-specific */
2063 clocks = <&rp 2062 clocks = <&rpmcc RPM_SMD_RF_CLK2>;
2064 clock-names = 2063 clock-names = "xo";
2065 }; 2064 };
2066 2065
2067 smd-edge { 2066 smd-edge {
2068 interrupts = 2067 interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>;
2069 mboxes = <&ap !! 2068 qcom,ipc = <&apcs1_mbox 8 17>;
2070 qcom,smd-edge 2069 qcom,smd-edge = <6>;
2071 qcom,remote-p 2070 qcom,remote-pid = <4>;
2072 2071
2073 label = "pron 2072 label = "pronto";
2074 2073
2075 wcnss { 2074 wcnss {
2076 compa 2075 compatible = "qcom,wcnss";
2077 qcom, 2076 qcom,smd-channels = "WCNSS_CTRL";
2078 2077
2079 qcom, 2078 qcom,mmio = <&wcnss>;
2080 2079
2081 wcnss 2080 wcnss_bt: bluetooth {
2082 2081 compatible = "qcom,wcnss-bt";
2083 }; 2082 };
2084 2083
2085 wcnss 2084 wcnss_wifi: wifi {
2086 2085 compatible = "qcom,wcnss-wlan";
2087 2086
2088 2087 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
2089 2088 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
2090 2089 interrupt-names = "tx", "rx";
2091 2090
2092 2091 qcom,smem-states = <&apps_smsm 10>,
2093 2092 <&apps_smsm 9>;
2094 2093 qcom,smem-state-names = "tx-enable",
2095 2094 "tx-rings-empty";
2096 }; 2095 };
2097 }; 2096 };
2098 }; 2097 };
2099 }; 2098 };
2100 2099
2101 intc: interrupt-controller@b0 2100 intc: interrupt-controller@b000000 {
2102 compatible = "qcom,ms 2101 compatible = "qcom,msm-qgic2";
2103 reg = <0x0b000000 0x1 2102 reg = <0x0b000000 0x1000>, <0x0b002000 0x2000>,
2104 <0x0b001000 0x1 2103 <0x0b001000 0x1000>, <0x0b004000 0x2000>;
2105 interrupt-controller; 2104 interrupt-controller;
2106 #interrupt-cells = <3 2105 #interrupt-cells = <3>;
2107 interrupts = <GIC_PPI 2106 interrupts = <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
2108 }; 2107 };
2109 2108
2110 apcs1_mbox: mailbox@b011000 { 2109 apcs1_mbox: mailbox@b011000 {
2111 compatible = "qcom,ms 2110 compatible = "qcom,msm8939-apcs-kpss-global", "syscon";
2112 reg = <0x0b011000 0x1 2111 reg = <0x0b011000 0x1000>;
2113 clocks = <&a53pll_c1> 2112 clocks = <&a53pll_c1>, <&gcc GPLL0_VOTE>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
2114 clock-names = "pll", 2113 clock-names = "pll", "aux", "ref";
2115 #clock-cells = <0>; 2114 #clock-cells = <0>;
2116 assigned-clocks = <&a 2115 assigned-clocks = <&apcs2>;
2117 assigned-clock-rates 2116 assigned-clock-rates = <297600000>;
2118 #mbox-cells = <1>; 2117 #mbox-cells = <1>;
2119 }; 2118 };
2120 2119
2121 a53pll_c1: clock@b016000 { 2120 a53pll_c1: clock@b016000 {
2122 compatible = "qcom,ms 2121 compatible = "qcom,msm8939-a53pll";
2123 reg = <0x0b016000 0x4 2122 reg = <0x0b016000 0x40>;
2124 #clock-cells = <0>; 2123 #clock-cells = <0>;
2125 }; 2124 };
2126 2125
2127 acc0: clock-controller@b08800 2126 acc0: clock-controller@b088000 {
2128 compatible = "qcom,kp 2127 compatible = "qcom,kpss-acc-v2";
2129 reg = <0x0b088000 0x1 2128 reg = <0x0b088000 0x1000>;
2130 }; 2129 };
2131 2130
2132 saw0: power-manager@b089000 { 2131 saw0: power-manager@b089000 {
2133 compatible = "qcom,ms 2132 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
2134 reg = <0x0b089000 0x1 2133 reg = <0x0b089000 0x1000>;
2135 }; 2134 };
2136 2135
2137 acc1: clock-controller@b09800 2136 acc1: clock-controller@b098000 {
2138 compatible = "qcom,kp 2137 compatible = "qcom,kpss-acc-v2";
2139 reg = <0x0b098000 0x1 2138 reg = <0x0b098000 0x1000>;
2140 }; 2139 };
2141 2140
2142 saw1: power-manager@b099000 { 2141 saw1: power-manager@b099000 {
2143 compatible = "qcom,ms 2142 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
2144 reg = <0x0b099000 0x1 2143 reg = <0x0b099000 0x1000>;
2145 }; 2144 };
2146 2145
2147 acc2: clock-controller@b0a800 2146 acc2: clock-controller@b0a8000 {
2148 compatible = "qcom,kp 2147 compatible = "qcom,kpss-acc-v2";
2149 reg = <0x0b0a8000 0x1 2148 reg = <0x0b0a8000 0x1000>;
2150 }; 2149 };
2151 2150
2152 saw2: power-manager@b0a9000 { 2151 saw2: power-manager@b0a9000 {
2153 compatible = "qcom,ms 2152 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
2154 reg = <0x0b0a9000 0x1 2153 reg = <0x0b0a9000 0x1000>;
2155 }; 2154 };
2156 2155
2157 acc3: clock-controller@b0b800 2156 acc3: clock-controller@b0b8000 {
2158 compatible = "qcom,kp 2157 compatible = "qcom,kpss-acc-v2";
2159 reg = <0x0b0b8000 0x1 2158 reg = <0x0b0b8000 0x1000>;
2160 }; 2159 };
2161 2160
2162 saw3: power-manager@b0b9000 { 2161 saw3: power-manager@b0b9000 {
2163 compatible = "qcom,ms 2162 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
2164 reg = <0x0b0b9000 0x1 2163 reg = <0x0b0b9000 0x1000>;
2165 }; 2164 };
2166 2165
2167 apcs0_mbox: mailbox@b111000 { 2166 apcs0_mbox: mailbox@b111000 {
2168 compatible = "qcom,ms 2167 compatible = "qcom,msm8939-apcs-kpss-global", "syscon";
2169 reg = <0x0b111000 0x1 2168 reg = <0x0b111000 0x1000>;
2170 clocks = <&a53pll_c0> 2169 clocks = <&a53pll_c0>, <&gcc GPLL0_VOTE>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
2171 clock-names = "pll", 2170 clock-names = "pll", "aux", "ref";
2172 #clock-cells = <0>; 2171 #clock-cells = <0>;
2173 #mbox-cells = <1>; 2172 #mbox-cells = <1>;
2174 }; 2173 };
2175 2174
2176 a53pll_c0: clock@b116000 { 2175 a53pll_c0: clock@b116000 {
2177 compatible = "qcom,ms 2176 compatible = "qcom,msm8939-a53pll";
2178 reg = <0x0b116000 0x4 2177 reg = <0x0b116000 0x40>;
2179 #clock-cells = <0>; 2178 #clock-cells = <0>;
2180 }; 2179 };
2181 2180
2182 timer@b120000 { 2181 timer@b120000 {
2183 compatible = "arm,arm 2182 compatible = "arm,armv7-timer-mem";
2184 reg = <0x0b120000 0x1 2183 reg = <0x0b120000 0x1000>;
2185 #address-cells = <1>; 2184 #address-cells = <1>;
2186 #size-cells = <1>; 2185 #size-cells = <1>;
2187 ranges; 2186 ranges;
2188 /* Necessary because 2187 /* Necessary because firmware does not configure this correctly */
2189 clock-frequency = <19 2188 clock-frequency = <19200000>;
2190 2189
2191 frame@b121000 { 2190 frame@b121000 {
2192 reg = <0x0b12 2191 reg = <0x0b121000 0x1000>,
2193 <0x0b12 2192 <0x0b122000 0x1000>;
2194 interrupts = 2193 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
2195 2194 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
2196 frame-number 2195 frame-number = <0>;
2197 }; 2196 };
2198 2197
2199 frame@b123000 { 2198 frame@b123000 {
2200 reg = <0x0b12 2199 reg = <0x0b123000 0x1000>;
2201 interrupts = 2200 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
2202 frame-number 2201 frame-number = <1>;
2203 status = "dis 2202 status = "disabled";
2204 }; 2203 };
2205 2204
2206 frame@b124000 { 2205 frame@b124000 {
2207 reg = <0x0b12 2206 reg = <0x0b124000 0x1000>;
2208 interrupts = 2207 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
2209 frame-number 2208 frame-number = <2>;
2210 status = "dis 2209 status = "disabled";
2211 }; 2210 };
2212 2211
2213 frame@b125000 { 2212 frame@b125000 {
2214 reg = <0x0b12 2213 reg = <0x0b125000 0x1000>;
2215 interrupts = 2214 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
2216 frame-number 2215 frame-number = <3>;
2217 status = "dis 2216 status = "disabled";
2218 }; 2217 };
2219 2218
2220 frame@b126000 { 2219 frame@b126000 {
2221 reg = <0x0b12 2220 reg = <0x0b126000 0x1000>;
2222 interrupts = 2221 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
2223 frame-number 2222 frame-number = <4>;
2224 status = "dis 2223 status = "disabled";
2225 }; 2224 };
2226 2225
2227 frame@b127000 { 2226 frame@b127000 {
2228 reg = <0x0b12 2227 reg = <0x0b127000 0x1000>;
2229 interrupts = 2228 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
2230 frame-number 2229 frame-number = <5>;
2231 status = "dis 2230 status = "disabled";
2232 }; 2231 };
2233 2232
2234 frame@b128000 { 2233 frame@b128000 {
2235 reg = <0x0b12 2234 reg = <0x0b128000 0x1000>;
2236 interrupts = 2235 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
2237 frame-number 2236 frame-number = <6>;
2238 status = "dis 2237 status = "disabled";
2239 }; 2238 };
2240 }; 2239 };
2241 2240
2242 acc4: clock-controller@b18800 2241 acc4: clock-controller@b188000 {
2243 compatible = "qcom,kp 2242 compatible = "qcom,kpss-acc-v2";
2244 reg = <0x0b188000 0x1 2243 reg = <0x0b188000 0x1000>;
2245 }; 2244 };
2246 2245
2247 saw4: power-manager@b189000 { 2246 saw4: power-manager@b189000 {
2248 compatible = "qcom,ms 2247 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
2249 reg = <0x0b189000 0x1 2248 reg = <0x0b189000 0x1000>;
2250 }; 2249 };
2251 2250
2252 acc5: clock-controller@b19800 2251 acc5: clock-controller@b198000 {
2253 compatible = "qcom,kp 2252 compatible = "qcom,kpss-acc-v2";
2254 reg = <0x0b198000 0x1 2253 reg = <0x0b198000 0x1000>;
2255 }; 2254 };
2256 2255
2257 saw5: power-manager@b199000 { 2256 saw5: power-manager@b199000 {
2258 compatible = "qcom,ms 2257 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
2259 reg = <0x0b199000 0x1 2258 reg = <0x0b199000 0x1000>;
2260 }; 2259 };
2261 2260
2262 acc6: clock-controller@b1a800 2261 acc6: clock-controller@b1a8000 {
2263 compatible = "qcom,kp 2262 compatible = "qcom,kpss-acc-v2";
2264 reg = <0x0b1a8000 0x1 2263 reg = <0x0b1a8000 0x1000>;
2265 }; 2264 };
2266 2265
2267 saw6: power-manager@b1a9000 { 2266 saw6: power-manager@b1a9000 {
2268 compatible = "qcom,ms 2267 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
2269 reg = <0x0b1a9000 0x1 2268 reg = <0x0b1a9000 0x1000>;
2270 }; 2269 };
2271 2270
2272 acc7: clock-controller@b1b800 2271 acc7: clock-controller@b1b8000 {
2273 compatible = "qcom,kp 2272 compatible = "qcom,kpss-acc-v2";
2274 reg = <0x0b1b8000 0x1 2273 reg = <0x0b1b8000 0x1000>;
2275 }; 2274 };
2276 2275
2277 saw7: power-manager@b1b9000 { 2276 saw7: power-manager@b1b9000 {
2278 compatible = "qcom,ms 2277 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
2279 reg = <0x0b1b9000 0x1 2278 reg = <0x0b1b9000 0x1000>;
2280 }; 2279 };
2281 2280
2282 a53pll_cci: clock@b1d0000 { 2281 a53pll_cci: clock@b1d0000 {
2283 compatible = "qcom,ms 2282 compatible = "qcom,msm8939-a53pll";
2284 reg = <0x0b1d0000 0x4 2283 reg = <0x0b1d0000 0x40>;
2285 #clock-cells = <0>; 2284 #clock-cells = <0>;
2286 }; 2285 };
2287 2286
2288 apcs2: mailbox@b1d1000 { 2287 apcs2: mailbox@b1d1000 {
2289 compatible = "qcom,ms 2288 compatible = "qcom,msm8939-apcs-kpss-global", "syscon";
2290 reg = <0x0b1d1000 0x1 2289 reg = <0x0b1d1000 0x1000>;
2291 clocks = <&a53pll_cci 2290 clocks = <&a53pll_cci>, <&gcc GPLL0_VOTE>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
2292 clock-names = "pll", 2291 clock-names = "pll", "aux", "ref";
2293 #clock-cells = <0>; 2292 #clock-cells = <0>;
2294 #mbox-cells = <1>; 2293 #mbox-cells = <1>;
2295 }; 2294 };
2296 }; 2295 };
2297 2296
2298 thermal_zones: thermal-zones { 2297 thermal_zones: thermal-zones {
2299 cpu0-thermal { 2298 cpu0-thermal {
2300 polling-delay-passive 2299 polling-delay-passive = <250>;
>> 2300 polling-delay = <1000>;
2301 2301
2302 thermal-sensors = <&t 2302 thermal-sensors = <&tsens 5>;
2303 2303
2304 trips { 2304 trips {
2305 cpu0_alert: t 2305 cpu0_alert: trip0 {
2306 tempe 2306 temperature = <75000>;
2307 hyste 2307 hysteresis = <2000>;
2308 type 2308 type = "passive";
2309 }; 2309 };
2310 2310
2311 cpu0_crit: tr 2311 cpu0_crit: trip1 {
2312 tempe 2312 temperature = <115000>;
2313 hyste 2313 hysteresis = <0>;
2314 type 2314 type = "critical";
2315 }; 2315 };
2316 }; 2316 };
2317 2317
2318 cooling-maps { 2318 cooling-maps {
2319 map0 { 2319 map0 {
2320 trip 2320 trip = <&cpu0_alert>;
2321 cooli 2321 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2322 2322 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2323 2323 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2324 2324 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2325 }; 2325 };
2326 }; 2326 };
2327 }; 2327 };
2328 2328
2329 cpu1-thermal { 2329 cpu1-thermal {
2330 polling-delay-passive 2330 polling-delay-passive = <250>;
>> 2331 polling-delay = <1000>;
2331 2332
2332 thermal-sensors = <&t 2333 thermal-sensors = <&tsens 6>;
2333 2334
2334 trips { 2335 trips {
2335 cpu1_alert: t 2336 cpu1_alert: trip0 {
2336 tempe 2337 temperature = <75000>;
2337 hyste 2338 hysteresis = <2000>;
2338 type 2339 type = "passive";
2339 }; 2340 };
2340 2341
2341 cpu1_crit: tr 2342 cpu1_crit: trip1 {
2342 tempe 2343 temperature = <110000>;
2343 hyste 2344 hysteresis = <2000>;
2344 type 2345 type = "critical";
2345 }; 2346 };
2346 }; 2347 };
2347 2348
2348 cooling-maps { 2349 cooling-maps {
2349 map0 { 2350 map0 {
2350 trip 2351 trip = <&cpu1_alert>;
2351 cooli 2352 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2352 2353 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2353 2354 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2354 2355 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2355 }; 2356 };
2356 }; 2357 };
2357 }; 2358 };
2358 2359
2359 cpu2-thermal { 2360 cpu2-thermal {
2360 polling-delay-passive 2361 polling-delay-passive = <250>;
>> 2362 polling-delay = <1000>;
2361 2363
2362 thermal-sensors = <&t 2364 thermal-sensors = <&tsens 7>;
2363 2365
2364 trips { 2366 trips {
2365 cpu2_alert: t 2367 cpu2_alert: trip0 {
2366 tempe 2368 temperature = <75000>;
2367 hyste 2369 hysteresis = <2000>;
2368 type 2370 type = "passive";
2369 }; 2371 };
2370 2372
2371 cpu2_crit: tr 2373 cpu2_crit: trip1 {
2372 tempe 2374 temperature = <110000>;
2373 hyste 2375 hysteresis = <2000>;
2374 type 2376 type = "critical";
2375 }; 2377 };
2376 }; 2378 };
2377 2379
2378 cooling-maps { 2380 cooling-maps {
2379 map0 { 2381 map0 {
2380 trip 2382 trip = <&cpu2_alert>;
2381 cooli 2383 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2382 2384 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2383 2385 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2384 2386 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2385 }; 2387 };
2386 }; 2388 };
2387 }; 2389 };
2388 2390
2389 cpu3-thermal { 2391 cpu3-thermal {
2390 polling-delay-passive 2392 polling-delay-passive = <250>;
>> 2393 polling-delay = <1000>;
2391 2394
2392 thermal-sensors = <&t 2395 thermal-sensors = <&tsens 8>;
2393 2396
2394 trips { 2397 trips {
2395 cpu3_alert: t 2398 cpu3_alert: trip0 {
2396 tempe 2399 temperature = <75000>;
2397 hyste 2400 hysteresis = <2000>;
2398 type 2401 type = "passive";
2399 }; 2402 };
2400 2403
2401 cpu3_crit: tr 2404 cpu3_crit: trip1 {
2402 tempe 2405 temperature = <110000>;
2403 hyste 2406 hysteresis = <2000>;
2404 type 2407 type = "critical";
2405 }; 2408 };
2406 }; 2409 };
2407 2410
2408 cooling-maps { 2411 cooling-maps {
2409 map0 { 2412 map0 {
2410 trip 2413 trip = <&cpu3_alert>;
2411 cooli 2414 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2412 2415 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2413 2416 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2414 2417 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2415 }; 2418 };
2416 }; 2419 };
2417 }; 2420 };
2418 2421
2419 cpu4567-thermal { 2422 cpu4567-thermal {
2420 polling-delay-passive 2423 polling-delay-passive = <250>;
>> 2424 polling-delay = <1000>;
2421 2425
2422 thermal-sensors = <&t 2426 thermal-sensors = <&tsens 9>;
2423 2427
2424 trips { 2428 trips {
2425 cpu4567_alert 2429 cpu4567_alert: trip0 {
2426 tempe 2430 temperature = <75000>;
2427 hyste 2431 hysteresis = <2000>;
2428 type 2432 type = "passive";
2429 }; 2433 };
2430 2434
2431 cpu4567_crit: 2435 cpu4567_crit: trip1 {
2432 tempe 2436 temperature = <110000>;
2433 hyste 2437 hysteresis = <2000>;
2434 type 2438 type = "critical";
2435 }; 2439 };
2436 }; 2440 };
2437 2441
2438 cooling-maps { 2442 cooling-maps {
2439 map0 { 2443 map0 {
2440 trip 2444 trip = <&cpu4567_alert>;
2441 cooli 2445 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2442 2446 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2443 2447 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2444 2448 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2445 }; 2449 };
2446 }; 2450 };
2447 }; 2451 };
2448 2452
2449 gpu-thermal { 2453 gpu-thermal {
2450 polling-delay-passive 2454 polling-delay-passive = <250>;
>> 2455 polling-delay = <1000>;
2451 2456
2452 thermal-sensors = <&t 2457 thermal-sensors = <&tsens 3>;
2453 2458
2454 cooling-maps { <<
2455 map0 { <<
2456 trip <<
2457 cooli <<
2458 }; <<
2459 }; <<
2460 <<
2461 trips { 2459 trips {
2462 gpu_alert0: t 2460 gpu_alert0: trip-point0 {
2463 tempe 2461 temperature = <75000>;
2464 hyste 2462 hysteresis = <2000>;
2465 type 2463 type = "passive";
2466 }; 2464 };
2467 2465
2468 gpu_crit: gpu !! 2466 gpu_crit: gpu_crit {
2469 tempe 2467 temperature = <95000>;
2470 hyste 2468 hysteresis = <2000>;
2471 type 2469 type = "critical";
2472 }; 2470 };
2473 }; 2471 };
2474 }; 2472 };
2475 2473
2476 modem1-thermal { 2474 modem1-thermal {
2477 polling-delay-passive 2475 polling-delay-passive = <250>;
>> 2476 polling-delay = <1000>;
2478 2477
2479 thermal-sensors = <&t 2478 thermal-sensors = <&tsens 0>;
2480 2479
2481 trips { 2480 trips {
2482 modem1_alert0 2481 modem1_alert0: trip-point0 {
2483 tempe 2482 temperature = <85000>;
2484 hyste 2483 hysteresis = <2000>;
2485 type 2484 type = "hot";
2486 }; 2485 };
2487 }; 2486 };
2488 }; 2487 };
2489 2488
2490 modem2-thermal { 2489 modem2-thermal {
2491 polling-delay-passive 2490 polling-delay-passive = <250>;
>> 2491 polling-delay = <1000>;
2492 2492
2493 thermal-sensors = <&t 2493 thermal-sensors = <&tsens 2>;
2494 2494
2495 trips { 2495 trips {
2496 modem2_alert0 2496 modem2_alert0: trip-point0 {
2497 tempe 2497 temperature = <85000>;
2498 hyste 2498 hysteresis = <2000>;
2499 type 2499 type = "hot";
2500 }; 2500 };
2501 }; 2501 };
2502 }; 2502 };
2503 2503
2504 camera-thermal { 2504 camera-thermal {
2505 polling-delay-passive 2505 polling-delay-passive = <250>;
>> 2506 polling-delay = <1000>;
2506 2507
2507 thermal-sensors = <&t 2508 thermal-sensors = <&tsens 1>;
2508 2509
2509 trips { 2510 trips {
2510 cam_alert0: t 2511 cam_alert0: trip-point0 {
2511 tempe 2512 temperature = <75000>;
2512 hyste 2513 hysteresis = <2000>;
2513 type 2514 type = "hot";
2514 }; 2515 };
2515 }; 2516 };
2516 }; 2517 };
2517 }; 2518 };
2518 2519
2519 timer { 2520 timer {
2520 compatible = "arm,armv8-timer 2521 compatible = "arm,armv8-timer";
2521 interrupts = <GIC_PPI 2 (GIC_ 2522 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
2522 <GIC_PPI 3 (GIC_ 2523 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
2523 <GIC_PPI 4 (GIC_ 2524 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
2524 <GIC_PPI 1 (GIC_ 2525 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
2525 }; 2526 };
2526 }; 2527 };
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