1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2013-2016, The Linux Foundati
4 */
5
6 #include <dt-bindings/interrupt-controller/arm
7 #include <dt-bindings/clock/qcom,gcc-msm8994.h
8 #include <dt-bindings/clock/qcom,mmcc-msm8994.
9 #include <dt-bindings/clock/qcom,rpmcc.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/power/qcom-rpmpd.h>
12
13 / {
14 interrupt-parent = <&intc>;
15
16 #address-cells = <2>;
17 #size-cells = <2>;
18
19 aliases {
20 mmc1 = &sdhc1;
21 mmc2 = &sdhc2;
22 };
23
24 chosen { };
25
26 clocks {
27 xo_board: xo-board {
28 compatible = "fixed-cl
29 #clock-cells = <0>;
30 clock-frequency = <192
31 clock-output-names = "
32 };
33
34 sleep_clk: sleep-clk {
35 compatible = "fixed-cl
36 #clock-cells = <0>;
37 clock-frequency = <327
38 clock-output-names = "
39 };
40 };
41
42 cpus {
43 #address-cells = <2>;
44 #size-cells = <0>;
45
46 CPU0: cpu@0 {
47 device_type = "cpu";
48 compatible = "arm,cort
49 reg = <0x0 0x0>;
50 enable-method = "psci"
51 next-level-cache = <&L
52 L2_0: l2-cache {
53 compatible = "
54 cache-level =
55 cache-unified;
56 };
57 };
58
59 CPU1: cpu@1 {
60 device_type = "cpu";
61 compatible = "arm,cort
62 reg = <0x0 0x1>;
63 enable-method = "psci"
64 next-level-cache = <&L
65 };
66
67 CPU2: cpu@2 {
68 device_type = "cpu";
69 compatible = "arm,cort
70 reg = <0x0 0x2>;
71 enable-method = "psci"
72 next-level-cache = <&L
73 };
74
75 CPU3: cpu@3 {
76 device_type = "cpu";
77 compatible = "arm,cort
78 reg = <0x0 0x3>;
79 enable-method = "psci"
80 next-level-cache = <&L
81 };
82
83 CPU4: cpu@100 {
84 device_type = "cpu";
85 compatible = "arm,cort
86 reg = <0x0 0x100>;
87 enable-method = "psci"
88 next-level-cache = <&L
89 L2_1: l2-cache {
90 compatible = "
91 cache-level =
92 cache-unified;
93 };
94 };
95
96 CPU5: cpu@101 {
97 device_type = "cpu";
98 compatible = "arm,cort
99 reg = <0x0 0x101>;
100 enable-method = "psci"
101 next-level-cache = <&L
102 };
103
104 CPU6: cpu@102 {
105 device_type = "cpu";
106 compatible = "arm,cort
107 reg = <0x0 0x102>;
108 enable-method = "psci"
109 next-level-cache = <&L
110 };
111
112 CPU7: cpu@103 {
113 device_type = "cpu";
114 compatible = "arm,cort
115 reg = <0x0 0x103>;
116 enable-method = "psci"
117 next-level-cache = <&L
118 };
119
120 cpu-map {
121 cluster0 {
122 core0 {
123 cpu =
124 };
125
126 core1 {
127 cpu =
128 };
129
130 core2 {
131 cpu =
132 };
133
134 core3 {
135 cpu =
136 };
137 };
138
139 cluster1 {
140 core0 {
141 cpu =
142 };
143
144 core1 {
145 cpu =
146 };
147
148 cpu6_map: core
149 cpu =
150 };
151
152 cpu7_map: core
153 cpu =
154 };
155 };
156 };
157 };
158
159 firmware {
160 scm {
161 compatible = "qcom,scm
162 };
163 };
164
165 memory@80000000 {
166 device_type = "memory";
167 /* We expect the bootloader to
168 reg = <0 0x80000000 0 0>;
169 };
170
171 pmu {
172 compatible = "arm,cortex-a53-p
173 interrupts = <GIC_PPI 7 (GIC_C
174 };
175
176 psci {
177 compatible = "arm,psci-0.2";
178 method = "hvc";
179 };
180
181 rpm: remoteproc {
182 compatible = "qcom,msm8994-rpm
183
184 smd-edge {
185 interrupts = <GIC_SPI
186 mboxes = <&apcs 0>;
187 qcom,smd-edge = <15>;
188 qcom,remote-pid = <6>;
189
190 rpm_requests: rpm-requ
191 compatible = "
192 qcom,smd-chann
193
194 rpmcc: clock-c
195 compat
196 #clock
197 };
198
199 rpmpd: power-c
200 compat
201 #power
202 operat
203
204 rpmpd_
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225 };
226 };
227 };
228 };
229 };
230
231 reserved-memory {
232 #address-cells = <2>;
233 #size-cells = <2>;
234 ranges;
235
236 dfps_data_mem: dfps-data@34000
237 reg = <0 0x03400000 0
238 no-map;
239 };
240
241 cont_splash_mem: memory@340100
242 reg = <0 0x03401000 0
243 no-map;
244 };
245
246 smem_mem: smem@6a00000 {
247 reg = <0 0x06a00000 0
248 no-map;
249 };
250
251 mpss_mem: memory@7000000 {
252 reg = <0 0x07000000 0
253 no-map;
254 };
255
256 peripheral_region: memory@ca00
257 reg = <0 0x0ca00000 0
258 no-map;
259 };
260
261 rmtfs_mem: memory@c6400000 {
262 compatible = "qcom,rmt
263 reg = <0 0xc6400000 0
264 no-map;
265
266 qcom,client-id = <1>;
267 };
268
269 mba_mem: memory@c6700000 {
270 reg = <0 0xc6700000 0
271 no-map;
272 };
273
274 audio_mem: memory@c7000000 {
275 reg = <0 0xc7000000 0
276 no-map;
277 };
278
279 adsp_mem: memory@c9400000 {
280 reg = <0 0xc9400000 0
281 no-map;
282 };
283
284 res_hyp_mem: reserved@6c00000
285 reg = <0 0x06c00000 0
286 no-map;
287 };
288 };
289
290 smem {
291 compatible = "qcom,smem";
292 memory-region = <&smem_mem>;
293 qcom,rpm-msg-ram = <&rpm_msg_r
294 hwlocks = <&tcsr_mutex 3>;
295 };
296
297 smp2p-lpass {
298 compatible = "qcom,smp2p";
299 qcom,smem = <443>, <429>;
300
301 interrupts = <GIC_SPI 158 IRQ_
302
303 mboxes = <&apcs 10>;
304
305 qcom,local-pid = <0>;
306 qcom,remote-pid = <2>;
307
308 adsp_smp2p_out: master-kernel
309 qcom,entry-name = "mas
310 #qcom,smem-state-cells
311 };
312
313 adsp_smp2p_in: slave-kernel {
314 qcom,entry-name = "sla
315
316 interrupt-controller;
317 #interrupt-cells = <2>
318 };
319 };
320
321 smp2p-modem {
322 compatible = "qcom,smp2p";
323 qcom,smem = <435>, <428>;
324
325 interrupt-parent = <&intc>;
326 interrupts = <GIC_SPI 27 IRQ_T
327
328 mboxes = <&apcs 14>;
329
330 qcom,local-pid = <0>;
331 qcom,remote-pid = <1>;
332
333 modem_smp2p_out: master-kernel
334 qcom,entry-name = "mas
335 #qcom,smem-state-cells
336 };
337
338 modem_smp2p_in: slave-kernel {
339 qcom,entry-name = "sla
340
341 interrupt-controller;
342 #interrupt-cells = <2>
343 };
344 };
345
346 soc: soc@0 {
347 #address-cells = <1>;
348 #size-cells = <1>;
349 ranges = <0 0 0 0xffffffff>;
350 compatible = "simple-bus";
351
352 intc: interrupt-controller@f90
353 compatible = "qcom,msm
354 interrupt-controller;
355 #interrupt-cells = <3>
356 reg = <0xf9000000 0x10
357 <0xf9002000 0x10
358 };
359
360 apcs: mailbox@f900d000 {
361 compatible = "qcom,msm
362 reg = <0xf900d000 0x20
363 #mbox-cells = <1>;
364 };
365
366 watchdog@f9017000 {
367 compatible = "qcom,aps
368 reg = <0xf9017000 0x10
369 interrupts = <GIC_SPI
370 <GIC_SPI
371 clocks = <&sleep_clk>;
372 timeout-sec = <10>;
373 };
374
375 timer@f9020000 {
376 #address-cells = <1>;
377 #size-cells = <1>;
378 ranges;
379 compatible = "arm,armv
380 reg = <0xf9020000 0x10
381
382 frame@f9021000 {
383 frame-number =
384 interrupts = <
385 <
386 reg = <0xf9021
387 <0xf9022
388 };
389
390 frame@f9023000 {
391 frame-number =
392 interrupts = <
393 reg = <0xf9023
394 status = "disa
395 };
396
397 frame@f9024000 {
398 frame-number =
399 interrupts = <
400 reg = <0xf9024
401 status = "disa
402 };
403
404 frame@f9025000 {
405 frame-number =
406 interrupts = <
407 reg = <0xf9025
408 status = "disa
409 };
410
411 frame@f9026000 {
412 frame-number =
413 interrupts = <
414 reg = <0xf9026
415 status = "disa
416 };
417
418 frame@f9027000 {
419 frame-number =
420 interrupts = <
421 reg = <0xf9027
422 status = "disa
423 };
424
425 frame@f9028000 {
426 frame-number =
427 interrupts = <
428 reg = <0xf9028
429 status = "disa
430 };
431 };
432
433 usb3: usb@f92f8800 {
434 compatible = "qcom,msm
435 reg = <0xf92f8800 0x40
436 #address-cells = <1>;
437 #size-cells = <1>;
438 ranges;
439
440 clocks = <&gcc GCC_USB
441 <&gcc GCC_SYS
442 <&gcc GCC_USB
443 <&gcc GCC_USB
444 clock-names = "core",
445 "iface",
446 "sleep",
447 "mock_ut
448
449 assigned-clocks = <&gc
450 <&gc
451 assigned-clock-rates =
452
453 power-domains = <&gcc
454 qcom,select-utmi-as-pi
455
456 usb@f9200000 {
457 compatible = "
458 reg = <0xf9200
459 interrupts = <
460 snps,dis_u2_su
461 snps,dis_enbls
462 maximum-speed
463 dr_mode = "per
464 };
465 };
466
467 sdhc1: mmc@f9824900 {
468 compatible = "qcom,msm
469 reg = <0xf9824900 0x1a
470 reg-names = "hc", "cor
471
472 interrupts = <GIC_SPI
473 <GIC_SPI
474 interrupt-names = "hc_
475
476 clocks = <&gcc GCC_SDC
477 <&gcc GCC_SDC
478 <&xo_board>;
479 clock-names = "iface",
480
481 pinctrl-names = "defau
482 pinctrl-0 = <&sdc1_clk
483 pinctrl-1 = <&sdc1_clk
484
485 bus-width = <8>;
486 non-removable;
487 status = "disabled";
488 };
489
490 sdhc2: mmc@f98a4900 {
491 compatible = "qcom,msm
492 reg = <0xf98a4900 0x11
493 reg-names = "hc", "cor
494
495 interrupts = <GIC_SPI
496 <GIC_SPI 221 I
497 interrupt-names = "hc_
498
499 clocks = <&gcc GCC_SDC
500 <&gcc GCC_SDC
501 <&xo_board>;
502 clock-names = "iface",
503
504 pinctrl-names = "defau
505 pinctrl-0 = <&sdc2_clk
506 pinctrl-1 = <&sdc2_clk
507
508 cd-gpios = <&tlmm 100
509 bus-width = <4>;
510 status = "disabled";
511 };
512
513 blsp1_dma: dma-controller@f990
514 compatible = "qcom,bam
515 reg = <0xf9904000 0x19
516 interrupts = <GIC_SPI
517 clocks = <&gcc GCC_BLS
518 clock-names = "bam_clk
519 #dma-cells = <1>;
520 qcom,ee = <0>;
521 qcom,controlled-remote
522 num-channels = <24>;
523 qcom,num-ees = <4>;
524 };
525
526 blsp1_uart2: serial@f991e000 {
527 compatible = "qcom,msm
528 reg = <0xf991e000 0x10
529 interrupts = <GIC_SPI
530 clock-names = "core",
531 clocks = <&gcc GCC_BLS
532 <&gcc GCC_BLS
533 pinctrl-names = "defau
534 pinctrl-0 = <&blsp1_ua
535 pinctrl-1 = <&blsp1_ua
536 status = "disabled";
537 };
538
539 blsp1_i2c1: i2c@f9923000 {
540 compatible = "qcom,i2c
541 reg = <0xf9923000 0x50
542 interrupts = <GIC_SPI
543 clocks = <&gcc GCC_BLS
544 <&gcc GCC_BLS
545 clock-names = "core",
546 clock-frequency = <400
547 dmas = <&blsp1_dma 12>
548 dma-names = "tx", "rx"
549 pinctrl-names = "defau
550 pinctrl-0 = <&i2c1_def
551 pinctrl-1 = <&i2c1_sle
552 #address-cells = <1>;
553 #size-cells = <0>;
554 status = "disabled";
555 };
556
557 blsp1_spi1: spi@f9923000 {
558 compatible = "qcom,spi
559 reg = <0xf9923000 0x50
560 interrupts = <GIC_SPI
561 clocks = <&gcc GCC_BLS
562 <&gcc GCC_BLS
563 clock-names = "core",
564 dmas = <&blsp1_dma 12>
565 dma-names = "tx", "rx"
566 pinctrl-names = "defau
567 pinctrl-0 = <&blsp1_sp
568 pinctrl-1 = <&blsp1_sp
569 #address-cells = <1>;
570 #size-cells = <0>;
571 status = "disabled";
572 };
573
574 blsp1_i2c2: i2c@f9924000 {
575 compatible = "qcom,i2c
576 reg = <0xf9924000 0x50
577 interrupts = <GIC_SPI
578 clocks = <&gcc GCC_BLS
579 <&gcc GCC_BLS
580 clock-names = "core",
581 clock-frequency = <400
582 dmas = <&blsp1_dma 14>
583 dma-names = "tx", "rx"
584 pinctrl-names = "defau
585 pinctrl-0 = <&i2c2_def
586 pinctrl-1 = <&i2c2_sle
587 #address-cells = <1>;
588 #size-cells = <0>;
589 status = "disabled";
590 };
591
592 /* I2C3 doesn't exist */
593
594 blsp1_i2c4: i2c@f9926000 {
595 compatible = "qcom,i2c
596 reg = <0xf9926000 0x50
597 interrupts = <GIC_SPI
598 clocks = <&gcc GCC_BLS
599 <&gcc GCC_BLS
600 clock-names = "core",
601 clock-frequency = <400
602 dmas = <&blsp1_dma 18>
603 dma-names = "tx", "rx"
604 pinctrl-names = "defau
605 pinctrl-0 = <&i2c4_def
606 pinctrl-1 = <&i2c4_sle
607 #address-cells = <1>;
608 #size-cells = <0>;
609 status = "disabled";
610 };
611
612 blsp1_i2c5: i2c@f9927000 {
613 compatible = "qcom,i2c
614 reg = <0xf9927000 0x50
615 interrupts = <GIC_SPI
616 clocks = <&gcc GCC_BLS
617 <&gcc GCC_BLS
618 clock-names = "core",
619 clock-frequency = <400
620 dmas = <&blsp2_dma 20>
621 dma-names = "tx", "rx"
622 pinctrl-names = "defau
623 pinctrl-0 = <&i2c5_def
624 pinctrl-1 = <&i2c5_sle
625 #address-cells = <1>;
626 #size-cells = <0>;
627 status = "disabled";
628 };
629
630 blsp1_i2c6: i2c@f9928000 {
631 compatible = "qcom,i2c
632 reg = <0xf9928000 0x50
633 interrupts = <GIC_SPI
634 clocks = <&gcc GCC_BLS
635 <&gcc GCC_BLS
636 clock-names = "core",
637 clock-frequency = <400
638 dmas = <&blsp1_dma 22>
639 dma-names = "tx", "rx"
640 pinctrl-names = "defau
641 pinctrl-0 = <&i2c6_def
642 pinctrl-1 = <&i2c6_sle
643 #address-cells = <1>;
644 #size-cells = <0>;
645 status = "disabled";
646 };
647
648 blsp2_dma: dma-controller@f994
649 compatible = "qcom,bam
650 reg = <0xf9944000 0x19
651 interrupts = <GIC_SPI
652 clocks = <&gcc GCC_BLS
653 clock-names = "bam_clk
654 #dma-cells = <1>;
655 qcom,ee = <0>;
656 qcom,controlled-remote
657 num-channels = <24>;
658 qcom,num-ees = <4>;
659 };
660
661 blsp2_uart2: serial@f995e000 {
662 compatible = "qcom,msm
663 reg = <0xf995e000 0x10
664 interrupts = <GIC_SPI
665 clock-names = "core",
666 clocks = <&gcc GCC_BLS
667 <&gcc
668 dmas = <&blsp2_dma 2>,
669 dma-names = "tx", "rx"
670 pinctrl-names = "defau
671 pinctrl-0 = <&blsp2_ua
672 pinctrl-1 = <&blsp2_ua
673 status = "disabled";
674 };
675
676 blsp2_i2c1: i2c@f9963000 {
677 compatible = "qcom,i2c
678 reg = <0xf9963000 0x50
679 interrupts = <GIC_SPI
680 clocks = <&gcc GCC_BLS
681 <&gcc GCC_BLS
682 clock-names = "core",
683 clock-frequency = <400
684 dmas = <&blsp2_dma 12>
685 dma-names = "tx", "rx"
686 pinctrl-names = "defau
687 pinctrl-0 = <&i2c7_def
688 pinctrl-1 = <&i2c7_sle
689 #address-cells = <1>;
690 #size-cells = <0>;
691 status = "disabled";
692 };
693
694 blsp2_spi4: spi@f9966000 {
695 compatible = "qcom,spi
696 reg = <0xf9966000 0x50
697 interrupts = <GIC_SPI
698 clocks = <&gcc GCC_BLS
699 <&gcc GCC_BLS
700 clock-names = "core",
701 dmas = <&blsp2_dma 18>
702 dma-names = "tx", "rx"
703 pinctrl-names = "defau
704 pinctrl-0 = <&blsp2_sp
705 pinctrl-1 = <&blsp2_sp
706 #address-cells = <1>;
707 #size-cells = <0>;
708 status = "disabled";
709 };
710
711 blsp2_i2c5: i2c@f9967000 {
712 compatible = "qcom,i2c
713 reg = <0xf9967000 0x50
714 interrupts = <GIC_SPI
715 clocks = <&gcc GCC_BLS
716 <&gcc GCC_BLS
717 clock-names = "core",
718 clock-frequency = <355
719 dmas = <&blsp2_dma 20>
720 dma-names = "tx", "rx"
721 pinctrl-names = "defau
722 pinctrl-0 = <&i2c11_de
723 pinctrl-1 = <&i2c11_sl
724 #address-cells = <1>;
725 #size-cells = <0>;
726 status = "disabled";
727 };
728
729 gcc: clock-controller@fc400000
730 compatible = "qcom,gcc
731 #clock-cells = <1>;
732 #reset-cells = <1>;
733 #power-domain-cells =
734 reg = <0xfc400000 0x20
735
736 clock-names = "xo", "s
737 clocks = <&xo_board>,
738 };
739
740 rpm_msg_ram: sram@fc428000 {
741 compatible = "qcom,rpm
742 reg = <0xfc428000 0x40
743 };
744
745 restart@fc4ab000 {
746 compatible = "qcom,psh
747 reg = <0xfc4ab000 0x4>
748 };
749
750 spmi_bus: spmi@fc4cf000 {
751 compatible = "qcom,spm
752 reg = <0xfc4cf000 0x10
753 <0xfc4cb000 0x10
754 <0xfc4ca000 0x10
755 reg-names = "core", "i
756 interrupt-names = "per
757 interrupts = <GIC_SPI
758 qcom,ee = <0>;
759 qcom,channel = <0>;
760 #address-cells = <2>;
761 #size-cells = <0>;
762 interrupt-controller;
763 #interrupt-cells = <4>
764 };
765
766 tcsr_mutex: hwlock@fd484000 {
767 compatible = "qcom,msm
768 reg = <0xfd484000 0x10
769 #hwlock-cells = <1>;
770 };
771
772 tlmm: pinctrl@fd510000 {
773 compatible = "qcom,msm
774 reg = <0xfd510000 0x40
775 interrupts = <GIC_SPI
776 gpio-controller;
777 gpio-ranges = <&tlmm 0
778 #gpio-cells = <2>;
779 interrupt-controller;
780 #interrupt-cells = <2>
781
782 blsp1_uart2_default: b
783 pins = "gpio4"
784 function = "bl
785 drive-strength
786 bias-disable;
787 };
788
789 blsp1_uart2_sleep: bls
790 pins = "gpio4"
791 function = "gp
792 drive-strength
793 bias-pull-down
794 };
795
796 blsp2_uart2_default: b
797 pins = "gpio45
798 function = "bl
799 drive-strength
800 bias-disable;
801 };
802
803 blsp2_uart2_sleep: bls
804 pins = "gpio45
805 function = "gp
806 drive-strength
807 bias-disable;
808 };
809
810 i2c1_default: i2c1-def
811 pins = "gpio2"
812 function = "bl
813 drive-strength
814 bias-disable;
815 };
816
817 i2c1_sleep: i2c1-sleep
818 pins = "gpio2"
819 function = "gp
820 drive-strength
821 bias-disable;
822 };
823
824 i2c2_default: i2c2-def
825 pins = "gpio6"
826 function = "bl
827 drive-strength
828 bias-disable;
829 };
830
831 i2c2_sleep: i2c2-sleep
832 pins = "gpio6"
833 function = "gp
834 drive-strength
835 bias-disable;
836 };
837
838 i2c4_default: i2c4-def
839 pins = "gpio19
840 function = "bl
841 drive-strength
842 bias-disable;
843 };
844
845 i2c4_sleep: i2c4-sleep
846 pins = "gpio19
847 function = "gp
848 drive-strength
849 bias-pull-down
850 };
851
852 i2c5_default: i2c5-def
853 pins = "gpio23
854 function = "bl
855 drive-strength
856 bias-disable;
857 };
858
859 i2c5_sleep: i2c5-sleep
860 pins = "gpio23
861 function = "gp
862 drive-strength
863 bias-disable;
864 };
865
866 i2c6_default: i2c6-def
867 pins = "gpio28
868 function = "bl
869 drive-strength
870 bias-disable;
871 };
872
873 i2c6_sleep: i2c6-sleep
874 pins = "gpio28
875 function = "gp
876 drive-strength
877 bias-disable;
878 };
879
880 i2c7_default: i2c7-def
881 pins = "gpio44
882 function = "bl
883 drive-strength
884 bias-disable;
885 };
886
887 i2c7_sleep: i2c7-sleep
888 pins = "gpio44
889 function = "gp
890 drive-strength
891 bias-disable;
892 };
893
894 blsp2_spi10_default: b
895 default-pins {
896 pins =
897 functi
898 drive-
899 bias-p
900 };
901
902 cs-pins {
903 pins =
904 functi
905 drive-
906 bias-d
907 };
908 };
909
910 blsp2_spi10_sleep: bls
911 pins = "gpio53
912 function = "gp
913 drive-strength
914 bias-disable;
915 };
916
917 i2c11_default: i2c11-d
918 pins = "gpio83
919 function = "bl
920 drive-strength
921 bias-disable;
922 };
923
924 i2c11_sleep: i2c11-sle
925 pins = "gpio83
926 function = "gp
927 drive-strength
928 bias-disable;
929 };
930
931 blsp1_spi1_default: bl
932 default-pins {
933 pins =
934 functi
935 drive-
936 bias-p
937 };
938
939 cs-pins {
940 pins =
941 functi
942 drive-
943 bias-d
944 };
945 };
946
947 blsp1_spi1_sleep: blsp
948 pins = "gpio0"
949 function = "gp
950 drive-strength
951 bias-disable;
952 };
953
954 sdc1_clk_on: clk-on-st
955 pins = "sdc1_c
956 bias-disable;
957 drive-strength
958 };
959
960 sdc1_clk_off: clk-off-
961 pins = "sdc1_c
962 bias-disable;
963 drive-strength
964 };
965
966 sdc1_cmd_on: cmd-on-st
967 pins = "sdc1_c
968 bias-pull-up;
969 drive-strength
970 };
971
972 sdc1_cmd_off: cmd-off-
973 pins = "sdc1_c
974 bias-pull-up;
975 drive-strength
976 };
977
978 sdc1_data_on: data-on-
979 pins = "sdc1_d
980 bias-pull-up;
981 drive-strength
982 };
983
984 sdc1_data_off: data-of
985 pins = "sdc1_d
986 bias-pull-up;
987 drive-strength
988 };
989
990 sdc1_rclk_on: rclk-on-
991 pins = "sdc1_r
992 bias-pull-down
993 };
994
995 sdc1_rclk_off: rclk-of
996 pins = "sdc1_r
997 bias-pull-down
998 };
999
1000 sdc2_clk_on: sdc2-clk
1001 pins = "sdc2_
1002 bias-disable;
1003 drive-strengt
1004 };
1005
1006 sdc2_clk_off: sdc2-cl
1007 pins = "sdc2_
1008 bias-disable;
1009 drive-strengt
1010 };
1011
1012 sdc2_cmd_on: sdc2-cmd
1013 pins = "sdc2_
1014 bias-pull-up;
1015 drive-strengt
1016 };
1017
1018 sdc2_cmd_off: sdc2-cm
1019 pins = "sdc2_
1020 bias-pull-up;
1021 drive-strengt
1022 };
1023
1024 sdc2_data_on: sdc2-da
1025 pins = "sdc2_
1026 bias-pull-up;
1027 drive-strengt
1028 };
1029
1030 sdc2_data_off: sdc2-d
1031 pins = "sdc2_
1032 bias-pull-up;
1033 drive-strengt
1034 };
1035 };
1036
1037 mmcc: clock-controller@fd8c00
1038 compatible = "qcom,mm
1039 reg = <0xfd8c0000 0x5
1040 #clock-cells = <1>;
1041 #reset-cells = <1>;
1042 #power-domain-cells =
1043
1044 clock-names = "xo",
1045 "gpll0"
1046 "mmssno
1047 "oxili_
1048 "dsi0pl
1049 "dsi0pl
1050 "dsi1pl
1051 "dsi1pl
1052 "hdmipl
1053 clocks = <&xo_board>,
1054 <&gcc GPLL0_
1055 <&rpmcc RPM_
1056 <&rpmcc RPM_
1057 <0>,
1058 <0>,
1059 <0>,
1060 <0>,
1061 <0>;
1062
1063 assigned-clocks = <&m
1064 <&m
1065 <&m
1066 <&m
1067 <&m
1068 assigned-clock-rates
1069
1070
1071
1072
1073 };
1074
1075 ocmem: sram@fdd00000 {
1076 compatible = "qcom,ms
1077 reg = <0xfdd00000 0x2
1078 <0xfec00000 0x2
1079 reg-names = "ctrl", "
1080 ranges = <0 0xfec0000
1081 clocks = <&rpmcc RPM_
1082 <&mmcc OCMEM
1083 clock-names = "core",
1084
1085 #address-cells = <1>;
1086 #size-cells = <1>;
1087
1088 gmu_sram: gmu-sram@0
1089 reg = <0x0 0x
1090 };
1091 };
1092 };
1093
1094 timer: timer {
1095 compatible = "arm,armv8-timer
1096 interrupts = <GIC_PPI 2 (GIC_
1097 <GIC_PPI 3 (GIC_
1098 <GIC_PPI 4 (GIC_
1099 <GIC_PPI 1 (GIC_
1100 };
1101
1102 vph_pwr: vph-pwr-regulator {
1103 compatible = "regulator-fixed
1104 regulator-name = "vph_pwr";
1105
1106 regulator-min-microvolt = <36
1107 regulator-max-microvolt = <36
1108
1109 regulator-always-on;
1110 };
1111 };
1112
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