1 // SPDX-License-Identifier: GPL-2.0-only 1 // SPDX-License-Identifier: GPL-2.0-only
2 /* !! 2 /* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
3 * Copyright (c) 2013-2016, The Linux Foundati <<
4 */ 3 */
5 4
6 #include <dt-bindings/interrupt-controller/arm 5 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,gcc-msm8994.h 6 #include <dt-bindings/clock/qcom,gcc-msm8994.h>
8 #include <dt-bindings/clock/qcom,mmcc-msm8994. <<
9 #include <dt-bindings/clock/qcom,rpmcc.h> <<
10 #include <dt-bindings/gpio/gpio.h> <<
11 #include <dt-bindings/power/qcom-rpmpd.h> <<
12 7
13 / { 8 / {
14 interrupt-parent = <&intc>; 9 interrupt-parent = <&intc>;
15 10
16 #address-cells = <2>; 11 #address-cells = <2>;
17 #size-cells = <2>; 12 #size-cells = <2>;
18 13
19 aliases { <<
20 mmc1 = &sdhc1; <<
21 mmc2 = &sdhc2; <<
22 }; <<
23 <<
24 chosen { }; 14 chosen { };
25 15
26 clocks { 16 clocks {
27 xo_board: xo-board { !! 17 xo_board: xo_board {
28 compatible = "fixed-cl 18 compatible = "fixed-clock";
29 #clock-cells = <0>; 19 #clock-cells = <0>;
30 clock-frequency = <192 20 clock-frequency = <19200000>;
31 clock-output-names = " <<
32 }; 21 };
33 22
34 sleep_clk: sleep-clk { !! 23 sleep_clk: sleep_clk {
35 compatible = "fixed-cl 24 compatible = "fixed-clock";
36 #clock-cells = <0>; 25 #clock-cells = <0>;
37 clock-frequency = <327 26 clock-frequency = <32768>;
38 clock-output-names = " <<
39 }; 27 };
40 }; 28 };
41 29
42 cpus { 30 cpus {
43 #address-cells = <2>; 31 #address-cells = <2>;
44 #size-cells = <0>; 32 #size-cells = <0>;
45 33
46 CPU0: cpu@0 { 34 CPU0: cpu@0 {
47 device_type = "cpu"; 35 device_type = "cpu";
48 compatible = "arm,cort 36 compatible = "arm,cortex-a53";
49 reg = <0x0 0x0>; 37 reg = <0x0 0x0>;
50 enable-method = "psci" 38 enable-method = "psci";
51 next-level-cache = <&L 39 next-level-cache = <&L2_0>;
52 L2_0: l2-cache { 40 L2_0: l2-cache {
53 compatible = " 41 compatible = "cache";
54 cache-level = 42 cache-level = <2>;
55 cache-unified; <<
56 }; 43 };
57 }; 44 };
58 45
59 CPU1: cpu@1 { 46 CPU1: cpu@1 {
60 device_type = "cpu"; 47 device_type = "cpu";
61 compatible = "arm,cort 48 compatible = "arm,cortex-a53";
62 reg = <0x0 0x1>; 49 reg = <0x0 0x1>;
63 enable-method = "psci" 50 enable-method = "psci";
64 next-level-cache = <&L 51 next-level-cache = <&L2_0>;
65 }; 52 };
66 53
67 CPU2: cpu@2 { 54 CPU2: cpu@2 {
68 device_type = "cpu"; 55 device_type = "cpu";
69 compatible = "arm,cort 56 compatible = "arm,cortex-a53";
70 reg = <0x0 0x2>; 57 reg = <0x0 0x2>;
71 enable-method = "psci" 58 enable-method = "psci";
72 next-level-cache = <&L 59 next-level-cache = <&L2_0>;
73 }; 60 };
74 61
75 CPU3: cpu@3 { 62 CPU3: cpu@3 {
76 device_type = "cpu"; 63 device_type = "cpu";
77 compatible = "arm,cort 64 compatible = "arm,cortex-a53";
78 reg = <0x0 0x3>; 65 reg = <0x0 0x3>;
79 enable-method = "psci" 66 enable-method = "psci";
80 next-level-cache = <&L 67 next-level-cache = <&L2_0>;
81 }; 68 };
82 69
83 CPU4: cpu@100 { 70 CPU4: cpu@100 {
84 device_type = "cpu"; 71 device_type = "cpu";
85 compatible = "arm,cort 72 compatible = "arm,cortex-a57";
86 reg = <0x0 0x100>; 73 reg = <0x0 0x100>;
87 enable-method = "psci" 74 enable-method = "psci";
88 next-level-cache = <&L 75 next-level-cache = <&L2_1>;
89 L2_1: l2-cache { 76 L2_1: l2-cache {
90 compatible = " 77 compatible = "cache";
91 cache-level = 78 cache-level = <2>;
92 cache-unified; <<
93 }; 79 };
94 }; 80 };
95 81
96 CPU5: cpu@101 { 82 CPU5: cpu@101 {
97 device_type = "cpu"; 83 device_type = "cpu";
98 compatible = "arm,cort 84 compatible = "arm,cortex-a57";
99 reg = <0x0 0x101>; 85 reg = <0x0 0x101>;
100 enable-method = "psci" 86 enable-method = "psci";
101 next-level-cache = <&L 87 next-level-cache = <&L2_1>;
102 }; 88 };
103 89
104 CPU6: cpu@102 { 90 CPU6: cpu@102 {
105 device_type = "cpu"; 91 device_type = "cpu";
106 compatible = "arm,cort 92 compatible = "arm,cortex-a57";
107 reg = <0x0 0x102>; !! 93 reg = <0x0 0x101>;
108 enable-method = "psci" 94 enable-method = "psci";
109 next-level-cache = <&L 95 next-level-cache = <&L2_1>;
110 }; 96 };
111 97
112 CPU7: cpu@103 { 98 CPU7: cpu@103 {
113 device_type = "cpu"; 99 device_type = "cpu";
114 compatible = "arm,cort 100 compatible = "arm,cortex-a57";
115 reg = <0x0 0x103>; !! 101 reg = <0x0 0x101>;
116 enable-method = "psci" 102 enable-method = "psci";
117 next-level-cache = <&L 103 next-level-cache = <&L2_1>;
118 }; 104 };
119 105
120 cpu-map { 106 cpu-map {
121 cluster0 { 107 cluster0 {
122 core0 { 108 core0 {
123 cpu = 109 cpu = <&CPU0>;
124 }; 110 };
125 111
126 core1 { 112 core1 {
127 cpu = 113 cpu = <&CPU1>;
128 }; 114 };
129 115
130 core2 { 116 core2 {
131 cpu = 117 cpu = <&CPU2>;
132 }; 118 };
133 119
134 core3 { 120 core3 {
135 cpu = 121 cpu = <&CPU3>;
136 }; 122 };
137 }; 123 };
138 124
139 cluster1 { 125 cluster1 {
140 core0 { 126 core0 {
141 cpu = 127 cpu = <&CPU4>;
142 }; 128 };
143 129
144 core1 { 130 core1 {
145 cpu = 131 cpu = <&CPU5>;
146 }; 132 };
147 133
148 cpu6_map: core !! 134 core2 {
149 cpu = 135 cpu = <&CPU6>;
150 }; 136 };
151 137
152 cpu7_map: core !! 138 core3 {
153 cpu = 139 cpu = <&CPU7>;
154 }; 140 };
155 }; 141 };
156 }; 142 };
157 }; 143 };
158 144
159 firmware { 145 firmware {
160 scm { 146 scm {
161 compatible = "qcom,scm 147 compatible = "qcom,scm-msm8994", "qcom,scm";
162 }; 148 };
163 }; 149 };
164 150
165 memory@80000000 { !! 151 memory {
166 device_type = "memory"; 152 device_type = "memory";
167 /* We expect the bootloader to 153 /* We expect the bootloader to fill in the reg */
168 reg = <0 0x80000000 0 0>; !! 154 reg = <0 0 0 0>;
169 }; 155 };
170 156
171 pmu { 157 pmu {
172 compatible = "arm,cortex-a53-p 158 compatible = "arm,cortex-a53-pmu";
173 interrupts = <GIC_PPI 7 (GIC_C 159 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4)| IRQ_TYPE_LEVEL_HIGH)>;
174 }; 160 };
175 161
176 psci { 162 psci {
177 compatible = "arm,psci-0.2"; 163 compatible = "arm,psci-0.2";
178 method = "hvc"; 164 method = "hvc";
179 }; 165 };
180 166
181 rpm: remoteproc { !! 167 reserved-memory {
182 compatible = "qcom,msm8994-rpm !! 168 #address-cells = <2>;
>> 169 #size-cells = <2>;
>> 170 ranges;
183 171
184 smd-edge { !! 172 smem_mem: smem_region@6a00000 {
>> 173 reg = <0x0 0x6a00000 0x0 0x200000>;
>> 174 no-map;
>> 175 };
>> 176 };
>> 177
>> 178 smd {
>> 179 compatible = "qcom,smd";
>> 180 rpm {
185 interrupts = <GIC_SPI 181 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
186 mboxes = <&apcs 0>; !! 182 qcom,ipc = <&apcs 8 0>;
187 qcom,smd-edge = <15>; 183 qcom,smd-edge = <15>;
>> 184 qcom,local-pid = <0>;
188 qcom,remote-pid = <6>; 185 qcom,remote-pid = <6>;
189 186
190 rpm_requests: rpm-requ 187 rpm_requests: rpm-requests {
191 compatible = " !! 188 compatible = "qcom,rpm-msm8994";
192 qcom,smd-chann 189 qcom,smd-channels = "rpm_requests";
193 190
194 rpmcc: clock-c !! 191 rpmcc: rpmcc {
195 compat !! 192 compatible = "qcom,rpmcc-msm8994";
196 #clock 193 #clock-cells = <1>;
197 }; 194 };
198 <<
199 rpmpd: power-c <<
200 compat <<
201 #power <<
202 operat <<
203 <<
204 rpmpd_ <<
205 <<
206 <<
207 <<
208 <<
209 <<
210 <<
211 <<
212 <<
213 <<
214 <<
215 <<
216 <<
217 <<
218 <<
219 <<
220 <<
221 <<
222 <<
223 <<
224 <<
225 }; <<
226 }; <<
227 }; 195 };
228 }; 196 };
229 }; 197 };
230 198
231 reserved-memory { <<
232 #address-cells = <2>; <<
233 #size-cells = <2>; <<
234 ranges; <<
235 <<
236 dfps_data_mem: dfps-data@34000 <<
237 reg = <0 0x03400000 0 <<
238 no-map; <<
239 }; <<
240 <<
241 cont_splash_mem: memory@340100 <<
242 reg = <0 0x03401000 0 <<
243 no-map; <<
244 }; <<
245 <<
246 smem_mem: smem@6a00000 { <<
247 reg = <0 0x06a00000 0 <<
248 no-map; <<
249 }; <<
250 <<
251 mpss_mem: memory@7000000 { <<
252 reg = <0 0x07000000 0 <<
253 no-map; <<
254 }; <<
255 <<
256 peripheral_region: memory@ca00 <<
257 reg = <0 0x0ca00000 0 <<
258 no-map; <<
259 }; <<
260 <<
261 rmtfs_mem: memory@c6400000 { <<
262 compatible = "qcom,rmt <<
263 reg = <0 0xc6400000 0 <<
264 no-map; <<
265 <<
266 qcom,client-id = <1>; <<
267 }; <<
268 <<
269 mba_mem: memory@c6700000 { <<
270 reg = <0 0xc6700000 0 <<
271 no-map; <<
272 }; <<
273 <<
274 audio_mem: memory@c7000000 { <<
275 reg = <0 0xc7000000 0 <<
276 no-map; <<
277 }; <<
278 <<
279 adsp_mem: memory@c9400000 { <<
280 reg = <0 0xc9400000 0 <<
281 no-map; <<
282 }; <<
283 <<
284 res_hyp_mem: reserved@6c00000 <<
285 reg = <0 0x06c00000 0 <<
286 no-map; <<
287 }; <<
288 }; <<
289 <<
290 smem { 199 smem {
291 compatible = "qcom,smem"; 200 compatible = "qcom,smem";
292 memory-region = <&smem_mem>; 201 memory-region = <&smem_mem>;
293 qcom,rpm-msg-ram = <&rpm_msg_r 202 qcom,rpm-msg-ram = <&rpm_msg_ram>;
294 hwlocks = <&tcsr_mutex 3>; 203 hwlocks = <&tcsr_mutex 3>;
295 }; 204 };
296 205
297 smp2p-lpass { !! 206 soc: soc {
298 compatible = "qcom,smp2p"; <<
299 qcom,smem = <443>, <429>; <<
300 <<
301 interrupts = <GIC_SPI 158 IRQ_ <<
302 <<
303 mboxes = <&apcs 10>; <<
304 <<
305 qcom,local-pid = <0>; <<
306 qcom,remote-pid = <2>; <<
307 <<
308 adsp_smp2p_out: master-kernel <<
309 qcom,entry-name = "mas <<
310 #qcom,smem-state-cells <<
311 }; <<
312 <<
313 adsp_smp2p_in: slave-kernel { <<
314 qcom,entry-name = "sla <<
315 <<
316 interrupt-controller; <<
317 #interrupt-cells = <2> <<
318 }; <<
319 }; <<
320 <<
321 smp2p-modem { <<
322 compatible = "qcom,smp2p"; <<
323 qcom,smem = <435>, <428>; <<
324 <<
325 interrupt-parent = <&intc>; <<
326 interrupts = <GIC_SPI 27 IRQ_T <<
327 207
328 mboxes = <&apcs 14>; <<
329 <<
330 qcom,local-pid = <0>; <<
331 qcom,remote-pid = <1>; <<
332 <<
333 modem_smp2p_out: master-kernel <<
334 qcom,entry-name = "mas <<
335 #qcom,smem-state-cells <<
336 }; <<
337 <<
338 modem_smp2p_in: slave-kernel { <<
339 qcom,entry-name = "sla <<
340 <<
341 interrupt-controller; <<
342 #interrupt-cells = <2> <<
343 }; <<
344 }; <<
345 <<
346 soc: soc@0 { <<
347 #address-cells = <1>; 208 #address-cells = <1>;
348 #size-cells = <1>; 209 #size-cells = <1>;
349 ranges = <0 0 0 0xffffffff>; 210 ranges = <0 0 0 0xffffffff>;
350 compatible = "simple-bus"; 211 compatible = "simple-bus";
351 212
352 intc: interrupt-controller@f90 213 intc: interrupt-controller@f9000000 {
353 compatible = "qcom,msm 214 compatible = "qcom,msm-qgic2";
354 interrupt-controller; 215 interrupt-controller;
355 #interrupt-cells = <3> 216 #interrupt-cells = <3>;
356 reg = <0xf9000000 0x10 217 reg = <0xf9000000 0x1000>,
357 <0xf9002000 0x10 218 <0xf9002000 0x1000>;
358 }; 219 };
359 220
360 apcs: mailbox@f900d000 { 221 apcs: mailbox@f900d000 {
361 compatible = "qcom,msm 222 compatible = "qcom,msm8994-apcs-kpss-global", "syscon";
362 reg = <0xf900d000 0x20 223 reg = <0xf900d000 0x2000>;
363 #mbox-cells = <1>; 224 #mbox-cells = <1>;
364 }; 225 };
365 226
366 watchdog@f9017000 { <<
367 compatible = "qcom,aps <<
368 reg = <0xf9017000 0x10 <<
369 interrupts = <GIC_SPI <<
370 <GIC_SPI <<
371 clocks = <&sleep_clk>; <<
372 timeout-sec = <10>; <<
373 }; <<
374 <<
375 timer@f9020000 { 227 timer@f9020000 {
376 #address-cells = <1>; 228 #address-cells = <1>;
377 #size-cells = <1>; 229 #size-cells = <1>;
378 ranges; 230 ranges;
379 compatible = "arm,armv 231 compatible = "arm,armv7-timer-mem";
380 reg = <0xf9020000 0x10 232 reg = <0xf9020000 0x1000>;
381 233
382 frame@f9021000 { 234 frame@f9021000 {
383 frame-number = 235 frame-number = <0>;
384 interrupts = < 236 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
385 < 237 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
386 reg = <0xf9021 238 reg = <0xf9021000 0x1000>,
387 <0xf9022 239 <0xf9022000 0x1000>;
388 }; 240 };
389 241
390 frame@f9023000 { 242 frame@f9023000 {
391 frame-number = 243 frame-number = <1>;
392 interrupts = < 244 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
393 reg = <0xf9023 245 reg = <0xf9023000 0x1000>;
394 status = "disa 246 status = "disabled";
395 }; 247 };
396 248
397 frame@f9024000 { 249 frame@f9024000 {
398 frame-number = 250 frame-number = <2>;
399 interrupts = < 251 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
400 reg = <0xf9024 252 reg = <0xf9024000 0x1000>;
401 status = "disa 253 status = "disabled";
402 }; 254 };
403 255
404 frame@f9025000 { 256 frame@f9025000 {
405 frame-number = 257 frame-number = <3>;
406 interrupts = < 258 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
407 reg = <0xf9025 259 reg = <0xf9025000 0x1000>;
408 status = "disa 260 status = "disabled";
409 }; 261 };
410 262
411 frame@f9026000 { 263 frame@f9026000 {
412 frame-number = 264 frame-number = <4>;
413 interrupts = < 265 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
414 reg = <0xf9026 266 reg = <0xf9026000 0x1000>;
415 status = "disa 267 status = "disabled";
416 }; 268 };
417 269
418 frame@f9027000 { 270 frame@f9027000 {
419 frame-number = 271 frame-number = <5>;
420 interrupts = < 272 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
421 reg = <0xf9027 273 reg = <0xf9027000 0x1000>;
422 status = "disa 274 status = "disabled";
423 }; 275 };
424 276
425 frame@f9028000 { 277 frame@f9028000 {
426 frame-number = 278 frame-number = <6>;
427 interrupts = < 279 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
428 reg = <0xf9028 280 reg = <0xf9028000 0x1000>;
429 status = "disa 281 status = "disabled";
430 }; 282 };
431 }; 283 };
432 284
433 usb3: usb@f92f8800 { 285 usb3: usb@f92f8800 {
434 compatible = "qcom,msm !! 286 compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
435 reg = <0xf92f8800 0x40 287 reg = <0xf92f8800 0x400>;
436 #address-cells = <1>; 288 #address-cells = <1>;
437 #size-cells = <1>; 289 #size-cells = <1>;
438 ranges; 290 ranges;
439 291
440 clocks = <&gcc GCC_USB 292 clocks = <&gcc GCC_USB30_MASTER_CLK>,
441 <&gcc GCC_SYS 293 <&gcc GCC_SYS_NOC_USB3_AXI_CLK>,
442 <&gcc GCC_USB 294 <&gcc GCC_USB30_SLEEP_CLK>,
443 <&gcc GCC_USB 295 <&gcc GCC_USB30_MOCK_UTMI_CLK>;
444 clock-names = "core", !! 296 clock-names = "core", "iface", "sleep", "mock_utmi", "ref", "xo";
445 "iface", <<
446 "sleep", <<
447 "mock_ut <<
448 297
449 assigned-clocks = <&gc 298 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
450 <&gc 299 <&gcc GCC_USB30_MASTER_CLK>;
451 assigned-clock-rates = 300 assigned-clock-rates = <19200000>, <120000000>;
452 301
453 power-domains = <&gcc 302 power-domains = <&gcc USB30_GDSC>;
454 qcom,select-utmi-as-pi 303 qcom,select-utmi-as-pipe-clk;
455 304
456 usb@f9200000 { !! 305 dwc3@f9200000 {
457 compatible = " 306 compatible = "snps,dwc3";
458 reg = <0xf9200 307 reg = <0xf9200000 0xcc00>;
459 interrupts = < !! 308 interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>;
460 snps,dis_u2_su 309 snps,dis_u2_susphy_quirk;
461 snps,dis_enbls 310 snps,dis_enblslpm_quirk;
462 maximum-speed 311 maximum-speed = "high-speed";
463 dr_mode = "per 312 dr_mode = "peripheral";
464 }; 313 };
465 }; 314 };
466 315
467 sdhc1: mmc@f9824900 { !! 316 sdhc1: sdhci@f9824900 {
468 compatible = "qcom,msm !! 317 compatible = "qcom,sdhci-msm-v4";
469 reg = <0xf9824900 0x1a 318 reg = <0xf9824900 0x1a0>, <0xf9824000 0x800>;
470 reg-names = "hc", "cor !! 319 reg-names = "hc_mem", "core_mem";
471 320
472 interrupts = <GIC_SPI 321 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
473 <GIC_SPI 322 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
474 interrupt-names = "hc_ 323 interrupt-names = "hc_irq", "pwr_irq";
475 324
476 clocks = <&gcc GCC_SDC !! 325 clocks = <&gcc GCC_SDCC1_APPS_CLK>,
477 <&gcc GCC_SDC !! 326 <&gcc GCC_SDCC1_AHB_CLK>,
478 <&xo_board>; 327 <&xo_board>;
479 clock-names = "iface", !! 328 clock-names = "core", "iface", "xo";
480 329
481 pinctrl-names = "defau 330 pinctrl-names = "default", "sleep";
482 pinctrl-0 = <&sdc1_clk 331 pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>;
483 pinctrl-1 = <&sdc1_clk 332 pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>;
484 333
485 bus-width = <8>; 334 bus-width = <8>;
486 non-removable; 335 non-removable;
487 status = "disabled"; 336 status = "disabled";
488 }; 337 };
489 338
490 sdhc2: mmc@f98a4900 { !! 339 sdhc2: sdhci@f98a4900 {
491 compatible = "qcom,msm !! 340 compatible = "qcom,sdhci-msm-v4";
492 reg = <0xf98a4900 0x11 341 reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
493 reg-names = "hc", "cor !! 342 reg-names = "hc_mem", "core_mem";
494 343
495 interrupts = <GIC_SPI 344 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
496 <GIC_SPI 221 I 345 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
497 interrupt-names = "hc_ 346 interrupt-names = "hc_irq", "pwr_irq";
498 347
499 clocks = <&gcc GCC_SDC !! 348 clocks = <&gcc GCC_SDCC2_APPS_CLK>,
500 <&gcc GCC_SDC !! 349 <&gcc GCC_SDCC2_AHB_CLK>,
501 <&xo_board>; !! 350 <&xo_board>;
502 clock-names = "iface", !! 351 clock-names = "core", "iface", "xo";
503 352
504 pinctrl-names = "defau 353 pinctrl-names = "default", "sleep";
505 pinctrl-0 = <&sdc2_clk 354 pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>;
506 pinctrl-1 = <&sdc2_clk 355 pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>;
507 356
508 cd-gpios = <&tlmm 100 !! 357 cd-gpios = <&tlmm 100 0>;
509 bus-width = <4>; 358 bus-width = <4>;
510 status = "disabled"; 359 status = "disabled";
511 }; 360 };
512 361
513 blsp1_dma: dma-controller@f990 362 blsp1_dma: dma-controller@f9904000 {
514 compatible = "qcom,bam 363 compatible = "qcom,bam-v1.7.0";
515 reg = <0xf9904000 0x19 364 reg = <0xf9904000 0x19000>;
516 interrupts = <GIC_SPI 365 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
517 clocks = <&gcc GCC_BLS 366 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
518 clock-names = "bam_clk 367 clock-names = "bam_clk";
519 #dma-cells = <1>; 368 #dma-cells = <1>;
520 qcom,ee = <0>; 369 qcom,ee = <0>;
521 qcom,controlled-remote 370 qcom,controlled-remotely;
522 num-channels = <24>; !! 371 num-channels = <18>;
523 qcom,num-ees = <4>; 372 qcom,num-ees = <4>;
524 }; 373 };
525 374
526 blsp1_uart2: serial@f991e000 { 375 blsp1_uart2: serial@f991e000 {
527 compatible = "qcom,msm 376 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
528 reg = <0xf991e000 0x10 377 reg = <0xf991e000 0x1000>;
529 interrupts = <GIC_SPI 378 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
530 clock-names = "core", 379 clock-names = "core", "iface";
531 clocks = <&gcc GCC_BLS 380 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
532 <&gcc GCC_BLS 381 <&gcc GCC_BLSP1_AHB_CLK>;
533 pinctrl-names = "defau 382 pinctrl-names = "default", "sleep";
534 pinctrl-0 = <&blsp1_ua 383 pinctrl-0 = <&blsp1_uart2_default>;
535 pinctrl-1 = <&blsp1_ua 384 pinctrl-1 = <&blsp1_uart2_sleep>;
536 status = "disabled"; 385 status = "disabled";
537 }; 386 };
538 387
539 blsp1_i2c1: i2c@f9923000 { !! 388 blsp_i2c1: i2c@f9923000 {
540 compatible = "qcom,i2c 389 compatible = "qcom,i2c-qup-v2.2.1";
541 reg = <0xf9923000 0x50 390 reg = <0xf9923000 0x500>;
542 interrupts = <GIC_SPI 391 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
543 clocks = <&gcc GCC_BLS !! 392 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
544 <&gcc GCC_BLS !! 393 <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>;
545 clock-names = "core", !! 394 clock-names = "iface", "core";
546 clock-frequency = <400 395 clock-frequency = <400000>;
547 dmas = <&blsp1_dma 12> <<
548 dma-names = "tx", "rx" <<
549 pinctrl-names = "defau 396 pinctrl-names = "default", "sleep";
550 pinctrl-0 = <&i2c1_def 397 pinctrl-0 = <&i2c1_default>;
551 pinctrl-1 = <&i2c1_sle 398 pinctrl-1 = <&i2c1_sleep>;
552 #address-cells = <1>; 399 #address-cells = <1>;
553 #size-cells = <0>; 400 #size-cells = <0>;
554 status = "disabled"; 401 status = "disabled";
555 }; 402 };
556 403
557 blsp1_spi1: spi@f9923000 { !! 404 blsp_spi0: spi@f9923000 {
558 compatible = "qcom,spi 405 compatible = "qcom,spi-qup-v2.2.1";
559 reg = <0xf9923000 0x50 406 reg = <0xf9923000 0x500>;
560 interrupts = <GIC_SPI 407 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
561 clocks = <&gcc GCC_BLS 408 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
562 <&gcc GCC_BLS 409 <&gcc GCC_BLSP1_AHB_CLK>;
563 clock-names = "core", 410 clock-names = "core", "iface";
>> 411 spi-max-frequency = <19200000>;
564 dmas = <&blsp1_dma 12> 412 dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
565 dma-names = "tx", "rx" 413 dma-names = "tx", "rx";
566 pinctrl-names = "defau 414 pinctrl-names = "default", "sleep";
567 pinctrl-0 = <&blsp1_sp !! 415 pinctrl-0 = <&blsp1_spi0_default>;
568 pinctrl-1 = <&blsp1_sp !! 416 pinctrl-1 = <&blsp1_spi0_sleep>;
569 #address-cells = <1>; 417 #address-cells = <1>;
570 #size-cells = <0>; 418 #size-cells = <0>;
571 status = "disabled"; 419 status = "disabled";
572 }; 420 };
573 421
574 blsp1_i2c2: i2c@f9924000 { !! 422 blsp_i2c2: i2c@f9924000 {
575 compatible = "qcom,i2c 423 compatible = "qcom,i2c-qup-v2.2.1";
576 reg = <0xf9924000 0x50 424 reg = <0xf9924000 0x500>;
577 interrupts = <GIC_SPI 425 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
578 clocks = <&gcc GCC_BLS !! 426 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
579 <&gcc GCC_BLS !! 427 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
580 clock-names = "core", !! 428 clock-names = "iface", "core";
581 clock-frequency = <400 !! 429 clock-frequency = <355000>;
582 dmas = <&blsp1_dma 14> 430 dmas = <&blsp1_dma 14>, <&blsp1_dma 15>;
583 dma-names = "tx", "rx" 431 dma-names = "tx", "rx";
584 pinctrl-names = "defau 432 pinctrl-names = "default", "sleep";
585 pinctrl-0 = <&i2c2_def 433 pinctrl-0 = <&i2c2_default>;
586 pinctrl-1 = <&i2c2_sle 434 pinctrl-1 = <&i2c2_sleep>;
587 #address-cells = <1>; 435 #address-cells = <1>;
588 #size-cells = <0>; 436 #size-cells = <0>;
589 status = "disabled"; 437 status = "disabled";
590 }; 438 };
591 439
592 /* I2C3 doesn't exist */ 440 /* I2C3 doesn't exist */
593 441
594 blsp1_i2c4: i2c@f9926000 { !! 442 blsp_i2c4: i2c@f9926000 {
595 compatible = "qcom,i2c 443 compatible = "qcom,i2c-qup-v2.2.1";
596 reg = <0xf9926000 0x50 444 reg = <0xf9926000 0x500>;
597 interrupts = <GIC_SPI 445 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
598 clocks = <&gcc GCC_BLS !! 446 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
599 <&gcc GCC_BLS !! 447 <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
600 clock-names = "core", !! 448 clock-names = "iface", "core";
601 clock-frequency = <400 !! 449 clock-frequency = <355000>;
602 dmas = <&blsp1_dma 18> <<
603 dma-names = "tx", "rx" <<
604 pinctrl-names = "defau 450 pinctrl-names = "default", "sleep";
605 pinctrl-0 = <&i2c4_def 451 pinctrl-0 = <&i2c4_default>;
606 pinctrl-1 = <&i2c4_sle 452 pinctrl-1 = <&i2c4_sleep>;
607 #address-cells = <1>; 453 #address-cells = <1>;
608 #size-cells = <0>; 454 #size-cells = <0>;
609 status = "disabled"; 455 status = "disabled";
610 }; 456 };
611 457
612 blsp1_i2c5: i2c@f9927000 { !! 458 blsp2_dma: dma-controller@f9944000 {
613 compatible = "qcom,i2c !! 459 compatible = "qcom,bam-v1.7.0";
614 reg = <0xf9927000 0x50 !! 460 reg = <0xf9944000 0x19000>;
615 interrupts = <GIC_SPI !! 461 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
616 clocks = <&gcc GCC_BLS !! 462 clocks = <&gcc GCC_BLSP2_AHB_CLK>;
617 <&gcc GCC_BLS !! 463 clock-names = "bam_clk";
618 clock-names = "core", !! 464 #dma-cells = <1>;
619 clock-frequency = <400 !! 465 qcom,ee = <0>;
620 dmas = <&blsp2_dma 20> !! 466 qcom,controlled-remotely;
621 dma-names = "tx", "rx" !! 467 num-channels = <18>;
622 pinctrl-names = "defau !! 468 qcom,num-ees = <4>;
623 pinctrl-0 = <&i2c5_def <<
624 pinctrl-1 = <&i2c5_sle <<
625 #address-cells = <1>; <<
626 #size-cells = <0>; <<
627 status = "disabled"; <<
628 }; 469 };
629 470
630 blsp1_i2c6: i2c@f9928000 { !! 471 /* According to downstream kernels, i2c6
>> 472 * comes before i2c5 address-wise...
>> 473 */
>> 474
>> 475 blsp_i2c6: i2c@f9928000 {
631 compatible = "qcom,i2c 476 compatible = "qcom,i2c-qup-v2.2.1";
632 reg = <0xf9928000 0x50 477 reg = <0xf9928000 0x500>;
633 interrupts = <GIC_SPI 478 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
634 clocks = <&gcc GCC_BLS !! 479 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
635 <&gcc GCC_BLS !! 480 <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;
636 clock-names = "core", !! 481 clock-names = "iface", "core";
637 clock-frequency = <400 !! 482 clock-frequency = <355000>;
638 dmas = <&blsp1_dma 22> 483 dmas = <&blsp1_dma 22>, <&blsp1_dma 23>;
639 dma-names = "tx", "rx" 484 dma-names = "tx", "rx";
640 pinctrl-names = "defau 485 pinctrl-names = "default", "sleep";
641 pinctrl-0 = <&i2c6_def 486 pinctrl-0 = <&i2c6_default>;
642 pinctrl-1 = <&i2c6_sle 487 pinctrl-1 = <&i2c6_sleep>;
643 #address-cells = <1>; 488 #address-cells = <1>;
644 #size-cells = <0>; 489 #size-cells = <0>;
645 status = "disabled"; 490 status = "disabled";
646 }; 491 };
647 492
648 blsp2_dma: dma-controller@f994 <<
649 compatible = "qcom,bam <<
650 reg = <0xf9944000 0x19 <<
651 interrupts = <GIC_SPI <<
652 clocks = <&gcc GCC_BLS <<
653 clock-names = "bam_clk <<
654 #dma-cells = <1>; <<
655 qcom,ee = <0>; <<
656 qcom,controlled-remote <<
657 num-channels = <24>; <<
658 qcom,num-ees = <4>; <<
659 }; <<
660 <<
661 blsp2_uart2: serial@f995e000 { 493 blsp2_uart2: serial@f995e000 {
662 compatible = "qcom,msm 494 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
663 reg = <0xf995e000 0x10 495 reg = <0xf995e000 0x1000>;
664 interrupts = <GIC_SPI !! 496 interrupts = <GIC_SPI 146 IRQ_TYPE_EDGE_FALLING>;
665 clock-names = "core", 497 clock-names = "core", "iface";
666 clocks = <&gcc GCC_BLS 498 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
667 <&gcc 499 <&gcc GCC_BLSP2_AHB_CLK>;
668 dmas = <&blsp2_dma 2>, 500 dmas = <&blsp2_dma 2>, <&blsp2_dma 3>;
669 dma-names = "tx", "rx" 501 dma-names = "tx", "rx";
670 pinctrl-names = "defau 502 pinctrl-names = "default", "sleep";
671 pinctrl-0 = <&blsp2_ua 503 pinctrl-0 = <&blsp2_uart2_default>;
672 pinctrl-1 = <&blsp2_ua 504 pinctrl-1 = <&blsp2_uart2_sleep>;
673 status = "disabled"; 505 status = "disabled";
674 }; 506 };
675 507
676 blsp2_i2c1: i2c@f9963000 { !! 508 blsp_i2c5: i2c@f9967000 {
677 compatible = "qcom,i2c <<
678 reg = <0xf9963000 0x50 <<
679 interrupts = <GIC_SPI <<
680 clocks = <&gcc GCC_BLS <<
681 <&gcc GCC_BLS <<
682 clock-names = "core", <<
683 clock-frequency = <400 <<
684 dmas = <&blsp2_dma 12> <<
685 dma-names = "tx", "rx" <<
686 pinctrl-names = "defau <<
687 pinctrl-0 = <&i2c7_def <<
688 pinctrl-1 = <&i2c7_sle <<
689 #address-cells = <1>; <<
690 #size-cells = <0>; <<
691 status = "disabled"; <<
692 }; <<
693 <<
694 blsp2_spi4: spi@f9966000 { <<
695 compatible = "qcom,spi <<
696 reg = <0xf9966000 0x50 <<
697 interrupts = <GIC_SPI <<
698 clocks = <&gcc GCC_BLS <<
699 <&gcc GCC_BLS <<
700 clock-names = "core", <<
701 dmas = <&blsp2_dma 18> <<
702 dma-names = "tx", "rx" <<
703 pinctrl-names = "defau <<
704 pinctrl-0 = <&blsp2_sp <<
705 pinctrl-1 = <&blsp2_sp <<
706 #address-cells = <1>; <<
707 #size-cells = <0>; <<
708 status = "disabled"; <<
709 }; <<
710 <<
711 blsp2_i2c5: i2c@f9967000 { <<
712 compatible = "qcom,i2c 509 compatible = "qcom,i2c-qup-v2.2.1";
713 reg = <0xf9967000 0x50 510 reg = <0xf9967000 0x500>;
714 interrupts = <GIC_SPI 511 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
715 clocks = <&gcc GCC_BLS !! 512 clocks = <&gcc GCC_BLSP2_AHB_CLK>,
716 <&gcc GCC_BLS !! 513 <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>;
717 clock-names = "core", !! 514 clock-names = "iface", "core";
718 clock-frequency = <355 515 clock-frequency = <355000>;
719 dmas = <&blsp2_dma 20> 516 dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
720 dma-names = "tx", "rx" 517 dma-names = "tx", "rx";
721 pinctrl-names = "defau 518 pinctrl-names = "default", "sleep";
722 pinctrl-0 = <&i2c11_de !! 519 pinctrl-0 = <&i2c5_default>;
723 pinctrl-1 = <&i2c11_sl !! 520 pinctrl-1 = <&i2c5_sleep>;
724 #address-cells = <1>; 521 #address-cells = <1>;
725 #size-cells = <0>; 522 #size-cells = <0>;
726 status = "disabled"; 523 status = "disabled";
727 }; 524 };
728 525
729 gcc: clock-controller@fc400000 526 gcc: clock-controller@fc400000 {
730 compatible = "qcom,gcc 527 compatible = "qcom,gcc-msm8994";
731 #clock-cells = <1>; 528 #clock-cells = <1>;
732 #reset-cells = <1>; 529 #reset-cells = <1>;
733 #power-domain-cells = 530 #power-domain-cells = <1>;
734 reg = <0xfc400000 0x20 531 reg = <0xfc400000 0x2000>;
735 <<
736 clock-names = "xo", "s <<
737 clocks = <&xo_board>, <<
738 }; 532 };
739 533
740 rpm_msg_ram: sram@fc428000 { !! 534 rpm_msg_ram: memory@fc428000 {
741 compatible = "qcom,rpm 535 compatible = "qcom,rpm-msg-ram";
742 reg = <0xfc428000 0x40 536 reg = <0xfc428000 0x4000>;
743 }; 537 };
744 538
745 restart@fc4ab000 { 539 restart@fc4ab000 {
746 compatible = "qcom,psh 540 compatible = "qcom,pshold";
747 reg = <0xfc4ab000 0x4> 541 reg = <0xfc4ab000 0x4>;
748 }; 542 };
749 543
750 spmi_bus: spmi@fc4cf000 { !! 544 spmi_bus: spmi@fc4c0000 {
751 compatible = "qcom,spm 545 compatible = "qcom,spmi-pmic-arb";
752 reg = <0xfc4cf000 0x10 546 reg = <0xfc4cf000 0x1000>,
753 <0xfc4cb000 0x10 547 <0xfc4cb000 0x1000>,
754 <0xfc4ca000 0x10 548 <0xfc4ca000 0x1000>;
755 reg-names = "core", "i 549 reg-names = "core", "intr", "cnfg";
756 interrupt-names = "per 550 interrupt-names = "periph_irq";
757 interrupts = <GIC_SPI 551 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
758 qcom,ee = <0>; 552 qcom,ee = <0>;
759 qcom,channel = <0>; 553 qcom,channel = <0>;
760 #address-cells = <2>; 554 #address-cells = <2>;
761 #size-cells = <0>; 555 #size-cells = <0>;
762 interrupt-controller; 556 interrupt-controller;
763 #interrupt-cells = <4> 557 #interrupt-cells = <4>;
764 }; 558 };
765 559
766 tcsr_mutex: hwlock@fd484000 { !! 560 tcsr_mutex_regs: syscon@fd484000 {
767 compatible = "qcom,msm !! 561 compatible = "syscon";
768 reg = <0xfd484000 0x10 !! 562 reg = <0xfd484000 0x2000>;
769 #hwlock-cells = <1>; <<
770 }; 563 };
771 564
772 tlmm: pinctrl@fd510000 { 565 tlmm: pinctrl@fd510000 {
773 compatible = "qcom,msm 566 compatible = "qcom,msm8994-pinctrl";
774 reg = <0xfd510000 0x40 567 reg = <0xfd510000 0x4000>;
775 interrupts = <GIC_SPI 568 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
776 gpio-controller; 569 gpio-controller;
777 gpio-ranges = <&tlmm 0 570 gpio-ranges = <&tlmm 0 0 146>;
778 #gpio-cells = <2>; 571 #gpio-cells = <2>;
779 interrupt-controller; 572 interrupt-controller;
780 #interrupt-cells = <2> 573 #interrupt-cells = <2>;
781 574
782 blsp1_uart2_default: b !! 575 blsp1_uart2_default: blsp1-uart2-default {
783 pins = "gpio4" <<
784 function = "bl 576 function = "blsp_uart2";
>> 577 pins = "gpio4", "gpio5";
785 drive-strength 578 drive-strength = <16>;
786 bias-disable; 579 bias-disable;
787 }; 580 };
788 581
789 blsp1_uart2_sleep: bls !! 582 blsp1_uart2_sleep: blsp1-uart2-sleep {
790 pins = "gpio4" <<
791 function = "gp 583 function = "gpio";
>> 584 pins = "gpio4", "gpio5";
792 drive-strength 585 drive-strength = <2>;
793 bias-pull-down 586 bias-pull-down;
794 }; 587 };
795 588
796 blsp2_uart2_default: b !! 589 blsp2_uart2_default: blsp2-uart2-default {
797 pins = "gpio45 <<
798 function = "bl 590 function = "blsp_uart8";
799 drive-strength !! 591 pins = "gpio45", "gpio46";
>> 592 drive-strength = <2>;
800 bias-disable; 593 bias-disable;
801 }; 594 };
802 595
803 blsp2_uart2_sleep: bls !! 596 blsp2_uart2_sleep: blsp2-uart2-sleep {
804 pins = "gpio45 <<
805 function = "gp 597 function = "gpio";
>> 598 pins = "gpio45", "gpio46";
806 drive-strength 599 drive-strength = <2>;
807 bias-disable; !! 600 bias-pull-down;
808 }; 601 };
809 602
810 i2c1_default: i2c1-def !! 603 i2c1_default: i2c1-default {
811 pins = "gpio2" <<
812 function = "bl 604 function = "blsp_i2c1";
>> 605 pins = "gpio2", "gpio3";
813 drive-strength 606 drive-strength = <2>;
814 bias-disable; 607 bias-disable;
815 }; 608 };
816 609
817 i2c1_sleep: i2c1-sleep !! 610 i2c1_sleep: i2c1-sleep {
818 pins = "gpio2" <<
819 function = "gp 611 function = "gpio";
>> 612 pins = "gpio2", "gpio3";
820 drive-strength 613 drive-strength = <2>;
821 bias-disable; 614 bias-disable;
822 }; 615 };
823 616
824 i2c2_default: i2c2-def !! 617 i2c2_default: i2c2-default {
825 pins = "gpio6" <<
826 function = "bl 618 function = "blsp_i2c2";
>> 619 pins = "gpio6", "gpio7";
827 drive-strength 620 drive-strength = <2>;
828 bias-disable; 621 bias-disable;
829 }; 622 };
830 623
831 i2c2_sleep: i2c2-sleep !! 624 i2c2_sleep: i2c2-sleep {
832 pins = "gpio6" <<
833 function = "gp 625 function = "gpio";
>> 626 pins = "gpio6", "gpio7";
834 drive-strength 627 drive-strength = <2>;
835 bias-disable; 628 bias-disable;
836 }; 629 };
837 630
838 i2c4_default: i2c4-def !! 631 i2c4_default: i2c4-default {
839 pins = "gpio19 <<
840 function = "bl 632 function = "blsp_i2c4";
>> 633 pins = "gpio19", "gpio20";
841 drive-strength 634 drive-strength = <2>;
842 bias-disable; 635 bias-disable;
843 }; 636 };
844 637
845 i2c4_sleep: i2c4-sleep !! 638 i2c4_sleep: i2c4-sleep {
846 pins = "gpio19 <<
847 function = "gp 639 function = "gpio";
>> 640 pins = "gpio19", "gpio20";
848 drive-strength 641 drive-strength = <2>;
849 bias-pull-down 642 bias-pull-down;
>> 643 input-enable;
850 }; 644 };
851 645
852 i2c5_default: i2c5-def !! 646 i2c5_default: i2c5-default {
853 pins = "gpio23 <<
854 function = "bl 647 function = "blsp_i2c5";
>> 648 pins = "gpio23", "gpio24";
855 drive-strength 649 drive-strength = <2>;
856 bias-disable; 650 bias-disable;
857 }; 651 };
858 652
859 i2c5_sleep: i2c5-sleep !! 653 i2c5_sleep: i2c5-sleep {
860 pins = "gpio23 <<
861 function = "gp 654 function = "gpio";
>> 655 pins = "gpio23", "gpio24";
862 drive-strength 656 drive-strength = <2>;
863 bias-disable; 657 bias-disable;
864 }; 658 };
865 659
866 i2c6_default: i2c6-def !! 660 i2c6_default: i2c6-default {
867 pins = "gpio28 <<
868 function = "bl 661 function = "blsp_i2c6";
869 drive-strength <<
870 bias-disable; <<
871 }; <<
872 <<
873 i2c6_sleep: i2c6-sleep <<
874 pins = "gpio28 662 pins = "gpio28", "gpio27";
875 function = "gp <<
876 drive-strength 663 drive-strength = <2>;
877 bias-disable; 664 bias-disable;
878 }; 665 };
879 666
880 i2c7_default: i2c7-def !! 667 i2c6_sleep: i2c6-sleep {
881 pins = "gpio44 <<
882 function = "bl <<
883 drive-strength <<
884 bias-disable; <<
885 }; <<
886 <<
887 i2c7_sleep: i2c7-sleep <<
888 pins = "gpio44 <<
889 function = "gp <<
890 drive-strength <<
891 bias-disable; <<
892 }; <<
893 <<
894 blsp2_spi10_default: b <<
895 default-pins { <<
896 pins = <<
897 functi <<
898 drive- <<
899 bias-p <<
900 }; <<
901 <<
902 cs-pins { <<
903 pins = <<
904 functi <<
905 drive- <<
906 bias-d <<
907 }; <<
908 }; <<
909 <<
910 blsp2_spi10_sleep: bls <<
911 pins = "gpio53 <<
912 function = "gp <<
913 drive-strength <<
914 bias-disable; <<
915 }; <<
916 <<
917 i2c11_default: i2c11-d <<
918 pins = "gpio83 <<
919 function = "bl <<
920 drive-strength <<
921 bias-disable; <<
922 }; <<
923 <<
924 i2c11_sleep: i2c11-sle <<
925 pins = "gpio83 <<
926 function = "gp 668 function = "gpio";
>> 669 pins = "gpio28", "gpio27";
927 drive-strength 670 drive-strength = <2>;
928 bias-disable; 671 bias-disable;
929 }; 672 };
930 673
931 blsp1_spi1_default: bl !! 674 blsp1_spi0_default: blsp1-spi0-default {
932 default-pins { !! 675 default {
933 pins = <<
934 functi 676 function = "blsp_spi1";
>> 677 pins = "gpio0", "gpio1", "gpio3";
935 drive- 678 drive-strength = <10>;
936 bias-p 679 bias-pull-down;
937 }; 680 };
938 !! 681 cs {
939 cs-pins { <<
940 pins = <<
941 functi 682 function = "gpio";
>> 683 pins = "gpio8";
942 drive- 684 drive-strength = <2>;
943 bias-d 685 bias-disable;
944 }; 686 };
945 }; 687 };
946 688
947 blsp1_spi1_sleep: blsp !! 689 blsp1_spi0_sleep: blsp1-spi0-sleep {
948 pins = "gpio0" 690 pins = "gpio0", "gpio1", "gpio3";
949 function = "gp <<
950 drive-strength 691 drive-strength = <2>;
951 bias-disable; 692 bias-disable;
952 }; 693 };
953 694
954 sdc1_clk_on: clk-on-st !! 695 sdc1_clk_on: clk-on {
955 pins = "sdc1_c 696 pins = "sdc1_clk";
956 bias-disable; 697 bias-disable;
957 drive-strength 698 drive-strength = <16>;
958 }; 699 };
959 700
960 sdc1_clk_off: clk-off- !! 701 sdc1_clk_off: clk-off {
961 pins = "sdc1_c 702 pins = "sdc1_clk";
962 bias-disable; 703 bias-disable;
963 drive-strength 704 drive-strength = <2>;
964 }; 705 };
965 706
966 sdc1_cmd_on: cmd-on-st !! 707 sdc1_cmd_on: cmd-on {
967 pins = "sdc1_c 708 pins = "sdc1_cmd";
968 bias-pull-up; 709 bias-pull-up;
969 drive-strength 710 drive-strength = <8>;
970 }; 711 };
971 712
972 sdc1_cmd_off: cmd-off- !! 713 sdc1_cmd_off: cmd-off {
973 pins = "sdc1_c 714 pins = "sdc1_cmd";
974 bias-pull-up; 715 bias-pull-up;
975 drive-strength 716 drive-strength = <2>;
976 }; 717 };
977 718
978 sdc1_data_on: data-on- !! 719 sdc1_data_on: data-on {
979 pins = "sdc1_d 720 pins = "sdc1_data";
980 bias-pull-up; 721 bias-pull-up;
981 drive-strength 722 drive-strength = <8>;
982 }; 723 };
983 724
984 sdc1_data_off: data-of !! 725 sdc1_data_off: data-off {
985 pins = "sdc1_d 726 pins = "sdc1_data";
986 bias-pull-up; 727 bias-pull-up;
987 drive-strength 728 drive-strength = <2>;
988 }; 729 };
989 730
990 sdc1_rclk_on: rclk-on- !! 731 sdc1_rclk_on: rclk-on {
991 pins = "sdc1_r 732 pins = "sdc1_rclk";
992 bias-pull-down 733 bias-pull-down;
993 }; 734 };
994 735
995 sdc1_rclk_off: rclk-of !! 736 sdc1_rclk_off: rclk-off {
996 pins = "sdc1_r 737 pins = "sdc1_rclk";
997 bias-pull-down 738 bias-pull-down;
998 }; 739 };
999 740
1000 sdc2_clk_on: sdc2-clk !! 741 sdc2_clk_on: sdc2-clk-on {
1001 pins = "sdc2_ 742 pins = "sdc2_clk";
1002 bias-disable; 743 bias-disable;
1003 drive-strengt 744 drive-strength = <10>;
1004 }; 745 };
1005 746
1006 sdc2_clk_off: sdc2-cl !! 747 sdc2_clk_off: sdc2-clk-off {
1007 pins = "sdc2_ 748 pins = "sdc2_clk";
1008 bias-disable; 749 bias-disable;
1009 drive-strengt 750 drive-strength = <2>;
1010 }; 751 };
1011 752
1012 sdc2_cmd_on: sdc2-cmd !! 753 sdc2_cmd_on: sdc2-cmd-on {
1013 pins = "sdc2_ 754 pins = "sdc2_cmd";
1014 bias-pull-up; 755 bias-pull-up;
1015 drive-strengt 756 drive-strength = <10>;
1016 }; 757 };
1017 758
1018 sdc2_cmd_off: sdc2-cm !! 759 sdc2_cmd_off: sdc2-cmd-off {
1019 pins = "sdc2_ 760 pins = "sdc2_cmd";
1020 bias-pull-up; 761 bias-pull-up;
1021 drive-strengt 762 drive-strength = <2>;
1022 }; 763 };
1023 764
1024 sdc2_data_on: sdc2-da !! 765 sdc2_data_on: sdc2-data-on {
1025 pins = "sdc2_ 766 pins = "sdc2_data";
1026 bias-pull-up; 767 bias-pull-up;
1027 drive-strengt 768 drive-strength = <10>;
1028 }; 769 };
1029 770
1030 sdc2_data_off: sdc2-d !! 771 sdc2_data_off: sdc2-data-off {
1031 pins = "sdc2_ 772 pins = "sdc2_data";
1032 bias-pull-up; 773 bias-pull-up;
1033 drive-strengt 774 drive-strength = <2>;
1034 }; 775 };
1035 }; 776 };
>> 777 };
1036 778
1037 mmcc: clock-controller@fd8c00 !! 779 tcsr_mutex: hwlock {
1038 compatible = "qcom,mm !! 780 compatible = "qcom,tcsr-mutex";
1039 reg = <0xfd8c0000 0x5 !! 781 syscon = <&tcsr_mutex_regs 0 0x80>;
1040 #clock-cells = <1>; !! 782 #hwlock-cells = <1>;
1041 #reset-cells = <1>; <<
1042 #power-domain-cells = <<
1043 <<
1044 clock-names = "xo", <<
1045 "gpll0" <<
1046 "mmssno <<
1047 "oxili_ <<
1048 "dsi0pl <<
1049 "dsi0pl <<
1050 "dsi1pl <<
1051 "dsi1pl <<
1052 "hdmipl <<
1053 clocks = <&xo_board>, <<
1054 <&gcc GPLL0_ <<
1055 <&rpmcc RPM_ <<
1056 <&rpmcc RPM_ <<
1057 <0>, <<
1058 <0>, <<
1059 <0>, <<
1060 <0>, <<
1061 <0>; <<
1062 <<
1063 assigned-clocks = <&m <<
1064 <&m <<
1065 <&m <<
1066 <&m <<
1067 <&m <<
1068 assigned-clock-rates <<
1069 <<
1070 <<
1071 <<
1072 <<
1073 }; <<
1074 <<
1075 ocmem: sram@fdd00000 { <<
1076 compatible = "qcom,ms <<
1077 reg = <0xfdd00000 0x2 <<
1078 <0xfec00000 0x2 <<
1079 reg-names = "ctrl", " <<
1080 ranges = <0 0xfec0000 <<
1081 clocks = <&rpmcc RPM_ <<
1082 <&mmcc OCMEM <<
1083 clock-names = "core", <<
1084 <<
1085 #address-cells = <1>; <<
1086 #size-cells = <1>; <<
1087 <<
1088 gmu_sram: gmu-sram@0 <<
1089 reg = <0x0 0x <<
1090 }; <<
1091 }; <<
1092 }; 783 };
1093 784
1094 timer: timer { !! 785 timer {
1095 compatible = "arm,armv8-timer 786 compatible = "arm,armv8-timer";
1096 interrupts = <GIC_PPI 2 (GIC_ !! 787 interrupts = <GIC_PPI 2 0xff08>,
1097 <GIC_PPI 3 (GIC_ !! 788 <GIC_PPI 3 0xff08>,
1098 <GIC_PPI 4 (GIC_ !! 789 <GIC_PPI 4 0xff08>,
1099 <GIC_PPI 1 (GIC_ !! 790 <GIC_PPI 1 0xff08>;
1100 }; 791 };
1101 792
1102 vph_pwr: vph-pwr-regulator { !! 793 vreg_vph_pwr: vreg-vph-pwr {
1103 compatible = "regulator-fixed 794 compatible = "regulator-fixed";
1104 regulator-name = "vph_pwr"; !! 795 regulator-name = "vph-pwr";
1105 796
1106 regulator-min-microvolt = <36 797 regulator-min-microvolt = <3600000>;
1107 regulator-max-microvolt = <36 798 regulator-max-microvolt = <3600000>;
1108 799
1109 regulator-always-on; 800 regulator-always-on;
1110 }; 801 };
1111 }; 802 };
1112 803
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