1 // SPDX-License-Identifier: GPL-2.0-only 1 // SPDX-License-Identifier: GPL-2.0-only
2 /* !! 2 /* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
3 * Copyright (c) 2013-2016, The Linux Foundati <<
4 */ 3 */
5 4
6 #include <dt-bindings/interrupt-controller/arm 5 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,gcc-msm8994.h 6 #include <dt-bindings/clock/qcom,gcc-msm8994.h>
8 #include <dt-bindings/clock/qcom,mmcc-msm8994. <<
9 #include <dt-bindings/clock/qcom,rpmcc.h> <<
10 #include <dt-bindings/gpio/gpio.h> <<
11 #include <dt-bindings/power/qcom-rpmpd.h> 7 #include <dt-bindings/power/qcom-rpmpd.h>
12 8
13 / { 9 / {
14 interrupt-parent = <&intc>; 10 interrupt-parent = <&intc>;
15 11
16 #address-cells = <2>; 12 #address-cells = <2>;
17 #size-cells = <2>; 13 #size-cells = <2>;
18 14
19 aliases { <<
20 mmc1 = &sdhc1; <<
21 mmc2 = &sdhc2; <<
22 }; <<
23 <<
24 chosen { }; 15 chosen { };
25 16
26 clocks { 17 clocks {
27 xo_board: xo-board { !! 18 xo_board: xo_board {
28 compatible = "fixed-cl 19 compatible = "fixed-clock";
29 #clock-cells = <0>; 20 #clock-cells = <0>;
30 clock-frequency = <192 21 clock-frequency = <19200000>;
31 clock-output-names = " <<
32 }; 22 };
33 23
34 sleep_clk: sleep-clk { !! 24 sleep_clk: sleep_clk {
35 compatible = "fixed-cl 25 compatible = "fixed-clock";
36 #clock-cells = <0>; 26 #clock-cells = <0>;
37 clock-frequency = <327 27 clock-frequency = <32768>;
38 clock-output-names = " <<
39 }; 28 };
40 }; 29 };
41 30
42 cpus { 31 cpus {
43 #address-cells = <2>; 32 #address-cells = <2>;
44 #size-cells = <0>; 33 #size-cells = <0>;
45 34
46 CPU0: cpu@0 { 35 CPU0: cpu@0 {
47 device_type = "cpu"; 36 device_type = "cpu";
48 compatible = "arm,cort 37 compatible = "arm,cortex-a53";
49 reg = <0x0 0x0>; 38 reg = <0x0 0x0>;
50 enable-method = "psci" 39 enable-method = "psci";
51 next-level-cache = <&L 40 next-level-cache = <&L2_0>;
52 L2_0: l2-cache { 41 L2_0: l2-cache {
53 compatible = " 42 compatible = "cache";
54 cache-level = 43 cache-level = <2>;
55 cache-unified; <<
56 }; 44 };
57 }; 45 };
58 46
59 CPU1: cpu@1 { 47 CPU1: cpu@1 {
60 device_type = "cpu"; 48 device_type = "cpu";
61 compatible = "arm,cort 49 compatible = "arm,cortex-a53";
62 reg = <0x0 0x1>; 50 reg = <0x0 0x1>;
63 enable-method = "psci" 51 enable-method = "psci";
64 next-level-cache = <&L 52 next-level-cache = <&L2_0>;
65 }; 53 };
66 54
67 CPU2: cpu@2 { 55 CPU2: cpu@2 {
68 device_type = "cpu"; 56 device_type = "cpu";
69 compatible = "arm,cort 57 compatible = "arm,cortex-a53";
70 reg = <0x0 0x2>; 58 reg = <0x0 0x2>;
71 enable-method = "psci" 59 enable-method = "psci";
72 next-level-cache = <&L 60 next-level-cache = <&L2_0>;
73 }; 61 };
74 62
75 CPU3: cpu@3 { 63 CPU3: cpu@3 {
76 device_type = "cpu"; 64 device_type = "cpu";
77 compatible = "arm,cort 65 compatible = "arm,cortex-a53";
78 reg = <0x0 0x3>; 66 reg = <0x0 0x3>;
79 enable-method = "psci" 67 enable-method = "psci";
80 next-level-cache = <&L 68 next-level-cache = <&L2_0>;
81 }; 69 };
82 70
83 CPU4: cpu@100 { 71 CPU4: cpu@100 {
84 device_type = "cpu"; 72 device_type = "cpu";
85 compatible = "arm,cort 73 compatible = "arm,cortex-a57";
86 reg = <0x0 0x100>; 74 reg = <0x0 0x100>;
87 enable-method = "psci" 75 enable-method = "psci";
88 next-level-cache = <&L 76 next-level-cache = <&L2_1>;
89 L2_1: l2-cache { 77 L2_1: l2-cache {
90 compatible = " 78 compatible = "cache";
91 cache-level = 79 cache-level = <2>;
92 cache-unified; <<
93 }; 80 };
94 }; 81 };
95 82
96 CPU5: cpu@101 { 83 CPU5: cpu@101 {
97 device_type = "cpu"; 84 device_type = "cpu";
98 compatible = "arm,cort 85 compatible = "arm,cortex-a57";
99 reg = <0x0 0x101>; 86 reg = <0x0 0x101>;
100 enable-method = "psci" 87 enable-method = "psci";
101 next-level-cache = <&L 88 next-level-cache = <&L2_1>;
102 }; 89 };
103 90
104 CPU6: cpu@102 { 91 CPU6: cpu@102 {
105 device_type = "cpu"; 92 device_type = "cpu";
106 compatible = "arm,cort 93 compatible = "arm,cortex-a57";
107 reg = <0x0 0x102>; !! 94 reg = <0x0 0x101>;
108 enable-method = "psci" 95 enable-method = "psci";
109 next-level-cache = <&L 96 next-level-cache = <&L2_1>;
110 }; 97 };
111 98
112 CPU7: cpu@103 { 99 CPU7: cpu@103 {
113 device_type = "cpu"; 100 device_type = "cpu";
114 compatible = "arm,cort 101 compatible = "arm,cortex-a57";
115 reg = <0x0 0x103>; !! 102 reg = <0x0 0x101>;
116 enable-method = "psci" 103 enable-method = "psci";
117 next-level-cache = <&L 104 next-level-cache = <&L2_1>;
118 }; 105 };
119 106
120 cpu-map { 107 cpu-map {
121 cluster0 { 108 cluster0 {
122 core0 { 109 core0 {
123 cpu = 110 cpu = <&CPU0>;
124 }; 111 };
125 112
126 core1 { 113 core1 {
127 cpu = 114 cpu = <&CPU1>;
128 }; 115 };
129 116
130 core2 { 117 core2 {
131 cpu = 118 cpu = <&CPU2>;
132 }; 119 };
133 120
134 core3 { 121 core3 {
135 cpu = 122 cpu = <&CPU3>;
136 }; 123 };
137 }; 124 };
138 125
139 cluster1 { 126 cluster1 {
140 core0 { 127 core0 {
141 cpu = 128 cpu = <&CPU4>;
142 }; 129 };
143 130
144 core1 { 131 core1 {
145 cpu = 132 cpu = <&CPU5>;
146 }; 133 };
147 134
148 cpu6_map: core 135 cpu6_map: core2 {
149 cpu = 136 cpu = <&CPU6>;
150 }; 137 };
151 138
152 cpu7_map: core 139 cpu7_map: core3 {
153 cpu = 140 cpu = <&CPU7>;
154 }; 141 };
155 }; 142 };
156 }; 143 };
157 }; 144 };
158 145
159 firmware { 146 firmware {
160 scm { 147 scm {
161 compatible = "qcom,scm 148 compatible = "qcom,scm-msm8994", "qcom,scm";
162 }; 149 };
163 }; 150 };
164 151
165 memory@80000000 { !! 152 memory {
166 device_type = "memory"; 153 device_type = "memory";
167 /* We expect the bootloader to 154 /* We expect the bootloader to fill in the reg */
168 reg = <0 0x80000000 0 0>; !! 155 reg = <0 0 0 0>;
>> 156 };
>> 157
>> 158 tcsr_mutex: hwlock {
>> 159 compatible = "qcom,tcsr-mutex";
>> 160 syscon = <&tcsr_mutex_regs 0 0x80>;
>> 161 #hwlock-cells = <1>;
169 }; 162 };
170 163
171 pmu { 164 pmu {
172 compatible = "arm,cortex-a53-p 165 compatible = "arm,cortex-a53-pmu";
173 interrupts = <GIC_PPI 7 (GIC_C 166 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4)| IRQ_TYPE_LEVEL_HIGH)>;
174 }; 167 };
175 168
176 psci { 169 psci {
177 compatible = "arm,psci-0.2"; 170 compatible = "arm,psci-0.2";
178 method = "hvc"; 171 method = "hvc";
179 }; 172 };
180 173
181 rpm: remoteproc { <<
182 compatible = "qcom,msm8994-rpm <<
183 <<
184 smd-edge { <<
185 interrupts = <GIC_SPI <<
186 mboxes = <&apcs 0>; <<
187 qcom,smd-edge = <15>; <<
188 qcom,remote-pid = <6>; <<
189 <<
190 rpm_requests: rpm-requ <<
191 compatible = " <<
192 qcom,smd-chann <<
193 <<
194 rpmcc: clock-c <<
195 compat <<
196 #clock <<
197 }; <<
198 <<
199 rpmpd: power-c <<
200 compat <<
201 #power <<
202 operat <<
203 <<
204 rpmpd_ <<
205 <<
206 <<
207 <<
208 <<
209 <<
210 <<
211 <<
212 <<
213 <<
214 <<
215 <<
216 <<
217 <<
218 <<
219 <<
220 <<
221 <<
222 <<
223 <<
224 <<
225 }; <<
226 }; <<
227 }; <<
228 }; <<
229 }; <<
230 <<
231 reserved-memory { 174 reserved-memory {
232 #address-cells = <2>; 175 #address-cells = <2>;
233 #size-cells = <2>; 176 #size-cells = <2>;
234 ranges; 177 ranges;
235 178
236 dfps_data_mem: dfps-data@34000 !! 179 dfps_data_mem: dfps_data_mem@3400000 {
237 reg = <0 0x03400000 0 180 reg = <0 0x03400000 0 0x1000>;
238 no-map; 181 no-map;
239 }; 182 };
240 183
241 cont_splash_mem: memory@340100 !! 184 cont_splash_mem: memory@3800000 {
242 reg = <0 0x03401000 0 !! 185 reg = <0 0x03800000 0 0x2400000>;
243 no-map; 186 no-map;
244 }; 187 };
245 188
246 smem_mem: smem@6a00000 { !! 189 smem_mem: smem_region@6a00000 {
247 reg = <0 0x06a00000 0 190 reg = <0 0x06a00000 0 0x200000>;
248 no-map; 191 no-map;
249 }; 192 };
250 193
251 mpss_mem: memory@7000000 { 194 mpss_mem: memory@7000000 {
252 reg = <0 0x07000000 0 195 reg = <0 0x07000000 0 0x5a00000>;
253 no-map; 196 no-map;
254 }; 197 };
255 198
256 peripheral_region: memory@ca00 199 peripheral_region: memory@ca00000 {
257 reg = <0 0x0ca00000 0 200 reg = <0 0x0ca00000 0 0x1f00000>;
258 no-map; 201 no-map;
259 }; 202 };
260 203
261 rmtfs_mem: memory@c6400000 { 204 rmtfs_mem: memory@c6400000 {
262 compatible = "qcom,rmt 205 compatible = "qcom,rmtfs-mem";
263 reg = <0 0xc6400000 0 206 reg = <0 0xc6400000 0 0x180000>;
264 no-map; 207 no-map;
265 208
266 qcom,client-id = <1>; 209 qcom,client-id = <1>;
267 }; 210 };
268 211
269 mba_mem: memory@c6700000 { 212 mba_mem: memory@c6700000 {
270 reg = <0 0xc6700000 0 213 reg = <0 0xc6700000 0 0x100000>;
271 no-map; 214 no-map;
272 }; 215 };
273 216
274 audio_mem: memory@c7000000 { 217 audio_mem: memory@c7000000 {
275 reg = <0 0xc7000000 0 218 reg = <0 0xc7000000 0 0x800000>;
276 no-map; 219 no-map;
277 }; 220 };
278 221
279 adsp_mem: memory@c9400000 { 222 adsp_mem: memory@c9400000 {
280 reg = <0 0xc9400000 0 223 reg = <0 0xc9400000 0 0x3f00000>;
281 no-map; 224 no-map;
282 }; 225 };
>> 226 };
283 227
284 res_hyp_mem: reserved@6c00000 !! 228 smd {
285 reg = <0 0x06c00000 0 !! 229 compatible = "qcom,smd";
286 no-map; !! 230 rpm {
>> 231 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
>> 232 qcom,ipc = <&apcs 8 0>;
>> 233 qcom,smd-edge = <15>;
>> 234 qcom,local-pid = <0>;
>> 235 qcom,remote-pid = <6>;
>> 236
>> 237 rpm_requests: rpm-requests {
>> 238 compatible = "qcom,rpm-msm8994";
>> 239 qcom,smd-channels = "rpm_requests";
>> 240
>> 241 rpmcc: rpmcc {
>> 242 compatible = "qcom,rpmcc-msm8994";
>> 243 #clock-cells = <1>;
>> 244 };
>> 245
>> 246 rpmpd: power-controller {
>> 247 compatible = "qcom,msm8994-rpmpd";
>> 248 #power-domain-cells = <1>;
>> 249 operating-points-v2 = <&rpmpd_opp_table>;
>> 250
>> 251 rpmpd_opp_table: opp-table {
>> 252 compatible = "operating-points-v2";
>> 253
>> 254 rpmpd_opp_ret: opp1 {
>> 255 opp-level = <1>;
>> 256 };
>> 257 rpmpd_opp_svs_krait: opp2 {
>> 258 opp-level = <2>;
>> 259 };
>> 260 rpmpd_opp_svs_soc: opp3 {
>> 261 opp-level = <3>;
>> 262 };
>> 263 rpmpd_opp_nom: opp4 {
>> 264 opp-level = <4>;
>> 265 };
>> 266 rpmpd_opp_turbo: opp5 {
>> 267 opp-level = <5>;
>> 268 };
>> 269 rpmpd_opp_super_turbo: opp6 {
>> 270 opp-level = <6>;
>> 271 };
>> 272 };
>> 273 };
>> 274 };
287 }; 275 };
288 }; 276 };
289 277
290 smem { 278 smem {
291 compatible = "qcom,smem"; 279 compatible = "qcom,smem";
292 memory-region = <&smem_mem>; 280 memory-region = <&smem_mem>;
293 qcom,rpm-msg-ram = <&rpm_msg_r 281 qcom,rpm-msg-ram = <&rpm_msg_ram>;
294 hwlocks = <&tcsr_mutex 3>; 282 hwlocks = <&tcsr_mutex 3>;
295 }; 283 };
296 284
297 smp2p-lpass { 285 smp2p-lpass {
298 compatible = "qcom,smp2p"; 286 compatible = "qcom,smp2p";
299 qcom,smem = <443>, <429>; 287 qcom,smem = <443>, <429>;
300 288
301 interrupts = <GIC_SPI 158 IRQ_ 289 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
302 290
303 mboxes = <&apcs 10>; !! 291 qcom,ipc = <&apcs 8 10>;
304 292
305 qcom,local-pid = <0>; 293 qcom,local-pid = <0>;
306 qcom,remote-pid = <2>; 294 qcom,remote-pid = <2>;
307 295
308 adsp_smp2p_out: master-kernel 296 adsp_smp2p_out: master-kernel {
309 qcom,entry-name = "mas 297 qcom,entry-name = "master-kernel";
310 #qcom,smem-state-cells 298 #qcom,smem-state-cells = <1>;
311 }; 299 };
312 300
313 adsp_smp2p_in: slave-kernel { 301 adsp_smp2p_in: slave-kernel {
314 qcom,entry-name = "sla 302 qcom,entry-name = "slave-kernel";
315 303
316 interrupt-controller; 304 interrupt-controller;
317 #interrupt-cells = <2> 305 #interrupt-cells = <2>;
318 }; 306 };
319 }; 307 };
320 308
321 smp2p-modem { 309 smp2p-modem {
322 compatible = "qcom,smp2p"; 310 compatible = "qcom,smp2p";
323 qcom,smem = <435>, <428>; 311 qcom,smem = <435>, <428>;
324 312
325 interrupt-parent = <&intc>; 313 interrupt-parent = <&intc>;
326 interrupts = <GIC_SPI 27 IRQ_T 314 interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>;
327 315
328 mboxes = <&apcs 14>; !! 316 qcom,ipc = <&apcs 8 14>;
329 317
330 qcom,local-pid = <0>; 318 qcom,local-pid = <0>;
331 qcom,remote-pid = <1>; 319 qcom,remote-pid = <1>;
332 320
333 modem_smp2p_out: master-kernel 321 modem_smp2p_out: master-kernel {
334 qcom,entry-name = "mas 322 qcom,entry-name = "master-kernel";
335 #qcom,smem-state-cells 323 #qcom,smem-state-cells = <1>;
336 }; 324 };
337 325
338 modem_smp2p_in: slave-kernel { 326 modem_smp2p_in: slave-kernel {
339 qcom,entry-name = "sla 327 qcom,entry-name = "slave-kernel";
340 328
341 interrupt-controller; 329 interrupt-controller;
342 #interrupt-cells = <2> 330 #interrupt-cells = <2>;
343 }; 331 };
344 }; 332 };
345 333
346 soc: soc@0 { !! 334 soc: soc {
>> 335
347 #address-cells = <1>; 336 #address-cells = <1>;
348 #size-cells = <1>; 337 #size-cells = <1>;
349 ranges = <0 0 0 0xffffffff>; 338 ranges = <0 0 0 0xffffffff>;
350 compatible = "simple-bus"; 339 compatible = "simple-bus";
351 340
352 intc: interrupt-controller@f90 341 intc: interrupt-controller@f9000000 {
353 compatible = "qcom,msm 342 compatible = "qcom,msm-qgic2";
354 interrupt-controller; 343 interrupt-controller;
355 #interrupt-cells = <3> 344 #interrupt-cells = <3>;
356 reg = <0xf9000000 0x10 345 reg = <0xf9000000 0x1000>,
357 <0xf9002000 0x10 346 <0xf9002000 0x1000>;
358 }; 347 };
359 348
360 apcs: mailbox@f900d000 { 349 apcs: mailbox@f900d000 {
361 compatible = "qcom,msm 350 compatible = "qcom,msm8994-apcs-kpss-global", "syscon";
362 reg = <0xf900d000 0x20 351 reg = <0xf900d000 0x2000>;
363 #mbox-cells = <1>; 352 #mbox-cells = <1>;
364 }; 353 };
365 354
366 watchdog@f9017000 { <<
367 compatible = "qcom,aps <<
368 reg = <0xf9017000 0x10 <<
369 interrupts = <GIC_SPI <<
370 <GIC_SPI <<
371 clocks = <&sleep_clk>; <<
372 timeout-sec = <10>; <<
373 }; <<
374 <<
375 timer@f9020000 { 355 timer@f9020000 {
376 #address-cells = <1>; 356 #address-cells = <1>;
377 #size-cells = <1>; 357 #size-cells = <1>;
378 ranges; 358 ranges;
379 compatible = "arm,armv 359 compatible = "arm,armv7-timer-mem";
380 reg = <0xf9020000 0x10 360 reg = <0xf9020000 0x1000>;
381 361
382 frame@f9021000 { 362 frame@f9021000 {
383 frame-number = 363 frame-number = <0>;
384 interrupts = < 364 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
385 < 365 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
386 reg = <0xf9021 366 reg = <0xf9021000 0x1000>,
387 <0xf9022 367 <0xf9022000 0x1000>;
388 }; 368 };
389 369
390 frame@f9023000 { 370 frame@f9023000 {
391 frame-number = 371 frame-number = <1>;
392 interrupts = < 372 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
393 reg = <0xf9023 373 reg = <0xf9023000 0x1000>;
394 status = "disa 374 status = "disabled";
395 }; 375 };
396 376
397 frame@f9024000 { 377 frame@f9024000 {
398 frame-number = 378 frame-number = <2>;
399 interrupts = < 379 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
400 reg = <0xf9024 380 reg = <0xf9024000 0x1000>;
401 status = "disa 381 status = "disabled";
402 }; 382 };
403 383
404 frame@f9025000 { 384 frame@f9025000 {
405 frame-number = 385 frame-number = <3>;
406 interrupts = < 386 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
407 reg = <0xf9025 387 reg = <0xf9025000 0x1000>;
408 status = "disa 388 status = "disabled";
409 }; 389 };
410 390
411 frame@f9026000 { 391 frame@f9026000 {
412 frame-number = 392 frame-number = <4>;
413 interrupts = < 393 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
414 reg = <0xf9026 394 reg = <0xf9026000 0x1000>;
415 status = "disa 395 status = "disabled";
416 }; 396 };
417 397
418 frame@f9027000 { 398 frame@f9027000 {
419 frame-number = 399 frame-number = <5>;
420 interrupts = < 400 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
421 reg = <0xf9027 401 reg = <0xf9027000 0x1000>;
422 status = "disa 402 status = "disabled";
423 }; 403 };
424 404
425 frame@f9028000 { 405 frame@f9028000 {
426 frame-number = 406 frame-number = <6>;
427 interrupts = < 407 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
428 reg = <0xf9028 408 reg = <0xf9028000 0x1000>;
429 status = "disa 409 status = "disabled";
430 }; 410 };
431 }; 411 };
432 412
433 usb3: usb@f92f8800 { 413 usb3: usb@f92f8800 {
434 compatible = "qcom,msm !! 414 compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
435 reg = <0xf92f8800 0x40 415 reg = <0xf92f8800 0x400>;
436 #address-cells = <1>; 416 #address-cells = <1>;
437 #size-cells = <1>; 417 #size-cells = <1>;
438 ranges; 418 ranges;
439 419
440 clocks = <&gcc GCC_USB 420 clocks = <&gcc GCC_USB30_MASTER_CLK>,
441 <&gcc GCC_SYS 421 <&gcc GCC_SYS_NOC_USB3_AXI_CLK>,
442 <&gcc GCC_USB 422 <&gcc GCC_USB30_SLEEP_CLK>,
443 <&gcc GCC_USB 423 <&gcc GCC_USB30_MOCK_UTMI_CLK>;
444 clock-names = "core", !! 424 clock-names = "core", "iface", "sleep", "mock_utmi", "ref", "xo";
445 "iface", <<
446 "sleep", <<
447 "mock_ut <<
448 425
449 assigned-clocks = <&gc 426 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
450 <&gc 427 <&gcc GCC_USB30_MASTER_CLK>;
451 assigned-clock-rates = 428 assigned-clock-rates = <19200000>, <120000000>;
452 429
453 power-domains = <&gcc 430 power-domains = <&gcc USB30_GDSC>;
454 qcom,select-utmi-as-pi 431 qcom,select-utmi-as-pipe-clk;
455 432
456 usb@f9200000 { !! 433 dwc3@f9200000 {
457 compatible = " 434 compatible = "snps,dwc3";
458 reg = <0xf9200 435 reg = <0xf9200000 0xcc00>;
459 interrupts = < !! 436 interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>;
460 snps,dis_u2_su 437 snps,dis_u2_susphy_quirk;
461 snps,dis_enbls 438 snps,dis_enblslpm_quirk;
462 maximum-speed 439 maximum-speed = "high-speed";
463 dr_mode = "per 440 dr_mode = "peripheral";
464 }; 441 };
465 }; 442 };
466 443
467 sdhc1: mmc@f9824900 { !! 444 sdhc1: sdhci@f9824900 {
468 compatible = "qcom,msm !! 445 compatible = "qcom,sdhci-msm-v4";
469 reg = <0xf9824900 0x1a 446 reg = <0xf9824900 0x1a0>, <0xf9824000 0x800>;
470 reg-names = "hc", "cor !! 447 reg-names = "hc_mem", "core_mem";
471 448
472 interrupts = <GIC_SPI 449 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
473 <GIC_SPI 450 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
474 interrupt-names = "hc_ 451 interrupt-names = "hc_irq", "pwr_irq";
475 452
476 clocks = <&gcc GCC_SDC !! 453 clocks = <&gcc GCC_SDCC1_APPS_CLK>,
477 <&gcc GCC_SDC !! 454 <&gcc GCC_SDCC1_AHB_CLK>,
478 <&xo_board>; 455 <&xo_board>;
479 clock-names = "iface", !! 456 clock-names = "core", "iface", "xo";
480 457
481 pinctrl-names = "defau 458 pinctrl-names = "default", "sleep";
482 pinctrl-0 = <&sdc1_clk 459 pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>;
483 pinctrl-1 = <&sdc1_clk 460 pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>;
484 461
485 bus-width = <8>; 462 bus-width = <8>;
486 non-removable; 463 non-removable;
487 status = "disabled"; 464 status = "disabled";
488 }; 465 };
489 466
490 sdhc2: mmc@f98a4900 { !! 467 sdhc2: sdhci@f98a4900 {
491 compatible = "qcom,msm !! 468 compatible = "qcom,sdhci-msm-v4";
492 reg = <0xf98a4900 0x11 469 reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
493 reg-names = "hc", "cor !! 470 reg-names = "hc_mem", "core_mem";
494 471
495 interrupts = <GIC_SPI 472 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
496 <GIC_SPI 221 I 473 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
497 interrupt-names = "hc_ 474 interrupt-names = "hc_irq", "pwr_irq";
498 475
499 clocks = <&gcc GCC_SDC !! 476 clocks = <&gcc GCC_SDCC2_APPS_CLK>,
500 <&gcc GCC_SDC !! 477 <&gcc GCC_SDCC2_AHB_CLK>,
501 <&xo_board>; !! 478 <&xo_board>;
502 clock-names = "iface", !! 479 clock-names = "core", "iface", "xo";
503 480
504 pinctrl-names = "defau 481 pinctrl-names = "default", "sleep";
505 pinctrl-0 = <&sdc2_clk 482 pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>;
506 pinctrl-1 = <&sdc2_clk 483 pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>;
507 484
508 cd-gpios = <&tlmm 100 !! 485 cd-gpios = <&tlmm 100 0>;
509 bus-width = <4>; 486 bus-width = <4>;
510 status = "disabled"; 487 status = "disabled";
511 }; 488 };
512 489
513 blsp1_dma: dma-controller@f990 490 blsp1_dma: dma-controller@f9904000 {
514 compatible = "qcom,bam 491 compatible = "qcom,bam-v1.7.0";
515 reg = <0xf9904000 0x19 492 reg = <0xf9904000 0x19000>;
516 interrupts = <GIC_SPI 493 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
517 clocks = <&gcc GCC_BLS 494 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
518 clock-names = "bam_clk 495 clock-names = "bam_clk";
519 #dma-cells = <1>; 496 #dma-cells = <1>;
520 qcom,ee = <0>; 497 qcom,ee = <0>;
521 qcom,controlled-remote 498 qcom,controlled-remotely;
522 num-channels = <24>; !! 499 num-channels = <18>;
523 qcom,num-ees = <4>; 500 qcom,num-ees = <4>;
524 }; 501 };
525 502
526 blsp1_uart2: serial@f991e000 { 503 blsp1_uart2: serial@f991e000 {
527 compatible = "qcom,msm 504 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
528 reg = <0xf991e000 0x10 505 reg = <0xf991e000 0x1000>;
529 interrupts = <GIC_SPI 506 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
530 clock-names = "core", 507 clock-names = "core", "iface";
531 clocks = <&gcc GCC_BLS 508 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
532 <&gcc GCC_BLS 509 <&gcc GCC_BLSP1_AHB_CLK>;
533 pinctrl-names = "defau 510 pinctrl-names = "default", "sleep";
534 pinctrl-0 = <&blsp1_ua 511 pinctrl-0 = <&blsp1_uart2_default>;
535 pinctrl-1 = <&blsp1_ua 512 pinctrl-1 = <&blsp1_uart2_sleep>;
536 status = "disabled"; 513 status = "disabled";
537 }; 514 };
538 515
539 blsp1_i2c1: i2c@f9923000 { 516 blsp1_i2c1: i2c@f9923000 {
540 compatible = "qcom,i2c 517 compatible = "qcom,i2c-qup-v2.2.1";
541 reg = <0xf9923000 0x50 518 reg = <0xf9923000 0x500>;
542 interrupts = <GIC_SPI 519 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
543 clocks = <&gcc GCC_BLS !! 520 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
544 <&gcc GCC_BLS !! 521 <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>;
545 clock-names = "core", !! 522 clock-names = "iface", "core";
546 clock-frequency = <400 523 clock-frequency = <400000>;
547 dmas = <&blsp1_dma 12> 524 dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
548 dma-names = "tx", "rx" 525 dma-names = "tx", "rx";
549 pinctrl-names = "defau 526 pinctrl-names = "default", "sleep";
550 pinctrl-0 = <&i2c1_def 527 pinctrl-0 = <&i2c1_default>;
551 pinctrl-1 = <&i2c1_sle 528 pinctrl-1 = <&i2c1_sleep>;
552 #address-cells = <1>; 529 #address-cells = <1>;
553 #size-cells = <0>; 530 #size-cells = <0>;
554 status = "disabled"; 531 status = "disabled";
555 }; 532 };
556 533
557 blsp1_spi1: spi@f9923000 { 534 blsp1_spi1: spi@f9923000 {
558 compatible = "qcom,spi 535 compatible = "qcom,spi-qup-v2.2.1";
559 reg = <0xf9923000 0x50 536 reg = <0xf9923000 0x500>;
560 interrupts = <GIC_SPI 537 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
561 clocks = <&gcc GCC_BLS 538 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
562 <&gcc GCC_BLS 539 <&gcc GCC_BLSP1_AHB_CLK>;
563 clock-names = "core", 540 clock-names = "core", "iface";
>> 541 spi-max-frequency = <19200000>;
564 dmas = <&blsp1_dma 12> 542 dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
565 dma-names = "tx", "rx" 543 dma-names = "tx", "rx";
566 pinctrl-names = "defau 544 pinctrl-names = "default", "sleep";
567 pinctrl-0 = <&blsp1_sp 545 pinctrl-0 = <&blsp1_spi1_default>;
568 pinctrl-1 = <&blsp1_sp 546 pinctrl-1 = <&blsp1_spi1_sleep>;
569 #address-cells = <1>; 547 #address-cells = <1>;
570 #size-cells = <0>; 548 #size-cells = <0>;
571 status = "disabled"; 549 status = "disabled";
572 }; 550 };
573 551
574 blsp1_i2c2: i2c@f9924000 { 552 blsp1_i2c2: i2c@f9924000 {
575 compatible = "qcom,i2c 553 compatible = "qcom,i2c-qup-v2.2.1";
576 reg = <0xf9924000 0x50 554 reg = <0xf9924000 0x500>;
577 interrupts = <GIC_SPI 555 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
578 clocks = <&gcc GCC_BLS !! 556 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
579 <&gcc GCC_BLS !! 557 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
580 clock-names = "core", !! 558 clock-names = "iface", "core";
581 clock-frequency = <400 559 clock-frequency = <400000>;
582 dmas = <&blsp1_dma 14> 560 dmas = <&blsp1_dma 14>, <&blsp1_dma 15>;
583 dma-names = "tx", "rx" 561 dma-names = "tx", "rx";
584 pinctrl-names = "defau 562 pinctrl-names = "default", "sleep";
585 pinctrl-0 = <&i2c2_def 563 pinctrl-0 = <&i2c2_default>;
586 pinctrl-1 = <&i2c2_sle 564 pinctrl-1 = <&i2c2_sleep>;
587 #address-cells = <1>; 565 #address-cells = <1>;
588 #size-cells = <0>; 566 #size-cells = <0>;
589 status = "disabled"; 567 status = "disabled";
590 }; 568 };
591 569
592 /* I2C3 doesn't exist */ 570 /* I2C3 doesn't exist */
593 571
594 blsp1_i2c4: i2c@f9926000 { 572 blsp1_i2c4: i2c@f9926000 {
595 compatible = "qcom,i2c 573 compatible = "qcom,i2c-qup-v2.2.1";
596 reg = <0xf9926000 0x50 574 reg = <0xf9926000 0x500>;
597 interrupts = <GIC_SPI 575 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
598 clocks = <&gcc GCC_BLS !! 576 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
599 <&gcc GCC_BLS !! 577 <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
600 clock-names = "core", !! 578 clock-names = "iface", "core";
601 clock-frequency = <400 579 clock-frequency = <400000>;
602 dmas = <&blsp1_dma 18> 580 dmas = <&blsp1_dma 18>, <&blsp1_dma 19>;
603 dma-names = "tx", "rx" 581 dma-names = "tx", "rx";
604 pinctrl-names = "defau 582 pinctrl-names = "default", "sleep";
605 pinctrl-0 = <&i2c4_def 583 pinctrl-0 = <&i2c4_default>;
606 pinctrl-1 = <&i2c4_sle 584 pinctrl-1 = <&i2c4_sleep>;
607 #address-cells = <1>; 585 #address-cells = <1>;
608 #size-cells = <0>; 586 #size-cells = <0>;
609 status = "disabled"; 587 status = "disabled";
610 }; 588 };
611 589
612 blsp1_i2c5: i2c@f9927000 { 590 blsp1_i2c5: i2c@f9927000 {
613 compatible = "qcom,i2c 591 compatible = "qcom,i2c-qup-v2.2.1";
614 reg = <0xf9927000 0x50 592 reg = <0xf9927000 0x500>;
615 interrupts = <GIC_SPI 593 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
616 clocks = <&gcc GCC_BLS !! 594 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
617 <&gcc GCC_BLS !! 595 <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>;
618 clock-names = "core", !! 596 clock-names = "iface", "core";
619 clock-frequency = <400 597 clock-frequency = <400000>;
620 dmas = <&blsp2_dma 20> 598 dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
621 dma-names = "tx", "rx" 599 dma-names = "tx", "rx";
622 pinctrl-names = "defau 600 pinctrl-names = "default", "sleep";
623 pinctrl-0 = <&i2c5_def 601 pinctrl-0 = <&i2c5_default>;
624 pinctrl-1 = <&i2c5_sle 602 pinctrl-1 = <&i2c5_sleep>;
625 #address-cells = <1>; 603 #address-cells = <1>;
626 #size-cells = <0>; 604 #size-cells = <0>;
627 status = "disabled"; 605 status = "disabled";
628 }; 606 };
629 607
630 blsp1_i2c6: i2c@f9928000 { 608 blsp1_i2c6: i2c@f9928000 {
631 compatible = "qcom,i2c 609 compatible = "qcom,i2c-qup-v2.2.1";
632 reg = <0xf9928000 0x50 610 reg = <0xf9928000 0x500>;
633 interrupts = <GIC_SPI 611 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
634 clocks = <&gcc GCC_BLS !! 612 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
635 <&gcc GCC_BLS !! 613 <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;
636 clock-names = "core", !! 614 clock-names = "iface", "core";
637 clock-frequency = <400 615 clock-frequency = <400000>;
638 dmas = <&blsp1_dma 22> 616 dmas = <&blsp1_dma 22>, <&blsp1_dma 23>;
639 dma-names = "tx", "rx" 617 dma-names = "tx", "rx";
640 pinctrl-names = "defau 618 pinctrl-names = "default", "sleep";
641 pinctrl-0 = <&i2c6_def 619 pinctrl-0 = <&i2c6_default>;
642 pinctrl-1 = <&i2c6_sle 620 pinctrl-1 = <&i2c6_sleep>;
643 #address-cells = <1>; 621 #address-cells = <1>;
644 #size-cells = <0>; 622 #size-cells = <0>;
645 status = "disabled"; 623 status = "disabled";
646 }; 624 };
647 625
648 blsp2_dma: dma-controller@f994 626 blsp2_dma: dma-controller@f9944000 {
649 compatible = "qcom,bam 627 compatible = "qcom,bam-v1.7.0";
650 reg = <0xf9944000 0x19 628 reg = <0xf9944000 0x19000>;
651 interrupts = <GIC_SPI 629 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
652 clocks = <&gcc GCC_BLS 630 clocks = <&gcc GCC_BLSP2_AHB_CLK>;
653 clock-names = "bam_clk 631 clock-names = "bam_clk";
654 #dma-cells = <1>; 632 #dma-cells = <1>;
655 qcom,ee = <0>; 633 qcom,ee = <0>;
656 qcom,controlled-remote 634 qcom,controlled-remotely;
657 num-channels = <24>; !! 635 num-channels = <18>;
658 qcom,num-ees = <4>; 636 qcom,num-ees = <4>;
659 }; 637 };
660 638
661 blsp2_uart2: serial@f995e000 { 639 blsp2_uart2: serial@f995e000 {
662 compatible = "qcom,msm 640 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
663 reg = <0xf995e000 0x10 641 reg = <0xf995e000 0x1000>;
664 interrupts = <GIC_SPI 642 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
665 clock-names = "core", 643 clock-names = "core", "iface";
666 clocks = <&gcc GCC_BLS 644 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
667 <&gcc 645 <&gcc GCC_BLSP2_AHB_CLK>;
668 dmas = <&blsp2_dma 2>, 646 dmas = <&blsp2_dma 2>, <&blsp2_dma 3>;
669 dma-names = "tx", "rx" 647 dma-names = "tx", "rx";
670 pinctrl-names = "defau 648 pinctrl-names = "default", "sleep";
671 pinctrl-0 = <&blsp2_ua 649 pinctrl-0 = <&blsp2_uart2_default>;
672 pinctrl-1 = <&blsp2_ua 650 pinctrl-1 = <&blsp2_uart2_sleep>;
673 status = "disabled"; 651 status = "disabled";
674 }; 652 };
675 653
676 blsp2_i2c1: i2c@f9963000 { 654 blsp2_i2c1: i2c@f9963000 {
677 compatible = "qcom,i2c 655 compatible = "qcom,i2c-qup-v2.2.1";
678 reg = <0xf9963000 0x50 656 reg = <0xf9963000 0x500>;
679 interrupts = <GIC_SPI 657 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
680 clocks = <&gcc GCC_BLS !! 658 clocks = <&gcc GCC_BLSP2_AHB_CLK>,
681 <&gcc GCC_BLS !! 659 <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>;
682 clock-names = "core", !! 660 clock-names = "iface", "core";
683 clock-frequency = <400 661 clock-frequency = <400000>;
684 dmas = <&blsp2_dma 12> 662 dmas = <&blsp2_dma 12>, <&blsp2_dma 13>;
685 dma-names = "tx", "rx" 663 dma-names = "tx", "rx";
686 pinctrl-names = "defau 664 pinctrl-names = "default", "sleep";
687 pinctrl-0 = <&i2c7_def 665 pinctrl-0 = <&i2c7_default>;
688 pinctrl-1 = <&i2c7_sle 666 pinctrl-1 = <&i2c7_sleep>;
689 #address-cells = <1>; 667 #address-cells = <1>;
690 #size-cells = <0>; 668 #size-cells = <0>;
691 status = "disabled"; 669 status = "disabled";
692 }; 670 };
693 671
694 blsp2_spi4: spi@f9966000 { 672 blsp2_spi4: spi@f9966000 {
695 compatible = "qcom,spi 673 compatible = "qcom,spi-qup-v2.2.1";
696 reg = <0xf9966000 0x50 674 reg = <0xf9966000 0x500>;
697 interrupts = <GIC_SPI 675 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
698 clocks = <&gcc GCC_BLS 676 clocks = <&gcc GCC_BLSP2_QUP4_SPI_APPS_CLK>,
699 <&gcc GCC_BLS 677 <&gcc GCC_BLSP2_AHB_CLK>;
700 clock-names = "core", 678 clock-names = "core", "iface";
>> 679 spi-max-frequency = <19200000>;
701 dmas = <&blsp2_dma 18> 680 dmas = <&blsp2_dma 18>, <&blsp2_dma 19>;
702 dma-names = "tx", "rx" 681 dma-names = "tx", "rx";
703 pinctrl-names = "defau 682 pinctrl-names = "default", "sleep";
704 pinctrl-0 = <&blsp2_sp 683 pinctrl-0 = <&blsp2_spi10_default>;
705 pinctrl-1 = <&blsp2_sp 684 pinctrl-1 = <&blsp2_spi10_sleep>;
706 #address-cells = <1>; 685 #address-cells = <1>;
707 #size-cells = <0>; 686 #size-cells = <0>;
708 status = "disabled"; 687 status = "disabled";
709 }; 688 };
710 689
711 blsp2_i2c5: i2c@f9967000 { 690 blsp2_i2c5: i2c@f9967000 {
712 compatible = "qcom,i2c 691 compatible = "qcom,i2c-qup-v2.2.1";
713 reg = <0xf9967000 0x50 692 reg = <0xf9967000 0x500>;
714 interrupts = <GIC_SPI 693 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
715 clocks = <&gcc GCC_BLS !! 694 clocks = <&gcc GCC_BLSP2_AHB_CLK>,
716 <&gcc GCC_BLS !! 695 <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>;
717 clock-names = "core", !! 696 clock-names = "iface", "core";
718 clock-frequency = <355 697 clock-frequency = <355000>;
719 dmas = <&blsp2_dma 20> 698 dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
720 dma-names = "tx", "rx" 699 dma-names = "tx", "rx";
721 pinctrl-names = "defau 700 pinctrl-names = "default", "sleep";
722 pinctrl-0 = <&i2c11_de 701 pinctrl-0 = <&i2c11_default>;
723 pinctrl-1 = <&i2c11_sl 702 pinctrl-1 = <&i2c11_sleep>;
724 #address-cells = <1>; 703 #address-cells = <1>;
725 #size-cells = <0>; 704 #size-cells = <0>;
726 status = "disabled"; 705 status = "disabled";
727 }; 706 };
728 707
729 gcc: clock-controller@fc400000 708 gcc: clock-controller@fc400000 {
730 compatible = "qcom,gcc 709 compatible = "qcom,gcc-msm8994";
731 #clock-cells = <1>; 710 #clock-cells = <1>;
732 #reset-cells = <1>; 711 #reset-cells = <1>;
733 #power-domain-cells = 712 #power-domain-cells = <1>;
734 reg = <0xfc400000 0x20 713 reg = <0xfc400000 0x2000>;
735 <<
736 clock-names = "xo", "s <<
737 clocks = <&xo_board>, <<
738 }; 714 };
739 715
740 rpm_msg_ram: sram@fc428000 { !! 716 rpm_msg_ram: memory@fc428000 {
741 compatible = "qcom,rpm 717 compatible = "qcom,rpm-msg-ram";
742 reg = <0xfc428000 0x40 718 reg = <0xfc428000 0x4000>;
743 }; 719 };
744 720
745 restart@fc4ab000 { 721 restart@fc4ab000 {
746 compatible = "qcom,psh 722 compatible = "qcom,pshold";
747 reg = <0xfc4ab000 0x4> 723 reg = <0xfc4ab000 0x4>;
748 }; 724 };
749 725
750 spmi_bus: spmi@fc4cf000 { !! 726 spmi_bus: spmi@fc4c0000 {
751 compatible = "qcom,spm 727 compatible = "qcom,spmi-pmic-arb";
752 reg = <0xfc4cf000 0x10 728 reg = <0xfc4cf000 0x1000>,
753 <0xfc4cb000 0x10 729 <0xfc4cb000 0x1000>,
754 <0xfc4ca000 0x10 730 <0xfc4ca000 0x1000>;
755 reg-names = "core", "i 731 reg-names = "core", "intr", "cnfg";
756 interrupt-names = "per 732 interrupt-names = "periph_irq";
757 interrupts = <GIC_SPI 733 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
758 qcom,ee = <0>; 734 qcom,ee = <0>;
759 qcom,channel = <0>; 735 qcom,channel = <0>;
760 #address-cells = <2>; 736 #address-cells = <2>;
761 #size-cells = <0>; 737 #size-cells = <0>;
762 interrupt-controller; 738 interrupt-controller;
763 #interrupt-cells = <4> 739 #interrupt-cells = <4>;
764 }; 740 };
765 741
766 tcsr_mutex: hwlock@fd484000 { !! 742 tcsr_mutex_regs: syscon@fd484000 {
767 compatible = "qcom,msm !! 743 compatible = "syscon";
768 reg = <0xfd484000 0x10 !! 744 reg = <0xfd484000 0x2000>;
769 #hwlock-cells = <1>; <<
770 }; 745 };
771 746
772 tlmm: pinctrl@fd510000 { 747 tlmm: pinctrl@fd510000 {
773 compatible = "qcom,msm 748 compatible = "qcom,msm8994-pinctrl";
774 reg = <0xfd510000 0x40 749 reg = <0xfd510000 0x4000>;
775 interrupts = <GIC_SPI 750 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
776 gpio-controller; 751 gpio-controller;
777 gpio-ranges = <&tlmm 0 752 gpio-ranges = <&tlmm 0 0 146>;
778 #gpio-cells = <2>; 753 #gpio-cells = <2>;
779 interrupt-controller; 754 interrupt-controller;
780 #interrupt-cells = <2> 755 #interrupt-cells = <2>;
781 756
782 blsp1_uart2_default: b !! 757 blsp1_uart2_default: blsp1-uart2-default {
783 pins = "gpio4" <<
784 function = "bl 758 function = "blsp_uart2";
>> 759 pins = "gpio4", "gpio5";
785 drive-strength 760 drive-strength = <16>;
786 bias-disable; 761 bias-disable;
787 }; 762 };
788 763
789 blsp1_uart2_sleep: bls !! 764 blsp1_uart2_sleep: blsp1-uart2-sleep {
790 pins = "gpio4" <<
791 function = "gp 765 function = "gpio";
>> 766 pins = "gpio4", "gpio5";
792 drive-strength 767 drive-strength = <2>;
793 bias-pull-down 768 bias-pull-down;
794 }; 769 };
795 770
796 blsp2_uart2_default: b !! 771 blsp2_uart2_default: blsp2-uart2-default {
797 pins = "gpio45 <<
798 function = "bl 772 function = "blsp_uart8";
>> 773 pins = "gpio45", "gpio46",
>> 774 "gpio47", "gpio48";
799 drive-strength 775 drive-strength = <16>;
800 bias-disable; 776 bias-disable;
801 }; 777 };
802 778
803 blsp2_uart2_sleep: bls !! 779 blsp2_uart2_sleep: blsp2-uart2-sleep {
804 pins = "gpio45 <<
805 function = "gp 780 function = "gpio";
>> 781 pins = "gpio45", "gpio46",
>> 782 "gpio47", "gpio48";
806 drive-strength 783 drive-strength = <2>;
807 bias-disable; 784 bias-disable;
808 }; 785 };
809 786
810 i2c1_default: i2c1-def !! 787 i2c1_default: i2c1-default {
811 pins = "gpio2" <<
812 function = "bl 788 function = "blsp_i2c1";
>> 789 pins = "gpio2", "gpio3";
813 drive-strength 790 drive-strength = <2>;
814 bias-disable; 791 bias-disable;
815 }; 792 };
816 793
817 i2c1_sleep: i2c1-sleep !! 794 i2c1_sleep: i2c1-sleep {
818 pins = "gpio2" <<
819 function = "gp 795 function = "gpio";
>> 796 pins = "gpio2", "gpio3";
820 drive-strength 797 drive-strength = <2>;
821 bias-disable; 798 bias-disable;
822 }; 799 };
823 800
824 i2c2_default: i2c2-def !! 801 i2c2_default: i2c2-default {
825 pins = "gpio6" <<
826 function = "bl 802 function = "blsp_i2c2";
>> 803 pins = "gpio6", "gpio7";
827 drive-strength 804 drive-strength = <2>;
828 bias-disable; 805 bias-disable;
829 }; 806 };
830 807
831 i2c2_sleep: i2c2-sleep !! 808 i2c2_sleep: i2c2-sleep {
832 pins = "gpio6" <<
833 function = "gp 809 function = "gpio";
>> 810 pins = "gpio6", "gpio7";
834 drive-strength 811 drive-strength = <2>;
835 bias-disable; 812 bias-disable;
836 }; 813 };
837 814
838 i2c4_default: i2c4-def !! 815 i2c4_default: i2c4-default {
839 pins = "gpio19 <<
840 function = "bl 816 function = "blsp_i2c4";
>> 817 pins = "gpio19", "gpio20";
841 drive-strength 818 drive-strength = <2>;
842 bias-disable; 819 bias-disable;
843 }; 820 };
844 821
845 i2c4_sleep: i2c4-sleep !! 822 i2c4_sleep: i2c4-sleep {
846 pins = "gpio19 <<
847 function = "gp 823 function = "gpio";
>> 824 pins = "gpio19", "gpio20";
848 drive-strength 825 drive-strength = <2>;
849 bias-pull-down 826 bias-pull-down;
>> 827 input-enable;
850 }; 828 };
851 829
852 i2c5_default: i2c5-def !! 830 i2c5_default: i2c5-default {
853 pins = "gpio23 <<
854 function = "bl 831 function = "blsp_i2c5";
>> 832 pins = "gpio23", "gpio24";
855 drive-strength 833 drive-strength = <2>;
856 bias-disable; 834 bias-disable;
857 }; 835 };
858 836
859 i2c5_sleep: i2c5-sleep !! 837 i2c5_sleep: i2c5-sleep {
860 pins = "gpio23 <<
861 function = "gp 838 function = "gpio";
>> 839 pins = "gpio23", "gpio24";
862 drive-strength 840 drive-strength = <2>;
863 bias-disable; 841 bias-disable;
864 }; 842 };
865 843
866 i2c6_default: i2c6-def !! 844 i2c6_default: i2c6-default {
867 pins = "gpio28 <<
868 function = "bl 845 function = "blsp_i2c6";
>> 846 pins = "gpio28", "gpio27";
869 drive-strength 847 drive-strength = <2>;
870 bias-disable; 848 bias-disable;
871 }; 849 };
872 850
873 i2c6_sleep: i2c6-sleep !! 851 i2c6_sleep: i2c6-sleep {
874 pins = "gpio28 <<
875 function = "gp 852 function = "gpio";
>> 853 pins = "gpio28", "gpio27";
876 drive-strength 854 drive-strength = <2>;
877 bias-disable; 855 bias-disable;
878 }; 856 };
879 857
880 i2c7_default: i2c7-def !! 858 i2c7_default: i2c7-default {
881 pins = "gpio44 <<
882 function = "bl 859 function = "blsp_i2c7";
>> 860 pins = "gpio44", "gpio43";
883 drive-strength 861 drive-strength = <2>;
884 bias-disable; 862 bias-disable;
885 }; 863 };
886 864
887 i2c7_sleep: i2c7-sleep !! 865 i2c7_sleep: i2c7-sleep {
888 pins = "gpio44 <<
889 function = "gp 866 function = "gpio";
>> 867 pins = "gpio44", "gpio43";
890 drive-strength 868 drive-strength = <2>;
891 bias-disable; 869 bias-disable;
892 }; 870 };
893 871
894 blsp2_spi10_default: b !! 872 blsp2_spi10_default: blsp2-spi10-default {
895 default-pins { !! 873 default {
896 pins = <<
897 functi 874 function = "blsp_spi10";
>> 875 pins = "gpio53", "gpio54", "gpio55";
898 drive- 876 drive-strength = <10>;
899 bias-p 877 bias-pull-down;
900 }; 878 };
901 !! 879 cs {
902 cs-pins { <<
903 pins = <<
904 functi 880 function = "gpio";
>> 881 pins = "gpio55";
905 drive- 882 drive-strength = <2>;
906 bias-d 883 bias-disable;
907 }; 884 };
908 }; 885 };
909 886
910 blsp2_spi10_sleep: bls !! 887 blsp2_spi10_sleep: blsp2-spi10-sleep {
911 pins = "gpio53 888 pins = "gpio53", "gpio54", "gpio55";
912 function = "gp <<
913 drive-strength 889 drive-strength = <2>;
914 bias-disable; 890 bias-disable;
915 }; 891 };
916 892
917 i2c11_default: i2c11-d !! 893 i2c11_default: i2c11-default {
918 pins = "gpio83 <<
919 function = "bl 894 function = "blsp_i2c11";
>> 895 pins = "gpio83", "gpio84";
920 drive-strength 896 drive-strength = <2>;
921 bias-disable; 897 bias-disable;
922 }; 898 };
923 899
924 i2c11_sleep: i2c11-sle !! 900 i2c11_sleep: i2c11-sleep {
925 pins = "gpio83 <<
926 function = "gp 901 function = "gpio";
>> 902 pins = "gpio83", "gpio84";
927 drive-strength 903 drive-strength = <2>;
928 bias-disable; 904 bias-disable;
929 }; 905 };
930 906
931 blsp1_spi1_default: bl !! 907 blsp1_spi1_default: blsp1-spi1-default {
932 default-pins { !! 908 default {
933 pins = <<
934 functi 909 function = "blsp_spi1";
>> 910 pins = "gpio0", "gpio1", "gpio3";
935 drive- 911 drive-strength = <10>;
936 bias-p 912 bias-pull-down;
937 }; 913 };
938 !! 914 cs {
939 cs-pins { <<
940 pins = <<
941 functi 915 function = "gpio";
>> 916 pins = "gpio8";
942 drive- 917 drive-strength = <2>;
943 bias-d 918 bias-disable;
944 }; 919 };
945 }; 920 };
946 921
947 blsp1_spi1_sleep: blsp !! 922 blsp1_spi1_sleep: blsp1-spi1-sleep {
948 pins = "gpio0" 923 pins = "gpio0", "gpio1", "gpio3";
949 function = "gp <<
950 drive-strength 924 drive-strength = <2>;
951 bias-disable; 925 bias-disable;
952 }; 926 };
953 927
954 sdc1_clk_on: clk-on-st !! 928 sdc1_clk_on: clk-on {
955 pins = "sdc1_c 929 pins = "sdc1_clk";
956 bias-disable; 930 bias-disable;
957 drive-strength 931 drive-strength = <16>;
958 }; 932 };
959 933
960 sdc1_clk_off: clk-off- !! 934 sdc1_clk_off: clk-off {
961 pins = "sdc1_c 935 pins = "sdc1_clk";
962 bias-disable; 936 bias-disable;
963 drive-strength 937 drive-strength = <2>;
964 }; 938 };
965 939
966 sdc1_cmd_on: cmd-on-st !! 940 sdc1_cmd_on: cmd-on {
967 pins = "sdc1_c 941 pins = "sdc1_cmd";
968 bias-pull-up; 942 bias-pull-up;
969 drive-strength 943 drive-strength = <8>;
970 }; 944 };
971 945
972 sdc1_cmd_off: cmd-off- !! 946 sdc1_cmd_off: cmd-off {
973 pins = "sdc1_c 947 pins = "sdc1_cmd";
974 bias-pull-up; 948 bias-pull-up;
975 drive-strength 949 drive-strength = <2>;
976 }; 950 };
977 951
978 sdc1_data_on: data-on- !! 952 sdc1_data_on: data-on {
979 pins = "sdc1_d 953 pins = "sdc1_data";
980 bias-pull-up; 954 bias-pull-up;
981 drive-strength 955 drive-strength = <8>;
982 }; 956 };
983 957
984 sdc1_data_off: data-of !! 958 sdc1_data_off: data-off {
985 pins = "sdc1_d 959 pins = "sdc1_data";
986 bias-pull-up; 960 bias-pull-up;
987 drive-strength 961 drive-strength = <2>;
988 }; 962 };
989 963
990 sdc1_rclk_on: rclk-on- !! 964 sdc1_rclk_on: rclk-on {
991 pins = "sdc1_r 965 pins = "sdc1_rclk";
992 bias-pull-down 966 bias-pull-down;
993 }; 967 };
994 968
995 sdc1_rclk_off: rclk-of !! 969 sdc1_rclk_off: rclk-off {
996 pins = "sdc1_r 970 pins = "sdc1_rclk";
997 bias-pull-down 971 bias-pull-down;
998 }; 972 };
999 973
1000 sdc2_clk_on: sdc2-clk !! 974 sdc2_clk_on: sdc2-clk-on {
1001 pins = "sdc2_ 975 pins = "sdc2_clk";
1002 bias-disable; 976 bias-disable;
1003 drive-strengt 977 drive-strength = <10>;
1004 }; 978 };
1005 979
1006 sdc2_clk_off: sdc2-cl !! 980 sdc2_clk_off: sdc2-clk-off {
1007 pins = "sdc2_ 981 pins = "sdc2_clk";
1008 bias-disable; 982 bias-disable;
1009 drive-strengt 983 drive-strength = <2>;
1010 }; 984 };
1011 985
1012 sdc2_cmd_on: sdc2-cmd !! 986 sdc2_cmd_on: sdc2-cmd-on {
1013 pins = "sdc2_ 987 pins = "sdc2_cmd";
1014 bias-pull-up; 988 bias-pull-up;
1015 drive-strengt 989 drive-strength = <10>;
1016 }; 990 };
1017 991
1018 sdc2_cmd_off: sdc2-cm !! 992 sdc2_cmd_off: sdc2-cmd-off {
1019 pins = "sdc2_ 993 pins = "sdc2_cmd";
1020 bias-pull-up; 994 bias-pull-up;
1021 drive-strengt 995 drive-strength = <2>;
1022 }; 996 };
1023 997
1024 sdc2_data_on: sdc2-da !! 998 sdc2_data_on: sdc2-data-on {
1025 pins = "sdc2_ 999 pins = "sdc2_data";
1026 bias-pull-up; 1000 bias-pull-up;
1027 drive-strengt 1001 drive-strength = <10>;
1028 }; 1002 };
1029 1003
1030 sdc2_data_off: sdc2-d !! 1004 sdc2_data_off: sdc2-data-off {
1031 pins = "sdc2_ 1005 pins = "sdc2_data";
1032 bias-pull-up; 1006 bias-pull-up;
1033 drive-strengt 1007 drive-strength = <2>;
1034 }; 1008 };
1035 }; 1009 };
1036 <<
1037 mmcc: clock-controller@fd8c00 <<
1038 compatible = "qcom,mm <<
1039 reg = <0xfd8c0000 0x5 <<
1040 #clock-cells = <1>; <<
1041 #reset-cells = <1>; <<
1042 #power-domain-cells = <<
1043 <<
1044 clock-names = "xo", <<
1045 "gpll0" <<
1046 "mmssno <<
1047 "oxili_ <<
1048 "dsi0pl <<
1049 "dsi0pl <<
1050 "dsi1pl <<
1051 "dsi1pl <<
1052 "hdmipl <<
1053 clocks = <&xo_board>, <<
1054 <&gcc GPLL0_ <<
1055 <&rpmcc RPM_ <<
1056 <&rpmcc RPM_ <<
1057 <0>, <<
1058 <0>, <<
1059 <0>, <<
1060 <0>, <<
1061 <0>; <<
1062 <<
1063 assigned-clocks = <&m <<
1064 <&m <<
1065 <&m <<
1066 <&m <<
1067 <&m <<
1068 assigned-clock-rates <<
1069 <<
1070 <<
1071 <<
1072 <<
1073 }; <<
1074 <<
1075 ocmem: sram@fdd00000 { <<
1076 compatible = "qcom,ms <<
1077 reg = <0xfdd00000 0x2 <<
1078 <0xfec00000 0x2 <<
1079 reg-names = "ctrl", " <<
1080 ranges = <0 0xfec0000 <<
1081 clocks = <&rpmcc RPM_ <<
1082 <&mmcc OCMEM <<
1083 clock-names = "core", <<
1084 <<
1085 #address-cells = <1>; <<
1086 #size-cells = <1>; <<
1087 <<
1088 gmu_sram: gmu-sram@0 <<
1089 reg = <0x0 0x <<
1090 }; <<
1091 }; <<
1092 }; 1010 };
1093 1011
1094 timer: timer { 1012 timer: timer {
1095 compatible = "arm,armv8-timer 1013 compatible = "arm,armv8-timer";
1096 interrupts = <GIC_PPI 2 (GIC_ !! 1014 interrupts = <GIC_PPI 2 0xff08>,
1097 <GIC_PPI 3 (GIC_ !! 1015 <GIC_PPI 3 0xff08>,
1098 <GIC_PPI 4 (GIC_ !! 1016 <GIC_PPI 4 0xff08>,
1099 <GIC_PPI 1 (GIC_ !! 1017 <GIC_PPI 1 0xff08>;
1100 }; 1018 };
1101 1019
1102 vph_pwr: vph-pwr-regulator { 1020 vph_pwr: vph-pwr-regulator {
1103 compatible = "regulator-fixed 1021 compatible = "regulator-fixed";
1104 regulator-name = "vph_pwr"; 1022 regulator-name = "vph_pwr";
1105 1023
1106 regulator-min-microvolt = <36 1024 regulator-min-microvolt = <3600000>;
1107 regulator-max-microvolt = <36 1025 regulator-max-microvolt = <3600000>;
1108 1026
1109 regulator-always-on; 1027 regulator-always-on;
1110 }; 1028 };
1111 }; 1029 };
1112 1030
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