1 // SPDX-License-Identifier: GPL-2.0-only 1 // SPDX-License-Identifier: GPL-2.0-only
2 /* !! 2 /* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
3 * Copyright (c) 2013-2016, The Linux Foundati <<
4 */ 3 */
5 4
6 #include <dt-bindings/interrupt-controller/arm 5 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,gcc-msm8994.h 6 #include <dt-bindings/clock/qcom,gcc-msm8994.h>
8 #include <dt-bindings/clock/qcom,mmcc-msm8994. <<
9 #include <dt-bindings/clock/qcom,rpmcc.h> <<
10 #include <dt-bindings/gpio/gpio.h> <<
11 #include <dt-bindings/power/qcom-rpmpd.h> 7 #include <dt-bindings/power/qcom-rpmpd.h>
12 8
13 / { 9 / {
14 interrupt-parent = <&intc>; 10 interrupt-parent = <&intc>;
15 11
16 #address-cells = <2>; 12 #address-cells = <2>;
17 #size-cells = <2>; 13 #size-cells = <2>;
18 14
19 aliases { <<
20 mmc1 = &sdhc1; <<
21 mmc2 = &sdhc2; <<
22 }; <<
23 <<
24 chosen { }; 15 chosen { };
25 16
26 clocks { 17 clocks {
27 xo_board: xo-board { 18 xo_board: xo-board {
28 compatible = "fixed-cl 19 compatible = "fixed-clock";
29 #clock-cells = <0>; 20 #clock-cells = <0>;
30 clock-frequency = <192 21 clock-frequency = <19200000>;
31 clock-output-names = " 22 clock-output-names = "xo_board";
32 }; 23 };
33 24
34 sleep_clk: sleep-clk { 25 sleep_clk: sleep-clk {
35 compatible = "fixed-cl 26 compatible = "fixed-clock";
36 #clock-cells = <0>; 27 #clock-cells = <0>;
37 clock-frequency = <327 28 clock-frequency = <32768>;
38 clock-output-names = " 29 clock-output-names = "sleep_clk";
39 }; 30 };
40 }; 31 };
41 32
42 cpus { 33 cpus {
43 #address-cells = <2>; 34 #address-cells = <2>;
44 #size-cells = <0>; 35 #size-cells = <0>;
45 36
46 CPU0: cpu@0 { 37 CPU0: cpu@0 {
47 device_type = "cpu"; 38 device_type = "cpu";
48 compatible = "arm,cort 39 compatible = "arm,cortex-a53";
49 reg = <0x0 0x0>; 40 reg = <0x0 0x0>;
50 enable-method = "psci" 41 enable-method = "psci";
51 next-level-cache = <&L 42 next-level-cache = <&L2_0>;
52 L2_0: l2-cache { 43 L2_0: l2-cache {
53 compatible = " 44 compatible = "cache";
54 cache-level = 45 cache-level = <2>;
55 cache-unified; <<
56 }; 46 };
57 }; 47 };
58 48
59 CPU1: cpu@1 { 49 CPU1: cpu@1 {
60 device_type = "cpu"; 50 device_type = "cpu";
61 compatible = "arm,cort 51 compatible = "arm,cortex-a53";
62 reg = <0x0 0x1>; 52 reg = <0x0 0x1>;
63 enable-method = "psci" 53 enable-method = "psci";
64 next-level-cache = <&L 54 next-level-cache = <&L2_0>;
65 }; 55 };
66 56
67 CPU2: cpu@2 { 57 CPU2: cpu@2 {
68 device_type = "cpu"; 58 device_type = "cpu";
69 compatible = "arm,cort 59 compatible = "arm,cortex-a53";
70 reg = <0x0 0x2>; 60 reg = <0x0 0x2>;
71 enable-method = "psci" 61 enable-method = "psci";
72 next-level-cache = <&L 62 next-level-cache = <&L2_0>;
73 }; 63 };
74 64
75 CPU3: cpu@3 { 65 CPU3: cpu@3 {
76 device_type = "cpu"; 66 device_type = "cpu";
77 compatible = "arm,cort 67 compatible = "arm,cortex-a53";
78 reg = <0x0 0x3>; 68 reg = <0x0 0x3>;
79 enable-method = "psci" 69 enable-method = "psci";
80 next-level-cache = <&L 70 next-level-cache = <&L2_0>;
81 }; 71 };
82 72
83 CPU4: cpu@100 { 73 CPU4: cpu@100 {
84 device_type = "cpu"; 74 device_type = "cpu";
85 compatible = "arm,cort 75 compatible = "arm,cortex-a57";
86 reg = <0x0 0x100>; 76 reg = <0x0 0x100>;
87 enable-method = "psci" 77 enable-method = "psci";
88 next-level-cache = <&L 78 next-level-cache = <&L2_1>;
89 L2_1: l2-cache { 79 L2_1: l2-cache {
90 compatible = " 80 compatible = "cache";
91 cache-level = 81 cache-level = <2>;
92 cache-unified; <<
93 }; 82 };
94 }; 83 };
95 84
96 CPU5: cpu@101 { 85 CPU5: cpu@101 {
97 device_type = "cpu"; 86 device_type = "cpu";
98 compatible = "arm,cort 87 compatible = "arm,cortex-a57";
99 reg = <0x0 0x101>; 88 reg = <0x0 0x101>;
100 enable-method = "psci" 89 enable-method = "psci";
101 next-level-cache = <&L 90 next-level-cache = <&L2_1>;
102 }; 91 };
103 92
104 CPU6: cpu@102 { 93 CPU6: cpu@102 {
105 device_type = "cpu"; 94 device_type = "cpu";
106 compatible = "arm,cort 95 compatible = "arm,cortex-a57";
107 reg = <0x0 0x102>; 96 reg = <0x0 0x102>;
108 enable-method = "psci" 97 enable-method = "psci";
109 next-level-cache = <&L 98 next-level-cache = <&L2_1>;
110 }; 99 };
111 100
112 CPU7: cpu@103 { 101 CPU7: cpu@103 {
113 device_type = "cpu"; 102 device_type = "cpu";
114 compatible = "arm,cort 103 compatible = "arm,cortex-a57";
115 reg = <0x0 0x103>; 104 reg = <0x0 0x103>;
116 enable-method = "psci" 105 enable-method = "psci";
117 next-level-cache = <&L 106 next-level-cache = <&L2_1>;
118 }; 107 };
119 108
120 cpu-map { 109 cpu-map {
121 cluster0 { 110 cluster0 {
122 core0 { 111 core0 {
123 cpu = 112 cpu = <&CPU0>;
124 }; 113 };
125 114
126 core1 { 115 core1 {
127 cpu = 116 cpu = <&CPU1>;
128 }; 117 };
129 118
130 core2 { 119 core2 {
131 cpu = 120 cpu = <&CPU2>;
132 }; 121 };
133 122
134 core3 { 123 core3 {
135 cpu = 124 cpu = <&CPU3>;
136 }; 125 };
137 }; 126 };
138 127
139 cluster1 { 128 cluster1 {
140 core0 { 129 core0 {
141 cpu = 130 cpu = <&CPU4>;
142 }; 131 };
143 132
144 core1 { 133 core1 {
145 cpu = 134 cpu = <&CPU5>;
146 }; 135 };
147 136
148 cpu6_map: core 137 cpu6_map: core2 {
149 cpu = 138 cpu = <&CPU6>;
150 }; 139 };
151 140
152 cpu7_map: core 141 cpu7_map: core3 {
153 cpu = 142 cpu = <&CPU7>;
154 }; 143 };
155 }; 144 };
156 }; 145 };
157 }; 146 };
158 147
159 firmware { 148 firmware {
160 scm { 149 scm {
161 compatible = "qcom,scm 150 compatible = "qcom,scm-msm8994", "qcom,scm";
162 }; 151 };
163 }; 152 };
164 153
165 memory@80000000 { 154 memory@80000000 {
166 device_type = "memory"; 155 device_type = "memory";
167 /* We expect the bootloader to 156 /* We expect the bootloader to fill in the reg */
168 reg = <0 0x80000000 0 0>; 157 reg = <0 0x80000000 0 0>;
169 }; 158 };
170 159
>> 160 tcsr_mutex: hwlock {
>> 161 compatible = "qcom,tcsr-mutex";
>> 162 syscon = <&tcsr_mutex_regs 0 0x80>;
>> 163 #hwlock-cells = <1>;
>> 164 };
>> 165
171 pmu { 166 pmu {
172 compatible = "arm,cortex-a53-p 167 compatible = "arm,cortex-a53-pmu";
173 interrupts = <GIC_PPI 7 (GIC_C 168 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4)| IRQ_TYPE_LEVEL_HIGH)>;
174 }; 169 };
175 170
176 psci { 171 psci {
177 compatible = "arm,psci-0.2"; 172 compatible = "arm,psci-0.2";
178 method = "hvc"; 173 method = "hvc";
179 }; 174 };
180 175
181 rpm: remoteproc { <<
182 compatible = "qcom,msm8994-rpm <<
183 <<
184 smd-edge { <<
185 interrupts = <GIC_SPI <<
186 mboxes = <&apcs 0>; <<
187 qcom,smd-edge = <15>; <<
188 qcom,remote-pid = <6>; <<
189 <<
190 rpm_requests: rpm-requ <<
191 compatible = " <<
192 qcom,smd-chann <<
193 <<
194 rpmcc: clock-c <<
195 compat <<
196 #clock <<
197 }; <<
198 <<
199 rpmpd: power-c <<
200 compat <<
201 #power <<
202 operat <<
203 <<
204 rpmpd_ <<
205 <<
206 <<
207 <<
208 <<
209 <<
210 <<
211 <<
212 <<
213 <<
214 <<
215 <<
216 <<
217 <<
218 <<
219 <<
220 <<
221 <<
222 <<
223 <<
224 <<
225 }; <<
226 }; <<
227 }; <<
228 }; <<
229 }; <<
230 <<
231 reserved-memory { 176 reserved-memory {
232 #address-cells = <2>; 177 #address-cells = <2>;
233 #size-cells = <2>; 178 #size-cells = <2>;
234 ranges; 179 ranges;
235 180
236 dfps_data_mem: dfps-data@34000 !! 181 dfps_data_mem: dfps_data_mem@3400000 {
237 reg = <0 0x03400000 0 182 reg = <0 0x03400000 0 0x1000>;
238 no-map; 183 no-map;
239 }; 184 };
240 185
241 cont_splash_mem: memory@340100 186 cont_splash_mem: memory@3401000 {
242 reg = <0 0x03401000 0 187 reg = <0 0x03401000 0 0x2200000>;
243 no-map; 188 no-map;
244 }; 189 };
245 190
246 smem_mem: smem@6a00000 { !! 191 smem_mem: smem_region@6a00000 {
247 reg = <0 0x06a00000 0 192 reg = <0 0x06a00000 0 0x200000>;
248 no-map; 193 no-map;
249 }; 194 };
250 195
251 mpss_mem: memory@7000000 { 196 mpss_mem: memory@7000000 {
252 reg = <0 0x07000000 0 197 reg = <0 0x07000000 0 0x5a00000>;
253 no-map; 198 no-map;
254 }; 199 };
255 200
256 peripheral_region: memory@ca00 201 peripheral_region: memory@ca00000 {
257 reg = <0 0x0ca00000 0 202 reg = <0 0x0ca00000 0 0x1f00000>;
258 no-map; 203 no-map;
259 }; 204 };
260 205
261 rmtfs_mem: memory@c6400000 { 206 rmtfs_mem: memory@c6400000 {
262 compatible = "qcom,rmt 207 compatible = "qcom,rmtfs-mem";
263 reg = <0 0xc6400000 0 208 reg = <0 0xc6400000 0 0x180000>;
264 no-map; 209 no-map;
265 210
266 qcom,client-id = <1>; 211 qcom,client-id = <1>;
267 }; 212 };
268 213
269 mba_mem: memory@c6700000 { 214 mba_mem: memory@c6700000 {
270 reg = <0 0xc6700000 0 215 reg = <0 0xc6700000 0 0x100000>;
271 no-map; 216 no-map;
272 }; 217 };
273 218
274 audio_mem: memory@c7000000 { 219 audio_mem: memory@c7000000 {
275 reg = <0 0xc7000000 0 220 reg = <0 0xc7000000 0 0x800000>;
276 no-map; 221 no-map;
277 }; 222 };
278 223
279 adsp_mem: memory@c9400000 { 224 adsp_mem: memory@c9400000 {
280 reg = <0 0xc9400000 0 225 reg = <0 0xc9400000 0 0x3f00000>;
281 no-map; 226 no-map;
282 }; 227 };
>> 228 };
283 229
284 res_hyp_mem: reserved@6c00000 !! 230 smd {
285 reg = <0 0x06c00000 0 !! 231 compatible = "qcom,smd";
286 no-map; !! 232 rpm {
>> 233 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
>> 234 qcom,ipc = <&apcs 8 0>;
>> 235 qcom,smd-edge = <15>;
>> 236 qcom,local-pid = <0>;
>> 237 qcom,remote-pid = <6>;
>> 238
>> 239 rpm_requests: rpm-requests {
>> 240 compatible = "qcom,rpm-msm8994";
>> 241 qcom,smd-channels = "rpm_requests";
>> 242
>> 243 rpmcc: rpmcc {
>> 244 compatible = "qcom,rpmcc-msm8994";
>> 245 #clock-cells = <1>;
>> 246 };
>> 247
>> 248 rpmpd: power-controller {
>> 249 compatible = "qcom,msm8994-rpmpd";
>> 250 #power-domain-cells = <1>;
>> 251 operating-points-v2 = <&rpmpd_opp_table>;
>> 252
>> 253 rpmpd_opp_table: opp-table {
>> 254 compatible = "operating-points-v2";
>> 255
>> 256 rpmpd_opp_ret: opp1 {
>> 257 opp-level = <1>;
>> 258 };
>> 259 rpmpd_opp_svs_krait: opp2 {
>> 260 opp-level = <2>;
>> 261 };
>> 262 rpmpd_opp_svs_soc: opp3 {
>> 263 opp-level = <3>;
>> 264 };
>> 265 rpmpd_opp_nom: opp4 {
>> 266 opp-level = <4>;
>> 267 };
>> 268 rpmpd_opp_turbo: opp5 {
>> 269 opp-level = <5>;
>> 270 };
>> 271 rpmpd_opp_super_turbo: opp6 {
>> 272 opp-level = <6>;
>> 273 };
>> 274 };
>> 275 };
>> 276 };
287 }; 277 };
288 }; 278 };
289 279
290 smem { 280 smem {
291 compatible = "qcom,smem"; 281 compatible = "qcom,smem";
292 memory-region = <&smem_mem>; 282 memory-region = <&smem_mem>;
293 qcom,rpm-msg-ram = <&rpm_msg_r 283 qcom,rpm-msg-ram = <&rpm_msg_ram>;
294 hwlocks = <&tcsr_mutex 3>; 284 hwlocks = <&tcsr_mutex 3>;
295 }; 285 };
296 286
297 smp2p-lpass { 287 smp2p-lpass {
298 compatible = "qcom,smp2p"; 288 compatible = "qcom,smp2p";
299 qcom,smem = <443>, <429>; 289 qcom,smem = <443>, <429>;
300 290
301 interrupts = <GIC_SPI 158 IRQ_ 291 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
302 292
303 mboxes = <&apcs 10>; !! 293 qcom,ipc = <&apcs 8 10>;
304 294
305 qcom,local-pid = <0>; 295 qcom,local-pid = <0>;
306 qcom,remote-pid = <2>; 296 qcom,remote-pid = <2>;
307 297
308 adsp_smp2p_out: master-kernel 298 adsp_smp2p_out: master-kernel {
309 qcom,entry-name = "mas 299 qcom,entry-name = "master-kernel";
310 #qcom,smem-state-cells 300 #qcom,smem-state-cells = <1>;
311 }; 301 };
312 302
313 adsp_smp2p_in: slave-kernel { 303 adsp_smp2p_in: slave-kernel {
314 qcom,entry-name = "sla 304 qcom,entry-name = "slave-kernel";
315 305
316 interrupt-controller; 306 interrupt-controller;
317 #interrupt-cells = <2> 307 #interrupt-cells = <2>;
318 }; 308 };
319 }; 309 };
320 310
321 smp2p-modem { 311 smp2p-modem {
322 compatible = "qcom,smp2p"; 312 compatible = "qcom,smp2p";
323 qcom,smem = <435>, <428>; 313 qcom,smem = <435>, <428>;
324 314
325 interrupt-parent = <&intc>; 315 interrupt-parent = <&intc>;
326 interrupts = <GIC_SPI 27 IRQ_T 316 interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>;
327 317
328 mboxes = <&apcs 14>; !! 318 qcom,ipc = <&apcs 8 14>;
329 319
330 qcom,local-pid = <0>; 320 qcom,local-pid = <0>;
331 qcom,remote-pid = <1>; 321 qcom,remote-pid = <1>;
332 322
333 modem_smp2p_out: master-kernel 323 modem_smp2p_out: master-kernel {
334 qcom,entry-name = "mas 324 qcom,entry-name = "master-kernel";
335 #qcom,smem-state-cells 325 #qcom,smem-state-cells = <1>;
336 }; 326 };
337 327
338 modem_smp2p_in: slave-kernel { 328 modem_smp2p_in: slave-kernel {
339 qcom,entry-name = "sla 329 qcom,entry-name = "slave-kernel";
340 330
341 interrupt-controller; 331 interrupt-controller;
342 #interrupt-cells = <2> 332 #interrupt-cells = <2>;
343 }; 333 };
344 }; 334 };
345 335
346 soc: soc@0 { !! 336 soc: soc {
>> 337
347 #address-cells = <1>; 338 #address-cells = <1>;
348 #size-cells = <1>; 339 #size-cells = <1>;
349 ranges = <0 0 0 0xffffffff>; 340 ranges = <0 0 0 0xffffffff>;
350 compatible = "simple-bus"; 341 compatible = "simple-bus";
351 342
352 intc: interrupt-controller@f90 343 intc: interrupt-controller@f9000000 {
353 compatible = "qcom,msm 344 compatible = "qcom,msm-qgic2";
354 interrupt-controller; 345 interrupt-controller;
355 #interrupt-cells = <3> 346 #interrupt-cells = <3>;
356 reg = <0xf9000000 0x10 347 reg = <0xf9000000 0x1000>,
357 <0xf9002000 0x10 348 <0xf9002000 0x1000>;
358 }; 349 };
359 350
360 apcs: mailbox@f900d000 { 351 apcs: mailbox@f900d000 {
361 compatible = "qcom,msm 352 compatible = "qcom,msm8994-apcs-kpss-global", "syscon";
362 reg = <0xf900d000 0x20 353 reg = <0xf900d000 0x2000>;
363 #mbox-cells = <1>; 354 #mbox-cells = <1>;
364 }; 355 };
365 356
366 watchdog@f9017000 { <<
367 compatible = "qcom,aps <<
368 reg = <0xf9017000 0x10 <<
369 interrupts = <GIC_SPI <<
370 <GIC_SPI <<
371 clocks = <&sleep_clk>; <<
372 timeout-sec = <10>; <<
373 }; <<
374 <<
375 timer@f9020000 { 357 timer@f9020000 {
376 #address-cells = <1>; 358 #address-cells = <1>;
377 #size-cells = <1>; 359 #size-cells = <1>;
378 ranges; 360 ranges;
379 compatible = "arm,armv 361 compatible = "arm,armv7-timer-mem";
380 reg = <0xf9020000 0x10 362 reg = <0xf9020000 0x1000>;
381 363
382 frame@f9021000 { 364 frame@f9021000 {
383 frame-number = 365 frame-number = <0>;
384 interrupts = < 366 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
385 < 367 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
386 reg = <0xf9021 368 reg = <0xf9021000 0x1000>,
387 <0xf9022 369 <0xf9022000 0x1000>;
388 }; 370 };
389 371
390 frame@f9023000 { 372 frame@f9023000 {
391 frame-number = 373 frame-number = <1>;
392 interrupts = < 374 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
393 reg = <0xf9023 375 reg = <0xf9023000 0x1000>;
394 status = "disa 376 status = "disabled";
395 }; 377 };
396 378
397 frame@f9024000 { 379 frame@f9024000 {
398 frame-number = 380 frame-number = <2>;
399 interrupts = < 381 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
400 reg = <0xf9024 382 reg = <0xf9024000 0x1000>;
401 status = "disa 383 status = "disabled";
402 }; 384 };
403 385
404 frame@f9025000 { 386 frame@f9025000 {
405 frame-number = 387 frame-number = <3>;
406 interrupts = < 388 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
407 reg = <0xf9025 389 reg = <0xf9025000 0x1000>;
408 status = "disa 390 status = "disabled";
409 }; 391 };
410 392
411 frame@f9026000 { 393 frame@f9026000 {
412 frame-number = 394 frame-number = <4>;
413 interrupts = < 395 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
414 reg = <0xf9026 396 reg = <0xf9026000 0x1000>;
415 status = "disa 397 status = "disabled";
416 }; 398 };
417 399
418 frame@f9027000 { 400 frame@f9027000 {
419 frame-number = 401 frame-number = <5>;
420 interrupts = < 402 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
421 reg = <0xf9027 403 reg = <0xf9027000 0x1000>;
422 status = "disa 404 status = "disabled";
423 }; 405 };
424 406
425 frame@f9028000 { 407 frame@f9028000 {
426 frame-number = 408 frame-number = <6>;
427 interrupts = < 409 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
428 reg = <0xf9028 410 reg = <0xf9028000 0x1000>;
429 status = "disa 411 status = "disabled";
430 }; 412 };
431 }; 413 };
432 414
433 usb3: usb@f92f8800 { 415 usb3: usb@f92f8800 {
434 compatible = "qcom,msm !! 416 compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
435 reg = <0xf92f8800 0x40 417 reg = <0xf92f8800 0x400>;
436 #address-cells = <1>; 418 #address-cells = <1>;
437 #size-cells = <1>; 419 #size-cells = <1>;
438 ranges; 420 ranges;
439 421
440 clocks = <&gcc GCC_USB 422 clocks = <&gcc GCC_USB30_MASTER_CLK>,
441 <&gcc GCC_SYS 423 <&gcc GCC_SYS_NOC_USB3_AXI_CLK>,
442 <&gcc GCC_USB 424 <&gcc GCC_USB30_SLEEP_CLK>,
443 <&gcc GCC_USB 425 <&gcc GCC_USB30_MOCK_UTMI_CLK>;
444 clock-names = "core", !! 426 clock-names = "core", "iface", "sleep", "mock_utmi", "ref", "xo";
445 "iface", <<
446 "sleep", <<
447 "mock_ut <<
448 427
449 assigned-clocks = <&gc 428 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
450 <&gc 429 <&gcc GCC_USB30_MASTER_CLK>;
451 assigned-clock-rates = 430 assigned-clock-rates = <19200000>, <120000000>;
452 431
453 power-domains = <&gcc 432 power-domains = <&gcc USB30_GDSC>;
454 qcom,select-utmi-as-pi 433 qcom,select-utmi-as-pipe-clk;
455 434
456 usb@f9200000 { 435 usb@f9200000 {
457 compatible = " 436 compatible = "snps,dwc3";
458 reg = <0xf9200 437 reg = <0xf9200000 0xcc00>;
459 interrupts = < !! 438 interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>;
460 snps,dis_u2_su 439 snps,dis_u2_susphy_quirk;
461 snps,dis_enbls 440 snps,dis_enblslpm_quirk;
462 maximum-speed 441 maximum-speed = "high-speed";
463 dr_mode = "per 442 dr_mode = "peripheral";
464 }; 443 };
465 }; 444 };
466 445
467 sdhc1: mmc@f9824900 { !! 446 sdhc1: sdhci@f9824900 {
468 compatible = "qcom,msm !! 447 compatible = "qcom,sdhci-msm-v4";
469 reg = <0xf9824900 0x1a 448 reg = <0xf9824900 0x1a0>, <0xf9824000 0x800>;
470 reg-names = "hc", "cor !! 449 reg-names = "hc_mem", "core_mem";
471 450
472 interrupts = <GIC_SPI 451 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
473 <GIC_SPI 452 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
474 interrupt-names = "hc_ 453 interrupt-names = "hc_irq", "pwr_irq";
475 454
476 clocks = <&gcc GCC_SDC !! 455 clocks = <&gcc GCC_SDCC1_APPS_CLK>,
477 <&gcc GCC_SDC !! 456 <&gcc GCC_SDCC1_AHB_CLK>,
478 <&xo_board>; 457 <&xo_board>;
479 clock-names = "iface", !! 458 clock-names = "core", "iface", "xo";
480 459
481 pinctrl-names = "defau 460 pinctrl-names = "default", "sleep";
482 pinctrl-0 = <&sdc1_clk 461 pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>;
483 pinctrl-1 = <&sdc1_clk 462 pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>;
484 463
485 bus-width = <8>; 464 bus-width = <8>;
486 non-removable; 465 non-removable;
487 status = "disabled"; 466 status = "disabled";
488 }; 467 };
489 468
490 sdhc2: mmc@f98a4900 { !! 469 sdhc2: sdhci@f98a4900 {
491 compatible = "qcom,msm !! 470 compatible = "qcom,sdhci-msm-v4";
492 reg = <0xf98a4900 0x11 471 reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
493 reg-names = "hc", "cor !! 472 reg-names = "hc_mem", "core_mem";
494 473
495 interrupts = <GIC_SPI 474 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
496 <GIC_SPI 221 I 475 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
497 interrupt-names = "hc_ 476 interrupt-names = "hc_irq", "pwr_irq";
498 477
499 clocks = <&gcc GCC_SDC !! 478 clocks = <&gcc GCC_SDCC2_APPS_CLK>,
500 <&gcc GCC_SDC !! 479 <&gcc GCC_SDCC2_AHB_CLK>,
501 <&xo_board>; !! 480 <&xo_board>;
502 clock-names = "iface", !! 481 clock-names = "core", "iface", "xo";
503 482
504 pinctrl-names = "defau 483 pinctrl-names = "default", "sleep";
505 pinctrl-0 = <&sdc2_clk 484 pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>;
506 pinctrl-1 = <&sdc2_clk 485 pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>;
507 486
508 cd-gpios = <&tlmm 100 !! 487 cd-gpios = <&tlmm 100 0>;
509 bus-width = <4>; 488 bus-width = <4>;
510 status = "disabled"; 489 status = "disabled";
511 }; 490 };
512 491
513 blsp1_dma: dma-controller@f990 492 blsp1_dma: dma-controller@f9904000 {
514 compatible = "qcom,bam 493 compatible = "qcom,bam-v1.7.0";
515 reg = <0xf9904000 0x19 494 reg = <0xf9904000 0x19000>;
516 interrupts = <GIC_SPI 495 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
517 clocks = <&gcc GCC_BLS 496 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
518 clock-names = "bam_clk 497 clock-names = "bam_clk";
519 #dma-cells = <1>; 498 #dma-cells = <1>;
520 qcom,ee = <0>; 499 qcom,ee = <0>;
521 qcom,controlled-remote 500 qcom,controlled-remotely;
522 num-channels = <24>; 501 num-channels = <24>;
523 qcom,num-ees = <4>; 502 qcom,num-ees = <4>;
524 }; 503 };
525 504
526 blsp1_uart2: serial@f991e000 { 505 blsp1_uart2: serial@f991e000 {
527 compatible = "qcom,msm 506 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
528 reg = <0xf991e000 0x10 507 reg = <0xf991e000 0x1000>;
529 interrupts = <GIC_SPI 508 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
530 clock-names = "core", 509 clock-names = "core", "iface";
531 clocks = <&gcc GCC_BLS 510 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
532 <&gcc GCC_BLS 511 <&gcc GCC_BLSP1_AHB_CLK>;
533 pinctrl-names = "defau 512 pinctrl-names = "default", "sleep";
534 pinctrl-0 = <&blsp1_ua 513 pinctrl-0 = <&blsp1_uart2_default>;
535 pinctrl-1 = <&blsp1_ua 514 pinctrl-1 = <&blsp1_uart2_sleep>;
536 status = "disabled"; 515 status = "disabled";
537 }; 516 };
538 517
539 blsp1_i2c1: i2c@f9923000 { 518 blsp1_i2c1: i2c@f9923000 {
540 compatible = "qcom,i2c 519 compatible = "qcom,i2c-qup-v2.2.1";
541 reg = <0xf9923000 0x50 520 reg = <0xf9923000 0x500>;
542 interrupts = <GIC_SPI 521 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
543 clocks = <&gcc GCC_BLS !! 522 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
544 <&gcc GCC_BLS !! 523 <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>;
545 clock-names = "core", !! 524 clock-names = "iface", "core";
546 clock-frequency = <400 525 clock-frequency = <400000>;
547 dmas = <&blsp1_dma 12> 526 dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
548 dma-names = "tx", "rx" 527 dma-names = "tx", "rx";
549 pinctrl-names = "defau 528 pinctrl-names = "default", "sleep";
550 pinctrl-0 = <&i2c1_def 529 pinctrl-0 = <&i2c1_default>;
551 pinctrl-1 = <&i2c1_sle 530 pinctrl-1 = <&i2c1_sleep>;
552 #address-cells = <1>; 531 #address-cells = <1>;
553 #size-cells = <0>; 532 #size-cells = <0>;
554 status = "disabled"; 533 status = "disabled";
555 }; 534 };
556 535
557 blsp1_spi1: spi@f9923000 { 536 blsp1_spi1: spi@f9923000 {
558 compatible = "qcom,spi 537 compatible = "qcom,spi-qup-v2.2.1";
559 reg = <0xf9923000 0x50 538 reg = <0xf9923000 0x500>;
560 interrupts = <GIC_SPI 539 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
561 clocks = <&gcc GCC_BLS 540 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
562 <&gcc GCC_BLS 541 <&gcc GCC_BLSP1_AHB_CLK>;
563 clock-names = "core", 542 clock-names = "core", "iface";
>> 543 spi-max-frequency = <19200000>;
564 dmas = <&blsp1_dma 12> 544 dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
565 dma-names = "tx", "rx" 545 dma-names = "tx", "rx";
566 pinctrl-names = "defau 546 pinctrl-names = "default", "sleep";
567 pinctrl-0 = <&blsp1_sp 547 pinctrl-0 = <&blsp1_spi1_default>;
568 pinctrl-1 = <&blsp1_sp 548 pinctrl-1 = <&blsp1_spi1_sleep>;
569 #address-cells = <1>; 549 #address-cells = <1>;
570 #size-cells = <0>; 550 #size-cells = <0>;
571 status = "disabled"; 551 status = "disabled";
572 }; 552 };
573 553
574 blsp1_i2c2: i2c@f9924000 { 554 blsp1_i2c2: i2c@f9924000 {
575 compatible = "qcom,i2c 555 compatible = "qcom,i2c-qup-v2.2.1";
576 reg = <0xf9924000 0x50 556 reg = <0xf9924000 0x500>;
577 interrupts = <GIC_SPI 557 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
578 clocks = <&gcc GCC_BLS !! 558 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
579 <&gcc GCC_BLS !! 559 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
580 clock-names = "core", !! 560 clock-names = "iface", "core";
581 clock-frequency = <400 561 clock-frequency = <400000>;
582 dmas = <&blsp1_dma 14> 562 dmas = <&blsp1_dma 14>, <&blsp1_dma 15>;
583 dma-names = "tx", "rx" 563 dma-names = "tx", "rx";
584 pinctrl-names = "defau 564 pinctrl-names = "default", "sleep";
585 pinctrl-0 = <&i2c2_def 565 pinctrl-0 = <&i2c2_default>;
586 pinctrl-1 = <&i2c2_sle 566 pinctrl-1 = <&i2c2_sleep>;
587 #address-cells = <1>; 567 #address-cells = <1>;
588 #size-cells = <0>; 568 #size-cells = <0>;
589 status = "disabled"; 569 status = "disabled";
590 }; 570 };
591 571
592 /* I2C3 doesn't exist */ 572 /* I2C3 doesn't exist */
593 573
594 blsp1_i2c4: i2c@f9926000 { 574 blsp1_i2c4: i2c@f9926000 {
595 compatible = "qcom,i2c 575 compatible = "qcom,i2c-qup-v2.2.1";
596 reg = <0xf9926000 0x50 576 reg = <0xf9926000 0x500>;
597 interrupts = <GIC_SPI 577 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
598 clocks = <&gcc GCC_BLS !! 578 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
599 <&gcc GCC_BLS !! 579 <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
600 clock-names = "core", !! 580 clock-names = "iface", "core";
601 clock-frequency = <400 581 clock-frequency = <400000>;
602 dmas = <&blsp1_dma 18> 582 dmas = <&blsp1_dma 18>, <&blsp1_dma 19>;
603 dma-names = "tx", "rx" 583 dma-names = "tx", "rx";
604 pinctrl-names = "defau 584 pinctrl-names = "default", "sleep";
605 pinctrl-0 = <&i2c4_def 585 pinctrl-0 = <&i2c4_default>;
606 pinctrl-1 = <&i2c4_sle 586 pinctrl-1 = <&i2c4_sleep>;
607 #address-cells = <1>; 587 #address-cells = <1>;
608 #size-cells = <0>; 588 #size-cells = <0>;
609 status = "disabled"; 589 status = "disabled";
610 }; 590 };
611 591
612 blsp1_i2c5: i2c@f9927000 { 592 blsp1_i2c5: i2c@f9927000 {
613 compatible = "qcom,i2c 593 compatible = "qcom,i2c-qup-v2.2.1";
614 reg = <0xf9927000 0x50 594 reg = <0xf9927000 0x500>;
615 interrupts = <GIC_SPI 595 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
616 clocks = <&gcc GCC_BLS !! 596 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
617 <&gcc GCC_BLS !! 597 <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>;
618 clock-names = "core", !! 598 clock-names = "iface", "core";
619 clock-frequency = <400 599 clock-frequency = <400000>;
620 dmas = <&blsp2_dma 20> 600 dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
621 dma-names = "tx", "rx" 601 dma-names = "tx", "rx";
622 pinctrl-names = "defau 602 pinctrl-names = "default", "sleep";
623 pinctrl-0 = <&i2c5_def 603 pinctrl-0 = <&i2c5_default>;
624 pinctrl-1 = <&i2c5_sle 604 pinctrl-1 = <&i2c5_sleep>;
625 #address-cells = <1>; 605 #address-cells = <1>;
626 #size-cells = <0>; 606 #size-cells = <0>;
627 status = "disabled"; 607 status = "disabled";
628 }; 608 };
629 609
630 blsp1_i2c6: i2c@f9928000 { 610 blsp1_i2c6: i2c@f9928000 {
631 compatible = "qcom,i2c 611 compatible = "qcom,i2c-qup-v2.2.1";
632 reg = <0xf9928000 0x50 612 reg = <0xf9928000 0x500>;
633 interrupts = <GIC_SPI 613 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
634 clocks = <&gcc GCC_BLS !! 614 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
635 <&gcc GCC_BLS !! 615 <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;
636 clock-names = "core", !! 616 clock-names = "iface", "core";
637 clock-frequency = <400 617 clock-frequency = <400000>;
638 dmas = <&blsp1_dma 22> 618 dmas = <&blsp1_dma 22>, <&blsp1_dma 23>;
639 dma-names = "tx", "rx" 619 dma-names = "tx", "rx";
640 pinctrl-names = "defau 620 pinctrl-names = "default", "sleep";
641 pinctrl-0 = <&i2c6_def 621 pinctrl-0 = <&i2c6_default>;
642 pinctrl-1 = <&i2c6_sle 622 pinctrl-1 = <&i2c6_sleep>;
643 #address-cells = <1>; 623 #address-cells = <1>;
644 #size-cells = <0>; 624 #size-cells = <0>;
645 status = "disabled"; 625 status = "disabled";
646 }; 626 };
647 627
648 blsp2_dma: dma-controller@f994 628 blsp2_dma: dma-controller@f9944000 {
649 compatible = "qcom,bam 629 compatible = "qcom,bam-v1.7.0";
650 reg = <0xf9944000 0x19 630 reg = <0xf9944000 0x19000>;
651 interrupts = <GIC_SPI 631 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
652 clocks = <&gcc GCC_BLS 632 clocks = <&gcc GCC_BLSP2_AHB_CLK>;
653 clock-names = "bam_clk 633 clock-names = "bam_clk";
654 #dma-cells = <1>; 634 #dma-cells = <1>;
655 qcom,ee = <0>; 635 qcom,ee = <0>;
656 qcom,controlled-remote 636 qcom,controlled-remotely;
657 num-channels = <24>; 637 num-channels = <24>;
658 qcom,num-ees = <4>; 638 qcom,num-ees = <4>;
659 }; 639 };
660 640
661 blsp2_uart2: serial@f995e000 { 641 blsp2_uart2: serial@f995e000 {
662 compatible = "qcom,msm 642 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
663 reg = <0xf995e000 0x10 643 reg = <0xf995e000 0x1000>;
664 interrupts = <GIC_SPI 644 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
665 clock-names = "core", 645 clock-names = "core", "iface";
666 clocks = <&gcc GCC_BLS 646 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
667 <&gcc 647 <&gcc GCC_BLSP2_AHB_CLK>;
668 dmas = <&blsp2_dma 2>, 648 dmas = <&blsp2_dma 2>, <&blsp2_dma 3>;
669 dma-names = "tx", "rx" 649 dma-names = "tx", "rx";
670 pinctrl-names = "defau 650 pinctrl-names = "default", "sleep";
671 pinctrl-0 = <&blsp2_ua 651 pinctrl-0 = <&blsp2_uart2_default>;
672 pinctrl-1 = <&blsp2_ua 652 pinctrl-1 = <&blsp2_uart2_sleep>;
673 status = "disabled"; 653 status = "disabled";
674 }; 654 };
675 655
676 blsp2_i2c1: i2c@f9963000 { 656 blsp2_i2c1: i2c@f9963000 {
677 compatible = "qcom,i2c 657 compatible = "qcom,i2c-qup-v2.2.1";
678 reg = <0xf9963000 0x50 658 reg = <0xf9963000 0x500>;
679 interrupts = <GIC_SPI 659 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
680 clocks = <&gcc GCC_BLS !! 660 clocks = <&gcc GCC_BLSP2_AHB_CLK>,
681 <&gcc GCC_BLS !! 661 <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>;
682 clock-names = "core", !! 662 clock-names = "iface", "core";
683 clock-frequency = <400 663 clock-frequency = <400000>;
684 dmas = <&blsp2_dma 12> 664 dmas = <&blsp2_dma 12>, <&blsp2_dma 13>;
685 dma-names = "tx", "rx" 665 dma-names = "tx", "rx";
686 pinctrl-names = "defau 666 pinctrl-names = "default", "sleep";
687 pinctrl-0 = <&i2c7_def 667 pinctrl-0 = <&i2c7_default>;
688 pinctrl-1 = <&i2c7_sle 668 pinctrl-1 = <&i2c7_sleep>;
689 #address-cells = <1>; 669 #address-cells = <1>;
690 #size-cells = <0>; 670 #size-cells = <0>;
691 status = "disabled"; 671 status = "disabled";
692 }; 672 };
693 673
694 blsp2_spi4: spi@f9966000 { 674 blsp2_spi4: spi@f9966000 {
695 compatible = "qcom,spi 675 compatible = "qcom,spi-qup-v2.2.1";
696 reg = <0xf9966000 0x50 676 reg = <0xf9966000 0x500>;
697 interrupts = <GIC_SPI 677 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
698 clocks = <&gcc GCC_BLS 678 clocks = <&gcc GCC_BLSP2_QUP4_SPI_APPS_CLK>,
699 <&gcc GCC_BLS 679 <&gcc GCC_BLSP2_AHB_CLK>;
700 clock-names = "core", 680 clock-names = "core", "iface";
>> 681 spi-max-frequency = <19200000>;
701 dmas = <&blsp2_dma 18> 682 dmas = <&blsp2_dma 18>, <&blsp2_dma 19>;
702 dma-names = "tx", "rx" 683 dma-names = "tx", "rx";
703 pinctrl-names = "defau 684 pinctrl-names = "default", "sleep";
704 pinctrl-0 = <&blsp2_sp 685 pinctrl-0 = <&blsp2_spi10_default>;
705 pinctrl-1 = <&blsp2_sp 686 pinctrl-1 = <&blsp2_spi10_sleep>;
706 #address-cells = <1>; 687 #address-cells = <1>;
707 #size-cells = <0>; 688 #size-cells = <0>;
708 status = "disabled"; 689 status = "disabled";
709 }; 690 };
710 691
711 blsp2_i2c5: i2c@f9967000 { 692 blsp2_i2c5: i2c@f9967000 {
712 compatible = "qcom,i2c 693 compatible = "qcom,i2c-qup-v2.2.1";
713 reg = <0xf9967000 0x50 694 reg = <0xf9967000 0x500>;
714 interrupts = <GIC_SPI 695 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
715 clocks = <&gcc GCC_BLS !! 696 clocks = <&gcc GCC_BLSP2_AHB_CLK>,
716 <&gcc GCC_BLS !! 697 <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>;
717 clock-names = "core", !! 698 clock-names = "iface", "core";
718 clock-frequency = <355 699 clock-frequency = <355000>;
719 dmas = <&blsp2_dma 20> 700 dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
720 dma-names = "tx", "rx" 701 dma-names = "tx", "rx";
721 pinctrl-names = "defau 702 pinctrl-names = "default", "sleep";
722 pinctrl-0 = <&i2c11_de 703 pinctrl-0 = <&i2c11_default>;
723 pinctrl-1 = <&i2c11_sl 704 pinctrl-1 = <&i2c11_sleep>;
724 #address-cells = <1>; 705 #address-cells = <1>;
725 #size-cells = <0>; 706 #size-cells = <0>;
726 status = "disabled"; 707 status = "disabled";
727 }; 708 };
728 709
729 gcc: clock-controller@fc400000 710 gcc: clock-controller@fc400000 {
730 compatible = "qcom,gcc 711 compatible = "qcom,gcc-msm8994";
731 #clock-cells = <1>; 712 #clock-cells = <1>;
732 #reset-cells = <1>; 713 #reset-cells = <1>;
733 #power-domain-cells = 714 #power-domain-cells = <1>;
734 reg = <0xfc400000 0x20 715 reg = <0xfc400000 0x2000>;
735 <<
736 clock-names = "xo", "s <<
737 clocks = <&xo_board>, <<
738 }; 716 };
739 717
740 rpm_msg_ram: sram@fc428000 { 718 rpm_msg_ram: sram@fc428000 {
741 compatible = "qcom,rpm 719 compatible = "qcom,rpm-msg-ram";
742 reg = <0xfc428000 0x40 720 reg = <0xfc428000 0x4000>;
743 }; 721 };
744 722
745 restart@fc4ab000 { 723 restart@fc4ab000 {
746 compatible = "qcom,psh 724 compatible = "qcom,pshold";
747 reg = <0xfc4ab000 0x4> 725 reg = <0xfc4ab000 0x4>;
748 }; 726 };
749 727
750 spmi_bus: spmi@fc4cf000 { 728 spmi_bus: spmi@fc4cf000 {
751 compatible = "qcom,spm 729 compatible = "qcom,spmi-pmic-arb";
752 reg = <0xfc4cf000 0x10 730 reg = <0xfc4cf000 0x1000>,
753 <0xfc4cb000 0x10 731 <0xfc4cb000 0x1000>,
754 <0xfc4ca000 0x10 732 <0xfc4ca000 0x1000>;
755 reg-names = "core", "i 733 reg-names = "core", "intr", "cnfg";
756 interrupt-names = "per 734 interrupt-names = "periph_irq";
757 interrupts = <GIC_SPI 735 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
758 qcom,ee = <0>; 736 qcom,ee = <0>;
759 qcom,channel = <0>; 737 qcom,channel = <0>;
760 #address-cells = <2>; 738 #address-cells = <2>;
761 #size-cells = <0>; 739 #size-cells = <0>;
762 interrupt-controller; 740 interrupt-controller;
763 #interrupt-cells = <4> 741 #interrupt-cells = <4>;
764 }; 742 };
765 743
766 tcsr_mutex: hwlock@fd484000 { !! 744 tcsr_mutex_regs: syscon@fd484000 {
767 compatible = "qcom,msm !! 745 compatible = "syscon";
768 reg = <0xfd484000 0x10 !! 746 reg = <0xfd484000 0x2000>;
769 #hwlock-cells = <1>; <<
770 }; 747 };
771 748
772 tlmm: pinctrl@fd510000 { 749 tlmm: pinctrl@fd510000 {
773 compatible = "qcom,msm 750 compatible = "qcom,msm8994-pinctrl";
774 reg = <0xfd510000 0x40 751 reg = <0xfd510000 0x4000>;
775 interrupts = <GIC_SPI 752 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
776 gpio-controller; 753 gpio-controller;
777 gpio-ranges = <&tlmm 0 754 gpio-ranges = <&tlmm 0 0 146>;
778 #gpio-cells = <2>; 755 #gpio-cells = <2>;
779 interrupt-controller; 756 interrupt-controller;
780 #interrupt-cells = <2> 757 #interrupt-cells = <2>;
781 758
782 blsp1_uart2_default: b !! 759 blsp1_uart2_default: blsp1-uart2-default {
783 pins = "gpio4" <<
784 function = "bl 760 function = "blsp_uart2";
>> 761 pins = "gpio4", "gpio5";
785 drive-strength 762 drive-strength = <16>;
786 bias-disable; 763 bias-disable;
787 }; 764 };
788 765
789 blsp1_uart2_sleep: bls !! 766 blsp1_uart2_sleep: blsp1-uart2-sleep {
790 pins = "gpio4" <<
791 function = "gp 767 function = "gpio";
>> 768 pins = "gpio4", "gpio5";
792 drive-strength 769 drive-strength = <2>;
793 bias-pull-down 770 bias-pull-down;
794 }; 771 };
795 772
796 blsp2_uart2_default: b !! 773 blsp2_uart2_default: blsp2-uart2-default {
797 pins = "gpio45 <<
798 function = "bl 774 function = "blsp_uart8";
>> 775 pins = "gpio45", "gpio46",
>> 776 "gpio47", "gpio48";
799 drive-strength 777 drive-strength = <16>;
800 bias-disable; 778 bias-disable;
801 }; 779 };
802 780
803 blsp2_uart2_sleep: bls !! 781 blsp2_uart2_sleep: blsp2-uart2-sleep {
804 pins = "gpio45 <<
805 function = "gp 782 function = "gpio";
>> 783 pins = "gpio45", "gpio46",
>> 784 "gpio47", "gpio48";
806 drive-strength 785 drive-strength = <2>;
807 bias-disable; 786 bias-disable;
808 }; 787 };
809 788
810 i2c1_default: i2c1-def !! 789 i2c1_default: i2c1-default {
811 pins = "gpio2" <<
812 function = "bl 790 function = "blsp_i2c1";
>> 791 pins = "gpio2", "gpio3";
813 drive-strength 792 drive-strength = <2>;
814 bias-disable; 793 bias-disable;
815 }; 794 };
816 795
817 i2c1_sleep: i2c1-sleep !! 796 i2c1_sleep: i2c1-sleep {
818 pins = "gpio2" <<
819 function = "gp 797 function = "gpio";
>> 798 pins = "gpio2", "gpio3";
820 drive-strength 799 drive-strength = <2>;
821 bias-disable; 800 bias-disable;
822 }; 801 };
823 802
824 i2c2_default: i2c2-def !! 803 i2c2_default: i2c2-default {
825 pins = "gpio6" <<
826 function = "bl 804 function = "blsp_i2c2";
>> 805 pins = "gpio6", "gpio7";
827 drive-strength 806 drive-strength = <2>;
828 bias-disable; 807 bias-disable;
829 }; 808 };
830 809
831 i2c2_sleep: i2c2-sleep !! 810 i2c2_sleep: i2c2-sleep {
832 pins = "gpio6" <<
833 function = "gp 811 function = "gpio";
>> 812 pins = "gpio6", "gpio7";
834 drive-strength 813 drive-strength = <2>;
835 bias-disable; 814 bias-disable;
836 }; 815 };
837 816
838 i2c4_default: i2c4-def !! 817 i2c4_default: i2c4-default {
839 pins = "gpio19 <<
840 function = "bl 818 function = "blsp_i2c4";
>> 819 pins = "gpio19", "gpio20";
841 drive-strength 820 drive-strength = <2>;
842 bias-disable; 821 bias-disable;
843 }; 822 };
844 823
845 i2c4_sleep: i2c4-sleep !! 824 i2c4_sleep: i2c4-sleep {
846 pins = "gpio19 <<
847 function = "gp 825 function = "gpio";
>> 826 pins = "gpio19", "gpio20";
848 drive-strength 827 drive-strength = <2>;
849 bias-pull-down 828 bias-pull-down;
>> 829 input-enable;
850 }; 830 };
851 831
852 i2c5_default: i2c5-def !! 832 i2c5_default: i2c5-default {
853 pins = "gpio23 <<
854 function = "bl 833 function = "blsp_i2c5";
>> 834 pins = "gpio23", "gpio24";
855 drive-strength 835 drive-strength = <2>;
856 bias-disable; 836 bias-disable;
857 }; 837 };
858 838
859 i2c5_sleep: i2c5-sleep !! 839 i2c5_sleep: i2c5-sleep {
860 pins = "gpio23 <<
861 function = "gp 840 function = "gpio";
>> 841 pins = "gpio23", "gpio24";
862 drive-strength 842 drive-strength = <2>;
863 bias-disable; 843 bias-disable;
864 }; 844 };
865 845
866 i2c6_default: i2c6-def !! 846 i2c6_default: i2c6-default {
867 pins = "gpio28 <<
868 function = "bl 847 function = "blsp_i2c6";
>> 848 pins = "gpio28", "gpio27";
869 drive-strength 849 drive-strength = <2>;
870 bias-disable; 850 bias-disable;
871 }; 851 };
872 852
873 i2c6_sleep: i2c6-sleep !! 853 i2c6_sleep: i2c6-sleep {
874 pins = "gpio28 <<
875 function = "gp 854 function = "gpio";
>> 855 pins = "gpio28", "gpio27";
876 drive-strength 856 drive-strength = <2>;
877 bias-disable; 857 bias-disable;
878 }; 858 };
879 859
880 i2c7_default: i2c7-def !! 860 i2c7_default: i2c7-default {
881 pins = "gpio44 <<
882 function = "bl 861 function = "blsp_i2c7";
>> 862 pins = "gpio44", "gpio43";
883 drive-strength 863 drive-strength = <2>;
884 bias-disable; 864 bias-disable;
885 }; 865 };
886 866
887 i2c7_sleep: i2c7-sleep !! 867 i2c7_sleep: i2c7-sleep {
888 pins = "gpio44 <<
889 function = "gp 868 function = "gpio";
>> 869 pins = "gpio44", "gpio43";
890 drive-strength 870 drive-strength = <2>;
891 bias-disable; 871 bias-disable;
892 }; 872 };
893 873
894 blsp2_spi10_default: b !! 874 blsp2_spi10_default: blsp2-spi10-default {
895 default-pins { !! 875 default {
896 pins = <<
897 functi 876 function = "blsp_spi10";
>> 877 pins = "gpio53", "gpio54", "gpio55";
898 drive- 878 drive-strength = <10>;
899 bias-p 879 bias-pull-down;
900 }; 880 };
901 !! 881 cs {
902 cs-pins { <<
903 pins = <<
904 functi 882 function = "gpio";
>> 883 pins = "gpio55";
905 drive- 884 drive-strength = <2>;
906 bias-d 885 bias-disable;
907 }; 886 };
908 }; 887 };
909 888
910 blsp2_spi10_sleep: bls !! 889 blsp2_spi10_sleep: blsp2-spi10-sleep {
911 pins = "gpio53 890 pins = "gpio53", "gpio54", "gpio55";
912 function = "gp <<
913 drive-strength 891 drive-strength = <2>;
914 bias-disable; 892 bias-disable;
915 }; 893 };
916 894
917 i2c11_default: i2c11-d !! 895 i2c11_default: i2c11-default {
918 pins = "gpio83 <<
919 function = "bl 896 function = "blsp_i2c11";
>> 897 pins = "gpio83", "gpio84";
920 drive-strength 898 drive-strength = <2>;
921 bias-disable; 899 bias-disable;
922 }; 900 };
923 901
924 i2c11_sleep: i2c11-sle !! 902 i2c11_sleep: i2c11-sleep {
925 pins = "gpio83 <<
926 function = "gp 903 function = "gpio";
>> 904 pins = "gpio83", "gpio84";
927 drive-strength 905 drive-strength = <2>;
928 bias-disable; 906 bias-disable;
929 }; 907 };
930 908
931 blsp1_spi1_default: bl !! 909 blsp1_spi1_default: blsp1-spi1-default {
932 default-pins { !! 910 default {
933 pins = <<
934 functi 911 function = "blsp_spi1";
>> 912 pins = "gpio0", "gpio1", "gpio3";
935 drive- 913 drive-strength = <10>;
936 bias-p 914 bias-pull-down;
937 }; 915 };
938 !! 916 cs {
939 cs-pins { <<
940 pins = <<
941 functi 917 function = "gpio";
>> 918 pins = "gpio8";
942 drive- 919 drive-strength = <2>;
943 bias-d 920 bias-disable;
944 }; 921 };
945 }; 922 };
946 923
947 blsp1_spi1_sleep: blsp !! 924 blsp1_spi1_sleep: blsp1-spi1-sleep {
948 pins = "gpio0" 925 pins = "gpio0", "gpio1", "gpio3";
949 function = "gp <<
950 drive-strength 926 drive-strength = <2>;
951 bias-disable; 927 bias-disable;
952 }; 928 };
953 929
954 sdc1_clk_on: clk-on-st !! 930 sdc1_clk_on: clk-on {
955 pins = "sdc1_c 931 pins = "sdc1_clk";
956 bias-disable; 932 bias-disable;
957 drive-strength 933 drive-strength = <16>;
958 }; 934 };
959 935
960 sdc1_clk_off: clk-off- !! 936 sdc1_clk_off: clk-off {
961 pins = "sdc1_c 937 pins = "sdc1_clk";
962 bias-disable; 938 bias-disable;
963 drive-strength 939 drive-strength = <2>;
964 }; 940 };
965 941
966 sdc1_cmd_on: cmd-on-st !! 942 sdc1_cmd_on: cmd-on {
967 pins = "sdc1_c 943 pins = "sdc1_cmd";
968 bias-pull-up; 944 bias-pull-up;
969 drive-strength 945 drive-strength = <8>;
970 }; 946 };
971 947
972 sdc1_cmd_off: cmd-off- !! 948 sdc1_cmd_off: cmd-off {
973 pins = "sdc1_c 949 pins = "sdc1_cmd";
974 bias-pull-up; 950 bias-pull-up;
975 drive-strength 951 drive-strength = <2>;
976 }; 952 };
977 953
978 sdc1_data_on: data-on- !! 954 sdc1_data_on: data-on {
979 pins = "sdc1_d 955 pins = "sdc1_data";
980 bias-pull-up; 956 bias-pull-up;
981 drive-strength 957 drive-strength = <8>;
982 }; 958 };
983 959
984 sdc1_data_off: data-of !! 960 sdc1_data_off: data-off {
985 pins = "sdc1_d 961 pins = "sdc1_data";
986 bias-pull-up; 962 bias-pull-up;
987 drive-strength 963 drive-strength = <2>;
988 }; 964 };
989 965
990 sdc1_rclk_on: rclk-on- !! 966 sdc1_rclk_on: rclk-on {
991 pins = "sdc1_r 967 pins = "sdc1_rclk";
992 bias-pull-down 968 bias-pull-down;
993 }; 969 };
994 970
995 sdc1_rclk_off: rclk-of !! 971 sdc1_rclk_off: rclk-off {
996 pins = "sdc1_r 972 pins = "sdc1_rclk";
997 bias-pull-down 973 bias-pull-down;
998 }; 974 };
999 975
1000 sdc2_clk_on: sdc2-clk !! 976 sdc2_clk_on: sdc2-clk-on {
1001 pins = "sdc2_ 977 pins = "sdc2_clk";
1002 bias-disable; 978 bias-disable;
1003 drive-strengt 979 drive-strength = <10>;
1004 }; 980 };
1005 981
1006 sdc2_clk_off: sdc2-cl !! 982 sdc2_clk_off: sdc2-clk-off {
1007 pins = "sdc2_ 983 pins = "sdc2_clk";
1008 bias-disable; 984 bias-disable;
1009 drive-strengt 985 drive-strength = <2>;
1010 }; 986 };
1011 987
1012 sdc2_cmd_on: sdc2-cmd !! 988 sdc2_cmd_on: sdc2-cmd-on {
1013 pins = "sdc2_ 989 pins = "sdc2_cmd";
1014 bias-pull-up; 990 bias-pull-up;
1015 drive-strengt 991 drive-strength = <10>;
1016 }; 992 };
1017 993
1018 sdc2_cmd_off: sdc2-cm !! 994 sdc2_cmd_off: sdc2-cmd-off {
1019 pins = "sdc2_ 995 pins = "sdc2_cmd";
1020 bias-pull-up; 996 bias-pull-up;
1021 drive-strengt 997 drive-strength = <2>;
1022 }; 998 };
1023 999
1024 sdc2_data_on: sdc2-da !! 1000 sdc2_data_on: sdc2-data-on {
1025 pins = "sdc2_ 1001 pins = "sdc2_data";
1026 bias-pull-up; 1002 bias-pull-up;
1027 drive-strengt 1003 drive-strength = <10>;
1028 }; 1004 };
1029 1005
1030 sdc2_data_off: sdc2-d !! 1006 sdc2_data_off: sdc2-data-off {
1031 pins = "sdc2_ 1007 pins = "sdc2_data";
1032 bias-pull-up; 1008 bias-pull-up;
1033 drive-strengt 1009 drive-strength = <2>;
1034 }; 1010 };
1035 }; 1011 };
1036 <<
1037 mmcc: clock-controller@fd8c00 <<
1038 compatible = "qcom,mm <<
1039 reg = <0xfd8c0000 0x5 <<
1040 #clock-cells = <1>; <<
1041 #reset-cells = <1>; <<
1042 #power-domain-cells = <<
1043 <<
1044 clock-names = "xo", <<
1045 "gpll0" <<
1046 "mmssno <<
1047 "oxili_ <<
1048 "dsi0pl <<
1049 "dsi0pl <<
1050 "dsi1pl <<
1051 "dsi1pl <<
1052 "hdmipl <<
1053 clocks = <&xo_board>, <<
1054 <&gcc GPLL0_ <<
1055 <&rpmcc RPM_ <<
1056 <&rpmcc RPM_ <<
1057 <0>, <<
1058 <0>, <<
1059 <0>, <<
1060 <0>, <<
1061 <0>; <<
1062 <<
1063 assigned-clocks = <&m <<
1064 <&m <<
1065 <&m <<
1066 <&m <<
1067 <&m <<
1068 assigned-clock-rates <<
1069 <<
1070 <<
1071 <<
1072 <<
1073 }; <<
1074 <<
1075 ocmem: sram@fdd00000 { <<
1076 compatible = "qcom,ms <<
1077 reg = <0xfdd00000 0x2 <<
1078 <0xfec00000 0x2 <<
1079 reg-names = "ctrl", " <<
1080 ranges = <0 0xfec0000 <<
1081 clocks = <&rpmcc RPM_ <<
1082 <&mmcc OCMEM <<
1083 clock-names = "core", <<
1084 <<
1085 #address-cells = <1>; <<
1086 #size-cells = <1>; <<
1087 <<
1088 gmu_sram: gmu-sram@0 <<
1089 reg = <0x0 0x <<
1090 }; <<
1091 }; <<
1092 }; 1012 };
1093 1013
1094 timer: timer { 1014 timer: timer {
1095 compatible = "arm,armv8-timer 1015 compatible = "arm,armv8-timer";
1096 interrupts = <GIC_PPI 2 (GIC_ !! 1016 interrupts = <GIC_PPI 2 0xff08>,
1097 <GIC_PPI 3 (GIC_ !! 1017 <GIC_PPI 3 0xff08>,
1098 <GIC_PPI 4 (GIC_ !! 1018 <GIC_PPI 4 0xff08>,
1099 <GIC_PPI 1 (GIC_ !! 1019 <GIC_PPI 1 0xff08>;
1100 }; 1020 };
1101 1021
1102 vph_pwr: vph-pwr-regulator { 1022 vph_pwr: vph-pwr-regulator {
1103 compatible = "regulator-fixed 1023 compatible = "regulator-fixed";
1104 regulator-name = "vph_pwr"; 1024 regulator-name = "vph_pwr";
1105 1025
1106 regulator-min-microvolt = <36 1026 regulator-min-microvolt = <3600000>;
1107 regulator-max-microvolt = <36 1027 regulator-max-microvolt = <3600000>;
1108 1028
1109 regulator-always-on; 1029 regulator-always-on;
1110 }; 1030 };
1111 }; 1031 };
1112 1032
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