1 // SPDX-License-Identifier: GPL-2.0-only 1 // SPDX-License-Identifier: GPL-2.0-only
2 /* !! 2 /* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
3 * Copyright (c) 2013-2016, The Linux Foundati <<
4 */ 3 */
5 4
6 #include <dt-bindings/interrupt-controller/arm 5 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,gcc-msm8994.h 6 #include <dt-bindings/clock/qcom,gcc-msm8994.h>
8 #include <dt-bindings/clock/qcom,mmcc-msm8994. 7 #include <dt-bindings/clock/qcom,mmcc-msm8994.h>
9 #include <dt-bindings/clock/qcom,rpmcc.h> 8 #include <dt-bindings/clock/qcom,rpmcc.h>
10 #include <dt-bindings/gpio/gpio.h> 9 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/power/qcom-rpmpd.h> 10 #include <dt-bindings/power/qcom-rpmpd.h>
12 11
13 / { 12 / {
14 interrupt-parent = <&intc>; 13 interrupt-parent = <&intc>;
15 14
16 #address-cells = <2>; 15 #address-cells = <2>;
17 #size-cells = <2>; 16 #size-cells = <2>;
18 17
19 aliases { 18 aliases {
20 mmc1 = &sdhc1; 19 mmc1 = &sdhc1;
21 mmc2 = &sdhc2; 20 mmc2 = &sdhc2;
22 }; 21 };
23 22
24 chosen { }; 23 chosen { };
25 24
26 clocks { 25 clocks {
27 xo_board: xo-board { 26 xo_board: xo-board {
28 compatible = "fixed-cl 27 compatible = "fixed-clock";
29 #clock-cells = <0>; 28 #clock-cells = <0>;
30 clock-frequency = <192 29 clock-frequency = <19200000>;
31 clock-output-names = " 30 clock-output-names = "xo_board";
32 }; 31 };
33 32
34 sleep_clk: sleep-clk { 33 sleep_clk: sleep-clk {
35 compatible = "fixed-cl 34 compatible = "fixed-clock";
36 #clock-cells = <0>; 35 #clock-cells = <0>;
37 clock-frequency = <327 36 clock-frequency = <32768>;
38 clock-output-names = " 37 clock-output-names = "sleep_clk";
39 }; 38 };
40 }; 39 };
41 40
42 cpus { 41 cpus {
43 #address-cells = <2>; 42 #address-cells = <2>;
44 #size-cells = <0>; 43 #size-cells = <0>;
45 44
46 CPU0: cpu@0 { 45 CPU0: cpu@0 {
47 device_type = "cpu"; 46 device_type = "cpu";
48 compatible = "arm,cort 47 compatible = "arm,cortex-a53";
49 reg = <0x0 0x0>; 48 reg = <0x0 0x0>;
50 enable-method = "psci" 49 enable-method = "psci";
51 next-level-cache = <&L 50 next-level-cache = <&L2_0>;
52 L2_0: l2-cache { 51 L2_0: l2-cache {
53 compatible = " 52 compatible = "cache";
54 cache-level = 53 cache-level = <2>;
55 cache-unified; <<
56 }; 54 };
57 }; 55 };
58 56
59 CPU1: cpu@1 { 57 CPU1: cpu@1 {
60 device_type = "cpu"; 58 device_type = "cpu";
61 compatible = "arm,cort 59 compatible = "arm,cortex-a53";
62 reg = <0x0 0x1>; 60 reg = <0x0 0x1>;
63 enable-method = "psci" 61 enable-method = "psci";
64 next-level-cache = <&L 62 next-level-cache = <&L2_0>;
65 }; 63 };
66 64
67 CPU2: cpu@2 { 65 CPU2: cpu@2 {
68 device_type = "cpu"; 66 device_type = "cpu";
69 compatible = "arm,cort 67 compatible = "arm,cortex-a53";
70 reg = <0x0 0x2>; 68 reg = <0x0 0x2>;
71 enable-method = "psci" 69 enable-method = "psci";
72 next-level-cache = <&L 70 next-level-cache = <&L2_0>;
73 }; 71 };
74 72
75 CPU3: cpu@3 { 73 CPU3: cpu@3 {
76 device_type = "cpu"; 74 device_type = "cpu";
77 compatible = "arm,cort 75 compatible = "arm,cortex-a53";
78 reg = <0x0 0x3>; 76 reg = <0x0 0x3>;
79 enable-method = "psci" 77 enable-method = "psci";
80 next-level-cache = <&L 78 next-level-cache = <&L2_0>;
81 }; 79 };
82 80
83 CPU4: cpu@100 { 81 CPU4: cpu@100 {
84 device_type = "cpu"; 82 device_type = "cpu";
85 compatible = "arm,cort 83 compatible = "arm,cortex-a57";
86 reg = <0x0 0x100>; 84 reg = <0x0 0x100>;
87 enable-method = "psci" 85 enable-method = "psci";
88 next-level-cache = <&L 86 next-level-cache = <&L2_1>;
89 L2_1: l2-cache { 87 L2_1: l2-cache {
90 compatible = " 88 compatible = "cache";
91 cache-level = 89 cache-level = <2>;
92 cache-unified; <<
93 }; 90 };
94 }; 91 };
95 92
96 CPU5: cpu@101 { 93 CPU5: cpu@101 {
97 device_type = "cpu"; 94 device_type = "cpu";
98 compatible = "arm,cort 95 compatible = "arm,cortex-a57";
99 reg = <0x0 0x101>; 96 reg = <0x0 0x101>;
100 enable-method = "psci" 97 enable-method = "psci";
101 next-level-cache = <&L 98 next-level-cache = <&L2_1>;
102 }; 99 };
103 100
104 CPU6: cpu@102 { 101 CPU6: cpu@102 {
105 device_type = "cpu"; 102 device_type = "cpu";
106 compatible = "arm,cort 103 compatible = "arm,cortex-a57";
107 reg = <0x0 0x102>; 104 reg = <0x0 0x102>;
108 enable-method = "psci" 105 enable-method = "psci";
109 next-level-cache = <&L 106 next-level-cache = <&L2_1>;
110 }; 107 };
111 108
112 CPU7: cpu@103 { 109 CPU7: cpu@103 {
113 device_type = "cpu"; 110 device_type = "cpu";
114 compatible = "arm,cort 111 compatible = "arm,cortex-a57";
115 reg = <0x0 0x103>; 112 reg = <0x0 0x103>;
116 enable-method = "psci" 113 enable-method = "psci";
117 next-level-cache = <&L 114 next-level-cache = <&L2_1>;
118 }; 115 };
119 116
120 cpu-map { 117 cpu-map {
121 cluster0 { 118 cluster0 {
122 core0 { 119 core0 {
123 cpu = 120 cpu = <&CPU0>;
124 }; 121 };
125 122
126 core1 { 123 core1 {
127 cpu = 124 cpu = <&CPU1>;
128 }; 125 };
129 126
130 core2 { 127 core2 {
131 cpu = 128 cpu = <&CPU2>;
132 }; 129 };
133 130
134 core3 { 131 core3 {
135 cpu = 132 cpu = <&CPU3>;
136 }; 133 };
137 }; 134 };
138 135
139 cluster1 { 136 cluster1 {
140 core0 { 137 core0 {
141 cpu = 138 cpu = <&CPU4>;
142 }; 139 };
143 140
144 core1 { 141 core1 {
145 cpu = 142 cpu = <&CPU5>;
146 }; 143 };
147 144
148 cpu6_map: core 145 cpu6_map: core2 {
149 cpu = 146 cpu = <&CPU6>;
150 }; 147 };
151 148
152 cpu7_map: core 149 cpu7_map: core3 {
153 cpu = 150 cpu = <&CPU7>;
154 }; 151 };
155 }; 152 };
156 }; 153 };
157 }; 154 };
158 155
159 firmware { 156 firmware {
160 scm { 157 scm {
161 compatible = "qcom,scm 158 compatible = "qcom,scm-msm8994", "qcom,scm";
162 }; 159 };
163 }; 160 };
164 161
165 memory@80000000 { 162 memory@80000000 {
166 device_type = "memory"; 163 device_type = "memory";
167 /* We expect the bootloader to 164 /* We expect the bootloader to fill in the reg */
168 reg = <0 0x80000000 0 0>; 165 reg = <0 0x80000000 0 0>;
169 }; 166 };
170 167
171 pmu { 168 pmu {
172 compatible = "arm,cortex-a53-p 169 compatible = "arm,cortex-a53-pmu";
173 interrupts = <GIC_PPI 7 (GIC_C 170 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4)| IRQ_TYPE_LEVEL_HIGH)>;
174 }; 171 };
175 172
176 psci { 173 psci {
177 compatible = "arm,psci-0.2"; 174 compatible = "arm,psci-0.2";
178 method = "hvc"; 175 method = "hvc";
179 }; 176 };
180 177
181 rpm: remoteproc { <<
182 compatible = "qcom,msm8994-rpm <<
183 <<
184 smd-edge { <<
185 interrupts = <GIC_SPI <<
186 mboxes = <&apcs 0>; <<
187 qcom,smd-edge = <15>; <<
188 qcom,remote-pid = <6>; <<
189 <<
190 rpm_requests: rpm-requ <<
191 compatible = " <<
192 qcom,smd-chann <<
193 <<
194 rpmcc: clock-c <<
195 compat <<
196 #clock <<
197 }; <<
198 <<
199 rpmpd: power-c <<
200 compat <<
201 #power <<
202 operat <<
203 <<
204 rpmpd_ <<
205 <<
206 <<
207 <<
208 <<
209 <<
210 <<
211 <<
212 <<
213 <<
214 <<
215 <<
216 <<
217 <<
218 <<
219 <<
220 <<
221 <<
222 <<
223 <<
224 <<
225 }; <<
226 }; <<
227 }; <<
228 }; <<
229 }; <<
230 <<
231 reserved-memory { 178 reserved-memory {
232 #address-cells = <2>; 179 #address-cells = <2>;
233 #size-cells = <2>; 180 #size-cells = <2>;
234 ranges; 181 ranges;
235 182
236 dfps_data_mem: dfps-data@34000 !! 183 dfps_data_mem: dfps_data_mem@3400000 {
237 reg = <0 0x03400000 0 184 reg = <0 0x03400000 0 0x1000>;
238 no-map; 185 no-map;
239 }; 186 };
240 187
241 cont_splash_mem: memory@340100 188 cont_splash_mem: memory@3401000 {
242 reg = <0 0x03401000 0 189 reg = <0 0x03401000 0 0x2200000>;
243 no-map; 190 no-map;
244 }; 191 };
245 192
246 smem_mem: smem@6a00000 { !! 193 smem_mem: smem_region@6a00000 {
247 reg = <0 0x06a00000 0 194 reg = <0 0x06a00000 0 0x200000>;
248 no-map; 195 no-map;
249 }; 196 };
250 197
251 mpss_mem: memory@7000000 { 198 mpss_mem: memory@7000000 {
252 reg = <0 0x07000000 0 199 reg = <0 0x07000000 0 0x5a00000>;
253 no-map; 200 no-map;
254 }; 201 };
255 202
256 peripheral_region: memory@ca00 203 peripheral_region: memory@ca00000 {
257 reg = <0 0x0ca00000 0 204 reg = <0 0x0ca00000 0 0x1f00000>;
258 no-map; 205 no-map;
259 }; 206 };
260 207
261 rmtfs_mem: memory@c6400000 { 208 rmtfs_mem: memory@c6400000 {
262 compatible = "qcom,rmt 209 compatible = "qcom,rmtfs-mem";
263 reg = <0 0xc6400000 0 210 reg = <0 0xc6400000 0 0x180000>;
264 no-map; 211 no-map;
265 212
266 qcom,client-id = <1>; 213 qcom,client-id = <1>;
267 }; 214 };
268 215
269 mba_mem: memory@c6700000 { 216 mba_mem: memory@c6700000 {
270 reg = <0 0xc6700000 0 217 reg = <0 0xc6700000 0 0x100000>;
271 no-map; 218 no-map;
272 }; 219 };
273 220
274 audio_mem: memory@c7000000 { 221 audio_mem: memory@c7000000 {
275 reg = <0 0xc7000000 0 222 reg = <0 0xc7000000 0 0x800000>;
276 no-map; 223 no-map;
277 }; 224 };
278 225
279 adsp_mem: memory@c9400000 { 226 adsp_mem: memory@c9400000 {
280 reg = <0 0xc9400000 0 227 reg = <0 0xc9400000 0 0x3f00000>;
281 no-map; 228 no-map;
282 }; 229 };
283 230
284 res_hyp_mem: reserved@6c00000 !! 231 reserved@6c00000 {
285 reg = <0 0x06c00000 0 232 reg = <0 0x06c00000 0 0x400000>;
286 no-map; 233 no-map;
287 }; 234 };
288 }; 235 };
289 236
>> 237 smd {
>> 238 compatible = "qcom,smd";
>> 239 rpm {
>> 240 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
>> 241 qcom,ipc = <&apcs 8 0>;
>> 242 qcom,smd-edge = <15>;
>> 243 qcom,remote-pid = <6>;
>> 244
>> 245 rpm_requests: rpm-requests {
>> 246 compatible = "qcom,rpm-msm8994";
>> 247 qcom,smd-channels = "rpm_requests";
>> 248
>> 249 rpmcc: rpmcc {
>> 250 compatible = "qcom,rpmcc-msm8994", "qcom,rpmcc";
>> 251 #clock-cells = <1>;
>> 252 };
>> 253
>> 254 rpmpd: power-controller {
>> 255 compatible = "qcom,msm8994-rpmpd";
>> 256 #power-domain-cells = <1>;
>> 257 operating-points-v2 = <&rpmpd_opp_table>;
>> 258
>> 259 rpmpd_opp_table: opp-table {
>> 260 compatible = "operating-points-v2";
>> 261
>> 262 rpmpd_opp_ret: opp1 {
>> 263 opp-level = <1>;
>> 264 };
>> 265 rpmpd_opp_svs_krait: opp2 {
>> 266 opp-level = <2>;
>> 267 };
>> 268 rpmpd_opp_svs_soc: opp3 {
>> 269 opp-level = <3>;
>> 270 };
>> 271 rpmpd_opp_nom: opp4 {
>> 272 opp-level = <4>;
>> 273 };
>> 274 rpmpd_opp_turbo: opp5 {
>> 275 opp-level = <5>;
>> 276 };
>> 277 rpmpd_opp_super_turbo: opp6 {
>> 278 opp-level = <6>;
>> 279 };
>> 280 };
>> 281 };
>> 282 };
>> 283 };
>> 284 };
>> 285
290 smem { 286 smem {
291 compatible = "qcom,smem"; 287 compatible = "qcom,smem";
292 memory-region = <&smem_mem>; 288 memory-region = <&smem_mem>;
293 qcom,rpm-msg-ram = <&rpm_msg_r 289 qcom,rpm-msg-ram = <&rpm_msg_ram>;
294 hwlocks = <&tcsr_mutex 3>; 290 hwlocks = <&tcsr_mutex 3>;
295 }; 291 };
296 292
297 smp2p-lpass { 293 smp2p-lpass {
298 compatible = "qcom,smp2p"; 294 compatible = "qcom,smp2p";
299 qcom,smem = <443>, <429>; 295 qcom,smem = <443>, <429>;
300 296
301 interrupts = <GIC_SPI 158 IRQ_ 297 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
302 298
303 mboxes = <&apcs 10>; !! 299 qcom,ipc = <&apcs 8 10>;
304 300
305 qcom,local-pid = <0>; 301 qcom,local-pid = <0>;
306 qcom,remote-pid = <2>; 302 qcom,remote-pid = <2>;
307 303
308 adsp_smp2p_out: master-kernel 304 adsp_smp2p_out: master-kernel {
309 qcom,entry-name = "mas 305 qcom,entry-name = "master-kernel";
310 #qcom,smem-state-cells 306 #qcom,smem-state-cells = <1>;
311 }; 307 };
312 308
313 adsp_smp2p_in: slave-kernel { 309 adsp_smp2p_in: slave-kernel {
314 qcom,entry-name = "sla 310 qcom,entry-name = "slave-kernel";
315 311
316 interrupt-controller; 312 interrupt-controller;
317 #interrupt-cells = <2> 313 #interrupt-cells = <2>;
318 }; 314 };
319 }; 315 };
320 316
321 smp2p-modem { 317 smp2p-modem {
322 compatible = "qcom,smp2p"; 318 compatible = "qcom,smp2p";
323 qcom,smem = <435>, <428>; 319 qcom,smem = <435>, <428>;
324 320
325 interrupt-parent = <&intc>; 321 interrupt-parent = <&intc>;
326 interrupts = <GIC_SPI 27 IRQ_T 322 interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>;
327 323
328 mboxes = <&apcs 14>; !! 324 qcom,ipc = <&apcs 8 14>;
329 325
330 qcom,local-pid = <0>; 326 qcom,local-pid = <0>;
331 qcom,remote-pid = <1>; 327 qcom,remote-pid = <1>;
332 328
333 modem_smp2p_out: master-kernel 329 modem_smp2p_out: master-kernel {
334 qcom,entry-name = "mas 330 qcom,entry-name = "master-kernel";
335 #qcom,smem-state-cells 331 #qcom,smem-state-cells = <1>;
336 }; 332 };
337 333
338 modem_smp2p_in: slave-kernel { 334 modem_smp2p_in: slave-kernel {
339 qcom,entry-name = "sla 335 qcom,entry-name = "slave-kernel";
340 336
341 interrupt-controller; 337 interrupt-controller;
342 #interrupt-cells = <2> 338 #interrupt-cells = <2>;
343 }; 339 };
344 }; 340 };
345 341
346 soc: soc@0 { !! 342 soc: soc {
>> 343
347 #address-cells = <1>; 344 #address-cells = <1>;
348 #size-cells = <1>; 345 #size-cells = <1>;
349 ranges = <0 0 0 0xffffffff>; 346 ranges = <0 0 0 0xffffffff>;
350 compatible = "simple-bus"; 347 compatible = "simple-bus";
351 348
352 intc: interrupt-controller@f90 349 intc: interrupt-controller@f9000000 {
353 compatible = "qcom,msm 350 compatible = "qcom,msm-qgic2";
354 interrupt-controller; 351 interrupt-controller;
355 #interrupt-cells = <3> 352 #interrupt-cells = <3>;
356 reg = <0xf9000000 0x10 353 reg = <0xf9000000 0x1000>,
357 <0xf9002000 0x10 354 <0xf9002000 0x1000>;
358 }; 355 };
359 356
360 apcs: mailbox@f900d000 { 357 apcs: mailbox@f900d000 {
361 compatible = "qcom,msm 358 compatible = "qcom,msm8994-apcs-kpss-global", "syscon";
362 reg = <0xf900d000 0x20 359 reg = <0xf900d000 0x2000>;
363 #mbox-cells = <1>; 360 #mbox-cells = <1>;
364 }; 361 };
365 362
366 watchdog@f9017000 { 363 watchdog@f9017000 {
367 compatible = "qcom,aps 364 compatible = "qcom,apss-wdt-msm8994", "qcom,kpss-wdt";
368 reg = <0xf9017000 0x10 365 reg = <0xf9017000 0x1000>;
369 interrupts = <GIC_SPI 366 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>,
370 <GIC_SPI 367 <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>;
371 clocks = <&sleep_clk>; 368 clocks = <&sleep_clk>;
372 timeout-sec = <10>; 369 timeout-sec = <10>;
373 }; 370 };
374 371
375 timer@f9020000 { 372 timer@f9020000 {
376 #address-cells = <1>; 373 #address-cells = <1>;
377 #size-cells = <1>; 374 #size-cells = <1>;
378 ranges; 375 ranges;
379 compatible = "arm,armv 376 compatible = "arm,armv7-timer-mem";
380 reg = <0xf9020000 0x10 377 reg = <0xf9020000 0x1000>;
381 378
382 frame@f9021000 { 379 frame@f9021000 {
383 frame-number = 380 frame-number = <0>;
384 interrupts = < 381 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
385 < 382 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
386 reg = <0xf9021 383 reg = <0xf9021000 0x1000>,
387 <0xf9022 384 <0xf9022000 0x1000>;
388 }; 385 };
389 386
390 frame@f9023000 { 387 frame@f9023000 {
391 frame-number = 388 frame-number = <1>;
392 interrupts = < 389 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
393 reg = <0xf9023 390 reg = <0xf9023000 0x1000>;
394 status = "disa 391 status = "disabled";
395 }; 392 };
396 393
397 frame@f9024000 { 394 frame@f9024000 {
398 frame-number = 395 frame-number = <2>;
399 interrupts = < 396 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
400 reg = <0xf9024 397 reg = <0xf9024000 0x1000>;
401 status = "disa 398 status = "disabled";
402 }; 399 };
403 400
404 frame@f9025000 { 401 frame@f9025000 {
405 frame-number = 402 frame-number = <3>;
406 interrupts = < 403 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
407 reg = <0xf9025 404 reg = <0xf9025000 0x1000>;
408 status = "disa 405 status = "disabled";
409 }; 406 };
410 407
411 frame@f9026000 { 408 frame@f9026000 {
412 frame-number = 409 frame-number = <4>;
413 interrupts = < 410 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
414 reg = <0xf9026 411 reg = <0xf9026000 0x1000>;
415 status = "disa 412 status = "disabled";
416 }; 413 };
417 414
418 frame@f9027000 { 415 frame@f9027000 {
419 frame-number = 416 frame-number = <5>;
420 interrupts = < 417 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
421 reg = <0xf9027 418 reg = <0xf9027000 0x1000>;
422 status = "disa 419 status = "disabled";
423 }; 420 };
424 421
425 frame@f9028000 { 422 frame@f9028000 {
426 frame-number = 423 frame-number = <6>;
427 interrupts = < 424 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
428 reg = <0xf9028 425 reg = <0xf9028000 0x1000>;
429 status = "disa 426 status = "disabled";
430 }; 427 };
431 }; 428 };
432 429
433 usb3: usb@f92f8800 { 430 usb3: usb@f92f8800 {
434 compatible = "qcom,msm 431 compatible = "qcom,msm8994-dwc3", "qcom,dwc3";
435 reg = <0xf92f8800 0x40 432 reg = <0xf92f8800 0x400>;
436 #address-cells = <1>; 433 #address-cells = <1>;
437 #size-cells = <1>; 434 #size-cells = <1>;
438 ranges; 435 ranges;
439 436
440 clocks = <&gcc GCC_USB 437 clocks = <&gcc GCC_USB30_MASTER_CLK>,
441 <&gcc GCC_SYS 438 <&gcc GCC_SYS_NOC_USB3_AXI_CLK>,
442 <&gcc GCC_USB 439 <&gcc GCC_USB30_SLEEP_CLK>,
443 <&gcc GCC_USB 440 <&gcc GCC_USB30_MOCK_UTMI_CLK>;
444 clock-names = "core", 441 clock-names = "core",
445 "iface", 442 "iface",
446 "sleep", 443 "sleep",
447 "mock_ut 444 "mock_utmi";
448 445
449 assigned-clocks = <&gc 446 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
450 <&gc 447 <&gcc GCC_USB30_MASTER_CLK>;
451 assigned-clock-rates = 448 assigned-clock-rates = <19200000>, <120000000>;
452 449
453 power-domains = <&gcc 450 power-domains = <&gcc USB30_GDSC>;
454 qcom,select-utmi-as-pi 451 qcom,select-utmi-as-pipe-clk;
455 452
456 usb@f9200000 { 453 usb@f9200000 {
457 compatible = " 454 compatible = "snps,dwc3";
458 reg = <0xf9200 455 reg = <0xf9200000 0xcc00>;
459 interrupts = < !! 456 interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>;
460 snps,dis_u2_su 457 snps,dis_u2_susphy_quirk;
461 snps,dis_enbls 458 snps,dis_enblslpm_quirk;
462 maximum-speed 459 maximum-speed = "high-speed";
463 dr_mode = "per 460 dr_mode = "peripheral";
464 }; 461 };
465 }; 462 };
466 463
467 sdhc1: mmc@f9824900 { 464 sdhc1: mmc@f9824900 {
468 compatible = "qcom,msm 465 compatible = "qcom,msm8994-sdhci", "qcom,sdhci-msm-v4";
469 reg = <0xf9824900 0x1a 466 reg = <0xf9824900 0x1a0>, <0xf9824000 0x800>;
470 reg-names = "hc", "cor 467 reg-names = "hc", "core";
471 468
472 interrupts = <GIC_SPI 469 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
473 <GIC_SPI 470 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
474 interrupt-names = "hc_ 471 interrupt-names = "hc_irq", "pwr_irq";
475 472
476 clocks = <&gcc GCC_SDC 473 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
477 <&gcc GCC_SDC 474 <&gcc GCC_SDCC1_APPS_CLK>,
478 <&xo_board>; 475 <&xo_board>;
479 clock-names = "iface", 476 clock-names = "iface", "core", "xo";
480 477
481 pinctrl-names = "defau 478 pinctrl-names = "default", "sleep";
482 pinctrl-0 = <&sdc1_clk 479 pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>;
483 pinctrl-1 = <&sdc1_clk 480 pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>;
484 481
485 bus-width = <8>; 482 bus-width = <8>;
486 non-removable; 483 non-removable;
487 status = "disabled"; 484 status = "disabled";
488 }; 485 };
489 486
490 sdhc2: mmc@f98a4900 { 487 sdhc2: mmc@f98a4900 {
491 compatible = "qcom,msm 488 compatible = "qcom,msm8994-sdhci", "qcom,sdhci-msm-v4";
492 reg = <0xf98a4900 0x11 489 reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
493 reg-names = "hc", "cor 490 reg-names = "hc", "core";
494 491
495 interrupts = <GIC_SPI 492 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
496 <GIC_SPI 221 I 493 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
497 interrupt-names = "hc_ 494 interrupt-names = "hc_irq", "pwr_irq";
498 495
499 clocks = <&gcc GCC_SDC 496 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
500 <&gcc GCC_SDC 497 <&gcc GCC_SDCC2_APPS_CLK>,
501 <&xo_board>; 498 <&xo_board>;
502 clock-names = "iface", 499 clock-names = "iface", "core", "xo";
503 500
504 pinctrl-names = "defau 501 pinctrl-names = "default", "sleep";
505 pinctrl-0 = <&sdc2_clk 502 pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>;
506 pinctrl-1 = <&sdc2_clk 503 pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>;
507 504
508 cd-gpios = <&tlmm 100 505 cd-gpios = <&tlmm 100 GPIO_ACTIVE_HIGH>;
509 bus-width = <4>; 506 bus-width = <4>;
510 status = "disabled"; 507 status = "disabled";
511 }; 508 };
512 509
513 blsp1_dma: dma-controller@f990 510 blsp1_dma: dma-controller@f9904000 {
514 compatible = "qcom,bam 511 compatible = "qcom,bam-v1.7.0";
515 reg = <0xf9904000 0x19 512 reg = <0xf9904000 0x19000>;
516 interrupts = <GIC_SPI 513 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
517 clocks = <&gcc GCC_BLS 514 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
518 clock-names = "bam_clk 515 clock-names = "bam_clk";
519 #dma-cells = <1>; 516 #dma-cells = <1>;
520 qcom,ee = <0>; 517 qcom,ee = <0>;
521 qcom,controlled-remote 518 qcom,controlled-remotely;
522 num-channels = <24>; 519 num-channels = <24>;
523 qcom,num-ees = <4>; 520 qcom,num-ees = <4>;
524 }; 521 };
525 522
526 blsp1_uart2: serial@f991e000 { 523 blsp1_uart2: serial@f991e000 {
527 compatible = "qcom,msm 524 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
528 reg = <0xf991e000 0x10 525 reg = <0xf991e000 0x1000>;
529 interrupts = <GIC_SPI 526 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
530 clock-names = "core", 527 clock-names = "core", "iface";
531 clocks = <&gcc GCC_BLS 528 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
532 <&gcc GCC_BLS 529 <&gcc GCC_BLSP1_AHB_CLK>;
533 pinctrl-names = "defau 530 pinctrl-names = "default", "sleep";
534 pinctrl-0 = <&blsp1_ua 531 pinctrl-0 = <&blsp1_uart2_default>;
535 pinctrl-1 = <&blsp1_ua 532 pinctrl-1 = <&blsp1_uart2_sleep>;
536 status = "disabled"; 533 status = "disabled";
537 }; 534 };
538 535
539 blsp1_i2c1: i2c@f9923000 { 536 blsp1_i2c1: i2c@f9923000 {
540 compatible = "qcom,i2c 537 compatible = "qcom,i2c-qup-v2.2.1";
541 reg = <0xf9923000 0x50 538 reg = <0xf9923000 0x500>;
542 interrupts = <GIC_SPI 539 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
543 clocks = <&gcc GCC_BLS 540 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
544 <&gcc GCC_BLS 541 <&gcc GCC_BLSP1_AHB_CLK>;
545 clock-names = "core", 542 clock-names = "core", "iface";
546 clock-frequency = <400 543 clock-frequency = <400000>;
547 dmas = <&blsp1_dma 12> 544 dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
548 dma-names = "tx", "rx" 545 dma-names = "tx", "rx";
549 pinctrl-names = "defau 546 pinctrl-names = "default", "sleep";
550 pinctrl-0 = <&i2c1_def 547 pinctrl-0 = <&i2c1_default>;
551 pinctrl-1 = <&i2c1_sle 548 pinctrl-1 = <&i2c1_sleep>;
552 #address-cells = <1>; 549 #address-cells = <1>;
553 #size-cells = <0>; 550 #size-cells = <0>;
554 status = "disabled"; 551 status = "disabled";
555 }; 552 };
556 553
557 blsp1_spi1: spi@f9923000 { 554 blsp1_spi1: spi@f9923000 {
558 compatible = "qcom,spi 555 compatible = "qcom,spi-qup-v2.2.1";
559 reg = <0xf9923000 0x50 556 reg = <0xf9923000 0x500>;
560 interrupts = <GIC_SPI 557 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
561 clocks = <&gcc GCC_BLS 558 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
562 <&gcc GCC_BLS 559 <&gcc GCC_BLSP1_AHB_CLK>;
563 clock-names = "core", 560 clock-names = "core", "iface";
>> 561 spi-max-frequency = <19200000>;
564 dmas = <&blsp1_dma 12> 562 dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
565 dma-names = "tx", "rx" 563 dma-names = "tx", "rx";
566 pinctrl-names = "defau 564 pinctrl-names = "default", "sleep";
567 pinctrl-0 = <&blsp1_sp 565 pinctrl-0 = <&blsp1_spi1_default>;
568 pinctrl-1 = <&blsp1_sp 566 pinctrl-1 = <&blsp1_spi1_sleep>;
569 #address-cells = <1>; 567 #address-cells = <1>;
570 #size-cells = <0>; 568 #size-cells = <0>;
571 status = "disabled"; 569 status = "disabled";
572 }; 570 };
573 571
574 blsp1_i2c2: i2c@f9924000 { 572 blsp1_i2c2: i2c@f9924000 {
575 compatible = "qcom,i2c 573 compatible = "qcom,i2c-qup-v2.2.1";
576 reg = <0xf9924000 0x50 574 reg = <0xf9924000 0x500>;
577 interrupts = <GIC_SPI 575 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
578 clocks = <&gcc GCC_BLS 576 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
579 <&gcc GCC_BLS 577 <&gcc GCC_BLSP1_AHB_CLK>;
580 clock-names = "core", 578 clock-names = "core", "iface";
581 clock-frequency = <400 579 clock-frequency = <400000>;
582 dmas = <&blsp1_dma 14> 580 dmas = <&blsp1_dma 14>, <&blsp1_dma 15>;
583 dma-names = "tx", "rx" 581 dma-names = "tx", "rx";
584 pinctrl-names = "defau 582 pinctrl-names = "default", "sleep";
585 pinctrl-0 = <&i2c2_def 583 pinctrl-0 = <&i2c2_default>;
586 pinctrl-1 = <&i2c2_sle 584 pinctrl-1 = <&i2c2_sleep>;
587 #address-cells = <1>; 585 #address-cells = <1>;
588 #size-cells = <0>; 586 #size-cells = <0>;
589 status = "disabled"; 587 status = "disabled";
590 }; 588 };
591 589
592 /* I2C3 doesn't exist */ 590 /* I2C3 doesn't exist */
593 591
594 blsp1_i2c4: i2c@f9926000 { 592 blsp1_i2c4: i2c@f9926000 {
595 compatible = "qcom,i2c 593 compatible = "qcom,i2c-qup-v2.2.1";
596 reg = <0xf9926000 0x50 594 reg = <0xf9926000 0x500>;
597 interrupts = <GIC_SPI 595 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
598 clocks = <&gcc GCC_BLS 596 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
599 <&gcc GCC_BLS 597 <&gcc GCC_BLSP1_AHB_CLK>;
600 clock-names = "core", 598 clock-names = "core", "iface";
601 clock-frequency = <400 599 clock-frequency = <400000>;
602 dmas = <&blsp1_dma 18> 600 dmas = <&blsp1_dma 18>, <&blsp1_dma 19>;
603 dma-names = "tx", "rx" 601 dma-names = "tx", "rx";
604 pinctrl-names = "defau 602 pinctrl-names = "default", "sleep";
605 pinctrl-0 = <&i2c4_def 603 pinctrl-0 = <&i2c4_default>;
606 pinctrl-1 = <&i2c4_sle 604 pinctrl-1 = <&i2c4_sleep>;
607 #address-cells = <1>; 605 #address-cells = <1>;
608 #size-cells = <0>; 606 #size-cells = <0>;
609 status = "disabled"; 607 status = "disabled";
610 }; 608 };
611 609
612 blsp1_i2c5: i2c@f9927000 { 610 blsp1_i2c5: i2c@f9927000 {
613 compatible = "qcom,i2c 611 compatible = "qcom,i2c-qup-v2.2.1";
614 reg = <0xf9927000 0x50 612 reg = <0xf9927000 0x500>;
615 interrupts = <GIC_SPI 613 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
616 clocks = <&gcc GCC_BLS 614 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
617 <&gcc GCC_BLS 615 <&gcc GCC_BLSP1_AHB_CLK>;
618 clock-names = "core", 616 clock-names = "core", "iface";
619 clock-frequency = <400 617 clock-frequency = <400000>;
620 dmas = <&blsp2_dma 20> 618 dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
621 dma-names = "tx", "rx" 619 dma-names = "tx", "rx";
622 pinctrl-names = "defau 620 pinctrl-names = "default", "sleep";
623 pinctrl-0 = <&i2c5_def 621 pinctrl-0 = <&i2c5_default>;
624 pinctrl-1 = <&i2c5_sle 622 pinctrl-1 = <&i2c5_sleep>;
625 #address-cells = <1>; 623 #address-cells = <1>;
626 #size-cells = <0>; 624 #size-cells = <0>;
627 status = "disabled"; 625 status = "disabled";
628 }; 626 };
629 627
630 blsp1_i2c6: i2c@f9928000 { 628 blsp1_i2c6: i2c@f9928000 {
631 compatible = "qcom,i2c 629 compatible = "qcom,i2c-qup-v2.2.1";
632 reg = <0xf9928000 0x50 630 reg = <0xf9928000 0x500>;
633 interrupts = <GIC_SPI 631 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
634 clocks = <&gcc GCC_BLS 632 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
635 <&gcc GCC_BLS 633 <&gcc GCC_BLSP1_AHB_CLK>;
636 clock-names = "core", 634 clock-names = "core", "iface";
637 clock-frequency = <400 635 clock-frequency = <400000>;
638 dmas = <&blsp1_dma 22> 636 dmas = <&blsp1_dma 22>, <&blsp1_dma 23>;
639 dma-names = "tx", "rx" 637 dma-names = "tx", "rx";
640 pinctrl-names = "defau 638 pinctrl-names = "default", "sleep";
641 pinctrl-0 = <&i2c6_def 639 pinctrl-0 = <&i2c6_default>;
642 pinctrl-1 = <&i2c6_sle 640 pinctrl-1 = <&i2c6_sleep>;
643 #address-cells = <1>; 641 #address-cells = <1>;
644 #size-cells = <0>; 642 #size-cells = <0>;
645 status = "disabled"; 643 status = "disabled";
646 }; 644 };
647 645
648 blsp2_dma: dma-controller@f994 646 blsp2_dma: dma-controller@f9944000 {
649 compatible = "qcom,bam 647 compatible = "qcom,bam-v1.7.0";
650 reg = <0xf9944000 0x19 648 reg = <0xf9944000 0x19000>;
651 interrupts = <GIC_SPI 649 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
652 clocks = <&gcc GCC_BLS 650 clocks = <&gcc GCC_BLSP2_AHB_CLK>;
653 clock-names = "bam_clk 651 clock-names = "bam_clk";
654 #dma-cells = <1>; 652 #dma-cells = <1>;
655 qcom,ee = <0>; 653 qcom,ee = <0>;
656 qcom,controlled-remote 654 qcom,controlled-remotely;
657 num-channels = <24>; 655 num-channels = <24>;
658 qcom,num-ees = <4>; 656 qcom,num-ees = <4>;
659 }; 657 };
660 658
661 blsp2_uart2: serial@f995e000 { 659 blsp2_uart2: serial@f995e000 {
662 compatible = "qcom,msm 660 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
663 reg = <0xf995e000 0x10 661 reg = <0xf995e000 0x1000>;
664 interrupts = <GIC_SPI 662 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
665 clock-names = "core", 663 clock-names = "core", "iface";
666 clocks = <&gcc GCC_BLS 664 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
667 <&gcc 665 <&gcc GCC_BLSP2_AHB_CLK>;
668 dmas = <&blsp2_dma 2>, 666 dmas = <&blsp2_dma 2>, <&blsp2_dma 3>;
669 dma-names = "tx", "rx" 667 dma-names = "tx", "rx";
670 pinctrl-names = "defau 668 pinctrl-names = "default", "sleep";
671 pinctrl-0 = <&blsp2_ua 669 pinctrl-0 = <&blsp2_uart2_default>;
672 pinctrl-1 = <&blsp2_ua 670 pinctrl-1 = <&blsp2_uart2_sleep>;
673 status = "disabled"; 671 status = "disabled";
674 }; 672 };
675 673
676 blsp2_i2c1: i2c@f9963000 { 674 blsp2_i2c1: i2c@f9963000 {
677 compatible = "qcom,i2c 675 compatible = "qcom,i2c-qup-v2.2.1";
678 reg = <0xf9963000 0x50 676 reg = <0xf9963000 0x500>;
679 interrupts = <GIC_SPI 677 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
680 clocks = <&gcc GCC_BLS 678 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
681 <&gcc GCC_BLS 679 <&gcc GCC_BLSP2_AHB_CLK>;
682 clock-names = "core", 680 clock-names = "core", "iface";
683 clock-frequency = <400 681 clock-frequency = <400000>;
684 dmas = <&blsp2_dma 12> 682 dmas = <&blsp2_dma 12>, <&blsp2_dma 13>;
685 dma-names = "tx", "rx" 683 dma-names = "tx", "rx";
686 pinctrl-names = "defau 684 pinctrl-names = "default", "sleep";
687 pinctrl-0 = <&i2c7_def 685 pinctrl-0 = <&i2c7_default>;
688 pinctrl-1 = <&i2c7_sle 686 pinctrl-1 = <&i2c7_sleep>;
689 #address-cells = <1>; 687 #address-cells = <1>;
690 #size-cells = <0>; 688 #size-cells = <0>;
691 status = "disabled"; 689 status = "disabled";
692 }; 690 };
693 691
694 blsp2_spi4: spi@f9966000 { 692 blsp2_spi4: spi@f9966000 {
695 compatible = "qcom,spi 693 compatible = "qcom,spi-qup-v2.2.1";
696 reg = <0xf9966000 0x50 694 reg = <0xf9966000 0x500>;
697 interrupts = <GIC_SPI 695 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
698 clocks = <&gcc GCC_BLS 696 clocks = <&gcc GCC_BLSP2_QUP4_SPI_APPS_CLK>,
699 <&gcc GCC_BLS 697 <&gcc GCC_BLSP2_AHB_CLK>;
700 clock-names = "core", 698 clock-names = "core", "iface";
>> 699 spi-max-frequency = <19200000>;
701 dmas = <&blsp2_dma 18> 700 dmas = <&blsp2_dma 18>, <&blsp2_dma 19>;
702 dma-names = "tx", "rx" 701 dma-names = "tx", "rx";
703 pinctrl-names = "defau 702 pinctrl-names = "default", "sleep";
704 pinctrl-0 = <&blsp2_sp 703 pinctrl-0 = <&blsp2_spi10_default>;
705 pinctrl-1 = <&blsp2_sp 704 pinctrl-1 = <&blsp2_spi10_sleep>;
706 #address-cells = <1>; 705 #address-cells = <1>;
707 #size-cells = <0>; 706 #size-cells = <0>;
708 status = "disabled"; 707 status = "disabled";
709 }; 708 };
710 709
711 blsp2_i2c5: i2c@f9967000 { 710 blsp2_i2c5: i2c@f9967000 {
712 compatible = "qcom,i2c 711 compatible = "qcom,i2c-qup-v2.2.1";
713 reg = <0xf9967000 0x50 712 reg = <0xf9967000 0x500>;
714 interrupts = <GIC_SPI 713 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
715 clocks = <&gcc GCC_BLS 714 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>,
716 <&gcc GCC_BLS 715 <&gcc GCC_BLSP2_AHB_CLK>;
717 clock-names = "core", 716 clock-names = "core", "iface";
718 clock-frequency = <355 717 clock-frequency = <355000>;
719 dmas = <&blsp2_dma 20> 718 dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
720 dma-names = "tx", "rx" 719 dma-names = "tx", "rx";
721 pinctrl-names = "defau 720 pinctrl-names = "default", "sleep";
722 pinctrl-0 = <&i2c11_de 721 pinctrl-0 = <&i2c11_default>;
723 pinctrl-1 = <&i2c11_sl 722 pinctrl-1 = <&i2c11_sleep>;
724 #address-cells = <1>; 723 #address-cells = <1>;
725 #size-cells = <0>; 724 #size-cells = <0>;
726 status = "disabled"; 725 status = "disabled";
727 }; 726 };
728 727
729 gcc: clock-controller@fc400000 728 gcc: clock-controller@fc400000 {
730 compatible = "qcom,gcc 729 compatible = "qcom,gcc-msm8994";
731 #clock-cells = <1>; 730 #clock-cells = <1>;
732 #reset-cells = <1>; 731 #reset-cells = <1>;
733 #power-domain-cells = 732 #power-domain-cells = <1>;
734 reg = <0xfc400000 0x20 733 reg = <0xfc400000 0x2000>;
735 734
736 clock-names = "xo", "s 735 clock-names = "xo", "sleep";
737 clocks = <&xo_board>, 736 clocks = <&xo_board>, <&sleep_clk>;
738 }; 737 };
739 738
740 rpm_msg_ram: sram@fc428000 { 739 rpm_msg_ram: sram@fc428000 {
741 compatible = "qcom,rpm 740 compatible = "qcom,rpm-msg-ram";
742 reg = <0xfc428000 0x40 741 reg = <0xfc428000 0x4000>;
743 }; 742 };
744 743
745 restart@fc4ab000 { 744 restart@fc4ab000 {
746 compatible = "qcom,psh 745 compatible = "qcom,pshold";
747 reg = <0xfc4ab000 0x4> 746 reg = <0xfc4ab000 0x4>;
748 }; 747 };
749 748
750 spmi_bus: spmi@fc4cf000 { 749 spmi_bus: spmi@fc4cf000 {
751 compatible = "qcom,spm 750 compatible = "qcom,spmi-pmic-arb";
752 reg = <0xfc4cf000 0x10 751 reg = <0xfc4cf000 0x1000>,
753 <0xfc4cb000 0x10 752 <0xfc4cb000 0x1000>,
754 <0xfc4ca000 0x10 753 <0xfc4ca000 0x1000>;
755 reg-names = "core", "i 754 reg-names = "core", "intr", "cnfg";
756 interrupt-names = "per 755 interrupt-names = "periph_irq";
757 interrupts = <GIC_SPI 756 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
758 qcom,ee = <0>; 757 qcom,ee = <0>;
759 qcom,channel = <0>; 758 qcom,channel = <0>;
760 #address-cells = <2>; 759 #address-cells = <2>;
761 #size-cells = <0>; 760 #size-cells = <0>;
762 interrupt-controller; 761 interrupt-controller;
763 #interrupt-cells = <4> 762 #interrupt-cells = <4>;
764 }; 763 };
765 764
766 tcsr_mutex: hwlock@fd484000 { 765 tcsr_mutex: hwlock@fd484000 {
767 compatible = "qcom,msm 766 compatible = "qcom,msm8994-tcsr-mutex", "qcom,tcsr-mutex";
768 reg = <0xfd484000 0x10 767 reg = <0xfd484000 0x1000>;
769 #hwlock-cells = <1>; 768 #hwlock-cells = <1>;
770 }; 769 };
771 770
772 tlmm: pinctrl@fd510000 { 771 tlmm: pinctrl@fd510000 {
773 compatible = "qcom,msm 772 compatible = "qcom,msm8994-pinctrl";
774 reg = <0xfd510000 0x40 773 reg = <0xfd510000 0x4000>;
775 interrupts = <GIC_SPI 774 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
776 gpio-controller; 775 gpio-controller;
777 gpio-ranges = <&tlmm 0 776 gpio-ranges = <&tlmm 0 0 146>;
778 #gpio-cells = <2>; 777 #gpio-cells = <2>;
779 interrupt-controller; 778 interrupt-controller;
780 #interrupt-cells = <2> 779 #interrupt-cells = <2>;
781 780
782 blsp1_uart2_default: b !! 781 blsp1_uart2_default: blsp1-uart2-default {
783 pins = "gpio4" <<
784 function = "bl 782 function = "blsp_uart2";
>> 783 pins = "gpio4", "gpio5";
785 drive-strength 784 drive-strength = <16>;
786 bias-disable; 785 bias-disable;
787 }; 786 };
788 787
789 blsp1_uart2_sleep: bls !! 788 blsp1_uart2_sleep: blsp1-uart2-sleep {
790 pins = "gpio4" <<
791 function = "gp 789 function = "gpio";
>> 790 pins = "gpio4", "gpio5";
792 drive-strength 791 drive-strength = <2>;
793 bias-pull-down 792 bias-pull-down;
794 }; 793 };
795 794
796 blsp2_uart2_default: b !! 795 blsp2_uart2_default: blsp2-uart2-default {
797 pins = "gpio45 <<
798 function = "bl 796 function = "blsp_uart8";
>> 797 pins = "gpio45", "gpio46",
>> 798 "gpio47", "gpio48";
799 drive-strength 799 drive-strength = <16>;
800 bias-disable; 800 bias-disable;
801 }; 801 };
802 802
803 blsp2_uart2_sleep: bls !! 803 blsp2_uart2_sleep: blsp2-uart2-sleep {
804 pins = "gpio45 <<
805 function = "gp 804 function = "gpio";
>> 805 pins = "gpio45", "gpio46",
>> 806 "gpio47", "gpio48";
806 drive-strength 807 drive-strength = <2>;
807 bias-disable; 808 bias-disable;
808 }; 809 };
809 810
810 i2c1_default: i2c1-def !! 811 i2c1_default: i2c1-default {
811 pins = "gpio2" <<
812 function = "bl 812 function = "blsp_i2c1";
>> 813 pins = "gpio2", "gpio3";
813 drive-strength 814 drive-strength = <2>;
814 bias-disable; 815 bias-disable;
815 }; 816 };
816 817
817 i2c1_sleep: i2c1-sleep !! 818 i2c1_sleep: i2c1-sleep {
818 pins = "gpio2" <<
819 function = "gp 819 function = "gpio";
>> 820 pins = "gpio2", "gpio3";
820 drive-strength 821 drive-strength = <2>;
821 bias-disable; 822 bias-disable;
822 }; 823 };
823 824
824 i2c2_default: i2c2-def !! 825 i2c2_default: i2c2-default {
825 pins = "gpio6" <<
826 function = "bl 826 function = "blsp_i2c2";
>> 827 pins = "gpio6", "gpio7";
827 drive-strength 828 drive-strength = <2>;
828 bias-disable; 829 bias-disable;
829 }; 830 };
830 831
831 i2c2_sleep: i2c2-sleep !! 832 i2c2_sleep: i2c2-sleep {
832 pins = "gpio6" <<
833 function = "gp 833 function = "gpio";
>> 834 pins = "gpio6", "gpio7";
834 drive-strength 835 drive-strength = <2>;
835 bias-disable; 836 bias-disable;
836 }; 837 };
837 838
838 i2c4_default: i2c4-def !! 839 i2c4_default: i2c4-default {
839 pins = "gpio19 <<
840 function = "bl 840 function = "blsp_i2c4";
>> 841 pins = "gpio19", "gpio20";
841 drive-strength 842 drive-strength = <2>;
842 bias-disable; 843 bias-disable;
843 }; 844 };
844 845
845 i2c4_sleep: i2c4-sleep !! 846 i2c4_sleep: i2c4-sleep {
846 pins = "gpio19 <<
847 function = "gp 847 function = "gpio";
>> 848 pins = "gpio19", "gpio20";
848 drive-strength 849 drive-strength = <2>;
849 bias-pull-down 850 bias-pull-down;
>> 851 input-enable;
850 }; 852 };
851 853
852 i2c5_default: i2c5-def !! 854 i2c5_default: i2c5-default {
853 pins = "gpio23 <<
854 function = "bl 855 function = "blsp_i2c5";
>> 856 pins = "gpio23", "gpio24";
855 drive-strength 857 drive-strength = <2>;
856 bias-disable; 858 bias-disable;
857 }; 859 };
858 860
859 i2c5_sleep: i2c5-sleep !! 861 i2c5_sleep: i2c5-sleep {
860 pins = "gpio23 <<
861 function = "gp 862 function = "gpio";
>> 863 pins = "gpio23", "gpio24";
862 drive-strength 864 drive-strength = <2>;
863 bias-disable; 865 bias-disable;
864 }; 866 };
865 867
866 i2c6_default: i2c6-def !! 868 i2c6_default: i2c6-default {
867 pins = "gpio28 <<
868 function = "bl 869 function = "blsp_i2c6";
>> 870 pins = "gpio28", "gpio27";
869 drive-strength 871 drive-strength = <2>;
870 bias-disable; 872 bias-disable;
871 }; 873 };
872 874
873 i2c6_sleep: i2c6-sleep !! 875 i2c6_sleep: i2c6-sleep {
874 pins = "gpio28 <<
875 function = "gp 876 function = "gpio";
>> 877 pins = "gpio28", "gpio27";
876 drive-strength 878 drive-strength = <2>;
877 bias-disable; 879 bias-disable;
878 }; 880 };
879 881
880 i2c7_default: i2c7-def !! 882 i2c7_default: i2c7-default {
881 pins = "gpio44 <<
882 function = "bl 883 function = "blsp_i2c7";
>> 884 pins = "gpio44", "gpio43";
883 drive-strength 885 drive-strength = <2>;
884 bias-disable; 886 bias-disable;
885 }; 887 };
886 888
887 i2c7_sleep: i2c7-sleep !! 889 i2c7_sleep: i2c7-sleep {
888 pins = "gpio44 <<
889 function = "gp 890 function = "gpio";
>> 891 pins = "gpio44", "gpio43";
890 drive-strength 892 drive-strength = <2>;
891 bias-disable; 893 bias-disable;
892 }; 894 };
893 895
894 blsp2_spi10_default: b !! 896 blsp2_spi10_default: blsp2-spi10-default {
895 default-pins { !! 897 default {
896 pins = <<
897 functi 898 function = "blsp_spi10";
>> 899 pins = "gpio53", "gpio54", "gpio55";
898 drive- 900 drive-strength = <10>;
899 bias-p 901 bias-pull-down;
900 }; 902 };
901 !! 903 cs {
902 cs-pins { <<
903 pins = <<
904 functi 904 function = "gpio";
>> 905 pins = "gpio55";
905 drive- 906 drive-strength = <2>;
906 bias-d 907 bias-disable;
907 }; 908 };
908 }; 909 };
909 910
910 blsp2_spi10_sleep: bls !! 911 blsp2_spi10_sleep: blsp2-spi10-sleep {
911 pins = "gpio53 912 pins = "gpio53", "gpio54", "gpio55";
912 function = "gp <<
913 drive-strength 913 drive-strength = <2>;
914 bias-disable; 914 bias-disable;
915 }; 915 };
916 916
917 i2c11_default: i2c11-d !! 917 i2c11_default: i2c11-default {
918 pins = "gpio83 <<
919 function = "bl 918 function = "blsp_i2c11";
>> 919 pins = "gpio83", "gpio84";
920 drive-strength 920 drive-strength = <2>;
921 bias-disable; 921 bias-disable;
922 }; 922 };
923 923
924 i2c11_sleep: i2c11-sle !! 924 i2c11_sleep: i2c11-sleep {
925 pins = "gpio83 <<
926 function = "gp 925 function = "gpio";
>> 926 pins = "gpio83", "gpio84";
927 drive-strength 927 drive-strength = <2>;
928 bias-disable; 928 bias-disable;
929 }; 929 };
930 930
931 blsp1_spi1_default: bl !! 931 blsp1_spi1_default: blsp1-spi1-default {
932 default-pins { !! 932 default {
933 pins = <<
934 functi 933 function = "blsp_spi1";
>> 934 pins = "gpio0", "gpio1", "gpio3";
935 drive- 935 drive-strength = <10>;
936 bias-p 936 bias-pull-down;
937 }; 937 };
938 !! 938 cs {
939 cs-pins { <<
940 pins = <<
941 functi 939 function = "gpio";
>> 940 pins = "gpio8";
942 drive- 941 drive-strength = <2>;
943 bias-d 942 bias-disable;
944 }; 943 };
945 }; 944 };
946 945
947 blsp1_spi1_sleep: blsp !! 946 blsp1_spi1_sleep: blsp1-spi1-sleep {
948 pins = "gpio0" 947 pins = "gpio0", "gpio1", "gpio3";
949 function = "gp <<
950 drive-strength 948 drive-strength = <2>;
951 bias-disable; 949 bias-disable;
952 }; 950 };
953 951
954 sdc1_clk_on: clk-on-st !! 952 sdc1_clk_on: clk-on {
955 pins = "sdc1_c 953 pins = "sdc1_clk";
956 bias-disable; 954 bias-disable;
957 drive-strength 955 drive-strength = <16>;
958 }; 956 };
959 957
960 sdc1_clk_off: clk-off- !! 958 sdc1_clk_off: clk-off {
961 pins = "sdc1_c 959 pins = "sdc1_clk";
962 bias-disable; 960 bias-disable;
963 drive-strength 961 drive-strength = <2>;
964 }; 962 };
965 963
966 sdc1_cmd_on: cmd-on-st !! 964 sdc1_cmd_on: cmd-on {
967 pins = "sdc1_c 965 pins = "sdc1_cmd";
968 bias-pull-up; 966 bias-pull-up;
969 drive-strength 967 drive-strength = <8>;
970 }; 968 };
971 969
972 sdc1_cmd_off: cmd-off- !! 970 sdc1_cmd_off: cmd-off {
973 pins = "sdc1_c 971 pins = "sdc1_cmd";
974 bias-pull-up; 972 bias-pull-up;
975 drive-strength 973 drive-strength = <2>;
976 }; 974 };
977 975
978 sdc1_data_on: data-on- !! 976 sdc1_data_on: data-on {
979 pins = "sdc1_d 977 pins = "sdc1_data";
980 bias-pull-up; 978 bias-pull-up;
981 drive-strength 979 drive-strength = <8>;
982 }; 980 };
983 981
984 sdc1_data_off: data-of !! 982 sdc1_data_off: data-off {
985 pins = "sdc1_d 983 pins = "sdc1_data";
986 bias-pull-up; 984 bias-pull-up;
987 drive-strength 985 drive-strength = <2>;
988 }; 986 };
989 987
990 sdc1_rclk_on: rclk-on- !! 988 sdc1_rclk_on: rclk-on {
991 pins = "sdc1_r 989 pins = "sdc1_rclk";
992 bias-pull-down 990 bias-pull-down;
993 }; 991 };
994 992
995 sdc1_rclk_off: rclk-of !! 993 sdc1_rclk_off: rclk-off {
996 pins = "sdc1_r 994 pins = "sdc1_rclk";
997 bias-pull-down 995 bias-pull-down;
998 }; 996 };
999 997
1000 sdc2_clk_on: sdc2-clk !! 998 sdc2_clk_on: sdc2-clk-on {
1001 pins = "sdc2_ 999 pins = "sdc2_clk";
1002 bias-disable; 1000 bias-disable;
1003 drive-strengt 1001 drive-strength = <10>;
1004 }; 1002 };
1005 1003
1006 sdc2_clk_off: sdc2-cl !! 1004 sdc2_clk_off: sdc2-clk-off {
1007 pins = "sdc2_ 1005 pins = "sdc2_clk";
1008 bias-disable; 1006 bias-disable;
1009 drive-strengt 1007 drive-strength = <2>;
1010 }; 1008 };
1011 1009
1012 sdc2_cmd_on: sdc2-cmd !! 1010 sdc2_cmd_on: sdc2-cmd-on {
1013 pins = "sdc2_ 1011 pins = "sdc2_cmd";
1014 bias-pull-up; 1012 bias-pull-up;
1015 drive-strengt 1013 drive-strength = <10>;
1016 }; 1014 };
1017 1015
1018 sdc2_cmd_off: sdc2-cm !! 1016 sdc2_cmd_off: sdc2-cmd-off {
1019 pins = "sdc2_ 1017 pins = "sdc2_cmd";
1020 bias-pull-up; 1018 bias-pull-up;
1021 drive-strengt 1019 drive-strength = <2>;
1022 }; 1020 };
1023 1021
1024 sdc2_data_on: sdc2-da !! 1022 sdc2_data_on: sdc2-data-on {
1025 pins = "sdc2_ 1023 pins = "sdc2_data";
1026 bias-pull-up; 1024 bias-pull-up;
1027 drive-strengt 1025 drive-strength = <10>;
1028 }; 1026 };
1029 1027
1030 sdc2_data_off: sdc2-d !! 1028 sdc2_data_off: sdc2-data-off {
1031 pins = "sdc2_ 1029 pins = "sdc2_data";
1032 bias-pull-up; 1030 bias-pull-up;
1033 drive-strengt 1031 drive-strength = <2>;
1034 }; 1032 };
1035 }; 1033 };
1036 1034
1037 mmcc: clock-controller@fd8c00 1035 mmcc: clock-controller@fd8c0000 {
1038 compatible = "qcom,mm 1036 compatible = "qcom,mmcc-msm8994";
1039 reg = <0xfd8c0000 0x5 1037 reg = <0xfd8c0000 0x5200>;
1040 #clock-cells = <1>; 1038 #clock-cells = <1>;
1041 #reset-cells = <1>; 1039 #reset-cells = <1>;
1042 #power-domain-cells = 1040 #power-domain-cells = <1>;
1043 1041
1044 clock-names = "xo", 1042 clock-names = "xo",
1045 "gpll0" 1043 "gpll0",
1046 "mmssno 1044 "mmssnoc_ahb",
1047 "oxili_ 1045 "oxili_gfx3d_clk_src",
1048 "dsi0pl 1046 "dsi0pll",
1049 "dsi0pl 1047 "dsi0pllbyte",
1050 "dsi1pl 1048 "dsi1pll",
1051 "dsi1pl 1049 "dsi1pllbyte",
1052 "hdmipl 1050 "hdmipll";
1053 clocks = <&xo_board>, 1051 clocks = <&xo_board>,
1054 <&gcc GPLL0_ 1052 <&gcc GPLL0_OUT_MMSSCC>,
1055 <&rpmcc RPM_ 1053 <&rpmcc RPM_SMD_MMSSNOC_AHB_CLK>,
1056 <&rpmcc RPM_ 1054 <&rpmcc RPM_SMD_GFX3D_CLK_SRC>,
1057 <0>, 1055 <0>,
1058 <0>, 1056 <0>,
1059 <0>, 1057 <0>,
1060 <0>, 1058 <0>,
1061 <0>; 1059 <0>;
1062 1060
1063 assigned-clocks = <&m 1061 assigned-clocks = <&mmcc MMPLL0_PLL>,
1064 <&m 1062 <&mmcc MMPLL1_PLL>,
1065 <&m 1063 <&mmcc MMPLL3_PLL>,
1066 <&m 1064 <&mmcc MMPLL4_PLL>,
1067 <&m 1065 <&mmcc MMPLL5_PLL>;
1068 assigned-clock-rates 1066 assigned-clock-rates = <800000000>,
1069 1067 <1167000000>,
1070 1068 <1020000000>,
1071 1069 <960000000>,
1072 1070 <600000000>;
1073 }; 1071 };
1074 1072
1075 ocmem: sram@fdd00000 { 1073 ocmem: sram@fdd00000 {
1076 compatible = "qcom,ms 1074 compatible = "qcom,msm8974-ocmem";
1077 reg = <0xfdd00000 0x2 1075 reg = <0xfdd00000 0x2000>,
1078 <0xfec00000 0x2 1076 <0xfec00000 0x200000>;
1079 reg-names = "ctrl", " 1077 reg-names = "ctrl", "mem";
1080 ranges = <0 0xfec0000 1078 ranges = <0 0xfec00000 0x200000>;
1081 clocks = <&rpmcc RPM_ 1079 clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>,
1082 <&mmcc OCMEM 1080 <&mmcc OCMEMCX_OCMEMNOC_CLK>;
1083 clock-names = "core", 1081 clock-names = "core", "iface";
1084 1082
1085 #address-cells = <1>; 1083 #address-cells = <1>;
1086 #size-cells = <1>; 1084 #size-cells = <1>;
1087 1085
1088 gmu_sram: gmu-sram@0 1086 gmu_sram: gmu-sram@0 {
1089 reg = <0x0 0x 1087 reg = <0x0 0x180000>;
1090 }; 1088 };
1091 }; 1089 };
1092 }; 1090 };
1093 1091
1094 timer: timer { 1092 timer: timer {
1095 compatible = "arm,armv8-timer 1093 compatible = "arm,armv8-timer";
1096 interrupts = <GIC_PPI 2 (GIC_ !! 1094 interrupts = <GIC_PPI 2 0xff08>,
1097 <GIC_PPI 3 (GIC_ !! 1095 <GIC_PPI 3 0xff08>,
1098 <GIC_PPI 4 (GIC_ !! 1096 <GIC_PPI 4 0xff08>,
1099 <GIC_PPI 1 (GIC_ !! 1097 <GIC_PPI 1 0xff08>;
1100 }; 1098 };
1101 1099
1102 vph_pwr: vph-pwr-regulator { 1100 vph_pwr: vph-pwr-regulator {
1103 compatible = "regulator-fixed 1101 compatible = "regulator-fixed";
1104 regulator-name = "vph_pwr"; 1102 regulator-name = "vph_pwr";
1105 1103
1106 regulator-min-microvolt = <36 1104 regulator-min-microvolt = <3600000>;
1107 regulator-max-microvolt = <36 1105 regulator-max-microvolt = <3600000>;
1108 1106
1109 regulator-always-on; 1107 regulator-always-on;
1110 }; 1108 };
1111 }; 1109 };
1112 1110
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