1 // SPDX-License-Identifier: GPL-2.0-only 1 // SPDX-License-Identifier: GPL-2.0-only
2 /* 2 /*
3 * Copyright (c) 2013-2016, The Linux Foundati 3 * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
4 */ 4 */
5 5
6 #include <dt-bindings/interrupt-controller/arm 6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,gcc-msm8994.h 7 #include <dt-bindings/clock/qcom,gcc-msm8994.h>
8 #include <dt-bindings/clock/qcom,mmcc-msm8994. 8 #include <dt-bindings/clock/qcom,mmcc-msm8994.h>
9 #include <dt-bindings/clock/qcom,rpmcc.h> 9 #include <dt-bindings/clock/qcom,rpmcc.h>
10 #include <dt-bindings/gpio/gpio.h> 10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/power/qcom-rpmpd.h> 11 #include <dt-bindings/power/qcom-rpmpd.h>
12 12
13 / { 13 / {
14 interrupt-parent = <&intc>; 14 interrupt-parent = <&intc>;
15 15
16 #address-cells = <2>; 16 #address-cells = <2>;
17 #size-cells = <2>; 17 #size-cells = <2>;
18 18
19 aliases { 19 aliases {
20 mmc1 = &sdhc1; 20 mmc1 = &sdhc1;
21 mmc2 = &sdhc2; 21 mmc2 = &sdhc2;
22 }; 22 };
23 23
24 chosen { }; 24 chosen { };
25 25
26 clocks { 26 clocks {
27 xo_board: xo-board { 27 xo_board: xo-board {
28 compatible = "fixed-cl 28 compatible = "fixed-clock";
29 #clock-cells = <0>; 29 #clock-cells = <0>;
30 clock-frequency = <192 30 clock-frequency = <19200000>;
31 clock-output-names = " 31 clock-output-names = "xo_board";
32 }; 32 };
33 33
34 sleep_clk: sleep-clk { 34 sleep_clk: sleep-clk {
35 compatible = "fixed-cl 35 compatible = "fixed-clock";
36 #clock-cells = <0>; 36 #clock-cells = <0>;
37 clock-frequency = <327 37 clock-frequency = <32768>;
38 clock-output-names = " 38 clock-output-names = "sleep_clk";
39 }; 39 };
40 }; 40 };
41 41
42 cpus { 42 cpus {
43 #address-cells = <2>; 43 #address-cells = <2>;
44 #size-cells = <0>; 44 #size-cells = <0>;
45 45
46 CPU0: cpu@0 { 46 CPU0: cpu@0 {
47 device_type = "cpu"; 47 device_type = "cpu";
48 compatible = "arm,cort 48 compatible = "arm,cortex-a53";
49 reg = <0x0 0x0>; 49 reg = <0x0 0x0>;
50 enable-method = "psci" 50 enable-method = "psci";
51 next-level-cache = <&L 51 next-level-cache = <&L2_0>;
52 L2_0: l2-cache { 52 L2_0: l2-cache {
53 compatible = " 53 compatible = "cache";
54 cache-level = 54 cache-level = <2>;
55 cache-unified; <<
56 }; 55 };
57 }; 56 };
58 57
59 CPU1: cpu@1 { 58 CPU1: cpu@1 {
60 device_type = "cpu"; 59 device_type = "cpu";
61 compatible = "arm,cort 60 compatible = "arm,cortex-a53";
62 reg = <0x0 0x1>; 61 reg = <0x0 0x1>;
63 enable-method = "psci" 62 enable-method = "psci";
64 next-level-cache = <&L 63 next-level-cache = <&L2_0>;
65 }; 64 };
66 65
67 CPU2: cpu@2 { 66 CPU2: cpu@2 {
68 device_type = "cpu"; 67 device_type = "cpu";
69 compatible = "arm,cort 68 compatible = "arm,cortex-a53";
70 reg = <0x0 0x2>; 69 reg = <0x0 0x2>;
71 enable-method = "psci" 70 enable-method = "psci";
72 next-level-cache = <&L 71 next-level-cache = <&L2_0>;
73 }; 72 };
74 73
75 CPU3: cpu@3 { 74 CPU3: cpu@3 {
76 device_type = "cpu"; 75 device_type = "cpu";
77 compatible = "arm,cort 76 compatible = "arm,cortex-a53";
78 reg = <0x0 0x3>; 77 reg = <0x0 0x3>;
79 enable-method = "psci" 78 enable-method = "psci";
80 next-level-cache = <&L 79 next-level-cache = <&L2_0>;
81 }; 80 };
82 81
83 CPU4: cpu@100 { 82 CPU4: cpu@100 {
84 device_type = "cpu"; 83 device_type = "cpu";
85 compatible = "arm,cort 84 compatible = "arm,cortex-a57";
86 reg = <0x0 0x100>; 85 reg = <0x0 0x100>;
87 enable-method = "psci" 86 enable-method = "psci";
88 next-level-cache = <&L 87 next-level-cache = <&L2_1>;
89 L2_1: l2-cache { 88 L2_1: l2-cache {
90 compatible = " 89 compatible = "cache";
91 cache-level = 90 cache-level = <2>;
92 cache-unified; <<
93 }; 91 };
94 }; 92 };
95 93
96 CPU5: cpu@101 { 94 CPU5: cpu@101 {
97 device_type = "cpu"; 95 device_type = "cpu";
98 compatible = "arm,cort 96 compatible = "arm,cortex-a57";
99 reg = <0x0 0x101>; 97 reg = <0x0 0x101>;
100 enable-method = "psci" 98 enable-method = "psci";
101 next-level-cache = <&L 99 next-level-cache = <&L2_1>;
102 }; 100 };
103 101
104 CPU6: cpu@102 { 102 CPU6: cpu@102 {
105 device_type = "cpu"; 103 device_type = "cpu";
106 compatible = "arm,cort 104 compatible = "arm,cortex-a57";
107 reg = <0x0 0x102>; 105 reg = <0x0 0x102>;
108 enable-method = "psci" 106 enable-method = "psci";
109 next-level-cache = <&L 107 next-level-cache = <&L2_1>;
110 }; 108 };
111 109
112 CPU7: cpu@103 { 110 CPU7: cpu@103 {
113 device_type = "cpu"; 111 device_type = "cpu";
114 compatible = "arm,cort 112 compatible = "arm,cortex-a57";
115 reg = <0x0 0x103>; 113 reg = <0x0 0x103>;
116 enable-method = "psci" 114 enable-method = "psci";
117 next-level-cache = <&L 115 next-level-cache = <&L2_1>;
118 }; 116 };
119 117
120 cpu-map { 118 cpu-map {
121 cluster0 { 119 cluster0 {
122 core0 { 120 core0 {
123 cpu = 121 cpu = <&CPU0>;
124 }; 122 };
125 123
126 core1 { 124 core1 {
127 cpu = 125 cpu = <&CPU1>;
128 }; 126 };
129 127
130 core2 { 128 core2 {
131 cpu = 129 cpu = <&CPU2>;
132 }; 130 };
133 131
134 core3 { 132 core3 {
135 cpu = 133 cpu = <&CPU3>;
136 }; 134 };
137 }; 135 };
138 136
139 cluster1 { 137 cluster1 {
140 core0 { 138 core0 {
141 cpu = 139 cpu = <&CPU4>;
142 }; 140 };
143 141
144 core1 { 142 core1 {
145 cpu = 143 cpu = <&CPU5>;
146 }; 144 };
147 145
148 cpu6_map: core 146 cpu6_map: core2 {
149 cpu = 147 cpu = <&CPU6>;
150 }; 148 };
151 149
152 cpu7_map: core 150 cpu7_map: core3 {
153 cpu = 151 cpu = <&CPU7>;
154 }; 152 };
155 }; 153 };
156 }; 154 };
157 }; 155 };
158 156
159 firmware { 157 firmware {
160 scm { 158 scm {
161 compatible = "qcom,scm 159 compatible = "qcom,scm-msm8994", "qcom,scm";
162 }; 160 };
163 }; 161 };
164 162
165 memory@80000000 { 163 memory@80000000 {
166 device_type = "memory"; 164 device_type = "memory";
167 /* We expect the bootloader to 165 /* We expect the bootloader to fill in the reg */
168 reg = <0 0x80000000 0 0>; 166 reg = <0 0x80000000 0 0>;
169 }; 167 };
170 168
171 pmu { 169 pmu {
172 compatible = "arm,cortex-a53-p 170 compatible = "arm,cortex-a53-pmu";
173 interrupts = <GIC_PPI 7 (GIC_C 171 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4)| IRQ_TYPE_LEVEL_HIGH)>;
174 }; 172 };
175 173
176 psci { 174 psci {
177 compatible = "arm,psci-0.2"; 175 compatible = "arm,psci-0.2";
178 method = "hvc"; 176 method = "hvc";
179 }; 177 };
180 178
181 rpm: remoteproc { <<
182 compatible = "qcom,msm8994-rpm <<
183 <<
184 smd-edge { <<
185 interrupts = <GIC_SPI <<
186 mboxes = <&apcs 0>; <<
187 qcom,smd-edge = <15>; <<
188 qcom,remote-pid = <6>; <<
189 <<
190 rpm_requests: rpm-requ <<
191 compatible = " <<
192 qcom,smd-chann <<
193 <<
194 rpmcc: clock-c <<
195 compat <<
196 #clock <<
197 }; <<
198 <<
199 rpmpd: power-c <<
200 compat <<
201 #power <<
202 operat <<
203 <<
204 rpmpd_ <<
205 <<
206 <<
207 <<
208 <<
209 <<
210 <<
211 <<
212 <<
213 <<
214 <<
215 <<
216 <<
217 <<
218 <<
219 <<
220 <<
221 <<
222 <<
223 <<
224 <<
225 }; <<
226 }; <<
227 }; <<
228 }; <<
229 }; <<
230 <<
231 reserved-memory { 179 reserved-memory {
232 #address-cells = <2>; 180 #address-cells = <2>;
233 #size-cells = <2>; 181 #size-cells = <2>;
234 ranges; 182 ranges;
235 183
236 dfps_data_mem: dfps-data@34000 !! 184 dfps_data_mem: dfps_data_mem@3400000 {
237 reg = <0 0x03400000 0 185 reg = <0 0x03400000 0 0x1000>;
238 no-map; 186 no-map;
239 }; 187 };
240 188
241 cont_splash_mem: memory@340100 189 cont_splash_mem: memory@3401000 {
242 reg = <0 0x03401000 0 190 reg = <0 0x03401000 0 0x2200000>;
243 no-map; 191 no-map;
244 }; 192 };
245 193
246 smem_mem: smem@6a00000 { !! 194 smem_mem: smem_region@6a00000 {
247 reg = <0 0x06a00000 0 195 reg = <0 0x06a00000 0 0x200000>;
248 no-map; 196 no-map;
249 }; 197 };
250 198
251 mpss_mem: memory@7000000 { 199 mpss_mem: memory@7000000 {
252 reg = <0 0x07000000 0 200 reg = <0 0x07000000 0 0x5a00000>;
253 no-map; 201 no-map;
254 }; 202 };
255 203
256 peripheral_region: memory@ca00 204 peripheral_region: memory@ca00000 {
257 reg = <0 0x0ca00000 0 205 reg = <0 0x0ca00000 0 0x1f00000>;
258 no-map; 206 no-map;
259 }; 207 };
260 208
261 rmtfs_mem: memory@c6400000 { 209 rmtfs_mem: memory@c6400000 {
262 compatible = "qcom,rmt 210 compatible = "qcom,rmtfs-mem";
263 reg = <0 0xc6400000 0 211 reg = <0 0xc6400000 0 0x180000>;
264 no-map; 212 no-map;
265 213
266 qcom,client-id = <1>; 214 qcom,client-id = <1>;
267 }; 215 };
268 216
269 mba_mem: memory@c6700000 { 217 mba_mem: memory@c6700000 {
270 reg = <0 0xc6700000 0 218 reg = <0 0xc6700000 0 0x100000>;
271 no-map; 219 no-map;
272 }; 220 };
273 221
274 audio_mem: memory@c7000000 { 222 audio_mem: memory@c7000000 {
275 reg = <0 0xc7000000 0 223 reg = <0 0xc7000000 0 0x800000>;
276 no-map; 224 no-map;
277 }; 225 };
278 226
279 adsp_mem: memory@c9400000 { 227 adsp_mem: memory@c9400000 {
280 reg = <0 0xc9400000 0 228 reg = <0 0xc9400000 0 0x3f00000>;
281 no-map; 229 no-map;
282 }; 230 };
283 231
284 res_hyp_mem: reserved@6c00000 !! 232 reserved@6c00000 {
285 reg = <0 0x06c00000 0 233 reg = <0 0x06c00000 0 0x400000>;
286 no-map; 234 no-map;
287 }; 235 };
288 }; 236 };
289 237
>> 238 smd {
>> 239 compatible = "qcom,smd";
>> 240 rpm {
>> 241 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
>> 242 qcom,ipc = <&apcs 8 0>;
>> 243 qcom,smd-edge = <15>;
>> 244 qcom,remote-pid = <6>;
>> 245
>> 246 rpm_requests: rpm-requests {
>> 247 compatible = "qcom,rpm-msm8994";
>> 248 qcom,smd-channels = "rpm_requests";
>> 249
>> 250 rpmcc: rpmcc {
>> 251 compatible = "qcom,rpmcc-msm8994", "qcom,rpmcc";
>> 252 #clock-cells = <1>;
>> 253 };
>> 254
>> 255 rpmpd: power-controller {
>> 256 compatible = "qcom,msm8994-rpmpd";
>> 257 #power-domain-cells = <1>;
>> 258 operating-points-v2 = <&rpmpd_opp_table>;
>> 259
>> 260 rpmpd_opp_table: opp-table {
>> 261 compatible = "operating-points-v2";
>> 262
>> 263 rpmpd_opp_ret: opp1 {
>> 264 opp-level = <1>;
>> 265 };
>> 266 rpmpd_opp_svs_krait: opp2 {
>> 267 opp-level = <2>;
>> 268 };
>> 269 rpmpd_opp_svs_soc: opp3 {
>> 270 opp-level = <3>;
>> 271 };
>> 272 rpmpd_opp_nom: opp4 {
>> 273 opp-level = <4>;
>> 274 };
>> 275 rpmpd_opp_turbo: opp5 {
>> 276 opp-level = <5>;
>> 277 };
>> 278 rpmpd_opp_super_turbo: opp6 {
>> 279 opp-level = <6>;
>> 280 };
>> 281 };
>> 282 };
>> 283 };
>> 284 };
>> 285 };
>> 286
290 smem { 287 smem {
291 compatible = "qcom,smem"; 288 compatible = "qcom,smem";
292 memory-region = <&smem_mem>; 289 memory-region = <&smem_mem>;
293 qcom,rpm-msg-ram = <&rpm_msg_r 290 qcom,rpm-msg-ram = <&rpm_msg_ram>;
294 hwlocks = <&tcsr_mutex 3>; 291 hwlocks = <&tcsr_mutex 3>;
295 }; 292 };
296 293
297 smp2p-lpass { 294 smp2p-lpass {
298 compatible = "qcom,smp2p"; 295 compatible = "qcom,smp2p";
299 qcom,smem = <443>, <429>; 296 qcom,smem = <443>, <429>;
300 297
301 interrupts = <GIC_SPI 158 IRQ_ 298 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
302 299
303 mboxes = <&apcs 10>; !! 300 qcom,ipc = <&apcs 8 10>;
304 301
305 qcom,local-pid = <0>; 302 qcom,local-pid = <0>;
306 qcom,remote-pid = <2>; 303 qcom,remote-pid = <2>;
307 304
308 adsp_smp2p_out: master-kernel 305 adsp_smp2p_out: master-kernel {
309 qcom,entry-name = "mas 306 qcom,entry-name = "master-kernel";
310 #qcom,smem-state-cells 307 #qcom,smem-state-cells = <1>;
311 }; 308 };
312 309
313 adsp_smp2p_in: slave-kernel { 310 adsp_smp2p_in: slave-kernel {
314 qcom,entry-name = "sla 311 qcom,entry-name = "slave-kernel";
315 312
316 interrupt-controller; 313 interrupt-controller;
317 #interrupt-cells = <2> 314 #interrupt-cells = <2>;
318 }; 315 };
319 }; 316 };
320 317
321 smp2p-modem { 318 smp2p-modem {
322 compatible = "qcom,smp2p"; 319 compatible = "qcom,smp2p";
323 qcom,smem = <435>, <428>; 320 qcom,smem = <435>, <428>;
324 321
325 interrupt-parent = <&intc>; 322 interrupt-parent = <&intc>;
326 interrupts = <GIC_SPI 27 IRQ_T 323 interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>;
327 324
328 mboxes = <&apcs 14>; !! 325 qcom,ipc = <&apcs 8 14>;
329 326
330 qcom,local-pid = <0>; 327 qcom,local-pid = <0>;
331 qcom,remote-pid = <1>; 328 qcom,remote-pid = <1>;
332 329
333 modem_smp2p_out: master-kernel 330 modem_smp2p_out: master-kernel {
334 qcom,entry-name = "mas 331 qcom,entry-name = "master-kernel";
335 #qcom,smem-state-cells 332 #qcom,smem-state-cells = <1>;
336 }; 333 };
337 334
338 modem_smp2p_in: slave-kernel { 335 modem_smp2p_in: slave-kernel {
339 qcom,entry-name = "sla 336 qcom,entry-name = "slave-kernel";
340 337
341 interrupt-controller; 338 interrupt-controller;
342 #interrupt-cells = <2> 339 #interrupt-cells = <2>;
343 }; 340 };
344 }; 341 };
345 342
346 soc: soc@0 { !! 343 soc: soc {
>> 344
347 #address-cells = <1>; 345 #address-cells = <1>;
348 #size-cells = <1>; 346 #size-cells = <1>;
349 ranges = <0 0 0 0xffffffff>; 347 ranges = <0 0 0 0xffffffff>;
350 compatible = "simple-bus"; 348 compatible = "simple-bus";
351 349
352 intc: interrupt-controller@f90 350 intc: interrupt-controller@f9000000 {
353 compatible = "qcom,msm 351 compatible = "qcom,msm-qgic2";
354 interrupt-controller; 352 interrupt-controller;
355 #interrupt-cells = <3> 353 #interrupt-cells = <3>;
356 reg = <0xf9000000 0x10 354 reg = <0xf9000000 0x1000>,
357 <0xf9002000 0x10 355 <0xf9002000 0x1000>;
358 }; 356 };
359 357
360 apcs: mailbox@f900d000 { 358 apcs: mailbox@f900d000 {
361 compatible = "qcom,msm 359 compatible = "qcom,msm8994-apcs-kpss-global", "syscon";
362 reg = <0xf900d000 0x20 360 reg = <0xf900d000 0x2000>;
363 #mbox-cells = <1>; 361 #mbox-cells = <1>;
364 }; 362 };
365 363
366 watchdog@f9017000 { 364 watchdog@f9017000 {
367 compatible = "qcom,aps 365 compatible = "qcom,apss-wdt-msm8994", "qcom,kpss-wdt";
368 reg = <0xf9017000 0x10 366 reg = <0xf9017000 0x1000>;
369 interrupts = <GIC_SPI 367 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>,
370 <GIC_SPI 368 <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>;
371 clocks = <&sleep_clk>; 369 clocks = <&sleep_clk>;
372 timeout-sec = <10>; 370 timeout-sec = <10>;
373 }; 371 };
374 372
375 timer@f9020000 { 373 timer@f9020000 {
376 #address-cells = <1>; 374 #address-cells = <1>;
377 #size-cells = <1>; 375 #size-cells = <1>;
378 ranges; 376 ranges;
379 compatible = "arm,armv 377 compatible = "arm,armv7-timer-mem";
380 reg = <0xf9020000 0x10 378 reg = <0xf9020000 0x1000>;
381 379
382 frame@f9021000 { 380 frame@f9021000 {
383 frame-number = 381 frame-number = <0>;
384 interrupts = < 382 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
385 < 383 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
386 reg = <0xf9021 384 reg = <0xf9021000 0x1000>,
387 <0xf9022 385 <0xf9022000 0x1000>;
388 }; 386 };
389 387
390 frame@f9023000 { 388 frame@f9023000 {
391 frame-number = 389 frame-number = <1>;
392 interrupts = < 390 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
393 reg = <0xf9023 391 reg = <0xf9023000 0x1000>;
394 status = "disa 392 status = "disabled";
395 }; 393 };
396 394
397 frame@f9024000 { 395 frame@f9024000 {
398 frame-number = 396 frame-number = <2>;
399 interrupts = < 397 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
400 reg = <0xf9024 398 reg = <0xf9024000 0x1000>;
401 status = "disa 399 status = "disabled";
402 }; 400 };
403 401
404 frame@f9025000 { 402 frame@f9025000 {
405 frame-number = 403 frame-number = <3>;
406 interrupts = < 404 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
407 reg = <0xf9025 405 reg = <0xf9025000 0x1000>;
408 status = "disa 406 status = "disabled";
409 }; 407 };
410 408
411 frame@f9026000 { 409 frame@f9026000 {
412 frame-number = 410 frame-number = <4>;
413 interrupts = < 411 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
414 reg = <0xf9026 412 reg = <0xf9026000 0x1000>;
415 status = "disa 413 status = "disabled";
416 }; 414 };
417 415
418 frame@f9027000 { 416 frame@f9027000 {
419 frame-number = 417 frame-number = <5>;
420 interrupts = < 418 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
421 reg = <0xf9027 419 reg = <0xf9027000 0x1000>;
422 status = "disa 420 status = "disabled";
423 }; 421 };
424 422
425 frame@f9028000 { 423 frame@f9028000 {
426 frame-number = 424 frame-number = <6>;
427 interrupts = < 425 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
428 reg = <0xf9028 426 reg = <0xf9028000 0x1000>;
429 status = "disa 427 status = "disabled";
430 }; 428 };
431 }; 429 };
432 430
433 usb3: usb@f92f8800 { 431 usb3: usb@f92f8800 {
434 compatible = "qcom,msm 432 compatible = "qcom,msm8994-dwc3", "qcom,dwc3";
435 reg = <0xf92f8800 0x40 433 reg = <0xf92f8800 0x400>;
436 #address-cells = <1>; 434 #address-cells = <1>;
437 #size-cells = <1>; 435 #size-cells = <1>;
438 ranges; 436 ranges;
439 437
440 clocks = <&gcc GCC_USB 438 clocks = <&gcc GCC_USB30_MASTER_CLK>,
441 <&gcc GCC_SYS 439 <&gcc GCC_SYS_NOC_USB3_AXI_CLK>,
442 <&gcc GCC_USB 440 <&gcc GCC_USB30_SLEEP_CLK>,
443 <&gcc GCC_USB 441 <&gcc GCC_USB30_MOCK_UTMI_CLK>;
444 clock-names = "core", 442 clock-names = "core",
445 "iface", 443 "iface",
446 "sleep", 444 "sleep",
447 "mock_ut 445 "mock_utmi";
448 446
449 assigned-clocks = <&gc 447 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
450 <&gc 448 <&gcc GCC_USB30_MASTER_CLK>;
451 assigned-clock-rates = 449 assigned-clock-rates = <19200000>, <120000000>;
452 450
453 power-domains = <&gcc 451 power-domains = <&gcc USB30_GDSC>;
454 qcom,select-utmi-as-pi 452 qcom,select-utmi-as-pipe-clk;
455 453
456 usb@f9200000 { 454 usb@f9200000 {
457 compatible = " 455 compatible = "snps,dwc3";
458 reg = <0xf9200 456 reg = <0xf9200000 0xcc00>;
459 interrupts = < !! 457 interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>;
460 snps,dis_u2_su 458 snps,dis_u2_susphy_quirk;
461 snps,dis_enbls 459 snps,dis_enblslpm_quirk;
462 maximum-speed 460 maximum-speed = "high-speed";
463 dr_mode = "per 461 dr_mode = "peripheral";
464 }; 462 };
465 }; 463 };
466 464
467 sdhc1: mmc@f9824900 { 465 sdhc1: mmc@f9824900 {
468 compatible = "qcom,msm 466 compatible = "qcom,msm8994-sdhci", "qcom,sdhci-msm-v4";
469 reg = <0xf9824900 0x1a 467 reg = <0xf9824900 0x1a0>, <0xf9824000 0x800>;
470 reg-names = "hc", "cor 468 reg-names = "hc", "core";
471 469
472 interrupts = <GIC_SPI 470 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
473 <GIC_SPI 471 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
474 interrupt-names = "hc_ 472 interrupt-names = "hc_irq", "pwr_irq";
475 473
476 clocks = <&gcc GCC_SDC 474 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
477 <&gcc GCC_SDC 475 <&gcc GCC_SDCC1_APPS_CLK>,
478 <&xo_board>; 476 <&xo_board>;
479 clock-names = "iface", 477 clock-names = "iface", "core", "xo";
480 478
481 pinctrl-names = "defau 479 pinctrl-names = "default", "sleep";
482 pinctrl-0 = <&sdc1_clk 480 pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>;
483 pinctrl-1 = <&sdc1_clk 481 pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>;
484 482
485 bus-width = <8>; 483 bus-width = <8>;
486 non-removable; 484 non-removable;
487 status = "disabled"; 485 status = "disabled";
488 }; 486 };
489 487
490 sdhc2: mmc@f98a4900 { 488 sdhc2: mmc@f98a4900 {
491 compatible = "qcom,msm 489 compatible = "qcom,msm8994-sdhci", "qcom,sdhci-msm-v4";
492 reg = <0xf98a4900 0x11 490 reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
493 reg-names = "hc", "cor 491 reg-names = "hc", "core";
494 492
495 interrupts = <GIC_SPI 493 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
496 <GIC_SPI 221 I 494 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
497 interrupt-names = "hc_ 495 interrupt-names = "hc_irq", "pwr_irq";
498 496
499 clocks = <&gcc GCC_SDC 497 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
500 <&gcc GCC_SDC 498 <&gcc GCC_SDCC2_APPS_CLK>,
501 <&xo_board>; 499 <&xo_board>;
502 clock-names = "iface", 500 clock-names = "iface", "core", "xo";
503 501
504 pinctrl-names = "defau 502 pinctrl-names = "default", "sleep";
505 pinctrl-0 = <&sdc2_clk 503 pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>;
506 pinctrl-1 = <&sdc2_clk 504 pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>;
507 505
508 cd-gpios = <&tlmm 100 506 cd-gpios = <&tlmm 100 GPIO_ACTIVE_HIGH>;
509 bus-width = <4>; 507 bus-width = <4>;
510 status = "disabled"; 508 status = "disabled";
511 }; 509 };
512 510
513 blsp1_dma: dma-controller@f990 511 blsp1_dma: dma-controller@f9904000 {
514 compatible = "qcom,bam 512 compatible = "qcom,bam-v1.7.0";
515 reg = <0xf9904000 0x19 513 reg = <0xf9904000 0x19000>;
516 interrupts = <GIC_SPI 514 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
517 clocks = <&gcc GCC_BLS 515 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
518 clock-names = "bam_clk 516 clock-names = "bam_clk";
519 #dma-cells = <1>; 517 #dma-cells = <1>;
520 qcom,ee = <0>; 518 qcom,ee = <0>;
521 qcom,controlled-remote 519 qcom,controlled-remotely;
522 num-channels = <24>; 520 num-channels = <24>;
523 qcom,num-ees = <4>; 521 qcom,num-ees = <4>;
524 }; 522 };
525 523
526 blsp1_uart2: serial@f991e000 { 524 blsp1_uart2: serial@f991e000 {
527 compatible = "qcom,msm 525 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
528 reg = <0xf991e000 0x10 526 reg = <0xf991e000 0x1000>;
529 interrupts = <GIC_SPI 527 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
530 clock-names = "core", 528 clock-names = "core", "iface";
531 clocks = <&gcc GCC_BLS 529 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
532 <&gcc GCC_BLS 530 <&gcc GCC_BLSP1_AHB_CLK>;
533 pinctrl-names = "defau 531 pinctrl-names = "default", "sleep";
534 pinctrl-0 = <&blsp1_ua 532 pinctrl-0 = <&blsp1_uart2_default>;
535 pinctrl-1 = <&blsp1_ua 533 pinctrl-1 = <&blsp1_uart2_sleep>;
536 status = "disabled"; 534 status = "disabled";
537 }; 535 };
538 536
539 blsp1_i2c1: i2c@f9923000 { 537 blsp1_i2c1: i2c@f9923000 {
540 compatible = "qcom,i2c 538 compatible = "qcom,i2c-qup-v2.2.1";
541 reg = <0xf9923000 0x50 539 reg = <0xf9923000 0x500>;
542 interrupts = <GIC_SPI 540 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
543 clocks = <&gcc GCC_BLS 541 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
544 <&gcc GCC_BLS 542 <&gcc GCC_BLSP1_AHB_CLK>;
545 clock-names = "core", 543 clock-names = "core", "iface";
546 clock-frequency = <400 544 clock-frequency = <400000>;
547 dmas = <&blsp1_dma 12> 545 dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
548 dma-names = "tx", "rx" 546 dma-names = "tx", "rx";
549 pinctrl-names = "defau 547 pinctrl-names = "default", "sleep";
550 pinctrl-0 = <&i2c1_def 548 pinctrl-0 = <&i2c1_default>;
551 pinctrl-1 = <&i2c1_sle 549 pinctrl-1 = <&i2c1_sleep>;
552 #address-cells = <1>; 550 #address-cells = <1>;
553 #size-cells = <0>; 551 #size-cells = <0>;
554 status = "disabled"; 552 status = "disabled";
555 }; 553 };
556 554
557 blsp1_spi1: spi@f9923000 { 555 blsp1_spi1: spi@f9923000 {
558 compatible = "qcom,spi 556 compatible = "qcom,spi-qup-v2.2.1";
559 reg = <0xf9923000 0x50 557 reg = <0xf9923000 0x500>;
560 interrupts = <GIC_SPI 558 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
561 clocks = <&gcc GCC_BLS 559 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
562 <&gcc GCC_BLS 560 <&gcc GCC_BLSP1_AHB_CLK>;
563 clock-names = "core", 561 clock-names = "core", "iface";
564 dmas = <&blsp1_dma 12> 562 dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
565 dma-names = "tx", "rx" 563 dma-names = "tx", "rx";
566 pinctrl-names = "defau 564 pinctrl-names = "default", "sleep";
567 pinctrl-0 = <&blsp1_sp 565 pinctrl-0 = <&blsp1_spi1_default>;
568 pinctrl-1 = <&blsp1_sp 566 pinctrl-1 = <&blsp1_spi1_sleep>;
569 #address-cells = <1>; 567 #address-cells = <1>;
570 #size-cells = <0>; 568 #size-cells = <0>;
571 status = "disabled"; 569 status = "disabled";
572 }; 570 };
573 571
574 blsp1_i2c2: i2c@f9924000 { 572 blsp1_i2c2: i2c@f9924000 {
575 compatible = "qcom,i2c 573 compatible = "qcom,i2c-qup-v2.2.1";
576 reg = <0xf9924000 0x50 574 reg = <0xf9924000 0x500>;
577 interrupts = <GIC_SPI 575 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
578 clocks = <&gcc GCC_BLS 576 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
579 <&gcc GCC_BLS 577 <&gcc GCC_BLSP1_AHB_CLK>;
580 clock-names = "core", 578 clock-names = "core", "iface";
581 clock-frequency = <400 579 clock-frequency = <400000>;
582 dmas = <&blsp1_dma 14> 580 dmas = <&blsp1_dma 14>, <&blsp1_dma 15>;
583 dma-names = "tx", "rx" 581 dma-names = "tx", "rx";
584 pinctrl-names = "defau 582 pinctrl-names = "default", "sleep";
585 pinctrl-0 = <&i2c2_def 583 pinctrl-0 = <&i2c2_default>;
586 pinctrl-1 = <&i2c2_sle 584 pinctrl-1 = <&i2c2_sleep>;
587 #address-cells = <1>; 585 #address-cells = <1>;
588 #size-cells = <0>; 586 #size-cells = <0>;
589 status = "disabled"; 587 status = "disabled";
590 }; 588 };
591 589
592 /* I2C3 doesn't exist */ 590 /* I2C3 doesn't exist */
593 591
594 blsp1_i2c4: i2c@f9926000 { 592 blsp1_i2c4: i2c@f9926000 {
595 compatible = "qcom,i2c 593 compatible = "qcom,i2c-qup-v2.2.1";
596 reg = <0xf9926000 0x50 594 reg = <0xf9926000 0x500>;
597 interrupts = <GIC_SPI 595 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
598 clocks = <&gcc GCC_BLS 596 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
599 <&gcc GCC_BLS 597 <&gcc GCC_BLSP1_AHB_CLK>;
600 clock-names = "core", 598 clock-names = "core", "iface";
601 clock-frequency = <400 599 clock-frequency = <400000>;
602 dmas = <&blsp1_dma 18> 600 dmas = <&blsp1_dma 18>, <&blsp1_dma 19>;
603 dma-names = "tx", "rx" 601 dma-names = "tx", "rx";
604 pinctrl-names = "defau 602 pinctrl-names = "default", "sleep";
605 pinctrl-0 = <&i2c4_def 603 pinctrl-0 = <&i2c4_default>;
606 pinctrl-1 = <&i2c4_sle 604 pinctrl-1 = <&i2c4_sleep>;
607 #address-cells = <1>; 605 #address-cells = <1>;
608 #size-cells = <0>; 606 #size-cells = <0>;
609 status = "disabled"; 607 status = "disabled";
610 }; 608 };
611 609
612 blsp1_i2c5: i2c@f9927000 { 610 blsp1_i2c5: i2c@f9927000 {
613 compatible = "qcom,i2c 611 compatible = "qcom,i2c-qup-v2.2.1";
614 reg = <0xf9927000 0x50 612 reg = <0xf9927000 0x500>;
615 interrupts = <GIC_SPI 613 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
616 clocks = <&gcc GCC_BLS 614 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
617 <&gcc GCC_BLS 615 <&gcc GCC_BLSP1_AHB_CLK>;
618 clock-names = "core", 616 clock-names = "core", "iface";
619 clock-frequency = <400 617 clock-frequency = <400000>;
620 dmas = <&blsp2_dma 20> 618 dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
621 dma-names = "tx", "rx" 619 dma-names = "tx", "rx";
622 pinctrl-names = "defau 620 pinctrl-names = "default", "sleep";
623 pinctrl-0 = <&i2c5_def 621 pinctrl-0 = <&i2c5_default>;
624 pinctrl-1 = <&i2c5_sle 622 pinctrl-1 = <&i2c5_sleep>;
625 #address-cells = <1>; 623 #address-cells = <1>;
626 #size-cells = <0>; 624 #size-cells = <0>;
627 status = "disabled"; 625 status = "disabled";
628 }; 626 };
629 627
630 blsp1_i2c6: i2c@f9928000 { 628 blsp1_i2c6: i2c@f9928000 {
631 compatible = "qcom,i2c 629 compatible = "qcom,i2c-qup-v2.2.1";
632 reg = <0xf9928000 0x50 630 reg = <0xf9928000 0x500>;
633 interrupts = <GIC_SPI 631 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
634 clocks = <&gcc GCC_BLS 632 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
635 <&gcc GCC_BLS 633 <&gcc GCC_BLSP1_AHB_CLK>;
636 clock-names = "core", 634 clock-names = "core", "iface";
637 clock-frequency = <400 635 clock-frequency = <400000>;
638 dmas = <&blsp1_dma 22> 636 dmas = <&blsp1_dma 22>, <&blsp1_dma 23>;
639 dma-names = "tx", "rx" 637 dma-names = "tx", "rx";
640 pinctrl-names = "defau 638 pinctrl-names = "default", "sleep";
641 pinctrl-0 = <&i2c6_def 639 pinctrl-0 = <&i2c6_default>;
642 pinctrl-1 = <&i2c6_sle 640 pinctrl-1 = <&i2c6_sleep>;
643 #address-cells = <1>; 641 #address-cells = <1>;
644 #size-cells = <0>; 642 #size-cells = <0>;
645 status = "disabled"; 643 status = "disabled";
646 }; 644 };
647 645
648 blsp2_dma: dma-controller@f994 646 blsp2_dma: dma-controller@f9944000 {
649 compatible = "qcom,bam 647 compatible = "qcom,bam-v1.7.0";
650 reg = <0xf9944000 0x19 648 reg = <0xf9944000 0x19000>;
651 interrupts = <GIC_SPI 649 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
652 clocks = <&gcc GCC_BLS 650 clocks = <&gcc GCC_BLSP2_AHB_CLK>;
653 clock-names = "bam_clk 651 clock-names = "bam_clk";
654 #dma-cells = <1>; 652 #dma-cells = <1>;
655 qcom,ee = <0>; 653 qcom,ee = <0>;
656 qcom,controlled-remote 654 qcom,controlled-remotely;
657 num-channels = <24>; 655 num-channels = <24>;
658 qcom,num-ees = <4>; 656 qcom,num-ees = <4>;
659 }; 657 };
660 658
661 blsp2_uart2: serial@f995e000 { 659 blsp2_uart2: serial@f995e000 {
662 compatible = "qcom,msm 660 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
663 reg = <0xf995e000 0x10 661 reg = <0xf995e000 0x1000>;
664 interrupts = <GIC_SPI 662 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
665 clock-names = "core", 663 clock-names = "core", "iface";
666 clocks = <&gcc GCC_BLS 664 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
667 <&gcc 665 <&gcc GCC_BLSP2_AHB_CLK>;
668 dmas = <&blsp2_dma 2>, 666 dmas = <&blsp2_dma 2>, <&blsp2_dma 3>;
669 dma-names = "tx", "rx" 667 dma-names = "tx", "rx";
670 pinctrl-names = "defau 668 pinctrl-names = "default", "sleep";
671 pinctrl-0 = <&blsp2_ua 669 pinctrl-0 = <&blsp2_uart2_default>;
672 pinctrl-1 = <&blsp2_ua 670 pinctrl-1 = <&blsp2_uart2_sleep>;
673 status = "disabled"; 671 status = "disabled";
674 }; 672 };
675 673
676 blsp2_i2c1: i2c@f9963000 { 674 blsp2_i2c1: i2c@f9963000 {
677 compatible = "qcom,i2c 675 compatible = "qcom,i2c-qup-v2.2.1";
678 reg = <0xf9963000 0x50 676 reg = <0xf9963000 0x500>;
679 interrupts = <GIC_SPI 677 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
680 clocks = <&gcc GCC_BLS 678 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
681 <&gcc GCC_BLS 679 <&gcc GCC_BLSP2_AHB_CLK>;
682 clock-names = "core", 680 clock-names = "core", "iface";
683 clock-frequency = <400 681 clock-frequency = <400000>;
684 dmas = <&blsp2_dma 12> 682 dmas = <&blsp2_dma 12>, <&blsp2_dma 13>;
685 dma-names = "tx", "rx" 683 dma-names = "tx", "rx";
686 pinctrl-names = "defau 684 pinctrl-names = "default", "sleep";
687 pinctrl-0 = <&i2c7_def 685 pinctrl-0 = <&i2c7_default>;
688 pinctrl-1 = <&i2c7_sle 686 pinctrl-1 = <&i2c7_sleep>;
689 #address-cells = <1>; 687 #address-cells = <1>;
690 #size-cells = <0>; 688 #size-cells = <0>;
691 status = "disabled"; 689 status = "disabled";
692 }; 690 };
693 691
694 blsp2_spi4: spi@f9966000 { 692 blsp2_spi4: spi@f9966000 {
695 compatible = "qcom,spi 693 compatible = "qcom,spi-qup-v2.2.1";
696 reg = <0xf9966000 0x50 694 reg = <0xf9966000 0x500>;
697 interrupts = <GIC_SPI 695 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
698 clocks = <&gcc GCC_BLS 696 clocks = <&gcc GCC_BLSP2_QUP4_SPI_APPS_CLK>,
699 <&gcc GCC_BLS 697 <&gcc GCC_BLSP2_AHB_CLK>;
700 clock-names = "core", 698 clock-names = "core", "iface";
701 dmas = <&blsp2_dma 18> 699 dmas = <&blsp2_dma 18>, <&blsp2_dma 19>;
702 dma-names = "tx", "rx" 700 dma-names = "tx", "rx";
703 pinctrl-names = "defau 701 pinctrl-names = "default", "sleep";
704 pinctrl-0 = <&blsp2_sp 702 pinctrl-0 = <&blsp2_spi10_default>;
705 pinctrl-1 = <&blsp2_sp 703 pinctrl-1 = <&blsp2_spi10_sleep>;
706 #address-cells = <1>; 704 #address-cells = <1>;
707 #size-cells = <0>; 705 #size-cells = <0>;
708 status = "disabled"; 706 status = "disabled";
709 }; 707 };
710 708
711 blsp2_i2c5: i2c@f9967000 { 709 blsp2_i2c5: i2c@f9967000 {
712 compatible = "qcom,i2c 710 compatible = "qcom,i2c-qup-v2.2.1";
713 reg = <0xf9967000 0x50 711 reg = <0xf9967000 0x500>;
714 interrupts = <GIC_SPI 712 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
715 clocks = <&gcc GCC_BLS 713 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>,
716 <&gcc GCC_BLS 714 <&gcc GCC_BLSP2_AHB_CLK>;
717 clock-names = "core", 715 clock-names = "core", "iface";
718 clock-frequency = <355 716 clock-frequency = <355000>;
719 dmas = <&blsp2_dma 20> 717 dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
720 dma-names = "tx", "rx" 718 dma-names = "tx", "rx";
721 pinctrl-names = "defau 719 pinctrl-names = "default", "sleep";
722 pinctrl-0 = <&i2c11_de 720 pinctrl-0 = <&i2c11_default>;
723 pinctrl-1 = <&i2c11_sl 721 pinctrl-1 = <&i2c11_sleep>;
724 #address-cells = <1>; 722 #address-cells = <1>;
725 #size-cells = <0>; 723 #size-cells = <0>;
726 status = "disabled"; 724 status = "disabled";
727 }; 725 };
728 726
729 gcc: clock-controller@fc400000 727 gcc: clock-controller@fc400000 {
730 compatible = "qcom,gcc 728 compatible = "qcom,gcc-msm8994";
731 #clock-cells = <1>; 729 #clock-cells = <1>;
732 #reset-cells = <1>; 730 #reset-cells = <1>;
733 #power-domain-cells = 731 #power-domain-cells = <1>;
734 reg = <0xfc400000 0x20 732 reg = <0xfc400000 0x2000>;
735 733
736 clock-names = "xo", "s 734 clock-names = "xo", "sleep";
737 clocks = <&xo_board>, 735 clocks = <&xo_board>, <&sleep_clk>;
738 }; 736 };
739 737
740 rpm_msg_ram: sram@fc428000 { 738 rpm_msg_ram: sram@fc428000 {
741 compatible = "qcom,rpm 739 compatible = "qcom,rpm-msg-ram";
742 reg = <0xfc428000 0x40 740 reg = <0xfc428000 0x4000>;
743 }; 741 };
744 742
745 restart@fc4ab000 { 743 restart@fc4ab000 {
746 compatible = "qcom,psh 744 compatible = "qcom,pshold";
747 reg = <0xfc4ab000 0x4> 745 reg = <0xfc4ab000 0x4>;
748 }; 746 };
749 747
750 spmi_bus: spmi@fc4cf000 { !! 748 spmi_bus: spmi@fc4c0000 {
751 compatible = "qcom,spm 749 compatible = "qcom,spmi-pmic-arb";
752 reg = <0xfc4cf000 0x10 750 reg = <0xfc4cf000 0x1000>,
753 <0xfc4cb000 0x10 751 <0xfc4cb000 0x1000>,
754 <0xfc4ca000 0x10 752 <0xfc4ca000 0x1000>;
755 reg-names = "core", "i 753 reg-names = "core", "intr", "cnfg";
756 interrupt-names = "per 754 interrupt-names = "periph_irq";
757 interrupts = <GIC_SPI 755 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
758 qcom,ee = <0>; 756 qcom,ee = <0>;
759 qcom,channel = <0>; 757 qcom,channel = <0>;
760 #address-cells = <2>; 758 #address-cells = <2>;
761 #size-cells = <0>; 759 #size-cells = <0>;
762 interrupt-controller; 760 interrupt-controller;
763 #interrupt-cells = <4> 761 #interrupt-cells = <4>;
764 }; 762 };
765 763
766 tcsr_mutex: hwlock@fd484000 { 764 tcsr_mutex: hwlock@fd484000 {
767 compatible = "qcom,msm 765 compatible = "qcom,msm8994-tcsr-mutex", "qcom,tcsr-mutex";
768 reg = <0xfd484000 0x10 766 reg = <0xfd484000 0x1000>;
769 #hwlock-cells = <1>; 767 #hwlock-cells = <1>;
770 }; 768 };
771 769
772 tlmm: pinctrl@fd510000 { 770 tlmm: pinctrl@fd510000 {
773 compatible = "qcom,msm 771 compatible = "qcom,msm8994-pinctrl";
774 reg = <0xfd510000 0x40 772 reg = <0xfd510000 0x4000>;
775 interrupts = <GIC_SPI 773 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
776 gpio-controller; 774 gpio-controller;
777 gpio-ranges = <&tlmm 0 775 gpio-ranges = <&tlmm 0 0 146>;
778 #gpio-cells = <2>; 776 #gpio-cells = <2>;
779 interrupt-controller; 777 interrupt-controller;
780 #interrupt-cells = <2> 778 #interrupt-cells = <2>;
781 779
782 blsp1_uart2_default: b 780 blsp1_uart2_default: blsp1-uart2-default-state {
783 pins = "gpio4" 781 pins = "gpio4", "gpio5";
784 function = "bl 782 function = "blsp_uart2";
785 drive-strength 783 drive-strength = <16>;
786 bias-disable; 784 bias-disable;
787 }; 785 };
788 786
789 blsp1_uart2_sleep: bls 787 blsp1_uart2_sleep: blsp1-uart2-sleep-state {
790 pins = "gpio4" 788 pins = "gpio4", "gpio5";
791 function = "gp 789 function = "gpio";
792 drive-strength 790 drive-strength = <2>;
793 bias-pull-down 791 bias-pull-down;
794 }; 792 };
795 793
796 blsp2_uart2_default: b 794 blsp2_uart2_default: blsp2-uart2-default-state {
797 pins = "gpio45 795 pins = "gpio45", "gpio46", "gpio47", "gpio48";
798 function = "bl 796 function = "blsp_uart8";
799 drive-strength 797 drive-strength = <16>;
800 bias-disable; 798 bias-disable;
801 }; 799 };
802 800
803 blsp2_uart2_sleep: bls 801 blsp2_uart2_sleep: blsp2-uart2-sleep-state {
804 pins = "gpio45 802 pins = "gpio45", "gpio46", "gpio47", "gpio48";
805 function = "gp 803 function = "gpio";
806 drive-strength 804 drive-strength = <2>;
807 bias-disable; 805 bias-disable;
808 }; 806 };
809 807
810 i2c1_default: i2c1-def 808 i2c1_default: i2c1-default-state {
811 pins = "gpio2" 809 pins = "gpio2", "gpio3";
812 function = "bl 810 function = "blsp_i2c1";
813 drive-strength 811 drive-strength = <2>;
814 bias-disable; 812 bias-disable;
815 }; 813 };
816 814
817 i2c1_sleep: i2c1-sleep 815 i2c1_sleep: i2c1-sleep-state {
818 pins = "gpio2" 816 pins = "gpio2", "gpio3";
819 function = "gp 817 function = "gpio";
820 drive-strength 818 drive-strength = <2>;
821 bias-disable; 819 bias-disable;
822 }; 820 };
823 821
824 i2c2_default: i2c2-def 822 i2c2_default: i2c2-default-state {
825 pins = "gpio6" 823 pins = "gpio6", "gpio7";
826 function = "bl 824 function = "blsp_i2c2";
827 drive-strength 825 drive-strength = <2>;
828 bias-disable; 826 bias-disable;
829 }; 827 };
830 828
831 i2c2_sleep: i2c2-sleep 829 i2c2_sleep: i2c2-sleep-state {
832 pins = "gpio6" 830 pins = "gpio6", "gpio7";
833 function = "gp 831 function = "gpio";
834 drive-strength 832 drive-strength = <2>;
835 bias-disable; 833 bias-disable;
836 }; 834 };
837 835
838 i2c4_default: i2c4-def 836 i2c4_default: i2c4-default-state {
839 pins = "gpio19 837 pins = "gpio19", "gpio20";
840 function = "bl 838 function = "blsp_i2c4";
841 drive-strength 839 drive-strength = <2>;
842 bias-disable; 840 bias-disable;
843 }; 841 };
844 842
845 i2c4_sleep: i2c4-sleep 843 i2c4_sleep: i2c4-sleep-state {
846 pins = "gpio19 844 pins = "gpio19", "gpio20";
847 function = "gp 845 function = "gpio";
848 drive-strength 846 drive-strength = <2>;
849 bias-pull-down 847 bias-pull-down;
>> 848 input-enable;
850 }; 849 };
851 850
852 i2c5_default: i2c5-def 851 i2c5_default: i2c5-default-state {
853 pins = "gpio23 852 pins = "gpio23", "gpio24";
854 function = "bl 853 function = "blsp_i2c5";
855 drive-strength 854 drive-strength = <2>;
856 bias-disable; 855 bias-disable;
857 }; 856 };
858 857
859 i2c5_sleep: i2c5-sleep 858 i2c5_sleep: i2c5-sleep-state {
860 pins = "gpio23 859 pins = "gpio23", "gpio24";
861 function = "gp 860 function = "gpio";
862 drive-strength 861 drive-strength = <2>;
863 bias-disable; 862 bias-disable;
864 }; 863 };
865 864
866 i2c6_default: i2c6-def 865 i2c6_default: i2c6-default-state {
867 pins = "gpio28 866 pins = "gpio28", "gpio27";
868 function = "bl 867 function = "blsp_i2c6";
869 drive-strength 868 drive-strength = <2>;
870 bias-disable; 869 bias-disable;
871 }; 870 };
872 871
873 i2c6_sleep: i2c6-sleep 872 i2c6_sleep: i2c6-sleep-state {
874 pins = "gpio28 873 pins = "gpio28", "gpio27";
875 function = "gp 874 function = "gpio";
876 drive-strength 875 drive-strength = <2>;
877 bias-disable; 876 bias-disable;
878 }; 877 };
879 878
880 i2c7_default: i2c7-def 879 i2c7_default: i2c7-default-state {
881 pins = "gpio44 880 pins = "gpio44", "gpio43";
882 function = "bl 881 function = "blsp_i2c7";
883 drive-strength 882 drive-strength = <2>;
884 bias-disable; 883 bias-disable;
885 }; 884 };
886 885
887 i2c7_sleep: i2c7-sleep 886 i2c7_sleep: i2c7-sleep-state {
888 pins = "gpio44 887 pins = "gpio44", "gpio43";
889 function = "gp 888 function = "gpio";
890 drive-strength 889 drive-strength = <2>;
891 bias-disable; 890 bias-disable;
892 }; 891 };
893 892
894 blsp2_spi10_default: b 893 blsp2_spi10_default: blsp2-spi10-default-state {
895 default-pins { 894 default-pins {
896 pins = 895 pins = "gpio53", "gpio54", "gpio55";
897 functi 896 function = "blsp_spi10";
898 drive- 897 drive-strength = <10>;
899 bias-p 898 bias-pull-down;
900 }; 899 };
901 900
902 cs-pins { 901 cs-pins {
903 pins = 902 pins = "gpio67";
904 functi 903 function = "gpio";
905 drive- 904 drive-strength = <2>;
906 bias-d 905 bias-disable;
907 }; 906 };
908 }; 907 };
909 908
910 blsp2_spi10_sleep: bls 909 blsp2_spi10_sleep: blsp2-spi10-sleep-state {
911 pins = "gpio53 910 pins = "gpio53", "gpio54", "gpio55";
912 function = "gp 911 function = "gpio";
913 drive-strength 912 drive-strength = <2>;
914 bias-disable; 913 bias-disable;
915 }; 914 };
916 915
917 i2c11_default: i2c11-d 916 i2c11_default: i2c11-default-state {
918 pins = "gpio83 917 pins = "gpio83", "gpio84";
919 function = "bl 918 function = "blsp_i2c11";
920 drive-strength 919 drive-strength = <2>;
921 bias-disable; 920 bias-disable;
922 }; 921 };
923 922
924 i2c11_sleep: i2c11-sle 923 i2c11_sleep: i2c11-sleep-state {
925 pins = "gpio83 924 pins = "gpio83", "gpio84";
926 function = "gp 925 function = "gpio";
927 drive-strength 926 drive-strength = <2>;
928 bias-disable; 927 bias-disable;
929 }; 928 };
930 929
931 blsp1_spi1_default: bl 930 blsp1_spi1_default: blsp1-spi1-default-state {
932 default-pins { 931 default-pins {
933 pins = 932 pins = "gpio0", "gpio1", "gpio3";
934 functi 933 function = "blsp_spi1";
935 drive- 934 drive-strength = <10>;
936 bias-p 935 bias-pull-down;
937 }; 936 };
938 937
939 cs-pins { 938 cs-pins {
940 pins = 939 pins = "gpio8";
941 functi 940 function = "gpio";
942 drive- 941 drive-strength = <2>;
943 bias-d 942 bias-disable;
944 }; 943 };
945 }; 944 };
946 945
947 blsp1_spi1_sleep: blsp 946 blsp1_spi1_sleep: blsp1-spi1-sleep-state {
948 pins = "gpio0" 947 pins = "gpio0", "gpio1", "gpio3";
949 function = "gp 948 function = "gpio";
950 drive-strength 949 drive-strength = <2>;
951 bias-disable; 950 bias-disable;
952 }; 951 };
953 952
954 sdc1_clk_on: clk-on-st 953 sdc1_clk_on: clk-on-state {
955 pins = "sdc1_c 954 pins = "sdc1_clk";
956 bias-disable; 955 bias-disable;
957 drive-strength 956 drive-strength = <16>;
958 }; 957 };
959 958
960 sdc1_clk_off: clk-off- 959 sdc1_clk_off: clk-off-state {
961 pins = "sdc1_c 960 pins = "sdc1_clk";
962 bias-disable; 961 bias-disable;
963 drive-strength 962 drive-strength = <2>;
964 }; 963 };
965 964
966 sdc1_cmd_on: cmd-on-st 965 sdc1_cmd_on: cmd-on-state {
967 pins = "sdc1_c 966 pins = "sdc1_cmd";
968 bias-pull-up; 967 bias-pull-up;
969 drive-strength 968 drive-strength = <8>;
970 }; 969 };
971 970
972 sdc1_cmd_off: cmd-off- 971 sdc1_cmd_off: cmd-off-state {
973 pins = "sdc1_c 972 pins = "sdc1_cmd";
974 bias-pull-up; 973 bias-pull-up;
975 drive-strength 974 drive-strength = <2>;
976 }; 975 };
977 976
978 sdc1_data_on: data-on- 977 sdc1_data_on: data-on-state {
979 pins = "sdc1_d 978 pins = "sdc1_data";
980 bias-pull-up; 979 bias-pull-up;
981 drive-strength 980 drive-strength = <8>;
982 }; 981 };
983 982
984 sdc1_data_off: data-of 983 sdc1_data_off: data-off-state {
985 pins = "sdc1_d 984 pins = "sdc1_data";
986 bias-pull-up; 985 bias-pull-up;
987 drive-strength 986 drive-strength = <2>;
988 }; 987 };
989 988
990 sdc1_rclk_on: rclk-on- 989 sdc1_rclk_on: rclk-on-state {
991 pins = "sdc1_r 990 pins = "sdc1_rclk";
992 bias-pull-down 991 bias-pull-down;
993 }; 992 };
994 993
995 sdc1_rclk_off: rclk-of 994 sdc1_rclk_off: rclk-off-state {
996 pins = "sdc1_r 995 pins = "sdc1_rclk";
997 bias-pull-down 996 bias-pull-down;
998 }; 997 };
999 998
1000 sdc2_clk_on: sdc2-clk 999 sdc2_clk_on: sdc2-clk-on-state {
1001 pins = "sdc2_ 1000 pins = "sdc2_clk";
1002 bias-disable; 1001 bias-disable;
1003 drive-strengt 1002 drive-strength = <10>;
1004 }; 1003 };
1005 1004
1006 sdc2_clk_off: sdc2-cl 1005 sdc2_clk_off: sdc2-clk-off-state {
1007 pins = "sdc2_ 1006 pins = "sdc2_clk";
1008 bias-disable; 1007 bias-disable;
1009 drive-strengt 1008 drive-strength = <2>;
1010 }; 1009 };
1011 1010
1012 sdc2_cmd_on: sdc2-cmd 1011 sdc2_cmd_on: sdc2-cmd-on-state {
1013 pins = "sdc2_ 1012 pins = "sdc2_cmd";
1014 bias-pull-up; 1013 bias-pull-up;
1015 drive-strengt 1014 drive-strength = <10>;
1016 }; 1015 };
1017 1016
1018 sdc2_cmd_off: sdc2-cm 1017 sdc2_cmd_off: sdc2-cmd-off-state {
1019 pins = "sdc2_ 1018 pins = "sdc2_cmd";
1020 bias-pull-up; 1019 bias-pull-up;
1021 drive-strengt 1020 drive-strength = <2>;
1022 }; 1021 };
1023 1022
1024 sdc2_data_on: sdc2-da 1023 sdc2_data_on: sdc2-data-on-state {
1025 pins = "sdc2_ 1024 pins = "sdc2_data";
1026 bias-pull-up; 1025 bias-pull-up;
1027 drive-strengt 1026 drive-strength = <10>;
1028 }; 1027 };
1029 1028
1030 sdc2_data_off: sdc2-d 1029 sdc2_data_off: sdc2-data-off-state {
1031 pins = "sdc2_ 1030 pins = "sdc2_data";
1032 bias-pull-up; 1031 bias-pull-up;
1033 drive-strengt 1032 drive-strength = <2>;
1034 }; 1033 };
1035 }; 1034 };
1036 1035
1037 mmcc: clock-controller@fd8c00 1036 mmcc: clock-controller@fd8c0000 {
1038 compatible = "qcom,mm 1037 compatible = "qcom,mmcc-msm8994";
1039 reg = <0xfd8c0000 0x5 1038 reg = <0xfd8c0000 0x5200>;
1040 #clock-cells = <1>; 1039 #clock-cells = <1>;
1041 #reset-cells = <1>; 1040 #reset-cells = <1>;
1042 #power-domain-cells = 1041 #power-domain-cells = <1>;
1043 1042
1044 clock-names = "xo", 1043 clock-names = "xo",
1045 "gpll0" 1044 "gpll0",
1046 "mmssno 1045 "mmssnoc_ahb",
1047 "oxili_ 1046 "oxili_gfx3d_clk_src",
1048 "dsi0pl 1047 "dsi0pll",
1049 "dsi0pl 1048 "dsi0pllbyte",
1050 "dsi1pl 1049 "dsi1pll",
1051 "dsi1pl 1050 "dsi1pllbyte",
1052 "hdmipl 1051 "hdmipll";
1053 clocks = <&xo_board>, 1052 clocks = <&xo_board>,
1054 <&gcc GPLL0_ 1053 <&gcc GPLL0_OUT_MMSSCC>,
1055 <&rpmcc RPM_ 1054 <&rpmcc RPM_SMD_MMSSNOC_AHB_CLK>,
1056 <&rpmcc RPM_ 1055 <&rpmcc RPM_SMD_GFX3D_CLK_SRC>,
1057 <0>, 1056 <0>,
1058 <0>, 1057 <0>,
1059 <0>, 1058 <0>,
1060 <0>, 1059 <0>,
1061 <0>; 1060 <0>;
1062 1061
1063 assigned-clocks = <&m 1062 assigned-clocks = <&mmcc MMPLL0_PLL>,
1064 <&m 1063 <&mmcc MMPLL1_PLL>,
1065 <&m 1064 <&mmcc MMPLL3_PLL>,
1066 <&m 1065 <&mmcc MMPLL4_PLL>,
1067 <&m 1066 <&mmcc MMPLL5_PLL>;
1068 assigned-clock-rates 1067 assigned-clock-rates = <800000000>,
1069 1068 <1167000000>,
1070 1069 <1020000000>,
1071 1070 <960000000>,
1072 1071 <600000000>;
1073 }; 1072 };
1074 1073
1075 ocmem: sram@fdd00000 { 1074 ocmem: sram@fdd00000 {
1076 compatible = "qcom,ms 1075 compatible = "qcom,msm8974-ocmem";
1077 reg = <0xfdd00000 0x2 1076 reg = <0xfdd00000 0x2000>,
1078 <0xfec00000 0x2 1077 <0xfec00000 0x200000>;
1079 reg-names = "ctrl", " 1078 reg-names = "ctrl", "mem";
1080 ranges = <0 0xfec0000 1079 ranges = <0 0xfec00000 0x200000>;
1081 clocks = <&rpmcc RPM_ 1080 clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>,
1082 <&mmcc OCMEM 1081 <&mmcc OCMEMCX_OCMEMNOC_CLK>;
1083 clock-names = "core", 1082 clock-names = "core", "iface";
1084 1083
1085 #address-cells = <1>; 1084 #address-cells = <1>;
1086 #size-cells = <1>; 1085 #size-cells = <1>;
1087 1086
1088 gmu_sram: gmu-sram@0 1087 gmu_sram: gmu-sram@0 {
1089 reg = <0x0 0x 1088 reg = <0x0 0x180000>;
1090 }; 1089 };
1091 }; 1090 };
1092 }; 1091 };
1093 1092
1094 timer: timer { 1093 timer: timer {
1095 compatible = "arm,armv8-timer 1094 compatible = "arm,armv8-timer";
1096 interrupts = <GIC_PPI 2 (GIC_ !! 1095 interrupts = <GIC_PPI 2 0xff08>,
1097 <GIC_PPI 3 (GIC_ !! 1096 <GIC_PPI 3 0xff08>,
1098 <GIC_PPI 4 (GIC_ !! 1097 <GIC_PPI 4 0xff08>,
1099 <GIC_PPI 1 (GIC_ !! 1098 <GIC_PPI 1 0xff08>;
1100 }; 1099 };
1101 1100
1102 vph_pwr: vph-pwr-regulator { 1101 vph_pwr: vph-pwr-regulator {
1103 compatible = "regulator-fixed 1102 compatible = "regulator-fixed";
1104 regulator-name = "vph_pwr"; 1103 regulator-name = "vph_pwr";
1105 1104
1106 regulator-min-microvolt = <36 1105 regulator-min-microvolt = <3600000>;
1107 regulator-max-microvolt = <36 1106 regulator-max-microvolt = <3600000>;
1108 1107
1109 regulator-always-on; 1108 regulator-always-on;
1110 }; 1109 };
1111 }; 1110 };
1112 1111
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