1 // SPDX-License-Identifier: GPL-2.0-only 1 // SPDX-License-Identifier: GPL-2.0-only
2 /* 2 /*
3 * Copyright (c) 2013-2016, The Linux Foundati 3 * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
4 */ 4 */
5 5
6 #include <dt-bindings/interrupt-controller/arm 6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,gcc-msm8994.h 7 #include <dt-bindings/clock/qcom,gcc-msm8994.h>
8 #include <dt-bindings/clock/qcom,mmcc-msm8994. 8 #include <dt-bindings/clock/qcom,mmcc-msm8994.h>
9 #include <dt-bindings/clock/qcom,rpmcc.h> 9 #include <dt-bindings/clock/qcom,rpmcc.h>
10 #include <dt-bindings/gpio/gpio.h> 10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/power/qcom-rpmpd.h> 11 #include <dt-bindings/power/qcom-rpmpd.h>
12 12
13 / { 13 / {
14 interrupt-parent = <&intc>; 14 interrupt-parent = <&intc>;
15 15
16 #address-cells = <2>; 16 #address-cells = <2>;
17 #size-cells = <2>; 17 #size-cells = <2>;
18 18
19 aliases { 19 aliases {
20 mmc1 = &sdhc1; 20 mmc1 = &sdhc1;
21 mmc2 = &sdhc2; 21 mmc2 = &sdhc2;
22 }; 22 };
23 23
24 chosen { }; 24 chosen { };
25 25
26 clocks { 26 clocks {
27 xo_board: xo-board { 27 xo_board: xo-board {
28 compatible = "fixed-cl 28 compatible = "fixed-clock";
29 #clock-cells = <0>; 29 #clock-cells = <0>;
30 clock-frequency = <192 30 clock-frequency = <19200000>;
31 clock-output-names = " 31 clock-output-names = "xo_board";
32 }; 32 };
33 33
34 sleep_clk: sleep-clk { 34 sleep_clk: sleep-clk {
35 compatible = "fixed-cl 35 compatible = "fixed-clock";
36 #clock-cells = <0>; 36 #clock-cells = <0>;
37 clock-frequency = <327 37 clock-frequency = <32768>;
38 clock-output-names = " 38 clock-output-names = "sleep_clk";
39 }; 39 };
40 }; 40 };
41 41
42 cpus { 42 cpus {
43 #address-cells = <2>; 43 #address-cells = <2>;
44 #size-cells = <0>; 44 #size-cells = <0>;
45 45
46 CPU0: cpu@0 { 46 CPU0: cpu@0 {
47 device_type = "cpu"; 47 device_type = "cpu";
48 compatible = "arm,cort 48 compatible = "arm,cortex-a53";
49 reg = <0x0 0x0>; 49 reg = <0x0 0x0>;
50 enable-method = "psci" 50 enable-method = "psci";
51 next-level-cache = <&L 51 next-level-cache = <&L2_0>;
52 L2_0: l2-cache { 52 L2_0: l2-cache {
53 compatible = " 53 compatible = "cache";
54 cache-level = 54 cache-level = <2>;
55 cache-unified; 55 cache-unified;
56 }; 56 };
57 }; 57 };
58 58
59 CPU1: cpu@1 { 59 CPU1: cpu@1 {
60 device_type = "cpu"; 60 device_type = "cpu";
61 compatible = "arm,cort 61 compatible = "arm,cortex-a53";
62 reg = <0x0 0x1>; 62 reg = <0x0 0x1>;
63 enable-method = "psci" 63 enable-method = "psci";
64 next-level-cache = <&L 64 next-level-cache = <&L2_0>;
65 }; 65 };
66 66
67 CPU2: cpu@2 { 67 CPU2: cpu@2 {
68 device_type = "cpu"; 68 device_type = "cpu";
69 compatible = "arm,cort 69 compatible = "arm,cortex-a53";
70 reg = <0x0 0x2>; 70 reg = <0x0 0x2>;
71 enable-method = "psci" 71 enable-method = "psci";
72 next-level-cache = <&L 72 next-level-cache = <&L2_0>;
73 }; 73 };
74 74
75 CPU3: cpu@3 { 75 CPU3: cpu@3 {
76 device_type = "cpu"; 76 device_type = "cpu";
77 compatible = "arm,cort 77 compatible = "arm,cortex-a53";
78 reg = <0x0 0x3>; 78 reg = <0x0 0x3>;
79 enable-method = "psci" 79 enable-method = "psci";
80 next-level-cache = <&L 80 next-level-cache = <&L2_0>;
81 }; 81 };
82 82
83 CPU4: cpu@100 { 83 CPU4: cpu@100 {
84 device_type = "cpu"; 84 device_type = "cpu";
85 compatible = "arm,cort 85 compatible = "arm,cortex-a57";
86 reg = <0x0 0x100>; 86 reg = <0x0 0x100>;
87 enable-method = "psci" 87 enable-method = "psci";
88 next-level-cache = <&L 88 next-level-cache = <&L2_1>;
89 L2_1: l2-cache { 89 L2_1: l2-cache {
90 compatible = " 90 compatible = "cache";
91 cache-level = 91 cache-level = <2>;
92 cache-unified; 92 cache-unified;
93 }; 93 };
94 }; 94 };
95 95
96 CPU5: cpu@101 { 96 CPU5: cpu@101 {
97 device_type = "cpu"; 97 device_type = "cpu";
98 compatible = "arm,cort 98 compatible = "arm,cortex-a57";
99 reg = <0x0 0x101>; 99 reg = <0x0 0x101>;
100 enable-method = "psci" 100 enable-method = "psci";
101 next-level-cache = <&L 101 next-level-cache = <&L2_1>;
102 }; 102 };
103 103
104 CPU6: cpu@102 { 104 CPU6: cpu@102 {
105 device_type = "cpu"; 105 device_type = "cpu";
106 compatible = "arm,cort 106 compatible = "arm,cortex-a57";
107 reg = <0x0 0x102>; 107 reg = <0x0 0x102>;
108 enable-method = "psci" 108 enable-method = "psci";
109 next-level-cache = <&L 109 next-level-cache = <&L2_1>;
110 }; 110 };
111 111
112 CPU7: cpu@103 { 112 CPU7: cpu@103 {
113 device_type = "cpu"; 113 device_type = "cpu";
114 compatible = "arm,cort 114 compatible = "arm,cortex-a57";
115 reg = <0x0 0x103>; 115 reg = <0x0 0x103>;
116 enable-method = "psci" 116 enable-method = "psci";
117 next-level-cache = <&L 117 next-level-cache = <&L2_1>;
118 }; 118 };
119 119
120 cpu-map { 120 cpu-map {
121 cluster0 { 121 cluster0 {
122 core0 { 122 core0 {
123 cpu = 123 cpu = <&CPU0>;
124 }; 124 };
125 125
126 core1 { 126 core1 {
127 cpu = 127 cpu = <&CPU1>;
128 }; 128 };
129 129
130 core2 { 130 core2 {
131 cpu = 131 cpu = <&CPU2>;
132 }; 132 };
133 133
134 core3 { 134 core3 {
135 cpu = 135 cpu = <&CPU3>;
136 }; 136 };
137 }; 137 };
138 138
139 cluster1 { 139 cluster1 {
140 core0 { 140 core0 {
141 cpu = 141 cpu = <&CPU4>;
142 }; 142 };
143 143
144 core1 { 144 core1 {
145 cpu = 145 cpu = <&CPU5>;
146 }; 146 };
147 147
148 cpu6_map: core 148 cpu6_map: core2 {
149 cpu = 149 cpu = <&CPU6>;
150 }; 150 };
151 151
152 cpu7_map: core 152 cpu7_map: core3 {
153 cpu = 153 cpu = <&CPU7>;
154 }; 154 };
155 }; 155 };
156 }; 156 };
157 }; 157 };
158 158
159 firmware { 159 firmware {
160 scm { 160 scm {
161 compatible = "qcom,scm 161 compatible = "qcom,scm-msm8994", "qcom,scm";
162 }; 162 };
163 }; 163 };
164 164
165 memory@80000000 { 165 memory@80000000 {
166 device_type = "memory"; 166 device_type = "memory";
167 /* We expect the bootloader to 167 /* We expect the bootloader to fill in the reg */
168 reg = <0 0x80000000 0 0>; 168 reg = <0 0x80000000 0 0>;
169 }; 169 };
170 170
171 pmu { 171 pmu {
172 compatible = "arm,cortex-a53-p 172 compatible = "arm,cortex-a53-pmu";
173 interrupts = <GIC_PPI 7 (GIC_C 173 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4)| IRQ_TYPE_LEVEL_HIGH)>;
174 }; 174 };
175 175
176 psci { 176 psci {
177 compatible = "arm,psci-0.2"; 177 compatible = "arm,psci-0.2";
178 method = "hvc"; 178 method = "hvc";
179 }; 179 };
180 180
181 rpm: remoteproc { <<
182 compatible = "qcom,msm8994-rpm <<
183 <<
184 smd-edge { <<
185 interrupts = <GIC_SPI <<
186 mboxes = <&apcs 0>; <<
187 qcom,smd-edge = <15>; <<
188 qcom,remote-pid = <6>; <<
189 <<
190 rpm_requests: rpm-requ <<
191 compatible = " <<
192 qcom,smd-chann <<
193 <<
194 rpmcc: clock-c <<
195 compat <<
196 #clock <<
197 }; <<
198 <<
199 rpmpd: power-c <<
200 compat <<
201 #power <<
202 operat <<
203 <<
204 rpmpd_ <<
205 <<
206 <<
207 <<
208 <<
209 <<
210 <<
211 <<
212 <<
213 <<
214 <<
215 <<
216 <<
217 <<
218 <<
219 <<
220 <<
221 <<
222 <<
223 <<
224 <<
225 }; <<
226 }; <<
227 }; <<
228 }; <<
229 }; <<
230 <<
231 reserved-memory { 181 reserved-memory {
232 #address-cells = <2>; 182 #address-cells = <2>;
233 #size-cells = <2>; 183 #size-cells = <2>;
234 ranges; 184 ranges;
235 185
236 dfps_data_mem: dfps-data@34000 !! 186 dfps_data_mem: dfps_data_mem@3400000 {
237 reg = <0 0x03400000 0 187 reg = <0 0x03400000 0 0x1000>;
238 no-map; 188 no-map;
239 }; 189 };
240 190
241 cont_splash_mem: memory@340100 191 cont_splash_mem: memory@3401000 {
242 reg = <0 0x03401000 0 192 reg = <0 0x03401000 0 0x2200000>;
243 no-map; 193 no-map;
244 }; 194 };
245 195
246 smem_mem: smem@6a00000 { !! 196 smem_mem: smem_region@6a00000 {
247 reg = <0 0x06a00000 0 197 reg = <0 0x06a00000 0 0x200000>;
248 no-map; 198 no-map;
249 }; 199 };
250 200
251 mpss_mem: memory@7000000 { 201 mpss_mem: memory@7000000 {
252 reg = <0 0x07000000 0 202 reg = <0 0x07000000 0 0x5a00000>;
253 no-map; 203 no-map;
254 }; 204 };
255 205
256 peripheral_region: memory@ca00 206 peripheral_region: memory@ca00000 {
257 reg = <0 0x0ca00000 0 207 reg = <0 0x0ca00000 0 0x1f00000>;
258 no-map; 208 no-map;
259 }; 209 };
260 210
261 rmtfs_mem: memory@c6400000 { 211 rmtfs_mem: memory@c6400000 {
262 compatible = "qcom,rmt 212 compatible = "qcom,rmtfs-mem";
263 reg = <0 0xc6400000 0 213 reg = <0 0xc6400000 0 0x180000>;
264 no-map; 214 no-map;
265 215
266 qcom,client-id = <1>; 216 qcom,client-id = <1>;
267 }; 217 };
268 218
269 mba_mem: memory@c6700000 { 219 mba_mem: memory@c6700000 {
270 reg = <0 0xc6700000 0 220 reg = <0 0xc6700000 0 0x100000>;
271 no-map; 221 no-map;
272 }; 222 };
273 223
274 audio_mem: memory@c7000000 { 224 audio_mem: memory@c7000000 {
275 reg = <0 0xc7000000 0 225 reg = <0 0xc7000000 0 0x800000>;
276 no-map; 226 no-map;
277 }; 227 };
278 228
279 adsp_mem: memory@c9400000 { 229 adsp_mem: memory@c9400000 {
280 reg = <0 0xc9400000 0 230 reg = <0 0xc9400000 0 0x3f00000>;
281 no-map; 231 no-map;
282 }; 232 };
283 233
284 res_hyp_mem: reserved@6c00000 !! 234 reserved@6c00000 {
285 reg = <0 0x06c00000 0 235 reg = <0 0x06c00000 0 0x400000>;
286 no-map; 236 no-map;
287 }; 237 };
288 }; 238 };
289 239
>> 240 smd {
>> 241 compatible = "qcom,smd";
>> 242 rpm {
>> 243 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
>> 244 qcom,ipc = <&apcs 8 0>;
>> 245 qcom,smd-edge = <15>;
>> 246 qcom,remote-pid = <6>;
>> 247
>> 248 rpm_requests: rpm-requests {
>> 249 compatible = "qcom,rpm-msm8994";
>> 250 qcom,smd-channels = "rpm_requests";
>> 251
>> 252 rpmcc: clock-controller {
>> 253 compatible = "qcom,rpmcc-msm8994", "qcom,rpmcc";
>> 254 #clock-cells = <1>;
>> 255 };
>> 256
>> 257 rpmpd: power-controller {
>> 258 compatible = "qcom,msm8994-rpmpd";
>> 259 #power-domain-cells = <1>;
>> 260 operating-points-v2 = <&rpmpd_opp_table>;
>> 261
>> 262 rpmpd_opp_table: opp-table {
>> 263 compatible = "operating-points-v2";
>> 264
>> 265 rpmpd_opp_ret: opp1 {
>> 266 opp-level = <1>;
>> 267 };
>> 268 rpmpd_opp_svs_krait: opp2 {
>> 269 opp-level = <2>;
>> 270 };
>> 271 rpmpd_opp_svs_soc: opp3 {
>> 272 opp-level = <3>;
>> 273 };
>> 274 rpmpd_opp_nom: opp4 {
>> 275 opp-level = <4>;
>> 276 };
>> 277 rpmpd_opp_turbo: opp5 {
>> 278 opp-level = <5>;
>> 279 };
>> 280 rpmpd_opp_super_turbo: opp6 {
>> 281 opp-level = <6>;
>> 282 };
>> 283 };
>> 284 };
>> 285 };
>> 286 };
>> 287 };
>> 288
290 smem { 289 smem {
291 compatible = "qcom,smem"; 290 compatible = "qcom,smem";
292 memory-region = <&smem_mem>; 291 memory-region = <&smem_mem>;
293 qcom,rpm-msg-ram = <&rpm_msg_r 292 qcom,rpm-msg-ram = <&rpm_msg_ram>;
294 hwlocks = <&tcsr_mutex 3>; 293 hwlocks = <&tcsr_mutex 3>;
295 }; 294 };
296 295
297 smp2p-lpass { 296 smp2p-lpass {
298 compatible = "qcom,smp2p"; 297 compatible = "qcom,smp2p";
299 qcom,smem = <443>, <429>; 298 qcom,smem = <443>, <429>;
300 299
301 interrupts = <GIC_SPI 158 IRQ_ 300 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
302 301
303 mboxes = <&apcs 10>; !! 302 qcom,ipc = <&apcs 8 10>;
304 303
305 qcom,local-pid = <0>; 304 qcom,local-pid = <0>;
306 qcom,remote-pid = <2>; 305 qcom,remote-pid = <2>;
307 306
308 adsp_smp2p_out: master-kernel 307 adsp_smp2p_out: master-kernel {
309 qcom,entry-name = "mas 308 qcom,entry-name = "master-kernel";
310 #qcom,smem-state-cells 309 #qcom,smem-state-cells = <1>;
311 }; 310 };
312 311
313 adsp_smp2p_in: slave-kernel { 312 adsp_smp2p_in: slave-kernel {
314 qcom,entry-name = "sla 313 qcom,entry-name = "slave-kernel";
315 314
316 interrupt-controller; 315 interrupt-controller;
317 #interrupt-cells = <2> 316 #interrupt-cells = <2>;
318 }; 317 };
319 }; 318 };
320 319
321 smp2p-modem { 320 smp2p-modem {
322 compatible = "qcom,smp2p"; 321 compatible = "qcom,smp2p";
323 qcom,smem = <435>, <428>; 322 qcom,smem = <435>, <428>;
324 323
325 interrupt-parent = <&intc>; 324 interrupt-parent = <&intc>;
326 interrupts = <GIC_SPI 27 IRQ_T 325 interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>;
327 326
328 mboxes = <&apcs 14>; !! 327 qcom,ipc = <&apcs 8 14>;
329 328
330 qcom,local-pid = <0>; 329 qcom,local-pid = <0>;
331 qcom,remote-pid = <1>; 330 qcom,remote-pid = <1>;
332 331
333 modem_smp2p_out: master-kernel 332 modem_smp2p_out: master-kernel {
334 qcom,entry-name = "mas 333 qcom,entry-name = "master-kernel";
335 #qcom,smem-state-cells 334 #qcom,smem-state-cells = <1>;
336 }; 335 };
337 336
338 modem_smp2p_in: slave-kernel { 337 modem_smp2p_in: slave-kernel {
339 qcom,entry-name = "sla 338 qcom,entry-name = "slave-kernel";
340 339
341 interrupt-controller; 340 interrupt-controller;
342 #interrupt-cells = <2> 341 #interrupt-cells = <2>;
343 }; 342 };
344 }; 343 };
345 344
346 soc: soc@0 { 345 soc: soc@0 {
347 #address-cells = <1>; 346 #address-cells = <1>;
348 #size-cells = <1>; 347 #size-cells = <1>;
349 ranges = <0 0 0 0xffffffff>; 348 ranges = <0 0 0 0xffffffff>;
350 compatible = "simple-bus"; 349 compatible = "simple-bus";
351 350
352 intc: interrupt-controller@f90 351 intc: interrupt-controller@f9000000 {
353 compatible = "qcom,msm 352 compatible = "qcom,msm-qgic2";
354 interrupt-controller; 353 interrupt-controller;
355 #interrupt-cells = <3> 354 #interrupt-cells = <3>;
356 reg = <0xf9000000 0x10 355 reg = <0xf9000000 0x1000>,
357 <0xf9002000 0x10 356 <0xf9002000 0x1000>;
358 }; 357 };
359 358
360 apcs: mailbox@f900d000 { 359 apcs: mailbox@f900d000 {
361 compatible = "qcom,msm 360 compatible = "qcom,msm8994-apcs-kpss-global", "syscon";
362 reg = <0xf900d000 0x20 361 reg = <0xf900d000 0x2000>;
363 #mbox-cells = <1>; 362 #mbox-cells = <1>;
364 }; 363 };
365 364
366 watchdog@f9017000 { 365 watchdog@f9017000 {
367 compatible = "qcom,aps 366 compatible = "qcom,apss-wdt-msm8994", "qcom,kpss-wdt";
368 reg = <0xf9017000 0x10 367 reg = <0xf9017000 0x1000>;
369 interrupts = <GIC_SPI 368 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>,
370 <GIC_SPI 369 <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>;
371 clocks = <&sleep_clk>; 370 clocks = <&sleep_clk>;
372 timeout-sec = <10>; 371 timeout-sec = <10>;
373 }; 372 };
374 373
375 timer@f9020000 { 374 timer@f9020000 {
376 #address-cells = <1>; 375 #address-cells = <1>;
377 #size-cells = <1>; 376 #size-cells = <1>;
378 ranges; 377 ranges;
379 compatible = "arm,armv 378 compatible = "arm,armv7-timer-mem";
380 reg = <0xf9020000 0x10 379 reg = <0xf9020000 0x1000>;
381 380
382 frame@f9021000 { 381 frame@f9021000 {
383 frame-number = 382 frame-number = <0>;
384 interrupts = < 383 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
385 < 384 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
386 reg = <0xf9021 385 reg = <0xf9021000 0x1000>,
387 <0xf9022 386 <0xf9022000 0x1000>;
388 }; 387 };
389 388
390 frame@f9023000 { 389 frame@f9023000 {
391 frame-number = 390 frame-number = <1>;
392 interrupts = < 391 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
393 reg = <0xf9023 392 reg = <0xf9023000 0x1000>;
394 status = "disa 393 status = "disabled";
395 }; 394 };
396 395
397 frame@f9024000 { 396 frame@f9024000 {
398 frame-number = 397 frame-number = <2>;
399 interrupts = < 398 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
400 reg = <0xf9024 399 reg = <0xf9024000 0x1000>;
401 status = "disa 400 status = "disabled";
402 }; 401 };
403 402
404 frame@f9025000 { 403 frame@f9025000 {
405 frame-number = 404 frame-number = <3>;
406 interrupts = < 405 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
407 reg = <0xf9025 406 reg = <0xf9025000 0x1000>;
408 status = "disa 407 status = "disabled";
409 }; 408 };
410 409
411 frame@f9026000 { 410 frame@f9026000 {
412 frame-number = 411 frame-number = <4>;
413 interrupts = < 412 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
414 reg = <0xf9026 413 reg = <0xf9026000 0x1000>;
415 status = "disa 414 status = "disabled";
416 }; 415 };
417 416
418 frame@f9027000 { 417 frame@f9027000 {
419 frame-number = 418 frame-number = <5>;
420 interrupts = < 419 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
421 reg = <0xf9027 420 reg = <0xf9027000 0x1000>;
422 status = "disa 421 status = "disabled";
423 }; 422 };
424 423
425 frame@f9028000 { 424 frame@f9028000 {
426 frame-number = 425 frame-number = <6>;
427 interrupts = < 426 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
428 reg = <0xf9028 427 reg = <0xf9028000 0x1000>;
429 status = "disa 428 status = "disabled";
430 }; 429 };
431 }; 430 };
432 431
433 usb3: usb@f92f8800 { 432 usb3: usb@f92f8800 {
434 compatible = "qcom,msm 433 compatible = "qcom,msm8994-dwc3", "qcom,dwc3";
435 reg = <0xf92f8800 0x40 434 reg = <0xf92f8800 0x400>;
436 #address-cells = <1>; 435 #address-cells = <1>;
437 #size-cells = <1>; 436 #size-cells = <1>;
438 ranges; 437 ranges;
439 438
440 clocks = <&gcc GCC_USB 439 clocks = <&gcc GCC_USB30_MASTER_CLK>,
441 <&gcc GCC_SYS 440 <&gcc GCC_SYS_NOC_USB3_AXI_CLK>,
442 <&gcc GCC_USB 441 <&gcc GCC_USB30_SLEEP_CLK>,
443 <&gcc GCC_USB 442 <&gcc GCC_USB30_MOCK_UTMI_CLK>;
444 clock-names = "core", 443 clock-names = "core",
445 "iface", 444 "iface",
446 "sleep", 445 "sleep",
447 "mock_ut 446 "mock_utmi";
448 447
449 assigned-clocks = <&gc 448 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
450 <&gc 449 <&gcc GCC_USB30_MASTER_CLK>;
451 assigned-clock-rates = 450 assigned-clock-rates = <19200000>, <120000000>;
452 451
453 power-domains = <&gcc 452 power-domains = <&gcc USB30_GDSC>;
454 qcom,select-utmi-as-pi 453 qcom,select-utmi-as-pipe-clk;
455 454
456 usb@f9200000 { 455 usb@f9200000 {
457 compatible = " 456 compatible = "snps,dwc3";
458 reg = <0xf9200 457 reg = <0xf9200000 0xcc00>;
459 interrupts = < !! 458 interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>;
460 snps,dis_u2_su 459 snps,dis_u2_susphy_quirk;
461 snps,dis_enbls 460 snps,dis_enblslpm_quirk;
462 maximum-speed 461 maximum-speed = "high-speed";
463 dr_mode = "per 462 dr_mode = "peripheral";
464 }; 463 };
465 }; 464 };
466 465
467 sdhc1: mmc@f9824900 { 466 sdhc1: mmc@f9824900 {
468 compatible = "qcom,msm 467 compatible = "qcom,msm8994-sdhci", "qcom,sdhci-msm-v4";
469 reg = <0xf9824900 0x1a 468 reg = <0xf9824900 0x1a0>, <0xf9824000 0x800>;
470 reg-names = "hc", "cor 469 reg-names = "hc", "core";
471 470
472 interrupts = <GIC_SPI 471 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
473 <GIC_SPI 472 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
474 interrupt-names = "hc_ 473 interrupt-names = "hc_irq", "pwr_irq";
475 474
476 clocks = <&gcc GCC_SDC 475 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
477 <&gcc GCC_SDC 476 <&gcc GCC_SDCC1_APPS_CLK>,
478 <&xo_board>; 477 <&xo_board>;
479 clock-names = "iface", 478 clock-names = "iface", "core", "xo";
480 479
481 pinctrl-names = "defau 480 pinctrl-names = "default", "sleep";
482 pinctrl-0 = <&sdc1_clk 481 pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>;
483 pinctrl-1 = <&sdc1_clk 482 pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>;
484 483
485 bus-width = <8>; 484 bus-width = <8>;
486 non-removable; 485 non-removable;
487 status = "disabled"; 486 status = "disabled";
488 }; 487 };
489 488
490 sdhc2: mmc@f98a4900 { 489 sdhc2: mmc@f98a4900 {
491 compatible = "qcom,msm 490 compatible = "qcom,msm8994-sdhci", "qcom,sdhci-msm-v4";
492 reg = <0xf98a4900 0x11 491 reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
493 reg-names = "hc", "cor 492 reg-names = "hc", "core";
494 493
495 interrupts = <GIC_SPI 494 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
496 <GIC_SPI 221 I 495 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
497 interrupt-names = "hc_ 496 interrupt-names = "hc_irq", "pwr_irq";
498 497
499 clocks = <&gcc GCC_SDC 498 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
500 <&gcc GCC_SDC 499 <&gcc GCC_SDCC2_APPS_CLK>,
501 <&xo_board>; 500 <&xo_board>;
502 clock-names = "iface", 501 clock-names = "iface", "core", "xo";
503 502
504 pinctrl-names = "defau 503 pinctrl-names = "default", "sleep";
505 pinctrl-0 = <&sdc2_clk 504 pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>;
506 pinctrl-1 = <&sdc2_clk 505 pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>;
507 506
508 cd-gpios = <&tlmm 100 507 cd-gpios = <&tlmm 100 GPIO_ACTIVE_HIGH>;
509 bus-width = <4>; 508 bus-width = <4>;
510 status = "disabled"; 509 status = "disabled";
511 }; 510 };
512 511
513 blsp1_dma: dma-controller@f990 512 blsp1_dma: dma-controller@f9904000 {
514 compatible = "qcom,bam 513 compatible = "qcom,bam-v1.7.0";
515 reg = <0xf9904000 0x19 514 reg = <0xf9904000 0x19000>;
516 interrupts = <GIC_SPI 515 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
517 clocks = <&gcc GCC_BLS 516 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
518 clock-names = "bam_clk 517 clock-names = "bam_clk";
519 #dma-cells = <1>; 518 #dma-cells = <1>;
520 qcom,ee = <0>; 519 qcom,ee = <0>;
521 qcom,controlled-remote 520 qcom,controlled-remotely;
522 num-channels = <24>; 521 num-channels = <24>;
523 qcom,num-ees = <4>; 522 qcom,num-ees = <4>;
524 }; 523 };
525 524
526 blsp1_uart2: serial@f991e000 { 525 blsp1_uart2: serial@f991e000 {
527 compatible = "qcom,msm 526 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
528 reg = <0xf991e000 0x10 527 reg = <0xf991e000 0x1000>;
529 interrupts = <GIC_SPI 528 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
530 clock-names = "core", 529 clock-names = "core", "iface";
531 clocks = <&gcc GCC_BLS 530 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
532 <&gcc GCC_BLS 531 <&gcc GCC_BLSP1_AHB_CLK>;
533 pinctrl-names = "defau 532 pinctrl-names = "default", "sleep";
534 pinctrl-0 = <&blsp1_ua 533 pinctrl-0 = <&blsp1_uart2_default>;
535 pinctrl-1 = <&blsp1_ua 534 pinctrl-1 = <&blsp1_uart2_sleep>;
536 status = "disabled"; 535 status = "disabled";
537 }; 536 };
538 537
539 blsp1_i2c1: i2c@f9923000 { 538 blsp1_i2c1: i2c@f9923000 {
540 compatible = "qcom,i2c 539 compatible = "qcom,i2c-qup-v2.2.1";
541 reg = <0xf9923000 0x50 540 reg = <0xf9923000 0x500>;
542 interrupts = <GIC_SPI 541 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
543 clocks = <&gcc GCC_BLS 542 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
544 <&gcc GCC_BLS 543 <&gcc GCC_BLSP1_AHB_CLK>;
545 clock-names = "core", 544 clock-names = "core", "iface";
546 clock-frequency = <400 545 clock-frequency = <400000>;
547 dmas = <&blsp1_dma 12> 546 dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
548 dma-names = "tx", "rx" 547 dma-names = "tx", "rx";
549 pinctrl-names = "defau 548 pinctrl-names = "default", "sleep";
550 pinctrl-0 = <&i2c1_def 549 pinctrl-0 = <&i2c1_default>;
551 pinctrl-1 = <&i2c1_sle 550 pinctrl-1 = <&i2c1_sleep>;
552 #address-cells = <1>; 551 #address-cells = <1>;
553 #size-cells = <0>; 552 #size-cells = <0>;
554 status = "disabled"; 553 status = "disabled";
555 }; 554 };
556 555
557 blsp1_spi1: spi@f9923000 { 556 blsp1_spi1: spi@f9923000 {
558 compatible = "qcom,spi 557 compatible = "qcom,spi-qup-v2.2.1";
559 reg = <0xf9923000 0x50 558 reg = <0xf9923000 0x500>;
560 interrupts = <GIC_SPI 559 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
561 clocks = <&gcc GCC_BLS 560 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
562 <&gcc GCC_BLS 561 <&gcc GCC_BLSP1_AHB_CLK>;
563 clock-names = "core", 562 clock-names = "core", "iface";
564 dmas = <&blsp1_dma 12> 563 dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
565 dma-names = "tx", "rx" 564 dma-names = "tx", "rx";
566 pinctrl-names = "defau 565 pinctrl-names = "default", "sleep";
567 pinctrl-0 = <&blsp1_sp 566 pinctrl-0 = <&blsp1_spi1_default>;
568 pinctrl-1 = <&blsp1_sp 567 pinctrl-1 = <&blsp1_spi1_sleep>;
569 #address-cells = <1>; 568 #address-cells = <1>;
570 #size-cells = <0>; 569 #size-cells = <0>;
571 status = "disabled"; 570 status = "disabled";
572 }; 571 };
573 572
574 blsp1_i2c2: i2c@f9924000 { 573 blsp1_i2c2: i2c@f9924000 {
575 compatible = "qcom,i2c 574 compatible = "qcom,i2c-qup-v2.2.1";
576 reg = <0xf9924000 0x50 575 reg = <0xf9924000 0x500>;
577 interrupts = <GIC_SPI 576 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
578 clocks = <&gcc GCC_BLS 577 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
579 <&gcc GCC_BLS 578 <&gcc GCC_BLSP1_AHB_CLK>;
580 clock-names = "core", 579 clock-names = "core", "iface";
581 clock-frequency = <400 580 clock-frequency = <400000>;
582 dmas = <&blsp1_dma 14> 581 dmas = <&blsp1_dma 14>, <&blsp1_dma 15>;
583 dma-names = "tx", "rx" 582 dma-names = "tx", "rx";
584 pinctrl-names = "defau 583 pinctrl-names = "default", "sleep";
585 pinctrl-0 = <&i2c2_def 584 pinctrl-0 = <&i2c2_default>;
586 pinctrl-1 = <&i2c2_sle 585 pinctrl-1 = <&i2c2_sleep>;
587 #address-cells = <1>; 586 #address-cells = <1>;
588 #size-cells = <0>; 587 #size-cells = <0>;
589 status = "disabled"; 588 status = "disabled";
590 }; 589 };
591 590
592 /* I2C3 doesn't exist */ 591 /* I2C3 doesn't exist */
593 592
594 blsp1_i2c4: i2c@f9926000 { 593 blsp1_i2c4: i2c@f9926000 {
595 compatible = "qcom,i2c 594 compatible = "qcom,i2c-qup-v2.2.1";
596 reg = <0xf9926000 0x50 595 reg = <0xf9926000 0x500>;
597 interrupts = <GIC_SPI 596 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
598 clocks = <&gcc GCC_BLS 597 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
599 <&gcc GCC_BLS 598 <&gcc GCC_BLSP1_AHB_CLK>;
600 clock-names = "core", 599 clock-names = "core", "iface";
601 clock-frequency = <400 600 clock-frequency = <400000>;
602 dmas = <&blsp1_dma 18> 601 dmas = <&blsp1_dma 18>, <&blsp1_dma 19>;
603 dma-names = "tx", "rx" 602 dma-names = "tx", "rx";
604 pinctrl-names = "defau 603 pinctrl-names = "default", "sleep";
605 pinctrl-0 = <&i2c4_def 604 pinctrl-0 = <&i2c4_default>;
606 pinctrl-1 = <&i2c4_sle 605 pinctrl-1 = <&i2c4_sleep>;
607 #address-cells = <1>; 606 #address-cells = <1>;
608 #size-cells = <0>; 607 #size-cells = <0>;
609 status = "disabled"; 608 status = "disabled";
610 }; 609 };
611 610
612 blsp1_i2c5: i2c@f9927000 { 611 blsp1_i2c5: i2c@f9927000 {
613 compatible = "qcom,i2c 612 compatible = "qcom,i2c-qup-v2.2.1";
614 reg = <0xf9927000 0x50 613 reg = <0xf9927000 0x500>;
615 interrupts = <GIC_SPI 614 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
616 clocks = <&gcc GCC_BLS 615 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
617 <&gcc GCC_BLS 616 <&gcc GCC_BLSP1_AHB_CLK>;
618 clock-names = "core", 617 clock-names = "core", "iface";
619 clock-frequency = <400 618 clock-frequency = <400000>;
620 dmas = <&blsp2_dma 20> 619 dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
621 dma-names = "tx", "rx" 620 dma-names = "tx", "rx";
622 pinctrl-names = "defau 621 pinctrl-names = "default", "sleep";
623 pinctrl-0 = <&i2c5_def 622 pinctrl-0 = <&i2c5_default>;
624 pinctrl-1 = <&i2c5_sle 623 pinctrl-1 = <&i2c5_sleep>;
625 #address-cells = <1>; 624 #address-cells = <1>;
626 #size-cells = <0>; 625 #size-cells = <0>;
627 status = "disabled"; 626 status = "disabled";
628 }; 627 };
629 628
630 blsp1_i2c6: i2c@f9928000 { 629 blsp1_i2c6: i2c@f9928000 {
631 compatible = "qcom,i2c 630 compatible = "qcom,i2c-qup-v2.2.1";
632 reg = <0xf9928000 0x50 631 reg = <0xf9928000 0x500>;
633 interrupts = <GIC_SPI 632 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
634 clocks = <&gcc GCC_BLS 633 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
635 <&gcc GCC_BLS 634 <&gcc GCC_BLSP1_AHB_CLK>;
636 clock-names = "core", 635 clock-names = "core", "iface";
637 clock-frequency = <400 636 clock-frequency = <400000>;
638 dmas = <&blsp1_dma 22> 637 dmas = <&blsp1_dma 22>, <&blsp1_dma 23>;
639 dma-names = "tx", "rx" 638 dma-names = "tx", "rx";
640 pinctrl-names = "defau 639 pinctrl-names = "default", "sleep";
641 pinctrl-0 = <&i2c6_def 640 pinctrl-0 = <&i2c6_default>;
642 pinctrl-1 = <&i2c6_sle 641 pinctrl-1 = <&i2c6_sleep>;
643 #address-cells = <1>; 642 #address-cells = <1>;
644 #size-cells = <0>; 643 #size-cells = <0>;
645 status = "disabled"; 644 status = "disabled";
646 }; 645 };
647 646
648 blsp2_dma: dma-controller@f994 647 blsp2_dma: dma-controller@f9944000 {
649 compatible = "qcom,bam 648 compatible = "qcom,bam-v1.7.0";
650 reg = <0xf9944000 0x19 649 reg = <0xf9944000 0x19000>;
651 interrupts = <GIC_SPI 650 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
652 clocks = <&gcc GCC_BLS 651 clocks = <&gcc GCC_BLSP2_AHB_CLK>;
653 clock-names = "bam_clk 652 clock-names = "bam_clk";
654 #dma-cells = <1>; 653 #dma-cells = <1>;
655 qcom,ee = <0>; 654 qcom,ee = <0>;
656 qcom,controlled-remote 655 qcom,controlled-remotely;
657 num-channels = <24>; 656 num-channels = <24>;
658 qcom,num-ees = <4>; 657 qcom,num-ees = <4>;
659 }; 658 };
660 659
661 blsp2_uart2: serial@f995e000 { 660 blsp2_uart2: serial@f995e000 {
662 compatible = "qcom,msm 661 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
663 reg = <0xf995e000 0x10 662 reg = <0xf995e000 0x1000>;
664 interrupts = <GIC_SPI 663 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
665 clock-names = "core", 664 clock-names = "core", "iface";
666 clocks = <&gcc GCC_BLS 665 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
667 <&gcc 666 <&gcc GCC_BLSP2_AHB_CLK>;
668 dmas = <&blsp2_dma 2>, 667 dmas = <&blsp2_dma 2>, <&blsp2_dma 3>;
669 dma-names = "tx", "rx" 668 dma-names = "tx", "rx";
670 pinctrl-names = "defau 669 pinctrl-names = "default", "sleep";
671 pinctrl-0 = <&blsp2_ua 670 pinctrl-0 = <&blsp2_uart2_default>;
672 pinctrl-1 = <&blsp2_ua 671 pinctrl-1 = <&blsp2_uart2_sleep>;
673 status = "disabled"; 672 status = "disabled";
674 }; 673 };
675 674
676 blsp2_i2c1: i2c@f9963000 { 675 blsp2_i2c1: i2c@f9963000 {
677 compatible = "qcom,i2c 676 compatible = "qcom,i2c-qup-v2.2.1";
678 reg = <0xf9963000 0x50 677 reg = <0xf9963000 0x500>;
679 interrupts = <GIC_SPI 678 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
680 clocks = <&gcc GCC_BLS 679 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
681 <&gcc GCC_BLS 680 <&gcc GCC_BLSP2_AHB_CLK>;
682 clock-names = "core", 681 clock-names = "core", "iface";
683 clock-frequency = <400 682 clock-frequency = <400000>;
684 dmas = <&blsp2_dma 12> 683 dmas = <&blsp2_dma 12>, <&blsp2_dma 13>;
685 dma-names = "tx", "rx" 684 dma-names = "tx", "rx";
686 pinctrl-names = "defau 685 pinctrl-names = "default", "sleep";
687 pinctrl-0 = <&i2c7_def 686 pinctrl-0 = <&i2c7_default>;
688 pinctrl-1 = <&i2c7_sle 687 pinctrl-1 = <&i2c7_sleep>;
689 #address-cells = <1>; 688 #address-cells = <1>;
690 #size-cells = <0>; 689 #size-cells = <0>;
691 status = "disabled"; 690 status = "disabled";
692 }; 691 };
693 692
694 blsp2_spi4: spi@f9966000 { 693 blsp2_spi4: spi@f9966000 {
695 compatible = "qcom,spi 694 compatible = "qcom,spi-qup-v2.2.1";
696 reg = <0xf9966000 0x50 695 reg = <0xf9966000 0x500>;
697 interrupts = <GIC_SPI 696 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
698 clocks = <&gcc GCC_BLS 697 clocks = <&gcc GCC_BLSP2_QUP4_SPI_APPS_CLK>,
699 <&gcc GCC_BLS 698 <&gcc GCC_BLSP2_AHB_CLK>;
700 clock-names = "core", 699 clock-names = "core", "iface";
701 dmas = <&blsp2_dma 18> 700 dmas = <&blsp2_dma 18>, <&blsp2_dma 19>;
702 dma-names = "tx", "rx" 701 dma-names = "tx", "rx";
703 pinctrl-names = "defau 702 pinctrl-names = "default", "sleep";
704 pinctrl-0 = <&blsp2_sp 703 pinctrl-0 = <&blsp2_spi10_default>;
705 pinctrl-1 = <&blsp2_sp 704 pinctrl-1 = <&blsp2_spi10_sleep>;
706 #address-cells = <1>; 705 #address-cells = <1>;
707 #size-cells = <0>; 706 #size-cells = <0>;
708 status = "disabled"; 707 status = "disabled";
709 }; 708 };
710 709
711 blsp2_i2c5: i2c@f9967000 { 710 blsp2_i2c5: i2c@f9967000 {
712 compatible = "qcom,i2c 711 compatible = "qcom,i2c-qup-v2.2.1";
713 reg = <0xf9967000 0x50 712 reg = <0xf9967000 0x500>;
714 interrupts = <GIC_SPI 713 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
715 clocks = <&gcc GCC_BLS 714 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>,
716 <&gcc GCC_BLS 715 <&gcc GCC_BLSP2_AHB_CLK>;
717 clock-names = "core", 716 clock-names = "core", "iface";
718 clock-frequency = <355 717 clock-frequency = <355000>;
719 dmas = <&blsp2_dma 20> 718 dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
720 dma-names = "tx", "rx" 719 dma-names = "tx", "rx";
721 pinctrl-names = "defau 720 pinctrl-names = "default", "sleep";
722 pinctrl-0 = <&i2c11_de 721 pinctrl-0 = <&i2c11_default>;
723 pinctrl-1 = <&i2c11_sl 722 pinctrl-1 = <&i2c11_sleep>;
724 #address-cells = <1>; 723 #address-cells = <1>;
725 #size-cells = <0>; 724 #size-cells = <0>;
726 status = "disabled"; 725 status = "disabled";
727 }; 726 };
728 727
729 gcc: clock-controller@fc400000 728 gcc: clock-controller@fc400000 {
730 compatible = "qcom,gcc 729 compatible = "qcom,gcc-msm8994";
731 #clock-cells = <1>; 730 #clock-cells = <1>;
732 #reset-cells = <1>; 731 #reset-cells = <1>;
733 #power-domain-cells = 732 #power-domain-cells = <1>;
734 reg = <0xfc400000 0x20 733 reg = <0xfc400000 0x2000>;
735 734
736 clock-names = "xo", "s 735 clock-names = "xo", "sleep";
737 clocks = <&xo_board>, 736 clocks = <&xo_board>, <&sleep_clk>;
738 }; 737 };
739 738
740 rpm_msg_ram: sram@fc428000 { 739 rpm_msg_ram: sram@fc428000 {
741 compatible = "qcom,rpm 740 compatible = "qcom,rpm-msg-ram";
742 reg = <0xfc428000 0x40 741 reg = <0xfc428000 0x4000>;
743 }; 742 };
744 743
745 restart@fc4ab000 { 744 restart@fc4ab000 {
746 compatible = "qcom,psh 745 compatible = "qcom,pshold";
747 reg = <0xfc4ab000 0x4> 746 reg = <0xfc4ab000 0x4>;
748 }; 747 };
749 748
750 spmi_bus: spmi@fc4cf000 { 749 spmi_bus: spmi@fc4cf000 {
751 compatible = "qcom,spm 750 compatible = "qcom,spmi-pmic-arb";
752 reg = <0xfc4cf000 0x10 751 reg = <0xfc4cf000 0x1000>,
753 <0xfc4cb000 0x10 752 <0xfc4cb000 0x1000>,
754 <0xfc4ca000 0x10 753 <0xfc4ca000 0x1000>;
755 reg-names = "core", "i 754 reg-names = "core", "intr", "cnfg";
756 interrupt-names = "per 755 interrupt-names = "periph_irq";
757 interrupts = <GIC_SPI 756 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
758 qcom,ee = <0>; 757 qcom,ee = <0>;
759 qcom,channel = <0>; 758 qcom,channel = <0>;
760 #address-cells = <2>; 759 #address-cells = <2>;
761 #size-cells = <0>; 760 #size-cells = <0>;
762 interrupt-controller; 761 interrupt-controller;
763 #interrupt-cells = <4> 762 #interrupt-cells = <4>;
764 }; 763 };
765 764
766 tcsr_mutex: hwlock@fd484000 { 765 tcsr_mutex: hwlock@fd484000 {
767 compatible = "qcom,msm 766 compatible = "qcom,msm8994-tcsr-mutex", "qcom,tcsr-mutex";
768 reg = <0xfd484000 0x10 767 reg = <0xfd484000 0x1000>;
769 #hwlock-cells = <1>; 768 #hwlock-cells = <1>;
770 }; 769 };
771 770
772 tlmm: pinctrl@fd510000 { 771 tlmm: pinctrl@fd510000 {
773 compatible = "qcom,msm 772 compatible = "qcom,msm8994-pinctrl";
774 reg = <0xfd510000 0x40 773 reg = <0xfd510000 0x4000>;
775 interrupts = <GIC_SPI 774 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
776 gpio-controller; 775 gpio-controller;
777 gpio-ranges = <&tlmm 0 776 gpio-ranges = <&tlmm 0 0 146>;
778 #gpio-cells = <2>; 777 #gpio-cells = <2>;
779 interrupt-controller; 778 interrupt-controller;
780 #interrupt-cells = <2> 779 #interrupt-cells = <2>;
781 780
782 blsp1_uart2_default: b 781 blsp1_uart2_default: blsp1-uart2-default-state {
783 pins = "gpio4" 782 pins = "gpio4", "gpio5";
784 function = "bl 783 function = "blsp_uart2";
785 drive-strength 784 drive-strength = <16>;
786 bias-disable; 785 bias-disable;
787 }; 786 };
788 787
789 blsp1_uart2_sleep: bls 788 blsp1_uart2_sleep: blsp1-uart2-sleep-state {
790 pins = "gpio4" 789 pins = "gpio4", "gpio5";
791 function = "gp 790 function = "gpio";
792 drive-strength 791 drive-strength = <2>;
793 bias-pull-down 792 bias-pull-down;
794 }; 793 };
795 794
796 blsp2_uart2_default: b 795 blsp2_uart2_default: blsp2-uart2-default-state {
797 pins = "gpio45 796 pins = "gpio45", "gpio46", "gpio47", "gpio48";
798 function = "bl 797 function = "blsp_uart8";
799 drive-strength 798 drive-strength = <16>;
800 bias-disable; 799 bias-disable;
801 }; 800 };
802 801
803 blsp2_uart2_sleep: bls 802 blsp2_uart2_sleep: blsp2-uart2-sleep-state {
804 pins = "gpio45 803 pins = "gpio45", "gpio46", "gpio47", "gpio48";
805 function = "gp 804 function = "gpio";
806 drive-strength 805 drive-strength = <2>;
807 bias-disable; 806 bias-disable;
808 }; 807 };
809 808
810 i2c1_default: i2c1-def 809 i2c1_default: i2c1-default-state {
811 pins = "gpio2" 810 pins = "gpio2", "gpio3";
812 function = "bl 811 function = "blsp_i2c1";
813 drive-strength 812 drive-strength = <2>;
814 bias-disable; 813 bias-disable;
815 }; 814 };
816 815
817 i2c1_sleep: i2c1-sleep 816 i2c1_sleep: i2c1-sleep-state {
818 pins = "gpio2" 817 pins = "gpio2", "gpio3";
819 function = "gp 818 function = "gpio";
820 drive-strength 819 drive-strength = <2>;
821 bias-disable; 820 bias-disable;
822 }; 821 };
823 822
824 i2c2_default: i2c2-def 823 i2c2_default: i2c2-default-state {
825 pins = "gpio6" 824 pins = "gpio6", "gpio7";
826 function = "bl 825 function = "blsp_i2c2";
827 drive-strength 826 drive-strength = <2>;
828 bias-disable; 827 bias-disable;
829 }; 828 };
830 829
831 i2c2_sleep: i2c2-sleep 830 i2c2_sleep: i2c2-sleep-state {
832 pins = "gpio6" 831 pins = "gpio6", "gpio7";
833 function = "gp 832 function = "gpio";
834 drive-strength 833 drive-strength = <2>;
835 bias-disable; 834 bias-disable;
836 }; 835 };
837 836
838 i2c4_default: i2c4-def 837 i2c4_default: i2c4-default-state {
839 pins = "gpio19 838 pins = "gpio19", "gpio20";
840 function = "bl 839 function = "blsp_i2c4";
841 drive-strength 840 drive-strength = <2>;
842 bias-disable; 841 bias-disable;
843 }; 842 };
844 843
845 i2c4_sleep: i2c4-sleep 844 i2c4_sleep: i2c4-sleep-state {
846 pins = "gpio19 845 pins = "gpio19", "gpio20";
847 function = "gp 846 function = "gpio";
848 drive-strength 847 drive-strength = <2>;
849 bias-pull-down 848 bias-pull-down;
850 }; 849 };
851 850
852 i2c5_default: i2c5-def 851 i2c5_default: i2c5-default-state {
853 pins = "gpio23 852 pins = "gpio23", "gpio24";
854 function = "bl 853 function = "blsp_i2c5";
855 drive-strength 854 drive-strength = <2>;
856 bias-disable; 855 bias-disable;
857 }; 856 };
858 857
859 i2c5_sleep: i2c5-sleep 858 i2c5_sleep: i2c5-sleep-state {
860 pins = "gpio23 859 pins = "gpio23", "gpio24";
861 function = "gp 860 function = "gpio";
862 drive-strength 861 drive-strength = <2>;
863 bias-disable; 862 bias-disable;
864 }; 863 };
865 864
866 i2c6_default: i2c6-def 865 i2c6_default: i2c6-default-state {
867 pins = "gpio28 866 pins = "gpio28", "gpio27";
868 function = "bl 867 function = "blsp_i2c6";
869 drive-strength 868 drive-strength = <2>;
870 bias-disable; 869 bias-disable;
871 }; 870 };
872 871
873 i2c6_sleep: i2c6-sleep 872 i2c6_sleep: i2c6-sleep-state {
874 pins = "gpio28 873 pins = "gpio28", "gpio27";
875 function = "gp 874 function = "gpio";
876 drive-strength 875 drive-strength = <2>;
877 bias-disable; 876 bias-disable;
878 }; 877 };
879 878
880 i2c7_default: i2c7-def 879 i2c7_default: i2c7-default-state {
881 pins = "gpio44 880 pins = "gpio44", "gpio43";
882 function = "bl 881 function = "blsp_i2c7";
883 drive-strength 882 drive-strength = <2>;
884 bias-disable; 883 bias-disable;
885 }; 884 };
886 885
887 i2c7_sleep: i2c7-sleep 886 i2c7_sleep: i2c7-sleep-state {
888 pins = "gpio44 887 pins = "gpio44", "gpio43";
889 function = "gp 888 function = "gpio";
890 drive-strength 889 drive-strength = <2>;
891 bias-disable; 890 bias-disable;
892 }; 891 };
893 892
894 blsp2_spi10_default: b 893 blsp2_spi10_default: blsp2-spi10-default-state {
895 default-pins { 894 default-pins {
896 pins = 895 pins = "gpio53", "gpio54", "gpio55";
897 functi 896 function = "blsp_spi10";
898 drive- 897 drive-strength = <10>;
899 bias-p 898 bias-pull-down;
900 }; 899 };
901 900
902 cs-pins { 901 cs-pins {
903 pins = 902 pins = "gpio67";
904 functi 903 function = "gpio";
905 drive- 904 drive-strength = <2>;
906 bias-d 905 bias-disable;
907 }; 906 };
908 }; 907 };
909 908
910 blsp2_spi10_sleep: bls 909 blsp2_spi10_sleep: blsp2-spi10-sleep-state {
911 pins = "gpio53 910 pins = "gpio53", "gpio54", "gpio55";
912 function = "gp 911 function = "gpio";
913 drive-strength 912 drive-strength = <2>;
914 bias-disable; 913 bias-disable;
915 }; 914 };
916 915
917 i2c11_default: i2c11-d 916 i2c11_default: i2c11-default-state {
918 pins = "gpio83 917 pins = "gpio83", "gpio84";
919 function = "bl 918 function = "blsp_i2c11";
920 drive-strength 919 drive-strength = <2>;
921 bias-disable; 920 bias-disable;
922 }; 921 };
923 922
924 i2c11_sleep: i2c11-sle 923 i2c11_sleep: i2c11-sleep-state {
925 pins = "gpio83 924 pins = "gpio83", "gpio84";
926 function = "gp 925 function = "gpio";
927 drive-strength 926 drive-strength = <2>;
928 bias-disable; 927 bias-disable;
929 }; 928 };
930 929
931 blsp1_spi1_default: bl 930 blsp1_spi1_default: blsp1-spi1-default-state {
932 default-pins { 931 default-pins {
933 pins = 932 pins = "gpio0", "gpio1", "gpio3";
934 functi 933 function = "blsp_spi1";
935 drive- 934 drive-strength = <10>;
936 bias-p 935 bias-pull-down;
937 }; 936 };
938 937
939 cs-pins { 938 cs-pins {
940 pins = 939 pins = "gpio8";
941 functi 940 function = "gpio";
942 drive- 941 drive-strength = <2>;
943 bias-d 942 bias-disable;
944 }; 943 };
945 }; 944 };
946 945
947 blsp1_spi1_sleep: blsp 946 blsp1_spi1_sleep: blsp1-spi1-sleep-state {
948 pins = "gpio0" 947 pins = "gpio0", "gpio1", "gpio3";
949 function = "gp 948 function = "gpio";
950 drive-strength 949 drive-strength = <2>;
951 bias-disable; 950 bias-disable;
952 }; 951 };
953 952
954 sdc1_clk_on: clk-on-st 953 sdc1_clk_on: clk-on-state {
955 pins = "sdc1_c 954 pins = "sdc1_clk";
956 bias-disable; 955 bias-disable;
957 drive-strength 956 drive-strength = <16>;
958 }; 957 };
959 958
960 sdc1_clk_off: clk-off- 959 sdc1_clk_off: clk-off-state {
961 pins = "sdc1_c 960 pins = "sdc1_clk";
962 bias-disable; 961 bias-disable;
963 drive-strength 962 drive-strength = <2>;
964 }; 963 };
965 964
966 sdc1_cmd_on: cmd-on-st 965 sdc1_cmd_on: cmd-on-state {
967 pins = "sdc1_c 966 pins = "sdc1_cmd";
968 bias-pull-up; 967 bias-pull-up;
969 drive-strength 968 drive-strength = <8>;
970 }; 969 };
971 970
972 sdc1_cmd_off: cmd-off- 971 sdc1_cmd_off: cmd-off-state {
973 pins = "sdc1_c 972 pins = "sdc1_cmd";
974 bias-pull-up; 973 bias-pull-up;
975 drive-strength 974 drive-strength = <2>;
976 }; 975 };
977 976
978 sdc1_data_on: data-on- 977 sdc1_data_on: data-on-state {
979 pins = "sdc1_d 978 pins = "sdc1_data";
980 bias-pull-up; 979 bias-pull-up;
981 drive-strength 980 drive-strength = <8>;
982 }; 981 };
983 982
984 sdc1_data_off: data-of 983 sdc1_data_off: data-off-state {
985 pins = "sdc1_d 984 pins = "sdc1_data";
986 bias-pull-up; 985 bias-pull-up;
987 drive-strength 986 drive-strength = <2>;
988 }; 987 };
989 988
990 sdc1_rclk_on: rclk-on- 989 sdc1_rclk_on: rclk-on-state {
991 pins = "sdc1_r 990 pins = "sdc1_rclk";
992 bias-pull-down 991 bias-pull-down;
993 }; 992 };
994 993
995 sdc1_rclk_off: rclk-of 994 sdc1_rclk_off: rclk-off-state {
996 pins = "sdc1_r 995 pins = "sdc1_rclk";
997 bias-pull-down 996 bias-pull-down;
998 }; 997 };
999 998
1000 sdc2_clk_on: sdc2-clk 999 sdc2_clk_on: sdc2-clk-on-state {
1001 pins = "sdc2_ 1000 pins = "sdc2_clk";
1002 bias-disable; 1001 bias-disable;
1003 drive-strengt 1002 drive-strength = <10>;
1004 }; 1003 };
1005 1004
1006 sdc2_clk_off: sdc2-cl 1005 sdc2_clk_off: sdc2-clk-off-state {
1007 pins = "sdc2_ 1006 pins = "sdc2_clk";
1008 bias-disable; 1007 bias-disable;
1009 drive-strengt 1008 drive-strength = <2>;
1010 }; 1009 };
1011 1010
1012 sdc2_cmd_on: sdc2-cmd 1011 sdc2_cmd_on: sdc2-cmd-on-state {
1013 pins = "sdc2_ 1012 pins = "sdc2_cmd";
1014 bias-pull-up; 1013 bias-pull-up;
1015 drive-strengt 1014 drive-strength = <10>;
1016 }; 1015 };
1017 1016
1018 sdc2_cmd_off: sdc2-cm 1017 sdc2_cmd_off: sdc2-cmd-off-state {
1019 pins = "sdc2_ 1018 pins = "sdc2_cmd";
1020 bias-pull-up; 1019 bias-pull-up;
1021 drive-strengt 1020 drive-strength = <2>;
1022 }; 1021 };
1023 1022
1024 sdc2_data_on: sdc2-da 1023 sdc2_data_on: sdc2-data-on-state {
1025 pins = "sdc2_ 1024 pins = "sdc2_data";
1026 bias-pull-up; 1025 bias-pull-up;
1027 drive-strengt 1026 drive-strength = <10>;
1028 }; 1027 };
1029 1028
1030 sdc2_data_off: sdc2-d 1029 sdc2_data_off: sdc2-data-off-state {
1031 pins = "sdc2_ 1030 pins = "sdc2_data";
1032 bias-pull-up; 1031 bias-pull-up;
1033 drive-strengt 1032 drive-strength = <2>;
1034 }; 1033 };
1035 }; 1034 };
1036 1035
1037 mmcc: clock-controller@fd8c00 1036 mmcc: clock-controller@fd8c0000 {
1038 compatible = "qcom,mm 1037 compatible = "qcom,mmcc-msm8994";
1039 reg = <0xfd8c0000 0x5 1038 reg = <0xfd8c0000 0x5200>;
1040 #clock-cells = <1>; 1039 #clock-cells = <1>;
1041 #reset-cells = <1>; 1040 #reset-cells = <1>;
1042 #power-domain-cells = 1041 #power-domain-cells = <1>;
1043 1042
1044 clock-names = "xo", 1043 clock-names = "xo",
1045 "gpll0" 1044 "gpll0",
1046 "mmssno 1045 "mmssnoc_ahb",
1047 "oxili_ 1046 "oxili_gfx3d_clk_src",
1048 "dsi0pl 1047 "dsi0pll",
1049 "dsi0pl 1048 "dsi0pllbyte",
1050 "dsi1pl 1049 "dsi1pll",
1051 "dsi1pl 1050 "dsi1pllbyte",
1052 "hdmipl 1051 "hdmipll";
1053 clocks = <&xo_board>, 1052 clocks = <&xo_board>,
1054 <&gcc GPLL0_ 1053 <&gcc GPLL0_OUT_MMSSCC>,
1055 <&rpmcc RPM_ 1054 <&rpmcc RPM_SMD_MMSSNOC_AHB_CLK>,
1056 <&rpmcc RPM_ 1055 <&rpmcc RPM_SMD_GFX3D_CLK_SRC>,
1057 <0>, 1056 <0>,
1058 <0>, 1057 <0>,
1059 <0>, 1058 <0>,
1060 <0>, 1059 <0>,
1061 <0>; 1060 <0>;
1062 1061
1063 assigned-clocks = <&m 1062 assigned-clocks = <&mmcc MMPLL0_PLL>,
1064 <&m 1063 <&mmcc MMPLL1_PLL>,
1065 <&m 1064 <&mmcc MMPLL3_PLL>,
1066 <&m 1065 <&mmcc MMPLL4_PLL>,
1067 <&m 1066 <&mmcc MMPLL5_PLL>;
1068 assigned-clock-rates 1067 assigned-clock-rates = <800000000>,
1069 1068 <1167000000>,
1070 1069 <1020000000>,
1071 1070 <960000000>,
1072 1071 <600000000>;
1073 }; 1072 };
1074 1073
1075 ocmem: sram@fdd00000 { 1074 ocmem: sram@fdd00000 {
1076 compatible = "qcom,ms 1075 compatible = "qcom,msm8974-ocmem";
1077 reg = <0xfdd00000 0x2 1076 reg = <0xfdd00000 0x2000>,
1078 <0xfec00000 0x2 1077 <0xfec00000 0x200000>;
1079 reg-names = "ctrl", " 1078 reg-names = "ctrl", "mem";
1080 ranges = <0 0xfec0000 1079 ranges = <0 0xfec00000 0x200000>;
1081 clocks = <&rpmcc RPM_ 1080 clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>,
1082 <&mmcc OCMEM 1081 <&mmcc OCMEMCX_OCMEMNOC_CLK>;
1083 clock-names = "core", 1082 clock-names = "core", "iface";
1084 1083
1085 #address-cells = <1>; 1084 #address-cells = <1>;
1086 #size-cells = <1>; 1085 #size-cells = <1>;
1087 1086
1088 gmu_sram: gmu-sram@0 1087 gmu_sram: gmu-sram@0 {
1089 reg = <0x0 0x 1088 reg = <0x0 0x180000>;
1090 }; 1089 };
1091 }; 1090 };
1092 }; 1091 };
1093 1092
1094 timer: timer { 1093 timer: timer {
1095 compatible = "arm,armv8-timer 1094 compatible = "arm,armv8-timer";
1096 interrupts = <GIC_PPI 2 (GIC_ !! 1095 interrupts = <GIC_PPI 2 0xff08>,
1097 <GIC_PPI 3 (GIC_ !! 1096 <GIC_PPI 3 0xff08>,
1098 <GIC_PPI 4 (GIC_ !! 1097 <GIC_PPI 4 0xff08>,
1099 <GIC_PPI 1 (GIC_ !! 1098 <GIC_PPI 1 0xff08>;
1100 }; 1099 };
1101 1100
1102 vph_pwr: vph-pwr-regulator { 1101 vph_pwr: vph-pwr-regulator {
1103 compatible = "regulator-fixed 1102 compatible = "regulator-fixed";
1104 regulator-name = "vph_pwr"; 1103 regulator-name = "vph_pwr";
1105 1104
1106 regulator-min-microvolt = <36 1105 regulator-min-microvolt = <3600000>;
1107 regulator-max-microvolt = <36 1106 regulator-max-microvolt = <3600000>;
1108 1107
1109 regulator-always-on; 1108 regulator-always-on;
1110 }; 1109 };
1111 }; 1110 };
1112 1111
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