1 // SPDX-License-Identifier: GPL-2.0-only !! 1 /* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
2 /* !! 2 *
3 * Copyright (c) 2014-2015, The Linux Foundati !! 3 * This program is free software; you can redistribute it and/or modify
>> 4 * it under the terms of the GNU General Public License version 2 and
>> 5 * only version 2 as published by the Free Software Foundation.
>> 6 *
>> 7 * This program is distributed in the hope that it will be useful,
>> 8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> 9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> 10 * GNU General Public License for more details.
4 */ 11 */
5 12
6 #include <dt-bindings/interrupt-controller/arm 13 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,gcc-msm8996.h 14 #include <dt-bindings/clock/qcom,gcc-msm8996.h>
8 #include <dt-bindings/clock/qcom,mmcc-msm8996. 15 #include <dt-bindings/clock/qcom,mmcc-msm8996.h>
9 #include <dt-bindings/clock/qcom,rpmcc.h> <<
10 #include <dt-bindings/interconnect/qcom,msm899 <<
11 #include <dt-bindings/interconnect/qcom,msm899 <<
12 #include <dt-bindings/firmware/qcom,scm.h> <<
13 #include <dt-bindings/gpio/gpio.h> <<
14 #include <dt-bindings/power/qcom-rpmpd.h> <<
15 #include <dt-bindings/soc/qcom,apr.h> <<
16 #include <dt-bindings/thermal/thermal.h> <<
17 16
18 / { 17 / {
>> 18 model = "Qualcomm Technologies, Inc. MSM8996";
>> 19
19 interrupt-parent = <&intc>; 20 interrupt-parent = <&intc>;
20 21
21 #address-cells = <2>; 22 #address-cells = <2>;
22 #size-cells = <2>; 23 #size-cells = <2>;
23 24
24 chosen { }; 25 chosen { };
25 26
26 clocks { !! 27 memory {
27 xo_board: xo-board { !! 28 device_type = "memory";
28 compatible = "fixed-cl !! 29 /* We expect the bootloader to fill in the reg */
29 #clock-cells = <0>; !! 30 reg = <0 0 0 0>;
30 clock-frequency = <192 !! 31 };
31 clock-output-names = " !! 32
>> 33 reserved-memory {
>> 34 #address-cells = <2>;
>> 35 #size-cells = <2>;
>> 36 ranges;
>> 37
>> 38 mba_region: mba@91500000 {
>> 39 reg = <0x0 0x91500000 0x0 0x200000>;
>> 40 no-map;
32 }; 41 };
33 42
34 sleep_clk: sleep-clk { !! 43 slpi_region: slpi@90b00000 {
35 compatible = "fixed-cl !! 44 reg = <0x0 0x90b00000 0x0 0xa00000>;
36 #clock-cells = <0>; !! 45 no-map;
37 clock-frequency = <327 !! 46 };
38 clock-output-names = " !! 47
>> 48 venus_region: venus@90400000 {
>> 49 reg = <0x0 0x90400000 0x0 0x700000>;
>> 50 no-map;
>> 51 };
>> 52
>> 53 adsp_region: adsp@8ea00000 {
>> 54 reg = <0x0 0x8ea00000 0x0 0x1a00000>;
>> 55 no-map;
>> 56 };
>> 57
>> 58 mpss_region: mpss@88800000 {
>> 59 reg = <0x0 0x88800000 0x0 0x6200000>;
>> 60 no-map;
>> 61 };
>> 62
>> 63 smem_mem: smem-mem@86000000 {
>> 64 reg = <0x0 0x86000000 0x0 0x200000>;
>> 65 no-map;
>> 66 };
>> 67
>> 68 memory@85800000 {
>> 69 reg = <0x0 0x85800000 0x0 0x800000>;
>> 70 no-map;
>> 71 };
>> 72
>> 73 memory@86200000 {
>> 74 reg = <0x0 0x86200000 0x0 0x2600000>;
>> 75 no-map;
39 }; 76 };
40 }; 77 };
41 78
42 cpus { 79 cpus {
43 #address-cells = <2>; 80 #address-cells = <2>;
44 #size-cells = <0>; 81 #size-cells = <0>;
45 82
46 CPU0: cpu@0 { 83 CPU0: cpu@0 {
47 device_type = "cpu"; 84 device_type = "cpu";
48 compatible = "qcom,kry 85 compatible = "qcom,kryo";
49 reg = <0x0 0x0>; 86 reg = <0x0 0x0>;
50 enable-method = "psci" 87 enable-method = "psci";
51 cpu-idle-states = <&CP <<
52 capacity-dmips-mhz = < <<
53 clocks = <&kryocc 0>; <<
54 interconnects = <&cbf <<
55 operating-points-v2 = <<
56 #cooling-cells = <2>; <<
57 next-level-cache = <&L 88 next-level-cache = <&L2_0>;
58 L2_0: l2-cache { 89 L2_0: l2-cache {
59 compatible = " !! 90 compatible = "cache";
60 cache-level = !! 91 cache-level = <2>;
61 cache-unified; <<
62 }; 92 };
63 }; 93 };
64 94
65 CPU1: cpu@1 { 95 CPU1: cpu@1 {
66 device_type = "cpu"; 96 device_type = "cpu";
67 compatible = "qcom,kry 97 compatible = "qcom,kryo";
68 reg = <0x0 0x1>; 98 reg = <0x0 0x1>;
69 enable-method = "psci" 99 enable-method = "psci";
70 cpu-idle-states = <&CP <<
71 capacity-dmips-mhz = < <<
72 clocks = <&kryocc 0>; <<
73 interconnects = <&cbf <<
74 operating-points-v2 = <<
75 #cooling-cells = <2>; <<
76 next-level-cache = <&L 100 next-level-cache = <&L2_0>;
77 }; 101 };
78 102
79 CPU2: cpu@100 { 103 CPU2: cpu@100 {
80 device_type = "cpu"; 104 device_type = "cpu";
81 compatible = "qcom,kry 105 compatible = "qcom,kryo";
82 reg = <0x0 0x100>; 106 reg = <0x0 0x100>;
83 enable-method = "psci" 107 enable-method = "psci";
84 cpu-idle-states = <&CP <<
85 capacity-dmips-mhz = < <<
86 clocks = <&kryocc 1>; <<
87 interconnects = <&cbf <<
88 operating-points-v2 = <<
89 #cooling-cells = <2>; <<
90 next-level-cache = <&L 108 next-level-cache = <&L2_1>;
91 L2_1: l2-cache { 109 L2_1: l2-cache {
92 compatible = " !! 110 compatible = "cache";
93 cache-level = !! 111 cache-level = <2>;
94 cache-unified; <<
95 }; 112 };
96 }; 113 };
97 114
98 CPU3: cpu@101 { 115 CPU3: cpu@101 {
99 device_type = "cpu"; 116 device_type = "cpu";
100 compatible = "qcom,kry 117 compatible = "qcom,kryo";
101 reg = <0x0 0x101>; 118 reg = <0x0 0x101>;
102 enable-method = "psci" 119 enable-method = "psci";
103 cpu-idle-states = <&CP <<
104 capacity-dmips-mhz = < <<
105 clocks = <&kryocc 1>; <<
106 interconnects = <&cbf <<
107 operating-points-v2 = <<
108 #cooling-cells = <2>; <<
109 next-level-cache = <&L 120 next-level-cache = <&L2_1>;
110 }; 121 };
111 122
112 cpu-map { 123 cpu-map {
113 cluster0 { 124 cluster0 {
114 core0 { 125 core0 {
115 cpu = 126 cpu = <&CPU0>;
116 }; 127 };
117 128
118 core1 { 129 core1 {
119 cpu = 130 cpu = <&CPU1>;
120 }; 131 };
121 }; 132 };
122 133
123 cluster1 { 134 cluster1 {
124 core0 { 135 core0 {
125 cpu = 136 cpu = <&CPU2>;
126 }; 137 };
127 138
128 core1 { 139 core1 {
129 cpu = 140 cpu = <&CPU3>;
130 }; 141 };
131 }; 142 };
132 }; 143 };
133 <<
134 idle-states { <<
135 entry-method = "psci"; <<
136 <<
137 CPU_SLEEP_0: cpu-sleep <<
138 compatible = " <<
139 idle-state-nam <<
140 arm,psci-suspe <<
141 entry-latency- <<
142 exit-latency-u <<
143 min-residency- <<
144 }; <<
145 }; <<
146 }; <<
147 <<
148 cluster0_opp: opp-table-cluster0 { <<
149 compatible = "operating-points <<
150 nvmem-cells = <&speedbin_efuse <<
151 opp-shared; <<
152 <<
153 /* Nominal fmax for now */ <<
154 opp-307200000 { <<
155 opp-hz = /bits/ 64 <30 <<
156 opp-supported-hw = <0x <<
157 clock-latency-ns = <20 <<
158 opp-peak-kBps = <30720 <<
159 }; <<
160 opp-422400000 { <<
161 opp-hz = /bits/ 64 <42 <<
162 opp-supported-hw = <0x <<
163 clock-latency-ns = <20 <<
164 opp-peak-kBps = <30720 <<
165 }; <<
166 opp-480000000 { <<
167 opp-hz = /bits/ 64 <48 <<
168 opp-supported-hw = <0x <<
169 clock-latency-ns = <20 <<
170 opp-peak-kBps = <30720 <<
171 }; <<
172 opp-556800000 { <<
173 opp-hz = /bits/ 64 <55 <<
174 opp-supported-hw = <0x <<
175 clock-latency-ns = <20 <<
176 opp-peak-kBps = <30720 <<
177 }; <<
178 opp-652800000 { <<
179 opp-hz = /bits/ 64 <65 <<
180 opp-supported-hw = <0x <<
181 clock-latency-ns = <20 <<
182 opp-peak-kBps = <38400 <<
183 }; <<
184 opp-729600000 { <<
185 opp-hz = /bits/ 64 <72 <<
186 opp-supported-hw = <0x <<
187 clock-latency-ns = <20 <<
188 opp-peak-kBps = <46080 <<
189 }; <<
190 opp-844800000 { <<
191 opp-hz = /bits/ 64 <84 <<
192 opp-supported-hw = <0x <<
193 clock-latency-ns = <20 <<
194 opp-peak-kBps = <53760 <<
195 }; <<
196 opp-960000000 { <<
197 opp-hz = /bits/ 64 <96 <<
198 opp-supported-hw = <0x <<
199 clock-latency-ns = <20 <<
200 opp-peak-kBps = <67200 <<
201 }; <<
202 opp-1036800000 { <<
203 opp-hz = /bits/ 64 <10 <<
204 opp-supported-hw = <0x <<
205 clock-latency-ns = <20 <<
206 opp-peak-kBps = <67200 <<
207 }; <<
208 opp-1113600000 { <<
209 opp-hz = /bits/ 64 <11 <<
210 opp-supported-hw = <0x <<
211 clock-latency-ns = <20 <<
212 opp-peak-kBps = <82560 <<
213 }; <<
214 opp-1190400000 { <<
215 opp-hz = /bits/ 64 <11 <<
216 opp-supported-hw = <0x <<
217 clock-latency-ns = <20 <<
218 opp-peak-kBps = <82560 <<
219 }; <<
220 opp-1228800000 { <<
221 opp-hz = /bits/ 64 <12 <<
222 opp-supported-hw = <0x <<
223 clock-latency-ns = <20 <<
224 opp-peak-kBps = <90240 <<
225 }; <<
226 opp-1324800000 { <<
227 opp-hz = /bits/ 64 <13 <<
228 opp-supported-hw = <0x <<
229 clock-latency-ns = <20 <<
230 opp-peak-kBps = <10560 <<
231 }; <<
232 opp-1363200000 { <<
233 opp-hz = /bits/ 64 <13 <<
234 opp-supported-hw = <0x <<
235 clock-latency-ns = <20 <<
236 opp-peak-kBps = <11328 <<
237 }; <<
238 opp-1401600000 { <<
239 opp-hz = /bits/ 64 <14 <<
240 opp-supported-hw = <0x <<
241 clock-latency-ns = <20 <<
242 opp-peak-kBps = <11328 <<
243 }; <<
244 opp-1478400000 { <<
245 opp-hz = /bits/ 64 <14 <<
246 opp-supported-hw = <0x <<
247 clock-latency-ns = <20 <<
248 opp-peak-kBps = <11904 <<
249 }; <<
250 opp-1497600000 { <<
251 opp-hz = /bits/ 64 <14 <<
252 opp-supported-hw = <0x <<
253 clock-latency-ns = <20 <<
254 opp-peak-kBps = <13056 <<
255 }; <<
256 opp-1593600000 { <<
257 opp-hz = /bits/ 64 <15 <<
258 opp-supported-hw = <0x <<
259 clock-latency-ns = <20 <<
260 opp-peak-kBps = <13824 <<
261 }; <<
262 }; <<
263 <<
264 cluster1_opp: opp-table-cluster1 { <<
265 compatible = "operating-points <<
266 nvmem-cells = <&speedbin_efuse <<
267 opp-shared; <<
268 <<
269 /* Nominal fmax for now */ <<
270 opp-307200000 { <<
271 opp-hz = /bits/ 64 <30 <<
272 opp-supported-hw = <0x <<
273 clock-latency-ns = <20 <<
274 opp-peak-kBps = <30720 <<
275 }; <<
276 opp-403200000 { <<
277 opp-hz = /bits/ 64 <40 <<
278 opp-supported-hw = <0x <<
279 clock-latency-ns = <20 <<
280 opp-peak-kBps = <30720 <<
281 }; <<
282 opp-480000000 { <<
283 opp-hz = /bits/ 64 <48 <<
284 opp-supported-hw = <0x <<
285 clock-latency-ns = <20 <<
286 opp-peak-kBps = <30720 <<
287 }; <<
288 opp-556800000 { <<
289 opp-hz = /bits/ 64 <55 <<
290 opp-supported-hw = <0x <<
291 clock-latency-ns = <20 <<
292 opp-peak-kBps = <30720 <<
293 }; <<
294 opp-652800000 { <<
295 opp-hz = /bits/ 64 <65 <<
296 opp-supported-hw = <0x <<
297 clock-latency-ns = <20 <<
298 opp-peak-kBps = <30720 <<
299 }; <<
300 opp-729600000 { <<
301 opp-hz = /bits/ 64 <72 <<
302 opp-supported-hw = <0x <<
303 clock-latency-ns = <20 <<
304 opp-peak-kBps = <30720 <<
305 }; <<
306 opp-806400000 { <<
307 opp-hz = /bits/ 64 <80 <<
308 opp-supported-hw = <0x <<
309 clock-latency-ns = <20 <<
310 opp-peak-kBps = <38400 <<
311 }; <<
312 opp-883200000 { <<
313 opp-hz = /bits/ 64 <88 <<
314 opp-supported-hw = <0x <<
315 clock-latency-ns = <20 <<
316 opp-peak-kBps = <46080 <<
317 }; <<
318 opp-940800000 { <<
319 opp-hz = /bits/ 64 <94 <<
320 opp-supported-hw = <0x <<
321 clock-latency-ns = <20 <<
322 opp-peak-kBps = <53760 <<
323 }; <<
324 opp-1036800000 { <<
325 opp-hz = /bits/ 64 <10 <<
326 opp-supported-hw = <0x <<
327 clock-latency-ns = <20 <<
328 opp-peak-kBps = <59520 <<
329 }; <<
330 opp-1113600000 { <<
331 opp-hz = /bits/ 64 <11 <<
332 opp-supported-hw = <0x <<
333 clock-latency-ns = <20 <<
334 opp-peak-kBps = <67200 <<
335 }; <<
336 opp-1190400000 { <<
337 opp-hz = /bits/ 64 <11 <<
338 opp-supported-hw = <0x <<
339 clock-latency-ns = <20 <<
340 opp-peak-kBps = <67200 <<
341 }; <<
342 opp-1248000000 { <<
343 opp-hz = /bits/ 64 <12 <<
344 opp-supported-hw = <0x <<
345 clock-latency-ns = <20 <<
346 opp-peak-kBps = <74880 <<
347 }; <<
348 opp-1324800000 { <<
349 opp-hz = /bits/ 64 <13 <<
350 opp-supported-hw = <0x <<
351 clock-latency-ns = <20 <<
352 opp-peak-kBps = <82560 <<
353 }; <<
354 opp-1401600000 { <<
355 opp-hz = /bits/ 64 <14 <<
356 opp-supported-hw = <0x <<
357 clock-latency-ns = <20 <<
358 opp-peak-kBps = <90240 <<
359 }; <<
360 opp-1478400000 { <<
361 opp-hz = /bits/ 64 <14 <<
362 opp-supported-hw = <0x <<
363 clock-latency-ns = <20 <<
364 opp-peak-kBps = <97920 <<
365 }; <<
366 opp-1555200000 { <<
367 opp-hz = /bits/ 64 <15 <<
368 opp-supported-hw = <0x <<
369 clock-latency-ns = <20 <<
370 opp-peak-kBps = <10560 <<
371 }; <<
372 opp-1632000000 { <<
373 opp-hz = /bits/ 64 <16 <<
374 opp-supported-hw = <0x <<
375 clock-latency-ns = <20 <<
376 opp-peak-kBps = <11904 <<
377 }; <<
378 opp-1708800000 { <<
379 opp-hz = /bits/ 64 <17 <<
380 opp-supported-hw = <0x <<
381 clock-latency-ns = <20 <<
382 opp-peak-kBps = <12288 <<
383 }; <<
384 opp-1785600000 { <<
385 opp-hz = /bits/ 64 <17 <<
386 opp-supported-hw = <0x <<
387 clock-latency-ns = <20 <<
388 opp-peak-kBps = <13056 <<
389 }; <<
390 opp-1804800000 { <<
391 opp-hz = /bits/ 64 <18 <<
392 opp-supported-hw = <0x <<
393 clock-latency-ns = <20 <<
394 opp-peak-kBps = <13056 <<
395 }; <<
396 opp-1824000000 { <<
397 opp-hz = /bits/ 64 <18 <<
398 opp-supported-hw = <0x <<
399 clock-latency-ns = <20 <<
400 opp-peak-kBps = <13824 <<
401 }; <<
402 opp-1900800000 { <<
403 opp-hz = /bits/ 64 <19 <<
404 opp-supported-hw = <0x <<
405 clock-latency-ns = <20 <<
406 opp-peak-kBps = <13056 <<
407 }; <<
408 opp-1920000000 { <<
409 opp-hz = /bits/ 64 <19 <<
410 opp-supported-hw = <0x <<
411 clock-latency-ns = <20 <<
412 opp-peak-kBps = <14592 <<
413 }; <<
414 opp-1996800000 { <<
415 opp-hz = /bits/ 64 <19 <<
416 opp-supported-hw = <0x <<
417 clock-latency-ns = <20 <<
418 opp-peak-kBps = <15936 <<
419 }; <<
420 opp-2073600000 { <<
421 opp-hz = /bits/ 64 <20 <<
422 opp-supported-hw = <0x <<
423 clock-latency-ns = <20 <<
424 opp-peak-kBps = <15936 <<
425 }; <<
426 opp-2150400000 { <<
427 opp-hz = /bits/ 64 <21 <<
428 opp-supported-hw = <0x <<
429 clock-latency-ns = <20 <<
430 opp-peak-kBps = <15936 <<
431 }; <<
432 }; 144 };
433 145
434 firmware { !! 146 thermal-zones {
435 scm { !! 147 cpu-thermal0 {
436 compatible = "qcom,scm !! 148 polling-delay-passive = <250>;
437 qcom,dload-mode = <&tc !! 149 polling-delay = <1000>;
438 }; <<
439 }; <<
440 150
441 memory@80000000 { !! 151 thermal-sensors = <&tsens0 3>;
442 device_type = "memory"; <<
443 /* We expect the bootloader to <<
444 reg = <0x0 0x80000000 0x0 0x0> <<
445 }; <<
446 152
447 etm { !! 153 trips {
448 compatible = "qcom,coresight-r !! 154 cpu_alert0: trip0 {
>> 155 temperature = <75000>;
>> 156 hysteresis = <2000>;
>> 157 type = "passive";
>> 158 };
449 159
450 out-ports { !! 160 cpu_crit0: trip1 {
451 port { !! 161 temperature = <110000>;
452 modem_etm_out_ !! 162 hysteresis = <2000>;
453 remote !! 163 type = "critical";
454 <&fu <<
455 }; 164 };
456 }; 165 };
457 }; 166 };
458 }; <<
459 167
460 psci { !! 168 cpu-thermal1 {
461 compatible = "arm,psci-1.0"; !! 169 polling-delay-passive = <250>;
462 method = "smc"; !! 170 polling-delay = <1000>;
463 }; <<
464 171
465 rpm: remoteproc { !! 172 thermal-sensors = <&tsens0 5>;
466 compatible = "qcom,msm8996-rpm <<
467 173
468 glink-edge { !! 174 trips {
469 compatible = "qcom,gli !! 175 cpu_alert1: trip0 {
470 interrupts = <GIC_SPI !! 176 temperature = <75000>;
471 qcom,rpm-msg-ram = <&r !! 177 hysteresis = <2000>;
472 mboxes = <&apcs_glb 0> !! 178 type = "passive";
473 <<
474 rpm_requests: rpm-requ <<
475 compatible = " <<
476 qcom,glink-cha <<
477 <<
478 rpmcc: clock-c <<
479 compat <<
480 #clock <<
481 clocks <<
482 clock- <<
483 }; 179 };
484 180
485 rpmpd: power-c !! 181 cpu_crit1: trip1 {
486 compat !! 182 temperature = <110000>;
487 #power !! 183 hysteresis = <2000>;
488 operat !! 184 type = "critical";
489 <<
490 rpmpd_ <<
491 <<
492 <<
493 <<
494 <<
495 <<
496 <<
497 <<
498 <<
499 <<
500 <<
501 <<
502 <<
503 <<
504 <<
505 <<
506 <<
507 <<
508 <<
509 <<
510 <<
511 <<
512 <<
513 <<
514 <<
515 <<
516 }; <<
517 }; 185 };
518 }; 186 };
519 }; 187 };
520 }; <<
521 <<
522 reserved-memory { <<
523 #address-cells = <2>; <<
524 #size-cells = <2>; <<
525 ranges; <<
526 188
527 hyp_mem: memory@85800000 { !! 189 cpu-thermal2 {
528 reg = <0x0 0x85800000 !! 190 polling-delay-passive = <250>;
529 no-map; !! 191 polling-delay = <1000>;
530 }; <<
531 192
532 xbl_mem: memory@85e00000 { !! 193 thermal-sensors = <&tsens0 8>;
533 reg = <0x0 0x85e00000 <<
534 no-map; <<
535 }; <<
536 194
537 smem_mem: smem-mem@86000000 { !! 195 trips {
538 reg = <0x0 0x86000000 !! 196 cpu_alert2: trip0 {
539 no-map; !! 197 temperature = <75000>;
540 }; !! 198 hysteresis = <2000>;
>> 199 type = "passive";
>> 200 };
541 201
542 tz_mem: memory@86200000 { !! 202 cpu_crit2: trip1 {
543 reg = <0x0 0x86200000 !! 203 temperature = <110000>;
544 no-map; !! 204 hysteresis = <2000>;
>> 205 type = "critical";
>> 206 };
>> 207 };
545 }; 208 };
546 209
547 rmtfs_mem: rmtfs { !! 210 cpu-thermal3 {
548 compatible = "qcom,rmt !! 211 polling-delay-passive = <250>;
>> 212 polling-delay = <1000>;
549 213
550 size = <0x0 0x200000>; !! 214 thermal-sensors = <&tsens0 10>;
551 alloc-ranges = <0x0 0x <<
552 no-map; <<
553 215
554 qcom,client-id = <1>; !! 216 trips {
555 qcom,vmid = <QCOM_SCM_ !! 217 cpu_alert3: trip0 {
556 }; !! 218 temperature = <75000>;
>> 219 hysteresis = <2000>;
>> 220 type = "passive";
>> 221 };
557 222
558 mpss_mem: mpss@88800000 { !! 223 cpu_crit3: trip1 {
559 reg = <0x0 0x88800000 !! 224 temperature = <110000>;
560 no-map; !! 225 hysteresis = <2000>;
>> 226 type = "critical";
>> 227 };
>> 228 };
561 }; 229 };
>> 230 };
562 231
563 adsp_mem: adsp@8ea00000 { !! 232 timer {
564 reg = <0x0 0x8ea00000 !! 233 compatible = "arm,armv8-timer";
565 no-map; !! 234 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
566 }; !! 235 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
>> 236 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
>> 237 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
>> 238 };
567 239
568 slpi_mem: slpi@90500000 { !! 240 clocks {
569 reg = <0x0 0x90500000 !! 241 xo_board: xo_board {
570 no-map; !! 242 compatible = "fixed-clock";
>> 243 #clock-cells = <0>;
>> 244 clock-frequency = <19200000>;
>> 245 clock-output-names = "xo_board";
571 }; 246 };
572 247
573 gpu_mem: gpu@90f00000 { !! 248 sleep_clk: sleep_clk {
574 compatible = "shared-d !! 249 compatible = "fixed-clock";
575 reg = <0x0 0x90f00000 !! 250 #clock-cells = <0>;
576 no-map; !! 251 clock-frequency = <32764>;
>> 252 clock-output-names = "sleep_clk";
577 }; 253 };
>> 254 };
578 255
579 venus_mem: venus@91000000 { !! 256 psci {
580 reg = <0x0 0x91000000 !! 257 compatible = "arm,psci-1.0";
581 no-map; !! 258 method = "smc";
582 }; !! 259 };
583 260
584 mba_mem: mba@91500000 { !! 261 firmware {
585 reg = <0x0 0x91500000 !! 262 scm {
586 no-map; !! 263 compatible = "qcom,scm-msm8996";
587 }; 264 };
>> 265 };
588 266
589 mdata_mem: mpss-metadata { !! 267 tcsr_mutex: hwlock {
590 alloc-ranges = <0x0 0x !! 268 compatible = "qcom,tcsr-mutex";
591 size = <0x0 0x4000>; !! 269 syscon = <&tcsr_mutex_regs 0 0x1000>;
592 no-map; !! 270 #hwlock-cells = <1>;
593 }; <<
594 }; 271 };
595 272
596 smem { 273 smem {
597 compatible = "qcom,smem"; 274 compatible = "qcom,smem";
598 memory-region = <&smem_mem>; 275 memory-region = <&smem_mem>;
599 hwlocks = <&tcsr_mutex 3>; 276 hwlocks = <&tcsr_mutex 3>;
600 }; 277 };
601 278
602 smp2p-adsp { !! 279 soc: soc {
603 compatible = "qcom,smp2p"; <<
604 qcom,smem = <443>, <429>; <<
605 <<
606 interrupts = <GIC_SPI 158 IRQ_ <<
607 <<
608 mboxes = <&apcs_glb 10>; <<
609 <<
610 qcom,local-pid = <0>; <<
611 qcom,remote-pid = <2>; <<
612 <<
613 adsp_smp2p_out: master-kernel <<
614 qcom,entry-name = "mas <<
615 #qcom,smem-state-cells <<
616 }; <<
617 <<
618 adsp_smp2p_in: slave-kernel { <<
619 qcom,entry-name = "sla <<
620 <<
621 interrupt-controller; <<
622 #interrupt-cells = <2> <<
623 }; <<
624 }; <<
625 <<
626 smp2p-mpss { <<
627 compatible = "qcom,smp2p"; <<
628 qcom,smem = <435>, <428>; <<
629 <<
630 interrupts = <GIC_SPI 451 IRQ_ <<
631 <<
632 mboxes = <&apcs_glb 14>; <<
633 <<
634 qcom,local-pid = <0>; <<
635 qcom,remote-pid = <1>; <<
636 <<
637 mpss_smp2p_out: master-kernel <<
638 qcom,entry-name = "mas <<
639 #qcom,smem-state-cells <<
640 }; <<
641 <<
642 mpss_smp2p_in: slave-kernel { <<
643 qcom,entry-name = "sla <<
644 <<
645 interrupt-controller; <<
646 #interrupt-cells = <2> <<
647 }; <<
648 }; <<
649 <<
650 smp2p-slpi { <<
651 compatible = "qcom,smp2p"; <<
652 qcom,smem = <481>, <430>; <<
653 <<
654 interrupts = <GIC_SPI 178 IRQ_ <<
655 <<
656 mboxes = <&apcs_glb 26>; <<
657 <<
658 qcom,local-pid = <0>; <<
659 qcom,remote-pid = <3>; <<
660 <<
661 slpi_smp2p_out: master-kernel <<
662 qcom,entry-name = "mas <<
663 #qcom,smem-state-cells <<
664 }; <<
665 <<
666 slpi_smp2p_in: slave-kernel { <<
667 qcom,entry-name = "sla <<
668 <<
669 interrupt-controller; <<
670 #interrupt-cells = <2> <<
671 }; <<
672 }; <<
673 <<
674 soc: soc@0 { <<
675 #address-cells = <1>; 280 #address-cells = <1>;
676 #size-cells = <1>; 281 #size-cells = <1>;
677 ranges = <0 0 0 0xffffffff>; 282 ranges = <0 0 0 0xffffffff>;
678 compatible = "simple-bus"; 283 compatible = "simple-bus";
679 284
680 pcie_phy: phy-wrapper@34000 { !! 285 tcsr_mutex_regs: syscon@740000 {
681 compatible = "qcom,msm !! 286 compatible = "syscon";
682 reg = <0x00034000 0x48 !! 287 reg = <0x740000 0x20000>;
683 #address-cells = <1>; <<
684 #size-cells = <1>; <<
685 ranges = <0x0 0x000340 <<
686 <<
687 clocks = <&gcc GCC_PCI <<
688 <&gcc GCC_PCIE <<
689 <&gcc GCC_PCIE <<
690 clock-names = "aux", " <<
691 <<
692 resets = <&gcc GCC_PCI <<
693 <&gcc GCC_PCIE <<
694 <&gcc GCC_PCIE <<
695 reset-names = "phy", " <<
696 <<
697 status = "disabled"; <<
698 <<
699 pciephy_0: phy@1000 { <<
700 reg = <0x1000 <<
701 <0x1200 <<
702 <0x1400 <<
703 <<
704 clocks = <&gcc <<
705 clock-names = <<
706 resets = <&gcc <<
707 reset-names = <<
708 <<
709 #clock-cells = <<
710 clock-output-n <<
711 <<
712 #phy-cells = < <<
713 }; <<
714 <<
715 pciephy_1: phy@2000 { <<
716 reg = <0x2000 <<
717 <0x2200 <<
718 <0x2400 <<
719 <<
720 clocks = <&gcc <<
721 clock-names = <<
722 resets = <&gcc <<
723 reset-names = <<
724 <<
725 #clock-cells = <<
726 clock-output-n <<
727 <<
728 #phy-cells = < <<
729 }; <<
730 <<
731 pciephy_2: phy@3000 { <<
732 reg = <0x3000 <<
733 <0x3200 <<
734 <0x3400 <<
735 <<
736 clocks = <&gcc <<
737 clock-names = <<
738 resets = <&gcc <<
739 reset-names = <<
740 <<
741 #clock-cells = <<
742 clock-output-n <<
743 <<
744 #phy-cells = < <<
745 }; <<
746 }; <<
747 <<
748 rpm_msg_ram: sram@68000 { <<
749 compatible = "qcom,rpm <<
750 reg = <0x00068000 0x60 <<
751 }; 288 };
752 289
753 qfprom@74000 { !! 290 intc: interrupt-controller@9bc0000 {
754 compatible = "qcom,msm !! 291 compatible = "arm,gic-v3";
755 reg = <0x00074000 0x8f !! 292 #interrupt-cells = <3>;
756 #address-cells = <1>; !! 293 interrupt-controller;
757 #size-cells = <1>; !! 294 #redistributor-regions = <1>;
758 !! 295 redistributor-stride = <0x0 0x40000>;
759 qusb2p_hstx_trim: hstx !! 296 reg = <0x09bc0000 0x10000>,
760 reg = <0x24e 0 !! 297 <0x09c00000 0x100000>;
761 bits = <5 4>; !! 298 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
762 }; <<
763 <<
764 qusb2s_hstx_trim: hstx <<
765 reg = <0x24f 0 <<
766 bits = <1 4>; <<
767 }; <<
768 <<
769 speedbin_efuse: speedb <<
770 reg = <0x133 0 <<
771 bits = <5 3>; <<
772 }; <<
773 }; 299 };
774 300
775 rng: rng@83000 { !! 301 apcs: syscon@9820000 {
776 compatible = "qcom,prn !! 302 compatible = "syscon";
777 reg = <0x00083000 0x10 !! 303 reg = <0x9820000 0x1000>;
778 clocks = <&gcc GCC_PRN <<
779 clock-names = "core"; <<
780 }; 304 };
781 305
782 gcc: clock-controller@300000 { 306 gcc: clock-controller@300000 {
783 compatible = "qcom,gcc 307 compatible = "qcom,gcc-msm8996";
784 #clock-cells = <1>; 308 #clock-cells = <1>;
785 #reset-cells = <1>; 309 #reset-cells = <1>;
786 #power-domain-cells = 310 #power-domain-cells = <1>;
787 reg = <0x00300000 0x90 !! 311 reg = <0x300000 0x90000>;
788 <<
789 clocks = <&rpmcc RPM_S <<
790 <&rpmcc RPM_S <<
791 <&sleep_clk>, <<
792 <&pciephy_0>, <<
793 <&pciephy_1>, <<
794 <&pciephy_2>, <<
795 <&usb3phy>, <<
796 <&ufsphy 0>, <<
797 <&ufsphy 1>, <<
798 <&ufsphy 2>; <<
799 clock-names = "cxo", <<
800 "cxo2", <<
801 "sleep_c <<
802 "pcie_0_ <<
803 "pcie_1_ <<
804 "pcie_2_ <<
805 "usb3_ph <<
806 "ufs_rx_ <<
807 "ufs_rx_ <<
808 "ufs_tx_ <<
809 }; <<
810 <<
811 bimc: interconnect@408000 { <<
812 compatible = "qcom,msm <<
813 reg = <0x00408000 0x5a <<
814 #interconnect-cells = <<
815 }; <<
816 <<
817 tsens0: thermal-sensor@4a9000 <<
818 compatible = "qcom,msm <<
819 reg = <0x004a9000 0x10 <<
820 <0x004a8000 0x10 <<
821 #qcom,sensors = <13>; <<
822 interrupts = <GIC_SPI <<
823 <GIC_SPI <<
824 interrupt-names = "upl <<
825 #thermal-sensor-cells <<
826 }; <<
827 <<
828 tsens1: thermal-sensor@4ad000 <<
829 compatible = "qcom,msm <<
830 reg = <0x004ad000 0x10 <<
831 <0x004ac000 0x10 <<
832 #qcom,sensors = <8>; <<
833 interrupts = <GIC_SPI <<
834 <GIC_SPI <<
835 interrupt-names = "upl <<
836 #thermal-sensor-cells <<
837 }; <<
838 <<
839 cryptobam: dma-controller@6440 <<
840 compatible = "qcom,bam <<
841 reg = <0x00644000 0x24 <<
842 interrupts = <GIC_SPI <<
843 clocks = <&gcc GCC_CE1 <<
844 clock-names = "bam_clk <<
845 #dma-cells = <1>; <<
846 qcom,ee = <0>; <<
847 qcom,controlled-remote <<
848 }; <<
849 <<
850 crypto: crypto@67a000 { <<
851 compatible = "qcom,cry <<
852 reg = <0x0067a000 0x60 <<
853 clocks = <&gcc GCC_CE1 <<
854 <&gcc GCC_CE1 <<
855 <&gcc GCC_CE1 <<
856 clock-names = "iface", <<
857 dmas = <&cryptobam 6>, <<
858 dma-names = "rx", "tx" <<
859 }; <<
860 <<
861 cnoc: interconnect@500000 { <<
862 compatible = "qcom,msm <<
863 reg = <0x00500000 0x10 <<
864 #interconnect-cells = <<
865 }; <<
866 <<
867 snoc: interconnect@524000 { <<
868 compatible = "qcom,msm <<
869 reg = <0x00524000 0x1c <<
870 #interconnect-cells = <<
871 }; <<
872 <<
873 a0noc: interconnect@543000 { <<
874 compatible = "qcom,msm <<
875 reg = <0x00543000 0x60 <<
876 #interconnect-cells = <<
877 clock-names = "aggre0_ <<
878 "aggre0_ <<
879 "aggre0_ <<
880 clocks = <&gcc GCC_AGG <<
881 <&gcc GCC_AGG <<
882 <&gcc GCC_AGG <<
883 power-domains = <&gcc <<
884 }; <<
885 <<
886 a1noc: interconnect@562000 { <<
887 compatible = "qcom,msm <<
888 reg = <0x00562000 0x50 <<
889 #interconnect-cells = <<
890 }; <<
891 <<
892 a2noc: interconnect@583000 { <<
893 compatible = "qcom,msm <<
894 reg = <0x00583000 0x70 <<
895 #interconnect-cells = <<
896 clock-names = "aggre2_ <<
897 clocks = <&gcc GCC_AGG <<
898 <&gcc GCC_UFS <<
899 }; <<
900 <<
901 mnoc: interconnect@5a4000 { <<
902 compatible = "qcom,msm <<
903 reg = <0x005a4000 0x1c <<
904 #interconnect-cells = <<
905 clock-names = "iface"; <<
906 clocks = <&mmcc AHB_CL <<
907 }; <<
908 <<
909 pnoc: interconnect@5c0000 { <<
910 compatible = "qcom,msm <<
911 reg = <0x005c0000 0x30 <<
912 #interconnect-cells = <<
913 }; <<
914 <<
915 tcsr_mutex: hwlock@740000 { <<
916 compatible = "qcom,tcs <<
917 reg = <0x00740000 0x20 <<
918 #hwlock-cells = <1>; <<
919 }; <<
920 <<
921 tcsr_1: syscon@760000 { <<
922 compatible = "qcom,tcs <<
923 reg = <0x00760000 0x20 <<
924 }; <<
925 <<
926 tcsr_2: syscon@7a0000 { <<
927 compatible = "qcom,tcs <<
928 reg = <0x007a0000 0x18 <<
929 }; <<
930 <<
931 mmcc: clock-controller@8c0000 <<
932 compatible = "qcom,mmc <<
933 #clock-cells = <1>; <<
934 #reset-cells = <1>; <<
935 #power-domain-cells = <<
936 reg = <0x008c0000 0x40 <<
937 clocks = <&xo_board>, <<
938 <&gcc GPLL0>, <<
939 <&gcc GCC_MMS <<
940 <&mdss_dsi0_p <<
941 <&mdss_dsi0_p <<
942 <&mdss_dsi1_p <<
943 <&mdss_dsi1_p <<
944 <&mdss_hdmi_p <<
945 clock-names = "xo", <<
946 "gpll0", <<
947 "gcc_mms <<
948 "dsi0pll <<
949 "dsi0pll <<
950 "dsi1pll <<
951 "dsi1pll <<
952 "hdmipll <<
953 assigned-clocks = <&mm <<
954 <&mm <<
955 <&mm <<
956 <&mm <<
957 <&mm <<
958 assigned-clock-rates = <<
959 <<
960 <<
961 <<
962 <<
963 }; <<
964 <<
965 mdss: display-subsystem@900000 <<
966 compatible = "qcom,mds <<
967 <<
968 reg = <0x00900000 0x10 <<
969 <0x009b0000 0x10 <<
970 <0x009b8000 0x10 <<
971 reg-names = "mdss_phys <<
972 "vbif_phys <<
973 "vbif_nrt_ <<
974 <<
975 power-domains = <&mmcc <<
976 interrupts = <GIC_SPI <<
977 <<
978 interrupt-controller; <<
979 #interrupt-cells = <1> <<
980 <<
981 clocks = <&mmcc MDSS_A <<
982 <&mmcc MDSS_M <<
983 clock-names = "iface", <<
984 <<
985 resets = <&mmcc MDSS_B <<
986 <<
987 #address-cells = <1>; <<
988 #size-cells = <1>; <<
989 ranges; <<
990 <<
991 status = "disabled"; <<
992 <<
993 mdp: display-controlle <<
994 compatible = " <<
995 reg = <0x00901 <<
996 reg-names = "m <<
997 <<
998 interrupt-pare <<
999 interrupts = < <<
1000 <<
1001 clocks = <&mm <<
1002 <&mm <<
1003 <&mm <<
1004 <&mm <<
1005 <&mm <<
1006 clock-names = <<
1007 <<
1008 <<
1009 <<
1010 <<
1011 <<
1012 iommus = <&md <<
1013 <<
1014 assigned-cloc <<
1015 <&mm <<
1016 assigned-cloc <<
1017 <192 <<
1018 <<
1019 interconnects <<
1020 <<
1021 <<
1022 interconnect- <<
1023 <<
1024 ports { <<
1025 #addr <<
1026 #size <<
1027 <<
1028 port@ <<
1029 <<
1030 <<
1031 <<
1032 <<
1033 }; <<
1034 <<
1035 port@ <<
1036 <<
1037 <<
1038 <<
1039 <<
1040 }; <<
1041 <<
1042 port@ <<
1043 <<
1044 <<
1045 <<
1046 <<
1047 }; <<
1048 }; <<
1049 }; <<
1050 <<
1051 mdss_dsi0: dsi@994000 <<
1052 compatible = <<
1053 <<
1054 reg = <0x0099 <<
1055 reg-names = " <<
1056 <<
1057 interrupt-par <<
1058 interrupts = <<
1059 <<
1060 clocks = <&mm <<
1061 <&mm <<
1062 <&mm <<
1063 <&mm <<
1064 <&mm <<
1065 <&mm <<
1066 <&mm <<
1067 clock-names = <<
1068 <<
1069 <<
1070 <<
1071 <<
1072 <<
1073 <<
1074 assigned-cloc <<
1075 assigned-cloc <<
1076 <<
1077 phys = <&mdss <<
1078 status = "dis <<
1079 <<
1080 #address-cell <<
1081 #size-cells = <<
1082 <<
1083 ports { <<
1084 #addr <<
1085 #size <<
1086 <<
1087 port@ <<
1088 <<
1089 <<
1090 <<
1091 <<
1092 }; <<
1093 <<
1094 port@ <<
1095 <<
1096 <<
1097 <<
1098 }; <<
1099 }; <<
1100 }; <<
1101 <<
1102 mdss_dsi0_phy: phy@99 <<
1103 compatible = <<
1104 reg = <0x0099 <<
1105 <0x0099 <<
1106 <0x0099 <<
1107 reg-names = " <<
1108 " <<
1109 " <<
1110 <<
1111 #clock-cells <<
1112 #phy-cells = <<
1113 <<
1114 clocks = <&mm <<
1115 clock-names = <<
1116 status = "dis <<
1117 }; <<
1118 <<
1119 mdss_dsi1: dsi@996000 <<
1120 compatible = <<
1121 <<
1122 reg = <0x0099 <<
1123 reg-names = " <<
1124 <<
1125 interrupt-par <<
1126 interrupts = <<
1127 <<
1128 clocks = <&mm <<
1129 <&mm <<
1130 <&mm <<
1131 <&mm <<
1132 <&mm <<
1133 <&mm <<
1134 <&mm <<
1135 clock-names = <<
1136 <<
1137 <<
1138 <<
1139 <<
1140 <<
1141 <<
1142 assigned-cloc <<
1143 assigned-cloc <<
1144 <<
1145 phys = <&mdss <<
1146 status = "dis <<
1147 <<
1148 #address-cell <<
1149 #size-cells = <<
1150 <<
1151 ports { <<
1152 #addr <<
1153 #size <<
1154 <<
1155 port@ <<
1156 <<
1157 <<
1158 <<
1159 <<
1160 }; <<
1161 <<
1162 port@ <<
1163 <<
1164 <<
1165 <<
1166 }; <<
1167 }; <<
1168 }; <<
1169 <<
1170 mdss_dsi1_phy: phy@99 <<
1171 compatible = <<
1172 reg = <0x0099 <<
1173 <0x0099 <<
1174 <0x0099 <<
1175 reg-names = " <<
1176 " <<
1177 " <<
1178 <<
1179 #clock-cells <<
1180 #phy-cells = <<
1181 <<
1182 clocks = <&mm <<
1183 clock-names = <<
1184 status = "dis <<
1185 }; <<
1186 <<
1187 mdss_hdmi: hdmi-tx@9a <<
1188 compatible = <<
1189 reg = <0x009a <<
1190 <0x0007 <<
1191 <0x009e <<
1192 reg-names = " <<
1193 " <<
1194 " <<
1195 <<
1196 interrupt-par <<
1197 interrupts = <<
1198 <<
1199 clocks = <&mm <<
1200 <&mm <<
1201 <&mm <<
1202 <&mm <<
1203 <&mm <<
1204 clock-names = <<
1205 "mdp_ <<
1206 "ifac <<
1207 "core <<
1208 "alt_ <<
1209 "extp <<
1210 <<
1211 phys = <&mdss <<
1212 #sound-dai-ce <<
1213 <<
1214 status = "dis <<
1215 <<
1216 ports { <<
1217 #addr <<
1218 #size <<
1219 <<
1220 port@ <<
1221 <<
1222 <<
1223 <<
1224 <<
1225 }; <<
1226 }; <<
1227 }; <<
1228 <<
1229 mdss_hdmi_phy: phy@9a <<
1230 #phy-cells = <<
1231 compatible = <<
1232 reg = <0x009a <<
1233 <0x009a <<
1234 <0x009a <<
1235 <0x009a <<
1236 <0x009a <<
1237 <0x009a <<
1238 reg-names = " <<
1239 " <<
1240 " <<
1241 " <<
1242 " <<
1243 " <<
1244 <<
1245 clocks = <&mm <<
1246 <&gc <<
1247 <&xo <<
1248 clock-names = <<
1249 <<
1250 <<
1251 <<
1252 #clock-cells <<
1253 <<
1254 status = "dis <<
1255 }; <<
1256 }; <<
1257 <<
1258 gpu: gpu@b00000 { <<
1259 compatible = "qcom,ad <<
1260 <<
1261 reg = <0x00b00000 0x3 <<
1262 reg-names = "kgsl_3d0 <<
1263 <<
1264 interrupts = <GIC_SPI <<
1265 <<
1266 clocks = <&mmcc GPU_G <<
1267 <&mmcc GPU_AH <<
1268 <&mmcc GPU_GX <<
1269 <&gcc GCC_BIM <<
1270 <&gcc GCC_MMS <<
1271 <<
1272 clock-names = "core", <<
1273 "iface", <<
1274 "rbbmtimer", <<
1275 "mem", <<
1276 "mem_iface"; <<
1277 <<
1278 interconnects = <&bim <<
1279 interconnect-names = <<
1280 <<
1281 power-domains = <&mmc <<
1282 iommus = <&adreno_smm <<
1283 <<
1284 nvmem-cells = <&speed <<
1285 nvmem-cell-names = "s <<
1286 <<
1287 operating-points-v2 = <<
1288 <<
1289 status = "disabled"; <<
1290 <<
1291 #cooling-cells = <2>; <<
1292 <<
1293 gpu_opp_table: opp-ta <<
1294 compatible = <<
1295 <<
1296 /* <<
1297 * 624Mhz is <<
1298 * 560Mhz is <<
1299 * All the re <<
1300 */ <<
1301 opp-624000000 <<
1302 opp-h <<
1303 opp-s <<
1304 }; <<
1305 opp-560000000 <<
1306 opp-h <<
1307 opp-s <<
1308 }; <<
1309 opp-510000000 <<
1310 opp-h <<
1311 opp-s <<
1312 }; <<
1313 opp-401800000 <<
1314 opp-h <<
1315 opp-s <<
1316 }; <<
1317 opp-315000000 <<
1318 opp-h <<
1319 opp-s <<
1320 }; <<
1321 opp-214000000 <<
1322 opp-h <<
1323 opp-s <<
1324 }; <<
1325 opp-133000000 <<
1326 opp-h <<
1327 opp-s <<
1328 }; <<
1329 }; <<
1330 <<
1331 zap-shader { <<
1332 memory-region <<
1333 }; <<
1334 }; <<
1335 <<
1336 tlmm: pinctrl@1010000 { <<
1337 compatible = "qcom,ms <<
1338 reg = <0x01010000 0x3 <<
1339 interrupts = <GIC_SPI <<
1340 gpio-controller; <<
1341 gpio-ranges = <&tlmm <<
1342 #gpio-cells = <2>; <<
1343 interrupt-controller; <<
1344 #interrupt-cells = <2 <<
1345 <<
1346 blsp1_spi1_default: b <<
1347 spi-pins { <<
1348 pins <<
1349 funct <<
1350 drive <<
1351 bias- <<
1352 }; <<
1353 <<
1354 cs-pins { <<
1355 pins <<
1356 funct <<
1357 drive <<
1358 bias- <<
1359 outpu <<
1360 }; <<
1361 }; <<
1362 <<
1363 blsp1_spi1_sleep: bls <<
1364 pins = "gpio0 <<
1365 function = "g <<
1366 drive-strengt <<
1367 bias-pull-dow <<
1368 }; <<
1369 <<
1370 blsp2_uart2_2pins_def <<
1371 pins = "gpio4 <<
1372 function = "b <<
1373 drive-strengt <<
1374 bias-disable; <<
1375 }; <<
1376 <<
1377 blsp2_uart2_2pins_sle <<
1378 pins = "gpio4 <<
1379 function = "g <<
1380 drive-strengt <<
1381 bias-disable; <<
1382 }; <<
1383 <<
1384 blsp2_i2c2_default: b <<
1385 pins = "gpio6 <<
1386 function = "b <<
1387 drive-strengt <<
1388 bias-disable; <<
1389 }; <<
1390 <<
1391 blsp2_i2c2_sleep: bls <<
1392 pins = "gpio6 <<
1393 function = "g <<
1394 drive-strengt <<
1395 bias-disable; <<
1396 }; <<
1397 <<
1398 blsp1_i2c6_default: b <<
1399 pins = "gpio2 <<
1400 function = "b <<
1401 drive-strengt <<
1402 bias-disable; <<
1403 }; <<
1404 <<
1405 blsp1_i2c6_sleep: bls <<
1406 pins = "gpio2 <<
1407 function = "g <<
1408 drive-strengt <<
1409 bias-pull-up; <<
1410 }; <<
1411 <<
1412 cci0_default: cci0-de <<
1413 pins = "gpio1 <<
1414 function = "c <<
1415 drive-strengt <<
1416 bias-disable; <<
1417 }; <<
1418 <<
1419 camera0_state_on: <<
1420 camera_rear_default: <<
1421 camera0_mclk: <<
1422 pins <<
1423 funct <<
1424 drive <<
1425 bias- <<
1426 }; <<
1427 <<
1428 camera0_rst: <<
1429 pins <<
1430 funct <<
1431 drive <<
1432 bias- <<
1433 }; <<
1434 <<
1435 camera0_pwdn: <<
1436 pins <<
1437 funct <<
1438 drive <<
1439 bias- <<
1440 }; <<
1441 }; <<
1442 <<
1443 cci1_default: cci1-de <<
1444 pins = "gpio1 <<
1445 function = "c <<
1446 drive-strengt <<
1447 bias-disable; <<
1448 }; <<
1449 <<
1450 camera1_state_on: <<
1451 camera_board_default: <<
1452 mclk1-pins { <<
1453 pins <<
1454 funct <<
1455 drive <<
1456 bias- <<
1457 }; <<
1458 <<
1459 pwdn-pins { <<
1460 pins <<
1461 funct <<
1462 drive <<
1463 bias- <<
1464 }; <<
1465 <<
1466 rst-pins { <<
1467 pins <<
1468 funct <<
1469 drive <<
1470 bias- <<
1471 }; <<
1472 }; <<
1473 <<
1474 camera2_state_on: <<
1475 camera_front_default: <<
1476 camera2_mclk: <<
1477 pins <<
1478 funct <<
1479 drive <<
1480 bias- <<
1481 }; <<
1482 <<
1483 camera2_rst: <<
1484 pins <<
1485 funct <<
1486 drive <<
1487 bias- <<
1488 }; <<
1489 <<
1490 pwdn-pins { <<
1491 pins <<
1492 funct <<
1493 drive <<
1494 bias- <<
1495 }; <<
1496 }; <<
1497 <<
1498 pcie0_state_on: pcie0 <<
1499 perst-pins { <<
1500 pins <<
1501 funct <<
1502 drive <<
1503 bias- <<
1504 }; <<
1505 <<
1506 clkreq-pins { <<
1507 pins <<
1508 funct <<
1509 drive <<
1510 bias- <<
1511 }; <<
1512 <<
1513 wake-pins { <<
1514 pins <<
1515 funct <<
1516 drive <<
1517 bias- <<
1518 }; <<
1519 }; <<
1520 <<
1521 pcie0_state_off: pcie <<
1522 perst-pins { <<
1523 pins <<
1524 funct <<
1525 drive <<
1526 bias- <<
1527 }; <<
1528 <<
1529 clkreq-pins { <<
1530 pins <<
1531 funct <<
1532 drive <<
1533 bias- <<
1534 }; <<
1535 <<
1536 wake-pins { <<
1537 pins <<
1538 funct <<
1539 drive <<
1540 bias- <<
1541 }; <<
1542 }; <<
1543 <<
1544 blsp1_uart2_default: <<
1545 pins = "gpio4 <<
1546 function = "b <<
1547 drive-strengt <<
1548 bias-disable; <<
1549 }; <<
1550 <<
1551 blsp1_uart2_sleep: bl <<
1552 pins = "gpio4 <<
1553 function = "g <<
1554 drive-strengt <<
1555 bias-disable; <<
1556 }; <<
1557 <<
1558 blsp1_i2c3_default: b <<
1559 pins = "gpio4 <<
1560 function = "b <<
1561 drive-strengt <<
1562 bias-disable; <<
1563 }; <<
1564 <<
1565 blsp1_i2c3_sleep: bls <<
1566 pins = "gpio4 <<
1567 function = "g <<
1568 drive-strengt <<
1569 bias-disable; <<
1570 }; <<
1571 <<
1572 blsp2_uart3_4pins_def <<
1573 pins = "gpio4 <<
1574 function = "b <<
1575 drive-strengt <<
1576 bias-disable; <<
1577 }; <<
1578 <<
1579 blsp2_uart3_4pins_sle <<
1580 pins = "gpio4 <<
1581 function = "b <<
1582 drive-strengt <<
1583 bias-disable; <<
1584 }; <<
1585 <<
1586 blsp2_i2c3_default: b <<
1587 pins = "gpio5 <<
1588 function = "b <<
1589 drive-strengt <<
1590 bias-disable; <<
1591 }; <<
1592 <<
1593 blsp2_i2c3_sleep: bls <<
1594 pins = "gpio5 <<
1595 function = "g <<
1596 drive-strengt <<
1597 bias-disable; <<
1598 }; <<
1599 <<
1600 wcd_intr_default: wcd <<
1601 pins = "gpio5 <<
1602 function = "g <<
1603 drive-strengt <<
1604 bias-pull-dow <<
1605 }; <<
1606 <<
1607 blsp2_i2c1_default: b <<
1608 pins = "gpio5 <<
1609 function = "b <<
1610 drive-strengt <<
1611 bias-disable; <<
1612 }; <<
1613 <<
1614 blsp2_i2c1_sleep: bls <<
1615 pins = "gpio5 <<
1616 function = "g <<
1617 drive-strengt <<
1618 bias-disable; <<
1619 }; <<
1620 <<
1621 blsp2_i2c5_default: b <<
1622 pins = "gpio6 <<
1623 function = "b <<
1624 drive-strengt <<
1625 bias-disable; <<
1626 }; <<
1627 <<
1628 /* Sleep state for BL <<
1629 <<
1630 cdc_reset_active: cdc <<
1631 pins = "gpio6 <<
1632 function = "g <<
1633 drive-strengt <<
1634 bias-pull-dow <<
1635 output-high; <<
1636 }; <<
1637 <<
1638 cdc_reset_sleep: cdc- <<
1639 pins = "gpio6 <<
1640 function = "g <<
1641 drive-strengt <<
1642 bias-disable; <<
1643 output-low; <<
1644 }; <<
1645 <<
1646 blsp2_spi6_default: b <<
1647 spi-pins { <<
1648 pins <<
1649 funct <<
1650 drive <<
1651 bias- <<
1652 }; <<
1653 <<
1654 cs-pins { <<
1655 pins <<
1656 funct <<
1657 drive <<
1658 bias- <<
1659 outpu <<
1660 }; <<
1661 }; <<
1662 <<
1663 blsp2_spi6_sleep: bls <<
1664 pins = "gpio8 <<
1665 function = "g <<
1666 drive-strengt <<
1667 bias-pull-dow <<
1668 }; <<
1669 <<
1670 blsp2_i2c6_default: b <<
1671 pins = "gpio8 <<
1672 function = "b <<
1673 drive-strengt <<
1674 bias-disable; <<
1675 }; <<
1676 <<
1677 blsp2_i2c6_sleep: bls <<
1678 pins = "gpio8 <<
1679 function = "g <<
1680 drive-strengt <<
1681 bias-disable; <<
1682 }; <<
1683 <<
1684 pcie1_state_on: pcie1 <<
1685 perst-pins { <<
1686 pins <<
1687 funct <<
1688 drive <<
1689 bias- <<
1690 }; <<
1691 <<
1692 clkreq-pins { <<
1693 pins <<
1694 funct <<
1695 drive <<
1696 bias- <<
1697 }; <<
1698 <<
1699 wake-pins { <<
1700 pins <<
1701 funct <<
1702 drive <<
1703 bias- <<
1704 }; <<
1705 }; <<
1706 <<
1707 pcie1_state_off: pcie <<
1708 /* Perst is m <<
1709 clkreq-pins { <<
1710 pins <<
1711 funct <<
1712 drive <<
1713 bias- <<
1714 }; <<
1715 <<
1716 wake-pins { <<
1717 pins <<
1718 funct <<
1719 drive <<
1720 bias- <<
1721 }; <<
1722 }; <<
1723 <<
1724 pcie2_state_on: pcie2 <<
1725 perst-pins { <<
1726 pins <<
1727 funct <<
1728 drive <<
1729 bias- <<
1730 }; <<
1731 <<
1732 clkreq-pins { <<
1733 pins <<
1734 funct <<
1735 drive <<
1736 bias- <<
1737 }; <<
1738 <<
1739 wake-pins { <<
1740 pins <<
1741 funct <<
1742 drive <<
1743 bias- <<
1744 }; <<
1745 }; <<
1746 <<
1747 pcie2_state_off: pcie <<
1748 /* Perst is m <<
1749 clkreq-pins { <<
1750 pins <<
1751 funct <<
1752 drive <<
1753 bias- <<
1754 }; <<
1755 <<
1756 wake-pins { <<
1757 pins <<
1758 funct <<
1759 drive <<
1760 bias- <<
1761 }; <<
1762 }; <<
1763 <<
1764 sdc1_state_on: sdc1-o <<
1765 clk-pins { <<
1766 pins <<
1767 bias- <<
1768 drive <<
1769 }; <<
1770 <<
1771 cmd-pins { <<
1772 pins <<
1773 bias- <<
1774 drive <<
1775 }; <<
1776 <<
1777 data-pins { <<
1778 pins <<
1779 bias- <<
1780 drive <<
1781 }; <<
1782 <<
1783 rclk-pins { <<
1784 pins <<
1785 bias- <<
1786 }; <<
1787 }; <<
1788 <<
1789 sdc1_state_off: sdc1- <<
1790 clk-pins { <<
1791 pins <<
1792 bias- <<
1793 drive <<
1794 }; <<
1795 <<
1796 cmd-pins { <<
1797 pins <<
1798 bias- <<
1799 drive <<
1800 }; <<
1801 <<
1802 data-pins { <<
1803 pins <<
1804 bias- <<
1805 drive <<
1806 }; <<
1807 <<
1808 rclk-pins { <<
1809 pins <<
1810 bias- <<
1811 }; <<
1812 }; <<
1813 <<
1814 sdc2_state_on: sdc2-o <<
1815 clk-pins { <<
1816 pins <<
1817 bias- <<
1818 drive <<
1819 }; <<
1820 <<
1821 cmd-pins { <<
1822 pins <<
1823 bias- <<
1824 drive <<
1825 }; <<
1826 <<
1827 data-pins { <<
1828 pins <<
1829 bias- <<
1830 drive <<
1831 }; <<
1832 }; <<
1833 <<
1834 sdc2_state_off: sdc2- <<
1835 clk-pins { <<
1836 pins <<
1837 bias- <<
1838 drive <<
1839 }; <<
1840 <<
1841 cmd-pins { <<
1842 pins <<
1843 bias- <<
1844 drive <<
1845 }; <<
1846 <<
1847 data-pins { <<
1848 pins <<
1849 bias- <<
1850 drive <<
1851 }; <<
1852 }; <<
1853 }; <<
1854 <<
1855 sram@290000 { <<
1856 compatible = "qcom,rp <<
1857 reg = <0x00290000 0x1 <<
1858 }; <<
1859 <<
1860 spmi_bus: spmi@400f000 { <<
1861 compatible = "qcom,sp <<
1862 reg = <0x0400f000 0x1 <<
1863 <0x04400000 0x8 <<
1864 <0x04c00000 0x8 <<
1865 <0x05800000 0x2 <<
1866 <0x0400a000 0x0 <<
1867 reg-names = "core", " <<
1868 interrupt-names = "pe <<
1869 interrupts = <GIC_SPI <<
1870 qcom,ee = <0>; <<
1871 qcom,channel = <0>; <<
1872 #address-cells = <2>; <<
1873 #size-cells = <0>; <<
1874 interrupt-controller; <<
1875 #interrupt-cells = <4 <<
1876 }; <<
1877 <<
1878 bus@0 { <<
1879 power-domains = <&gcc <<
1880 compatible = "simple- <<
1881 #address-cells = <1>; <<
1882 #size-cells = <1>; <<
1883 ranges = <0x0 0x0 0xf <<
1884 <<
1885 pcie0: pcie@600000 { <<
1886 compatible = <<
1887 status = "dis <<
1888 power-domains <<
1889 bus-range = < <<
1890 num-lanes = < <<
1891 <<
1892 reg = <0x0060 <<
1893 <0x0c00 <<
1894 <0x0c00 <<
1895 <0x0c10 <<
1896 reg-names = " <<
1897 <<
1898 phys = <&pcie <<
1899 phy-names = " <<
1900 <<
1901 #address-cell <<
1902 #size-cells = <<
1903 ranges = <0x0 <<
1904 <0x0 <<
1905 <<
1906 device_type = <<
1907 <<
1908 interrupts = <<
1909 interrupt-nam <<
1910 #interrupt-ce <<
1911 interrupt-map <<
1912 interrupt-map <<
1913 <<
1914 <<
1915 <<
1916 <<
1917 pinctrl-names <<
1918 pinctrl-0 = < <<
1919 pinctrl-1 = < <<
1920 <<
1921 linux,pci-dom <<
1922 <<
1923 clocks = <&gc <<
1924 <&gcc <<
1925 <&gcc <<
1926 <&gcc <<
1927 <&gcc <<
1928 <<
1929 clock-names = <<
1930 <<
1931 <<
1932 <<
1933 <<
1934 <<
1935 pcie@0 { <<
1936 devic <<
1937 reg = <<
1938 bus-r <<
1939 <<
1940 #addr <<
1941 #size <<
1942 range <<
1943 }; <<
1944 }; <<
1945 <<
1946 pcie1: pcie@608000 { <<
1947 compatible = <<
1948 power-domains <<
1949 bus-range = < <<
1950 num-lanes = < <<
1951 <<
1952 status = "dis <<
1953 <<
1954 reg = <0x0060 <<
1955 <0x0d00 <<
1956 <0x0d00 <<
1957 <0x0d10 <<
1958 <<
1959 reg-names = " <<
1960 <<
1961 phys = <&pcie <<
1962 phy-names = " <<
1963 <<
1964 #address-cell <<
1965 #size-cells = <<
1966 ranges = <0x0 <<
1967 <0x0 <<
1968 <<
1969 device_type = <<
1970 <<
1971 interrupts = <<
1972 interrupt-nam <<
1973 #interrupt-ce <<
1974 interrupt-map <<
1975 interrupt-map <<
1976 <<
1977 <<
1978 <<
1979 <<
1980 pinctrl-names <<
1981 pinctrl-0 = < <<
1982 pinctrl-1 = < <<
1983 <<
1984 linux,pci-dom <<
1985 <<
1986 clocks = <&gc <<
1987 <&gcc <<
1988 <&gcc <<
1989 <&gcc <<
1990 <&gcc <<
1991 <<
1992 clock-names = <<
1993 <<
1994 <<
1995 <<
1996 <<
1997 <<
1998 pcie@0 { <<
1999 devic <<
2000 reg = <<
2001 bus-r <<
2002 <<
2003 #addr <<
2004 #size <<
2005 range <<
2006 }; <<
2007 }; <<
2008 <<
2009 pcie2: pcie@610000 { <<
2010 compatible = <<
2011 power-domains <<
2012 bus-range = < <<
2013 num-lanes = < <<
2014 status = "dis <<
2015 reg = <0x0061 <<
2016 <0x0e00 <<
2017 <0x0e00 <<
2018 <0x0e10 <<
2019 <<
2020 reg-names = " <<
2021 <<
2022 phys = <&pcie <<
2023 phy-names = " <<
2024 <<
2025 #address-cell <<
2026 #size-cells = <<
2027 ranges = <0x0 <<
2028 <0x0 <<
2029 <<
2030 device_type = <<
2031 <<
2032 interrupts = <<
2033 interrupt-nam <<
2034 #interrupt-ce <<
2035 interrupt-map <<
2036 interrupt-map <<
2037 <<
2038 <<
2039 <<
2040 <<
2041 pinctrl-names <<
2042 pinctrl-0 = < <<
2043 pinctrl-1 = < <<
2044 <<
2045 linux,pci-dom <<
2046 clocks = <&gc <<
2047 <&gcc <<
2048 <&gcc <<
2049 <&gcc <<
2050 <&gcc <<
2051 <<
2052 clock-names = <<
2053 <<
2054 <<
2055 <<
2056 <<
2057 <<
2058 pcie@0 { <<
2059 devic <<
2060 reg = <<
2061 bus-r <<
2062 <<
2063 #addr <<
2064 #size <<
2065 range <<
2066 }; <<
2067 }; <<
2068 }; <<
2069 <<
2070 ufshc: ufshc@624000 { <<
2071 compatible = "qcom,ms <<
2072 "jedec,u <<
2073 reg = <0x00624000 0x2 <<
2074 interrupts = <GIC_SPI <<
2075 <<
2076 phys = <&ufsphy>; <<
2077 phy-names = "ufsphy"; <<
2078 <<
2079 power-domains = <&gcc <<
2080 <<
2081 clock-names = <<
2082 "core_clk", <<
2083 "bus_clk", <<
2084 "bus_aggr_clk <<
2085 "iface_clk", <<
2086 "core_clk_uni <<
2087 "core_clk_ice <<
2088 "ref_clk", <<
2089 "tx_lane0_syn <<
2090 "rx_lane0_syn <<
2091 clocks = <<
2092 <&gcc GCC_UFS <<
2093 <&gcc GCC_SYS <<
2094 <&gcc GCC_AGG <<
2095 <&gcc GCC_UFS <<
2096 <&gcc GCC_UFS <<
2097 <&gcc GCC_UFS <<
2098 <&rpmcc RPM_S <<
2099 <&gcc GCC_UFS <<
2100 <&gcc GCC_UFS <<
2101 freq-table-hz = <<
2102 <100000000 20 <<
2103 <0 0>, <<
2104 <0 0>, <<
2105 <0 0>, <<
2106 <75000000 150 <<
2107 <150000000 30 <<
2108 <0 0>, <<
2109 <0 0>, <<
2110 <0 0>; <<
2111 <<
2112 interconnects = <&a2n <<
2113 <&bim <<
2114 interconnect-names = <<
2115 <<
2116 lanes-per-direction = <<
2117 #reset-cells = <1>; <<
2118 status = "disabled"; <<
2119 }; <<
2120 <<
2121 ufsphy: phy@627000 { <<
2122 compatible = "qcom,ms <<
2123 reg = <0x00627000 0x1 <<
2124 <<
2125 clocks = <&rpmcc RPM_ <<
2126 clock-names = "ref", <<
2127 <<
2128 resets = <&ufshc 0>; <<
2129 reset-names = "ufsphy <<
2130 <<
2131 #clock-cells = <1>; <<
2132 #phy-cells = <0>; <<
2133 <<
2134 status = "disabled"; <<
2135 }; <<
2136 <<
2137 camss: camss@a34000 { <<
2138 compatible = "qcom,ms <<
2139 reg = <0x00a34000 0x1 <<
2140 <0x00a00030 0x4 <<
2141 <0x00a35000 0x1 <<
2142 <0x00a00038 0x4 <<
2143 <0x00a36000 0x1 <<
2144 <0x00a00040 0x4 <<
2145 <0x00a30000 0x1 <<
2146 <0x00a30400 0x1 <<
2147 <0x00a30800 0x1 <<
2148 <0x00a30c00 0x1 <<
2149 <0x00a31000 0x5 <<
2150 <0x00a00020 0x1 <<
2151 <0x00a10000 0x1 <<
2152 <0x00a14000 0x1 <<
2153 reg-names = "csiphy0" <<
2154 "csiphy0_clk_ <<
2155 "csiphy1", <<
2156 "csiphy1_clk_ <<
2157 "csiphy2", <<
2158 "csiphy2_clk_ <<
2159 "csid0", <<
2160 "csid1", <<
2161 "csid2", <<
2162 "csid3", <<
2163 "ispif", <<
2164 "csi_clk_mux" <<
2165 "vfe0", <<
2166 "vfe1"; <<
2167 interrupts = <GIC_SPI <<
2168 <GIC_SPI 79 I <<
2169 <GIC_SPI 80 I <<
2170 <GIC_SPI 296 <<
2171 <GIC_SPI 297 <<
2172 <GIC_SPI 298 <<
2173 <GIC_SPI 299 <<
2174 <GIC_SPI 309 <<
2175 <GIC_SPI 314 <<
2176 <GIC_SPI 315 <<
2177 interrupt-names = "cs <<
2178 "csiphy1", <<
2179 "csiphy2", <<
2180 "csid0", <<
2181 "csid1", <<
2182 "csid2", <<
2183 "csid3", <<
2184 "ispif", <<
2185 "vfe0", <<
2186 "vfe1"; <<
2187 power-domains = <&mmc <<
2188 <&mmc <<
2189 clocks = <&mmcc CAMSS <<
2190 <&mmcc CAMSS_ <<
2191 <&mmcc CAMSS_ <<
2192 <&mmcc CAMSS_ <<
2193 <&mmcc CAMSS_ <<
2194 <&mmcc CAMSS_ <<
2195 <&mmcc CAMSS_ <<
2196 <&mmcc CAMSS_ <<
2197 <&mmcc CAMSS_ <<
2198 <&mmcc CAMSS_ <<
2199 <&mmcc CAMSS_ <<
2200 <&mmcc CAMSS_ <<
2201 <&mmcc CAMSS_ <<
2202 <&mmcc CAMSS_ <<
2203 <&mmcc CAMSS_ <<
2204 <&mmcc CAMSS_ <<
2205 <&mmcc CAMSS_ <<
2206 <&mmcc CAMSS_ <<
2207 <&mmcc CAMSS_ <<
2208 <&mmcc CAMSS_ <<
2209 <&mmcc CAMSS_ <<
2210 <&mmcc CAMSS_ <<
2211 <&mmcc CAMSS_ <<
2212 <&mmcc CAMSS_ <<
2213 <&mmcc CAMSS_ <<
2214 <&mmcc CAMSS_ <<
2215 <&mmcc CAMSS_ <<
2216 <&mmcc CAMSS_ <<
2217 <&mmcc CAMSS_ <<
2218 <&mmcc CAMSS_ <<
2219 <&mmcc CAMSS_ <<
2220 <&mmcc CAMSS_ <<
2221 <&mmcc CAMSS_ <<
2222 <&mmcc CAMSS_ <<
2223 <&mmcc CAMSS_ <<
2224 <&mmcc CAMSS_ <<
2225 clock-names = "top_ah <<
2226 "ispif_ahb", <<
2227 "csiphy0_time <<
2228 "csiphy1_time <<
2229 "csiphy2_time <<
2230 "csi0_ahb", <<
2231 "csi0", <<
2232 "csi0_phy", <<
2233 "csi0_pix", <<
2234 "csi0_rdi", <<
2235 "csi1_ahb", <<
2236 "csi1", <<
2237 "csi1_phy", <<
2238 "csi1_pix", <<
2239 "csi1_rdi", <<
2240 "csi2_ahb", <<
2241 "csi2", <<
2242 "csi2_phy", <<
2243 "csi2_pix", <<
2244 "csi2_rdi", <<
2245 "csi3_ahb", <<
2246 "csi3", <<
2247 "csi3_phy", <<
2248 "csi3_pix", <<
2249 "csi3_rdi", <<
2250 "ahb", <<
2251 "vfe0", <<
2252 "csi_vfe0", <<
2253 "vfe0_ahb", <<
2254 "vfe0_stream" <<
2255 "vfe1", <<
2256 "csi_vfe1", <<
2257 "vfe1_ahb", <<
2258 "vfe1_stream" <<
2259 "vfe_ahb", <<
2260 "vfe_axi"; <<
2261 iommus = <&vfe_smmu 0 <<
2262 <&vfe_smmu 1 <<
2263 <&vfe_smmu 2 <<
2264 <&vfe_smmu 3 <<
2265 status = "disabled"; <<
2266 ports { <<
2267 #address-cell <<
2268 #size-cells = <<
2269 }; <<
2270 }; <<
2271 <<
2272 cci: cci@a0c000 { <<
2273 compatible = "qcom,ms <<
2274 #address-cells = <1>; <<
2275 #size-cells = <0>; <<
2276 reg = <0xa0c000 0x100 <<
2277 interrupts = <GIC_SPI <<
2278 power-domains = <&mmc <<
2279 clocks = <&mmcc CAMSS <<
2280 <&mmcc CAMSS <<
2281 <&mmcc CAMSS <<
2282 <&mmcc CAMSS <<
2283 clock-names = "camss_ <<
2284 "cci_ah <<
2285 "cci", <<
2286 "camss_ <<
2287 assigned-clocks = <&m <<
2288 <&m <<
2289 assigned-clock-rates <<
2290 pinctrl-names = "defa <<
2291 pinctrl-0 = <&cci0_de <<
2292 status = "disabled"; <<
2293 <<
2294 cci_i2c0: i2c-bus@0 { <<
2295 reg = <0>; <<
2296 clock-frequen <<
2297 #address-cell <<
2298 #size-cells = <<
2299 }; <<
2300 <<
2301 cci_i2c1: i2c-bus@1 { <<
2302 reg = <1>; <<
2303 clock-frequen <<
2304 #address-cell <<
2305 #size-cells = <<
2306 }; <<
2307 }; <<
2308 <<
2309 adreno_smmu: iommu@b40000 { <<
2310 compatible = "qcom,ms <<
2311 reg = <0x00b40000 0x1 <<
2312 <<
2313 #global-interrupts = <<
2314 interrupts = <GIC_SPI <<
2315 <GIC_SPI <<
2316 <GIC_SPI <<
2317 #iommu-cells = <1>; <<
2318 <<
2319 clocks = <&gcc GCC_MM <<
2320 <&mmcc GPU_A <<
2321 clock-names = "bus", <<
2322 <<
2323 power-domains = <&mmc <<
2324 }; <<
2325 <<
2326 venus: video-codec@c00000 { <<
2327 compatible = "qcom,ms <<
2328 reg = <0x00c00000 0xf <<
2329 interrupts = <GIC_SPI <<
2330 power-domains = <&mmc <<
2331 clocks = <&mmcc VIDEO <<
2332 <&mmcc VIDEO <<
2333 <&mmcc VIDEO <<
2334 <&mmcc VIDEO <<
2335 clock-names = "core", <<
2336 interconnects = <&mno <<
2337 <&bim <<
2338 interconnect-names = <<
2339 iommus = <&venus_smmu <<
2340 <&venus_smmu <<
2341 <&venus_smmu <<
2342 <&venus_smmu <<
2343 <&venus_smmu <<
2344 <&venus_smmu <<
2345 <&venus_smmu <<
2346 <&venus_smmu <<
2347 <&venus_smmu <<
2348 <&venus_smmu <<
2349 <&venus_smmu <<
2350 <&venus_smmu <<
2351 <&venus_smmu <<
2352 <&venus_smmu <<
2353 <&venus_smmu <<
2354 <&venus_smmu <<
2355 <&venus_smmu <<
2356 <&venus_smmu <<
2357 <&venus_smmu <<
2358 <&venus_smmu <<
2359 memory-region = <&ven <<
2360 status = "disabled"; <<
2361 <<
2362 video-decoder { <<
2363 compatible = <<
2364 clocks = <&mm <<
2365 clock-names = <<
2366 power-domains <<
2367 }; <<
2368 <<
2369 video-encoder { <<
2370 compatible = <<
2371 clocks = <&mm <<
2372 clock-names = <<
2373 power-domains <<
2374 }; <<
2375 }; <<
2376 <<
2377 mdp_smmu: iommu@d00000 { <<
2378 compatible = "qcom,ms <<
2379 reg = <0x00d00000 0x1 <<
2380 <<
2381 #global-interrupts = <<
2382 interrupts = <GIC_SPI <<
2383 <GIC_SPI <<
2384 <GIC_SPI <<
2385 #iommu-cells = <1>; <<
2386 clocks = <&mmcc SMMU_ <<
2387 <&mmcc SMMU_ <<
2388 clock-names = "bus", <<
2389 <<
2390 power-domains = <&mmc <<
2391 }; <<
2392 <<
2393 venus_smmu: iommu@d40000 { <<
2394 compatible = "qcom,ms <<
2395 reg = <0x00d40000 0x2 <<
2396 #global-interrupts = <<
2397 interrupts = <GIC_SPI <<
2398 <GIC_SPI <<
2399 <GIC_SPI <<
2400 <GIC_SPI <<
2401 <GIC_SPI <<
2402 <GIC_SPI <<
2403 <GIC_SPI <<
2404 <GIC_SPI <<
2405 power-domains = <&mmc <<
2406 clocks = <&mmcc SMMU_ <<
2407 <&mmcc SMMU_ <<
2408 clock-names = "bus", <<
2409 #iommu-cells = <1>; <<
2410 status = "okay"; <<
2411 }; <<
2412 <<
2413 vfe_smmu: iommu@da0000 { <<
2414 compatible = "qcom,ms <<
2415 reg = <0x00da0000 0x1 <<
2416 <<
2417 #global-interrupts = <<
2418 interrupts = <GIC_SPI <<
2419 <GIC_SPI <<
2420 <GIC_SPI <<
2421 power-domains = <&mmc <<
2422 clocks = <&mmcc SMMU_ <<
2423 <&mmcc SMMU_ <<
2424 clock-names = "bus", <<
2425 #iommu-cells = <1>; <<
2426 }; <<
2427 <<
2428 lpass_q6_smmu: iommu@1600000 <<
2429 compatible = "qcom,ms <<
2430 reg = <0x01600000 0x2 <<
2431 #iommu-cells = <1>; <<
2432 power-domains = <&gcc <<
2433 <<
2434 #global-interrupts = <<
2435 interrupts = <GIC_SPI <<
2436 <GIC_SPI 226 <<
2437 <GIC_SPI 393 <<
2438 <GIC_SPI 394 <<
2439 <GIC_SPI 395 <<
2440 <GIC_SPI 396 <<
2441 <GIC_SPI 397 <<
2442 <GIC_SPI 398 <<
2443 <GIC_SPI 399 <<
2444 <GIC_SPI 400 <<
2445 <GIC_SPI 401 <<
2446 <GIC_SPI 402 <<
2447 <GIC_SPI 403 <<
2448 <<
2449 clocks = <&gcc GCC_HL <<
2450 <&gcc GCC_HL <<
2451 clock-names = "bus", <<
2452 }; <<
2453 <<
2454 slpi_pil: remoteproc@1c00000 <<
2455 compatible = "qcom,ms <<
2456 reg = <0x01c00000 0x4 <<
2457 <<
2458 interrupts-extended = <<
2459 <<
2460 <<
2461 <<
2462 <<
2463 interrupt-names = "wd <<
2464 "fa <<
2465 "re <<
2466 "ha <<
2467 "st <<
2468 <<
2469 clocks = <&xo_board>; <<
2470 clock-names = "xo"; <<
2471 <<
2472 memory-region = <&slp <<
2473 <<
2474 qcom,smem-states = <& <<
2475 qcom,smem-state-names <<
2476 <<
2477 power-domains = <&rpm <<
2478 power-domain-names = <<
2479 <<
2480 status = "disabled"; <<
2481 <<
2482 glink-edge { <<
2483 interrupts = <<
2484 label = "dsps <<
2485 qcom,remote-p <<
2486 mboxes = <&ap <<
2487 }; <<
2488 <<
2489 smd-edge { <<
2490 interrupts = <<
2491 <<
2492 label = "dsps <<
2493 mboxes = <&ap <<
2494 qcom,smd-edge <<
2495 qcom,remote-p <<
2496 }; <<
2497 }; <<
2498 <<
2499 mss_pil: remoteproc@2080000 { <<
2500 compatible = "qcom,ms <<
2501 reg = <0x2080000 0x10 <<
2502 <0x2180000 0x02 <<
2503 reg-names = "qdsp6", <<
2504 <<
2505 interrupts-extended = <<
2506 <<
2507 <<
2508 <<
2509 <<
2510 <<
2511 interrupt-names = "wd <<
2512 "ha <<
2513 "sh <<
2514 <<
2515 clocks = <&gcc GCC_MS <<
2516 <&gcc GCC_MS <<
2517 <&gcc GCC_BO <<
2518 <&xo_board>, <<
2519 <&gcc GCC_MS <<
2520 <&gcc GCC_MS <<
2521 <&gcc GCC_MS <<
2522 <&rpmcc RPM_ <<
2523 clock-names = "iface" <<
2524 "bus", <<
2525 "mem", <<
2526 "xo", <<
2527 "gpll0_ <<
2528 "snoc_a <<
2529 "mnoc_a <<
2530 "qdss"; <<
2531 <<
2532 resets = <&gcc GCC_MS <<
2533 reset-names = "mss_re <<
2534 <<
2535 power-domains = <&rpm <<
2536 <&rpm <<
2537 power-domain-names = <<
2538 <<
2539 qcom,smem-states = <& <<
2540 qcom,smem-state-names <<
2541 <<
2542 qcom,halt-regs = <&tc <<
2543 <<
2544 status = "disabled"; <<
2545 <<
2546 mba { <<
2547 memory-region <<
2548 }; <<
2549 <<
2550 mpss { <<
2551 memory-region <<
2552 }; <<
2553 <<
2554 metadata { <<
2555 memory-region <<
2556 }; <<
2557 <<
2558 glink-edge { <<
2559 interrupts = <<
2560 label = "mode <<
2561 qcom,remote-p <<
2562 mboxes = <&ap <<
2563 }; <<
2564 <<
2565 smd-edge { <<
2566 interrupts = <<
2567 <<
2568 label = "mpss <<
2569 mboxes = <&ap <<
2570 qcom,smd-edge <<
2571 qcom,remote-p <<
2572 }; <<
2573 }; <<
2574 <<
2575 stm@3002000 { <<
2576 compatible = "arm,cor <<
2577 reg = <0x3002000 0x10 <<
2578 <0x8280000 0x18 <<
2579 reg-names = "stm-base <<
2580 <<
2581 clocks = <&rpmcc RPM_ <<
2582 clock-names = "apb_pc <<
2583 <<
2584 out-ports { <<
2585 port { <<
2586 stm_o <<
2587 <<
2588 <<
2589 }; <<
2590 }; <<
2591 }; <<
2592 }; <<
2593 <<
2594 tpiu@3020000 { <<
2595 compatible = "arm,cor <<
2596 reg = <0x3020000 0x10 <<
2597 <<
2598 clocks = <&rpmcc RPM_ <<
2599 clock-names = "apb_pc <<
2600 <<
2601 in-ports { <<
2602 port { <<
2603 tpiu_ <<
2604 <<
2605 <<
2606 }; <<
2607 }; <<
2608 }; <<
2609 }; <<
2610 <<
2611 funnel@3021000 { <<
2612 compatible = "arm,cor <<
2613 reg = <0x3021000 0x10 <<
2614 <<
2615 clocks = <&rpmcc RPM_ <<
2616 clock-names = "apb_pc <<
2617 <<
2618 in-ports { <<
2619 #address-cell <<
2620 #size-cells = <<
2621 <<
2622 port@7 { <<
2623 reg = <<
2624 funne <<
2625 <<
2626 <<
2627 }; <<
2628 }; <<
2629 }; <<
2630 <<
2631 out-ports { <<
2632 port { <<
2633 funne <<
2634 <<
2635 <<
2636 }; <<
2637 }; <<
2638 }; <<
2639 }; <<
2640 <<
2641 funnel@3022000 { <<
2642 compatible = "arm,cor <<
2643 reg = <0x3022000 0x10 <<
2644 <<
2645 clocks = <&rpmcc RPM_ <<
2646 clock-names = "apb_pc <<
2647 <<
2648 in-ports { <<
2649 #address-cell <<
2650 #size-cells = <<
2651 <<
2652 port@6 { <<
2653 reg = <<
2654 funne <<
2655 <<
2656 <<
2657 }; <<
2658 }; <<
2659 }; <<
2660 <<
2661 out-ports { <<
2662 port { <<
2663 funne <<
2664 <<
2665 <<
2666 }; <<
2667 }; <<
2668 }; <<
2669 }; <<
2670 <<
2671 funnel@3023000 { <<
2672 compatible = "arm,cor <<
2673 reg = <0x3023000 0x10 <<
2674 <<
2675 clocks = <&rpmcc RPM_ <<
2676 clock-names = "apb_pc <<
2677 <<
2678 in-ports { <<
2679 port { <<
2680 funne <<
2681 <<
2682 <<
2683 }; <<
2684 }; <<
2685 }; <<
2686 <<
2687 out-ports { <<
2688 port { <<
2689 funne <<
2690 <<
2691 <<
2692 }; <<
2693 }; <<
2694 }; <<
2695 }; <<
2696 <<
2697 funnel@3025000 { <<
2698 compatible = "arm,cor <<
2699 reg = <0x3025000 0x10 <<
2700 <<
2701 clocks = <&rpmcc RPM_ <<
2702 clock-names = "apb_pc <<
2703 <<
2704 in-ports { <<
2705 #address-cell <<
2706 #size-cells = <<
2707 <<
2708 port@0 { <<
2709 reg = <<
2710 merge <<
2711 <<
2712 <<
2713 }; <<
2714 }; <<
2715 <<
2716 port@1 { <<
2717 reg = <<
2718 merge <<
2719 <<
2720 <<
2721 }; <<
2722 }; <<
2723 <<
2724 port@2 { <<
2725 reg = <<
2726 merge <<
2727 <<
2728 <<
2729 }; <<
2730 }; <<
2731 }; <<
2732 <<
2733 out-ports { <<
2734 port { <<
2735 merge <<
2736 <<
2737 <<
2738 }; <<
2739 }; <<
2740 }; <<
2741 }; <<
2742 <<
2743 replicator@3026000 { <<
2744 compatible = "arm,cor <<
2745 reg = <0x3026000 0x10 <<
2746 <<
2747 clocks = <&rpmcc RPM_ <<
2748 clock-names = "apb_pc <<
2749 <<
2750 in-ports { <<
2751 port { <<
2752 repli <<
2753 <<
2754 <<
2755 }; <<
2756 }; <<
2757 }; <<
2758 <<
2759 out-ports { <<
2760 #address-cell <<
2761 #size-cells = <<
2762 <<
2763 port@0 { <<
2764 reg = <<
2765 repli <<
2766 <<
2767 <<
2768 }; <<
2769 }; <<
2770 <<
2771 port@1 { <<
2772 reg = <<
2773 repli <<
2774 <<
2775 <<
2776 }; <<
2777 }; <<
2778 }; <<
2779 }; <<
2780 <<
2781 etf@3027000 { <<
2782 compatible = "arm,cor <<
2783 reg = <0x3027000 0x10 <<
2784 <<
2785 clocks = <&rpmcc RPM_ <<
2786 clock-names = "apb_pc <<
2787 <<
2788 in-ports { <<
2789 port { <<
2790 etf_i <<
2791 <<
2792 <<
2793 }; <<
2794 }; <<
2795 }; <<
2796 <<
2797 out-ports { <<
2798 port { <<
2799 etf_o <<
2800 <<
2801 <<
2802 }; <<
2803 }; <<
2804 }; <<
2805 }; <<
2806 <<
2807 etr@3028000 { <<
2808 compatible = "arm,cor <<
2809 reg = <0x3028000 0x10 <<
2810 <<
2811 clocks = <&rpmcc RPM_ <<
2812 clock-names = "apb_pc <<
2813 arm,scatter-gather; <<
2814 <<
2815 in-ports { <<
2816 port { <<
2817 etr_i <<
2818 <<
2819 <<
2820 }; <<
2821 }; <<
2822 }; <<
2823 }; <<
2824 <<
2825 debug@3810000 { <<
2826 compatible = "arm,cor <<
2827 reg = <0x3810000 0x10 <<
2828 <<
2829 clocks = <&rpmcc RPM_ <<
2830 clock-names = "apb_pc <<
2831 <<
2832 cpu = <&CPU0>; <<
2833 }; <<
2834 <<
2835 etm@3840000 { <<
2836 compatible = "arm,cor <<
2837 reg = <0x3840000 0x10 <<
2838 <<
2839 clocks = <&rpmcc RPM_ <<
2840 clock-names = "apb_pc <<
2841 <<
2842 cpu = <&CPU0>; <<
2843 <<
2844 out-ports { <<
2845 port { <<
2846 etm0_ <<
2847 <<
2848 <<
2849 }; <<
2850 }; <<
2851 }; <<
2852 }; <<
2853 <<
2854 debug@3910000 { <<
2855 compatible = "arm,cor <<
2856 reg = <0x3910000 0x10 <<
2857 <<
2858 clocks = <&rpmcc RPM_ <<
2859 clock-names = "apb_pc <<
2860 <<
2861 cpu = <&CPU1>; <<
2862 }; <<
2863 <<
2864 etm@3940000 { <<
2865 compatible = "arm,cor <<
2866 reg = <0x3940000 0x10 <<
2867 <<
2868 clocks = <&rpmcc RPM_ <<
2869 clock-names = "apb_pc <<
2870 <<
2871 cpu = <&CPU1>; <<
2872 <<
2873 out-ports { <<
2874 port { <<
2875 etm1_ <<
2876 <<
2877 <<
2878 }; <<
2879 }; <<
2880 }; <<
2881 }; <<
2882 <<
2883 funnel@39b0000 { /* APSS Funn <<
2884 compatible = "arm,cor <<
2885 reg = <0x39b0000 0x10 <<
2886 <<
2887 clocks = <&rpmcc RPM_ <<
2888 clock-names = "apb_pc <<
2889 <<
2890 in-ports { <<
2891 #address-cell <<
2892 #size-cells = <<
2893 <<
2894 port@0 { <<
2895 reg = <<
2896 apss_ <<
2897 <<
2898 }; <<
2899 }; <<
2900 <<
2901 port@1 { <<
2902 reg = <<
2903 apss_ <<
2904 <<
2905 }; <<
2906 }; <<
2907 }; <<
2908 <<
2909 out-ports { <<
2910 port { <<
2911 apss_ <<
2912 <<
2913 <<
2914 }; <<
2915 }; <<
2916 }; <<
2917 }; <<
2918 <<
2919 debug@3a10000 { <<
2920 compatible = "arm,cor <<
2921 reg = <0x3a10000 0x10 <<
2922 <<
2923 clocks = <&rpmcc RPM_ <<
2924 clock-names = "apb_pc <<
2925 <<
2926 cpu = <&CPU2>; <<
2927 }; <<
2928 <<
2929 etm@3a40000 { <<
2930 compatible = "arm,cor <<
2931 reg = <0x3a40000 0x10 <<
2932 <<
2933 clocks = <&rpmcc RPM_ <<
2934 clock-names = "apb_pc <<
2935 <<
2936 cpu = <&CPU2>; <<
2937 <<
2938 out-ports { <<
2939 port { <<
2940 etm2_ <<
2941 <<
2942 <<
2943 }; <<
2944 }; <<
2945 }; <<
2946 }; <<
2947 <<
2948 debug@3b10000 { <<
2949 compatible = "arm,cor <<
2950 reg = <0x3b10000 0x10 <<
2951 <<
2952 clocks = <&rpmcc RPM_ <<
2953 clock-names = "apb_pc <<
2954 <<
2955 cpu = <&CPU3>; <<
2956 }; <<
2957 <<
2958 etm@3b40000 { <<
2959 compatible = "arm,cor <<
2960 reg = <0x3b40000 0x10 <<
2961 <<
2962 clocks = <&rpmcc RPM_ <<
2963 clock-names = "apb_pc <<
2964 <<
2965 cpu = <&CPU3>; <<
2966 <<
2967 out-ports { <<
2968 port { <<
2969 etm3_ <<
2970 <<
2971 <<
2972 }; <<
2973 }; <<
2974 }; <<
2975 }; <<
2976 <<
2977 funnel@3bb0000 { /* APSS Funn <<
2978 compatible = "arm,cor <<
2979 reg = <0x3bb0000 0x10 <<
2980 <<
2981 clocks = <&rpmcc RPM_ <<
2982 clock-names = "apb_pc <<
2983 <<
2984 in-ports { <<
2985 #address-cell <<
2986 #size-cells = <<
2987 <<
2988 port@0 { <<
2989 reg = <<
2990 apss_ <<
2991 <<
2992 }; <<
2993 }; <<
2994 <<
2995 port@1 { <<
2996 reg = <<
2997 apss_ <<
2998 <<
2999 }; <<
3000 }; <<
3001 }; <<
3002 <<
3003 out-ports { <<
3004 port { <<
3005 apss_ <<
3006 <<
3007 <<
3008 }; <<
3009 }; <<
3010 }; <<
3011 }; <<
3012 <<
3013 funnel@3bc0000 { <<
3014 compatible = "arm,cor <<
3015 reg = <0x3bc0000 0x10 <<
3016 <<
3017 clocks = <&rpmcc RPM_ <<
3018 clock-names = "apb_pc <<
3019 <<
3020 in-ports { <<
3021 #address-cell <<
3022 #size-cells = <<
3023 <<
3024 port@0 { <<
3025 reg = <<
3026 apss_ <<
3027 <<
3028 <<
3029 }; <<
3030 }; <<
3031 <<
3032 port@1 { <<
3033 reg = <<
3034 apss_ <<
3035 <<
3036 <<
3037 }; <<
3038 }; <<
3039 }; <<
3040 <<
3041 out-ports { <<
3042 port { <<
3043 apss_ <<
3044 <<
3045 <<
3046 }; <<
3047 }; <<
3048 }; <<
3049 }; 312 };
3050 313
3051 kryocc: clock-controller@6400 314 kryocc: clock-controller@6400000 {
3052 compatible = "qcom,ms !! 315 compatible = "qcom,apcc-msm8996";
3053 reg = <0x06400000 0x9 !! 316 reg = <0x6400000 0x90000>;
3054 <<
3055 clock-names = "xo", " <<
3056 clocks = <&rpmcc RPM_ <<
3057 <<
3058 #clock-cells = <1>; 317 #clock-cells = <1>;
3059 }; 318 };
3060 319
3061 usb3: usb@6af8800 { !! 320 blsp1_spi0: spi@07575000 {
3062 compatible = "qcom,ms <<
3063 reg = <0x06af8800 0x4 <<
3064 #address-cells = <1>; <<
3065 #size-cells = <1>; <<
3066 ranges; <<
3067 <<
3068 interrupts = <GIC_SPI <<
3069 <GIC_SPI <<
3070 interrupt-names = "hs <<
3071 <<
3072 clocks = <&gcc GCC_SY <<
3073 <&gcc GCC_US <<
3074 <&gcc GCC_AG <<
3075 <&gcc GCC_US <<
3076 <&gcc GCC_US <<
3077 clock-names = "cfg_no <<
3078 "core", <<
3079 "iface" <<
3080 "sleep" <<
3081 "mock_u <<
3082 <<
3083 assigned-clocks = <&g <<
3084 <&g <<
3085 assigned-clock-rates <<
3086 <<
3087 interconnects = <&a2n <<
3088 <&bim <<
3089 interconnect-names = <<
3090 <<
3091 power-domains = <&gcc <<
3092 status = "disabled"; <<
3093 <<
3094 usb3_dwc3: usb@6a0000 <<
3095 compatible = <<
3096 reg = <0x06a0 <<
3097 interrupts = <<
3098 phys = <&hsus <<
3099 phy-names = " <<
3100 snps,hird-thr <<
3101 snps,dis_u2_s <<
3102 snps,dis_enbl <<
3103 snps,is-utmi- <<
3104 snps,parkmode <<
3105 tx-fifo-resiz <<
3106 }; <<
3107 }; <<
3108 <<
3109 usb3phy: phy@7410000 { <<
3110 compatible = "qcom,ms <<
3111 reg = <0x07410000 0x1 <<
3112 <<
3113 clocks = <&gcc GCC_US <<
3114 <&gcc GCC_US <<
3115 <&gcc GCC_US <<
3116 <&gcc GCC_US <<
3117 clock-names = "aux", <<
3118 "ref", <<
3119 "cfg_ah <<
3120 "pipe"; <<
3121 clock-output-names = <<
3122 #clock-cells = <0>; <<
3123 #phy-cells = <0>; <<
3124 <<
3125 resets = <&gcc GCC_US <<
3126 <&gcc GCC_US <<
3127 reset-names = "phy", <<
3128 "phy_ph <<
3129 <<
3130 status = "disabled"; <<
3131 }; <<
3132 <<
3133 hsusb_phy1: phy@7411000 { <<
3134 compatible = "qcom,ms <<
3135 reg = <0x07411000 0x1 <<
3136 #phy-cells = <0>; <<
3137 <<
3138 clocks = <&gcc GCC_US <<
3139 <&gcc GCC_RX1 <<
3140 clock-names = "cfg_ah <<
3141 <<
3142 resets = <&gcc GCC_QU <<
3143 nvmem-cells = <&qusb2 <<
3144 status = "disabled"; <<
3145 }; <<
3146 <<
3147 hsusb_phy2: phy@7412000 { <<
3148 compatible = "qcom,ms <<
3149 reg = <0x07412000 0x1 <<
3150 #phy-cells = <0>; <<
3151 <<
3152 clocks = <&gcc GCC_US <<
3153 <&gcc GCC_RX2 <<
3154 clock-names = "cfg_ah <<
3155 <<
3156 resets = <&gcc GCC_QU <<
3157 nvmem-cells = <&qusb2 <<
3158 status = "disabled"; <<
3159 }; <<
3160 <<
3161 sdhc1: mmc@7464900 { <<
3162 compatible = "qcom,ms <<
3163 reg = <0x07464900 0x1 <<
3164 reg-names = "hc", "co <<
3165 <<
3166 interrupts = <GIC_SPI <<
3167 <GIC_ <<
3168 interrupt-names = "hc <<
3169 <<
3170 clock-names = "iface" <<
3171 clocks = <&gcc GCC_SD <<
3172 <&gcc GCC_SDC <<
3173 <&rpmcc RPM_S <<
3174 resets = <&gcc GCC_SD <<
3175 <<
3176 pinctrl-names = "defa <<
3177 pinctrl-0 = <&sdc1_st <<
3178 pinctrl-1 = <&sdc1_st <<
3179 <<
3180 bus-width = <8>; <<
3181 non-removable; <<
3182 status = "disabled"; <<
3183 }; <<
3184 <<
3185 sdhc2: mmc@74a4900 { <<
3186 compatible = "qcom,ms <<
3187 reg = <0x074a4900 0x3 <<
3188 reg-names = "hc", "co <<
3189 <<
3190 interrupts = <GIC_SPI <<
3191 <GIC_SP <<
3192 interrupt-names = "hc <<
3193 <<
3194 clock-names = "iface" <<
3195 clocks = <&gcc GCC_SD <<
3196 <&gcc GCC_SDC <<
3197 <&rpmcc RPM_S <<
3198 resets = <&gcc GCC_SD <<
3199 <<
3200 pinctrl-names = "defa <<
3201 pinctrl-0 = <&sdc2_st <<
3202 pinctrl-1 = <&sdc2_st <<
3203 <<
3204 bus-width = <4>; <<
3205 status = "disabled"; <<
3206 }; <<
3207 <<
3208 blsp1_dma: dma-controller@754 <<
3209 compatible = "qcom,ba <<
3210 reg = <0x07544000 0x2 <<
3211 interrupts = <GIC_SPI <<
3212 clocks = <&gcc GCC_BL <<
3213 clock-names = "bam_cl <<
3214 qcom,controlled-remot <<
3215 #dma-cells = <1>; <<
3216 qcom,ee = <0>; <<
3217 }; <<
3218 <<
3219 blsp1_uart2: serial@7570000 { <<
3220 compatible = "qcom,ms <<
3221 reg = <0x07570000 0x1 <<
3222 interrupts = <GIC_SPI <<
3223 clocks = <&gcc GCC_BL <<
3224 <&gcc GCC_BL <<
3225 clock-names = "core", <<
3226 pinctrl-names = "defa <<
3227 pinctrl-0 = <&blsp1_u <<
3228 pinctrl-1 = <&blsp1_u <<
3229 dmas = <&blsp1_dma 2> <<
3230 dma-names = "tx", "rx <<
3231 status = "disabled"; <<
3232 }; <<
3233 <<
3234 blsp1_spi1: spi@7575000 { <<
3235 compatible = "qcom,sp 321 compatible = "qcom,spi-qup-v2.2.1";
3236 reg = <0x07575000 0x6 322 reg = <0x07575000 0x600>;
3237 interrupts = <GIC_SPI 323 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
3238 clocks = <&gcc GCC_BL 324 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
3239 <&gcc GCC_BL 325 <&gcc GCC_BLSP1_AHB_CLK>;
3240 clock-names = "core", 326 clock-names = "core", "iface";
3241 pinctrl-names = "defa 327 pinctrl-names = "default", "sleep";
3242 pinctrl-0 = <&blsp1_s !! 328 pinctrl-0 = <&blsp1_spi0_default>;
3243 pinctrl-1 = <&blsp1_s !! 329 pinctrl-1 = <&blsp1_spi0_sleep>;
3244 dmas = <&blsp1_dma 12 <<
3245 dma-names = "tx", "rx <<
3246 #address-cells = <1>; <<
3247 #size-cells = <0>; <<
3248 status = "disabled"; <<
3249 }; <<
3250 <<
3251 blsp1_i2c3: i2c@7577000 { <<
3252 compatible = "qcom,i2 <<
3253 reg = <0x07577000 0x1 <<
3254 interrupts = <GIC_SPI <<
3255 clocks = <&gcc GCC_BL <<
3256 <&gcc GCC_BL <<
3257 clock-names = "core", <<
3258 pinctrl-names = "defa <<
3259 pinctrl-0 = <&blsp1_i <<
3260 pinctrl-1 = <&blsp1_i <<
3261 dmas = <&blsp1_dma 16 <<
3262 dma-names = "tx", "rx <<
3263 #address-cells = <1>; 330 #address-cells = <1>;
3264 #size-cells = <0>; 331 #size-cells = <0>;
3265 status = "disabled"; 332 status = "disabled";
3266 }; 333 };
3267 334
3268 blsp1_i2c6: i2c@757a000 { !! 335 blsp2_i2c0: i2c@075b5000 {
3269 compatible = "qcom,i2 336 compatible = "qcom,i2c-qup-v2.2.1";
3270 reg = <0x757a000 0x10 !! 337 reg = <0x075b5000 0x1000>;
3271 interrupts = <GIC_SPI !! 338 interrupts = <GIC_SPI 101 0>;
3272 clocks = <&gcc GCC_BL !! 339 clocks = <&gcc GCC_BLSP2_AHB_CLK>,
3273 <&gcc GCC_BL !! 340 <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>;
3274 clock-names = "core", !! 341 clock-names = "iface", "core";
3275 pinctrl-names = "defa 342 pinctrl-names = "default", "sleep";
3276 pinctrl-0 = <&blsp1_i !! 343 pinctrl-0 = <&blsp2_i2c0_default>;
3277 pinctrl-1 = <&blsp1_i !! 344 pinctrl-1 = <&blsp2_i2c0_sleep>;
3278 dmas = <&blsp1_dma 22 <<
3279 dma-names = "tx", "rx <<
3280 #address-cells = <1>; 345 #address-cells = <1>;
3281 #size-cells = <0>; 346 #size-cells = <0>;
3282 status = "disabled"; 347 status = "disabled";
3283 }; 348 };
3284 349
3285 blsp2_dma: dma-controller@758 !! 350 tsens0: thermal-sensor@4a8000 {
3286 compatible = "qcom,ba !! 351 compatible = "qcom,msm8996-tsens";
3287 reg = <0x07584000 0x2 !! 352 reg = <0x4a8000 0x2000>;
3288 interrupts = <GIC_SPI !! 353 #thermal-sensor-cells = <1>;
3289 clocks = <&gcc GCC_BL <<
3290 clock-names = "bam_cl <<
3291 qcom,controlled-remot <<
3292 #dma-cells = <1>; <<
3293 qcom,ee = <0>; <<
3294 }; 354 };
3295 355
3296 blsp2_uart2: serial@75b0000 { !! 356 blsp2_uart1: serial@75b0000 {
3297 compatible = "qcom,ms 357 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
3298 reg = <0x075b0000 0x1 !! 358 reg = <0x75b0000 0x1000>;
3299 interrupts = <GIC_SPI 359 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
3300 clocks = <&gcc GCC_BL 360 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
3301 <&gcc GCC_BL 361 <&gcc GCC_BLSP2_AHB_CLK>;
3302 clock-names = "core", 362 clock-names = "core", "iface";
3303 status = "disabled"; 363 status = "disabled";
3304 }; 364 };
3305 365
3306 blsp2_uart3: serial@75b1000 { !! 366 blsp2_i2c1: i2c@075b6000 {
3307 compatible = "qcom,ms <<
3308 reg = <0x075b1000 0x1 <<
3309 interrupts = <GIC_SPI <<
3310 clocks = <&gcc GCC_BL <<
3311 <&gcc GCC_BL <<
3312 clock-names = "core", <<
3313 status = "disabled"; <<
3314 }; <<
3315 <<
3316 blsp2_i2c1: i2c@75b5000 { <<
3317 compatible = "qcom,i2 367 compatible = "qcom,i2c-qup-v2.2.1";
3318 reg = <0x075b5000 0x1 !! 368 reg = <0x075b6000 0x1000>;
3319 interrupts = <GIC_SPI !! 369 interrupts = <GIC_SPI 102 0>;
3320 clocks = <&gcc GCC_BL !! 370 clocks = <&gcc GCC_BLSP2_AHB_CLK>,
3321 <&gcc GCC_BL !! 371 <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>;
3322 clock-names = "core", !! 372 clock-names = "iface", "core";
3323 pinctrl-names = "defa 373 pinctrl-names = "default", "sleep";
3324 pinctrl-0 = <&blsp2_i 374 pinctrl-0 = <&blsp2_i2c1_default>;
3325 pinctrl-1 = <&blsp2_i 375 pinctrl-1 = <&blsp2_i2c1_sleep>;
3326 dmas = <&blsp2_dma 12 <<
3327 dma-names = "tx", "rx <<
3328 #address-cells = <1>; <<
3329 #size-cells = <0>; <<
3330 status = "disabled"; <<
3331 }; <<
3332 <<
3333 blsp2_i2c2: i2c@75b6000 { <<
3334 compatible = "qcom,i2 <<
3335 reg = <0x075b6000 0x1 <<
3336 interrupts = <GIC_SPI <<
3337 clocks = <&gcc GCC_BL <<
3338 <&gcc GCC_BL <<
3339 clock-names = "core", <<
3340 pinctrl-names = "defa <<
3341 pinctrl-0 = <&blsp2_i <<
3342 pinctrl-1 = <&blsp2_i <<
3343 dmas = <&blsp2_dma 14 <<
3344 dma-names = "tx", "rx <<
3345 #address-cells = <1>; <<
3346 #size-cells = <0>; <<
3347 status = "disabled"; <<
3348 }; <<
3349 <<
3350 blsp2_i2c3: i2c@75b7000 { <<
3351 compatible = "qcom,i2 <<
3352 reg = <0x075b7000 0x1 <<
3353 interrupts = <GIC_SPI <<
3354 clocks = <&gcc GCC_BL <<
3355 <&gcc GCC_BL <<
3356 clock-names = "core", <<
3357 clock-frequency = <40 <<
3358 pinctrl-names = "defa <<
3359 pinctrl-0 = <&blsp2_i <<
3360 pinctrl-1 = <&blsp2_i <<
3361 dmas = <&blsp2_dma 16 <<
3362 dma-names = "tx", "rx <<
3363 #address-cells = <1>; 376 #address-cells = <1>;
3364 #size-cells = <0>; 377 #size-cells = <0>;
3365 status = "disabled"; 378 status = "disabled";
3366 }; 379 };
3367 380
3368 blsp2_i2c5: i2c@75b9000 { !! 381 blsp2_uart2: serial@75b1000 {
3369 compatible = "qcom,i2 !! 382 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
3370 reg = <0x75b9000 0x10 !! 383 reg = <0x075b1000 0x1000>;
3371 interrupts = <GIC_SPI !! 384 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
3372 clocks = <&gcc GCC_BL !! 385 clocks = <&gcc GCC_BLSP2_UART3_APPS_CLK>,
3373 <&gcc GCC_BL 386 <&gcc GCC_BLSP2_AHB_CLK>;
3374 clock-names = "core", 387 clock-names = "core", "iface";
3375 pinctrl-names = "defa <<
3376 pinctrl-0 = <&blsp2_i <<
3377 dmas = <&blsp2_dma 20 <<
3378 dma-names = "tx", "rx <<
3379 #address-cells = <1>; <<
3380 #size-cells = <0>; <<
3381 status = "disabled"; 388 status = "disabled";
3382 }; 389 };
3383 390
3384 blsp2_i2c6: i2c@75ba000 { !! 391 blsp1_i2c2: i2c@07577000 {
3385 compatible = "qcom,i2 392 compatible = "qcom,i2c-qup-v2.2.1";
3386 reg = <0x75ba000 0x10 !! 393 reg = <0x07577000 0x1000>;
3387 interrupts = <GIC_SPI !! 394 interrupts = <GIC_SPI 97 0>;
3388 clocks = <&gcc GCC_BL !! 395 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
3389 <&gcc GCC_BL !! 396 <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
3390 clock-names = "core", !! 397 clock-names = "iface", "core";
3391 pinctrl-names = "defa 398 pinctrl-names = "default", "sleep";
3392 pinctrl-0 = <&blsp2_i !! 399 pinctrl-0 = <&blsp1_i2c2_default>;
3393 pinctrl-1 = <&blsp2_i !! 400 pinctrl-1 = <&blsp1_i2c2_sleep>;
3394 dmas = <&blsp2_dma 22 <<
3395 dma-names = "tx", "rx <<
3396 #address-cells = <1>; 401 #address-cells = <1>;
3397 #size-cells = <0>; 402 #size-cells = <0>;
3398 status = "disabled"; 403 status = "disabled";
3399 }; 404 };
3400 405
3401 blsp2_spi6: spi@75ba000 { !! 406 blsp2_spi5: spi@075ba000{
3402 compatible = "qcom,sp 407 compatible = "qcom,spi-qup-v2.2.1";
3403 reg = <0x075ba000 0x6 408 reg = <0x075ba000 0x600>;
3404 interrupts = <GIC_SPI !! 409 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
3405 clocks = <&gcc GCC_BL !! 410 clocks = <&gcc GCC_BLSP2_QUP5_SPI_APPS_CLK>,
3406 <&gcc GCC_BL 411 <&gcc GCC_BLSP2_AHB_CLK>;
3407 clock-names = "core", 412 clock-names = "core", "iface";
3408 pinctrl-names = "defa 413 pinctrl-names = "default", "sleep";
3409 pinctrl-0 = <&blsp2_s !! 414 pinctrl-0 = <&blsp2_spi5_default>;
3410 pinctrl-1 = <&blsp2_s !! 415 pinctrl-1 = <&blsp2_spi5_sleep>;
3411 dmas = <&blsp2_dma 22 <<
3412 dma-names = "tx", "rx <<
3413 #address-cells = <1>; 416 #address-cells = <1>;
3414 #size-cells = <0>; 417 #size-cells = <0>;
3415 status = "disabled"; 418 status = "disabled";
3416 }; 419 };
3417 420
3418 usb2: usb@76f8800 { !! 421 sdhc2: sdhci@74a4900 {
3419 compatible = "qcom,ms !! 422 status = "disabled";
3420 reg = <0x076f8800 0x4 !! 423 compatible = "qcom,sdhci-msm-v4";
3421 #address-cells = <1>; !! 424 reg = <0x74a4900 0x314>, <0x74a4000 0x800>;
3422 #size-cells = <1>; !! 425 reg-names = "hc_mem", "core_mem";
3423 ranges; <<
3424 426
3425 interrupts = <GIC_SPI !! 427 interrupts = <0 125 0>, <0 221 0>;
3426 <GIC_SPI !! 428 interrupt-names = "hc_irq", "pwr_irq";
3427 <GIC_SPI <<
3428 interrupt-names = "pw <<
3429 "qu <<
3430 "hs <<
3431 <<
3432 clocks = <&gcc GCC_PE <<
3433 <&gcc GCC_USB <<
3434 <&gcc GCC_USB <<
3435 <&gcc GCC_USB <<
3436 <&gcc GCC_USB <<
3437 clock-names = "cfg_no <<
3438 "core", <<
3439 "iface" <<
3440 "sleep" <<
3441 "mock_u <<
3442 <<
3443 assigned-clocks = <&g <<
3444 <&g <<
3445 assigned-clock-rates <<
3446 <<
3447 power-domains = <&gcc <<
3448 qcom,select-utmi-as-p <<
3449 status = "disabled"; <<
3450 429
3451 usb2_dwc3: usb@760000 !! 430 clock-names = "iface", "core", "xo";
3452 compatible = !! 431 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
3453 reg = <0x0760 !! 432 <&gcc GCC_SDCC2_APPS_CLK>,
3454 interrupts = !! 433 <&xo_board>;
3455 phys = <&hsus !! 434 bus-width = <4>;
3456 phy-names = " !! 435 };
3457 maximum-speed <<
3458 snps,dis_u2_s <<
3459 snps,dis_enbl <<
3460 }; <<
3461 }; <<
3462 <<
3463 slimbam: dma-controller@91840 <<
3464 compatible = "qcom,ba <<
3465 qcom,controlled-remot <<
3466 reg = <0x09184000 0x3 <<
3467 num-channels = <31>; <<
3468 interrupts = <GIC_SPI <<
3469 #dma-cells = <1>; <<
3470 qcom,ee = <1>; <<
3471 qcom,num-ees = <2>; <<
3472 }; <<
3473 <<
3474 slim_msm: slim-ngd@91c0000 { <<
3475 compatible = "qcom,sl <<
3476 reg = <0x091c0000 0x2 <<
3477 interrupts = <GIC_SPI <<
3478 dmas = <&slimbam 3>, <<
3479 dma-names = "rx", "tx <<
3480 #address-cells = <1>; <<
3481 #size-cells = <0>; <<
3482 <<
3483 status = "disabled"; <<
3484 }; <<
3485 <<
3486 adsp_pil: remoteproc@9300000 <<
3487 compatible = "qcom,ms <<
3488 reg = <0x09300000 0x8 <<
3489 <<
3490 interrupts-extended = <<
3491 <<
3492 <<
3493 <<
3494 <<
3495 interrupt-names = "wd <<
3496 "ha <<
3497 <<
3498 clocks = <&rpmcc RPM_ <<
3499 clock-names = "xo"; <<
3500 <<
3501 memory-region = <&ads <<
3502 <<
3503 qcom,smem-states = <& <<
3504 qcom,smem-state-names <<
3505 <<
3506 power-domains = <&rpm <<
3507 power-domain-names = <<
3508 <<
3509 status = "disabled"; <<
3510 <<
3511 glink-edge { <<
3512 interrupts = <<
3513 label = "lpas <<
3514 qcom,remote-p <<
3515 mboxes = <&ap <<
3516 }; <<
3517 <<
3518 <<
3519 smd-edge { <<
3520 interrupts = <<
3521 <<
3522 label = "lpas <<
3523 mboxes = <&ap <<
3524 qcom,smd-edge <<
3525 qcom,remote-p <<
3526 <<
3527 apr { <<
3528 power <<
3529 compa <<
3530 qcom, <<
3531 qcom, <<
3532 #addr <<
3533 #size <<
3534 <<
3535 servi <<
3536 <<
3537 <<
3538 }; <<
3539 <<
3540 q6afe <<
3541 <<
3542 <<
3543 <<
3544 <<
3545 <<
3546 <<
3547 <<
3548 <<
3549 <<
3550 <<
3551 <<
3552 }; <<
3553 <<
3554 q6asm <<
3555 <<
3556 <<
3557 <<
3558 <<
3559 <<
3560 <<
3561 <<
3562 <<
3563 <<
3564 }; <<
3565 <<
3566 q6adm <<
3567 <<
3568 <<
3569 <<
3570 <<
3571 <<
3572 <<
3573 }; <<
3574 }; <<
3575 <<
3576 fastrpc { <<
3577 compa <<
3578 qcom, <<
3579 label <<
3580 qcom, <<
3581 #addr <<
3582 #size <<
3583 <<
3584 cb@5 <<
3585 <<
3586 <<
3587 <<
3588 }; <<
3589 <<
3590 cb@6 <<
3591 <<
3592 <<
3593 <<
3594 }; <<
3595 <<
3596 cb@7 <<
3597 <<
3598 <<
3599 <<
3600 }; <<
3601 <<
3602 cb@8 <<
3603 <<
3604 <<
3605 <<
3606 }; <<
3607 <<
3608 cb@9 <<
3609 <<
3610 <<
3611 <<
3612 }; <<
3613 <<
3614 cb@10 <<
3615 <<
3616 <<
3617 <<
3618 }; <<
3619 <<
3620 cb@11 <<
3621 <<
3622 <<
3623 <<
3624 }; <<
3625 <<
3626 cb@12 <<
3627 <<
3628 <<
3629 <<
3630 }; <<
3631 }; <<
3632 }; <<
3633 }; <<
3634 <<
3635 apcs_glb: mailbox@9820000 { <<
3636 compatible = "qcom,ms <<
3637 reg = <0x09820000 0x1 <<
3638 436
3639 #mbox-cells = <1>; !! 437 msmgpio: pinctrl@1010000 {
3640 #clock-cells = <0>; !! 438 compatible = "qcom,msm8996-pinctrl";
>> 439 reg = <0x01010000 0x300000>;
>> 440 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
>> 441 gpio-controller;
>> 442 #gpio-cells = <2>;
>> 443 interrupt-controller;
>> 444 #interrupt-cells = <2>;
3641 }; 445 };
3642 446
3643 timer@9840000 { !! 447 timer@09840000 {
3644 #address-cells = <1>; 448 #address-cells = <1>;
3645 #size-cells = <1>; 449 #size-cells = <1>;
3646 ranges; 450 ranges;
3647 compatible = "arm,arm 451 compatible = "arm,armv7-timer-mem";
3648 reg = <0x09840000 0x1 452 reg = <0x09840000 0x1000>;
3649 clock-frequency = <19 453 clock-frequency = <19200000>;
3650 454
3651 frame@9850000 { 455 frame@9850000 {
3652 frame-number 456 frame-number = <0>;
3653 interrupts = 457 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
3654 458 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
3655 reg = <0x0985 459 reg = <0x09850000 0x1000>,
3656 <0x0986 460 <0x09860000 0x1000>;
3657 }; 461 };
3658 462
3659 frame@9870000 { 463 frame@9870000 {
3660 frame-number 464 frame-number = <1>;
3661 interrupts = 465 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
3662 reg = <0x0987 466 reg = <0x09870000 0x1000>;
3663 status = "dis 467 status = "disabled";
3664 }; 468 };
3665 469
3666 frame@9880000 { 470 frame@9880000 {
3667 frame-number 471 frame-number = <2>;
3668 interrupts = 472 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
3669 reg = <0x0988 473 reg = <0x09880000 0x1000>;
3670 status = "dis 474 status = "disabled";
3671 }; 475 };
3672 476
3673 frame@9890000 { 477 frame@9890000 {
3674 frame-number 478 frame-number = <3>;
3675 interrupts = 479 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
3676 reg = <0x0989 480 reg = <0x09890000 0x1000>;
3677 status = "dis 481 status = "disabled";
3678 }; 482 };
3679 483
3680 frame@98a0000 { 484 frame@98a0000 {
3681 frame-number 485 frame-number = <4>;
3682 interrupts = 486 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
3683 reg = <0x098a 487 reg = <0x098a0000 0x1000>;
3684 status = "dis 488 status = "disabled";
3685 }; 489 };
3686 490
3687 frame@98b0000 { 491 frame@98b0000 {
3688 frame-number 492 frame-number = <5>;
3689 interrupts = 493 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
3690 reg = <0x098b 494 reg = <0x098b0000 0x1000>;
3691 status = "dis 495 status = "disabled";
3692 }; 496 };
3693 497
3694 frame@98c0000 { 498 frame@98c0000 {
3695 frame-number 499 frame-number = <6>;
3696 interrupts = 500 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
3697 reg = <0x098c 501 reg = <0x098c0000 0x1000>;
3698 status = "dis 502 status = "disabled";
3699 }; 503 };
3700 }; 504 };
3701 505
3702 saw3: syscon@9a10000 { !! 506 spmi_bus: qcom,spmi@400f000 {
3703 compatible = "syscon" !! 507 compatible = "qcom,spmi-pmic-arb";
3704 reg = <0x09a10000 0x1 !! 508 reg = <0x400f000 0x1000>,
3705 }; !! 509 <0x4400000 0x800000>,
3706 !! 510 <0x4c00000 0x800000>,
3707 cbf: clock-controller@9a11000 !! 511 <0x5800000 0x200000>,
3708 compatible = "qcom,ms !! 512 <0x400a000 0x002100>;
3709 reg = <0x09a11000 0x1 !! 513 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
3710 clocks = <&rpmcc RPM_ !! 514 interrupt-names = "periph_irq";
3711 #clock-cells = <0>; !! 515 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
3712 #interconnect-cells = !! 516 qcom,ee = <0>;
3713 }; !! 517 qcom,channel = <0>;
3714 !! 518 #address-cells = <2>;
3715 intc: interrupt-controller@9b !! 519 #size-cells = <0>;
3716 compatible = "qcom,ms <<
3717 #interrupt-cells = <3 <<
3718 interrupt-controller; 520 interrupt-controller;
3719 #redistributor-region !! 521 #interrupt-cells = <4>;
3720 redistributor-stride <<
3721 reg = <0x09bc0000 0x1 <<
3722 <0x09c00000 0x1 <<
3723 interrupts = <GIC_PPI <<
3724 }; <<
3725 }; <<
3726 <<
3727 sound: sound { <<
3728 }; <<
3729 <<
3730 thermal-zones { <<
3731 cpu0-thermal { <<
3732 polling-delay-passive <<
3733 <<
3734 thermal-sensors = <&t <<
3735 <<
3736 trips { <<
3737 cpu0_alert0: <<
3738 tempe <<
3739 hyste <<
3740 type <<
3741 }; <<
3742 <<
3743 cpu0_crit: cp <<
3744 tempe <<
3745 hyste <<
3746 type <<
3747 }; <<
3748 }; <<
3749 }; <<
3750 <<
3751 cpu1-thermal { <<
3752 polling-delay-passive <<
3753 <<
3754 thermal-sensors = <&t <<
3755 <<
3756 trips { <<
3757 cpu1_alert0: <<
3758 tempe <<
3759 hyste <<
3760 type <<
3761 }; <<
3762 <<
3763 cpu1_crit: cp <<
3764 tempe <<
3765 hyste <<
3766 type <<
3767 }; <<
3768 }; <<
3769 }; <<
3770 <<
3771 cpu2-thermal { <<
3772 polling-delay-passive <<
3773 <<
3774 thermal-sensors = <&t <<
3775 <<
3776 trips { <<
3777 cpu2_alert0: <<
3778 tempe <<
3779 hyste <<
3780 type <<
3781 }; <<
3782 <<
3783 cpu2_crit: cp <<
3784 tempe <<
3785 hyste <<
3786 type <<
3787 }; <<
3788 }; <<
3789 }; <<
3790 <<
3791 cpu3-thermal { <<
3792 polling-delay-passive <<
3793 <<
3794 thermal-sensors = <&t <<
3795 <<
3796 trips { <<
3797 cpu3_alert0: <<
3798 tempe <<
3799 hyste <<
3800 type <<
3801 }; <<
3802 <<
3803 cpu3_crit: cp <<
3804 tempe <<
3805 hyste <<
3806 type <<
3807 }; <<
3808 }; <<
3809 }; <<
3810 <<
3811 gpu-top-thermal { <<
3812 polling-delay-passive <<
3813 <<
3814 thermal-sensors = <&t <<
3815 <<
3816 trips { <<
3817 gpu1_alert0: <<
3818 tempe <<
3819 hyste <<
3820 type <<
3821 }; <<
3822 }; <<
3823 <<
3824 cooling-maps { <<
3825 map0 { <<
3826 trip <<
3827 cooli <<
3828 }; <<
3829 }; <<
3830 }; 522 };
3831 523
3832 gpu-bottom-thermal { !! 524 mmcc: clock-controller@8c0000 {
3833 polling-delay-passive !! 525 compatible = "qcom,mmcc-msm8996";
3834 !! 526 #clock-cells = <1>;
3835 thermal-sensors = <&t !! 527 #reset-cells = <1>;
3836 !! 528 #power-domain-cells = <1>;
3837 trips { !! 529 reg = <0x8c0000 0x40000>;
3838 gpu2_alert0: !! 530 assigned-clocks = <&mmcc MMPLL9_PLL>,
3839 tempe !! 531 <&mmcc MMPLL1_PLL>,
3840 hyste !! 532 <&mmcc MMPLL3_PLL>,
3841 type !! 533 <&mmcc MMPLL4_PLL>,
3842 }; !! 534 <&mmcc MMPLL5_PLL>;
3843 }; !! 535 assigned-clock-rates = <624000000>,
3844 !! 536 <810000000>,
3845 cooling-maps { !! 537 <980000000>,
3846 map0 { !! 538 <960000000>,
3847 trip !! 539 <825000000>;
3848 cooli <<
3849 }; <<
3850 }; <<
3851 }; 540 };
>> 541 };
3852 542
3853 m4m-thermal { !! 543 adsp-pil {
3854 polling-delay-passive !! 544 compatible = "qcom,msm8996-adsp-pil";
3855 <<
3856 thermal-sensors = <&t <<
3857 545
3858 trips { !! 546 interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>,
3859 m4m_alert0: t !! 547 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3860 tempe !! 548 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
3861 hyste !! 549 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
3862 type !! 550 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
3863 }; !! 551 interrupt-names = "wdog", "fatal", "ready",
3864 }; !! 552 "handover", "stop-ack";
3865 }; <<
3866 553
3867 l3-or-venus-thermal { !! 554 clocks = <&xo_board>;
3868 polling-delay-passive !! 555 clock-names = "xo";
3869 556
3870 thermal-sensors = <&t !! 557 memory-region = <&adsp_region>;
3871 558
3872 trips { !! 559 qcom,smem-states = <&adsp_smp2p_out 0>;
3873 l3_or_venus_a !! 560 qcom,smem-state-names = "stop";
3874 tempe !! 561 };
3875 hyste <<
3876 type <<
3877 }; <<
3878 }; <<
3879 }; <<
3880 <<
3881 cluster0-l2-thermal { <<
3882 polling-delay-passive <<
3883 562
3884 thermal-sensors = <&t !! 563 adsp-smp2p {
>> 564 compatible = "qcom,smp2p";
>> 565 qcom,smem = <443>, <429>;
3885 566
3886 trips { !! 567 interrupts = <0 158 IRQ_TYPE_EDGE_RISING>;
3887 cluster0_l2_a <<
3888 tempe <<
3889 hyste <<
3890 type <<
3891 }; <<
3892 }; <<
3893 }; <<
3894 568
3895 cluster1-l2-thermal { !! 569 qcom,ipc = <&apcs 16 10>;
3896 polling-delay-passive <<
3897 570
3898 thermal-sensors = <&t !! 571 qcom,local-pid = <0>;
>> 572 qcom,remote-pid = <2>;
3899 573
3900 trips { !! 574 adsp_smp2p_out: master-kernel {
3901 cluster1_l2_a !! 575 qcom,entry-name = "master-kernel";
3902 tempe !! 576 #qcom,smem-state-cells = <1>;
3903 hyste <<
3904 type <<
3905 }; <<
3906 }; <<
3907 }; 577 };
3908 578
3909 camera-thermal { !! 579 adsp_smp2p_in: slave-kernel {
3910 polling-delay-passive !! 580 qcom,entry-name = "slave-kernel";
3911 <<
3912 thermal-sensors = <&t <<
3913 581
3914 trips { !! 582 interrupt-controller;
3915 camera_alert0 !! 583 #interrupt-cells = <2>;
3916 tempe <<
3917 hyste <<
3918 type <<
3919 }; <<
3920 }; <<
3921 }; 584 };
>> 585 };
3922 586
3923 q6-dsp-thermal { !! 587 smp2p-slpi {
3924 polling-delay-passive !! 588 compatible = "qcom,smp2p";
3925 !! 589 qcom,smem = <481>, <430>;
3926 thermal-sensors = <&t <<
3927 590
3928 trips { !! 591 interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>;
3929 q6_dsp_alert0 <<
3930 tempe <<
3931 hyste <<
3932 type <<
3933 }; <<
3934 }; <<
3935 }; <<
3936 592
3937 mem-thermal { !! 593 qcom,ipc = <&apcs 16 26>;
3938 polling-delay-passive <<
3939 594
3940 thermal-sensors = <&t !! 595 qcom,local-pid = <0>;
>> 596 qcom,remote-pid = <3>;
3941 597
3942 trips { !! 598 slpi_smp2p_in: slave-kernel {
3943 mem_alert0: t !! 599 qcom,entry-name = "slave-kernel";
3944 tempe !! 600 interrupt-controller;
3945 hyste !! 601 #interrupt-cells = <2>;
3946 type <<
3947 }; <<
3948 }; <<
3949 }; 602 };
3950 603
3951 modemtx-thermal { !! 604 slpi_smp2p_out: master-kernel {
3952 polling-delay-passive !! 605 qcom,entry-name = "master-kernel";
3953 !! 606 #qcom,smem-state-cells = <1>;
3954 thermal-sensors = <&t <<
3955 <<
3956 trips { <<
3957 modemtx_alert <<
3958 tempe <<
3959 hyste <<
3960 type <<
3961 }; <<
3962 }; <<
3963 }; 607 };
3964 }; 608 };
3965 609
3966 timer { <<
3967 compatible = "arm,armv8-timer <<
3968 interrupts = <GIC_PPI 13 IRQ_ <<
3969 <GIC_PPI 14 IRQ_ <<
3970 <GIC_PPI 11 IRQ_ <<
3971 <GIC_PPI 10 IRQ_ <<
3972 }; <<
3973 }; 610 };
>> 611 #include "msm8996-pins.dtsi"
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