1 // SPDX-License-Identifier: GPL-2.0-only 1 // SPDX-License-Identifier: GPL-2.0-only
2 /* !! 2 /* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
3 * Copyright (c) 2014-2015, The Linux Foundati <<
4 */ 3 */
5 4
6 #include <dt-bindings/interrupt-controller/arm 5 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,gcc-msm8996.h 6 #include <dt-bindings/clock/qcom,gcc-msm8996.h>
8 #include <dt-bindings/clock/qcom,mmcc-msm8996. 7 #include <dt-bindings/clock/qcom,mmcc-msm8996.h>
9 #include <dt-bindings/clock/qcom,rpmcc.h> 8 #include <dt-bindings/clock/qcom,rpmcc.h>
10 #include <dt-bindings/interconnect/qcom,msm899 <<
11 #include <dt-bindings/interconnect/qcom,msm899 <<
12 #include <dt-bindings/firmware/qcom,scm.h> <<
13 #include <dt-bindings/gpio/gpio.h> <<
14 #include <dt-bindings/power/qcom-rpmpd.h> 9 #include <dt-bindings/power/qcom-rpmpd.h>
15 #include <dt-bindings/soc/qcom,apr.h> 10 #include <dt-bindings/soc/qcom,apr.h>
16 #include <dt-bindings/thermal/thermal.h> 11 #include <dt-bindings/thermal/thermal.h>
17 12
18 / { 13 / {
19 interrupt-parent = <&intc>; 14 interrupt-parent = <&intc>;
20 15
21 #address-cells = <2>; 16 #address-cells = <2>;
22 #size-cells = <2>; 17 #size-cells = <2>;
23 18
24 chosen { }; 19 chosen { };
25 20
26 clocks { 21 clocks {
27 xo_board: xo-board { 22 xo_board: xo-board {
28 compatible = "fixed-cl 23 compatible = "fixed-clock";
29 #clock-cells = <0>; 24 #clock-cells = <0>;
30 clock-frequency = <192 25 clock-frequency = <19200000>;
31 clock-output-names = " 26 clock-output-names = "xo_board";
32 }; 27 };
33 28
34 sleep_clk: sleep-clk { 29 sleep_clk: sleep-clk {
35 compatible = "fixed-cl 30 compatible = "fixed-clock";
36 #clock-cells = <0>; 31 #clock-cells = <0>;
37 clock-frequency = <327 32 clock-frequency = <32764>;
38 clock-output-names = " 33 clock-output-names = "sleep_clk";
39 }; 34 };
40 }; 35 };
41 36
42 cpus { 37 cpus {
43 #address-cells = <2>; 38 #address-cells = <2>;
44 #size-cells = <0>; 39 #size-cells = <0>;
45 40
46 CPU0: cpu@0 { 41 CPU0: cpu@0 {
47 device_type = "cpu"; 42 device_type = "cpu";
48 compatible = "qcom,kry 43 compatible = "qcom,kryo";
49 reg = <0x0 0x0>; 44 reg = <0x0 0x0>;
50 enable-method = "psci" 45 enable-method = "psci";
51 cpu-idle-states = <&CP 46 cpu-idle-states = <&CPU_SLEEP_0>;
52 capacity-dmips-mhz = < 47 capacity-dmips-mhz = <1024>;
53 clocks = <&kryocc 0>; 48 clocks = <&kryocc 0>;
54 interconnects = <&cbf <<
55 operating-points-v2 = 49 operating-points-v2 = <&cluster0_opp>;
56 #cooling-cells = <2>; 50 #cooling-cells = <2>;
57 next-level-cache = <&L 51 next-level-cache = <&L2_0>;
58 L2_0: l2-cache { 52 L2_0: l2-cache {
59 compatible = " !! 53 compatible = "cache";
60 cache-level = !! 54 cache-level = <2>;
61 cache-unified; <<
62 }; 55 };
63 }; 56 };
64 57
65 CPU1: cpu@1 { 58 CPU1: cpu@1 {
66 device_type = "cpu"; 59 device_type = "cpu";
67 compatible = "qcom,kry 60 compatible = "qcom,kryo";
68 reg = <0x0 0x1>; 61 reg = <0x0 0x1>;
69 enable-method = "psci" 62 enable-method = "psci";
70 cpu-idle-states = <&CP 63 cpu-idle-states = <&CPU_SLEEP_0>;
71 capacity-dmips-mhz = < 64 capacity-dmips-mhz = <1024>;
72 clocks = <&kryocc 0>; 65 clocks = <&kryocc 0>;
73 interconnects = <&cbf <<
74 operating-points-v2 = 66 operating-points-v2 = <&cluster0_opp>;
75 #cooling-cells = <2>; 67 #cooling-cells = <2>;
76 next-level-cache = <&L 68 next-level-cache = <&L2_0>;
77 }; 69 };
78 70
79 CPU2: cpu@100 { 71 CPU2: cpu@100 {
80 device_type = "cpu"; 72 device_type = "cpu";
81 compatible = "qcom,kry 73 compatible = "qcom,kryo";
82 reg = <0x0 0x100>; 74 reg = <0x0 0x100>;
83 enable-method = "psci" 75 enable-method = "psci";
84 cpu-idle-states = <&CP 76 cpu-idle-states = <&CPU_SLEEP_0>;
85 capacity-dmips-mhz = < 77 capacity-dmips-mhz = <1024>;
86 clocks = <&kryocc 1>; 78 clocks = <&kryocc 1>;
87 interconnects = <&cbf <<
88 operating-points-v2 = 79 operating-points-v2 = <&cluster1_opp>;
89 #cooling-cells = <2>; 80 #cooling-cells = <2>;
90 next-level-cache = <&L 81 next-level-cache = <&L2_1>;
91 L2_1: l2-cache { 82 L2_1: l2-cache {
92 compatible = " !! 83 compatible = "cache";
93 cache-level = !! 84 cache-level = <2>;
94 cache-unified; <<
95 }; 85 };
96 }; 86 };
97 87
98 CPU3: cpu@101 { 88 CPU3: cpu@101 {
99 device_type = "cpu"; 89 device_type = "cpu";
100 compatible = "qcom,kry 90 compatible = "qcom,kryo";
101 reg = <0x0 0x101>; 91 reg = <0x0 0x101>;
102 enable-method = "psci" 92 enable-method = "psci";
103 cpu-idle-states = <&CP 93 cpu-idle-states = <&CPU_SLEEP_0>;
104 capacity-dmips-mhz = < 94 capacity-dmips-mhz = <1024>;
105 clocks = <&kryocc 1>; 95 clocks = <&kryocc 1>;
106 interconnects = <&cbf <<
107 operating-points-v2 = 96 operating-points-v2 = <&cluster1_opp>;
108 #cooling-cells = <2>; 97 #cooling-cells = <2>;
109 next-level-cache = <&L 98 next-level-cache = <&L2_1>;
110 }; 99 };
111 100
112 cpu-map { 101 cpu-map {
113 cluster0 { 102 cluster0 {
114 core0 { 103 core0 {
115 cpu = 104 cpu = <&CPU0>;
116 }; 105 };
117 106
118 core1 { 107 core1 {
119 cpu = 108 cpu = <&CPU1>;
120 }; 109 };
121 }; 110 };
122 111
123 cluster1 { 112 cluster1 {
124 core0 { 113 core0 {
125 cpu = 114 cpu = <&CPU2>;
126 }; 115 };
127 116
128 core1 { 117 core1 {
129 cpu = 118 cpu = <&CPU3>;
130 }; 119 };
131 }; 120 };
132 }; 121 };
133 122
134 idle-states { 123 idle-states {
135 entry-method = "psci"; 124 entry-method = "psci";
136 125
137 CPU_SLEEP_0: cpu-sleep 126 CPU_SLEEP_0: cpu-sleep-0 {
138 compatible = " 127 compatible = "arm,idle-state";
139 idle-state-nam 128 idle-state-name = "standalone-power-collapse";
140 arm,psci-suspe 129 arm,psci-suspend-param = <0x00000004>;
141 entry-latency- 130 entry-latency-us = <130>;
142 exit-latency-u 131 exit-latency-us = <80>;
143 min-residency- 132 min-residency-us = <300>;
144 }; 133 };
145 }; 134 };
146 }; 135 };
147 136
148 cluster0_opp: opp-table-cluster0 { !! 137 cluster0_opp: opp_table0 {
149 compatible = "operating-points 138 compatible = "operating-points-v2-kryo-cpu";
150 nvmem-cells = <&speedbin_efuse 139 nvmem-cells = <&speedbin_efuse>;
151 opp-shared; 140 opp-shared;
152 141
153 /* Nominal fmax for now */ 142 /* Nominal fmax for now */
154 opp-307200000 { 143 opp-307200000 {
155 opp-hz = /bits/ 64 <30 144 opp-hz = /bits/ 64 <307200000>;
156 opp-supported-hw = <0x !! 145 opp-supported-hw = <0x77>;
157 clock-latency-ns = <20 146 clock-latency-ns = <200000>;
158 opp-peak-kBps = <30720 <<
159 }; 147 };
160 opp-422400000 { 148 opp-422400000 {
161 opp-hz = /bits/ 64 <42 149 opp-hz = /bits/ 64 <422400000>;
162 opp-supported-hw = <0x !! 150 opp-supported-hw = <0x77>;
163 clock-latency-ns = <20 151 clock-latency-ns = <200000>;
164 opp-peak-kBps = <30720 <<
165 }; 152 };
166 opp-480000000 { 153 opp-480000000 {
167 opp-hz = /bits/ 64 <48 154 opp-hz = /bits/ 64 <480000000>;
168 opp-supported-hw = <0x !! 155 opp-supported-hw = <0x77>;
169 clock-latency-ns = <20 156 clock-latency-ns = <200000>;
170 opp-peak-kBps = <30720 <<
171 }; 157 };
172 opp-556800000 { 158 opp-556800000 {
173 opp-hz = /bits/ 64 <55 159 opp-hz = /bits/ 64 <556800000>;
174 opp-supported-hw = <0x !! 160 opp-supported-hw = <0x77>;
175 clock-latency-ns = <20 161 clock-latency-ns = <200000>;
176 opp-peak-kBps = <30720 <<
177 }; 162 };
178 opp-652800000 { 163 opp-652800000 {
179 opp-hz = /bits/ 64 <65 164 opp-hz = /bits/ 64 <652800000>;
180 opp-supported-hw = <0x !! 165 opp-supported-hw = <0x77>;
181 clock-latency-ns = <20 166 clock-latency-ns = <200000>;
182 opp-peak-kBps = <38400 <<
183 }; 167 };
184 opp-729600000 { 168 opp-729600000 {
185 opp-hz = /bits/ 64 <72 169 opp-hz = /bits/ 64 <729600000>;
186 opp-supported-hw = <0x !! 170 opp-supported-hw = <0x77>;
187 clock-latency-ns = <20 171 clock-latency-ns = <200000>;
188 opp-peak-kBps = <46080 <<
189 }; 172 };
190 opp-844800000 { 173 opp-844800000 {
191 opp-hz = /bits/ 64 <84 174 opp-hz = /bits/ 64 <844800000>;
192 opp-supported-hw = <0x !! 175 opp-supported-hw = <0x77>;
193 clock-latency-ns = <20 176 clock-latency-ns = <200000>;
194 opp-peak-kBps = <53760 <<
195 }; 177 };
196 opp-960000000 { 178 opp-960000000 {
197 opp-hz = /bits/ 64 <96 179 opp-hz = /bits/ 64 <960000000>;
198 opp-supported-hw = <0x !! 180 opp-supported-hw = <0x77>;
199 clock-latency-ns = <20 181 clock-latency-ns = <200000>;
200 opp-peak-kBps = <67200 <<
201 }; 182 };
202 opp-1036800000 { 183 opp-1036800000 {
203 opp-hz = /bits/ 64 <10 184 opp-hz = /bits/ 64 <1036800000>;
204 opp-supported-hw = <0x !! 185 opp-supported-hw = <0x77>;
205 clock-latency-ns = <20 186 clock-latency-ns = <200000>;
206 opp-peak-kBps = <67200 <<
207 }; 187 };
208 opp-1113600000 { 188 opp-1113600000 {
209 opp-hz = /bits/ 64 <11 189 opp-hz = /bits/ 64 <1113600000>;
210 opp-supported-hw = <0x !! 190 opp-supported-hw = <0x77>;
211 clock-latency-ns = <20 191 clock-latency-ns = <200000>;
212 opp-peak-kBps = <82560 <<
213 }; 192 };
214 opp-1190400000 { 193 opp-1190400000 {
215 opp-hz = /bits/ 64 <11 194 opp-hz = /bits/ 64 <1190400000>;
216 opp-supported-hw = <0x !! 195 opp-supported-hw = <0x77>;
217 clock-latency-ns = <20 196 clock-latency-ns = <200000>;
218 opp-peak-kBps = <82560 <<
219 }; 197 };
220 opp-1228800000 { 198 opp-1228800000 {
221 opp-hz = /bits/ 64 <12 199 opp-hz = /bits/ 64 <1228800000>;
222 opp-supported-hw = <0x !! 200 opp-supported-hw = <0x77>;
223 clock-latency-ns = <20 201 clock-latency-ns = <200000>;
224 opp-peak-kBps = <90240 <<
225 }; 202 };
226 opp-1324800000 { 203 opp-1324800000 {
227 opp-hz = /bits/ 64 <13 204 opp-hz = /bits/ 64 <1324800000>;
228 opp-supported-hw = <0x !! 205 opp-supported-hw = <0x77>;
229 clock-latency-ns = <20 206 clock-latency-ns = <200000>;
230 opp-peak-kBps = <10560 <<
231 }; <<
232 opp-1363200000 { <<
233 opp-hz = /bits/ 64 <13 <<
234 opp-supported-hw = <0x <<
235 clock-latency-ns = <20 <<
236 opp-peak-kBps = <11328 <<
237 }; 207 };
238 opp-1401600000 { 208 opp-1401600000 {
239 opp-hz = /bits/ 64 <14 209 opp-hz = /bits/ 64 <1401600000>;
240 opp-supported-hw = <0x !! 210 opp-supported-hw = <0x77>;
241 clock-latency-ns = <20 211 clock-latency-ns = <200000>;
242 opp-peak-kBps = <11328 <<
243 }; 212 };
244 opp-1478400000 { 213 opp-1478400000 {
245 opp-hz = /bits/ 64 <14 214 opp-hz = /bits/ 64 <1478400000>;
246 opp-supported-hw = <0x !! 215 opp-supported-hw = <0x77>;
247 clock-latency-ns = <20 <<
248 opp-peak-kBps = <11904 <<
249 }; <<
250 opp-1497600000 { <<
251 opp-hz = /bits/ 64 <14 <<
252 opp-supported-hw = <0x <<
253 clock-latency-ns = <20 216 clock-latency-ns = <200000>;
254 opp-peak-kBps = <13056 <<
255 }; 217 };
256 opp-1593600000 { 218 opp-1593600000 {
257 opp-hz = /bits/ 64 <15 219 opp-hz = /bits/ 64 <1593600000>;
258 opp-supported-hw = <0x !! 220 opp-supported-hw = <0x77>;
259 clock-latency-ns = <20 221 clock-latency-ns = <200000>;
260 opp-peak-kBps = <13824 <<
261 }; 222 };
262 }; 223 };
263 224
264 cluster1_opp: opp-table-cluster1 { !! 225 cluster1_opp: opp_table1 {
265 compatible = "operating-points 226 compatible = "operating-points-v2-kryo-cpu";
266 nvmem-cells = <&speedbin_efuse 227 nvmem-cells = <&speedbin_efuse>;
267 opp-shared; 228 opp-shared;
268 229
269 /* Nominal fmax for now */ 230 /* Nominal fmax for now */
270 opp-307200000 { 231 opp-307200000 {
271 opp-hz = /bits/ 64 <30 232 opp-hz = /bits/ 64 <307200000>;
272 opp-supported-hw = <0x !! 233 opp-supported-hw = <0x77>;
273 clock-latency-ns = <20 234 clock-latency-ns = <200000>;
274 opp-peak-kBps = <30720 <<
275 }; 235 };
276 opp-403200000 { 236 opp-403200000 {
277 opp-hz = /bits/ 64 <40 237 opp-hz = /bits/ 64 <403200000>;
278 opp-supported-hw = <0x !! 238 opp-supported-hw = <0x77>;
279 clock-latency-ns = <20 239 clock-latency-ns = <200000>;
280 opp-peak-kBps = <30720 <<
281 }; 240 };
282 opp-480000000 { 241 opp-480000000 {
283 opp-hz = /bits/ 64 <48 242 opp-hz = /bits/ 64 <480000000>;
284 opp-supported-hw = <0x !! 243 opp-supported-hw = <0x77>;
285 clock-latency-ns = <20 244 clock-latency-ns = <200000>;
286 opp-peak-kBps = <30720 <<
287 }; 245 };
288 opp-556800000 { 246 opp-556800000 {
289 opp-hz = /bits/ 64 <55 247 opp-hz = /bits/ 64 <556800000>;
290 opp-supported-hw = <0x !! 248 opp-supported-hw = <0x77>;
291 clock-latency-ns = <20 249 clock-latency-ns = <200000>;
292 opp-peak-kBps = <30720 <<
293 }; 250 };
294 opp-652800000 { 251 opp-652800000 {
295 opp-hz = /bits/ 64 <65 252 opp-hz = /bits/ 64 <652800000>;
296 opp-supported-hw = <0x !! 253 opp-supported-hw = <0x77>;
297 clock-latency-ns = <20 254 clock-latency-ns = <200000>;
298 opp-peak-kBps = <30720 <<
299 }; 255 };
300 opp-729600000 { 256 opp-729600000 {
301 opp-hz = /bits/ 64 <72 257 opp-hz = /bits/ 64 <729600000>;
302 opp-supported-hw = <0x !! 258 opp-supported-hw = <0x77>;
303 clock-latency-ns = <20 259 clock-latency-ns = <200000>;
304 opp-peak-kBps = <30720 <<
305 }; 260 };
306 opp-806400000 { 261 opp-806400000 {
307 opp-hz = /bits/ 64 <80 262 opp-hz = /bits/ 64 <806400000>;
308 opp-supported-hw = <0x !! 263 opp-supported-hw = <0x77>;
309 clock-latency-ns = <20 264 clock-latency-ns = <200000>;
310 opp-peak-kBps = <38400 <<
311 }; 265 };
312 opp-883200000 { 266 opp-883200000 {
313 opp-hz = /bits/ 64 <88 267 opp-hz = /bits/ 64 <883200000>;
314 opp-supported-hw = <0x !! 268 opp-supported-hw = <0x77>;
315 clock-latency-ns = <20 269 clock-latency-ns = <200000>;
316 opp-peak-kBps = <46080 <<
317 }; 270 };
318 opp-940800000 { 271 opp-940800000 {
319 opp-hz = /bits/ 64 <94 272 opp-hz = /bits/ 64 <940800000>;
320 opp-supported-hw = <0x !! 273 opp-supported-hw = <0x77>;
321 clock-latency-ns = <20 274 clock-latency-ns = <200000>;
322 opp-peak-kBps = <53760 <<
323 }; 275 };
324 opp-1036800000 { 276 opp-1036800000 {
325 opp-hz = /bits/ 64 <10 277 opp-hz = /bits/ 64 <1036800000>;
326 opp-supported-hw = <0x !! 278 opp-supported-hw = <0x77>;
327 clock-latency-ns = <20 279 clock-latency-ns = <200000>;
328 opp-peak-kBps = <59520 <<
329 }; 280 };
330 opp-1113600000 { 281 opp-1113600000 {
331 opp-hz = /bits/ 64 <11 282 opp-hz = /bits/ 64 <1113600000>;
332 opp-supported-hw = <0x !! 283 opp-supported-hw = <0x77>;
333 clock-latency-ns = <20 284 clock-latency-ns = <200000>;
334 opp-peak-kBps = <67200 <<
335 }; 285 };
336 opp-1190400000 { 286 opp-1190400000 {
337 opp-hz = /bits/ 64 <11 287 opp-hz = /bits/ 64 <1190400000>;
338 opp-supported-hw = <0x !! 288 opp-supported-hw = <0x77>;
339 clock-latency-ns = <20 289 clock-latency-ns = <200000>;
340 opp-peak-kBps = <67200 <<
341 }; 290 };
342 opp-1248000000 { 291 opp-1248000000 {
343 opp-hz = /bits/ 64 <12 292 opp-hz = /bits/ 64 <1248000000>;
344 opp-supported-hw = <0x !! 293 opp-supported-hw = <0x77>;
345 clock-latency-ns = <20 294 clock-latency-ns = <200000>;
346 opp-peak-kBps = <74880 <<
347 }; 295 };
348 opp-1324800000 { 296 opp-1324800000 {
349 opp-hz = /bits/ 64 <13 297 opp-hz = /bits/ 64 <1324800000>;
350 opp-supported-hw = <0x !! 298 opp-supported-hw = <0x77>;
351 clock-latency-ns = <20 299 clock-latency-ns = <200000>;
352 opp-peak-kBps = <82560 <<
353 }; 300 };
354 opp-1401600000 { 301 opp-1401600000 {
355 opp-hz = /bits/ 64 <14 302 opp-hz = /bits/ 64 <1401600000>;
356 opp-supported-hw = <0x !! 303 opp-supported-hw = <0x77>;
357 clock-latency-ns = <20 304 clock-latency-ns = <200000>;
358 opp-peak-kBps = <90240 <<
359 }; 305 };
360 opp-1478400000 { 306 opp-1478400000 {
361 opp-hz = /bits/ 64 <14 307 opp-hz = /bits/ 64 <1478400000>;
362 opp-supported-hw = <0x !! 308 opp-supported-hw = <0x77>;
363 clock-latency-ns = <20 309 clock-latency-ns = <200000>;
364 opp-peak-kBps = <97920 <<
365 }; 310 };
366 opp-1555200000 { 311 opp-1555200000 {
367 opp-hz = /bits/ 64 <15 312 opp-hz = /bits/ 64 <1555200000>;
368 opp-supported-hw = <0x !! 313 opp-supported-hw = <0x77>;
369 clock-latency-ns = <20 314 clock-latency-ns = <200000>;
370 opp-peak-kBps = <10560 <<
371 }; 315 };
372 opp-1632000000 { 316 opp-1632000000 {
373 opp-hz = /bits/ 64 <16 317 opp-hz = /bits/ 64 <1632000000>;
374 opp-supported-hw = <0x !! 318 opp-supported-hw = <0x77>;
375 clock-latency-ns = <20 319 clock-latency-ns = <200000>;
376 opp-peak-kBps = <11904 <<
377 }; 320 };
378 opp-1708800000 { 321 opp-1708800000 {
379 opp-hz = /bits/ 64 <17 322 opp-hz = /bits/ 64 <1708800000>;
380 opp-supported-hw = <0x !! 323 opp-supported-hw = <0x77>;
381 clock-latency-ns = <20 324 clock-latency-ns = <200000>;
382 opp-peak-kBps = <12288 <<
383 }; 325 };
384 opp-1785600000 { 326 opp-1785600000 {
385 opp-hz = /bits/ 64 <17 327 opp-hz = /bits/ 64 <1785600000>;
386 opp-supported-hw = <0x !! 328 opp-supported-hw = <0x77>;
387 clock-latency-ns = <20 329 clock-latency-ns = <200000>;
388 opp-peak-kBps = <13056 <<
389 }; <<
390 opp-1804800000 { <<
391 opp-hz = /bits/ 64 <18 <<
392 opp-supported-hw = <0x <<
393 clock-latency-ns = <20 <<
394 opp-peak-kBps = <13056 <<
395 }; 330 };
396 opp-1824000000 { 331 opp-1824000000 {
397 opp-hz = /bits/ 64 <18 332 opp-hz = /bits/ 64 <1824000000>;
398 opp-supported-hw = <0x !! 333 opp-supported-hw = <0x77>;
399 clock-latency-ns = <20 334 clock-latency-ns = <200000>;
400 opp-peak-kBps = <13824 <<
401 }; <<
402 opp-1900800000 { <<
403 opp-hz = /bits/ 64 <19 <<
404 opp-supported-hw = <0x <<
405 clock-latency-ns = <20 <<
406 opp-peak-kBps = <13056 <<
407 }; 335 };
408 opp-1920000000 { 336 opp-1920000000 {
409 opp-hz = /bits/ 64 <19 337 opp-hz = /bits/ 64 <1920000000>;
410 opp-supported-hw = <0x !! 338 opp-supported-hw = <0x77>;
411 clock-latency-ns = <20 339 clock-latency-ns = <200000>;
412 opp-peak-kBps = <14592 <<
413 }; 340 };
414 opp-1996800000 { 341 opp-1996800000 {
415 opp-hz = /bits/ 64 <19 342 opp-hz = /bits/ 64 <1996800000>;
416 opp-supported-hw = <0x !! 343 opp-supported-hw = <0x77>;
417 clock-latency-ns = <20 344 clock-latency-ns = <200000>;
418 opp-peak-kBps = <15936 <<
419 }; 345 };
420 opp-2073600000 { 346 opp-2073600000 {
421 opp-hz = /bits/ 64 <20 347 opp-hz = /bits/ 64 <2073600000>;
422 opp-supported-hw = <0x !! 348 opp-supported-hw = <0x77>;
423 clock-latency-ns = <20 349 clock-latency-ns = <200000>;
424 opp-peak-kBps = <15936 <<
425 }; 350 };
426 opp-2150400000 { 351 opp-2150400000 {
427 opp-hz = /bits/ 64 <21 352 opp-hz = /bits/ 64 <2150400000>;
428 opp-supported-hw = <0x !! 353 opp-supported-hw = <0x77>;
429 clock-latency-ns = <20 354 clock-latency-ns = <200000>;
430 opp-peak-kBps = <15936 <<
431 }; 355 };
432 }; 356 };
433 357
434 firmware { 358 firmware {
435 scm { 359 scm {
436 compatible = "qcom,scm !! 360 compatible = "qcom,scm-msm8996";
437 qcom,dload-mode = <&tc !! 361 qcom,dload-mode = <&tcsr 0x13000>;
438 }; 362 };
439 }; 363 };
440 364
441 memory@80000000 { !! 365 tcsr_mutex: hwlock {
442 device_type = "memory"; !! 366 compatible = "qcom,tcsr-mutex";
443 /* We expect the bootloader to !! 367 syscon = <&tcsr_mutex_regs 0 0x1000>;
444 reg = <0x0 0x80000000 0x0 0x0> !! 368 #hwlock-cells = <1>;
445 }; 369 };
446 370
447 etm { !! 371 memory {
448 compatible = "qcom,coresight-r !! 372 device_type = "memory";
449 !! 373 /* We expect the bootloader to fill in the reg */
450 out-ports { !! 374 reg = <0 0 0 0>;
451 port { <<
452 modem_etm_out_ <<
453 remote <<
454 <&fu <<
455 }; <<
456 }; <<
457 }; <<
458 }; 375 };
459 376
460 psci { 377 psci {
461 compatible = "arm,psci-1.0"; 378 compatible = "arm,psci-1.0";
462 method = "smc"; 379 method = "smc";
463 }; 380 };
464 381
465 rpm: remoteproc { <<
466 compatible = "qcom,msm8996-rpm <<
467 <<
468 glink-edge { <<
469 compatible = "qcom,gli <<
470 interrupts = <GIC_SPI <<
471 qcom,rpm-msg-ram = <&r <<
472 mboxes = <&apcs_glb 0> <<
473 <<
474 rpm_requests: rpm-requ <<
475 compatible = " <<
476 qcom,glink-cha <<
477 <<
478 rpmcc: clock-c <<
479 compat <<
480 #clock <<
481 clocks <<
482 clock- <<
483 }; <<
484 <<
485 rpmpd: power-c <<
486 compat <<
487 #power <<
488 operat <<
489 <<
490 rpmpd_ <<
491 <<
492 <<
493 <<
494 <<
495 <<
496 <<
497 <<
498 <<
499 <<
500 <<
501 <<
502 <<
503 <<
504 <<
505 <<
506 <<
507 <<
508 <<
509 <<
510 <<
511 <<
512 <<
513 <<
514 <<
515 <<
516 }; <<
517 }; <<
518 }; <<
519 }; <<
520 }; <<
521 <<
522 reserved-memory { 382 reserved-memory {
523 #address-cells = <2>; 383 #address-cells = <2>;
524 #size-cells = <2>; 384 #size-cells = <2>;
525 ranges; 385 ranges;
526 386
527 hyp_mem: memory@85800000 { !! 387 mba_region: mba@91500000 {
528 reg = <0x0 0x85800000 !! 388 reg = <0x0 0x91500000 0x0 0x200000>;
529 no-map; 389 no-map;
530 }; 390 };
531 391
532 xbl_mem: memory@85e00000 { !! 392 slpi_region: slpi@90b00000 {
533 reg = <0x0 0x85e00000 !! 393 reg = <0x0 0x90b00000 0x0 0xa00000>;
>> 394 no-map;
>> 395 };
>> 396
>> 397 venus_region: venus@90400000 {
>> 398 reg = <0x0 0x90400000 0x0 0x700000>;
>> 399 no-map;
>> 400 };
>> 401
>> 402 adsp_region: adsp@8ea00000 {
>> 403 reg = <0x0 0x8ea00000 0x0 0x1a00000>;
>> 404 no-map;
>> 405 };
>> 406
>> 407 mpss_region: mpss@88800000 {
>> 408 reg = <0x0 0x88800000 0x0 0x6200000>;
534 no-map; 409 no-map;
535 }; 410 };
536 411
537 smem_mem: smem-mem@86000000 { 412 smem_mem: smem-mem@86000000 {
538 reg = <0x0 0x86000000 413 reg = <0x0 0x86000000 0x0 0x200000>;
539 no-map; 414 no-map;
540 }; 415 };
541 416
542 tz_mem: memory@86200000 { !! 417 memory@85800000 {
>> 418 reg = <0x0 0x85800000 0x0 0x800000>;
>> 419 no-map;
>> 420 };
>> 421
>> 422 memory@86200000 {
543 reg = <0x0 0x86200000 423 reg = <0x0 0x86200000 0x0 0x2600000>;
544 no-map; 424 no-map;
545 }; 425 };
546 426
547 rmtfs_mem: rmtfs { !! 427 rmtfs@86700000 {
548 compatible = "qcom,rmt 428 compatible = "qcom,rmtfs-mem";
549 429
550 size = <0x0 0x200000>; 430 size = <0x0 0x200000>;
551 alloc-ranges = <0x0 0x 431 alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>;
552 no-map; 432 no-map;
553 433
554 qcom,client-id = <1>; 434 qcom,client-id = <1>;
555 qcom,vmid = <QCOM_SCM_ !! 435 qcom,vmid = <15>;
556 }; 436 };
557 437
558 mpss_mem: mpss@88800000 { !! 438 zap_shader_region: gpu@8f200000 {
559 reg = <0x0 0x88800000 !! 439 compatible = "shared-dma-pool";
>> 440 reg = <0x0 0x90b00000 0x0 0xa00000>;
560 no-map; 441 no-map;
561 }; 442 };
>> 443 };
562 444
563 adsp_mem: adsp@8ea00000 { !! 445 rpm-glink {
564 reg = <0x0 0x8ea00000 !! 446 compatible = "qcom,glink-rpm";
565 no-map; <<
566 }; <<
567 447
568 slpi_mem: slpi@90500000 { !! 448 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
569 reg = <0x0 0x90500000 <<
570 no-map; <<
571 }; <<
572 449
573 gpu_mem: gpu@90f00000 { !! 450 qcom,rpm-msg-ram = <&rpm_msg_ram>;
574 compatible = "shared-d <<
575 reg = <0x0 0x90f00000 <<
576 no-map; <<
577 }; <<
578 451
579 venus_mem: venus@91000000 { !! 452 mboxes = <&apcs_glb 0>;
580 reg = <0x0 0x91000000 <<
581 no-map; <<
582 }; <<
583 453
584 mba_mem: mba@91500000 { !! 454 rpm_requests: rpm-requests {
585 reg = <0x0 0x91500000 !! 455 compatible = "qcom,rpm-msm8996";
586 no-map; !! 456 qcom,glink-channels = "rpm_requests";
587 }; <<
588 457
589 mdata_mem: mpss-metadata { !! 458 rpmcc: qcom,rpmcc {
590 alloc-ranges = <0x0 0x !! 459 compatible = "qcom,rpmcc-msm8996";
591 size = <0x0 0x4000>; !! 460 #clock-cells = <1>;
592 no-map; !! 461 };
>> 462
>> 463 rpmpd: power-controller {
>> 464 compatible = "qcom,msm8996-rpmpd";
>> 465 #power-domain-cells = <1>;
>> 466 operating-points-v2 = <&rpmpd_opp_table>;
>> 467
>> 468 rpmpd_opp_table: opp-table {
>> 469 compatible = "operating-points-v2";
>> 470
>> 471 rpmpd_opp1: opp1 {
>> 472 opp-level = <1>;
>> 473 };
>> 474
>> 475 rpmpd_opp2: opp2 {
>> 476 opp-level = <2>;
>> 477 };
>> 478
>> 479 rpmpd_opp3: opp3 {
>> 480 opp-level = <3>;
>> 481 };
>> 482
>> 483 rpmpd_opp4: opp4 {
>> 484 opp-level = <4>;
>> 485 };
>> 486
>> 487 rpmpd_opp5: opp5 {
>> 488 opp-level = <5>;
>> 489 };
>> 490
>> 491 rpmpd_opp6: opp6 {
>> 492 opp-level = <6>;
>> 493 };
>> 494 };
>> 495 };
593 }; 496 };
594 }; 497 };
595 498
596 smem { 499 smem {
597 compatible = "qcom,smem"; 500 compatible = "qcom,smem";
598 memory-region = <&smem_mem>; 501 memory-region = <&smem_mem>;
599 hwlocks = <&tcsr_mutex 3>; 502 hwlocks = <&tcsr_mutex 3>;
600 }; 503 };
601 504
602 smp2p-adsp { 505 smp2p-adsp {
603 compatible = "qcom,smp2p"; 506 compatible = "qcom,smp2p";
604 qcom,smem = <443>, <429>; 507 qcom,smem = <443>, <429>;
605 508
606 interrupts = <GIC_SPI 158 IRQ_ !! 509 interrupts = <0 158 IRQ_TYPE_EDGE_RISING>;
607 510
608 mboxes = <&apcs_glb 10>; 511 mboxes = <&apcs_glb 10>;
609 512
610 qcom,local-pid = <0>; 513 qcom,local-pid = <0>;
611 qcom,remote-pid = <2>; 514 qcom,remote-pid = <2>;
612 515
613 adsp_smp2p_out: master-kernel !! 516 smp2p_adsp_out: master-kernel {
614 qcom,entry-name = "mas 517 qcom,entry-name = "master-kernel";
615 #qcom,smem-state-cells 518 #qcom,smem-state-cells = <1>;
616 }; 519 };
617 520
618 adsp_smp2p_in: slave-kernel { !! 521 smp2p_adsp_in: slave-kernel {
619 qcom,entry-name = "sla 522 qcom,entry-name = "slave-kernel";
620 523
621 interrupt-controller; 524 interrupt-controller;
622 #interrupt-cells = <2> 525 #interrupt-cells = <2>;
623 }; 526 };
624 }; 527 };
625 528
626 smp2p-mpss { !! 529 smp2p-modem {
627 compatible = "qcom,smp2p"; 530 compatible = "qcom,smp2p";
628 qcom,smem = <435>, <428>; 531 qcom,smem = <435>, <428>;
629 532
630 interrupts = <GIC_SPI 451 IRQ_ 533 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
631 534
632 mboxes = <&apcs_glb 14>; 535 mboxes = <&apcs_glb 14>;
633 536
634 qcom,local-pid = <0>; 537 qcom,local-pid = <0>;
635 qcom,remote-pid = <1>; 538 qcom,remote-pid = <1>;
636 539
637 mpss_smp2p_out: master-kernel !! 540 modem_smp2p_out: master-kernel {
638 qcom,entry-name = "mas 541 qcom,entry-name = "master-kernel";
639 #qcom,smem-state-cells 542 #qcom,smem-state-cells = <1>;
640 }; 543 };
641 544
642 mpss_smp2p_in: slave-kernel { !! 545 modem_smp2p_in: slave-kernel {
643 qcom,entry-name = "sla 546 qcom,entry-name = "slave-kernel";
644 547
645 interrupt-controller; 548 interrupt-controller;
646 #interrupt-cells = <2> 549 #interrupt-cells = <2>;
647 }; 550 };
648 }; 551 };
649 552
650 smp2p-slpi { 553 smp2p-slpi {
651 compatible = "qcom,smp2p"; 554 compatible = "qcom,smp2p";
652 qcom,smem = <481>, <430>; 555 qcom,smem = <481>, <430>;
653 556
654 interrupts = <GIC_SPI 178 IRQ_ 557 interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>;
655 558
656 mboxes = <&apcs_glb 26>; 559 mboxes = <&apcs_glb 26>;
657 560
658 qcom,local-pid = <0>; 561 qcom,local-pid = <0>;
659 qcom,remote-pid = <3>; 562 qcom,remote-pid = <3>;
660 563
661 slpi_smp2p_out: master-kernel !! 564 smp2p_slpi_in: slave-kernel {
662 qcom,entry-name = "mas <<
663 #qcom,smem-state-cells <<
664 }; <<
665 <<
666 slpi_smp2p_in: slave-kernel { <<
667 qcom,entry-name = "sla 565 qcom,entry-name = "slave-kernel";
668 <<
669 interrupt-controller; 566 interrupt-controller;
670 #interrupt-cells = <2> 567 #interrupt-cells = <2>;
671 }; 568 };
>> 569
>> 570 smp2p_slpi_out: master-kernel {
>> 571 qcom,entry-name = "master-kernel";
>> 572 #qcom,smem-state-cells = <1>;
>> 573 };
672 }; 574 };
673 575
674 soc: soc@0 { !! 576 soc: soc {
675 #address-cells = <1>; 577 #address-cells = <1>;
676 #size-cells = <1>; 578 #size-cells = <1>;
677 ranges = <0 0 0 0xffffffff>; 579 ranges = <0 0 0 0xffffffff>;
678 compatible = "simple-bus"; 580 compatible = "simple-bus";
679 581
680 pcie_phy: phy-wrapper@34000 { !! 582 pcie_phy: phy@34000 {
681 compatible = "qcom,msm 583 compatible = "qcom,msm8996-qmp-pcie-phy";
682 reg = <0x00034000 0x48 584 reg = <0x00034000 0x488>;
>> 585 #clock-cells = <1>;
683 #address-cells = <1>; 586 #address-cells = <1>;
684 #size-cells = <1>; 587 #size-cells = <1>;
685 ranges = <0x0 0x000340 !! 588 ranges;
686 589
687 clocks = <&gcc GCC_PCI 590 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
688 <&gcc GCC_PCIE 591 <&gcc GCC_PCIE_PHY_CFG_AHB_CLK>,
689 <&gcc GCC_PCIE 592 <&gcc GCC_PCIE_CLKREF_CLK>;
690 clock-names = "aux", " 593 clock-names = "aux", "cfg_ahb", "ref";
691 594
692 resets = <&gcc GCC_PCI 595 resets = <&gcc GCC_PCIE_PHY_BCR>,
693 <&gcc GCC_PCIE 596 <&gcc GCC_PCIE_PHY_COM_BCR>,
694 <&gcc GCC_PCIE 597 <&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>;
695 reset-names = "phy", " 598 reset-names = "phy", "common", "cfg";
696 <<
697 status = "disabled"; 599 status = "disabled";
698 600
699 pciephy_0: phy@1000 { !! 601 pciephy_0: lane@35000 {
700 reg = <0x1000 !! 602 reg = <0x00035000 0x130>,
701 <0x1200 !! 603 <0x00035200 0x200>,
702 <0x1400 !! 604 <0x00035400 0x1dc>;
>> 605 #phy-cells = <0>;
703 606
>> 607 clock-output-names = "pcie_0_pipe_clk_src";
704 clocks = <&gcc 608 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
705 clock-names = 609 clock-names = "pipe0";
706 resets = <&gcc 610 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
707 reset-names = 611 reset-names = "lane0";
708 <<
709 #clock-cells = <<
710 clock-output-n <<
711 <<
712 #phy-cells = < <<
713 }; 612 };
714 613
715 pciephy_1: phy@2000 { !! 614 pciephy_1: lane@36000 {
716 reg = <0x2000 !! 615 reg = <0x00036000 0x130>,
717 <0x2200 !! 616 <0x00036200 0x200>,
718 <0x2400 !! 617 <0x00036400 0x1dc>;
>> 618 #phy-cells = <0>;
719 619
>> 620 clock-output-names = "pcie_1_pipe_clk_src";
720 clocks = <&gcc 621 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
721 clock-names = 622 clock-names = "pipe1";
722 resets = <&gcc 623 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
723 reset-names = 624 reset-names = "lane1";
724 <<
725 #clock-cells = <<
726 clock-output-n <<
727 <<
728 #phy-cells = < <<
729 }; 625 };
730 626
731 pciephy_2: phy@3000 { !! 627 pciephy_2: lane@37000 {
732 reg = <0x3000 !! 628 reg = <0x00037000 0x130>,
733 <0x3200 !! 629 <0x00037200 0x200>,
734 <0x3400 !! 630 <0x00037400 0x1dc>;
>> 631 #phy-cells = <0>;
735 632
>> 633 clock-output-names = "pcie_2_pipe_clk_src";
736 clocks = <&gcc 634 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>;
737 clock-names = 635 clock-names = "pipe2";
738 resets = <&gcc 636 resets = <&gcc GCC_PCIE_2_PHY_BCR>;
739 reset-names = 637 reset-names = "lane2";
740 <<
741 #clock-cells = <<
742 clock-output-n <<
743 <<
744 #phy-cells = < <<
745 }; 638 };
746 }; 639 };
747 640
748 rpm_msg_ram: sram@68000 { !! 641 rpm_msg_ram: memory@68000 {
749 compatible = "qcom,rpm 642 compatible = "qcom,rpm-msg-ram";
750 reg = <0x00068000 0x60 643 reg = <0x00068000 0x6000>;
751 }; 644 };
752 645
753 qfprom@74000 { 646 qfprom@74000 {
754 compatible = "qcom,msm !! 647 compatible = "qcom,qfprom";
755 reg = <0x00074000 0x8f 648 reg = <0x00074000 0x8ff>;
756 #address-cells = <1>; 649 #address-cells = <1>;
757 #size-cells = <1>; 650 #size-cells = <1>;
758 651
759 qusb2p_hstx_trim: hstx !! 652 qusb2p_hstx_trim: hstx_trim@24e {
760 reg = <0x24e 0 653 reg = <0x24e 0x2>;
761 bits = <5 4>; 654 bits = <5 4>;
762 }; 655 };
763 656
764 qusb2s_hstx_trim: hstx !! 657 qusb2s_hstx_trim: hstx_trim@24f {
765 reg = <0x24f 0 658 reg = <0x24f 0x1>;
766 bits = <1 4>; 659 bits = <1 4>;
767 }; 660 };
768 661
769 speedbin_efuse: speedb 662 speedbin_efuse: speedbin@133 {
770 reg = <0x133 0 663 reg = <0x133 0x1>;
771 bits = <5 3>; 664 bits = <5 3>;
772 }; 665 };
773 }; 666 };
774 667
775 rng: rng@83000 { 668 rng: rng@83000 {
776 compatible = "qcom,prn 669 compatible = "qcom,prng-ee";
777 reg = <0x00083000 0x10 670 reg = <0x00083000 0x1000>;
778 clocks = <&gcc GCC_PRN 671 clocks = <&gcc GCC_PRNG_AHB_CLK>;
779 clock-names = "core"; 672 clock-names = "core";
780 }; 673 };
781 674
782 gcc: clock-controller@300000 { 675 gcc: clock-controller@300000 {
783 compatible = "qcom,gcc 676 compatible = "qcom,gcc-msm8996";
784 #clock-cells = <1>; 677 #clock-cells = <1>;
785 #reset-cells = <1>; 678 #reset-cells = <1>;
786 #power-domain-cells = 679 #power-domain-cells = <1>;
787 reg = <0x00300000 0x90 680 reg = <0x00300000 0x90000>;
788 681
789 clocks = <&rpmcc RPM_S !! 682 clocks = <&rpmcc RPM_SMD_LN_BB_CLK>;
790 <&rpmcc RPM_S !! 683 clock-names = "cxo2";
791 <&sleep_clk>, <<
792 <&pciephy_0>, <<
793 <&pciephy_1>, <<
794 <&pciephy_2>, <<
795 <&usb3phy>, <<
796 <&ufsphy 0>, <<
797 <&ufsphy 1>, <<
798 <&ufsphy 2>; <<
799 clock-names = "cxo", <<
800 "cxo2", <<
801 "sleep_c <<
802 "pcie_0_ <<
803 "pcie_1_ <<
804 "pcie_2_ <<
805 "usb3_ph <<
806 "ufs_rx_ <<
807 "ufs_rx_ <<
808 "ufs_tx_ <<
809 }; <<
810 <<
811 bimc: interconnect@408000 { <<
812 compatible = "qcom,msm <<
813 reg = <0x00408000 0x5a <<
814 #interconnect-cells = <<
815 }; 684 };
816 685
817 tsens0: thermal-sensor@4a9000 686 tsens0: thermal-sensor@4a9000 {
818 compatible = "qcom,msm 687 compatible = "qcom,msm8996-tsens", "qcom,tsens-v2";
819 reg = <0x004a9000 0x10 688 reg = <0x004a9000 0x1000>, /* TM */
820 <0x004a8000 0x10 689 <0x004a8000 0x1000>; /* SROT */
821 #qcom,sensors = <13>; 690 #qcom,sensors = <13>;
822 interrupts = <GIC_SPI 691 interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
823 <GIC_SPI 692 <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
824 interrupt-names = "upl 693 interrupt-names = "uplow", "critical";
825 #thermal-sensor-cells 694 #thermal-sensor-cells = <1>;
826 }; 695 };
827 696
828 tsens1: thermal-sensor@4ad000 697 tsens1: thermal-sensor@4ad000 {
829 compatible = "qcom,msm 698 compatible = "qcom,msm8996-tsens", "qcom,tsens-v2";
830 reg = <0x004ad000 0x10 699 reg = <0x004ad000 0x1000>, /* TM */
831 <0x004ac000 0x10 700 <0x004ac000 0x1000>; /* SROT */
832 #qcom,sensors = <8>; 701 #qcom,sensors = <8>;
833 interrupts = <GIC_SPI 702 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
834 <GIC_SPI 703 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>;
835 interrupt-names = "upl 704 interrupt-names = "uplow", "critical";
836 #thermal-sensor-cells 705 #thermal-sensor-cells = <1>;
837 }; 706 };
838 707
839 cryptobam: dma-controller@6440 !! 708 tcsr_mutex_regs: syscon@740000 {
840 compatible = "qcom,bam !! 709 compatible = "syscon";
841 reg = <0x00644000 0x24 !! 710 reg = <0x00740000 0x40000>;
842 interrupts = <GIC_SPI <<
843 clocks = <&gcc GCC_CE1 <<
844 clock-names = "bam_clk <<
845 #dma-cells = <1>; <<
846 qcom,ee = <0>; <<
847 qcom,controlled-remote <<
848 }; <<
849 <<
850 crypto: crypto@67a000 { <<
851 compatible = "qcom,cry <<
852 reg = <0x0067a000 0x60 <<
853 clocks = <&gcc GCC_CE1 <<
854 <&gcc GCC_CE1 <<
855 <&gcc GCC_CE1 <<
856 clock-names = "iface", <<
857 dmas = <&cryptobam 6>, <<
858 dma-names = "rx", "tx" <<
859 }; <<
860 <<
861 cnoc: interconnect@500000 { <<
862 compatible = "qcom,msm <<
863 reg = <0x00500000 0x10 <<
864 #interconnect-cells = <<
865 }; <<
866 <<
867 snoc: interconnect@524000 { <<
868 compatible = "qcom,msm <<
869 reg = <0x00524000 0x1c <<
870 #interconnect-cells = <<
871 }; <<
872 <<
873 a0noc: interconnect@543000 { <<
874 compatible = "qcom,msm <<
875 reg = <0x00543000 0x60 <<
876 #interconnect-cells = <<
877 clock-names = "aggre0_ <<
878 "aggre0_ <<
879 "aggre0_ <<
880 clocks = <&gcc GCC_AGG <<
881 <&gcc GCC_AGG <<
882 <&gcc GCC_AGG <<
883 power-domains = <&gcc <<
884 }; <<
885 <<
886 a1noc: interconnect@562000 { <<
887 compatible = "qcom,msm <<
888 reg = <0x00562000 0x50 <<
889 #interconnect-cells = <<
890 }; <<
891 <<
892 a2noc: interconnect@583000 { <<
893 compatible = "qcom,msm <<
894 reg = <0x00583000 0x70 <<
895 #interconnect-cells = <<
896 clock-names = "aggre2_ <<
897 clocks = <&gcc GCC_AGG <<
898 <&gcc GCC_UFS <<
899 }; <<
900 <<
901 mnoc: interconnect@5a4000 { <<
902 compatible = "qcom,msm <<
903 reg = <0x005a4000 0x1c <<
904 #interconnect-cells = <<
905 clock-names = "iface"; <<
906 clocks = <&mmcc AHB_CL <<
907 }; <<
908 <<
909 pnoc: interconnect@5c0000 { <<
910 compatible = "qcom,msm <<
911 reg = <0x005c0000 0x30 <<
912 #interconnect-cells = <<
913 }; <<
914 <<
915 tcsr_mutex: hwlock@740000 { <<
916 compatible = "qcom,tcs <<
917 reg = <0x00740000 0x20 <<
918 #hwlock-cells = <1>; <<
919 }; <<
920 <<
921 tcsr_1: syscon@760000 { <<
922 compatible = "qcom,tcs <<
923 reg = <0x00760000 0x20 <<
924 }; 711 };
925 712
926 tcsr_2: syscon@7a0000 { !! 713 tcsr: syscon@7a0000 {
927 compatible = "qcom,tcs 714 compatible = "qcom,tcsr-msm8996", "syscon";
928 reg = <0x007a0000 0x18 715 reg = <0x007a0000 0x18000>;
929 }; 716 };
930 717
931 mmcc: clock-controller@8c0000 718 mmcc: clock-controller@8c0000 {
932 compatible = "qcom,mmc 719 compatible = "qcom,mmcc-msm8996";
933 #clock-cells = <1>; 720 #clock-cells = <1>;
934 #reset-cells = <1>; 721 #reset-cells = <1>;
935 #power-domain-cells = 722 #power-domain-cells = <1>;
936 reg = <0x008c0000 0x40 723 reg = <0x008c0000 0x40000>;
937 clocks = <&xo_board>, <<
938 <&gcc GPLL0>, <<
939 <&gcc GCC_MMS <<
940 <&mdss_dsi0_p <<
941 <&mdss_dsi0_p <<
942 <&mdss_dsi1_p <<
943 <&mdss_dsi1_p <<
944 <&mdss_hdmi_p <<
945 clock-names = "xo", <<
946 "gpll0", <<
947 "gcc_mms <<
948 "dsi0pll <<
949 "dsi0pll <<
950 "dsi1pll <<
951 "dsi1pll <<
952 "hdmipll <<
953 assigned-clocks = <&mm 724 assigned-clocks = <&mmcc MMPLL9_PLL>,
954 <&mm 725 <&mmcc MMPLL1_PLL>,
955 <&mm 726 <&mmcc MMPLL3_PLL>,
956 <&mm 727 <&mmcc MMPLL4_PLL>,
957 <&mm 728 <&mmcc MMPLL5_PLL>;
958 assigned-clock-rates = 729 assigned-clock-rates = <624000000>,
959 730 <810000000>,
960 731 <980000000>,
961 732 <960000000>,
962 733 <825000000>;
963 }; 734 };
964 735
965 mdss: display-subsystem@900000 !! 736 mdss: mdss@900000 {
966 compatible = "qcom,mds 737 compatible = "qcom,mdss";
967 738
968 reg = <0x00900000 0x10 739 reg = <0x00900000 0x1000>,
969 <0x009b0000 0x10 740 <0x009b0000 0x1040>,
970 <0x009b8000 0x10 741 <0x009b8000 0x1040>;
971 reg-names = "mdss_phys 742 reg-names = "mdss_phys",
972 "vbif_phys 743 "vbif_phys",
973 "vbif_nrt_ 744 "vbif_nrt_phys";
974 745
975 power-domains = <&mmcc 746 power-domains = <&mmcc MDSS_GDSC>;
976 interrupts = <GIC_SPI 747 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
977 748
978 interrupt-controller; 749 interrupt-controller;
979 #interrupt-cells = <1> 750 #interrupt-cells = <1>;
980 751
981 clocks = <&mmcc MDSS_A !! 752 clocks = <&mmcc MDSS_AHB_CLK>;
982 <&mmcc MDSS_M !! 753 clock-names = "iface";
983 clock-names = "iface", <<
984 <<
985 resets = <&mmcc MDSS_B <<
986 754
987 #address-cells = <1>; 755 #address-cells = <1>;
988 #size-cells = <1>; 756 #size-cells = <1>;
989 ranges; 757 ranges;
990 758
991 status = "disabled"; 759 status = "disabled";
992 760
993 mdp: display-controlle !! 761 mdp: mdp@901000 {
994 compatible = " !! 762 compatible = "qcom,mdp5";
995 reg = <0x00901 763 reg = <0x00901000 0x90000>;
996 reg-names = "m 764 reg-names = "mdp_phys";
997 765
998 interrupt-pare 766 interrupt-parent = <&mdss>;
999 interrupts = < !! 767 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
1000 768
1001 clocks = <&mm 769 clocks = <&mmcc MDSS_AHB_CLK>,
1002 <&mm 770 <&mmcc MDSS_AXI_CLK>,
1003 <&mm 771 <&mmcc MDSS_MDP_CLK>,
1004 <&mm 772 <&mmcc SMMU_MDP_AXI_CLK>,
1005 <&mm 773 <&mmcc MDSS_VSYNC_CLK>;
1006 clock-names = 774 clock-names = "iface",
1007 775 "bus",
1008 776 "core",
1009 777 "iommu",
1010 778 "vsync";
1011 779
1012 iommus = <&md 780 iommus = <&mdp_smmu 0>;
1013 781
1014 assigned-cloc 782 assigned-clocks = <&mmcc MDSS_MDP_CLK>,
1015 <&mm 783 <&mmcc MDSS_VSYNC_CLK>;
1016 assigned-cloc 784 assigned-clock-rates = <300000000>,
1017 <192 785 <19200000>;
1018 786
1019 interconnects <<
1020 <<
1021 <<
1022 interconnect- <<
1023 <<
1024 ports { 787 ports {
1025 #addr 788 #address-cells = <1>;
1026 #size 789 #size-cells = <0>;
1027 790
1028 port@ 791 port@0 {
1029 792 reg = <0>;
1030 793 mdp5_intf3_out: endpoint {
1031 !! 794 remote-endpoint = <&hdmi_in>;
1032 795 };
1033 }; 796 };
1034 797
1035 port@ 798 port@1 {
1036 799 reg = <1>;
1037 800 mdp5_intf1_out: endpoint {
1038 !! 801 remote-endpoint = <&dsi0_in>;
1039 <<
1040 }; <<
1041 <<
1042 port@ <<
1043 <<
1044 <<
1045 <<
1046 802 };
1047 }; 803 };
1048 }; 804 };
1049 }; 805 };
1050 806
1051 mdss_dsi0: dsi@994000 !! 807 dsi0: dsi@994000 {
1052 compatible = !! 808 compatible = "qcom,mdss-dsi-ctrl";
1053 <<
1054 reg = <0x0099 809 reg = <0x00994000 0x400>;
1055 reg-names = " 810 reg-names = "dsi_ctrl";
1056 811
1057 interrupt-par 812 interrupt-parent = <&mdss>;
1058 interrupts = !! 813 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
1059 814
1060 clocks = <&mm 815 clocks = <&mmcc MDSS_MDP_CLK>,
1061 <&mm 816 <&mmcc MDSS_BYTE0_CLK>,
1062 <&mm 817 <&mmcc MDSS_AHB_CLK>,
1063 <&mm 818 <&mmcc MDSS_AXI_CLK>,
1064 <&mm 819 <&mmcc MMSS_MISC_AHB_CLK>,
1065 <&mm 820 <&mmcc MDSS_PCLK0_CLK>,
1066 <&mm 821 <&mmcc MDSS_ESC0_CLK>;
1067 clock-names = 822 clock-names = "mdp_core",
1068 823 "byte",
1069 824 "iface",
1070 825 "bus",
1071 826 "core_mmss",
1072 827 "pixel",
1073 828 "core";
1074 assigned-cloc <<
1075 assigned-cloc <<
1076 829
1077 phys = <&mdss !! 830 phys = <&dsi0_phy>;
>> 831 phy-names = "dsi";
1078 status = "dis 832 status = "disabled";
1079 833
1080 #address-cell 834 #address-cells = <1>;
1081 #size-cells = 835 #size-cells = <0>;
1082 836
1083 ports { 837 ports {
1084 #addr 838 #address-cells = <1>;
1085 #size 839 #size-cells = <0>;
1086 840
1087 port@ 841 port@0 {
1088 842 reg = <0>;
1089 !! 843 dsi0_in: endpoint {
1090 844 remote-endpoint = <&mdp5_intf1_out>;
1091 845 };
1092 }; 846 };
1093 847
1094 port@ 848 port@1 {
1095 849 reg = <1>;
1096 !! 850 dsi0_out: endpoint {
1097 851 };
1098 }; 852 };
1099 }; 853 };
1100 }; 854 };
1101 855
1102 mdss_dsi0_phy: phy@99 !! 856 dsi0_phy: dsi-phy@994400 {
1103 compatible = 857 compatible = "qcom,dsi-phy-14nm";
1104 reg = <0x0099 858 reg = <0x00994400 0x100>,
1105 <0x0099 859 <0x00994500 0x300>,
1106 <0x0099 860 <0x00994800 0x188>;
1107 reg-names = " 861 reg-names = "dsi_phy",
1108 " 862 "dsi_phy_lane",
1109 " 863 "dsi_pll";
1110 864
1111 #clock-cells 865 #clock-cells = <1>;
1112 #phy-cells = 866 #phy-cells = <0>;
1113 867
1114 clocks = <&mm !! 868 clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>;
1115 clock-names = <<
1116 status = "dis <<
1117 }; <<
1118 <<
1119 mdss_dsi1: dsi@996000 <<
1120 compatible = <<
1121 <<
1122 reg = <0x0099 <<
1123 reg-names = " <<
1124 <<
1125 interrupt-par <<
1126 interrupts = <<
1127 <<
1128 clocks = <&mm <<
1129 <&mm <<
1130 <&mm <<
1131 <&mm <<
1132 <&mm <<
1133 <&mm <<
1134 <&mm <<
1135 clock-names = <<
1136 <<
1137 <<
1138 <<
1139 <<
1140 <<
1141 <<
1142 assigned-cloc <<
1143 assigned-cloc <<
1144 <<
1145 phys = <&mdss <<
1146 status = "dis <<
1147 <<
1148 #address-cell <<
1149 #size-cells = <<
1150 <<
1151 ports { <<
1152 #addr <<
1153 #size <<
1154 <<
1155 port@ <<
1156 <<
1157 <<
1158 <<
1159 <<
1160 }; <<
1161 <<
1162 port@ <<
1163 <<
1164 <<
1165 <<
1166 }; <<
1167 }; <<
1168 }; <<
1169 <<
1170 mdss_dsi1_phy: phy@99 <<
1171 compatible = <<
1172 reg = <0x0099 <<
1173 <0x0099 <<
1174 <0x0099 <<
1175 reg-names = " <<
1176 " <<
1177 " <<
1178 <<
1179 #clock-cells <<
1180 #phy-cells = <<
1181 <<
1182 clocks = <&mm <<
1183 clock-names = 869 clock-names = "iface", "ref";
1184 status = "dis 870 status = "disabled";
1185 }; 871 };
1186 872
1187 mdss_hdmi: hdmi-tx@9a !! 873 hdmi: hdmi-tx@9a0000 {
1188 compatible = 874 compatible = "qcom,hdmi-tx-8996";
1189 reg = <0x009a !! 875 reg = <0x009a0000 0x50c>,
1190 <0x0007 !! 876 <0x00070000 0x6158>,
1191 <0x009e !! 877 <0x009e0000 0xfff>;
1192 reg-names = " 878 reg-names = "core_physical",
1193 " 879 "qfprom_physical",
1194 " 880 "hdcp_physical";
1195 881
1196 interrupt-par 882 interrupt-parent = <&mdss>;
1197 interrupts = !! 883 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
1198 884
1199 clocks = <&mm 885 clocks = <&mmcc MDSS_MDP_CLK>,
1200 <&mm 886 <&mmcc MDSS_AHB_CLK>,
1201 <&mm 887 <&mmcc MDSS_HDMI_CLK>,
1202 <&mm 888 <&mmcc MDSS_HDMI_AHB_CLK>,
1203 <&mm 889 <&mmcc MDSS_EXTPCLK_CLK>;
1204 clock-names = 890 clock-names =
1205 "mdp_ 891 "mdp_core",
1206 "ifac 892 "iface",
1207 "core 893 "core",
1208 "alt_ 894 "alt_iface",
1209 "extp 895 "extp";
1210 896
1211 phys = <&mdss !! 897 phys = <&hdmi_phy>;
>> 898 phy-names = "hdmi_phy";
1212 #sound-dai-ce 899 #sound-dai-cells = <1>;
1213 900
1214 status = "dis <<
1215 <<
1216 ports { 901 ports {
1217 #addr 902 #address-cells = <1>;
1218 #size 903 #size-cells = <0>;
1219 904
1220 port@ 905 port@0 {
1221 906 reg = <0>;
1222 !! 907 hdmi_in: endpoint {
1223 908 remote-endpoint = <&mdp5_intf3_out>;
1224 909 };
1225 }; 910 };
1226 }; 911 };
1227 }; 912 };
1228 913
1229 mdss_hdmi_phy: phy@9a !! 914 hdmi_phy: hdmi-phy@9a0600 {
1230 #phy-cells = 915 #phy-cells = <0>;
1231 compatible = 916 compatible = "qcom,hdmi-phy-8996";
1232 reg = <0x009a 917 reg = <0x009a0600 0x1c4>,
1233 <0x009a 918 <0x009a0a00 0x124>,
1234 <0x009a 919 <0x009a0c00 0x124>,
1235 <0x009a 920 <0x009a0e00 0x124>,
1236 <0x009a 921 <0x009a1000 0x124>,
1237 <0x009a 922 <0x009a1200 0x0c8>;
1238 reg-names = " 923 reg-names = "hdmi_pll",
1239 " 924 "hdmi_tx_l0",
1240 " 925 "hdmi_tx_l1",
1241 " 926 "hdmi_tx_l2",
1242 " 927 "hdmi_tx_l3",
1243 " 928 "hdmi_phy";
1244 929
1245 clocks = <&mm 930 clocks = <&mmcc MDSS_AHB_CLK>,
1246 <&gc !! 931 <&gcc GCC_HDMI_CLKREF_CLK>;
1247 <&xo <<
1248 clock-names = 932 clock-names = "iface",
1249 !! 933 "ref";
1250 <<
1251 <<
1252 #clock-cells <<
1253 <<
1254 status = "dis <<
1255 }; 934 };
1256 }; 935 };
1257 936
1258 gpu: gpu@b00000 { 937 gpu: gpu@b00000 {
1259 compatible = "qcom,ad 938 compatible = "qcom,adreno-530.2", "qcom,adreno";
>> 939 #stream-id-cells = <16>;
1260 940
1261 reg = <0x00b00000 0x3 941 reg = <0x00b00000 0x3f000>;
1262 reg-names = "kgsl_3d0 942 reg-names = "kgsl_3d0_reg_memory";
1263 943
1264 interrupts = <GIC_SPI !! 944 interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;
1265 945
1266 clocks = <&mmcc GPU_G 946 clocks = <&mmcc GPU_GX_GFX3D_CLK>,
1267 <&mmcc GPU_AH 947 <&mmcc GPU_AHB_CLK>,
1268 <&mmcc GPU_GX 948 <&mmcc GPU_GX_RBBMTIMER_CLK>,
1269 <&gcc GCC_BIM 949 <&gcc GCC_BIMC_GFX_CLK>,
1270 <&gcc GCC_MMS 950 <&gcc GCC_MMSS_BIMC_GFX_CLK>;
1271 951
1272 clock-names = "core", 952 clock-names = "core",
1273 "iface", 953 "iface",
1274 "rbbmtimer", 954 "rbbmtimer",
1275 "mem", 955 "mem",
1276 "mem_iface"; 956 "mem_iface";
1277 957
1278 interconnects = <&bim <<
1279 interconnect-names = <<
1280 <<
1281 power-domains = <&mmc 958 power-domains = <&mmcc GPU_GX_GDSC>;
1282 iommus = <&adreno_smm 959 iommus = <&adreno_smmu 0>;
1283 960
1284 nvmem-cells = <&speed 961 nvmem-cells = <&speedbin_efuse>;
1285 nvmem-cell-names = "s 962 nvmem-cell-names = "speed_bin";
1286 963
>> 964 qcom,gpu-quirk-two-pass-use-wfi;
>> 965 qcom,gpu-quirk-fault-detect-mask;
>> 966
1287 operating-points-v2 = 967 operating-points-v2 = <&gpu_opp_table>;
1288 968
1289 status = "disabled"; 969 status = "disabled";
1290 970
1291 #cooling-cells = <2>; <<
1292 <<
1293 gpu_opp_table: opp-ta 971 gpu_opp_table: opp-table {
1294 compatible = !! 972 compatible ="operating-points-v2";
1295 973
1296 /* 974 /*
1297 * 624Mhz is !! 975 * 624Mhz and 560Mhz are only available on speed
1298 * 560Mhz is !! 976 * bin (1 << 0). All the rest are available on
1299 * All the re !! 977 * all bins of the hardware
1300 */ 978 */
1301 opp-624000000 979 opp-624000000 {
1302 opp-h 980 opp-hz = /bits/ 64 <624000000>;
1303 opp-s !! 981 opp-supported-hw = <0x01>;
1304 }; 982 };
1305 opp-560000000 983 opp-560000000 {
1306 opp-h 984 opp-hz = /bits/ 64 <560000000>;
1307 opp-s !! 985 opp-supported-hw = <0x01>;
1308 }; 986 };
1309 opp-510000000 987 opp-510000000 {
1310 opp-h 988 opp-hz = /bits/ 64 <510000000>;
1311 opp-s !! 989 opp-supported-hw = <0xFF>;
1312 }; 990 };
1313 opp-401800000 991 opp-401800000 {
1314 opp-h 992 opp-hz = /bits/ 64 <401800000>;
1315 opp-s !! 993 opp-supported-hw = <0xFF>;
1316 }; 994 };
1317 opp-315000000 995 opp-315000000 {
1318 opp-h 996 opp-hz = /bits/ 64 <315000000>;
1319 opp-s !! 997 opp-supported-hw = <0xFF>;
1320 }; 998 };
1321 opp-214000000 999 opp-214000000 {
1322 opp-h 1000 opp-hz = /bits/ 64 <214000000>;
1323 opp-s !! 1001 opp-supported-hw = <0xFF>;
1324 }; 1002 };
1325 opp-133000000 1003 opp-133000000 {
1326 opp-h 1004 opp-hz = /bits/ 64 <133000000>;
1327 opp-s !! 1005 opp-supported-hw = <0xFF>;
1328 }; 1006 };
1329 }; 1007 };
1330 1008
1331 zap-shader { 1009 zap-shader {
1332 memory-region !! 1010 memory-region = <&zap_shader_region>;
1333 }; 1011 };
1334 }; 1012 };
1335 1013
1336 tlmm: pinctrl@1010000 { 1014 tlmm: pinctrl@1010000 {
1337 compatible = "qcom,ms 1015 compatible = "qcom,msm8996-pinctrl";
1338 reg = <0x01010000 0x3 1016 reg = <0x01010000 0x300000>;
1339 interrupts = <GIC_SPI 1017 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1340 gpio-controller; 1018 gpio-controller;
1341 gpio-ranges = <&tlmm 1019 gpio-ranges = <&tlmm 0 0 150>;
1342 #gpio-cells = <2>; 1020 #gpio-cells = <2>;
1343 interrupt-controller; 1021 interrupt-controller;
1344 #interrupt-cells = <2 1022 #interrupt-cells = <2>;
1345 1023
1346 blsp1_spi1_default: b !! 1024 blsp1_spi1_default: blsp1-spi1-default {
1347 spi-pins { !! 1025 spi {
1348 pins 1026 pins = "gpio0", "gpio1", "gpio3";
1349 funct 1027 function = "blsp_spi1";
1350 drive 1028 drive-strength = <12>;
1351 bias- 1029 bias-disable;
1352 }; 1030 };
1353 1031
1354 cs-pins { !! 1032 cs {
1355 pins 1033 pins = "gpio2";
1356 funct 1034 function = "gpio";
1357 drive 1035 drive-strength = <16>;
1358 bias- 1036 bias-disable;
1359 outpu 1037 output-high;
1360 }; 1038 };
1361 }; 1039 };
1362 1040
1363 blsp1_spi1_sleep: bls !! 1041 blsp1_spi1_sleep: blsp1-spi1-sleep {
1364 pins = "gpio0 1042 pins = "gpio0", "gpio1", "gpio2", "gpio3";
1365 function = "g 1043 function = "gpio";
1366 drive-strengt 1044 drive-strength = <2>;
1367 bias-pull-dow 1045 bias-pull-down;
1368 }; 1046 };
1369 1047
1370 blsp2_uart2_2pins_def !! 1048 blsp2_uart2_2pins_default: blsp2-uart1-2pins {
1371 pins = "gpio4 1049 pins = "gpio4", "gpio5";
1372 function = "b 1050 function = "blsp_uart8";
1373 drive-strengt 1051 drive-strength = <16>;
1374 bias-disable; 1052 bias-disable;
1375 }; 1053 };
1376 1054
1377 blsp2_uart2_2pins_sle !! 1055 blsp2_uart2_2pins_sleep: blsp2-uart1-2pins-sleep {
1378 pins = "gpio4 1056 pins = "gpio4", "gpio5";
1379 function = "g 1057 function = "gpio";
1380 drive-strengt 1058 drive-strength = <2>;
1381 bias-disable; 1059 bias-disable;
1382 }; 1060 };
1383 1061
1384 blsp2_i2c2_default: b !! 1062 blsp2_i2c2_default: blsp2-i2c2 {
1385 pins = "gpio6 1063 pins = "gpio6", "gpio7";
1386 function = "b 1064 function = "blsp_i2c8";
1387 drive-strengt 1065 drive-strength = <16>;
1388 bias-disable; 1066 bias-disable;
1389 }; 1067 };
1390 1068
1391 blsp2_i2c2_sleep: bls !! 1069 blsp2_i2c2_sleep: blsp2-i2c2-sleep {
1392 pins = "gpio6 1070 pins = "gpio6", "gpio7";
1393 function = "g 1071 function = "gpio";
1394 drive-strengt 1072 drive-strength = <2>;
1395 bias-disable; 1073 bias-disable;
1396 }; 1074 };
1397 1075
1398 blsp1_i2c6_default: b !! 1076 cci0_default: cci0-default {
1399 pins = "gpio2 <<
1400 function = "b <<
1401 drive-strengt <<
1402 bias-disable; <<
1403 }; <<
1404 <<
1405 blsp1_i2c6_sleep: bls <<
1406 pins = "gpio2 <<
1407 function = "g <<
1408 drive-strengt <<
1409 bias-pull-up; <<
1410 }; <<
1411 <<
1412 cci0_default: cci0-de <<
1413 pins = "gpio1 1077 pins = "gpio17", "gpio18";
1414 function = "c 1078 function = "cci_i2c";
1415 drive-strengt 1079 drive-strength = <16>;
1416 bias-disable; 1080 bias-disable;
1417 }; 1081 };
1418 1082
1419 camera0_state_on: 1083 camera0_state_on:
1420 camera_rear_default: !! 1084 camera_rear_default: camera-rear-default {
1421 camera0_mclk: !! 1085 mclk0 {
1422 pins 1086 pins = "gpio13";
1423 funct 1087 function = "cam_mclk";
1424 drive 1088 drive-strength = <16>;
1425 bias- 1089 bias-disable;
1426 }; 1090 };
1427 1091
1428 camera0_rst: !! 1092 rst {
1429 pins 1093 pins = "gpio25";
1430 funct 1094 function = "gpio";
1431 drive 1095 drive-strength = <16>;
1432 bias- 1096 bias-disable;
1433 }; 1097 };
1434 1098
1435 camera0_pwdn: !! 1099 pwdn {
1436 pins 1100 pins = "gpio26";
1437 funct 1101 function = "gpio";
1438 drive 1102 drive-strength = <16>;
1439 bias- 1103 bias-disable;
1440 }; 1104 };
1441 }; 1105 };
1442 1106
1443 cci1_default: cci1-de !! 1107 cci1_default: cci1-default {
1444 pins = "gpio1 1108 pins = "gpio19", "gpio20";
1445 function = "c 1109 function = "cci_i2c";
1446 drive-strengt 1110 drive-strength = <16>;
1447 bias-disable; 1111 bias-disable;
1448 }; 1112 };
1449 1113
1450 camera1_state_on: 1114 camera1_state_on:
1451 camera_board_default: !! 1115 camera_board_default: camera-board-default {
1452 mclk1-pins { !! 1116 mclk1 {
1453 pins 1117 pins = "gpio14";
1454 funct 1118 function = "cam_mclk";
1455 drive 1119 drive-strength = <16>;
1456 bias- 1120 bias-disable;
1457 }; 1121 };
1458 1122
1459 pwdn-pins { !! 1123 pwdn {
1460 pins 1124 pins = "gpio98";
1461 funct 1125 function = "gpio";
1462 drive 1126 drive-strength = <16>;
1463 bias- 1127 bias-disable;
1464 }; 1128 };
1465 1129
1466 rst-pins { !! 1130 rst {
1467 pins 1131 pins = "gpio104";
1468 funct 1132 function = "gpio";
1469 drive 1133 drive-strength = <16>;
1470 bias- 1134 bias-disable;
1471 }; 1135 };
1472 }; 1136 };
1473 1137
1474 camera2_state_on: 1138 camera2_state_on:
1475 camera_front_default: !! 1139 camera_front_default: camera-front-default {
1476 camera2_mclk: !! 1140 mclk2 {
1477 pins 1141 pins = "gpio15";
1478 funct 1142 function = "cam_mclk";
1479 drive 1143 drive-strength = <16>;
1480 bias- 1144 bias-disable;
1481 }; 1145 };
1482 1146
1483 camera2_rst: !! 1147 rst {
1484 pins 1148 pins = "gpio23";
1485 funct 1149 function = "gpio";
1486 drive 1150 drive-strength = <16>;
1487 bias- 1151 bias-disable;
1488 }; 1152 };
1489 1153
1490 pwdn-pins { !! 1154 pwdn {
1491 pins 1155 pins = "gpio133";
1492 funct 1156 function = "gpio";
1493 drive 1157 drive-strength = <16>;
1494 bias- 1158 bias-disable;
1495 }; 1159 };
1496 }; 1160 };
1497 1161
1498 pcie0_state_on: pcie0 !! 1162 pcie0_state_on: pcie0-state-on {
1499 perst-pins { !! 1163 perst {
1500 pins 1164 pins = "gpio35";
1501 funct 1165 function = "gpio";
1502 drive 1166 drive-strength = <2>;
1503 bias- 1167 bias-pull-down;
1504 }; 1168 };
1505 1169
1506 clkreq-pins { !! 1170 clkreq {
1507 pins 1171 pins = "gpio36";
1508 funct 1172 function = "pci_e0";
1509 drive 1173 drive-strength = <2>;
1510 bias- 1174 bias-pull-up;
1511 }; 1175 };
1512 1176
1513 wake-pins { !! 1177 wake {
1514 pins 1178 pins = "gpio37";
1515 funct 1179 function = "gpio";
1516 drive 1180 drive-strength = <2>;
1517 bias- 1181 bias-pull-up;
1518 }; 1182 };
1519 }; 1183 };
1520 1184
1521 pcie0_state_off: pcie !! 1185 pcie0_state_off: pcie0-state-off {
1522 perst-pins { !! 1186 perst {
1523 pins 1187 pins = "gpio35";
1524 funct 1188 function = "gpio";
1525 drive 1189 drive-strength = <2>;
1526 bias- 1190 bias-pull-down;
1527 }; 1191 };
1528 1192
1529 clkreq-pins { !! 1193 clkreq {
1530 pins 1194 pins = "gpio36";
1531 funct 1195 function = "gpio";
1532 drive 1196 drive-strength = <2>;
1533 bias- 1197 bias-disable;
1534 }; 1198 };
1535 1199
1536 wake-pins { !! 1200 wake {
1537 pins 1201 pins = "gpio37";
1538 funct 1202 function = "gpio";
1539 drive 1203 drive-strength = <2>;
1540 bias- 1204 bias-disable;
1541 }; 1205 };
1542 }; 1206 };
1543 1207
1544 blsp1_uart2_default: !! 1208 blsp1_i2c3_default: blsp1-i2c2-default {
1545 pins = "gpio4 <<
1546 function = "b <<
1547 drive-strengt <<
1548 bias-disable; <<
1549 }; <<
1550 <<
1551 blsp1_uart2_sleep: bl <<
1552 pins = "gpio4 <<
1553 function = "g <<
1554 drive-strengt <<
1555 bias-disable; <<
1556 }; <<
1557 <<
1558 blsp1_i2c3_default: b <<
1559 pins = "gpio4 1209 pins = "gpio47", "gpio48";
1560 function = "b 1210 function = "blsp_i2c3";
1561 drive-strengt 1211 drive-strength = <16>;
1562 bias-disable; !! 1212 bias-disable = <0>;
1563 }; 1213 };
1564 1214
1565 blsp1_i2c3_sleep: bls !! 1215 blsp1_i2c3_sleep: blsp1-i2c2-sleep {
1566 pins = "gpio4 1216 pins = "gpio47", "gpio48";
1567 function = "g 1217 function = "gpio";
1568 drive-strengt 1218 drive-strength = <2>;
1569 bias-disable; !! 1219 bias-disable = <0>;
1570 }; 1220 };
1571 1221
1572 blsp2_uart3_4pins_def !! 1222 blsp2_uart3_4pins_default: blsp2-uart2-4pins {
1573 pins = "gpio4 1223 pins = "gpio49", "gpio50", "gpio51", "gpio52";
1574 function = "b 1224 function = "blsp_uart9";
1575 drive-strengt 1225 drive-strength = <16>;
1576 bias-disable; 1226 bias-disable;
1577 }; 1227 };
1578 1228
1579 blsp2_uart3_4pins_sle !! 1229 blsp2_uart3_4pins_sleep: blsp2-uart2-4pins-sleep {
1580 pins = "gpio4 1230 pins = "gpio49", "gpio50", "gpio51", "gpio52";
1581 function = "b 1231 function = "blsp_uart9";
1582 drive-strengt 1232 drive-strength = <2>;
1583 bias-disable; 1233 bias-disable;
1584 }; 1234 };
1585 1235
1586 blsp2_i2c3_default: b !! 1236 wcd_intr_default: wcd-intr-default{
1587 pins = "gpio5 <<
1588 function = "b <<
1589 drive-strengt <<
1590 bias-disable; <<
1591 }; <<
1592 <<
1593 blsp2_i2c3_sleep: bls <<
1594 pins = "gpio5 <<
1595 function = "g <<
1596 drive-strengt <<
1597 bias-disable; <<
1598 }; <<
1599 <<
1600 wcd_intr_default: wcd <<
1601 pins = "gpio5 1237 pins = "gpio54";
1602 function = "g 1238 function = "gpio";
1603 drive-strengt 1239 drive-strength = <2>;
1604 bias-pull-dow 1240 bias-pull-down;
>> 1241 input-enable;
1605 }; 1242 };
1606 1243
1607 blsp2_i2c1_default: b !! 1244 blsp2_i2c1_default: blsp2-i2c1 {
1608 pins = "gpio5 1245 pins = "gpio55", "gpio56";
1609 function = "b 1246 function = "blsp_i2c7";
1610 drive-strengt 1247 drive-strength = <16>;
1611 bias-disable; 1248 bias-disable;
1612 }; 1249 };
1613 1250
1614 blsp2_i2c1_sleep: bls !! 1251 blsp2_i2c1_sleep: blsp2-i2c0-sleep {
1615 pins = "gpio5 1252 pins = "gpio55", "gpio56";
1616 function = "g 1253 function = "gpio";
1617 drive-strengt 1254 drive-strength = <2>;
1618 bias-disable; 1255 bias-disable;
1619 }; 1256 };
1620 1257
1621 blsp2_i2c5_default: b !! 1258 blsp2_i2c5_default: blsp2-i2c5 {
1622 pins = "gpio6 1259 pins = "gpio60", "gpio61";
1623 function = "b 1260 function = "blsp_i2c11";
1624 drive-strengt 1261 drive-strength = <2>;
1625 bias-disable; 1262 bias-disable;
1626 }; 1263 };
1627 1264
1628 /* Sleep state for BL 1265 /* Sleep state for BLSP2_I2C5 is missing.. */
1629 1266
1630 cdc_reset_active: cdc !! 1267 cdc_reset_active: cdc-reset-active {
1631 pins = "gpio6 1268 pins = "gpio64";
1632 function = "g 1269 function = "gpio";
1633 drive-strengt 1270 drive-strength = <16>;
1634 bias-pull-dow 1271 bias-pull-down;
1635 output-high; 1272 output-high;
1636 }; 1273 };
1637 1274
1638 cdc_reset_sleep: cdc- !! 1275 cdc_reset_sleep: cdc-reset-sleep {
1639 pins = "gpio6 1276 pins = "gpio64";
1640 function = "g 1277 function = "gpio";
1641 drive-strengt 1278 drive-strength = <16>;
1642 bias-disable; 1279 bias-disable;
1643 output-low; 1280 output-low;
1644 }; 1281 };
1645 1282
1646 blsp2_spi6_default: b !! 1283 blsp2_spi6_default: blsp2-spi5-default {
1647 spi-pins { !! 1284 spi {
1648 pins 1285 pins = "gpio85", "gpio86", "gpio88";
1649 funct 1286 function = "blsp_spi12";
1650 drive 1287 drive-strength = <12>;
1651 bias- 1288 bias-disable;
1652 }; 1289 };
1653 1290
1654 cs-pins { !! 1291 cs {
1655 pins 1292 pins = "gpio87";
1656 funct 1293 function = "gpio";
1657 drive 1294 drive-strength = <16>;
1658 bias- 1295 bias-disable;
1659 outpu 1296 output-high;
1660 }; 1297 };
1661 }; 1298 };
1662 1299
1663 blsp2_spi6_sleep: bls !! 1300 blsp2_spi6_sleep: blsp2-spi5-sleep {
1664 pins = "gpio8 1301 pins = "gpio85", "gpio86", "gpio87", "gpio88";
1665 function = "g 1302 function = "gpio";
1666 drive-strengt 1303 drive-strength = <2>;
1667 bias-pull-dow 1304 bias-pull-down;
1668 }; 1305 };
1669 1306
1670 blsp2_i2c6_default: b !! 1307 blsp2_i2c6_default: blsp2-i2c6 {
1671 pins = "gpio8 1308 pins = "gpio87", "gpio88";
1672 function = "b 1309 function = "blsp_i2c12";
1673 drive-strengt 1310 drive-strength = <16>;
1674 bias-disable; 1311 bias-disable;
1675 }; 1312 };
1676 1313
1677 blsp2_i2c6_sleep: bls !! 1314 blsp2_i2c6_sleep: blsp2-i2c6-sleep {
1678 pins = "gpio8 1315 pins = "gpio87", "gpio88";
1679 function = "g 1316 function = "gpio";
1680 drive-strengt 1317 drive-strength = <2>;
1681 bias-disable; 1318 bias-disable;
1682 }; 1319 };
1683 1320
1684 pcie1_state_on: pcie1 !! 1321 pcie1_state_on: pcie1-state-on {
1685 perst-pins { !! 1322 perst {
1686 pins 1323 pins = "gpio130";
1687 funct 1324 function = "gpio";
1688 drive 1325 drive-strength = <2>;
1689 bias- 1326 bias-pull-down;
1690 }; 1327 };
1691 1328
1692 clkreq-pins { !! 1329 clkreq {
1693 pins 1330 pins = "gpio131";
1694 funct 1331 function = "pci_e1";
1695 drive 1332 drive-strength = <2>;
1696 bias- 1333 bias-pull-up;
1697 }; 1334 };
1698 1335
1699 wake-pins { !! 1336 wake {
1700 pins 1337 pins = "gpio132";
1701 funct 1338 function = "gpio";
1702 drive 1339 drive-strength = <2>;
1703 bias- 1340 bias-pull-down;
1704 }; 1341 };
1705 }; 1342 };
1706 1343
1707 pcie1_state_off: pcie !! 1344 pcie1_state_off: pcie1-state-off {
1708 /* Perst is m 1345 /* Perst is missing? */
1709 clkreq-pins { !! 1346 clkreq {
1710 pins 1347 pins = "gpio131";
1711 funct 1348 function = "gpio";
1712 drive 1349 drive-strength = <2>;
1713 bias- 1350 bias-disable;
1714 }; 1351 };
1715 1352
1716 wake-pins { !! 1353 wake {
1717 pins 1354 pins = "gpio132";
1718 funct 1355 function = "gpio";
1719 drive 1356 drive-strength = <2>;
1720 bias- 1357 bias-disable;
1721 }; 1358 };
1722 }; 1359 };
1723 1360
1724 pcie2_state_on: pcie2 !! 1361 pcie2_state_on: pcie2-state-on {
1725 perst-pins { !! 1362 perst {
1726 pins 1363 pins = "gpio114";
1727 funct 1364 function = "gpio";
1728 drive 1365 drive-strength = <2>;
1729 bias- 1366 bias-pull-down;
1730 }; 1367 };
1731 1368
1732 clkreq-pins { !! 1369 clkreq {
1733 pins 1370 pins = "gpio115";
1734 funct 1371 function = "pci_e2";
1735 drive 1372 drive-strength = <2>;
1736 bias- 1373 bias-pull-up;
1737 }; 1374 };
1738 1375
1739 wake-pins { !! 1376 wake {
1740 pins 1377 pins = "gpio116";
1741 funct 1378 function = "gpio";
1742 drive 1379 drive-strength = <2>;
1743 bias- 1380 bias-pull-down;
1744 }; 1381 };
1745 }; 1382 };
1746 1383
1747 pcie2_state_off: pcie !! 1384 pcie2_state_off: pcie2-state-off {
1748 /* Perst is m 1385 /* Perst is missing? */
1749 clkreq-pins { !! 1386 clkreq {
1750 pins 1387 pins = "gpio115";
1751 funct 1388 function = "gpio";
1752 drive 1389 drive-strength = <2>;
1753 bias- 1390 bias-disable;
1754 }; 1391 };
1755 1392
1756 wake-pins { !! 1393 wake {
1757 pins 1394 pins = "gpio116";
1758 funct 1395 function = "gpio";
1759 drive 1396 drive-strength = <2>;
1760 bias- 1397 bias-disable;
1761 }; 1398 };
1762 }; 1399 };
1763 1400
1764 sdc1_state_on: sdc1-o !! 1401 sdc1_state_on: sdc1-state-on {
1765 clk-pins { !! 1402 clk {
1766 pins 1403 pins = "sdc1_clk";
1767 bias- 1404 bias-disable;
1768 drive 1405 drive-strength = <16>;
1769 }; 1406 };
1770 1407
1771 cmd-pins { !! 1408 cmd {
1772 pins 1409 pins = "sdc1_cmd";
1773 bias- 1410 bias-pull-up;
1774 drive 1411 drive-strength = <10>;
1775 }; 1412 };
1776 1413
1777 data-pins { !! 1414 data {
1778 pins 1415 pins = "sdc1_data";
1779 bias- 1416 bias-pull-up;
1780 drive 1417 drive-strength = <10>;
1781 }; 1418 };
1782 1419
1783 rclk-pins { !! 1420 rclk {
1784 pins 1421 pins = "sdc1_rclk";
1785 bias- 1422 bias-pull-down;
1786 }; 1423 };
1787 }; 1424 };
1788 1425
1789 sdc1_state_off: sdc1- !! 1426 sdc1_state_off: sdc1-state-off {
1790 clk-pins { !! 1427 clk {
1791 pins 1428 pins = "sdc1_clk";
1792 bias- 1429 bias-disable;
1793 drive 1430 drive-strength = <2>;
1794 }; 1431 };
1795 1432
1796 cmd-pins { !! 1433 cmd {
1797 pins 1434 pins = "sdc1_cmd";
1798 bias- 1435 bias-pull-up;
1799 drive 1436 drive-strength = <2>;
1800 }; 1437 };
1801 1438
1802 data-pins { !! 1439 data {
1803 pins 1440 pins = "sdc1_data";
1804 bias- 1441 bias-pull-up;
1805 drive 1442 drive-strength = <2>;
1806 }; 1443 };
1807 1444
1808 rclk-pins { !! 1445 rclk {
1809 pins 1446 pins = "sdc1_rclk";
1810 bias- 1447 bias-pull-down;
1811 }; 1448 };
1812 }; 1449 };
1813 1450
1814 sdc2_state_on: sdc2-o !! 1451 sdc2_state_on: sdc2-clk-on {
1815 clk-pins { !! 1452 clk {
1816 pins 1453 pins = "sdc2_clk";
1817 bias- 1454 bias-disable;
1818 drive 1455 drive-strength = <16>;
1819 }; 1456 };
1820 1457
1821 cmd-pins { !! 1458 cmd {
1822 pins 1459 pins = "sdc2_cmd";
1823 bias- 1460 bias-pull-up;
1824 drive 1461 drive-strength = <10>;
1825 }; 1462 };
1826 1463
1827 data-pins { !! 1464 data {
1828 pins 1465 pins = "sdc2_data";
1829 bias- 1466 bias-pull-up;
1830 drive 1467 drive-strength = <10>;
1831 }; 1468 };
1832 }; 1469 };
1833 1470
1834 sdc2_state_off: sdc2- !! 1471 sdc2_state_off: sdc2-clk-off {
1835 clk-pins { !! 1472 clk {
1836 pins 1473 pins = "sdc2_clk";
1837 bias- 1474 bias-disable;
1838 drive 1475 drive-strength = <2>;
1839 }; 1476 };
1840 1477
1841 cmd-pins { !! 1478 cmd {
1842 pins 1479 pins = "sdc2_cmd";
1843 bias- 1480 bias-pull-up;
1844 drive 1481 drive-strength = <2>;
1845 }; 1482 };
1846 1483
1847 data-pins { !! 1484 data {
1848 pins 1485 pins = "sdc2_data";
1849 bias- 1486 bias-pull-up;
1850 drive 1487 drive-strength = <2>;
1851 }; 1488 };
1852 }; 1489 };
1853 }; 1490 };
1854 1491
1855 sram@290000 { !! 1492 spmi_bus: qcom,spmi@400f000 {
1856 compatible = "qcom,rp <<
1857 reg = <0x00290000 0x1 <<
1858 }; <<
1859 <<
1860 spmi_bus: spmi@400f000 { <<
1861 compatible = "qcom,sp 1493 compatible = "qcom,spmi-pmic-arb";
1862 reg = <0x0400f000 0x1 1494 reg = <0x0400f000 0x1000>,
1863 <0x04400000 0x8 1495 <0x04400000 0x800000>,
1864 <0x04c00000 0x8 1496 <0x04c00000 0x800000>,
1865 <0x05800000 0x2 1497 <0x05800000 0x200000>,
1866 <0x0400a000 0x0 1498 <0x0400a000 0x002100>;
1867 reg-names = "core", " 1499 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1868 interrupt-names = "pe 1500 interrupt-names = "periph_irq";
1869 interrupts = <GIC_SPI 1501 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
1870 qcom,ee = <0>; 1502 qcom,ee = <0>;
1871 qcom,channel = <0>; 1503 qcom,channel = <0>;
1872 #address-cells = <2>; 1504 #address-cells = <2>;
1873 #size-cells = <0>; 1505 #size-cells = <0>;
1874 interrupt-controller; 1506 interrupt-controller;
1875 #interrupt-cells = <4 1507 #interrupt-cells = <4>;
1876 }; 1508 };
1877 1509
1878 bus@0 { !! 1510 agnoc@0 {
1879 power-domains = <&gcc 1511 power-domains = <&gcc AGGRE0_NOC_GDSC>;
1880 compatible = "simple- 1512 compatible = "simple-pm-bus";
1881 #address-cells = <1>; 1513 #address-cells = <1>;
1882 #size-cells = <1>; 1514 #size-cells = <1>;
1883 ranges = <0x0 0x0 0xf !! 1515 ranges;
1884 1516
1885 pcie0: pcie@600000 { 1517 pcie0: pcie@600000 {
1886 compatible = !! 1518 compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
1887 status = "dis 1519 status = "disabled";
1888 power-domains 1520 power-domains = <&gcc PCIE0_GDSC>;
1889 bus-range = < 1521 bus-range = <0x00 0xff>;
1890 num-lanes = < 1522 num-lanes = <1>;
1891 1523
1892 reg = <0x0060 1524 reg = <0x00600000 0x2000>,
1893 <0x0c00 1525 <0x0c000000 0xf1d>,
1894 <0x0c00 1526 <0x0c000f20 0xa8>,
1895 <0x0c10 1527 <0x0c100000 0x100000>;
1896 reg-names = " 1528 reg-names = "parf", "dbi", "elbi","config";
1897 1529
1898 phys = <&pcie 1530 phys = <&pciephy_0>;
1899 phy-names = " 1531 phy-names = "pciephy";
1900 1532
1901 #address-cell 1533 #address-cells = <3>;
1902 #size-cells = 1534 #size-cells = <2>;
1903 ranges = <0x0 !! 1535 ranges = <0x01000000 0x0 0x0c200000 0x0c200000 0x0 0x100000>,
1904 <0x0 !! 1536 <0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>;
1905 1537
1906 device_type = 1538 device_type = "pci";
1907 1539
1908 interrupts = 1540 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
1909 interrupt-nam 1541 interrupt-names = "msi";
1910 #interrupt-ce 1542 #interrupt-cells = <1>;
1911 interrupt-map 1543 interrupt-map-mask = <0 0 0 0x7>;
1912 interrupt-map 1544 interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1913 1545 <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1914 1546 <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1915 1547 <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1916 1548
1917 pinctrl-names 1549 pinctrl-names = "default", "sleep";
1918 pinctrl-0 = < 1550 pinctrl-0 = <&pcie0_state_on>;
1919 pinctrl-1 = < 1551 pinctrl-1 = <&pcie0_state_off>;
1920 1552
1921 linux,pci-dom 1553 linux,pci-domain = <0>;
1922 1554
1923 clocks = <&gc 1555 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
1924 <&gcc 1556 <&gcc GCC_PCIE_0_AUX_CLK>,
1925 <&gcc 1557 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1926 <&gcc 1558 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1927 <&gcc 1559 <&gcc GCC_PCIE_0_SLV_AXI_CLK>;
1928 1560
1929 clock-names = !! 1561 clock-names = "pipe",
1930 1562 "aux",
1931 1563 "cfg",
1932 1564 "bus_master",
1933 1565 "bus_slave";
1934 1566
1935 pcie@0 { <<
1936 devic <<
1937 reg = <<
1938 bus-r <<
1939 <<
1940 #addr <<
1941 #size <<
1942 range <<
1943 }; <<
1944 }; 1567 };
1945 1568
1946 pcie1: pcie@608000 { 1569 pcie1: pcie@608000 {
1947 compatible = !! 1570 compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
1948 power-domains 1571 power-domains = <&gcc PCIE1_GDSC>;
1949 bus-range = < 1572 bus-range = <0x00 0xff>;
1950 num-lanes = < 1573 num-lanes = <1>;
1951 1574
1952 status = "dis !! 1575 status = "disabled";
1953 1576
1954 reg = <0x0060 1577 reg = <0x00608000 0x2000>,
1955 <0x0d00 1578 <0x0d000000 0xf1d>,
1956 <0x0d00 1579 <0x0d000f20 0xa8>,
1957 <0x0d10 1580 <0x0d100000 0x100000>;
1958 1581
1959 reg-names = " 1582 reg-names = "parf", "dbi", "elbi","config";
1960 1583
1961 phys = <&pcie 1584 phys = <&pciephy_1>;
1962 phy-names = " 1585 phy-names = "pciephy";
1963 1586
1964 #address-cell 1587 #address-cells = <3>;
1965 #size-cells = 1588 #size-cells = <2>;
1966 ranges = <0x0 !! 1589 ranges = <0x01000000 0x0 0x0d200000 0x0d200000 0x0 0x100000>,
1967 <0x0 !! 1590 <0x02000000 0x0 0x0d300000 0x0d300000 0x0 0xd00000>;
1968 1591
1969 device_type = 1592 device_type = "pci";
1970 1593
1971 interrupts = 1594 interrupts = <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>;
1972 interrupt-nam 1595 interrupt-names = "msi";
1973 #interrupt-ce 1596 #interrupt-cells = <1>;
1974 interrupt-map 1597 interrupt-map-mask = <0 0 0 0x7>;
1975 interrupt-map 1598 interrupt-map = <0 0 0 1 &intc 0 272 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1976 1599 <0 0 0 2 &intc 0 273 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1977 1600 <0 0 0 3 &intc 0 274 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1978 1601 <0 0 0 4 &intc 0 275 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1979 1602
1980 pinctrl-names 1603 pinctrl-names = "default", "sleep";
1981 pinctrl-0 = < 1604 pinctrl-0 = <&pcie1_state_on>;
1982 pinctrl-1 = < 1605 pinctrl-1 = <&pcie1_state_off>;
1983 1606
1984 linux,pci-dom 1607 linux,pci-domain = <1>;
1985 1608
1986 clocks = <&gc 1609 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
1987 <&gcc 1610 <&gcc GCC_PCIE_1_AUX_CLK>,
1988 <&gcc 1611 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1989 <&gcc 1612 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
1990 <&gcc 1613 <&gcc GCC_PCIE_1_SLV_AXI_CLK>;
1991 1614
1992 clock-names = !! 1615 clock-names = "pipe",
1993 1616 "aux",
1994 1617 "cfg",
1995 1618 "bus_master",
1996 1619 "bus_slave";
1997 <<
1998 pcie@0 { <<
1999 devic <<
2000 reg = <<
2001 bus-r <<
2002 <<
2003 #addr <<
2004 #size <<
2005 range <<
2006 }; <<
2007 }; 1620 };
2008 1621
2009 pcie2: pcie@610000 { 1622 pcie2: pcie@610000 {
2010 compatible = !! 1623 compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
2011 power-domains 1624 power-domains = <&gcc PCIE2_GDSC>;
2012 bus-range = < 1625 bus-range = <0x00 0xff>;
2013 num-lanes = < 1626 num-lanes = <1>;
2014 status = "dis 1627 status = "disabled";
2015 reg = <0x0061 1628 reg = <0x00610000 0x2000>,
2016 <0x0e00 1629 <0x0e000000 0xf1d>,
2017 <0x0e00 1630 <0x0e000f20 0xa8>,
2018 <0x0e10 1631 <0x0e100000 0x100000>;
2019 1632
2020 reg-names = " 1633 reg-names = "parf", "dbi", "elbi","config";
2021 1634
2022 phys = <&pcie 1635 phys = <&pciephy_2>;
2023 phy-names = " 1636 phy-names = "pciephy";
2024 1637
2025 #address-cell 1638 #address-cells = <3>;
2026 #size-cells = 1639 #size-cells = <2>;
2027 ranges = <0x0 !! 1640 ranges = <0x01000000 0x0 0x0e200000 0x0e200000 0x0 0x100000>,
2028 <0x0 !! 1641 <0x02000000 0x0 0x0e300000 0x0e300000 0x0 0x1d00000>;
2029 1642
2030 device_type = 1643 device_type = "pci";
2031 1644
2032 interrupts = 1645 interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
2033 interrupt-nam 1646 interrupt-names = "msi";
2034 #interrupt-ce 1647 #interrupt-cells = <1>;
2035 interrupt-map 1648 interrupt-map-mask = <0 0 0 0x7>;
2036 interrupt-map 1649 interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2037 1650 <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2038 1651 <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2039 1652 <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2040 1653
2041 pinctrl-names 1654 pinctrl-names = "default", "sleep";
2042 pinctrl-0 = < 1655 pinctrl-0 = <&pcie2_state_on>;
2043 pinctrl-1 = < 1656 pinctrl-1 = <&pcie2_state_off>;
2044 1657
2045 linux,pci-dom 1658 linux,pci-domain = <2>;
2046 clocks = <&gc 1659 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,
2047 <&gcc 1660 <&gcc GCC_PCIE_2_AUX_CLK>,
2048 <&gcc 1661 <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
2049 <&gcc 1662 <&gcc GCC_PCIE_2_MSTR_AXI_CLK>,
2050 <&gcc 1663 <&gcc GCC_PCIE_2_SLV_AXI_CLK>;
2051 1664
2052 clock-names = !! 1665 clock-names = "pipe",
2053 1666 "aux",
2054 1667 "cfg",
2055 1668 "bus_master",
2056 1669 "bus_slave";
2057 <<
2058 pcie@0 { <<
2059 devic <<
2060 reg = <<
2061 bus-r <<
2062 <<
2063 #addr <<
2064 #size <<
2065 range <<
2066 }; <<
2067 }; 1670 };
2068 }; 1671 };
2069 1672
2070 ufshc: ufshc@624000 { 1673 ufshc: ufshc@624000 {
2071 compatible = "qcom,ms !! 1674 compatible = "qcom,ufshc";
2072 "jedec,u <<
2073 reg = <0x00624000 0x2 1675 reg = <0x00624000 0x2500>;
2074 interrupts = <GIC_SPI 1676 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
2075 1677
2076 phys = <&ufsphy>; !! 1678 phys = <&ufsphy_lane>;
2077 phy-names = "ufsphy"; 1679 phy-names = "ufsphy";
2078 1680
2079 power-domains = <&gcc 1681 power-domains = <&gcc UFS_GDSC>;
2080 1682
2081 clock-names = 1683 clock-names =
>> 1684 "core_clk_src",
2082 "core_clk", 1685 "core_clk",
2083 "bus_clk", 1686 "bus_clk",
2084 "bus_aggr_clk 1687 "bus_aggr_clk",
2085 "iface_clk", 1688 "iface_clk",
>> 1689 "core_clk_unipro_src",
2086 "core_clk_uni 1690 "core_clk_unipro",
2087 "core_clk_ice 1691 "core_clk_ice",
2088 "ref_clk", 1692 "ref_clk",
2089 "tx_lane0_syn 1693 "tx_lane0_sync_clk",
2090 "rx_lane0_syn 1694 "rx_lane0_sync_clk";
2091 clocks = 1695 clocks =
>> 1696 <&gcc UFS_AXI_CLK_SRC>,
2092 <&gcc GCC_UFS 1697 <&gcc GCC_UFS_AXI_CLK>,
2093 <&gcc GCC_SYS 1698 <&gcc GCC_SYS_NOC_UFS_AXI_CLK>,
2094 <&gcc GCC_AGG 1699 <&gcc GCC_AGGRE2_UFS_AXI_CLK>,
2095 <&gcc GCC_UFS 1700 <&gcc GCC_UFS_AHB_CLK>,
>> 1701 <&gcc UFS_ICE_CORE_CLK_SRC>,
2096 <&gcc GCC_UFS 1702 <&gcc GCC_UFS_UNIPRO_CORE_CLK>,
2097 <&gcc GCC_UFS 1703 <&gcc GCC_UFS_ICE_CORE_CLK>,
2098 <&rpmcc RPM_S 1704 <&rpmcc RPM_SMD_LN_BB_CLK>,
2099 <&gcc GCC_UFS 1705 <&gcc GCC_UFS_TX_SYMBOL_0_CLK>,
2100 <&gcc GCC_UFS 1706 <&gcc GCC_UFS_RX_SYMBOL_0_CLK>;
2101 freq-table-hz = 1707 freq-table-hz =
2102 <100000000 20 1708 <100000000 200000000>,
2103 <0 0>, 1709 <0 0>,
2104 <0 0>, 1710 <0 0>,
2105 <0 0>, 1711 <0 0>,
2106 <75000000 150 !! 1712 <0 0>,
2107 <150000000 30 1713 <150000000 300000000>,
2108 <0 0>, 1714 <0 0>,
2109 <0 0>, 1715 <0 0>,
>> 1716 <0 0>,
>> 1717 <0 0>,
2110 <0 0>; 1718 <0 0>;
2111 1719
2112 interconnects = <&a2n <<
2113 <&bim <<
2114 interconnect-names = <<
2115 <<
2116 lanes-per-direction = 1720 lanes-per-direction = <1>;
2117 #reset-cells = <1>; 1721 #reset-cells = <1>;
2118 status = "disabled"; 1722 status = "disabled";
>> 1723
>> 1724 ufs_variant {
>> 1725 compatible = "qcom,ufs_variant";
>> 1726 };
2119 }; 1727 };
2120 1728
2121 ufsphy: phy@627000 { 1729 ufsphy: phy@627000 {
2122 compatible = "qcom,ms 1730 compatible = "qcom,msm8996-qmp-ufs-phy";
2123 reg = <0x00627000 0x1 !! 1731 reg = <0x00627000 0x1c4>;
>> 1732 #address-cells = <1>;
>> 1733 #size-cells = <1>;
>> 1734 ranges;
2124 1735
2125 clocks = <&rpmcc RPM_ !! 1736 clocks = <&gcc GCC_UFS_CLKREF_CLK>;
2126 clock-names = "ref", !! 1737 clock-names = "ref";
2127 1738
2128 resets = <&ufshc 0>; 1739 resets = <&ufshc 0>;
2129 reset-names = "ufsphy 1740 reset-names = "ufsphy";
2130 <<
2131 #clock-cells = <1>; <<
2132 #phy-cells = <0>; <<
2133 <<
2134 status = "disabled"; 1741 status = "disabled";
>> 1742
>> 1743 ufsphy_lane: lanes@627400 {
>> 1744 reg = <0x627400 0x12c>,
>> 1745 <0x627600 0x200>,
>> 1746 <0x627c00 0x1b4>;
>> 1747 #phy-cells = <0>;
>> 1748 };
2135 }; 1749 };
2136 1750
2137 camss: camss@a34000 { !! 1751 camss: camss@a00000 {
2138 compatible = "qcom,ms 1752 compatible = "qcom,msm8996-camss";
2139 reg = <0x00a34000 0x1 1753 reg = <0x00a34000 0x1000>,
2140 <0x00a00030 0x4 1754 <0x00a00030 0x4>,
2141 <0x00a35000 0x1 1755 <0x00a35000 0x1000>,
2142 <0x00a00038 0x4 1756 <0x00a00038 0x4>,
2143 <0x00a36000 0x1 1757 <0x00a36000 0x1000>,
2144 <0x00a00040 0x4 1758 <0x00a00040 0x4>,
2145 <0x00a30000 0x1 1759 <0x00a30000 0x100>,
2146 <0x00a30400 0x1 1760 <0x00a30400 0x100>,
2147 <0x00a30800 0x1 1761 <0x00a30800 0x100>,
2148 <0x00a30c00 0x1 1762 <0x00a30c00 0x100>,
2149 <0x00a31000 0x5 1763 <0x00a31000 0x500>,
2150 <0x00a00020 0x1 1764 <0x00a00020 0x10>,
2151 <0x00a10000 0x1 1765 <0x00a10000 0x1000>,
2152 <0x00a14000 0x1 1766 <0x00a14000 0x1000>;
2153 reg-names = "csiphy0" 1767 reg-names = "csiphy0",
2154 "csiphy0_clk_ 1768 "csiphy0_clk_mux",
2155 "csiphy1", 1769 "csiphy1",
2156 "csiphy1_clk_ 1770 "csiphy1_clk_mux",
2157 "csiphy2", 1771 "csiphy2",
2158 "csiphy2_clk_ 1772 "csiphy2_clk_mux",
2159 "csid0", 1773 "csid0",
2160 "csid1", 1774 "csid1",
2161 "csid2", 1775 "csid2",
2162 "csid3", 1776 "csid3",
2163 "ispif", 1777 "ispif",
2164 "csi_clk_mux" 1778 "csi_clk_mux",
2165 "vfe0", 1779 "vfe0",
2166 "vfe1"; 1780 "vfe1";
2167 interrupts = <GIC_SPI 1781 interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
2168 <GIC_SPI 79 I 1782 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
2169 <GIC_SPI 80 I 1783 <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>,
2170 <GIC_SPI 296 1784 <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>,
2171 <GIC_SPI 297 1785 <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>,
2172 <GIC_SPI 298 1786 <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>,
2173 <GIC_SPI 299 1787 <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>,
2174 <GIC_SPI 309 1788 <GIC_SPI 309 IRQ_TYPE_EDGE_RISING>,
2175 <GIC_SPI 314 1789 <GIC_SPI 314 IRQ_TYPE_EDGE_RISING>,
2176 <GIC_SPI 315 1790 <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>;
2177 interrupt-names = "cs 1791 interrupt-names = "csiphy0",
2178 "csiphy1", 1792 "csiphy1",
2179 "csiphy2", 1793 "csiphy2",
2180 "csid0", 1794 "csid0",
2181 "csid1", 1795 "csid1",
2182 "csid2", 1796 "csid2",
2183 "csid3", 1797 "csid3",
2184 "ispif", 1798 "ispif",
2185 "vfe0", 1799 "vfe0",
2186 "vfe1"; 1800 "vfe1";
2187 power-domains = <&mmc 1801 power-domains = <&mmcc VFE0_GDSC>,
2188 <&mmc 1802 <&mmcc VFE1_GDSC>;
2189 clocks = <&mmcc CAMSS 1803 clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
2190 <&mmcc CAMSS_ 1804 <&mmcc CAMSS_ISPIF_AHB_CLK>,
2191 <&mmcc CAMSS_ 1805 <&mmcc CAMSS_CSI0PHYTIMER_CLK>,
2192 <&mmcc CAMSS_ 1806 <&mmcc CAMSS_CSI1PHYTIMER_CLK>,
2193 <&mmcc CAMSS_ 1807 <&mmcc CAMSS_CSI2PHYTIMER_CLK>,
2194 <&mmcc CAMSS_ 1808 <&mmcc CAMSS_CSI0_AHB_CLK>,
2195 <&mmcc CAMSS_ 1809 <&mmcc CAMSS_CSI0_CLK>,
2196 <&mmcc CAMSS_ 1810 <&mmcc CAMSS_CSI0PHY_CLK>,
2197 <&mmcc CAMSS_ 1811 <&mmcc CAMSS_CSI0PIX_CLK>,
2198 <&mmcc CAMSS_ 1812 <&mmcc CAMSS_CSI0RDI_CLK>,
2199 <&mmcc CAMSS_ 1813 <&mmcc CAMSS_CSI1_AHB_CLK>,
2200 <&mmcc CAMSS_ 1814 <&mmcc CAMSS_CSI1_CLK>,
2201 <&mmcc CAMSS_ 1815 <&mmcc CAMSS_CSI1PHY_CLK>,
2202 <&mmcc CAMSS_ 1816 <&mmcc CAMSS_CSI1PIX_CLK>,
2203 <&mmcc CAMSS_ 1817 <&mmcc CAMSS_CSI1RDI_CLK>,
2204 <&mmcc CAMSS_ 1818 <&mmcc CAMSS_CSI2_AHB_CLK>,
2205 <&mmcc CAMSS_ 1819 <&mmcc CAMSS_CSI2_CLK>,
2206 <&mmcc CAMSS_ 1820 <&mmcc CAMSS_CSI2PHY_CLK>,
2207 <&mmcc CAMSS_ 1821 <&mmcc CAMSS_CSI2PIX_CLK>,
2208 <&mmcc CAMSS_ 1822 <&mmcc CAMSS_CSI2RDI_CLK>,
2209 <&mmcc CAMSS_ 1823 <&mmcc CAMSS_CSI3_AHB_CLK>,
2210 <&mmcc CAMSS_ 1824 <&mmcc CAMSS_CSI3_CLK>,
2211 <&mmcc CAMSS_ 1825 <&mmcc CAMSS_CSI3PHY_CLK>,
2212 <&mmcc CAMSS_ 1826 <&mmcc CAMSS_CSI3PIX_CLK>,
2213 <&mmcc CAMSS_ 1827 <&mmcc CAMSS_CSI3RDI_CLK>,
2214 <&mmcc CAMSS_ 1828 <&mmcc CAMSS_AHB_CLK>,
2215 <&mmcc CAMSS_ 1829 <&mmcc CAMSS_VFE0_CLK>,
2216 <&mmcc CAMSS_ 1830 <&mmcc CAMSS_CSI_VFE0_CLK>,
2217 <&mmcc CAMSS_ 1831 <&mmcc CAMSS_VFE0_AHB_CLK>,
2218 <&mmcc CAMSS_ 1832 <&mmcc CAMSS_VFE0_STREAM_CLK>,
2219 <&mmcc CAMSS_ 1833 <&mmcc CAMSS_VFE1_CLK>,
2220 <&mmcc CAMSS_ 1834 <&mmcc CAMSS_CSI_VFE1_CLK>,
2221 <&mmcc CAMSS_ 1835 <&mmcc CAMSS_VFE1_AHB_CLK>,
2222 <&mmcc CAMSS_ 1836 <&mmcc CAMSS_VFE1_STREAM_CLK>,
2223 <&mmcc CAMSS_ 1837 <&mmcc CAMSS_VFE_AHB_CLK>,
2224 <&mmcc CAMSS_ 1838 <&mmcc CAMSS_VFE_AXI_CLK>;
2225 clock-names = "top_ah 1839 clock-names = "top_ahb",
2226 "ispif_ahb", 1840 "ispif_ahb",
2227 "csiphy0_time 1841 "csiphy0_timer",
2228 "csiphy1_time 1842 "csiphy1_timer",
2229 "csiphy2_time 1843 "csiphy2_timer",
2230 "csi0_ahb", 1844 "csi0_ahb",
2231 "csi0", 1845 "csi0",
2232 "csi0_phy", 1846 "csi0_phy",
2233 "csi0_pix", 1847 "csi0_pix",
2234 "csi0_rdi", 1848 "csi0_rdi",
2235 "csi1_ahb", 1849 "csi1_ahb",
2236 "csi1", 1850 "csi1",
2237 "csi1_phy", 1851 "csi1_phy",
2238 "csi1_pix", 1852 "csi1_pix",
2239 "csi1_rdi", 1853 "csi1_rdi",
2240 "csi2_ahb", 1854 "csi2_ahb",
2241 "csi2", 1855 "csi2",
2242 "csi2_phy", 1856 "csi2_phy",
2243 "csi2_pix", 1857 "csi2_pix",
2244 "csi2_rdi", 1858 "csi2_rdi",
2245 "csi3_ahb", 1859 "csi3_ahb",
2246 "csi3", 1860 "csi3",
2247 "csi3_phy", 1861 "csi3_phy",
2248 "csi3_pix", 1862 "csi3_pix",
2249 "csi3_rdi", 1863 "csi3_rdi",
2250 "ahb", 1864 "ahb",
2251 "vfe0", 1865 "vfe0",
2252 "csi_vfe0", 1866 "csi_vfe0",
2253 "vfe0_ahb", 1867 "vfe0_ahb",
2254 "vfe0_stream" 1868 "vfe0_stream",
2255 "vfe1", 1869 "vfe1",
2256 "csi_vfe1", 1870 "csi_vfe1",
2257 "vfe1_ahb", 1871 "vfe1_ahb",
2258 "vfe1_stream" 1872 "vfe1_stream",
2259 "vfe_ahb", 1873 "vfe_ahb",
2260 "vfe_axi"; 1874 "vfe_axi";
2261 iommus = <&vfe_smmu 0 1875 iommus = <&vfe_smmu 0>,
2262 <&vfe_smmu 1 1876 <&vfe_smmu 1>,
2263 <&vfe_smmu 2 1877 <&vfe_smmu 2>,
2264 <&vfe_smmu 3 1878 <&vfe_smmu 3>;
2265 status = "disabled"; 1879 status = "disabled";
2266 ports { 1880 ports {
2267 #address-cell 1881 #address-cells = <1>;
2268 #size-cells = 1882 #size-cells = <0>;
2269 }; 1883 };
2270 }; 1884 };
2271 1885
2272 cci: cci@a0c000 { 1886 cci: cci@a0c000 {
2273 compatible = "qcom,ms 1887 compatible = "qcom,msm8996-cci";
2274 #address-cells = <1>; 1888 #address-cells = <1>;
2275 #size-cells = <0>; 1889 #size-cells = <0>;
2276 reg = <0xa0c000 0x100 1890 reg = <0xa0c000 0x1000>;
2277 interrupts = <GIC_SPI 1891 interrupts = <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>;
2278 power-domains = <&mmc 1892 power-domains = <&mmcc CAMSS_GDSC>;
2279 clocks = <&mmcc CAMSS 1893 clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
2280 <&mmcc CAMSS 1894 <&mmcc CAMSS_CCI_AHB_CLK>,
2281 <&mmcc CAMSS 1895 <&mmcc CAMSS_CCI_CLK>,
2282 <&mmcc CAMSS 1896 <&mmcc CAMSS_AHB_CLK>;
2283 clock-names = "camss_ 1897 clock-names = "camss_top_ahb",
2284 "cci_ah 1898 "cci_ahb",
2285 "cci", 1899 "cci",
2286 "camss_ 1900 "camss_ahb";
2287 assigned-clocks = <&m 1901 assigned-clocks = <&mmcc CAMSS_CCI_AHB_CLK>,
2288 <&m 1902 <&mmcc CAMSS_CCI_CLK>;
2289 assigned-clock-rates 1903 assigned-clock-rates = <80000000>, <37500000>;
2290 pinctrl-names = "defa 1904 pinctrl-names = "default";
2291 pinctrl-0 = <&cci0_de 1905 pinctrl-0 = <&cci0_default &cci1_default>;
2292 status = "disabled"; 1906 status = "disabled";
2293 1907
2294 cci_i2c0: i2c-bus@0 { 1908 cci_i2c0: i2c-bus@0 {
2295 reg = <0>; 1909 reg = <0>;
2296 clock-frequen 1910 clock-frequency = <400000>;
2297 #address-cell 1911 #address-cells = <1>;
2298 #size-cells = 1912 #size-cells = <0>;
2299 }; 1913 };
2300 1914
2301 cci_i2c1: i2c-bus@1 { 1915 cci_i2c1: i2c-bus@1 {
2302 reg = <1>; 1916 reg = <1>;
2303 clock-frequen 1917 clock-frequency = <400000>;
2304 #address-cell 1918 #address-cells = <1>;
2305 #size-cells = 1919 #size-cells = <0>;
2306 }; 1920 };
2307 }; 1921 };
2308 1922
2309 adreno_smmu: iommu@b40000 { 1923 adreno_smmu: iommu@b40000 {
2310 compatible = "qcom,ms 1924 compatible = "qcom,msm8996-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
2311 reg = <0x00b40000 0x1 1925 reg = <0x00b40000 0x10000>;
2312 1926
2313 #global-interrupts = 1927 #global-interrupts = <1>;
2314 interrupts = <GIC_SPI 1928 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
2315 <GIC_SPI 1929 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
2316 <GIC_SPI 1930 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
2317 #iommu-cells = <1>; 1931 #iommu-cells = <1>;
2318 1932
2319 clocks = <&gcc GCC_MM !! 1933 clocks = <&mmcc GPU_AHB_CLK>,
2320 <&mmcc GPU_A !! 1934 <&gcc GCC_MMSS_BIMC_GFX_CLK>;
2321 clock-names = "bus", !! 1935 clock-names = "iface", "bus";
2322 1936
2323 power-domains = <&mmc 1937 power-domains = <&mmcc GPU_GDSC>;
2324 }; 1938 };
2325 1939
2326 venus: video-codec@c00000 { 1940 venus: video-codec@c00000 {
2327 compatible = "qcom,ms 1941 compatible = "qcom,msm8996-venus";
2328 reg = <0x00c00000 0xf 1942 reg = <0x00c00000 0xff000>;
2329 interrupts = <GIC_SPI 1943 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
2330 power-domains = <&mmc 1944 power-domains = <&mmcc VENUS_GDSC>;
2331 clocks = <&mmcc VIDEO 1945 clocks = <&mmcc VIDEO_CORE_CLK>,
2332 <&mmcc VIDEO 1946 <&mmcc VIDEO_AHB_CLK>,
2333 <&mmcc VIDEO 1947 <&mmcc VIDEO_AXI_CLK>,
2334 <&mmcc VIDEO 1948 <&mmcc VIDEO_MAXI_CLK>;
2335 clock-names = "core", 1949 clock-names = "core", "iface", "bus", "mbus";
2336 interconnects = <&mno <<
2337 <&bim <<
2338 interconnect-names = <<
2339 iommus = <&venus_smmu 1950 iommus = <&venus_smmu 0x00>,
2340 <&venus_smmu 1951 <&venus_smmu 0x01>,
2341 <&venus_smmu 1952 <&venus_smmu 0x0a>,
2342 <&venus_smmu 1953 <&venus_smmu 0x07>,
2343 <&venus_smmu 1954 <&venus_smmu 0x0e>,
2344 <&venus_smmu 1955 <&venus_smmu 0x0f>,
2345 <&venus_smmu 1956 <&venus_smmu 0x08>,
2346 <&venus_smmu 1957 <&venus_smmu 0x09>,
2347 <&venus_smmu 1958 <&venus_smmu 0x0b>,
2348 <&venus_smmu 1959 <&venus_smmu 0x0c>,
2349 <&venus_smmu 1960 <&venus_smmu 0x0d>,
2350 <&venus_smmu 1961 <&venus_smmu 0x10>,
2351 <&venus_smmu 1962 <&venus_smmu 0x11>,
2352 <&venus_smmu 1963 <&venus_smmu 0x21>,
2353 <&venus_smmu 1964 <&venus_smmu 0x28>,
2354 <&venus_smmu 1965 <&venus_smmu 0x29>,
2355 <&venus_smmu 1966 <&venus_smmu 0x2b>,
2356 <&venus_smmu 1967 <&venus_smmu 0x2c>,
2357 <&venus_smmu 1968 <&venus_smmu 0x2d>,
2358 <&venus_smmu 1969 <&venus_smmu 0x31>;
2359 memory-region = <&ven !! 1970 memory-region = <&venus_region>;
2360 status = "disabled"; 1971 status = "disabled";
2361 1972
2362 video-decoder { 1973 video-decoder {
2363 compatible = 1974 compatible = "venus-decoder";
2364 clocks = <&mm 1975 clocks = <&mmcc VIDEO_SUBCORE0_CLK>;
2365 clock-names = 1976 clock-names = "core";
2366 power-domains 1977 power-domains = <&mmcc VENUS_CORE0_GDSC>;
2367 }; 1978 };
2368 1979
2369 video-encoder { 1980 video-encoder {
2370 compatible = 1981 compatible = "venus-encoder";
2371 clocks = <&mm 1982 clocks = <&mmcc VIDEO_SUBCORE1_CLK>;
2372 clock-names = 1983 clock-names = "core";
2373 power-domains 1984 power-domains = <&mmcc VENUS_CORE1_GDSC>;
2374 }; 1985 };
2375 }; 1986 };
2376 1987
2377 mdp_smmu: iommu@d00000 { 1988 mdp_smmu: iommu@d00000 {
2378 compatible = "qcom,ms 1989 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2379 reg = <0x00d00000 0x1 1990 reg = <0x00d00000 0x10000>;
2380 1991
2381 #global-interrupts = 1992 #global-interrupts = <1>;
2382 interrupts = <GIC_SPI 1993 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
2383 <GIC_SPI 1994 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
2384 <GIC_SPI 1995 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
2385 #iommu-cells = <1>; 1996 #iommu-cells = <1>;
2386 clocks = <&mmcc SMMU_ !! 1997 clocks = <&mmcc SMMU_MDP_AHB_CLK>,
2387 <&mmcc SMMU_ !! 1998 <&mmcc SMMU_MDP_AXI_CLK>;
2388 clock-names = "bus", !! 1999 clock-names = "iface", "bus";
2389 2000
2390 power-domains = <&mmc 2001 power-domains = <&mmcc MDSS_GDSC>;
2391 }; 2002 };
2392 2003
2393 venus_smmu: iommu@d40000 { 2004 venus_smmu: iommu@d40000 {
2394 compatible = "qcom,ms 2005 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2395 reg = <0x00d40000 0x2 2006 reg = <0x00d40000 0x20000>;
2396 #global-interrupts = 2007 #global-interrupts = <1>;
2397 interrupts = <GIC_SPI 2008 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>,
2398 <GIC_SPI 2009 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
2399 <GIC_SPI 2010 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
2400 <GIC_SPI 2011 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
2401 <GIC_SPI 2012 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
2402 <GIC_SPI 2013 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
2403 <GIC_SPI 2014 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
2404 <GIC_SPI 2015 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
2405 power-domains = <&mmc 2016 power-domains = <&mmcc MMAGIC_VIDEO_GDSC>;
2406 clocks = <&mmcc SMMU_ !! 2017 clocks = <&mmcc SMMU_VIDEO_AHB_CLK>,
2407 <&mmcc SMMU_ !! 2018 <&mmcc SMMU_VIDEO_AXI_CLK>;
2408 clock-names = "bus", !! 2019 clock-names = "iface", "bus";
2409 #iommu-cells = <1>; 2020 #iommu-cells = <1>;
2410 status = "okay"; 2021 status = "okay";
2411 }; 2022 };
2412 2023
2413 vfe_smmu: iommu@da0000 { 2024 vfe_smmu: iommu@da0000 {
2414 compatible = "qcom,ms 2025 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2415 reg = <0x00da0000 0x1 2026 reg = <0x00da0000 0x10000>;
2416 2027
2417 #global-interrupts = 2028 #global-interrupts = <1>;
2418 interrupts = <GIC_SPI 2029 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
2419 <GIC_SPI 2030 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
2420 <GIC_SPI 2031 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
2421 power-domains = <&mmc 2032 power-domains = <&mmcc MMAGIC_CAMSS_GDSC>;
2422 clocks = <&mmcc SMMU_ !! 2033 clocks = <&mmcc SMMU_VFE_AHB_CLK>,
2423 <&mmcc SMMU_ !! 2034 <&mmcc SMMU_VFE_AXI_CLK>;
2424 clock-names = "bus", !! 2035 clock-names = "iface",
>> 2036 "bus";
2425 #iommu-cells = <1>; 2037 #iommu-cells = <1>;
2426 }; 2038 };
2427 2039
2428 lpass_q6_smmu: iommu@1600000 2040 lpass_q6_smmu: iommu@1600000 {
2429 compatible = "qcom,ms 2041 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2430 reg = <0x01600000 0x2 2042 reg = <0x01600000 0x20000>;
2431 #iommu-cells = <1>; 2043 #iommu-cells = <1>;
2432 power-domains = <&gcc 2044 power-domains = <&gcc HLOS1_VOTE_LPASS_CORE_GDSC>;
2433 2045
2434 #global-interrupts = 2046 #global-interrupts = <1>;
2435 interrupts = <GIC_SPI 2047 interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
2436 <GIC_SPI 226 2048 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,
2437 <GIC_SPI 393 2049 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
2438 <GIC_SPI 394 2050 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
2439 <GIC_SPI 395 2051 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
2440 <GIC_SPI 396 2052 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
2441 <GIC_SPI 397 2053 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
2442 <GIC_SPI 398 2054 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
2443 <GIC_SPI 399 2055 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
2444 <GIC_SPI 400 2056 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
2445 <GIC_SPI 401 2057 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
2446 <GIC_SPI 402 2058 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
2447 <GIC_SPI 403 2059 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>;
2448 2060
2449 clocks = <&gcc GCC_HL !! 2061 clocks = <&gcc GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK>,
2450 <&gcc GCC_HL !! 2062 <&gcc GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>;
2451 clock-names = "bus", !! 2063 clock-names = "iface", "bus";
2452 }; <<
2453 <<
2454 slpi_pil: remoteproc@1c00000 <<
2455 compatible = "qcom,ms <<
2456 reg = <0x01c00000 0x4 <<
2457 <<
2458 interrupts-extended = <<
2459 <<
2460 <<
2461 <<
2462 <<
2463 interrupt-names = "wd <<
2464 "fa <<
2465 "re <<
2466 "ha <<
2467 "st <<
2468 <<
2469 clocks = <&xo_board>; <<
2470 clock-names = "xo"; <<
2471 <<
2472 memory-region = <&slp <<
2473 <<
2474 qcom,smem-states = <& <<
2475 qcom,smem-state-names <<
2476 <<
2477 power-domains = <&rpm <<
2478 power-domain-names = <<
2479 <<
2480 status = "disabled"; <<
2481 <<
2482 glink-edge { <<
2483 interrupts = <<
2484 label = "dsps <<
2485 qcom,remote-p <<
2486 mboxes = <&ap <<
2487 }; <<
2488 <<
2489 smd-edge { <<
2490 interrupts = <<
2491 <<
2492 label = "dsps <<
2493 mboxes = <&ap <<
2494 qcom,smd-edge <<
2495 qcom,remote-p <<
2496 }; <<
2497 }; <<
2498 <<
2499 mss_pil: remoteproc@2080000 { <<
2500 compatible = "qcom,ms <<
2501 reg = <0x2080000 0x10 <<
2502 <0x2180000 0x02 <<
2503 reg-names = "qdsp6", <<
2504 <<
2505 interrupts-extended = <<
2506 <<
2507 <<
2508 <<
2509 <<
2510 <<
2511 interrupt-names = "wd <<
2512 "ha <<
2513 "sh <<
2514 <<
2515 clocks = <&gcc GCC_MS <<
2516 <&gcc GCC_MS <<
2517 <&gcc GCC_BO <<
2518 <&xo_board>, <<
2519 <&gcc GCC_MS <<
2520 <&gcc GCC_MS <<
2521 <&gcc GCC_MS <<
2522 <&rpmcc RPM_ <<
2523 clock-names = "iface" <<
2524 "bus", <<
2525 "mem", <<
2526 "xo", <<
2527 "gpll0_ <<
2528 "snoc_a <<
2529 "mnoc_a <<
2530 "qdss"; <<
2531 <<
2532 resets = <&gcc GCC_MS <<
2533 reset-names = "mss_re <<
2534 <<
2535 power-domains = <&rpm <<
2536 <&rpm <<
2537 power-domain-names = <<
2538 <<
2539 qcom,smem-states = <& <<
2540 qcom,smem-state-names <<
2541 <<
2542 qcom,halt-regs = <&tc <<
2543 <<
2544 status = "disabled"; <<
2545 <<
2546 mba { <<
2547 memory-region <<
2548 }; <<
2549 <<
2550 mpss { <<
2551 memory-region <<
2552 }; <<
2553 <<
2554 metadata { <<
2555 memory-region <<
2556 }; <<
2557 <<
2558 glink-edge { <<
2559 interrupts = <<
2560 label = "mode <<
2561 qcom,remote-p <<
2562 mboxes = <&ap <<
2563 }; <<
2564 <<
2565 smd-edge { <<
2566 interrupts = <<
2567 <<
2568 label = "mpss <<
2569 mboxes = <&ap <<
2570 qcom,smd-edge <<
2571 qcom,remote-p <<
2572 }; <<
2573 }; 2064 };
2574 2065
2575 stm@3002000 { 2066 stm@3002000 {
2576 compatible = "arm,cor 2067 compatible = "arm,coresight-stm", "arm,primecell";
2577 reg = <0x3002000 0x10 2068 reg = <0x3002000 0x1000>,
2578 <0x8280000 0x18 2069 <0x8280000 0x180000>;
2579 reg-names = "stm-base 2070 reg-names = "stm-base", "stm-stimulus-base";
2580 2071
2581 clocks = <&rpmcc RPM_ 2072 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2582 clock-names = "apb_pc 2073 clock-names = "apb_pclk", "atclk";
2583 2074
2584 out-ports { 2075 out-ports {
2585 port { 2076 port {
2586 stm_o 2077 stm_out: endpoint {
2587 2078 remote-endpoint =
2588 2079 <&funnel0_in>;
2589 }; 2080 };
2590 }; 2081 };
2591 }; 2082 };
2592 }; 2083 };
2593 2084
2594 tpiu@3020000 { 2085 tpiu@3020000 {
2595 compatible = "arm,cor 2086 compatible = "arm,coresight-tpiu", "arm,primecell";
2596 reg = <0x3020000 0x10 2087 reg = <0x3020000 0x1000>;
2597 2088
2598 clocks = <&rpmcc RPM_ 2089 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2599 clock-names = "apb_pc 2090 clock-names = "apb_pclk", "atclk";
2600 2091
2601 in-ports { 2092 in-ports {
2602 port { 2093 port {
2603 tpiu_ 2094 tpiu_in: endpoint {
2604 2095 remote-endpoint =
2605 2096 <&replicator_out1>;
2606 }; 2097 };
2607 }; 2098 };
2608 }; 2099 };
2609 }; 2100 };
2610 2101
2611 funnel@3021000 { 2102 funnel@3021000 {
2612 compatible = "arm,cor 2103 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2613 reg = <0x3021000 0x10 2104 reg = <0x3021000 0x1000>;
2614 2105
2615 clocks = <&rpmcc RPM_ 2106 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2616 clock-names = "apb_pc 2107 clock-names = "apb_pclk", "atclk";
2617 2108
2618 in-ports { 2109 in-ports {
2619 #address-cell 2110 #address-cells = <1>;
2620 #size-cells = 2111 #size-cells = <0>;
2621 2112
2622 port@7 { 2113 port@7 {
2623 reg = 2114 reg = <7>;
2624 funne 2115 funnel0_in: endpoint {
2625 2116 remote-endpoint =
2626 2117 <&stm_out>;
2627 }; 2118 };
2628 }; 2119 };
2629 }; 2120 };
2630 2121
2631 out-ports { 2122 out-ports {
2632 port { 2123 port {
2633 funne 2124 funnel0_out: endpoint {
2634 2125 remote-endpoint =
2635 2126 <&merge_funnel_in0>;
2636 }; 2127 };
2637 }; 2128 };
2638 }; 2129 };
2639 }; 2130 };
2640 2131
2641 funnel@3022000 { 2132 funnel@3022000 {
2642 compatible = "arm,cor 2133 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2643 reg = <0x3022000 0x10 2134 reg = <0x3022000 0x1000>;
2644 2135
2645 clocks = <&rpmcc RPM_ 2136 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2646 clock-names = "apb_pc 2137 clock-names = "apb_pclk", "atclk";
2647 2138
2648 in-ports { 2139 in-ports {
2649 #address-cell 2140 #address-cells = <1>;
2650 #size-cells = 2141 #size-cells = <0>;
2651 2142
2652 port@6 { 2143 port@6 {
2653 reg = 2144 reg = <6>;
2654 funne 2145 funnel1_in: endpoint {
2655 2146 remote-endpoint =
2656 2147 <&apss_merge_funnel_out>;
2657 }; 2148 };
2658 }; 2149 };
2659 }; 2150 };
2660 2151
2661 out-ports { 2152 out-ports {
2662 port { 2153 port {
2663 funne 2154 funnel1_out: endpoint {
2664 2155 remote-endpoint =
2665 2156 <&merge_funnel_in1>;
2666 }; 2157 };
2667 }; 2158 };
2668 }; 2159 };
2669 }; 2160 };
2670 2161
2671 funnel@3023000 { 2162 funnel@3023000 {
2672 compatible = "arm,cor 2163 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2673 reg = <0x3023000 0x10 2164 reg = <0x3023000 0x1000>;
2674 2165
2675 clocks = <&rpmcc RPM_ 2166 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2676 clock-names = "apb_pc 2167 clock-names = "apb_pclk", "atclk";
2677 2168
2678 in-ports { <<
2679 port { <<
2680 funne <<
2681 <<
2682 <<
2683 }; <<
2684 }; <<
2685 }; <<
2686 2169
2687 out-ports { 2170 out-ports {
2688 port { 2171 port {
2689 funne 2172 funnel2_out: endpoint {
2690 2173 remote-endpoint =
2691 2174 <&merge_funnel_in2>;
2692 }; 2175 };
2693 }; 2176 };
2694 }; 2177 };
2695 }; 2178 };
2696 2179
2697 funnel@3025000 { 2180 funnel@3025000 {
2698 compatible = "arm,cor 2181 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2699 reg = <0x3025000 0x10 2182 reg = <0x3025000 0x1000>;
2700 2183
2701 clocks = <&rpmcc RPM_ 2184 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2702 clock-names = "apb_pc 2185 clock-names = "apb_pclk", "atclk";
2703 2186
2704 in-ports { 2187 in-ports {
2705 #address-cell 2188 #address-cells = <1>;
2706 #size-cells = 2189 #size-cells = <0>;
2707 2190
2708 port@0 { 2191 port@0 {
2709 reg = 2192 reg = <0>;
2710 merge 2193 merge_funnel_in0: endpoint {
2711 2194 remote-endpoint =
2712 2195 <&funnel0_out>;
2713 }; 2196 };
2714 }; 2197 };
2715 2198
2716 port@1 { 2199 port@1 {
2717 reg = 2200 reg = <1>;
2718 merge 2201 merge_funnel_in1: endpoint {
2719 2202 remote-endpoint =
2720 2203 <&funnel1_out>;
2721 }; 2204 };
2722 }; 2205 };
2723 2206
2724 port@2 { 2207 port@2 {
2725 reg = 2208 reg = <2>;
2726 merge 2209 merge_funnel_in2: endpoint {
2727 2210 remote-endpoint =
2728 2211 <&funnel2_out>;
2729 }; 2212 };
2730 }; 2213 };
2731 }; 2214 };
2732 2215
2733 out-ports { 2216 out-ports {
2734 port { 2217 port {
2735 merge 2218 merge_funnel_out: endpoint {
2736 2219 remote-endpoint =
2737 2220 <&etf_in>;
2738 }; 2221 };
2739 }; 2222 };
2740 }; 2223 };
2741 }; 2224 };
2742 2225
2743 replicator@3026000 { 2226 replicator@3026000 {
2744 compatible = "arm,cor 2227 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2745 reg = <0x3026000 0x10 2228 reg = <0x3026000 0x1000>;
2746 2229
2747 clocks = <&rpmcc RPM_ 2230 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2748 clock-names = "apb_pc 2231 clock-names = "apb_pclk", "atclk";
2749 2232
2750 in-ports { 2233 in-ports {
2751 port { 2234 port {
2752 repli 2235 replicator_in: endpoint {
2753 2236 remote-endpoint =
2754 2237 <&etf_out>;
2755 }; 2238 };
2756 }; 2239 };
2757 }; 2240 };
2758 2241
2759 out-ports { 2242 out-ports {
2760 #address-cell 2243 #address-cells = <1>;
2761 #size-cells = 2244 #size-cells = <0>;
2762 2245
2763 port@0 { 2246 port@0 {
2764 reg = 2247 reg = <0>;
2765 repli 2248 replicator_out0: endpoint {
2766 2249 remote-endpoint =
2767 2250 <&etr_in>;
2768 }; 2251 };
2769 }; 2252 };
2770 2253
2771 port@1 { 2254 port@1 {
2772 reg = 2255 reg = <1>;
2773 repli 2256 replicator_out1: endpoint {
2774 2257 remote-endpoint =
2775 2258 <&tpiu_in>;
2776 }; 2259 };
2777 }; 2260 };
2778 }; 2261 };
2779 }; 2262 };
2780 2263
2781 etf@3027000 { 2264 etf@3027000 {
2782 compatible = "arm,cor 2265 compatible = "arm,coresight-tmc", "arm,primecell";
2783 reg = <0x3027000 0x10 2266 reg = <0x3027000 0x1000>;
2784 2267
2785 clocks = <&rpmcc RPM_ 2268 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2786 clock-names = "apb_pc 2269 clock-names = "apb_pclk", "atclk";
2787 2270
2788 in-ports { 2271 in-ports {
2789 port { 2272 port {
2790 etf_i 2273 etf_in: endpoint {
2791 2274 remote-endpoint =
2792 2275 <&merge_funnel_out>;
2793 }; 2276 };
2794 }; 2277 };
2795 }; 2278 };
2796 2279
2797 out-ports { 2280 out-ports {
2798 port { 2281 port {
2799 etf_o 2282 etf_out: endpoint {
2800 2283 remote-endpoint =
2801 2284 <&replicator_in>;
2802 }; 2285 };
2803 }; 2286 };
2804 }; 2287 };
2805 }; 2288 };
2806 2289
2807 etr@3028000 { 2290 etr@3028000 {
2808 compatible = "arm,cor 2291 compatible = "arm,coresight-tmc", "arm,primecell";
2809 reg = <0x3028000 0x10 2292 reg = <0x3028000 0x1000>;
2810 2293
2811 clocks = <&rpmcc RPM_ 2294 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2812 clock-names = "apb_pc 2295 clock-names = "apb_pclk", "atclk";
2813 arm,scatter-gather; 2296 arm,scatter-gather;
2814 2297
2815 in-ports { 2298 in-ports {
2816 port { 2299 port {
2817 etr_i 2300 etr_in: endpoint {
2818 2301 remote-endpoint =
2819 2302 <&replicator_out0>;
2820 }; 2303 };
2821 }; 2304 };
2822 }; 2305 };
2823 }; 2306 };
2824 2307
2825 debug@3810000 { 2308 debug@3810000 {
2826 compatible = "arm,cor 2309 compatible = "arm,coresight-cpu-debug", "arm,primecell";
2827 reg = <0x3810000 0x10 2310 reg = <0x3810000 0x1000>;
2828 2311
2829 clocks = <&rpmcc RPM_ 2312 clocks = <&rpmcc RPM_QDSS_CLK>;
2830 clock-names = "apb_pc 2313 clock-names = "apb_pclk";
2831 2314
2832 cpu = <&CPU0>; 2315 cpu = <&CPU0>;
2833 }; 2316 };
2834 2317
2835 etm@3840000 { 2318 etm@3840000 {
2836 compatible = "arm,cor 2319 compatible = "arm,coresight-etm4x", "arm,primecell";
2837 reg = <0x3840000 0x10 2320 reg = <0x3840000 0x1000>;
2838 2321
2839 clocks = <&rpmcc RPM_ 2322 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2840 clock-names = "apb_pc 2323 clock-names = "apb_pclk", "atclk";
2841 2324
2842 cpu = <&CPU0>; 2325 cpu = <&CPU0>;
2843 2326
2844 out-ports { 2327 out-ports {
2845 port { 2328 port {
2846 etm0_ 2329 etm0_out: endpoint {
2847 2330 remote-endpoint =
2848 2331 <&apss_funnel0_in0>;
2849 }; 2332 };
2850 }; 2333 };
2851 }; 2334 };
2852 }; 2335 };
2853 2336
2854 debug@3910000 { 2337 debug@3910000 {
2855 compatible = "arm,cor 2338 compatible = "arm,coresight-cpu-debug", "arm,primecell";
2856 reg = <0x3910000 0x10 2339 reg = <0x3910000 0x1000>;
2857 2340
2858 clocks = <&rpmcc RPM_ 2341 clocks = <&rpmcc RPM_QDSS_CLK>;
2859 clock-names = "apb_pc 2342 clock-names = "apb_pclk";
2860 2343
2861 cpu = <&CPU1>; 2344 cpu = <&CPU1>;
2862 }; 2345 };
2863 2346
2864 etm@3940000 { 2347 etm@3940000 {
2865 compatible = "arm,cor 2348 compatible = "arm,coresight-etm4x", "arm,primecell";
2866 reg = <0x3940000 0x10 2349 reg = <0x3940000 0x1000>;
2867 2350
2868 clocks = <&rpmcc RPM_ 2351 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2869 clock-names = "apb_pc 2352 clock-names = "apb_pclk", "atclk";
2870 2353
2871 cpu = <&CPU1>; 2354 cpu = <&CPU1>;
2872 2355
2873 out-ports { 2356 out-ports {
2874 port { 2357 port {
2875 etm1_ 2358 etm1_out: endpoint {
2876 2359 remote-endpoint =
2877 2360 <&apss_funnel0_in1>;
2878 }; 2361 };
2879 }; 2362 };
2880 }; 2363 };
2881 }; 2364 };
2882 2365
2883 funnel@39b0000 { /* APSS Funn 2366 funnel@39b0000 { /* APSS Funnel 0 */
2884 compatible = "arm,cor 2367 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2885 reg = <0x39b0000 0x10 2368 reg = <0x39b0000 0x1000>;
2886 2369
2887 clocks = <&rpmcc RPM_ 2370 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2888 clock-names = "apb_pc 2371 clock-names = "apb_pclk", "atclk";
2889 2372
2890 in-ports { 2373 in-ports {
2891 #address-cell 2374 #address-cells = <1>;
2892 #size-cells = 2375 #size-cells = <0>;
2893 2376
2894 port@0 { 2377 port@0 {
2895 reg = 2378 reg = <0>;
2896 apss_ 2379 apss_funnel0_in0: endpoint {
2897 2380 remote-endpoint = <&etm0_out>;
2898 }; 2381 };
2899 }; 2382 };
2900 2383
2901 port@1 { 2384 port@1 {
2902 reg = 2385 reg = <1>;
2903 apss_ 2386 apss_funnel0_in1: endpoint {
2904 2387 remote-endpoint = <&etm1_out>;
2905 }; 2388 };
2906 }; 2389 };
2907 }; 2390 };
2908 2391
2909 out-ports { 2392 out-ports {
2910 port { 2393 port {
2911 apss_ 2394 apss_funnel0_out: endpoint {
2912 2395 remote-endpoint =
2913 2396 <&apss_merge_funnel_in0>;
2914 }; 2397 };
2915 }; 2398 };
2916 }; 2399 };
2917 }; 2400 };
2918 2401
2919 debug@3a10000 { 2402 debug@3a10000 {
2920 compatible = "arm,cor 2403 compatible = "arm,coresight-cpu-debug", "arm,primecell";
2921 reg = <0x3a10000 0x10 2404 reg = <0x3a10000 0x1000>;
2922 2405
2923 clocks = <&rpmcc RPM_ 2406 clocks = <&rpmcc RPM_QDSS_CLK>;
2924 clock-names = "apb_pc 2407 clock-names = "apb_pclk";
2925 2408
2926 cpu = <&CPU2>; 2409 cpu = <&CPU2>;
2927 }; 2410 };
2928 2411
2929 etm@3a40000 { 2412 etm@3a40000 {
2930 compatible = "arm,cor 2413 compatible = "arm,coresight-etm4x", "arm,primecell";
2931 reg = <0x3a40000 0x10 2414 reg = <0x3a40000 0x1000>;
2932 2415
2933 clocks = <&rpmcc RPM_ 2416 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2934 clock-names = "apb_pc 2417 clock-names = "apb_pclk", "atclk";
2935 2418
2936 cpu = <&CPU2>; 2419 cpu = <&CPU2>;
2937 2420
2938 out-ports { 2421 out-ports {
2939 port { 2422 port {
2940 etm2_ 2423 etm2_out: endpoint {
2941 2424 remote-endpoint =
2942 2425 <&apss_funnel1_in0>;
2943 }; 2426 };
2944 }; 2427 };
2945 }; 2428 };
2946 }; 2429 };
2947 2430
2948 debug@3b10000 { 2431 debug@3b10000 {
2949 compatible = "arm,cor 2432 compatible = "arm,coresight-cpu-debug", "arm,primecell";
2950 reg = <0x3b10000 0x10 2433 reg = <0x3b10000 0x1000>;
2951 2434
2952 clocks = <&rpmcc RPM_ 2435 clocks = <&rpmcc RPM_QDSS_CLK>;
2953 clock-names = "apb_pc 2436 clock-names = "apb_pclk";
2954 2437
2955 cpu = <&CPU3>; 2438 cpu = <&CPU3>;
2956 }; 2439 };
2957 2440
2958 etm@3b40000 { 2441 etm@3b40000 {
2959 compatible = "arm,cor 2442 compatible = "arm,coresight-etm4x", "arm,primecell";
2960 reg = <0x3b40000 0x10 2443 reg = <0x3b40000 0x1000>;
2961 2444
2962 clocks = <&rpmcc RPM_ 2445 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2963 clock-names = "apb_pc 2446 clock-names = "apb_pclk", "atclk";
2964 2447
2965 cpu = <&CPU3>; 2448 cpu = <&CPU3>;
2966 2449
2967 out-ports { 2450 out-ports {
2968 port { 2451 port {
2969 etm3_ 2452 etm3_out: endpoint {
2970 2453 remote-endpoint =
2971 2454 <&apss_funnel1_in1>;
2972 }; 2455 };
2973 }; 2456 };
2974 }; 2457 };
2975 }; 2458 };
2976 2459
2977 funnel@3bb0000 { /* APSS Funn 2460 funnel@3bb0000 { /* APSS Funnel 1 */
2978 compatible = "arm,cor 2461 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2979 reg = <0x3bb0000 0x10 2462 reg = <0x3bb0000 0x1000>;
2980 2463
2981 clocks = <&rpmcc RPM_ 2464 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2982 clock-names = "apb_pc 2465 clock-names = "apb_pclk", "atclk";
2983 2466
2984 in-ports { 2467 in-ports {
2985 #address-cell 2468 #address-cells = <1>;
2986 #size-cells = 2469 #size-cells = <0>;
2987 2470
2988 port@0 { 2471 port@0 {
2989 reg = 2472 reg = <0>;
2990 apss_ 2473 apss_funnel1_in0: endpoint {
2991 2474 remote-endpoint = <&etm2_out>;
2992 }; 2475 };
2993 }; 2476 };
2994 2477
2995 port@1 { 2478 port@1 {
2996 reg = 2479 reg = <1>;
2997 apss_ 2480 apss_funnel1_in1: endpoint {
2998 2481 remote-endpoint = <&etm3_out>;
2999 }; 2482 };
3000 }; 2483 };
3001 }; 2484 };
3002 2485
3003 out-ports { 2486 out-ports {
3004 port { 2487 port {
3005 apss_ 2488 apss_funnel1_out: endpoint {
3006 2489 remote-endpoint =
3007 2490 <&apss_merge_funnel_in1>;
3008 }; 2491 };
3009 }; 2492 };
3010 }; 2493 };
3011 }; 2494 };
3012 2495
3013 funnel@3bc0000 { 2496 funnel@3bc0000 {
3014 compatible = "arm,cor 2497 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3015 reg = <0x3bc0000 0x10 2498 reg = <0x3bc0000 0x1000>;
3016 2499
3017 clocks = <&rpmcc RPM_ 2500 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
3018 clock-names = "apb_pc 2501 clock-names = "apb_pclk", "atclk";
3019 2502
3020 in-ports { 2503 in-ports {
3021 #address-cell 2504 #address-cells = <1>;
3022 #size-cells = 2505 #size-cells = <0>;
3023 2506
3024 port@0 { 2507 port@0 {
3025 reg = 2508 reg = <0>;
3026 apss_ 2509 apss_merge_funnel_in0: endpoint {
3027 2510 remote-endpoint =
3028 2511 <&apss_funnel0_out>;
3029 }; 2512 };
3030 }; 2513 };
3031 2514
3032 port@1 { 2515 port@1 {
3033 reg = 2516 reg = <1>;
3034 apss_ 2517 apss_merge_funnel_in1: endpoint {
3035 2518 remote-endpoint =
3036 2519 <&apss_funnel1_out>;
3037 }; 2520 };
3038 }; 2521 };
3039 }; 2522 };
3040 2523
3041 out-ports { 2524 out-ports {
3042 port { 2525 port {
3043 apss_ 2526 apss_merge_funnel_out: endpoint {
3044 2527 remote-endpoint =
3045 2528 <&funnel1_in>;
3046 }; 2529 };
3047 }; 2530 };
3048 }; 2531 };
3049 }; 2532 };
3050 2533
3051 kryocc: clock-controller@6400 2534 kryocc: clock-controller@6400000 {
3052 compatible = "qcom,ms 2535 compatible = "qcom,msm8996-apcc";
3053 reg = <0x06400000 0x9 2536 reg = <0x06400000 0x90000>;
3054 2537
3055 clock-names = "xo", " !! 2538 clock-names = "xo";
3056 clocks = <&rpmcc RPM_ !! 2539 clocks = <&xo_board>;
3057 2540
3058 #clock-cells = <1>; 2541 #clock-cells = <1>;
3059 }; 2542 };
3060 2543
3061 usb3: usb@6af8800 { 2544 usb3: usb@6af8800 {
3062 compatible = "qcom,ms 2545 compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
3063 reg = <0x06af8800 0x4 2546 reg = <0x06af8800 0x400>;
3064 #address-cells = <1>; 2547 #address-cells = <1>;
3065 #size-cells = <1>; 2548 #size-cells = <1>;
3066 ranges; 2549 ranges;
3067 2550
3068 interrupts = <GIC_SPI 2551 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
3069 <GIC_SPI 2552 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
3070 interrupt-names = "hs 2553 interrupt-names = "hs_phy_irq", "ss_phy_irq";
3071 2554
3072 clocks = <&gcc GCC_SY 2555 clocks = <&gcc GCC_SYS_NOC_USB3_AXI_CLK>,
3073 <&gcc GCC_US !! 2556 <&gcc GCC_USB30_MASTER_CLK>,
3074 <&gcc GCC_AG !! 2557 <&gcc GCC_AGGRE2_USB3_AXI_CLK>,
3075 <&gcc GCC_US !! 2558 <&gcc GCC_USB30_MOCK_UTMI_CLK>,
3076 <&gcc GCC_US !! 2559 <&gcc GCC_USB30_SLEEP_CLK>,
3077 clock-names = "cfg_no !! 2560 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
3078 "core", <<
3079 "iface" <<
3080 "sleep" <<
3081 "mock_u <<
3082 2561
3083 assigned-clocks = <&g 2562 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
3084 <&g 2563 <&gcc GCC_USB30_MASTER_CLK>;
3085 assigned-clock-rates 2564 assigned-clock-rates = <19200000>, <120000000>;
3086 2565
3087 interconnects = <&a2n <<
3088 <&bim <<
3089 interconnect-names = <<
3090 <<
3091 power-domains = <&gcc 2566 power-domains = <&gcc USB30_GDSC>;
3092 status = "disabled"; 2567 status = "disabled";
3093 2568
3094 usb3_dwc3: usb@6a0000 !! 2569 dwc3@6a00000 {
3095 compatible = 2570 compatible = "snps,dwc3";
3096 reg = <0x06a0 2571 reg = <0x06a00000 0xcc00>;
3097 interrupts = !! 2572 interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>;
3098 phys = <&hsus !! 2573 phys = <&hsusb_phy1>, <&ssusb_phy_0>;
3099 phy-names = " 2574 phy-names = "usb2-phy", "usb3-phy";
3100 snps,hird-thr <<
3101 snps,dis_u2_s 2575 snps,dis_u2_susphy_quirk;
3102 snps,dis_enbl 2576 snps,dis_enblslpm_quirk;
3103 snps,is-utmi- <<
3104 snps,parkmode <<
3105 tx-fifo-resiz <<
3106 }; 2577 };
3107 }; 2578 };
3108 2579
3109 usb3phy: phy@7410000 { 2580 usb3phy: phy@7410000 {
3110 compatible = "qcom,ms 2581 compatible = "qcom,msm8996-qmp-usb3-phy";
3111 reg = <0x07410000 0x1 !! 2582 reg = <0x07410000 0x1c4>;
>> 2583 #clock-cells = <1>;
>> 2584 #address-cells = <1>;
>> 2585 #size-cells = <1>;
>> 2586 ranges;
3112 2587
3113 clocks = <&gcc GCC_US 2588 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
3114 <&gcc GCC_US !! 2589 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
3115 <&gcc GCC_US !! 2590 <&gcc GCC_USB3_CLKREF_CLK>;
3116 <&gcc GCC_US !! 2591 clock-names = "aux", "cfg_ahb", "ref";
3117 clock-names = "aux", <<
3118 "ref", <<
3119 "cfg_ah <<
3120 "pipe"; <<
3121 clock-output-names = <<
3122 #clock-cells = <0>; <<
3123 #phy-cells = <0>; <<
3124 2592
3125 resets = <&gcc GCC_US 2593 resets = <&gcc GCC_USB3_PHY_BCR>,
3126 <&gcc GCC_US !! 2594 <&gcc GCC_USB3PHY_PHY_BCR>;
3127 reset-names = "phy", !! 2595 reset-names = "phy", "common";
3128 "phy_ph <<
3129 <<
3130 status = "disabled"; 2596 status = "disabled";
>> 2597
>> 2598 ssusb_phy_0: lane@7410200 {
>> 2599 reg = <0x07410200 0x200>,
>> 2600 <0x07410400 0x130>,
>> 2601 <0x07410600 0x1a8>;
>> 2602 #phy-cells = <0>;
>> 2603
>> 2604 clock-output-names = "usb3_phy_pipe_clk_src";
>> 2605 clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
>> 2606 clock-names = "pipe0";
>> 2607 };
3131 }; 2608 };
3132 2609
3133 hsusb_phy1: phy@7411000 { 2610 hsusb_phy1: phy@7411000 {
3134 compatible = "qcom,ms 2611 compatible = "qcom,msm8996-qusb2-phy";
3135 reg = <0x07411000 0x1 2612 reg = <0x07411000 0x180>;
3136 #phy-cells = <0>; 2613 #phy-cells = <0>;
3137 2614
3138 clocks = <&gcc GCC_US 2615 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
3139 <&gcc GCC_RX1 2616 <&gcc GCC_RX1_USB2_CLKREF_CLK>;
3140 clock-names = "cfg_ah 2617 clock-names = "cfg_ahb", "ref";
3141 2618
3142 resets = <&gcc GCC_QU 2619 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
3143 nvmem-cells = <&qusb2 2620 nvmem-cells = <&qusb2p_hstx_trim>;
3144 status = "disabled"; 2621 status = "disabled";
3145 }; 2622 };
3146 2623
3147 hsusb_phy2: phy@7412000 { 2624 hsusb_phy2: phy@7412000 {
3148 compatible = "qcom,ms 2625 compatible = "qcom,msm8996-qusb2-phy";
3149 reg = <0x07412000 0x1 2626 reg = <0x07412000 0x180>;
3150 #phy-cells = <0>; 2627 #phy-cells = <0>;
3151 2628
3152 clocks = <&gcc GCC_US 2629 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
3153 <&gcc GCC_RX2 2630 <&gcc GCC_RX2_USB2_CLKREF_CLK>;
3154 clock-names = "cfg_ah 2631 clock-names = "cfg_ahb", "ref";
3155 2632
3156 resets = <&gcc GCC_QU 2633 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
3157 nvmem-cells = <&qusb2 2634 nvmem-cells = <&qusb2s_hstx_trim>;
3158 status = "disabled"; 2635 status = "disabled";
3159 }; 2636 };
3160 2637
3161 sdhc1: mmc@7464900 { !! 2638 sdhc1: sdhci@7464900 {
3162 compatible = "qcom,ms !! 2639 compatible = "qcom,sdhci-msm-v4";
3163 reg = <0x07464900 0x1 2640 reg = <0x07464900 0x11c>, <0x07464000 0x800>;
3164 reg-names = "hc", "co !! 2641 reg-names = "hc_mem", "core_mem";
3165 2642
3166 interrupts = <GIC_SPI 2643 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
3167 <GIC_ 2644 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
3168 interrupt-names = "hc 2645 interrupt-names = "hc_irq", "pwr_irq";
3169 2646
3170 clock-names = "iface" 2647 clock-names = "iface", "core", "xo";
3171 clocks = <&gcc GCC_SD 2648 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
3172 <&gcc GCC_SDC 2649 <&gcc GCC_SDCC1_APPS_CLK>,
3173 <&rpmcc RPM_S !! 2650 <&xo_board>;
3174 resets = <&gcc GCC_SD <<
3175 2651
3176 pinctrl-names = "defa 2652 pinctrl-names = "default", "sleep";
3177 pinctrl-0 = <&sdc1_st 2653 pinctrl-0 = <&sdc1_state_on>;
3178 pinctrl-1 = <&sdc1_st 2654 pinctrl-1 = <&sdc1_state_off>;
3179 2655
3180 bus-width = <8>; 2656 bus-width = <8>;
3181 non-removable; 2657 non-removable;
3182 status = "disabled"; 2658 status = "disabled";
3183 }; 2659 };
3184 2660
3185 sdhc2: mmc@74a4900 { !! 2661 sdhc2: sdhci@74a4900 {
3186 compatible = "qcom,ms !! 2662 compatible = "qcom,sdhci-msm-v4";
3187 reg = <0x074a4900 0x3 2663 reg = <0x074a4900 0x314>, <0x074a4000 0x800>;
3188 reg-names = "hc", "co !! 2664 reg-names = "hc_mem", "core_mem";
3189 2665
3190 interrupts = <GIC_SPI 2666 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
3191 <GIC_SP 2667 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
3192 interrupt-names = "hc 2668 interrupt-names = "hc_irq", "pwr_irq";
3193 2669
3194 clock-names = "iface" 2670 clock-names = "iface", "core", "xo";
3195 clocks = <&gcc GCC_SD 2671 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
3196 <&gcc GCC_SDC 2672 <&gcc GCC_SDCC2_APPS_CLK>,
3197 <&rpmcc RPM_S !! 2673 <&xo_board>;
3198 resets = <&gcc GCC_SD <<
3199 2674
3200 pinctrl-names = "defa 2675 pinctrl-names = "default", "sleep";
3201 pinctrl-0 = <&sdc2_st 2676 pinctrl-0 = <&sdc2_state_on>;
3202 pinctrl-1 = <&sdc2_st 2677 pinctrl-1 = <&sdc2_state_off>;
3203 2678
3204 bus-width = <4>; 2679 bus-width = <4>;
3205 status = "disabled"; 2680 status = "disabled";
3206 }; 2681 };
3207 2682
3208 blsp1_dma: dma-controller@754 !! 2683 blsp1_dma: dma@7544000 {
3209 compatible = "qcom,ba 2684 compatible = "qcom,bam-v1.7.0";
3210 reg = <0x07544000 0x2 2685 reg = <0x07544000 0x2b000>;
3211 interrupts = <GIC_SPI 2686 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
3212 clocks = <&gcc GCC_BL 2687 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
3213 clock-names = "bam_cl 2688 clock-names = "bam_clk";
3214 qcom,controlled-remot 2689 qcom,controlled-remotely;
3215 #dma-cells = <1>; 2690 #dma-cells = <1>;
3216 qcom,ee = <0>; 2691 qcom,ee = <0>;
3217 }; 2692 };
3218 2693
3219 blsp1_uart2: serial@7570000 { 2694 blsp1_uart2: serial@7570000 {
3220 compatible = "qcom,ms 2695 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
3221 reg = <0x07570000 0x1 2696 reg = <0x07570000 0x1000>;
3222 interrupts = <GIC_SPI 2697 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
3223 clocks = <&gcc GCC_BL 2698 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
3224 <&gcc GCC_BL 2699 <&gcc GCC_BLSP1_AHB_CLK>;
3225 clock-names = "core", 2700 clock-names = "core", "iface";
3226 pinctrl-names = "defa <<
3227 pinctrl-0 = <&blsp1_u <<
3228 pinctrl-1 = <&blsp1_u <<
3229 dmas = <&blsp1_dma 2> 2701 dmas = <&blsp1_dma 2>, <&blsp1_dma 3>;
3230 dma-names = "tx", "rx 2702 dma-names = "tx", "rx";
3231 status = "disabled"; 2703 status = "disabled";
3232 }; 2704 };
3233 2705
3234 blsp1_spi1: spi@7575000 { 2706 blsp1_spi1: spi@7575000 {
3235 compatible = "qcom,sp 2707 compatible = "qcom,spi-qup-v2.2.1";
3236 reg = <0x07575000 0x6 2708 reg = <0x07575000 0x600>;
3237 interrupts = <GIC_SPI 2709 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
3238 clocks = <&gcc GCC_BL 2710 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
3239 <&gcc GCC_BL 2711 <&gcc GCC_BLSP1_AHB_CLK>;
3240 clock-names = "core", 2712 clock-names = "core", "iface";
3241 pinctrl-names = "defa 2713 pinctrl-names = "default", "sleep";
3242 pinctrl-0 = <&blsp1_s 2714 pinctrl-0 = <&blsp1_spi1_default>;
3243 pinctrl-1 = <&blsp1_s 2715 pinctrl-1 = <&blsp1_spi1_sleep>;
3244 dmas = <&blsp1_dma 12 2716 dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
3245 dma-names = "tx", "rx 2717 dma-names = "tx", "rx";
3246 #address-cells = <1>; 2718 #address-cells = <1>;
3247 #size-cells = <0>; 2719 #size-cells = <0>;
3248 status = "disabled"; 2720 status = "disabled";
3249 }; 2721 };
3250 2722
3251 blsp1_i2c3: i2c@7577000 { 2723 blsp1_i2c3: i2c@7577000 {
3252 compatible = "qcom,i2 2724 compatible = "qcom,i2c-qup-v2.2.1";
3253 reg = <0x07577000 0x1 2725 reg = <0x07577000 0x1000>;
3254 interrupts = <GIC_SPI 2726 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
3255 clocks = <&gcc GCC_BL !! 2727 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
3256 <&gcc GCC_BL !! 2728 <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
3257 clock-names = "core", !! 2729 clock-names = "iface", "core";
3258 pinctrl-names = "defa 2730 pinctrl-names = "default", "sleep";
3259 pinctrl-0 = <&blsp1_i 2731 pinctrl-0 = <&blsp1_i2c3_default>;
3260 pinctrl-1 = <&blsp1_i 2732 pinctrl-1 = <&blsp1_i2c3_sleep>;
3261 dmas = <&blsp1_dma 16 2733 dmas = <&blsp1_dma 16>, <&blsp1_dma 17>;
3262 dma-names = "tx", "rx 2734 dma-names = "tx", "rx";
3263 #address-cells = <1>; 2735 #address-cells = <1>;
3264 #size-cells = <0>; 2736 #size-cells = <0>;
3265 status = "disabled"; 2737 status = "disabled";
3266 }; 2738 };
3267 2739
3268 blsp1_i2c6: i2c@757a000 { !! 2740 blsp2_dma: dma@7584000 {
3269 compatible = "qcom,i2 <<
3270 reg = <0x757a000 0x10 <<
3271 interrupts = <GIC_SPI <<
3272 clocks = <&gcc GCC_BL <<
3273 <&gcc GCC_BL <<
3274 clock-names = "core", <<
3275 pinctrl-names = "defa <<
3276 pinctrl-0 = <&blsp1_i <<
3277 pinctrl-1 = <&blsp1_i <<
3278 dmas = <&blsp1_dma 22 <<
3279 dma-names = "tx", "rx <<
3280 #address-cells = <1>; <<
3281 #size-cells = <0>; <<
3282 status = "disabled"; <<
3283 }; <<
3284 <<
3285 blsp2_dma: dma-controller@758 <<
3286 compatible = "qcom,ba 2741 compatible = "qcom,bam-v1.7.0";
3287 reg = <0x07584000 0x2 2742 reg = <0x07584000 0x2b000>;
3288 interrupts = <GIC_SPI 2743 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
3289 clocks = <&gcc GCC_BL 2744 clocks = <&gcc GCC_BLSP2_AHB_CLK>;
3290 clock-names = "bam_cl 2745 clock-names = "bam_clk";
3291 qcom,controlled-remot 2746 qcom,controlled-remotely;
3292 #dma-cells = <1>; 2747 #dma-cells = <1>;
3293 qcom,ee = <0>; 2748 qcom,ee = <0>;
3294 }; 2749 };
3295 2750
3296 blsp2_uart2: serial@75b0000 { 2751 blsp2_uart2: serial@75b0000 {
3297 compatible = "qcom,ms 2752 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
3298 reg = <0x075b0000 0x1 2753 reg = <0x075b0000 0x1000>;
3299 interrupts = <GIC_SPI 2754 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
3300 clocks = <&gcc GCC_BL 2755 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
3301 <&gcc GCC_BL 2756 <&gcc GCC_BLSP2_AHB_CLK>;
3302 clock-names = "core", 2757 clock-names = "core", "iface";
3303 status = "disabled"; 2758 status = "disabled";
3304 }; 2759 };
3305 2760
3306 blsp2_uart3: serial@75b1000 { 2761 blsp2_uart3: serial@75b1000 {
3307 compatible = "qcom,ms 2762 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
3308 reg = <0x075b1000 0x1 2763 reg = <0x075b1000 0x1000>;
3309 interrupts = <GIC_SPI 2764 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
3310 clocks = <&gcc GCC_BL 2765 clocks = <&gcc GCC_BLSP2_UART3_APPS_CLK>,
3311 <&gcc GCC_BL 2766 <&gcc GCC_BLSP2_AHB_CLK>;
3312 clock-names = "core", 2767 clock-names = "core", "iface";
3313 status = "disabled"; 2768 status = "disabled";
3314 }; 2769 };
3315 2770
3316 blsp2_i2c1: i2c@75b5000 { 2771 blsp2_i2c1: i2c@75b5000 {
3317 compatible = "qcom,i2 2772 compatible = "qcom,i2c-qup-v2.2.1";
3318 reg = <0x075b5000 0x1 2773 reg = <0x075b5000 0x1000>;
3319 interrupts = <GIC_SPI 2774 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
3320 clocks = <&gcc GCC_BL !! 2775 clocks = <&gcc GCC_BLSP2_AHB_CLK>,
3321 <&gcc GCC_BL !! 2776 <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>;
3322 clock-names = "core", !! 2777 clock-names = "iface", "core";
3323 pinctrl-names = "defa 2778 pinctrl-names = "default", "sleep";
3324 pinctrl-0 = <&blsp2_i 2779 pinctrl-0 = <&blsp2_i2c1_default>;
3325 pinctrl-1 = <&blsp2_i 2780 pinctrl-1 = <&blsp2_i2c1_sleep>;
3326 dmas = <&blsp2_dma 12 2781 dmas = <&blsp2_dma 12>, <&blsp2_dma 13>;
3327 dma-names = "tx", "rx 2782 dma-names = "tx", "rx";
3328 #address-cells = <1>; 2783 #address-cells = <1>;
3329 #size-cells = <0>; 2784 #size-cells = <0>;
3330 status = "disabled"; 2785 status = "disabled";
3331 }; 2786 };
3332 2787
3333 blsp2_i2c2: i2c@75b6000 { 2788 blsp2_i2c2: i2c@75b6000 {
3334 compatible = "qcom,i2 2789 compatible = "qcom,i2c-qup-v2.2.1";
3335 reg = <0x075b6000 0x1 2790 reg = <0x075b6000 0x1000>;
3336 interrupts = <GIC_SPI 2791 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
3337 clocks = <&gcc GCC_BL !! 2792 clocks = <&gcc GCC_BLSP2_AHB_CLK>,
3338 <&gcc GCC_BL !! 2793 <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>;
3339 clock-names = "core", !! 2794 clock-names = "iface", "core";
3340 pinctrl-names = "defa 2795 pinctrl-names = "default", "sleep";
3341 pinctrl-0 = <&blsp2_i 2796 pinctrl-0 = <&blsp2_i2c2_default>;
3342 pinctrl-1 = <&blsp2_i 2797 pinctrl-1 = <&blsp2_i2c2_sleep>;
3343 dmas = <&blsp2_dma 14 2798 dmas = <&blsp2_dma 14>, <&blsp2_dma 15>;
3344 dma-names = "tx", "rx 2799 dma-names = "tx", "rx";
3345 #address-cells = <1>; 2800 #address-cells = <1>;
3346 #size-cells = <0>; 2801 #size-cells = <0>;
3347 status = "disabled"; 2802 status = "disabled";
3348 }; 2803 };
3349 2804
3350 blsp2_i2c3: i2c@75b7000 { <<
3351 compatible = "qcom,i2 <<
3352 reg = <0x075b7000 0x1 <<
3353 interrupts = <GIC_SPI <<
3354 clocks = <&gcc GCC_BL <<
3355 <&gcc GCC_BL <<
3356 clock-names = "core", <<
3357 clock-frequency = <40 <<
3358 pinctrl-names = "defa <<
3359 pinctrl-0 = <&blsp2_i <<
3360 pinctrl-1 = <&blsp2_i <<
3361 dmas = <&blsp2_dma 16 <<
3362 dma-names = "tx", "rx <<
3363 #address-cells = <1>; <<
3364 #size-cells = <0>; <<
3365 status = "disabled"; <<
3366 }; <<
3367 <<
3368 blsp2_i2c5: i2c@75b9000 { 2805 blsp2_i2c5: i2c@75b9000 {
3369 compatible = "qcom,i2 2806 compatible = "qcom,i2c-qup-v2.2.1";
3370 reg = <0x75b9000 0x10 2807 reg = <0x75b9000 0x1000>;
3371 interrupts = <GIC_SPI 2808 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
3372 clocks = <&gcc GCC_BL !! 2809 clocks = <&gcc GCC_BLSP2_AHB_CLK>,
3373 <&gcc GCC_BL !! 2810 <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>;
3374 clock-names = "core", !! 2811 clock-names = "iface", "core";
3375 pinctrl-names = "defa 2812 pinctrl-names = "default";
3376 pinctrl-0 = <&blsp2_i 2813 pinctrl-0 = <&blsp2_i2c5_default>;
3377 dmas = <&blsp2_dma 20 2814 dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
3378 dma-names = "tx", "rx 2815 dma-names = "tx", "rx";
3379 #address-cells = <1>; 2816 #address-cells = <1>;
3380 #size-cells = <0>; 2817 #size-cells = <0>;
3381 status = "disabled"; 2818 status = "disabled";
3382 }; 2819 };
3383 2820
3384 blsp2_i2c6: i2c@75ba000 { 2821 blsp2_i2c6: i2c@75ba000 {
3385 compatible = "qcom,i2 2822 compatible = "qcom,i2c-qup-v2.2.1";
3386 reg = <0x75ba000 0x10 2823 reg = <0x75ba000 0x1000>;
3387 interrupts = <GIC_SPI 2824 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
3388 clocks = <&gcc GCC_BL !! 2825 clocks = <&gcc GCC_BLSP2_AHB_CLK>,
3389 <&gcc GCC_BL !! 2826 <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>;
3390 clock-names = "core", !! 2827 clock-names = "iface", "core";
3391 pinctrl-names = "defa 2828 pinctrl-names = "default", "sleep";
3392 pinctrl-0 = <&blsp2_i 2829 pinctrl-0 = <&blsp2_i2c6_default>;
3393 pinctrl-1 = <&blsp2_i 2830 pinctrl-1 = <&blsp2_i2c6_sleep>;
3394 dmas = <&blsp2_dma 22 2831 dmas = <&blsp2_dma 22>, <&blsp2_dma 23>;
3395 dma-names = "tx", "rx 2832 dma-names = "tx", "rx";
3396 #address-cells = <1>; 2833 #address-cells = <1>;
3397 #size-cells = <0>; 2834 #size-cells = <0>;
3398 status = "disabled"; 2835 status = "disabled";
3399 }; 2836 };
3400 2837
3401 blsp2_spi6: spi@75ba000 { !! 2838 blsp2_spi6: spi@75ba000{
3402 compatible = "qcom,sp 2839 compatible = "qcom,spi-qup-v2.2.1";
3403 reg = <0x075ba000 0x6 2840 reg = <0x075ba000 0x600>;
3404 interrupts = <GIC_SPI 2841 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
3405 clocks = <&gcc GCC_BL 2842 clocks = <&gcc GCC_BLSP2_QUP6_SPI_APPS_CLK>,
3406 <&gcc GCC_BL 2843 <&gcc GCC_BLSP2_AHB_CLK>;
3407 clock-names = "core", 2844 clock-names = "core", "iface";
3408 pinctrl-names = "defa 2845 pinctrl-names = "default", "sleep";
3409 pinctrl-0 = <&blsp2_s 2846 pinctrl-0 = <&blsp2_spi6_default>;
3410 pinctrl-1 = <&blsp2_s 2847 pinctrl-1 = <&blsp2_spi6_sleep>;
3411 dmas = <&blsp2_dma 22 2848 dmas = <&blsp2_dma 22>, <&blsp2_dma 23>;
3412 dma-names = "tx", "rx 2849 dma-names = "tx", "rx";
3413 #address-cells = <1>; 2850 #address-cells = <1>;
3414 #size-cells = <0>; 2851 #size-cells = <0>;
3415 status = "disabled"; 2852 status = "disabled";
3416 }; 2853 };
3417 2854
3418 usb2: usb@76f8800 { 2855 usb2: usb@76f8800 {
3419 compatible = "qcom,ms 2856 compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
3420 reg = <0x076f8800 0x4 2857 reg = <0x076f8800 0x400>;
3421 #address-cells = <1>; 2858 #address-cells = <1>;
3422 #size-cells = <1>; 2859 #size-cells = <1>;
3423 ranges; 2860 ranges;
3424 2861
3425 interrupts = <GIC_SPI <<
3426 <GIC_SPI <<
3427 <GIC_SPI <<
3428 interrupt-names = "pw <<
3429 "qu <<
3430 "hs <<
3431 <<
3432 clocks = <&gcc GCC_PE 2862 clocks = <&gcc GCC_PERIPH_NOC_USB20_AHB_CLK>,
3433 <&gcc GCC_USB 2863 <&gcc GCC_USB20_MASTER_CLK>,
3434 <&gcc GCC_USB 2864 <&gcc GCC_USB20_MOCK_UTMI_CLK>,
3435 <&gcc GCC_USB 2865 <&gcc GCC_USB20_SLEEP_CLK>,
3436 <&gcc GCC_USB 2866 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
3437 clock-names = "cfg_no <<
3438 "core", <<
3439 "iface" <<
3440 "sleep" <<
3441 "mock_u <<
3442 2867
3443 assigned-clocks = <&g 2868 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
3444 <&g 2869 <&gcc GCC_USB20_MASTER_CLK>;
3445 assigned-clock-rates 2870 assigned-clock-rates = <19200000>, <60000000>;
3446 2871
3447 power-domains = <&gcc 2872 power-domains = <&gcc USB30_GDSC>;
3448 qcom,select-utmi-as-p 2873 qcom,select-utmi-as-pipe-clk;
3449 status = "disabled"; 2874 status = "disabled";
3450 2875
3451 usb2_dwc3: usb@760000 !! 2876 dwc3@7600000 {
3452 compatible = 2877 compatible = "snps,dwc3";
3453 reg = <0x0760 2878 reg = <0x07600000 0xcc00>;
3454 interrupts = !! 2879 interrupts = <0 138 IRQ_TYPE_LEVEL_HIGH>;
3455 phys = <&hsus 2880 phys = <&hsusb_phy2>;
3456 phy-names = " 2881 phy-names = "usb2-phy";
3457 maximum-speed 2882 maximum-speed = "high-speed";
3458 snps,dis_u2_s 2883 snps,dis_u2_susphy_quirk;
3459 snps,dis_enbl 2884 snps,dis_enblslpm_quirk;
3460 }; 2885 };
3461 }; 2886 };
3462 2887
3463 slimbam: dma-controller@91840 2888 slimbam: dma-controller@9184000 {
3464 compatible = "qcom,ba 2889 compatible = "qcom,bam-v1.7.0";
3465 qcom,controlled-remot 2890 qcom,controlled-remotely;
3466 reg = <0x09184000 0x3 2891 reg = <0x09184000 0x32000>;
3467 num-channels = <31>; !! 2892 num-channels = <31>;
3468 interrupts = <GIC_SPI !! 2893 interrupts = <0 164 IRQ_TYPE_LEVEL_HIGH>;
3469 #dma-cells = <1>; 2894 #dma-cells = <1>;
3470 qcom,ee = <1>; 2895 qcom,ee = <1>;
3471 qcom,num-ees = <2>; 2896 qcom,num-ees = <2>;
3472 }; 2897 };
3473 2898
3474 slim_msm: slim-ngd@91c0000 { !! 2899 slim_msm: slim@91c0000 {
3475 compatible = "qcom,sl 2900 compatible = "qcom,slim-ngd-v1.5.0";
3476 reg = <0x091c0000 0x2 !! 2901 reg = <0x091c0000 0x2C000>;
3477 interrupts = <GIC_SPI !! 2902 reg-names = "ctrl";
3478 dmas = <&slimbam 3>, !! 2903 interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>;
3479 dma-names = "rx", "tx !! 2904 dmas = <&slimbam 3>, <&slimbam 4>,
>> 2905 <&slimbam 5>, <&slimbam 6>;
>> 2906 dma-names = "rx", "tx", "tx2", "rx2";
3480 #address-cells = <1>; 2907 #address-cells = <1>;
3481 #size-cells = <0>; 2908 #size-cells = <0>;
>> 2909 ngd@1 {
>> 2910 reg = <1>;
>> 2911 #address-cells = <1>;
>> 2912 #size-cells = <1>;
3482 2913
3483 status = "disabled"; !! 2914 tasha_ifd: tas-ifd {
>> 2915 compatible = "slim217,1a0";
>> 2916 reg = <0 0>;
>> 2917 };
>> 2918
>> 2919 wcd9335: codec@1{
>> 2920 pinctrl-0 = <&cdc_reset_active &wcd_intr_default>;
>> 2921 pinctrl-names = "default";
>> 2922
>> 2923 compatible = "slim217,1a0";
>> 2924 reg = <1 0>;
>> 2925
>> 2926 interrupt-parent = <&tlmm>;
>> 2927 interrupts = <54 IRQ_TYPE_LEVEL_HIGH>,
>> 2928 <53 IRQ_TYPE_LEVEL_HIGH>;
>> 2929 interrupt-names = "intr1", "intr2";
>> 2930 interrupt-controller;
>> 2931 #interrupt-cells = <1>;
>> 2932 reset-gpios = <&tlmm 64 0>;
>> 2933
>> 2934 slim-ifc-dev = <&tasha_ifd>;
>> 2935
>> 2936 #sound-dai-cells = <1>;
>> 2937 };
>> 2938 };
3484 }; 2939 };
3485 2940
3486 adsp_pil: remoteproc@9300000 2941 adsp_pil: remoteproc@9300000 {
3487 compatible = "qcom,ms 2942 compatible = "qcom,msm8996-adsp-pil";
3488 reg = <0x09300000 0x8 2943 reg = <0x09300000 0x80000>;
3489 2944
3490 interrupts-extended = 2945 interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>,
3491 !! 2946 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
3492 !! 2947 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
3493 !! 2948 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
3494 !! 2949 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
3495 interrupt-names = "wd 2950 interrupt-names = "wdog", "fatal", "ready",
3496 "ha 2951 "handover", "stop-ack";
3497 2952
3498 clocks = <&rpmcc RPM_ !! 2953 clocks = <&xo_board>;
3499 clock-names = "xo"; 2954 clock-names = "xo";
3500 2955
3501 memory-region = <&ads !! 2956 memory-region = <&adsp_region>;
3502 2957
3503 qcom,smem-states = <& !! 2958 qcom,smem-states = <&smp2p_adsp_out 0>;
3504 qcom,smem-state-names 2959 qcom,smem-state-names = "stop";
3505 2960
3506 power-domains = <&rpm 2961 power-domains = <&rpmpd MSM8996_VDDCX>;
3507 power-domain-names = 2962 power-domain-names = "cx";
3508 2963
3509 status = "disabled"; 2964 status = "disabled";
3510 2965
3511 glink-edge { <<
3512 interrupts = <<
3513 label = "lpas <<
3514 qcom,remote-p <<
3515 mboxes = <&ap <<
3516 }; <<
3517 <<
3518 <<
3519 smd-edge { 2966 smd-edge {
3520 interrupts = 2967 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
3521 2968
3522 label = "lpas 2969 label = "lpass";
3523 mboxes = <&ap 2970 mboxes = <&apcs_glb 8>;
3524 qcom,smd-edge 2971 qcom,smd-edge = <1>;
3525 qcom,remote-p 2972 qcom,remote-pid = <2>;
3526 !! 2973 #address-cells = <1>;
>> 2974 #size-cells = <0>;
3527 apr { 2975 apr {
3528 power 2976 power-domains = <&gcc HLOS1_VOTE_LPASS_ADSP_GDSC>;
3529 compa 2977 compatible = "qcom,apr-v2";
3530 qcom, 2978 qcom,smd-channels = "apr_audio_svc";
3531 qcom, !! 2979 qcom,apr-domain = <APR_DOMAIN_ADSP>;
3532 #addr 2980 #address-cells = <1>;
3533 #size 2981 #size-cells = <0>;
3534 2982
3535 servi !! 2983 q6core {
3536 2984 reg = <APR_SVC_ADSP_CORE>;
3537 2985 compatible = "qcom,q6core";
3538 }; 2986 };
3539 2987
3540 q6afe !! 2988 q6afe: q6afe {
3541 2989 compatible = "qcom,q6afe";
3542 2990 reg = <APR_SVC_AFE>;
3543 2991 q6afedai: dais {
3544 2992 compatible = "qcom,q6afe-dais";
3545 2993 #address-cells = <1>;
3546 2994 #size-cells = <0>;
3547 2995 #sound-dai-cells = <1>;
3548 !! 2996 hdmi@1 {
3549 2997 reg = <1>;
3550 2998 };
3551 2999 };
3552 }; 3000 };
3553 3001
3554 q6asm !! 3002 q6asm: q6asm {
3555 3003 compatible = "qcom,q6asm";
3556 3004 reg = <APR_SVC_ASM>;
3557 3005 q6asmdai: dais {
3558 3006 compatible = "qcom,q6asm-dais";
3559 3007 #address-cells = <1>;
3560 3008 #size-cells = <0>;
3561 3009 #sound-dai-cells = <1>;
3562 3010 iommus = <&lpass_q6_smmu 1>;
3563 3011 };
3564 }; 3012 };
3565 3013
3566 q6adm !! 3014 q6adm: q6adm {
3567 3015 compatible = "qcom,q6adm";
3568 3016 reg = <APR_SVC_ADM>;
3569 3017 q6routing: routing {
3570 3018 compatible = "qcom,q6adm-routing";
3571 3019 #sound-dai-cells = <0>;
3572 3020 };
3573 }; 3021 };
3574 }; 3022 };
3575 3023
3576 fastrpc { <<
3577 compa <<
3578 qcom, <<
3579 label <<
3580 qcom, <<
3581 #addr <<
3582 #size <<
3583 <<
3584 cb@5 <<
3585 <<
3586 <<
3587 <<
3588 }; <<
3589 <<
3590 cb@6 <<
3591 <<
3592 <<
3593 <<
3594 }; <<
3595 <<
3596 cb@7 <<
3597 <<
3598 <<
3599 <<
3600 }; <<
3601 <<
3602 cb@8 <<
3603 <<
3604 <<
3605 <<
3606 }; <<
3607 <<
3608 cb@9 <<
3609 <<
3610 <<
3611 <<
3612 }; <<
3613 <<
3614 cb@10 <<
3615 <<
3616 <<
3617 <<
3618 }; <<
3619 <<
3620 cb@11 <<
3621 <<
3622 <<
3623 <<
3624 }; <<
3625 <<
3626 cb@12 <<
3627 <<
3628 <<
3629 <<
3630 }; <<
3631 }; <<
3632 }; 3024 };
3633 }; 3025 };
3634 3026
3635 apcs_glb: mailbox@9820000 { 3027 apcs_glb: mailbox@9820000 {
3636 compatible = "qcom,ms 3028 compatible = "qcom,msm8996-apcs-hmss-global";
3637 reg = <0x09820000 0x1 3029 reg = <0x09820000 0x1000>;
3638 3030
3639 #mbox-cells = <1>; 3031 #mbox-cells = <1>;
3640 #clock-cells = <0>; <<
3641 }; 3032 };
3642 3033
3643 timer@9840000 { 3034 timer@9840000 {
3644 #address-cells = <1>; 3035 #address-cells = <1>;
3645 #size-cells = <1>; 3036 #size-cells = <1>;
3646 ranges; 3037 ranges;
3647 compatible = "arm,arm 3038 compatible = "arm,armv7-timer-mem";
3648 reg = <0x09840000 0x1 3039 reg = <0x09840000 0x1000>;
3649 clock-frequency = <19 3040 clock-frequency = <19200000>;
3650 3041
3651 frame@9850000 { 3042 frame@9850000 {
3652 frame-number 3043 frame-number = <0>;
3653 interrupts = 3044 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
3654 3045 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
3655 reg = <0x0985 3046 reg = <0x09850000 0x1000>,
3656 <0x0986 3047 <0x09860000 0x1000>;
3657 }; 3048 };
3658 3049
3659 frame@9870000 { 3050 frame@9870000 {
3660 frame-number 3051 frame-number = <1>;
3661 interrupts = 3052 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
3662 reg = <0x0987 3053 reg = <0x09870000 0x1000>;
3663 status = "dis 3054 status = "disabled";
3664 }; 3055 };
3665 3056
3666 frame@9880000 { 3057 frame@9880000 {
3667 frame-number 3058 frame-number = <2>;
3668 interrupts = 3059 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
3669 reg = <0x0988 3060 reg = <0x09880000 0x1000>;
3670 status = "dis 3061 status = "disabled";
3671 }; 3062 };
3672 3063
3673 frame@9890000 { 3064 frame@9890000 {
3674 frame-number 3065 frame-number = <3>;
3675 interrupts = 3066 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
3676 reg = <0x0989 3067 reg = <0x09890000 0x1000>;
3677 status = "dis 3068 status = "disabled";
3678 }; 3069 };
3679 3070
3680 frame@98a0000 { 3071 frame@98a0000 {
3681 frame-number 3072 frame-number = <4>;
3682 interrupts = 3073 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
3683 reg = <0x098a 3074 reg = <0x098a0000 0x1000>;
3684 status = "dis 3075 status = "disabled";
3685 }; 3076 };
3686 3077
3687 frame@98b0000 { 3078 frame@98b0000 {
3688 frame-number 3079 frame-number = <5>;
3689 interrupts = 3080 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
3690 reg = <0x098b 3081 reg = <0x098b0000 0x1000>;
3691 status = "dis 3082 status = "disabled";
3692 }; 3083 };
3693 3084
3694 frame@98c0000 { 3085 frame@98c0000 {
3695 frame-number 3086 frame-number = <6>;
3696 interrupts = 3087 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
3697 reg = <0x098c 3088 reg = <0x098c0000 0x1000>;
3698 status = "dis 3089 status = "disabled";
3699 }; 3090 };
3700 }; 3091 };
3701 3092
3702 saw3: syscon@9a10000 { 3093 saw3: syscon@9a10000 {
3703 compatible = "syscon" 3094 compatible = "syscon";
3704 reg = <0x09a10000 0x1 3095 reg = <0x09a10000 0x1000>;
3705 }; 3096 };
3706 3097
3707 cbf: clock-controller@9a11000 <<
3708 compatible = "qcom,ms <<
3709 reg = <0x09a11000 0x1 <<
3710 clocks = <&rpmcc RPM_ <<
3711 #clock-cells = <0>; <<
3712 #interconnect-cells = <<
3713 }; <<
3714 <<
3715 intc: interrupt-controller@9b 3098 intc: interrupt-controller@9bc0000 {
3716 compatible = "qcom,ms 3099 compatible = "qcom,msm8996-gic-v3", "arm,gic-v3";
3717 #interrupt-cells = <3 3100 #interrupt-cells = <3>;
3718 interrupt-controller; 3101 interrupt-controller;
3719 #redistributor-region 3102 #redistributor-regions = <1>;
3720 redistributor-stride 3103 redistributor-stride = <0x0 0x40000>;
3721 reg = <0x09bc0000 0x1 3104 reg = <0x09bc0000 0x10000>,
3722 <0x09c00000 0x1 3105 <0x09c00000 0x100000>;
3723 interrupts = <GIC_PPI 3106 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
3724 }; 3107 };
3725 }; 3108 };
3726 3109
3727 sound: sound { 3110 sound: sound {
3728 }; 3111 };
3729 3112
3730 thermal-zones { 3113 thermal-zones {
3731 cpu0-thermal { 3114 cpu0-thermal {
3732 polling-delay-passive 3115 polling-delay-passive = <250>;
>> 3116 polling-delay = <1000>;
3733 3117
3734 thermal-sensors = <&t 3118 thermal-sensors = <&tsens0 3>;
3735 3119
3736 trips { 3120 trips {
3737 cpu0_alert0: 3121 cpu0_alert0: trip-point0 {
3738 tempe 3122 temperature = <75000>;
3739 hyste 3123 hysteresis = <2000>;
3740 type 3124 type = "passive";
3741 }; 3125 };
3742 3126
3743 cpu0_crit: cp !! 3127 cpu0_crit: cpu_crit {
3744 tempe 3128 temperature = <110000>;
3745 hyste 3129 hysteresis = <2000>;
3746 type 3130 type = "critical";
3747 }; 3131 };
3748 }; 3132 };
3749 }; 3133 };
3750 3134
3751 cpu1-thermal { 3135 cpu1-thermal {
3752 polling-delay-passive 3136 polling-delay-passive = <250>;
>> 3137 polling-delay = <1000>;
3753 3138
3754 thermal-sensors = <&t 3139 thermal-sensors = <&tsens0 5>;
3755 3140
3756 trips { 3141 trips {
3757 cpu1_alert0: 3142 cpu1_alert0: trip-point0 {
3758 tempe 3143 temperature = <75000>;
3759 hyste 3144 hysteresis = <2000>;
3760 type 3145 type = "passive";
3761 }; 3146 };
3762 3147
3763 cpu1_crit: cp !! 3148 cpu1_crit: cpu_crit {
3764 tempe 3149 temperature = <110000>;
3765 hyste 3150 hysteresis = <2000>;
3766 type 3151 type = "critical";
3767 }; 3152 };
3768 }; 3153 };
3769 }; 3154 };
3770 3155
3771 cpu2-thermal { 3156 cpu2-thermal {
3772 polling-delay-passive 3157 polling-delay-passive = <250>;
>> 3158 polling-delay = <1000>;
3773 3159
3774 thermal-sensors = <&t 3160 thermal-sensors = <&tsens0 8>;
3775 3161
3776 trips { 3162 trips {
3777 cpu2_alert0: 3163 cpu2_alert0: trip-point0 {
3778 tempe 3164 temperature = <75000>;
3779 hyste 3165 hysteresis = <2000>;
3780 type 3166 type = "passive";
3781 }; 3167 };
3782 3168
3783 cpu2_crit: cp !! 3169 cpu2_crit: cpu_crit {
3784 tempe 3170 temperature = <110000>;
3785 hyste 3171 hysteresis = <2000>;
3786 type 3172 type = "critical";
3787 }; 3173 };
3788 }; 3174 };
3789 }; 3175 };
3790 3176
3791 cpu3-thermal { 3177 cpu3-thermal {
3792 polling-delay-passive 3178 polling-delay-passive = <250>;
>> 3179 polling-delay = <1000>;
3793 3180
3794 thermal-sensors = <&t 3181 thermal-sensors = <&tsens0 10>;
3795 3182
3796 trips { 3183 trips {
3797 cpu3_alert0: 3184 cpu3_alert0: trip-point0 {
3798 tempe 3185 temperature = <75000>;
3799 hyste 3186 hysteresis = <2000>;
3800 type 3187 type = "passive";
3801 }; 3188 };
3802 3189
3803 cpu3_crit: cp !! 3190 cpu3_crit: cpu_crit {
3804 tempe 3191 temperature = <110000>;
3805 hyste 3192 hysteresis = <2000>;
3806 type 3193 type = "critical";
3807 }; 3194 };
3808 }; 3195 };
3809 }; 3196 };
3810 3197
3811 gpu-top-thermal { !! 3198 gpu-thermal-top {
3812 polling-delay-passive 3199 polling-delay-passive = <250>;
>> 3200 polling-delay = <1000>;
3813 3201
3814 thermal-sensors = <&t 3202 thermal-sensors = <&tsens1 6>;
3815 3203
3816 trips { 3204 trips {
3817 gpu1_alert0: 3205 gpu1_alert0: trip-point0 {
3818 tempe 3206 temperature = <90000>;
3819 hyste 3207 hysteresis = <2000>;
3820 type !! 3208 type = "hot";
3821 }; <<
3822 }; <<
3823 <<
3824 cooling-maps { <<
3825 map0 { <<
3826 trip <<
3827 cooli <<
3828 }; 3209 };
3829 }; 3210 };
3830 }; 3211 };
3831 3212
3832 gpu-bottom-thermal { !! 3213 gpu-thermal-bottom {
3833 polling-delay-passive 3214 polling-delay-passive = <250>;
>> 3215 polling-delay = <1000>;
3834 3216
3835 thermal-sensors = <&t 3217 thermal-sensors = <&tsens1 7>;
3836 3218
3837 trips { 3219 trips {
3838 gpu2_alert0: 3220 gpu2_alert0: trip-point0 {
3839 tempe 3221 temperature = <90000>;
3840 hyste 3222 hysteresis = <2000>;
3841 type !! 3223 type = "hot";
3842 }; <<
3843 }; <<
3844 <<
3845 cooling-maps { <<
3846 map0 { <<
3847 trip <<
3848 cooli <<
3849 }; 3224 };
3850 }; 3225 };
3851 }; 3226 };
3852 3227
3853 m4m-thermal { 3228 m4m-thermal {
3854 polling-delay-passive 3229 polling-delay-passive = <250>;
>> 3230 polling-delay = <1000>;
3855 3231
3856 thermal-sensors = <&t 3232 thermal-sensors = <&tsens0 1>;
3857 3233
3858 trips { 3234 trips {
3859 m4m_alert0: t 3235 m4m_alert0: trip-point0 {
3860 tempe 3236 temperature = <90000>;
3861 hyste 3237 hysteresis = <2000>;
3862 type 3238 type = "hot";
3863 }; 3239 };
3864 }; 3240 };
3865 }; 3241 };
3866 3242
3867 l3-or-venus-thermal { 3243 l3-or-venus-thermal {
3868 polling-delay-passive 3244 polling-delay-passive = <250>;
>> 3245 polling-delay = <1000>;
3869 3246
3870 thermal-sensors = <&t 3247 thermal-sensors = <&tsens0 2>;
3871 3248
3872 trips { 3249 trips {
3873 l3_or_venus_a 3250 l3_or_venus_alert0: trip-point0 {
3874 tempe 3251 temperature = <90000>;
3875 hyste 3252 hysteresis = <2000>;
3876 type 3253 type = "hot";
3877 }; 3254 };
3878 }; 3255 };
3879 }; 3256 };
3880 3257
3881 cluster0-l2-thermal { 3258 cluster0-l2-thermal {
3882 polling-delay-passive 3259 polling-delay-passive = <250>;
>> 3260 polling-delay = <1000>;
3883 3261
3884 thermal-sensors = <&t 3262 thermal-sensors = <&tsens0 7>;
3885 3263
3886 trips { 3264 trips {
3887 cluster0_l2_a 3265 cluster0_l2_alert0: trip-point0 {
3888 tempe 3266 temperature = <90000>;
3889 hyste 3267 hysteresis = <2000>;
3890 type 3268 type = "hot";
3891 }; 3269 };
3892 }; 3270 };
3893 }; 3271 };
3894 3272
3895 cluster1-l2-thermal { 3273 cluster1-l2-thermal {
3896 polling-delay-passive 3274 polling-delay-passive = <250>;
>> 3275 polling-delay = <1000>;
3897 3276
3898 thermal-sensors = <&t 3277 thermal-sensors = <&tsens0 12>;
3899 3278
3900 trips { 3279 trips {
3901 cluster1_l2_a 3280 cluster1_l2_alert0: trip-point0 {
3902 tempe 3281 temperature = <90000>;
3903 hyste 3282 hysteresis = <2000>;
3904 type 3283 type = "hot";
3905 }; 3284 };
3906 }; 3285 };
3907 }; 3286 };
3908 3287
3909 camera-thermal { 3288 camera-thermal {
3910 polling-delay-passive 3289 polling-delay-passive = <250>;
>> 3290 polling-delay = <1000>;
3911 3291
3912 thermal-sensors = <&t 3292 thermal-sensors = <&tsens1 1>;
3913 3293
3914 trips { 3294 trips {
3915 camera_alert0 3295 camera_alert0: trip-point0 {
3916 tempe 3296 temperature = <90000>;
3917 hyste 3297 hysteresis = <2000>;
3918 type 3298 type = "hot";
3919 }; 3299 };
3920 }; 3300 };
3921 }; 3301 };
3922 3302
3923 q6-dsp-thermal { 3303 q6-dsp-thermal {
3924 polling-delay-passive 3304 polling-delay-passive = <250>;
>> 3305 polling-delay = <1000>;
3925 3306
3926 thermal-sensors = <&t 3307 thermal-sensors = <&tsens1 2>;
3927 3308
3928 trips { 3309 trips {
3929 q6_dsp_alert0 3310 q6_dsp_alert0: trip-point0 {
3930 tempe 3311 temperature = <90000>;
3931 hyste 3312 hysteresis = <2000>;
3932 type 3313 type = "hot";
3933 }; 3314 };
3934 }; 3315 };
3935 }; 3316 };
3936 3317
3937 mem-thermal { 3318 mem-thermal {
3938 polling-delay-passive 3319 polling-delay-passive = <250>;
>> 3320 polling-delay = <1000>;
3939 3321
3940 thermal-sensors = <&t 3322 thermal-sensors = <&tsens1 3>;
3941 3323
3942 trips { 3324 trips {
3943 mem_alert0: t 3325 mem_alert0: trip-point0 {
3944 tempe 3326 temperature = <90000>;
3945 hyste 3327 hysteresis = <2000>;
3946 type 3328 type = "hot";
3947 }; 3329 };
3948 }; 3330 };
3949 }; 3331 };
3950 3332
3951 modemtx-thermal { 3333 modemtx-thermal {
3952 polling-delay-passive 3334 polling-delay-passive = <250>;
>> 3335 polling-delay = <1000>;
3953 3336
3954 thermal-sensors = <&t 3337 thermal-sensors = <&tsens1 4>;
3955 3338
3956 trips { 3339 trips {
3957 modemtx_alert 3340 modemtx_alert0: trip-point0 {
3958 tempe 3341 temperature = <90000>;
3959 hyste 3342 hysteresis = <2000>;
3960 type 3343 type = "hot";
3961 }; 3344 };
3962 }; 3345 };
3963 }; 3346 };
3964 }; 3347 };
3965 3348
3966 timer { 3349 timer {
3967 compatible = "arm,armv8-timer 3350 compatible = "arm,armv8-timer";
3968 interrupts = <GIC_PPI 13 IRQ_ 3351 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
3969 <GIC_PPI 14 IRQ_ 3352 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
3970 <GIC_PPI 11 IRQ_ 3353 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
3971 <GIC_PPI 10 IRQ_ 3354 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
3972 }; 3355 };
3973 }; 3356 };
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