1 // SPDX-License-Identifier: GPL-2.0-only 1 // SPDX-License-Identifier: GPL-2.0-only
2 /* !! 2 /* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
3 * Copyright (c) 2014-2015, The Linux Foundati <<
4 */ 3 */
5 4
6 #include <dt-bindings/interrupt-controller/arm 5 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,gcc-msm8996.h 6 #include <dt-bindings/clock/qcom,gcc-msm8996.h>
8 #include <dt-bindings/clock/qcom,mmcc-msm8996. 7 #include <dt-bindings/clock/qcom,mmcc-msm8996.h>
9 #include <dt-bindings/clock/qcom,rpmcc.h> 8 #include <dt-bindings/clock/qcom,rpmcc.h>
10 #include <dt-bindings/interconnect/qcom,msm899 <<
11 #include <dt-bindings/interconnect/qcom,msm899 <<
12 #include <dt-bindings/firmware/qcom,scm.h> <<
13 #include <dt-bindings/gpio/gpio.h> <<
14 #include <dt-bindings/power/qcom-rpmpd.h> 9 #include <dt-bindings/power/qcom-rpmpd.h>
15 #include <dt-bindings/soc/qcom,apr.h> 10 #include <dt-bindings/soc/qcom,apr.h>
16 #include <dt-bindings/thermal/thermal.h> 11 #include <dt-bindings/thermal/thermal.h>
17 12
18 / { 13 / {
19 interrupt-parent = <&intc>; 14 interrupt-parent = <&intc>;
20 15
21 #address-cells = <2>; 16 #address-cells = <2>;
22 #size-cells = <2>; 17 #size-cells = <2>;
23 18
24 chosen { }; 19 chosen { };
25 20
26 clocks { 21 clocks {
27 xo_board: xo-board { 22 xo_board: xo-board {
28 compatible = "fixed-cl 23 compatible = "fixed-clock";
29 #clock-cells = <0>; 24 #clock-cells = <0>;
30 clock-frequency = <192 25 clock-frequency = <19200000>;
31 clock-output-names = " 26 clock-output-names = "xo_board";
32 }; 27 };
33 28
34 sleep_clk: sleep-clk { 29 sleep_clk: sleep-clk {
35 compatible = "fixed-cl 30 compatible = "fixed-clock";
36 #clock-cells = <0>; 31 #clock-cells = <0>;
37 clock-frequency = <327 32 clock-frequency = <32764>;
38 clock-output-names = " 33 clock-output-names = "sleep_clk";
39 }; 34 };
40 }; 35 };
41 36
42 cpus { 37 cpus {
43 #address-cells = <2>; 38 #address-cells = <2>;
44 #size-cells = <0>; 39 #size-cells = <0>;
45 40
46 CPU0: cpu@0 { 41 CPU0: cpu@0 {
47 device_type = "cpu"; 42 device_type = "cpu";
48 compatible = "qcom,kry 43 compatible = "qcom,kryo";
49 reg = <0x0 0x0>; 44 reg = <0x0 0x0>;
50 enable-method = "psci" 45 enable-method = "psci";
51 cpu-idle-states = <&CP 46 cpu-idle-states = <&CPU_SLEEP_0>;
52 capacity-dmips-mhz = < 47 capacity-dmips-mhz = <1024>;
53 clocks = <&kryocc 0>; 48 clocks = <&kryocc 0>;
54 interconnects = <&cbf <<
55 operating-points-v2 = 49 operating-points-v2 = <&cluster0_opp>;
56 #cooling-cells = <2>; 50 #cooling-cells = <2>;
57 next-level-cache = <&L 51 next-level-cache = <&L2_0>;
58 L2_0: l2-cache { 52 L2_0: l2-cache {
59 compatible = " !! 53 compatible = "cache";
60 cache-level = !! 54 cache-level = <2>;
61 cache-unified; <<
62 }; 55 };
63 }; 56 };
64 57
65 CPU1: cpu@1 { 58 CPU1: cpu@1 {
66 device_type = "cpu"; 59 device_type = "cpu";
67 compatible = "qcom,kry 60 compatible = "qcom,kryo";
68 reg = <0x0 0x1>; 61 reg = <0x0 0x1>;
69 enable-method = "psci" 62 enable-method = "psci";
70 cpu-idle-states = <&CP 63 cpu-idle-states = <&CPU_SLEEP_0>;
71 capacity-dmips-mhz = < 64 capacity-dmips-mhz = <1024>;
72 clocks = <&kryocc 0>; 65 clocks = <&kryocc 0>;
73 interconnects = <&cbf <<
74 operating-points-v2 = 66 operating-points-v2 = <&cluster0_opp>;
75 #cooling-cells = <2>; 67 #cooling-cells = <2>;
76 next-level-cache = <&L 68 next-level-cache = <&L2_0>;
77 }; 69 };
78 70
79 CPU2: cpu@100 { 71 CPU2: cpu@100 {
80 device_type = "cpu"; 72 device_type = "cpu";
81 compatible = "qcom,kry 73 compatible = "qcom,kryo";
82 reg = <0x0 0x100>; 74 reg = <0x0 0x100>;
83 enable-method = "psci" 75 enable-method = "psci";
84 cpu-idle-states = <&CP 76 cpu-idle-states = <&CPU_SLEEP_0>;
85 capacity-dmips-mhz = < 77 capacity-dmips-mhz = <1024>;
86 clocks = <&kryocc 1>; 78 clocks = <&kryocc 1>;
87 interconnects = <&cbf <<
88 operating-points-v2 = 79 operating-points-v2 = <&cluster1_opp>;
89 #cooling-cells = <2>; 80 #cooling-cells = <2>;
90 next-level-cache = <&L 81 next-level-cache = <&L2_1>;
91 L2_1: l2-cache { 82 L2_1: l2-cache {
92 compatible = " !! 83 compatible = "cache";
93 cache-level = !! 84 cache-level = <2>;
94 cache-unified; <<
95 }; 85 };
96 }; 86 };
97 87
98 CPU3: cpu@101 { 88 CPU3: cpu@101 {
99 device_type = "cpu"; 89 device_type = "cpu";
100 compatible = "qcom,kry 90 compatible = "qcom,kryo";
101 reg = <0x0 0x101>; 91 reg = <0x0 0x101>;
102 enable-method = "psci" 92 enable-method = "psci";
103 cpu-idle-states = <&CP 93 cpu-idle-states = <&CPU_SLEEP_0>;
104 capacity-dmips-mhz = < 94 capacity-dmips-mhz = <1024>;
105 clocks = <&kryocc 1>; 95 clocks = <&kryocc 1>;
106 interconnects = <&cbf <<
107 operating-points-v2 = 96 operating-points-v2 = <&cluster1_opp>;
108 #cooling-cells = <2>; 97 #cooling-cells = <2>;
109 next-level-cache = <&L 98 next-level-cache = <&L2_1>;
110 }; 99 };
111 100
112 cpu-map { 101 cpu-map {
113 cluster0 { 102 cluster0 {
114 core0 { 103 core0 {
115 cpu = 104 cpu = <&CPU0>;
116 }; 105 };
117 106
118 core1 { 107 core1 {
119 cpu = 108 cpu = <&CPU1>;
120 }; 109 };
121 }; 110 };
122 111
123 cluster1 { 112 cluster1 {
124 core0 { 113 core0 {
125 cpu = 114 cpu = <&CPU2>;
126 }; 115 };
127 116
128 core1 { 117 core1 {
129 cpu = 118 cpu = <&CPU3>;
130 }; 119 };
131 }; 120 };
132 }; 121 };
133 122
134 idle-states { 123 idle-states {
135 entry-method = "psci"; 124 entry-method = "psci";
136 125
137 CPU_SLEEP_0: cpu-sleep 126 CPU_SLEEP_0: cpu-sleep-0 {
138 compatible = " 127 compatible = "arm,idle-state";
139 idle-state-nam 128 idle-state-name = "standalone-power-collapse";
140 arm,psci-suspe 129 arm,psci-suspend-param = <0x00000004>;
141 entry-latency- 130 entry-latency-us = <130>;
142 exit-latency-u 131 exit-latency-us = <80>;
143 min-residency- 132 min-residency-us = <300>;
144 }; 133 };
145 }; 134 };
146 }; 135 };
147 136
148 cluster0_opp: opp-table-cluster0 { !! 137 cluster0_opp: opp_table0 {
149 compatible = "operating-points 138 compatible = "operating-points-v2-kryo-cpu";
150 nvmem-cells = <&speedbin_efuse 139 nvmem-cells = <&speedbin_efuse>;
151 opp-shared; 140 opp-shared;
152 141
153 /* Nominal fmax for now */ 142 /* Nominal fmax for now */
154 opp-307200000 { 143 opp-307200000 {
155 opp-hz = /bits/ 64 <30 144 opp-hz = /bits/ 64 <307200000>;
156 opp-supported-hw = <0x !! 145 opp-supported-hw = <0x77>;
157 clock-latency-ns = <20 146 clock-latency-ns = <200000>;
158 opp-peak-kBps = <30720 <<
159 }; 147 };
160 opp-422400000 { 148 opp-422400000 {
161 opp-hz = /bits/ 64 <42 149 opp-hz = /bits/ 64 <422400000>;
162 opp-supported-hw = <0x !! 150 opp-supported-hw = <0x77>;
163 clock-latency-ns = <20 151 clock-latency-ns = <200000>;
164 opp-peak-kBps = <30720 <<
165 }; 152 };
166 opp-480000000 { 153 opp-480000000 {
167 opp-hz = /bits/ 64 <48 154 opp-hz = /bits/ 64 <480000000>;
168 opp-supported-hw = <0x !! 155 opp-supported-hw = <0x77>;
169 clock-latency-ns = <20 156 clock-latency-ns = <200000>;
170 opp-peak-kBps = <30720 <<
171 }; 157 };
172 opp-556800000 { 158 opp-556800000 {
173 opp-hz = /bits/ 64 <55 159 opp-hz = /bits/ 64 <556800000>;
174 opp-supported-hw = <0x !! 160 opp-supported-hw = <0x77>;
175 clock-latency-ns = <20 161 clock-latency-ns = <200000>;
176 opp-peak-kBps = <30720 <<
177 }; 162 };
178 opp-652800000 { 163 opp-652800000 {
179 opp-hz = /bits/ 64 <65 164 opp-hz = /bits/ 64 <652800000>;
180 opp-supported-hw = <0x !! 165 opp-supported-hw = <0x77>;
181 clock-latency-ns = <20 166 clock-latency-ns = <200000>;
182 opp-peak-kBps = <38400 <<
183 }; 167 };
184 opp-729600000 { 168 opp-729600000 {
185 opp-hz = /bits/ 64 <72 169 opp-hz = /bits/ 64 <729600000>;
186 opp-supported-hw = <0x !! 170 opp-supported-hw = <0x77>;
187 clock-latency-ns = <20 171 clock-latency-ns = <200000>;
188 opp-peak-kBps = <46080 <<
189 }; 172 };
190 opp-844800000 { 173 opp-844800000 {
191 opp-hz = /bits/ 64 <84 174 opp-hz = /bits/ 64 <844800000>;
192 opp-supported-hw = <0x !! 175 opp-supported-hw = <0x77>;
193 clock-latency-ns = <20 176 clock-latency-ns = <200000>;
194 opp-peak-kBps = <53760 <<
195 }; 177 };
196 opp-960000000 { 178 opp-960000000 {
197 opp-hz = /bits/ 64 <96 179 opp-hz = /bits/ 64 <960000000>;
198 opp-supported-hw = <0x !! 180 opp-supported-hw = <0x77>;
199 clock-latency-ns = <20 181 clock-latency-ns = <200000>;
200 opp-peak-kBps = <67200 <<
201 }; 182 };
202 opp-1036800000 { 183 opp-1036800000 {
203 opp-hz = /bits/ 64 <10 184 opp-hz = /bits/ 64 <1036800000>;
204 opp-supported-hw = <0x !! 185 opp-supported-hw = <0x77>;
205 clock-latency-ns = <20 186 clock-latency-ns = <200000>;
206 opp-peak-kBps = <67200 <<
207 }; 187 };
208 opp-1113600000 { 188 opp-1113600000 {
209 opp-hz = /bits/ 64 <11 189 opp-hz = /bits/ 64 <1113600000>;
210 opp-supported-hw = <0x !! 190 opp-supported-hw = <0x77>;
211 clock-latency-ns = <20 191 clock-latency-ns = <200000>;
212 opp-peak-kBps = <82560 <<
213 }; 192 };
214 opp-1190400000 { 193 opp-1190400000 {
215 opp-hz = /bits/ 64 <11 194 opp-hz = /bits/ 64 <1190400000>;
216 opp-supported-hw = <0x !! 195 opp-supported-hw = <0x77>;
217 clock-latency-ns = <20 196 clock-latency-ns = <200000>;
218 opp-peak-kBps = <82560 <<
219 }; 197 };
220 opp-1228800000 { 198 opp-1228800000 {
221 opp-hz = /bits/ 64 <12 199 opp-hz = /bits/ 64 <1228800000>;
222 opp-supported-hw = <0x !! 200 opp-supported-hw = <0x77>;
223 clock-latency-ns = <20 201 clock-latency-ns = <200000>;
224 opp-peak-kBps = <90240 <<
225 }; 202 };
226 opp-1324800000 { 203 opp-1324800000 {
227 opp-hz = /bits/ 64 <13 204 opp-hz = /bits/ 64 <1324800000>;
228 opp-supported-hw = <0x !! 205 opp-supported-hw = <0x77>;
229 clock-latency-ns = <20 206 clock-latency-ns = <200000>;
230 opp-peak-kBps = <10560 <<
231 }; <<
232 opp-1363200000 { <<
233 opp-hz = /bits/ 64 <13 <<
234 opp-supported-hw = <0x <<
235 clock-latency-ns = <20 <<
236 opp-peak-kBps = <11328 <<
237 }; 207 };
238 opp-1401600000 { 208 opp-1401600000 {
239 opp-hz = /bits/ 64 <14 209 opp-hz = /bits/ 64 <1401600000>;
240 opp-supported-hw = <0x !! 210 opp-supported-hw = <0x77>;
241 clock-latency-ns = <20 211 clock-latency-ns = <200000>;
242 opp-peak-kBps = <11328 <<
243 }; 212 };
244 opp-1478400000 { 213 opp-1478400000 {
245 opp-hz = /bits/ 64 <14 214 opp-hz = /bits/ 64 <1478400000>;
246 opp-supported-hw = <0x !! 215 opp-supported-hw = <0x77>;
247 clock-latency-ns = <20 <<
248 opp-peak-kBps = <11904 <<
249 }; <<
250 opp-1497600000 { <<
251 opp-hz = /bits/ 64 <14 <<
252 opp-supported-hw = <0x <<
253 clock-latency-ns = <20 216 clock-latency-ns = <200000>;
254 opp-peak-kBps = <13056 <<
255 }; 217 };
256 opp-1593600000 { 218 opp-1593600000 {
257 opp-hz = /bits/ 64 <15 219 opp-hz = /bits/ 64 <1593600000>;
258 opp-supported-hw = <0x !! 220 opp-supported-hw = <0x77>;
259 clock-latency-ns = <20 221 clock-latency-ns = <200000>;
260 opp-peak-kBps = <13824 <<
261 }; 222 };
262 }; 223 };
263 224
264 cluster1_opp: opp-table-cluster1 { !! 225 cluster1_opp: opp_table1 {
265 compatible = "operating-points 226 compatible = "operating-points-v2-kryo-cpu";
266 nvmem-cells = <&speedbin_efuse 227 nvmem-cells = <&speedbin_efuse>;
267 opp-shared; 228 opp-shared;
268 229
269 /* Nominal fmax for now */ 230 /* Nominal fmax for now */
270 opp-307200000 { 231 opp-307200000 {
271 opp-hz = /bits/ 64 <30 232 opp-hz = /bits/ 64 <307200000>;
272 opp-supported-hw = <0x !! 233 opp-supported-hw = <0x77>;
273 clock-latency-ns = <20 234 clock-latency-ns = <200000>;
274 opp-peak-kBps = <30720 <<
275 }; 235 };
276 opp-403200000 { 236 opp-403200000 {
277 opp-hz = /bits/ 64 <40 237 opp-hz = /bits/ 64 <403200000>;
278 opp-supported-hw = <0x !! 238 opp-supported-hw = <0x77>;
279 clock-latency-ns = <20 239 clock-latency-ns = <200000>;
280 opp-peak-kBps = <30720 <<
281 }; 240 };
282 opp-480000000 { 241 opp-480000000 {
283 opp-hz = /bits/ 64 <48 242 opp-hz = /bits/ 64 <480000000>;
284 opp-supported-hw = <0x !! 243 opp-supported-hw = <0x77>;
285 clock-latency-ns = <20 244 clock-latency-ns = <200000>;
286 opp-peak-kBps = <30720 <<
287 }; 245 };
288 opp-556800000 { 246 opp-556800000 {
289 opp-hz = /bits/ 64 <55 247 opp-hz = /bits/ 64 <556800000>;
290 opp-supported-hw = <0x !! 248 opp-supported-hw = <0x77>;
291 clock-latency-ns = <20 249 clock-latency-ns = <200000>;
292 opp-peak-kBps = <30720 <<
293 }; 250 };
294 opp-652800000 { 251 opp-652800000 {
295 opp-hz = /bits/ 64 <65 252 opp-hz = /bits/ 64 <652800000>;
296 opp-supported-hw = <0x !! 253 opp-supported-hw = <0x77>;
297 clock-latency-ns = <20 254 clock-latency-ns = <200000>;
298 opp-peak-kBps = <30720 <<
299 }; 255 };
300 opp-729600000 { 256 opp-729600000 {
301 opp-hz = /bits/ 64 <72 257 opp-hz = /bits/ 64 <729600000>;
302 opp-supported-hw = <0x !! 258 opp-supported-hw = <0x77>;
303 clock-latency-ns = <20 259 clock-latency-ns = <200000>;
304 opp-peak-kBps = <30720 <<
305 }; 260 };
306 opp-806400000 { 261 opp-806400000 {
307 opp-hz = /bits/ 64 <80 262 opp-hz = /bits/ 64 <806400000>;
308 opp-supported-hw = <0x !! 263 opp-supported-hw = <0x77>;
309 clock-latency-ns = <20 264 clock-latency-ns = <200000>;
310 opp-peak-kBps = <38400 <<
311 }; 265 };
312 opp-883200000 { 266 opp-883200000 {
313 opp-hz = /bits/ 64 <88 267 opp-hz = /bits/ 64 <883200000>;
314 opp-supported-hw = <0x !! 268 opp-supported-hw = <0x77>;
315 clock-latency-ns = <20 269 clock-latency-ns = <200000>;
316 opp-peak-kBps = <46080 <<
317 }; 270 };
318 opp-940800000 { 271 opp-940800000 {
319 opp-hz = /bits/ 64 <94 272 opp-hz = /bits/ 64 <940800000>;
320 opp-supported-hw = <0x !! 273 opp-supported-hw = <0x77>;
321 clock-latency-ns = <20 274 clock-latency-ns = <200000>;
322 opp-peak-kBps = <53760 <<
323 }; 275 };
324 opp-1036800000 { 276 opp-1036800000 {
325 opp-hz = /bits/ 64 <10 277 opp-hz = /bits/ 64 <1036800000>;
326 opp-supported-hw = <0x !! 278 opp-supported-hw = <0x77>;
327 clock-latency-ns = <20 279 clock-latency-ns = <200000>;
328 opp-peak-kBps = <59520 <<
329 }; 280 };
330 opp-1113600000 { 281 opp-1113600000 {
331 opp-hz = /bits/ 64 <11 282 opp-hz = /bits/ 64 <1113600000>;
332 opp-supported-hw = <0x !! 283 opp-supported-hw = <0x77>;
333 clock-latency-ns = <20 284 clock-latency-ns = <200000>;
334 opp-peak-kBps = <67200 <<
335 }; 285 };
336 opp-1190400000 { 286 opp-1190400000 {
337 opp-hz = /bits/ 64 <11 287 opp-hz = /bits/ 64 <1190400000>;
338 opp-supported-hw = <0x !! 288 opp-supported-hw = <0x77>;
339 clock-latency-ns = <20 289 clock-latency-ns = <200000>;
340 opp-peak-kBps = <67200 <<
341 }; 290 };
342 opp-1248000000 { 291 opp-1248000000 {
343 opp-hz = /bits/ 64 <12 292 opp-hz = /bits/ 64 <1248000000>;
344 opp-supported-hw = <0x !! 293 opp-supported-hw = <0x77>;
345 clock-latency-ns = <20 294 clock-latency-ns = <200000>;
346 opp-peak-kBps = <74880 <<
347 }; 295 };
348 opp-1324800000 { 296 opp-1324800000 {
349 opp-hz = /bits/ 64 <13 297 opp-hz = /bits/ 64 <1324800000>;
350 opp-supported-hw = <0x !! 298 opp-supported-hw = <0x77>;
351 clock-latency-ns = <20 299 clock-latency-ns = <200000>;
352 opp-peak-kBps = <82560 <<
353 }; 300 };
354 opp-1401600000 { 301 opp-1401600000 {
355 opp-hz = /bits/ 64 <14 302 opp-hz = /bits/ 64 <1401600000>;
356 opp-supported-hw = <0x !! 303 opp-supported-hw = <0x77>;
357 clock-latency-ns = <20 304 clock-latency-ns = <200000>;
358 opp-peak-kBps = <90240 <<
359 }; 305 };
360 opp-1478400000 { 306 opp-1478400000 {
361 opp-hz = /bits/ 64 <14 307 opp-hz = /bits/ 64 <1478400000>;
362 opp-supported-hw = <0x !! 308 opp-supported-hw = <0x77>;
363 clock-latency-ns = <20 309 clock-latency-ns = <200000>;
364 opp-peak-kBps = <97920 <<
365 }; 310 };
366 opp-1555200000 { 311 opp-1555200000 {
367 opp-hz = /bits/ 64 <15 312 opp-hz = /bits/ 64 <1555200000>;
368 opp-supported-hw = <0x !! 313 opp-supported-hw = <0x77>;
369 clock-latency-ns = <20 314 clock-latency-ns = <200000>;
370 opp-peak-kBps = <10560 <<
371 }; 315 };
372 opp-1632000000 { 316 opp-1632000000 {
373 opp-hz = /bits/ 64 <16 317 opp-hz = /bits/ 64 <1632000000>;
374 opp-supported-hw = <0x !! 318 opp-supported-hw = <0x77>;
375 clock-latency-ns = <20 319 clock-latency-ns = <200000>;
376 opp-peak-kBps = <11904 <<
377 }; 320 };
378 opp-1708800000 { 321 opp-1708800000 {
379 opp-hz = /bits/ 64 <17 322 opp-hz = /bits/ 64 <1708800000>;
380 opp-supported-hw = <0x !! 323 opp-supported-hw = <0x77>;
381 clock-latency-ns = <20 324 clock-latency-ns = <200000>;
382 opp-peak-kBps = <12288 <<
383 }; 325 };
384 opp-1785600000 { 326 opp-1785600000 {
385 opp-hz = /bits/ 64 <17 327 opp-hz = /bits/ 64 <1785600000>;
386 opp-supported-hw = <0x !! 328 opp-supported-hw = <0x77>;
387 clock-latency-ns = <20 <<
388 opp-peak-kBps = <13056 <<
389 }; <<
390 opp-1804800000 { <<
391 opp-hz = /bits/ 64 <18 <<
392 opp-supported-hw = <0x <<
393 clock-latency-ns = <20 329 clock-latency-ns = <200000>;
394 opp-peak-kBps = <13056 <<
395 }; 330 };
396 opp-1824000000 { 331 opp-1824000000 {
397 opp-hz = /bits/ 64 <18 332 opp-hz = /bits/ 64 <1824000000>;
398 opp-supported-hw = <0x !! 333 opp-supported-hw = <0x77>;
399 clock-latency-ns = <20 334 clock-latency-ns = <200000>;
400 opp-peak-kBps = <13824 <<
401 }; <<
402 opp-1900800000 { <<
403 opp-hz = /bits/ 64 <19 <<
404 opp-supported-hw = <0x <<
405 clock-latency-ns = <20 <<
406 opp-peak-kBps = <13056 <<
407 }; 335 };
408 opp-1920000000 { 336 opp-1920000000 {
409 opp-hz = /bits/ 64 <19 337 opp-hz = /bits/ 64 <1920000000>;
410 opp-supported-hw = <0x !! 338 opp-supported-hw = <0x77>;
411 clock-latency-ns = <20 339 clock-latency-ns = <200000>;
412 opp-peak-kBps = <14592 <<
413 }; 340 };
414 opp-1996800000 { 341 opp-1996800000 {
415 opp-hz = /bits/ 64 <19 342 opp-hz = /bits/ 64 <1996800000>;
416 opp-supported-hw = <0x !! 343 opp-supported-hw = <0x77>;
417 clock-latency-ns = <20 344 clock-latency-ns = <200000>;
418 opp-peak-kBps = <15936 <<
419 }; 345 };
420 opp-2073600000 { 346 opp-2073600000 {
421 opp-hz = /bits/ 64 <20 347 opp-hz = /bits/ 64 <2073600000>;
422 opp-supported-hw = <0x !! 348 opp-supported-hw = <0x77>;
423 clock-latency-ns = <20 349 clock-latency-ns = <200000>;
424 opp-peak-kBps = <15936 <<
425 }; 350 };
426 opp-2150400000 { 351 opp-2150400000 {
427 opp-hz = /bits/ 64 <21 352 opp-hz = /bits/ 64 <2150400000>;
428 opp-supported-hw = <0x !! 353 opp-supported-hw = <0x77>;
429 clock-latency-ns = <20 354 clock-latency-ns = <200000>;
430 opp-peak-kBps = <15936 <<
431 }; 355 };
432 }; 356 };
433 357
434 firmware { 358 firmware {
435 scm { 359 scm {
436 compatible = "qcom,scm !! 360 compatible = "qcom,scm-msm8996";
437 qcom,dload-mode = <&tc !! 361 qcom,dload-mode = <&tcsr 0x13000>;
438 }; 362 };
439 }; 363 };
440 364
>> 365 tcsr_mutex: hwlock {
>> 366 compatible = "qcom,tcsr-mutex";
>> 367 syscon = <&tcsr_mutex_regs 0 0x1000>;
>> 368 #hwlock-cells = <1>;
>> 369 };
>> 370
441 memory@80000000 { 371 memory@80000000 {
442 device_type = "memory"; 372 device_type = "memory";
443 /* We expect the bootloader to 373 /* We expect the bootloader to fill in the reg */
444 reg = <0x0 0x80000000 0x0 0x0> 374 reg = <0x0 0x80000000 0x0 0x0>;
445 }; 375 };
446 376
447 etm { <<
448 compatible = "qcom,coresight-r <<
449 <<
450 out-ports { <<
451 port { <<
452 modem_etm_out_ <<
453 remote <<
454 <&fu <<
455 }; <<
456 }; <<
457 }; <<
458 }; <<
459 <<
460 psci { 377 psci {
461 compatible = "arm,psci-1.0"; 378 compatible = "arm,psci-1.0";
462 method = "smc"; 379 method = "smc";
463 }; 380 };
464 381
465 rpm: remoteproc { <<
466 compatible = "qcom,msm8996-rpm <<
467 <<
468 glink-edge { <<
469 compatible = "qcom,gli <<
470 interrupts = <GIC_SPI <<
471 qcom,rpm-msg-ram = <&r <<
472 mboxes = <&apcs_glb 0> <<
473 <<
474 rpm_requests: rpm-requ <<
475 compatible = " <<
476 qcom,glink-cha <<
477 <<
478 rpmcc: clock-c <<
479 compat <<
480 #clock <<
481 clocks <<
482 clock- <<
483 }; <<
484 <<
485 rpmpd: power-c <<
486 compat <<
487 #power <<
488 operat <<
489 <<
490 rpmpd_ <<
491 <<
492 <<
493 <<
494 <<
495 <<
496 <<
497 <<
498 <<
499 <<
500 <<
501 <<
502 <<
503 <<
504 <<
505 <<
506 <<
507 <<
508 <<
509 <<
510 <<
511 <<
512 <<
513 <<
514 <<
515 <<
516 }; <<
517 }; <<
518 }; <<
519 }; <<
520 }; <<
521 <<
522 reserved-memory { 382 reserved-memory {
523 #address-cells = <2>; 383 #address-cells = <2>;
524 #size-cells = <2>; 384 #size-cells = <2>;
525 ranges; 385 ranges;
526 386
527 hyp_mem: memory@85800000 { !! 387 mba_region: mba@91500000 {
528 reg = <0x0 0x85800000 !! 388 reg = <0x0 0x91500000 0x0 0x200000>;
>> 389 no-map;
>> 390 };
>> 391
>> 392 slpi_region: slpi@90b00000 {
>> 393 reg = <0x0 0x90b00000 0x0 0xa00000>;
>> 394 no-map;
>> 395 };
>> 396
>> 397 venus_region: venus@90400000 {
>> 398 reg = <0x0 0x90400000 0x0 0x700000>;
>> 399 no-map;
>> 400 };
>> 401
>> 402 adsp_region: adsp@8ea00000 {
>> 403 reg = <0x0 0x8ea00000 0x0 0x1a00000>;
529 no-map; 404 no-map;
530 }; 405 };
531 406
532 xbl_mem: memory@85e00000 { !! 407 mpss_region: mpss@88800000 {
533 reg = <0x0 0x85e00000 !! 408 reg = <0x0 0x88800000 0x0 0x6200000>;
534 no-map; 409 no-map;
535 }; 410 };
536 411
537 smem_mem: smem-mem@86000000 { 412 smem_mem: smem-mem@86000000 {
538 reg = <0x0 0x86000000 413 reg = <0x0 0x86000000 0x0 0x200000>;
539 no-map; 414 no-map;
540 }; 415 };
541 416
542 tz_mem: memory@86200000 { !! 417 memory@85800000 {
>> 418 reg = <0x0 0x85800000 0x0 0x800000>;
>> 419 no-map;
>> 420 };
>> 421
>> 422 memory@86200000 {
543 reg = <0x0 0x86200000 423 reg = <0x0 0x86200000 0x0 0x2600000>;
544 no-map; 424 no-map;
545 }; 425 };
546 426
547 rmtfs_mem: rmtfs { !! 427 rmtfs@86700000 {
548 compatible = "qcom,rmt 428 compatible = "qcom,rmtfs-mem";
549 429
550 size = <0x0 0x200000>; 430 size = <0x0 0x200000>;
551 alloc-ranges = <0x0 0x 431 alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>;
552 no-map; 432 no-map;
553 433
554 qcom,client-id = <1>; 434 qcom,client-id = <1>;
555 qcom,vmid = <QCOM_SCM_ !! 435 qcom,vmid = <15>;
556 }; 436 };
557 437
558 mpss_mem: mpss@88800000 { !! 438 zap_shader_region: gpu@8f200000 {
559 reg = <0x0 0x88800000 !! 439 compatible = "shared-dma-pool";
>> 440 reg = <0x0 0x90b00000 0x0 0xa00000>;
560 no-map; 441 no-map;
561 }; 442 };
>> 443 };
562 444
563 adsp_mem: adsp@8ea00000 { !! 445 rpm-glink {
564 reg = <0x0 0x8ea00000 !! 446 compatible = "qcom,glink-rpm";
565 no-map; <<
566 }; <<
567 447
568 slpi_mem: slpi@90500000 { !! 448 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
569 reg = <0x0 0x90500000 <<
570 no-map; <<
571 }; <<
572 449
573 gpu_mem: gpu@90f00000 { !! 450 qcom,rpm-msg-ram = <&rpm_msg_ram>;
574 compatible = "shared-d <<
575 reg = <0x0 0x90f00000 <<
576 no-map; <<
577 }; <<
578 451
579 venus_mem: venus@91000000 { !! 452 mboxes = <&apcs_glb 0>;
580 reg = <0x0 0x91000000 <<
581 no-map; <<
582 }; <<
583 453
584 mba_mem: mba@91500000 { !! 454 rpm_requests: rpm-requests {
585 reg = <0x0 0x91500000 !! 455 compatible = "qcom,rpm-msm8996";
586 no-map; !! 456 qcom,glink-channels = "rpm_requests";
587 }; <<
588 457
589 mdata_mem: mpss-metadata { !! 458 rpmcc: qcom,rpmcc {
590 alloc-ranges = <0x0 0x !! 459 compatible = "qcom,rpmcc-msm8996";
591 size = <0x0 0x4000>; !! 460 #clock-cells = <1>;
592 no-map; !! 461 };
>> 462
>> 463 rpmpd: power-controller {
>> 464 compatible = "qcom,msm8996-rpmpd";
>> 465 #power-domain-cells = <1>;
>> 466 operating-points-v2 = <&rpmpd_opp_table>;
>> 467
>> 468 rpmpd_opp_table: opp-table {
>> 469 compatible = "operating-points-v2";
>> 470
>> 471 rpmpd_opp1: opp1 {
>> 472 opp-level = <1>;
>> 473 };
>> 474
>> 475 rpmpd_opp2: opp2 {
>> 476 opp-level = <2>;
>> 477 };
>> 478
>> 479 rpmpd_opp3: opp3 {
>> 480 opp-level = <3>;
>> 481 };
>> 482
>> 483 rpmpd_opp4: opp4 {
>> 484 opp-level = <4>;
>> 485 };
>> 486
>> 487 rpmpd_opp5: opp5 {
>> 488 opp-level = <5>;
>> 489 };
>> 490
>> 491 rpmpd_opp6: opp6 {
>> 492 opp-level = <6>;
>> 493 };
>> 494 };
>> 495 };
593 }; 496 };
594 }; 497 };
595 498
596 smem { 499 smem {
597 compatible = "qcom,smem"; 500 compatible = "qcom,smem";
598 memory-region = <&smem_mem>; 501 memory-region = <&smem_mem>;
599 hwlocks = <&tcsr_mutex 3>; 502 hwlocks = <&tcsr_mutex 3>;
600 }; 503 };
601 504
602 smp2p-adsp { 505 smp2p-adsp {
603 compatible = "qcom,smp2p"; 506 compatible = "qcom,smp2p";
604 qcom,smem = <443>, <429>; 507 qcom,smem = <443>, <429>;
605 508
606 interrupts = <GIC_SPI 158 IRQ_ !! 509 interrupts = <0 158 IRQ_TYPE_EDGE_RISING>;
607 510
608 mboxes = <&apcs_glb 10>; 511 mboxes = <&apcs_glb 10>;
609 512
610 qcom,local-pid = <0>; 513 qcom,local-pid = <0>;
611 qcom,remote-pid = <2>; 514 qcom,remote-pid = <2>;
612 515
613 adsp_smp2p_out: master-kernel !! 516 smp2p_adsp_out: master-kernel {
614 qcom,entry-name = "mas 517 qcom,entry-name = "master-kernel";
615 #qcom,smem-state-cells 518 #qcom,smem-state-cells = <1>;
616 }; 519 };
617 520
618 adsp_smp2p_in: slave-kernel { !! 521 smp2p_adsp_in: slave-kernel {
619 qcom,entry-name = "sla 522 qcom,entry-name = "slave-kernel";
620 523
621 interrupt-controller; 524 interrupt-controller;
622 #interrupt-cells = <2> 525 #interrupt-cells = <2>;
623 }; 526 };
624 }; 527 };
625 528
626 smp2p-mpss { !! 529 smp2p-modem {
627 compatible = "qcom,smp2p"; 530 compatible = "qcom,smp2p";
628 qcom,smem = <435>, <428>; 531 qcom,smem = <435>, <428>;
629 532
630 interrupts = <GIC_SPI 451 IRQ_ 533 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
631 534
632 mboxes = <&apcs_glb 14>; 535 mboxes = <&apcs_glb 14>;
633 536
634 qcom,local-pid = <0>; 537 qcom,local-pid = <0>;
635 qcom,remote-pid = <1>; 538 qcom,remote-pid = <1>;
636 539
637 mpss_smp2p_out: master-kernel !! 540 modem_smp2p_out: master-kernel {
638 qcom,entry-name = "mas 541 qcom,entry-name = "master-kernel";
639 #qcom,smem-state-cells 542 #qcom,smem-state-cells = <1>;
640 }; 543 };
641 544
642 mpss_smp2p_in: slave-kernel { !! 545 modem_smp2p_in: slave-kernel {
643 qcom,entry-name = "sla 546 qcom,entry-name = "slave-kernel";
644 547
645 interrupt-controller; 548 interrupt-controller;
646 #interrupt-cells = <2> 549 #interrupt-cells = <2>;
647 }; 550 };
648 }; 551 };
649 552
650 smp2p-slpi { 553 smp2p-slpi {
651 compatible = "qcom,smp2p"; 554 compatible = "qcom,smp2p";
652 qcom,smem = <481>, <430>; 555 qcom,smem = <481>, <430>;
653 556
654 interrupts = <GIC_SPI 178 IRQ_ 557 interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>;
655 558
656 mboxes = <&apcs_glb 26>; 559 mboxes = <&apcs_glb 26>;
657 560
658 qcom,local-pid = <0>; 561 qcom,local-pid = <0>;
659 qcom,remote-pid = <3>; 562 qcom,remote-pid = <3>;
660 563
661 slpi_smp2p_out: master-kernel !! 564 smp2p_slpi_in: slave-kernel {
662 qcom,entry-name = "mas <<
663 #qcom,smem-state-cells <<
664 }; <<
665 <<
666 slpi_smp2p_in: slave-kernel { <<
667 qcom,entry-name = "sla 565 qcom,entry-name = "slave-kernel";
668 <<
669 interrupt-controller; 566 interrupt-controller;
670 #interrupt-cells = <2> 567 #interrupt-cells = <2>;
671 }; 568 };
>> 569
>> 570 smp2p_slpi_out: master-kernel {
>> 571 qcom,entry-name = "master-kernel";
>> 572 #qcom,smem-state-cells = <1>;
>> 573 };
672 }; 574 };
673 575
674 soc: soc@0 { !! 576 soc: soc {
675 #address-cells = <1>; 577 #address-cells = <1>;
676 #size-cells = <1>; 578 #size-cells = <1>;
677 ranges = <0 0 0 0xffffffff>; 579 ranges = <0 0 0 0xffffffff>;
678 compatible = "simple-bus"; 580 compatible = "simple-bus";
679 581
680 pcie_phy: phy-wrapper@34000 { !! 582 pcie_phy: phy@34000 {
681 compatible = "qcom,msm 583 compatible = "qcom,msm8996-qmp-pcie-phy";
682 reg = <0x00034000 0x48 584 reg = <0x00034000 0x488>;
683 #address-cells = <1>; 585 #address-cells = <1>;
684 #size-cells = <1>; 586 #size-cells = <1>;
685 ranges = <0x0 0x000340 !! 587 ranges;
686 588
687 clocks = <&gcc GCC_PCI 589 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
688 <&gcc GCC_PCIE 590 <&gcc GCC_PCIE_PHY_CFG_AHB_CLK>,
689 <&gcc GCC_PCIE 591 <&gcc GCC_PCIE_CLKREF_CLK>;
690 clock-names = "aux", " 592 clock-names = "aux", "cfg_ahb", "ref";
691 593
692 resets = <&gcc GCC_PCI 594 resets = <&gcc GCC_PCIE_PHY_BCR>,
693 <&gcc GCC_PCIE 595 <&gcc GCC_PCIE_PHY_COM_BCR>,
694 <&gcc GCC_PCIE 596 <&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>;
695 reset-names = "phy", " 597 reset-names = "phy", "common", "cfg";
696 <<
697 status = "disabled"; 598 status = "disabled";
698 599
699 pciephy_0: phy@1000 { !! 600 pciephy_0: phy@35000 {
700 reg = <0x1000 !! 601 reg = <0x00035000 0x130>,
701 <0x1200 !! 602 <0x00035200 0x200>,
702 <0x1400 !! 603 <0x00035400 0x1dc>;
>> 604 #phy-cells = <0>;
703 605
>> 606 #clock-cells = <1>;
>> 607 clock-output-names = "pcie_0_pipe_clk_src";
704 clocks = <&gcc 608 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
705 clock-names = 609 clock-names = "pipe0";
706 resets = <&gcc 610 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
707 reset-names = 611 reset-names = "lane0";
708 <<
709 #clock-cells = <<
710 clock-output-n <<
711 <<
712 #phy-cells = < <<
713 }; 612 };
714 613
715 pciephy_1: phy@2000 { !! 614 pciephy_1: phy@36000 {
716 reg = <0x2000 !! 615 reg = <0x00036000 0x130>,
717 <0x2200 !! 616 <0x00036200 0x200>,
718 <0x2400 !! 617 <0x00036400 0x1dc>;
>> 618 #phy-cells = <0>;
719 619
>> 620 clock-output-names = "pcie_1_pipe_clk_src";
720 clocks = <&gcc 621 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
721 clock-names = 622 clock-names = "pipe1";
722 resets = <&gcc 623 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
723 reset-names = 624 reset-names = "lane1";
724 <<
725 #clock-cells = <<
726 clock-output-n <<
727 <<
728 #phy-cells = < <<
729 }; 625 };
730 626
731 pciephy_2: phy@3000 { !! 627 pciephy_2: phy@37000 {
732 reg = <0x3000 !! 628 reg = <0x00037000 0x130>,
733 <0x3200 !! 629 <0x00037200 0x200>,
734 <0x3400 !! 630 <0x00037400 0x1dc>;
>> 631 #phy-cells = <0>;
735 632
>> 633 clock-output-names = "pcie_2_pipe_clk_src";
736 clocks = <&gcc 634 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>;
737 clock-names = 635 clock-names = "pipe2";
738 resets = <&gcc 636 resets = <&gcc GCC_PCIE_2_PHY_BCR>;
739 reset-names = 637 reset-names = "lane2";
740 <<
741 #clock-cells = <<
742 clock-output-n <<
743 <<
744 #phy-cells = < <<
745 }; 638 };
746 }; 639 };
747 640
748 rpm_msg_ram: sram@68000 { 641 rpm_msg_ram: sram@68000 {
749 compatible = "qcom,rpm 642 compatible = "qcom,rpm-msg-ram";
750 reg = <0x00068000 0x60 643 reg = <0x00068000 0x6000>;
751 }; 644 };
752 645
753 qfprom@74000 { 646 qfprom@74000 {
754 compatible = "qcom,msm !! 647 compatible = "qcom,qfprom";
755 reg = <0x00074000 0x8f 648 reg = <0x00074000 0x8ff>;
756 #address-cells = <1>; 649 #address-cells = <1>;
757 #size-cells = <1>; 650 #size-cells = <1>;
758 651
759 qusb2p_hstx_trim: hstx !! 652 qusb2p_hstx_trim: hstx_trim@24e {
760 reg = <0x24e 0 653 reg = <0x24e 0x2>;
761 bits = <5 4>; 654 bits = <5 4>;
762 }; 655 };
763 656
764 qusb2s_hstx_trim: hstx !! 657 qusb2s_hstx_trim: hstx_trim@24f {
765 reg = <0x24f 0 658 reg = <0x24f 0x1>;
766 bits = <1 4>; 659 bits = <1 4>;
767 }; 660 };
768 661
769 speedbin_efuse: speedb 662 speedbin_efuse: speedbin@133 {
770 reg = <0x133 0 663 reg = <0x133 0x1>;
771 bits = <5 3>; 664 bits = <5 3>;
772 }; 665 };
773 }; 666 };
774 667
775 rng: rng@83000 { 668 rng: rng@83000 {
776 compatible = "qcom,prn 669 compatible = "qcom,prng-ee";
777 reg = <0x00083000 0x10 670 reg = <0x00083000 0x1000>;
778 clocks = <&gcc GCC_PRN 671 clocks = <&gcc GCC_PRNG_AHB_CLK>;
779 clock-names = "core"; 672 clock-names = "core";
780 }; 673 };
781 674
782 gcc: clock-controller@300000 { 675 gcc: clock-controller@300000 {
783 compatible = "qcom,gcc 676 compatible = "qcom,gcc-msm8996";
784 #clock-cells = <1>; 677 #clock-cells = <1>;
785 #reset-cells = <1>; 678 #reset-cells = <1>;
786 #power-domain-cells = 679 #power-domain-cells = <1>;
787 reg = <0x00300000 0x90 680 reg = <0x00300000 0x90000>;
788 681
789 clocks = <&rpmcc RPM_S !! 682 clocks = <&rpmcc RPM_SMD_LN_BB_CLK>;
790 <&rpmcc RPM_S !! 683 clock-names = "cxo2";
791 <&sleep_clk>, <<
792 <&pciephy_0>, <<
793 <&pciephy_1>, <<
794 <&pciephy_2>, <<
795 <&usb3phy>, <<
796 <&ufsphy 0>, <<
797 <&ufsphy 1>, <<
798 <&ufsphy 2>; <<
799 clock-names = "cxo", <<
800 "cxo2", <<
801 "sleep_c <<
802 "pcie_0_ <<
803 "pcie_1_ <<
804 "pcie_2_ <<
805 "usb3_ph <<
806 "ufs_rx_ <<
807 "ufs_rx_ <<
808 "ufs_tx_ <<
809 }; <<
810 <<
811 bimc: interconnect@408000 { <<
812 compatible = "qcom,msm <<
813 reg = <0x00408000 0x5a <<
814 #interconnect-cells = <<
815 }; 684 };
816 685
817 tsens0: thermal-sensor@4a9000 686 tsens0: thermal-sensor@4a9000 {
818 compatible = "qcom,msm 687 compatible = "qcom,msm8996-tsens", "qcom,tsens-v2";
819 reg = <0x004a9000 0x10 688 reg = <0x004a9000 0x1000>, /* TM */
820 <0x004a8000 0x10 689 <0x004a8000 0x1000>; /* SROT */
821 #qcom,sensors = <13>; 690 #qcom,sensors = <13>;
822 interrupts = <GIC_SPI 691 interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
823 <GIC_SPI 692 <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
824 interrupt-names = "upl 693 interrupt-names = "uplow", "critical";
825 #thermal-sensor-cells 694 #thermal-sensor-cells = <1>;
826 }; 695 };
827 696
828 tsens1: thermal-sensor@4ad000 697 tsens1: thermal-sensor@4ad000 {
829 compatible = "qcom,msm 698 compatible = "qcom,msm8996-tsens", "qcom,tsens-v2";
830 reg = <0x004ad000 0x10 699 reg = <0x004ad000 0x1000>, /* TM */
831 <0x004ac000 0x10 700 <0x004ac000 0x1000>; /* SROT */
832 #qcom,sensors = <8>; 701 #qcom,sensors = <8>;
833 interrupts = <GIC_SPI 702 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
834 <GIC_SPI 703 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>;
835 interrupt-names = "upl 704 interrupt-names = "uplow", "critical";
836 #thermal-sensor-cells 705 #thermal-sensor-cells = <1>;
837 }; 706 };
838 707
839 cryptobam: dma-controller@6440 !! 708 cryptobam: dma@644000 {
840 compatible = "qcom,bam 709 compatible = "qcom,bam-v1.7.0";
841 reg = <0x00644000 0x24 710 reg = <0x00644000 0x24000>;
842 interrupts = <GIC_SPI 711 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
843 clocks = <&gcc GCC_CE1 712 clocks = <&gcc GCC_CE1_CLK>;
844 clock-names = "bam_clk 713 clock-names = "bam_clk";
845 #dma-cells = <1>; 714 #dma-cells = <1>;
846 qcom,ee = <0>; 715 qcom,ee = <0>;
847 qcom,controlled-remote !! 716 qcom,controlled-remotely = <1>;
848 }; 717 };
849 718
850 crypto: crypto@67a000 { 719 crypto: crypto@67a000 {
851 compatible = "qcom,cry 720 compatible = "qcom,crypto-v5.4";
852 reg = <0x0067a000 0x60 721 reg = <0x0067a000 0x6000>;
853 clocks = <&gcc GCC_CE1 722 clocks = <&gcc GCC_CE1_AHB_CLK>,
854 <&gcc GCC_CE1 723 <&gcc GCC_CE1_AXI_CLK>,
855 <&gcc GCC_CE1 724 <&gcc GCC_CE1_CLK>;
856 clock-names = "iface", 725 clock-names = "iface", "bus", "core";
857 dmas = <&cryptobam 6>, 726 dmas = <&cryptobam 6>, <&cryptobam 7>;
858 dma-names = "rx", "tx" 727 dma-names = "rx", "tx";
859 }; 728 };
860 729
861 cnoc: interconnect@500000 { !! 730 tcsr_mutex_regs: syscon@740000 {
862 compatible = "qcom,msm !! 731 compatible = "syscon";
863 reg = <0x00500000 0x10 !! 732 reg = <0x00740000 0x40000>;
864 #interconnect-cells = <<
865 }; <<
866 <<
867 snoc: interconnect@524000 { <<
868 compatible = "qcom,msm <<
869 reg = <0x00524000 0x1c <<
870 #interconnect-cells = <<
871 }; <<
872 <<
873 a0noc: interconnect@543000 { <<
874 compatible = "qcom,msm <<
875 reg = <0x00543000 0x60 <<
876 #interconnect-cells = <<
877 clock-names = "aggre0_ <<
878 "aggre0_ <<
879 "aggre0_ <<
880 clocks = <&gcc GCC_AGG <<
881 <&gcc GCC_AGG <<
882 <&gcc GCC_AGG <<
883 power-domains = <&gcc <<
884 }; <<
885 <<
886 a1noc: interconnect@562000 { <<
887 compatible = "qcom,msm <<
888 reg = <0x00562000 0x50 <<
889 #interconnect-cells = <<
890 }; <<
891 <<
892 a2noc: interconnect@583000 { <<
893 compatible = "qcom,msm <<
894 reg = <0x00583000 0x70 <<
895 #interconnect-cells = <<
896 clock-names = "aggre2_ <<
897 clocks = <&gcc GCC_AGG <<
898 <&gcc GCC_UFS <<
899 }; <<
900 <<
901 mnoc: interconnect@5a4000 { <<
902 compatible = "qcom,msm <<
903 reg = <0x005a4000 0x1c <<
904 #interconnect-cells = <<
905 clock-names = "iface"; <<
906 clocks = <&mmcc AHB_CL <<
907 }; <<
908 <<
909 pnoc: interconnect@5c0000 { <<
910 compatible = "qcom,msm <<
911 reg = <0x005c0000 0x30 <<
912 #interconnect-cells = <<
913 }; <<
914 <<
915 tcsr_mutex: hwlock@740000 { <<
916 compatible = "qcom,tcs <<
917 reg = <0x00740000 0x20 <<
918 #hwlock-cells = <1>; <<
919 }; <<
920 <<
921 tcsr_1: syscon@760000 { <<
922 compatible = "qcom,tcs <<
923 reg = <0x00760000 0x20 <<
924 }; 733 };
925 734
926 tcsr_2: syscon@7a0000 { !! 735 tcsr: syscon@7a0000 {
927 compatible = "qcom,tcs 736 compatible = "qcom,tcsr-msm8996", "syscon";
928 reg = <0x007a0000 0x18 737 reg = <0x007a0000 0x18000>;
929 }; 738 };
930 739
931 mmcc: clock-controller@8c0000 740 mmcc: clock-controller@8c0000 {
932 compatible = "qcom,mmc 741 compatible = "qcom,mmcc-msm8996";
933 #clock-cells = <1>; 742 #clock-cells = <1>;
934 #reset-cells = <1>; 743 #reset-cells = <1>;
935 #power-domain-cells = 744 #power-domain-cells = <1>;
936 reg = <0x008c0000 0x40 745 reg = <0x008c0000 0x40000>;
937 clocks = <&xo_board>, <<
938 <&gcc GPLL0>, <<
939 <&gcc GCC_MMS <<
940 <&mdss_dsi0_p <<
941 <&mdss_dsi0_p <<
942 <&mdss_dsi1_p <<
943 <&mdss_dsi1_p <<
944 <&mdss_hdmi_p <<
945 clock-names = "xo", <<
946 "gpll0", <<
947 "gcc_mms <<
948 "dsi0pll <<
949 "dsi0pll <<
950 "dsi1pll <<
951 "dsi1pll <<
952 "hdmipll <<
953 assigned-clocks = <&mm 746 assigned-clocks = <&mmcc MMPLL9_PLL>,
954 <&mm 747 <&mmcc MMPLL1_PLL>,
955 <&mm 748 <&mmcc MMPLL3_PLL>,
956 <&mm 749 <&mmcc MMPLL4_PLL>,
957 <&mm 750 <&mmcc MMPLL5_PLL>;
958 assigned-clock-rates = 751 assigned-clock-rates = <624000000>,
959 752 <810000000>,
960 753 <980000000>,
961 754 <960000000>,
962 755 <825000000>;
963 }; 756 };
964 757
965 mdss: display-subsystem@900000 !! 758 mdss: mdss@900000 {
966 compatible = "qcom,mds 759 compatible = "qcom,mdss";
967 760
968 reg = <0x00900000 0x10 761 reg = <0x00900000 0x1000>,
969 <0x009b0000 0x10 762 <0x009b0000 0x1040>,
970 <0x009b8000 0x10 763 <0x009b8000 0x1040>;
971 reg-names = "mdss_phys 764 reg-names = "mdss_phys",
972 "vbif_phys 765 "vbif_phys",
973 "vbif_nrt_ 766 "vbif_nrt_phys";
974 767
975 power-domains = <&mmcc 768 power-domains = <&mmcc MDSS_GDSC>;
976 interrupts = <GIC_SPI 769 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
977 770
978 interrupt-controller; 771 interrupt-controller;
979 #interrupt-cells = <1> 772 #interrupt-cells = <1>;
980 773
981 clocks = <&mmcc MDSS_A !! 774 clocks = <&mmcc MDSS_AHB_CLK>;
982 <&mmcc MDSS_M !! 775 clock-names = "iface";
983 clock-names = "iface", <<
984 <<
985 resets = <&mmcc MDSS_B <<
986 776
987 #address-cells = <1>; 777 #address-cells = <1>;
988 #size-cells = <1>; 778 #size-cells = <1>;
989 ranges; 779 ranges;
990 780
991 status = "disabled"; 781 status = "disabled";
992 782
993 mdp: display-controlle !! 783 mdp: mdp@901000 {
994 compatible = " !! 784 compatible = "qcom,mdp5";
995 reg = <0x00901 785 reg = <0x00901000 0x90000>;
996 reg-names = "m 786 reg-names = "mdp_phys";
997 787
998 interrupt-pare 788 interrupt-parent = <&mdss>;
999 interrupts = < !! 789 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
1000 790
1001 clocks = <&mm 791 clocks = <&mmcc MDSS_AHB_CLK>,
1002 <&mm 792 <&mmcc MDSS_AXI_CLK>,
1003 <&mm 793 <&mmcc MDSS_MDP_CLK>,
1004 <&mm 794 <&mmcc SMMU_MDP_AXI_CLK>,
1005 <&mm 795 <&mmcc MDSS_VSYNC_CLK>;
1006 clock-names = 796 clock-names = "iface",
1007 797 "bus",
1008 798 "core",
1009 799 "iommu",
1010 800 "vsync";
1011 801
1012 iommus = <&md 802 iommus = <&mdp_smmu 0>;
1013 803
1014 assigned-cloc 804 assigned-clocks = <&mmcc MDSS_MDP_CLK>,
1015 <&mm 805 <&mmcc MDSS_VSYNC_CLK>;
1016 assigned-cloc 806 assigned-clock-rates = <300000000>,
1017 <192 807 <19200000>;
1018 808
1019 interconnects <<
1020 <<
1021 <<
1022 interconnect- <<
1023 <<
1024 ports { 809 ports {
1025 #addr 810 #address-cells = <1>;
1026 #size 811 #size-cells = <0>;
1027 812
1028 port@ 813 port@0 {
1029 814 reg = <0>;
1030 815 mdp5_intf3_out: endpoint {
1031 !! 816 remote-endpoint = <&hdmi_in>;
1032 817 };
1033 }; 818 };
1034 819
1035 port@ 820 port@1 {
1036 821 reg = <1>;
1037 822 mdp5_intf1_out: endpoint {
1038 !! 823 remote-endpoint = <&dsi0_in>;
1039 <<
1040 }; <<
1041 <<
1042 port@ <<
1043 <<
1044 <<
1045 <<
1046 824 };
1047 }; 825 };
1048 }; 826 };
1049 }; 827 };
1050 828
1051 mdss_dsi0: dsi@994000 !! 829 dsi0: dsi@994000 {
1052 compatible = !! 830 compatible = "qcom,mdss-dsi-ctrl";
1053 <<
1054 reg = <0x0099 831 reg = <0x00994000 0x400>;
1055 reg-names = " 832 reg-names = "dsi_ctrl";
1056 833
1057 interrupt-par 834 interrupt-parent = <&mdss>;
1058 interrupts = !! 835 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
1059 836
1060 clocks = <&mm 837 clocks = <&mmcc MDSS_MDP_CLK>,
1061 <&mm 838 <&mmcc MDSS_BYTE0_CLK>,
1062 <&mm 839 <&mmcc MDSS_AHB_CLK>,
1063 <&mm 840 <&mmcc MDSS_AXI_CLK>,
1064 <&mm 841 <&mmcc MMSS_MISC_AHB_CLK>,
1065 <&mm 842 <&mmcc MDSS_PCLK0_CLK>,
1066 <&mm 843 <&mmcc MDSS_ESC0_CLK>;
1067 clock-names = 844 clock-names = "mdp_core",
1068 845 "byte",
1069 846 "iface",
1070 847 "bus",
1071 848 "core_mmss",
1072 849 "pixel",
1073 850 "core";
1074 assigned-cloc <<
1075 assigned-cloc <<
1076 851
1077 phys = <&mdss !! 852 phys = <&dsi0_phy>;
>> 853 phy-names = "dsi";
1078 status = "dis 854 status = "disabled";
1079 855
1080 #address-cell 856 #address-cells = <1>;
1081 #size-cells = 857 #size-cells = <0>;
1082 858
1083 ports { 859 ports {
1084 #addr 860 #address-cells = <1>;
1085 #size 861 #size-cells = <0>;
1086 862
1087 port@ 863 port@0 {
1088 864 reg = <0>;
1089 !! 865 dsi0_in: endpoint {
1090 866 remote-endpoint = <&mdp5_intf1_out>;
1091 867 };
1092 }; 868 };
1093 869
1094 port@ 870 port@1 {
1095 871 reg = <1>;
1096 !! 872 dsi0_out: endpoint {
1097 873 };
1098 }; 874 };
1099 }; 875 };
1100 }; 876 };
1101 877
1102 mdss_dsi0_phy: phy@99 !! 878 dsi0_phy: dsi-phy@994400 {
1103 compatible = 879 compatible = "qcom,dsi-phy-14nm";
1104 reg = <0x0099 880 reg = <0x00994400 0x100>,
1105 <0x0099 881 <0x00994500 0x300>,
1106 <0x0099 882 <0x00994800 0x188>;
1107 reg-names = " 883 reg-names = "dsi_phy",
1108 " 884 "dsi_phy_lane",
1109 " 885 "dsi_pll";
1110 886
1111 #clock-cells 887 #clock-cells = <1>;
1112 #phy-cells = 888 #phy-cells = <0>;
1113 889
1114 clocks = <&mm !! 890 clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>;
1115 clock-names = <<
1116 status = "dis <<
1117 }; <<
1118 <<
1119 mdss_dsi1: dsi@996000 <<
1120 compatible = <<
1121 <<
1122 reg = <0x0099 <<
1123 reg-names = " <<
1124 <<
1125 interrupt-par <<
1126 interrupts = <<
1127 <<
1128 clocks = <&mm <<
1129 <&mm <<
1130 <&mm <<
1131 <&mm <<
1132 <&mm <<
1133 <&mm <<
1134 <&mm <<
1135 clock-names = <<
1136 <<
1137 <<
1138 <<
1139 <<
1140 <<
1141 <<
1142 assigned-cloc <<
1143 assigned-cloc <<
1144 <<
1145 phys = <&mdss <<
1146 status = "dis <<
1147 <<
1148 #address-cell <<
1149 #size-cells = <<
1150 <<
1151 ports { <<
1152 #addr <<
1153 #size <<
1154 <<
1155 port@ <<
1156 <<
1157 <<
1158 <<
1159 <<
1160 }; <<
1161 <<
1162 port@ <<
1163 <<
1164 <<
1165 <<
1166 }; <<
1167 }; <<
1168 }; <<
1169 <<
1170 mdss_dsi1_phy: phy@99 <<
1171 compatible = <<
1172 reg = <0x0099 <<
1173 <0x0099 <<
1174 <0x0099 <<
1175 reg-names = " <<
1176 " <<
1177 " <<
1178 <<
1179 #clock-cells <<
1180 #phy-cells = <<
1181 <<
1182 clocks = <&mm <<
1183 clock-names = 891 clock-names = "iface", "ref";
1184 status = "dis 892 status = "disabled";
1185 }; 893 };
1186 894
1187 mdss_hdmi: hdmi-tx@9a !! 895 hdmi: hdmi-tx@9a0000 {
1188 compatible = 896 compatible = "qcom,hdmi-tx-8996";
1189 reg = <0x009a !! 897 reg = <0x009a0000 0x50c>,
1190 <0x0007 !! 898 <0x00070000 0x6158>,
1191 <0x009e !! 899 <0x009e0000 0xfff>;
1192 reg-names = " 900 reg-names = "core_physical",
1193 " 901 "qfprom_physical",
1194 " 902 "hdcp_physical";
1195 903
1196 interrupt-par 904 interrupt-parent = <&mdss>;
1197 interrupts = !! 905 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
1198 906
1199 clocks = <&mm 907 clocks = <&mmcc MDSS_MDP_CLK>,
1200 <&mm 908 <&mmcc MDSS_AHB_CLK>,
1201 <&mm 909 <&mmcc MDSS_HDMI_CLK>,
1202 <&mm 910 <&mmcc MDSS_HDMI_AHB_CLK>,
1203 <&mm 911 <&mmcc MDSS_EXTPCLK_CLK>;
1204 clock-names = 912 clock-names =
1205 "mdp_ 913 "mdp_core",
1206 "ifac 914 "iface",
1207 "core 915 "core",
1208 "alt_ 916 "alt_iface",
1209 "extp 917 "extp";
1210 918
1211 phys = <&mdss !! 919 phys = <&hdmi_phy>;
>> 920 phy-names = "hdmi_phy";
1212 #sound-dai-ce 921 #sound-dai-cells = <1>;
1213 922
1214 status = "dis 923 status = "disabled";
1215 924
1216 ports { 925 ports {
1217 #addr 926 #address-cells = <1>;
1218 #size 927 #size-cells = <0>;
1219 928
1220 port@ 929 port@0 {
1221 930 reg = <0>;
1222 !! 931 hdmi_in: endpoint {
1223 932 remote-endpoint = <&mdp5_intf3_out>;
1224 933 };
1225 }; 934 };
1226 }; 935 };
1227 }; 936 };
1228 937
1229 mdss_hdmi_phy: phy@9a !! 938 hdmi_phy: hdmi-phy@9a0600 {
1230 #phy-cells = 939 #phy-cells = <0>;
1231 compatible = 940 compatible = "qcom,hdmi-phy-8996";
1232 reg = <0x009a 941 reg = <0x009a0600 0x1c4>,
1233 <0x009a 942 <0x009a0a00 0x124>,
1234 <0x009a 943 <0x009a0c00 0x124>,
1235 <0x009a 944 <0x009a0e00 0x124>,
1236 <0x009a 945 <0x009a1000 0x124>,
1237 <0x009a 946 <0x009a1200 0x0c8>;
1238 reg-names = " 947 reg-names = "hdmi_pll",
1239 " 948 "hdmi_tx_l0",
1240 " 949 "hdmi_tx_l1",
1241 " 950 "hdmi_tx_l2",
1242 " 951 "hdmi_tx_l3",
1243 " 952 "hdmi_phy";
1244 953
1245 clocks = <&mm 954 clocks = <&mmcc MDSS_AHB_CLK>,
1246 <&gc !! 955 <&gcc GCC_HDMI_CLKREF_CLK>;
1247 <&xo <<
1248 clock-names = 956 clock-names = "iface",
1249 !! 957 "ref";
1250 <<
1251 <<
1252 #clock-cells <<
1253 958
1254 status = "dis 959 status = "disabled";
1255 }; 960 };
1256 }; 961 };
1257 962
1258 gpu: gpu@b00000 { 963 gpu: gpu@b00000 {
1259 compatible = "qcom,ad 964 compatible = "qcom,adreno-530.2", "qcom,adreno";
>> 965 #stream-id-cells = <16>;
1260 966
1261 reg = <0x00b00000 0x3 967 reg = <0x00b00000 0x3f000>;
1262 reg-names = "kgsl_3d0 968 reg-names = "kgsl_3d0_reg_memory";
1263 969
1264 interrupts = <GIC_SPI !! 970 interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;
1265 971
1266 clocks = <&mmcc GPU_G 972 clocks = <&mmcc GPU_GX_GFX3D_CLK>,
1267 <&mmcc GPU_AH 973 <&mmcc GPU_AHB_CLK>,
1268 <&mmcc GPU_GX 974 <&mmcc GPU_GX_RBBMTIMER_CLK>,
1269 <&gcc GCC_BIM 975 <&gcc GCC_BIMC_GFX_CLK>,
1270 <&gcc GCC_MMS 976 <&gcc GCC_MMSS_BIMC_GFX_CLK>;
1271 977
1272 clock-names = "core", 978 clock-names = "core",
1273 "iface", 979 "iface",
1274 "rbbmtimer", 980 "rbbmtimer",
1275 "mem", 981 "mem",
1276 "mem_iface"; 982 "mem_iface";
1277 983
1278 interconnects = <&bim <<
1279 interconnect-names = <<
1280 <<
1281 power-domains = <&mmc 984 power-domains = <&mmcc GPU_GX_GDSC>;
1282 iommus = <&adreno_smm 985 iommus = <&adreno_smmu 0>;
1283 986
1284 nvmem-cells = <&speed 987 nvmem-cells = <&speedbin_efuse>;
1285 nvmem-cell-names = "s 988 nvmem-cell-names = "speed_bin";
1286 989
1287 operating-points-v2 = 990 operating-points-v2 = <&gpu_opp_table>;
1288 991
1289 status = "disabled"; 992 status = "disabled";
1290 993
1291 #cooling-cells = <2>; 994 #cooling-cells = <2>;
1292 995
1293 gpu_opp_table: opp-ta 996 gpu_opp_table: opp-table {
1294 compatible = !! 997 compatible ="operating-points-v2";
1295 998
1296 /* 999 /*
1297 * 624Mhz is !! 1000 * 624Mhz and 560Mhz are only available on speed
1298 * 560Mhz is !! 1001 * bin (1 << 0). All the rest are available on
1299 * All the re !! 1002 * all bins of the hardware
1300 */ 1003 */
1301 opp-624000000 1004 opp-624000000 {
1302 opp-h 1005 opp-hz = /bits/ 64 <624000000>;
1303 opp-s !! 1006 opp-supported-hw = <0x01>;
1304 }; 1007 };
1305 opp-560000000 1008 opp-560000000 {
1306 opp-h 1009 opp-hz = /bits/ 64 <560000000>;
1307 opp-s !! 1010 opp-supported-hw = <0x01>;
1308 }; 1011 };
1309 opp-510000000 1012 opp-510000000 {
1310 opp-h 1013 opp-hz = /bits/ 64 <510000000>;
1311 opp-s !! 1014 opp-supported-hw = <0xFF>;
1312 }; 1015 };
1313 opp-401800000 1016 opp-401800000 {
1314 opp-h 1017 opp-hz = /bits/ 64 <401800000>;
1315 opp-s !! 1018 opp-supported-hw = <0xFF>;
1316 }; 1019 };
1317 opp-315000000 1020 opp-315000000 {
1318 opp-h 1021 opp-hz = /bits/ 64 <315000000>;
1319 opp-s !! 1022 opp-supported-hw = <0xFF>;
1320 }; 1023 };
1321 opp-214000000 1024 opp-214000000 {
1322 opp-h 1025 opp-hz = /bits/ 64 <214000000>;
1323 opp-s !! 1026 opp-supported-hw = <0xFF>;
1324 }; 1027 };
1325 opp-133000000 1028 opp-133000000 {
1326 opp-h 1029 opp-hz = /bits/ 64 <133000000>;
1327 opp-s !! 1030 opp-supported-hw = <0xFF>;
1328 }; 1031 };
1329 }; 1032 };
1330 1033
1331 zap-shader { 1034 zap-shader {
1332 memory-region !! 1035 memory-region = <&zap_shader_region>;
1333 }; 1036 };
1334 }; 1037 };
1335 1038
1336 tlmm: pinctrl@1010000 { 1039 tlmm: pinctrl@1010000 {
1337 compatible = "qcom,ms 1040 compatible = "qcom,msm8996-pinctrl";
1338 reg = <0x01010000 0x3 1041 reg = <0x01010000 0x300000>;
1339 interrupts = <GIC_SPI 1042 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1340 gpio-controller; 1043 gpio-controller;
1341 gpio-ranges = <&tlmm 1044 gpio-ranges = <&tlmm 0 0 150>;
1342 #gpio-cells = <2>; 1045 #gpio-cells = <2>;
1343 interrupt-controller; 1046 interrupt-controller;
1344 #interrupt-cells = <2 1047 #interrupt-cells = <2>;
1345 1048
1346 blsp1_spi1_default: b !! 1049 blsp1_spi1_default: blsp1-spi1-default {
1347 spi-pins { !! 1050 spi {
1348 pins 1051 pins = "gpio0", "gpio1", "gpio3";
1349 funct 1052 function = "blsp_spi1";
1350 drive 1053 drive-strength = <12>;
1351 bias- 1054 bias-disable;
1352 }; 1055 };
1353 1056
1354 cs-pins { !! 1057 cs {
1355 pins 1058 pins = "gpio2";
1356 funct 1059 function = "gpio";
1357 drive 1060 drive-strength = <16>;
1358 bias- 1061 bias-disable;
1359 outpu 1062 output-high;
1360 }; 1063 };
1361 }; 1064 };
1362 1065
1363 blsp1_spi1_sleep: bls !! 1066 blsp1_spi1_sleep: blsp1-spi1-sleep {
1364 pins = "gpio0 1067 pins = "gpio0", "gpio1", "gpio2", "gpio3";
1365 function = "g 1068 function = "gpio";
1366 drive-strengt 1069 drive-strength = <2>;
1367 bias-pull-dow 1070 bias-pull-down;
1368 }; 1071 };
1369 1072
1370 blsp2_uart2_2pins_def !! 1073 blsp2_uart2_2pins_default: blsp2-uart1-2pins {
1371 pins = "gpio4 1074 pins = "gpio4", "gpio5";
1372 function = "b 1075 function = "blsp_uart8";
1373 drive-strengt 1076 drive-strength = <16>;
1374 bias-disable; 1077 bias-disable;
1375 }; 1078 };
1376 1079
1377 blsp2_uart2_2pins_sle !! 1080 blsp2_uart2_2pins_sleep: blsp2-uart1-2pins-sleep {
1378 pins = "gpio4 1081 pins = "gpio4", "gpio5";
1379 function = "g 1082 function = "gpio";
1380 drive-strengt 1083 drive-strength = <2>;
1381 bias-disable; 1084 bias-disable;
1382 }; 1085 };
1383 1086
1384 blsp2_i2c2_default: b !! 1087 blsp2_i2c2_default: blsp2-i2c2 {
1385 pins = "gpio6 1088 pins = "gpio6", "gpio7";
1386 function = "b 1089 function = "blsp_i2c8";
1387 drive-strengt 1090 drive-strength = <16>;
1388 bias-disable; 1091 bias-disable;
1389 }; 1092 };
1390 1093
1391 blsp2_i2c2_sleep: bls !! 1094 blsp2_i2c2_sleep: blsp2-i2c2-sleep {
1392 pins = "gpio6 1095 pins = "gpio6", "gpio7";
1393 function = "g 1096 function = "gpio";
1394 drive-strengt 1097 drive-strength = <2>;
1395 bias-disable; 1098 bias-disable;
1396 }; 1099 };
1397 1100
1398 blsp1_i2c6_default: b !! 1101 cci0_default: cci0-default {
1399 pins = "gpio2 <<
1400 function = "b <<
1401 drive-strengt <<
1402 bias-disable; <<
1403 }; <<
1404 <<
1405 blsp1_i2c6_sleep: bls <<
1406 pins = "gpio2 <<
1407 function = "g <<
1408 drive-strengt <<
1409 bias-pull-up; <<
1410 }; <<
1411 <<
1412 cci0_default: cci0-de <<
1413 pins = "gpio1 1102 pins = "gpio17", "gpio18";
1414 function = "c 1103 function = "cci_i2c";
1415 drive-strengt 1104 drive-strength = <16>;
1416 bias-disable; 1105 bias-disable;
1417 }; 1106 };
1418 1107
1419 camera0_state_on: 1108 camera0_state_on:
1420 camera_rear_default: !! 1109 camera_rear_default: camera-rear-default {
1421 camera0_mclk: !! 1110 camera0_mclk: mclk0 {
1422 pins 1111 pins = "gpio13";
1423 funct 1112 function = "cam_mclk";
1424 drive 1113 drive-strength = <16>;
1425 bias- 1114 bias-disable;
1426 }; 1115 };
1427 1116
1428 camera0_rst: !! 1117 camera0_rst: rst {
1429 pins 1118 pins = "gpio25";
1430 funct 1119 function = "gpio";
1431 drive 1120 drive-strength = <16>;
1432 bias- 1121 bias-disable;
1433 }; 1122 };
1434 1123
1435 camera0_pwdn: !! 1124 camera0_pwdn: pwdn {
1436 pins 1125 pins = "gpio26";
1437 funct 1126 function = "gpio";
1438 drive 1127 drive-strength = <16>;
1439 bias- 1128 bias-disable;
1440 }; 1129 };
1441 }; 1130 };
1442 1131
1443 cci1_default: cci1-de !! 1132 cci1_default: cci1-default {
1444 pins = "gpio1 1133 pins = "gpio19", "gpio20";
1445 function = "c 1134 function = "cci_i2c";
1446 drive-strengt 1135 drive-strength = <16>;
1447 bias-disable; 1136 bias-disable;
1448 }; 1137 };
1449 1138
1450 camera1_state_on: 1139 camera1_state_on:
1451 camera_board_default: !! 1140 camera_board_default: camera-board-default {
1452 mclk1-pins { !! 1141 mclk1 {
1453 pins 1142 pins = "gpio14";
1454 funct 1143 function = "cam_mclk";
1455 drive 1144 drive-strength = <16>;
1456 bias- 1145 bias-disable;
1457 }; 1146 };
1458 1147
1459 pwdn-pins { !! 1148 pwdn {
1460 pins 1149 pins = "gpio98";
1461 funct 1150 function = "gpio";
1462 drive 1151 drive-strength = <16>;
1463 bias- 1152 bias-disable;
1464 }; 1153 };
1465 1154
1466 rst-pins { !! 1155 rst {
1467 pins 1156 pins = "gpio104";
1468 funct 1157 function = "gpio";
1469 drive 1158 drive-strength = <16>;
1470 bias- 1159 bias-disable;
1471 }; 1160 };
1472 }; 1161 };
1473 1162
1474 camera2_state_on: 1163 camera2_state_on:
1475 camera_front_default: !! 1164 camera_front_default: camera-front-default {
1476 camera2_mclk: !! 1165 camera2_mclk: mclk2 {
1477 pins 1166 pins = "gpio15";
1478 funct 1167 function = "cam_mclk";
1479 drive 1168 drive-strength = <16>;
1480 bias- 1169 bias-disable;
1481 }; 1170 };
1482 1171
1483 camera2_rst: !! 1172 camera2_rst: rst {
1484 pins 1173 pins = "gpio23";
1485 funct 1174 function = "gpio";
1486 drive 1175 drive-strength = <16>;
1487 bias- 1176 bias-disable;
1488 }; 1177 };
1489 1178
1490 pwdn-pins { !! 1179 pwdn {
1491 pins 1180 pins = "gpio133";
1492 funct 1181 function = "gpio";
1493 drive 1182 drive-strength = <16>;
1494 bias- 1183 bias-disable;
1495 }; 1184 };
1496 }; 1185 };
1497 1186
1498 pcie0_state_on: pcie0 !! 1187 pcie0_state_on: pcie0-state-on {
1499 perst-pins { !! 1188 perst {
1500 pins 1189 pins = "gpio35";
1501 funct 1190 function = "gpio";
1502 drive 1191 drive-strength = <2>;
1503 bias- 1192 bias-pull-down;
1504 }; 1193 };
1505 1194
1506 clkreq-pins { !! 1195 clkreq {
1507 pins 1196 pins = "gpio36";
1508 funct 1197 function = "pci_e0";
1509 drive 1198 drive-strength = <2>;
1510 bias- 1199 bias-pull-up;
1511 }; 1200 };
1512 1201
1513 wake-pins { !! 1202 wake {
1514 pins 1203 pins = "gpio37";
1515 funct 1204 function = "gpio";
1516 drive 1205 drive-strength = <2>;
1517 bias- 1206 bias-pull-up;
1518 }; 1207 };
1519 }; 1208 };
1520 1209
1521 pcie0_state_off: pcie !! 1210 pcie0_state_off: pcie0-state-off {
1522 perst-pins { !! 1211 perst {
1523 pins 1212 pins = "gpio35";
1524 funct 1213 function = "gpio";
1525 drive 1214 drive-strength = <2>;
1526 bias- 1215 bias-pull-down;
1527 }; 1216 };
1528 1217
1529 clkreq-pins { !! 1218 clkreq {
1530 pins 1219 pins = "gpio36";
1531 funct 1220 function = "gpio";
1532 drive 1221 drive-strength = <2>;
1533 bias- 1222 bias-disable;
1534 }; 1223 };
1535 1224
1536 wake-pins { !! 1225 wake {
1537 pins 1226 pins = "gpio37";
1538 funct 1227 function = "gpio";
1539 drive 1228 drive-strength = <2>;
1540 bias- 1229 bias-disable;
1541 }; 1230 };
1542 }; 1231 };
1543 1232
1544 blsp1_uart2_default: !! 1233 blsp1_uart2_default: blsp1-uart2-default {
1545 pins = "gpio4 1234 pins = "gpio41", "gpio42", "gpio43", "gpio44";
1546 function = "b 1235 function = "blsp_uart2";
1547 drive-strengt 1236 drive-strength = <16>;
1548 bias-disable; 1237 bias-disable;
1549 }; 1238 };
1550 1239
1551 blsp1_uart2_sleep: bl !! 1240 blsp1_uart2_sleep: blsp1-uart2-sleep {
1552 pins = "gpio4 1241 pins = "gpio41", "gpio42", "gpio43", "gpio44";
1553 function = "g 1242 function = "gpio";
1554 drive-strengt 1243 drive-strength = <2>;
1555 bias-disable; 1244 bias-disable;
1556 }; 1245 };
1557 1246
1558 blsp1_i2c3_default: b !! 1247 blsp1_i2c3_default: blsp1-i2c2-default {
1559 pins = "gpio4 1248 pins = "gpio47", "gpio48";
1560 function = "b 1249 function = "blsp_i2c3";
1561 drive-strengt 1250 drive-strength = <16>;
1562 bias-disable; !! 1251 bias-disable = <0>;
1563 }; 1252 };
1564 1253
1565 blsp1_i2c3_sleep: bls !! 1254 blsp1_i2c3_sleep: blsp1-i2c2-sleep {
1566 pins = "gpio4 1255 pins = "gpio47", "gpio48";
1567 function = "g 1256 function = "gpio";
1568 drive-strengt 1257 drive-strength = <2>;
1569 bias-disable; !! 1258 bias-disable = <0>;
1570 }; 1259 };
1571 1260
1572 blsp2_uart3_4pins_def !! 1261 blsp2_uart3_4pins_default: blsp2-uart2-4pins {
1573 pins = "gpio4 1262 pins = "gpio49", "gpio50", "gpio51", "gpio52";
1574 function = "b 1263 function = "blsp_uart9";
1575 drive-strengt 1264 drive-strength = <16>;
1576 bias-disable; 1265 bias-disable;
1577 }; 1266 };
1578 1267
1579 blsp2_uart3_4pins_sle !! 1268 blsp2_uart3_4pins_sleep: blsp2-uart2-4pins-sleep {
1580 pins = "gpio4 1269 pins = "gpio49", "gpio50", "gpio51", "gpio52";
1581 function = "b 1270 function = "blsp_uart9";
1582 drive-strengt 1271 drive-strength = <2>;
1583 bias-disable; 1272 bias-disable;
1584 }; 1273 };
1585 1274
1586 blsp2_i2c3_default: b !! 1275 blsp2_i2c3_default: blsp2-i2c3 {
1587 pins = "gpio5 1276 pins = "gpio51", "gpio52";
1588 function = "b 1277 function = "blsp_i2c9";
1589 drive-strengt 1278 drive-strength = <16>;
1590 bias-disable; 1279 bias-disable;
1591 }; 1280 };
1592 1281
1593 blsp2_i2c3_sleep: bls !! 1282 blsp2_i2c3_sleep: blsp2-i2c3-sleep {
1594 pins = "gpio5 1283 pins = "gpio51", "gpio52";
1595 function = "g 1284 function = "gpio";
1596 drive-strengt 1285 drive-strength = <2>;
1597 bias-disable; 1286 bias-disable;
1598 }; 1287 };
1599 1288
1600 wcd_intr_default: wcd !! 1289 wcd_intr_default: wcd-intr-default{
1601 pins = "gpio5 1290 pins = "gpio54";
1602 function = "g 1291 function = "gpio";
1603 drive-strengt 1292 drive-strength = <2>;
1604 bias-pull-dow 1293 bias-pull-down;
>> 1294 input-enable;
1605 }; 1295 };
1606 1296
1607 blsp2_i2c1_default: b !! 1297 blsp2_i2c1_default: blsp2-i2c1 {
1608 pins = "gpio5 1298 pins = "gpio55", "gpio56";
1609 function = "b 1299 function = "blsp_i2c7";
1610 drive-strengt 1300 drive-strength = <16>;
1611 bias-disable; 1301 bias-disable;
1612 }; 1302 };
1613 1303
1614 blsp2_i2c1_sleep: bls !! 1304 blsp2_i2c1_sleep: blsp2-i2c0-sleep {
1615 pins = "gpio5 1305 pins = "gpio55", "gpio56";
1616 function = "g 1306 function = "gpio";
1617 drive-strengt 1307 drive-strength = <2>;
1618 bias-disable; 1308 bias-disable;
1619 }; 1309 };
1620 1310
1621 blsp2_i2c5_default: b !! 1311 blsp2_i2c5_default: blsp2-i2c5 {
1622 pins = "gpio6 1312 pins = "gpio60", "gpio61";
1623 function = "b 1313 function = "blsp_i2c11";
1624 drive-strengt 1314 drive-strength = <2>;
1625 bias-disable; 1315 bias-disable;
1626 }; 1316 };
1627 1317
1628 /* Sleep state for BL 1318 /* Sleep state for BLSP2_I2C5 is missing.. */
1629 1319
1630 cdc_reset_active: cdc !! 1320 cdc_reset_active: cdc-reset-active {
1631 pins = "gpio6 1321 pins = "gpio64";
1632 function = "g 1322 function = "gpio";
1633 drive-strengt 1323 drive-strength = <16>;
1634 bias-pull-dow 1324 bias-pull-down;
1635 output-high; 1325 output-high;
1636 }; 1326 };
1637 1327
1638 cdc_reset_sleep: cdc- !! 1328 cdc_reset_sleep: cdc-reset-sleep {
1639 pins = "gpio6 1329 pins = "gpio64";
1640 function = "g 1330 function = "gpio";
1641 drive-strengt 1331 drive-strength = <16>;
1642 bias-disable; 1332 bias-disable;
1643 output-low; 1333 output-low;
1644 }; 1334 };
1645 1335
1646 blsp2_spi6_default: b !! 1336 blsp2_spi6_default: blsp2-spi5-default {
1647 spi-pins { !! 1337 spi {
1648 pins 1338 pins = "gpio85", "gpio86", "gpio88";
1649 funct 1339 function = "blsp_spi12";
1650 drive 1340 drive-strength = <12>;
1651 bias- 1341 bias-disable;
1652 }; 1342 };
1653 1343
1654 cs-pins { !! 1344 cs {
1655 pins 1345 pins = "gpio87";
1656 funct 1346 function = "gpio";
1657 drive 1347 drive-strength = <16>;
1658 bias- 1348 bias-disable;
1659 outpu 1349 output-high;
1660 }; 1350 };
1661 }; 1351 };
1662 1352
1663 blsp2_spi6_sleep: bls !! 1353 blsp2_spi6_sleep: blsp2-spi5-sleep {
1664 pins = "gpio8 1354 pins = "gpio85", "gpio86", "gpio87", "gpio88";
1665 function = "g 1355 function = "gpio";
1666 drive-strengt 1356 drive-strength = <2>;
1667 bias-pull-dow 1357 bias-pull-down;
1668 }; 1358 };
1669 1359
1670 blsp2_i2c6_default: b !! 1360 blsp2_i2c6_default: blsp2-i2c6 {
1671 pins = "gpio8 1361 pins = "gpio87", "gpio88";
1672 function = "b 1362 function = "blsp_i2c12";
1673 drive-strengt 1363 drive-strength = <16>;
1674 bias-disable; 1364 bias-disable;
1675 }; 1365 };
1676 1366
1677 blsp2_i2c6_sleep: bls !! 1367 blsp2_i2c6_sleep: blsp2-i2c6-sleep {
1678 pins = "gpio8 1368 pins = "gpio87", "gpio88";
1679 function = "g 1369 function = "gpio";
1680 drive-strengt 1370 drive-strength = <2>;
1681 bias-disable; 1371 bias-disable;
1682 }; 1372 };
1683 1373
1684 pcie1_state_on: pcie1 !! 1374 pcie1_state_on: pcie1-state-on {
1685 perst-pins { !! 1375 perst {
1686 pins 1376 pins = "gpio130";
1687 funct 1377 function = "gpio";
1688 drive 1378 drive-strength = <2>;
1689 bias- 1379 bias-pull-down;
1690 }; 1380 };
1691 1381
1692 clkreq-pins { !! 1382 clkreq {
1693 pins 1383 pins = "gpio131";
1694 funct 1384 function = "pci_e1";
1695 drive 1385 drive-strength = <2>;
1696 bias- 1386 bias-pull-up;
1697 }; 1387 };
1698 1388
1699 wake-pins { !! 1389 wake {
1700 pins 1390 pins = "gpio132";
1701 funct 1391 function = "gpio";
1702 drive 1392 drive-strength = <2>;
1703 bias- 1393 bias-pull-down;
1704 }; 1394 };
1705 }; 1395 };
1706 1396
1707 pcie1_state_off: pcie !! 1397 pcie1_state_off: pcie1-state-off {
1708 /* Perst is m 1398 /* Perst is missing? */
1709 clkreq-pins { !! 1399 clkreq {
1710 pins 1400 pins = "gpio131";
1711 funct 1401 function = "gpio";
1712 drive 1402 drive-strength = <2>;
1713 bias- 1403 bias-disable;
1714 }; 1404 };
1715 1405
1716 wake-pins { !! 1406 wake {
1717 pins 1407 pins = "gpio132";
1718 funct 1408 function = "gpio";
1719 drive 1409 drive-strength = <2>;
1720 bias- 1410 bias-disable;
1721 }; 1411 };
1722 }; 1412 };
1723 1413
1724 pcie2_state_on: pcie2 !! 1414 pcie2_state_on: pcie2-state-on {
1725 perst-pins { !! 1415 perst {
1726 pins 1416 pins = "gpio114";
1727 funct 1417 function = "gpio";
1728 drive 1418 drive-strength = <2>;
1729 bias- 1419 bias-pull-down;
1730 }; 1420 };
1731 1421
1732 clkreq-pins { !! 1422 clkreq {
1733 pins 1423 pins = "gpio115";
1734 funct 1424 function = "pci_e2";
1735 drive 1425 drive-strength = <2>;
1736 bias- 1426 bias-pull-up;
1737 }; 1427 };
1738 1428
1739 wake-pins { !! 1429 wake {
1740 pins 1430 pins = "gpio116";
1741 funct 1431 function = "gpio";
1742 drive 1432 drive-strength = <2>;
1743 bias- 1433 bias-pull-down;
1744 }; 1434 };
1745 }; 1435 };
1746 1436
1747 pcie2_state_off: pcie !! 1437 pcie2_state_off: pcie2-state-off {
1748 /* Perst is m 1438 /* Perst is missing? */
1749 clkreq-pins { !! 1439 clkreq {
1750 pins 1440 pins = "gpio115";
1751 funct 1441 function = "gpio";
1752 drive 1442 drive-strength = <2>;
1753 bias- 1443 bias-disable;
1754 }; 1444 };
1755 1445
1756 wake-pins { !! 1446 wake {
1757 pins 1447 pins = "gpio116";
1758 funct 1448 function = "gpio";
1759 drive 1449 drive-strength = <2>;
1760 bias- 1450 bias-disable;
1761 }; 1451 };
1762 }; 1452 };
1763 1453
1764 sdc1_state_on: sdc1-o !! 1454 sdc1_state_on: sdc1-state-on {
1765 clk-pins { !! 1455 clk {
1766 pins 1456 pins = "sdc1_clk";
1767 bias- 1457 bias-disable;
1768 drive 1458 drive-strength = <16>;
1769 }; 1459 };
1770 1460
1771 cmd-pins { !! 1461 cmd {
1772 pins 1462 pins = "sdc1_cmd";
1773 bias- 1463 bias-pull-up;
1774 drive 1464 drive-strength = <10>;
1775 }; 1465 };
1776 1466
1777 data-pins { !! 1467 data {
1778 pins 1468 pins = "sdc1_data";
1779 bias- 1469 bias-pull-up;
1780 drive 1470 drive-strength = <10>;
1781 }; 1471 };
1782 1472
1783 rclk-pins { !! 1473 rclk {
1784 pins 1474 pins = "sdc1_rclk";
1785 bias- 1475 bias-pull-down;
1786 }; 1476 };
1787 }; 1477 };
1788 1478
1789 sdc1_state_off: sdc1- !! 1479 sdc1_state_off: sdc1-state-off {
1790 clk-pins { !! 1480 clk {
1791 pins 1481 pins = "sdc1_clk";
1792 bias- 1482 bias-disable;
1793 drive 1483 drive-strength = <2>;
1794 }; 1484 };
1795 1485
1796 cmd-pins { !! 1486 cmd {
1797 pins 1487 pins = "sdc1_cmd";
1798 bias- 1488 bias-pull-up;
1799 drive 1489 drive-strength = <2>;
1800 }; 1490 };
1801 1491
1802 data-pins { !! 1492 data {
1803 pins 1493 pins = "sdc1_data";
1804 bias- 1494 bias-pull-up;
1805 drive 1495 drive-strength = <2>;
1806 }; 1496 };
1807 1497
1808 rclk-pins { !! 1498 rclk {
1809 pins 1499 pins = "sdc1_rclk";
1810 bias- 1500 bias-pull-down;
1811 }; 1501 };
1812 }; 1502 };
1813 1503
1814 sdc2_state_on: sdc2-o !! 1504 sdc2_state_on: sdc2-clk-on {
1815 clk-pins { !! 1505 clk {
1816 pins 1506 pins = "sdc2_clk";
1817 bias- 1507 bias-disable;
1818 drive 1508 drive-strength = <16>;
1819 }; 1509 };
1820 1510
1821 cmd-pins { !! 1511 cmd {
1822 pins 1512 pins = "sdc2_cmd";
1823 bias- 1513 bias-pull-up;
1824 drive 1514 drive-strength = <10>;
1825 }; 1515 };
1826 1516
1827 data-pins { !! 1517 data {
1828 pins 1518 pins = "sdc2_data";
1829 bias- 1519 bias-pull-up;
1830 drive 1520 drive-strength = <10>;
1831 }; 1521 };
1832 }; 1522 };
1833 1523
1834 sdc2_state_off: sdc2- !! 1524 sdc2_state_off: sdc2-clk-off {
1835 clk-pins { !! 1525 clk {
1836 pins 1526 pins = "sdc2_clk";
1837 bias- 1527 bias-disable;
1838 drive 1528 drive-strength = <2>;
1839 }; 1529 };
1840 1530
1841 cmd-pins { !! 1531 cmd {
1842 pins 1532 pins = "sdc2_cmd";
1843 bias- 1533 bias-pull-up;
1844 drive 1534 drive-strength = <2>;
1845 }; 1535 };
1846 1536
1847 data-pins { !! 1537 data {
1848 pins 1538 pins = "sdc2_data";
1849 bias- 1539 bias-pull-up;
1850 drive 1540 drive-strength = <2>;
1851 }; 1541 };
1852 }; 1542 };
1853 }; 1543 };
1854 1544
1855 sram@290000 { 1545 sram@290000 {
1856 compatible = "qcom,rp 1546 compatible = "qcom,rpm-stats";
1857 reg = <0x00290000 0x1 1547 reg = <0x00290000 0x10000>;
1858 }; 1548 };
1859 1549
1860 spmi_bus: spmi@400f000 { !! 1550 spmi_bus: qcom,spmi@400f000 {
1861 compatible = "qcom,sp 1551 compatible = "qcom,spmi-pmic-arb";
1862 reg = <0x0400f000 0x1 1552 reg = <0x0400f000 0x1000>,
1863 <0x04400000 0x8 1553 <0x04400000 0x800000>,
1864 <0x04c00000 0x8 1554 <0x04c00000 0x800000>,
1865 <0x05800000 0x2 1555 <0x05800000 0x200000>,
1866 <0x0400a000 0x0 1556 <0x0400a000 0x002100>;
1867 reg-names = "core", " 1557 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1868 interrupt-names = "pe 1558 interrupt-names = "periph_irq";
1869 interrupts = <GIC_SPI 1559 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
1870 qcom,ee = <0>; 1560 qcom,ee = <0>;
1871 qcom,channel = <0>; 1561 qcom,channel = <0>;
1872 #address-cells = <2>; 1562 #address-cells = <2>;
1873 #size-cells = <0>; 1563 #size-cells = <0>;
1874 interrupt-controller; 1564 interrupt-controller;
1875 #interrupt-cells = <4 1565 #interrupt-cells = <4>;
1876 }; 1566 };
1877 1567
1878 bus@0 { !! 1568 agnoc@0 {
1879 power-domains = <&gcc 1569 power-domains = <&gcc AGGRE0_NOC_GDSC>;
1880 compatible = "simple- 1570 compatible = "simple-pm-bus";
1881 #address-cells = <1>; 1571 #address-cells = <1>;
1882 #size-cells = <1>; 1572 #size-cells = <1>;
1883 ranges = <0x0 0x0 0xf !! 1573 ranges;
1884 1574
1885 pcie0: pcie@600000 { 1575 pcie0: pcie@600000 {
1886 compatible = !! 1576 compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
1887 status = "dis 1577 status = "disabled";
1888 power-domains 1578 power-domains = <&gcc PCIE0_GDSC>;
1889 bus-range = < 1579 bus-range = <0x00 0xff>;
1890 num-lanes = < 1580 num-lanes = <1>;
1891 1581
1892 reg = <0x0060 1582 reg = <0x00600000 0x2000>,
1893 <0x0c00 1583 <0x0c000000 0xf1d>,
1894 <0x0c00 1584 <0x0c000f20 0xa8>,
1895 <0x0c10 1585 <0x0c100000 0x100000>;
1896 reg-names = " 1586 reg-names = "parf", "dbi", "elbi","config";
1897 1587
1898 phys = <&pcie 1588 phys = <&pciephy_0>;
1899 phy-names = " 1589 phy-names = "pciephy";
1900 1590
1901 #address-cell 1591 #address-cells = <3>;
1902 #size-cells = 1592 #size-cells = <2>;
1903 ranges = <0x0 !! 1593 ranges = <0x01000000 0x0 0x0c200000 0x0c200000 0x0 0x100000>,
1904 <0x0 !! 1594 <0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>;
1905 1595
1906 device_type = 1596 device_type = "pci";
1907 1597
1908 interrupts = 1598 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
1909 interrupt-nam 1599 interrupt-names = "msi";
1910 #interrupt-ce 1600 #interrupt-cells = <1>;
1911 interrupt-map 1601 interrupt-map-mask = <0 0 0 0x7>;
1912 interrupt-map 1602 interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1913 1603 <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1914 1604 <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1915 1605 <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1916 1606
1917 pinctrl-names 1607 pinctrl-names = "default", "sleep";
1918 pinctrl-0 = < 1608 pinctrl-0 = <&pcie0_state_on>;
1919 pinctrl-1 = < 1609 pinctrl-1 = <&pcie0_state_off>;
1920 1610
1921 linux,pci-dom 1611 linux,pci-domain = <0>;
1922 1612
1923 clocks = <&gc 1613 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
1924 <&gcc 1614 <&gcc GCC_PCIE_0_AUX_CLK>,
1925 <&gcc 1615 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1926 <&gcc 1616 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1927 <&gcc 1617 <&gcc GCC_PCIE_0_SLV_AXI_CLK>;
1928 1618
1929 clock-names = !! 1619 clock-names = "pipe",
1930 1620 "aux",
1931 1621 "cfg",
1932 1622 "bus_master",
1933 1623 "bus_slave";
1934 1624
1935 pcie@0 { <<
1936 devic <<
1937 reg = <<
1938 bus-r <<
1939 <<
1940 #addr <<
1941 #size <<
1942 range <<
1943 }; <<
1944 }; 1625 };
1945 1626
1946 pcie1: pcie@608000 { 1627 pcie1: pcie@608000 {
1947 compatible = !! 1628 compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
1948 power-domains 1629 power-domains = <&gcc PCIE1_GDSC>;
1949 bus-range = < 1630 bus-range = <0x00 0xff>;
1950 num-lanes = < 1631 num-lanes = <1>;
1951 1632
1952 status = "dis !! 1633 status = "disabled";
1953 1634
1954 reg = <0x0060 1635 reg = <0x00608000 0x2000>,
1955 <0x0d00 1636 <0x0d000000 0xf1d>,
1956 <0x0d00 1637 <0x0d000f20 0xa8>,
1957 <0x0d10 1638 <0x0d100000 0x100000>;
1958 1639
1959 reg-names = " 1640 reg-names = "parf", "dbi", "elbi","config";
1960 1641
1961 phys = <&pcie 1642 phys = <&pciephy_1>;
1962 phy-names = " 1643 phy-names = "pciephy";
1963 1644
1964 #address-cell 1645 #address-cells = <3>;
1965 #size-cells = 1646 #size-cells = <2>;
1966 ranges = <0x0 !! 1647 ranges = <0x01000000 0x0 0x0d200000 0x0d200000 0x0 0x100000>,
1967 <0x0 !! 1648 <0x02000000 0x0 0x0d300000 0x0d300000 0x0 0xd00000>;
1968 1649
1969 device_type = 1650 device_type = "pci";
1970 1651
1971 interrupts = 1652 interrupts = <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>;
1972 interrupt-nam 1653 interrupt-names = "msi";
1973 #interrupt-ce 1654 #interrupt-cells = <1>;
1974 interrupt-map 1655 interrupt-map-mask = <0 0 0 0x7>;
1975 interrupt-map 1656 interrupt-map = <0 0 0 1 &intc 0 272 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1976 1657 <0 0 0 2 &intc 0 273 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1977 1658 <0 0 0 3 &intc 0 274 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1978 1659 <0 0 0 4 &intc 0 275 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1979 1660
1980 pinctrl-names 1661 pinctrl-names = "default", "sleep";
1981 pinctrl-0 = < 1662 pinctrl-0 = <&pcie1_state_on>;
1982 pinctrl-1 = < 1663 pinctrl-1 = <&pcie1_state_off>;
1983 1664
1984 linux,pci-dom 1665 linux,pci-domain = <1>;
1985 1666
1986 clocks = <&gc 1667 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
1987 <&gcc 1668 <&gcc GCC_PCIE_1_AUX_CLK>,
1988 <&gcc 1669 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1989 <&gcc 1670 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
1990 <&gcc 1671 <&gcc GCC_PCIE_1_SLV_AXI_CLK>;
1991 1672
1992 clock-names = !! 1673 clock-names = "pipe",
1993 1674 "aux",
1994 1675 "cfg",
1995 1676 "bus_master",
1996 1677 "bus_slave";
1997 <<
1998 pcie@0 { <<
1999 devic <<
2000 reg = <<
2001 bus-r <<
2002 <<
2003 #addr <<
2004 #size <<
2005 range <<
2006 }; <<
2007 }; 1678 };
2008 1679
2009 pcie2: pcie@610000 { 1680 pcie2: pcie@610000 {
2010 compatible = !! 1681 compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
2011 power-domains 1682 power-domains = <&gcc PCIE2_GDSC>;
2012 bus-range = < 1683 bus-range = <0x00 0xff>;
2013 num-lanes = < 1684 num-lanes = <1>;
2014 status = "dis 1685 status = "disabled";
2015 reg = <0x0061 1686 reg = <0x00610000 0x2000>,
2016 <0x0e00 1687 <0x0e000000 0xf1d>,
2017 <0x0e00 1688 <0x0e000f20 0xa8>,
2018 <0x0e10 1689 <0x0e100000 0x100000>;
2019 1690
2020 reg-names = " 1691 reg-names = "parf", "dbi", "elbi","config";
2021 1692
2022 phys = <&pcie 1693 phys = <&pciephy_2>;
2023 phy-names = " 1694 phy-names = "pciephy";
2024 1695
2025 #address-cell 1696 #address-cells = <3>;
2026 #size-cells = 1697 #size-cells = <2>;
2027 ranges = <0x0 !! 1698 ranges = <0x01000000 0x0 0x0e200000 0x0e200000 0x0 0x100000>,
2028 <0x0 !! 1699 <0x02000000 0x0 0x0e300000 0x0e300000 0x0 0x1d00000>;
2029 1700
2030 device_type = 1701 device_type = "pci";
2031 1702
2032 interrupts = 1703 interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
2033 interrupt-nam 1704 interrupt-names = "msi";
2034 #interrupt-ce 1705 #interrupt-cells = <1>;
2035 interrupt-map 1706 interrupt-map-mask = <0 0 0 0x7>;
2036 interrupt-map 1707 interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2037 1708 <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2038 1709 <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2039 1710 <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2040 1711
2041 pinctrl-names 1712 pinctrl-names = "default", "sleep";
2042 pinctrl-0 = < 1713 pinctrl-0 = <&pcie2_state_on>;
2043 pinctrl-1 = < 1714 pinctrl-1 = <&pcie2_state_off>;
2044 1715
2045 linux,pci-dom 1716 linux,pci-domain = <2>;
2046 clocks = <&gc 1717 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,
2047 <&gcc 1718 <&gcc GCC_PCIE_2_AUX_CLK>,
2048 <&gcc 1719 <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
2049 <&gcc 1720 <&gcc GCC_PCIE_2_MSTR_AXI_CLK>,
2050 <&gcc 1721 <&gcc GCC_PCIE_2_SLV_AXI_CLK>;
2051 1722
2052 clock-names = !! 1723 clock-names = "pipe",
2053 1724 "aux",
2054 1725 "cfg",
2055 1726 "bus_master",
2056 1727 "bus_slave";
2057 <<
2058 pcie@0 { <<
2059 devic <<
2060 reg = <<
2061 bus-r <<
2062 <<
2063 #addr <<
2064 #size <<
2065 range <<
2066 }; <<
2067 }; 1728 };
2068 }; 1729 };
2069 1730
2070 ufshc: ufshc@624000 { 1731 ufshc: ufshc@624000 {
2071 compatible = "qcom,ms !! 1732 compatible = "qcom,ufshc";
2072 "jedec,u <<
2073 reg = <0x00624000 0x2 1733 reg = <0x00624000 0x2500>;
2074 interrupts = <GIC_SPI 1734 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
2075 1735
2076 phys = <&ufsphy>; !! 1736 phys = <&ufsphy_lane>;
2077 phy-names = "ufsphy"; 1737 phy-names = "ufsphy";
2078 1738
2079 power-domains = <&gcc 1739 power-domains = <&gcc UFS_GDSC>;
2080 1740
2081 clock-names = 1741 clock-names =
>> 1742 "core_clk_src",
2082 "core_clk", 1743 "core_clk",
2083 "bus_clk", 1744 "bus_clk",
2084 "bus_aggr_clk 1745 "bus_aggr_clk",
2085 "iface_clk", 1746 "iface_clk",
>> 1747 "core_clk_unipro_src",
2086 "core_clk_uni 1748 "core_clk_unipro",
2087 "core_clk_ice 1749 "core_clk_ice",
2088 "ref_clk", 1750 "ref_clk",
2089 "tx_lane0_syn 1751 "tx_lane0_sync_clk",
2090 "rx_lane0_syn 1752 "rx_lane0_sync_clk";
2091 clocks = 1753 clocks =
>> 1754 <&gcc UFS_AXI_CLK_SRC>,
2092 <&gcc GCC_UFS 1755 <&gcc GCC_UFS_AXI_CLK>,
2093 <&gcc GCC_SYS 1756 <&gcc GCC_SYS_NOC_UFS_AXI_CLK>,
2094 <&gcc GCC_AGG 1757 <&gcc GCC_AGGRE2_UFS_AXI_CLK>,
2095 <&gcc GCC_UFS 1758 <&gcc GCC_UFS_AHB_CLK>,
>> 1759 <&gcc UFS_ICE_CORE_CLK_SRC>,
2096 <&gcc GCC_UFS 1760 <&gcc GCC_UFS_UNIPRO_CORE_CLK>,
2097 <&gcc GCC_UFS 1761 <&gcc GCC_UFS_ICE_CORE_CLK>,
2098 <&rpmcc RPM_S 1762 <&rpmcc RPM_SMD_LN_BB_CLK>,
2099 <&gcc GCC_UFS 1763 <&gcc GCC_UFS_TX_SYMBOL_0_CLK>,
2100 <&gcc GCC_UFS 1764 <&gcc GCC_UFS_RX_SYMBOL_0_CLK>;
2101 freq-table-hz = 1765 freq-table-hz =
2102 <100000000 20 1766 <100000000 200000000>,
2103 <0 0>, 1767 <0 0>,
2104 <0 0>, 1768 <0 0>,
2105 <0 0>, 1769 <0 0>,
2106 <75000000 150 !! 1770 <0 0>,
2107 <150000000 30 1771 <150000000 300000000>,
2108 <0 0>, 1772 <0 0>,
2109 <0 0>, 1773 <0 0>,
>> 1774 <0 0>,
>> 1775 <0 0>,
2110 <0 0>; 1776 <0 0>;
2111 1777
2112 interconnects = <&a2n <<
2113 <&bim <<
2114 interconnect-names = <<
2115 <<
2116 lanes-per-direction = 1778 lanes-per-direction = <1>;
2117 #reset-cells = <1>; 1779 #reset-cells = <1>;
2118 status = "disabled"; 1780 status = "disabled";
>> 1781
>> 1782 ufs_variant {
>> 1783 compatible = "qcom,ufs_variant";
>> 1784 };
2119 }; 1785 };
2120 1786
2121 ufsphy: phy@627000 { 1787 ufsphy: phy@627000 {
2122 compatible = "qcom,ms 1788 compatible = "qcom,msm8996-qmp-ufs-phy";
2123 reg = <0x00627000 0x1 !! 1789 reg = <0x00627000 0x1c4>;
>> 1790 #address-cells = <1>;
>> 1791 #size-cells = <1>;
>> 1792 ranges;
2124 1793
2125 clocks = <&rpmcc RPM_ !! 1794 clocks = <&gcc GCC_UFS_CLKREF_CLK>;
2126 clock-names = "ref", !! 1795 clock-names = "ref";
2127 1796
2128 resets = <&ufshc 0>; 1797 resets = <&ufshc 0>;
2129 reset-names = "ufsphy 1798 reset-names = "ufsphy";
2130 <<
2131 #clock-cells = <1>; <<
2132 #phy-cells = <0>; <<
2133 <<
2134 status = "disabled"; 1799 status = "disabled";
>> 1800
>> 1801 ufsphy_lane: phy@627400 {
>> 1802 reg = <0x627400 0x12c>,
>> 1803 <0x627600 0x200>,
>> 1804 <0x627c00 0x1b4>;
>> 1805 #phy-cells = <0>;
>> 1806 };
2135 }; 1807 };
2136 1808
2137 camss: camss@a34000 { !! 1809 camss: camss@a00000 {
2138 compatible = "qcom,ms 1810 compatible = "qcom,msm8996-camss";
2139 reg = <0x00a34000 0x1 1811 reg = <0x00a34000 0x1000>,
2140 <0x00a00030 0x4 1812 <0x00a00030 0x4>,
2141 <0x00a35000 0x1 1813 <0x00a35000 0x1000>,
2142 <0x00a00038 0x4 1814 <0x00a00038 0x4>,
2143 <0x00a36000 0x1 1815 <0x00a36000 0x1000>,
2144 <0x00a00040 0x4 1816 <0x00a00040 0x4>,
2145 <0x00a30000 0x1 1817 <0x00a30000 0x100>,
2146 <0x00a30400 0x1 1818 <0x00a30400 0x100>,
2147 <0x00a30800 0x1 1819 <0x00a30800 0x100>,
2148 <0x00a30c00 0x1 1820 <0x00a30c00 0x100>,
2149 <0x00a31000 0x5 1821 <0x00a31000 0x500>,
2150 <0x00a00020 0x1 1822 <0x00a00020 0x10>,
2151 <0x00a10000 0x1 1823 <0x00a10000 0x1000>,
2152 <0x00a14000 0x1 1824 <0x00a14000 0x1000>;
2153 reg-names = "csiphy0" 1825 reg-names = "csiphy0",
2154 "csiphy0_clk_ 1826 "csiphy0_clk_mux",
2155 "csiphy1", 1827 "csiphy1",
2156 "csiphy1_clk_ 1828 "csiphy1_clk_mux",
2157 "csiphy2", 1829 "csiphy2",
2158 "csiphy2_clk_ 1830 "csiphy2_clk_mux",
2159 "csid0", 1831 "csid0",
2160 "csid1", 1832 "csid1",
2161 "csid2", 1833 "csid2",
2162 "csid3", 1834 "csid3",
2163 "ispif", 1835 "ispif",
2164 "csi_clk_mux" 1836 "csi_clk_mux",
2165 "vfe0", 1837 "vfe0",
2166 "vfe1"; 1838 "vfe1";
2167 interrupts = <GIC_SPI 1839 interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
2168 <GIC_SPI 79 I 1840 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
2169 <GIC_SPI 80 I 1841 <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>,
2170 <GIC_SPI 296 1842 <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>,
2171 <GIC_SPI 297 1843 <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>,
2172 <GIC_SPI 298 1844 <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>,
2173 <GIC_SPI 299 1845 <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>,
2174 <GIC_SPI 309 1846 <GIC_SPI 309 IRQ_TYPE_EDGE_RISING>,
2175 <GIC_SPI 314 1847 <GIC_SPI 314 IRQ_TYPE_EDGE_RISING>,
2176 <GIC_SPI 315 1848 <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>;
2177 interrupt-names = "cs 1849 interrupt-names = "csiphy0",
2178 "csiphy1", 1850 "csiphy1",
2179 "csiphy2", 1851 "csiphy2",
2180 "csid0", 1852 "csid0",
2181 "csid1", 1853 "csid1",
2182 "csid2", 1854 "csid2",
2183 "csid3", 1855 "csid3",
2184 "ispif", 1856 "ispif",
2185 "vfe0", 1857 "vfe0",
2186 "vfe1"; 1858 "vfe1";
2187 power-domains = <&mmc 1859 power-domains = <&mmcc VFE0_GDSC>,
2188 <&mmc 1860 <&mmcc VFE1_GDSC>;
2189 clocks = <&mmcc CAMSS 1861 clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
2190 <&mmcc CAMSS_ 1862 <&mmcc CAMSS_ISPIF_AHB_CLK>,
2191 <&mmcc CAMSS_ 1863 <&mmcc CAMSS_CSI0PHYTIMER_CLK>,
2192 <&mmcc CAMSS_ 1864 <&mmcc CAMSS_CSI1PHYTIMER_CLK>,
2193 <&mmcc CAMSS_ 1865 <&mmcc CAMSS_CSI2PHYTIMER_CLK>,
2194 <&mmcc CAMSS_ 1866 <&mmcc CAMSS_CSI0_AHB_CLK>,
2195 <&mmcc CAMSS_ 1867 <&mmcc CAMSS_CSI0_CLK>,
2196 <&mmcc CAMSS_ 1868 <&mmcc CAMSS_CSI0PHY_CLK>,
2197 <&mmcc CAMSS_ 1869 <&mmcc CAMSS_CSI0PIX_CLK>,
2198 <&mmcc CAMSS_ 1870 <&mmcc CAMSS_CSI0RDI_CLK>,
2199 <&mmcc CAMSS_ 1871 <&mmcc CAMSS_CSI1_AHB_CLK>,
2200 <&mmcc CAMSS_ 1872 <&mmcc CAMSS_CSI1_CLK>,
2201 <&mmcc CAMSS_ 1873 <&mmcc CAMSS_CSI1PHY_CLK>,
2202 <&mmcc CAMSS_ 1874 <&mmcc CAMSS_CSI1PIX_CLK>,
2203 <&mmcc CAMSS_ 1875 <&mmcc CAMSS_CSI1RDI_CLK>,
2204 <&mmcc CAMSS_ 1876 <&mmcc CAMSS_CSI2_AHB_CLK>,
2205 <&mmcc CAMSS_ 1877 <&mmcc CAMSS_CSI2_CLK>,
2206 <&mmcc CAMSS_ 1878 <&mmcc CAMSS_CSI2PHY_CLK>,
2207 <&mmcc CAMSS_ 1879 <&mmcc CAMSS_CSI2PIX_CLK>,
2208 <&mmcc CAMSS_ 1880 <&mmcc CAMSS_CSI2RDI_CLK>,
2209 <&mmcc CAMSS_ 1881 <&mmcc CAMSS_CSI3_AHB_CLK>,
2210 <&mmcc CAMSS_ 1882 <&mmcc CAMSS_CSI3_CLK>,
2211 <&mmcc CAMSS_ 1883 <&mmcc CAMSS_CSI3PHY_CLK>,
2212 <&mmcc CAMSS_ 1884 <&mmcc CAMSS_CSI3PIX_CLK>,
2213 <&mmcc CAMSS_ 1885 <&mmcc CAMSS_CSI3RDI_CLK>,
2214 <&mmcc CAMSS_ 1886 <&mmcc CAMSS_AHB_CLK>,
2215 <&mmcc CAMSS_ 1887 <&mmcc CAMSS_VFE0_CLK>,
2216 <&mmcc CAMSS_ 1888 <&mmcc CAMSS_CSI_VFE0_CLK>,
2217 <&mmcc CAMSS_ 1889 <&mmcc CAMSS_VFE0_AHB_CLK>,
2218 <&mmcc CAMSS_ 1890 <&mmcc CAMSS_VFE0_STREAM_CLK>,
2219 <&mmcc CAMSS_ 1891 <&mmcc CAMSS_VFE1_CLK>,
2220 <&mmcc CAMSS_ 1892 <&mmcc CAMSS_CSI_VFE1_CLK>,
2221 <&mmcc CAMSS_ 1893 <&mmcc CAMSS_VFE1_AHB_CLK>,
2222 <&mmcc CAMSS_ 1894 <&mmcc CAMSS_VFE1_STREAM_CLK>,
2223 <&mmcc CAMSS_ 1895 <&mmcc CAMSS_VFE_AHB_CLK>,
2224 <&mmcc CAMSS_ 1896 <&mmcc CAMSS_VFE_AXI_CLK>;
2225 clock-names = "top_ah 1897 clock-names = "top_ahb",
2226 "ispif_ahb", 1898 "ispif_ahb",
2227 "csiphy0_time 1899 "csiphy0_timer",
2228 "csiphy1_time 1900 "csiphy1_timer",
2229 "csiphy2_time 1901 "csiphy2_timer",
2230 "csi0_ahb", 1902 "csi0_ahb",
2231 "csi0", 1903 "csi0",
2232 "csi0_phy", 1904 "csi0_phy",
2233 "csi0_pix", 1905 "csi0_pix",
2234 "csi0_rdi", 1906 "csi0_rdi",
2235 "csi1_ahb", 1907 "csi1_ahb",
2236 "csi1", 1908 "csi1",
2237 "csi1_phy", 1909 "csi1_phy",
2238 "csi1_pix", 1910 "csi1_pix",
2239 "csi1_rdi", 1911 "csi1_rdi",
2240 "csi2_ahb", 1912 "csi2_ahb",
2241 "csi2", 1913 "csi2",
2242 "csi2_phy", 1914 "csi2_phy",
2243 "csi2_pix", 1915 "csi2_pix",
2244 "csi2_rdi", 1916 "csi2_rdi",
2245 "csi3_ahb", 1917 "csi3_ahb",
2246 "csi3", 1918 "csi3",
2247 "csi3_phy", 1919 "csi3_phy",
2248 "csi3_pix", 1920 "csi3_pix",
2249 "csi3_rdi", 1921 "csi3_rdi",
2250 "ahb", 1922 "ahb",
2251 "vfe0", 1923 "vfe0",
2252 "csi_vfe0", 1924 "csi_vfe0",
2253 "vfe0_ahb", 1925 "vfe0_ahb",
2254 "vfe0_stream" 1926 "vfe0_stream",
2255 "vfe1", 1927 "vfe1",
2256 "csi_vfe1", 1928 "csi_vfe1",
2257 "vfe1_ahb", 1929 "vfe1_ahb",
2258 "vfe1_stream" 1930 "vfe1_stream",
2259 "vfe_ahb", 1931 "vfe_ahb",
2260 "vfe_axi"; 1932 "vfe_axi";
2261 iommus = <&vfe_smmu 0 1933 iommus = <&vfe_smmu 0>,
2262 <&vfe_smmu 1 1934 <&vfe_smmu 1>,
2263 <&vfe_smmu 2 1935 <&vfe_smmu 2>,
2264 <&vfe_smmu 3 1936 <&vfe_smmu 3>;
2265 status = "disabled"; 1937 status = "disabled";
2266 ports { 1938 ports {
2267 #address-cell 1939 #address-cells = <1>;
2268 #size-cells = 1940 #size-cells = <0>;
2269 }; 1941 };
2270 }; 1942 };
2271 1943
2272 cci: cci@a0c000 { 1944 cci: cci@a0c000 {
2273 compatible = "qcom,ms 1945 compatible = "qcom,msm8996-cci";
2274 #address-cells = <1>; 1946 #address-cells = <1>;
2275 #size-cells = <0>; 1947 #size-cells = <0>;
2276 reg = <0xa0c000 0x100 1948 reg = <0xa0c000 0x1000>;
2277 interrupts = <GIC_SPI 1949 interrupts = <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>;
2278 power-domains = <&mmc 1950 power-domains = <&mmcc CAMSS_GDSC>;
2279 clocks = <&mmcc CAMSS 1951 clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
2280 <&mmcc CAMSS 1952 <&mmcc CAMSS_CCI_AHB_CLK>,
2281 <&mmcc CAMSS 1953 <&mmcc CAMSS_CCI_CLK>,
2282 <&mmcc CAMSS 1954 <&mmcc CAMSS_AHB_CLK>;
2283 clock-names = "camss_ 1955 clock-names = "camss_top_ahb",
2284 "cci_ah 1956 "cci_ahb",
2285 "cci", 1957 "cci",
2286 "camss_ 1958 "camss_ahb";
2287 assigned-clocks = <&m 1959 assigned-clocks = <&mmcc CAMSS_CCI_AHB_CLK>,
2288 <&m 1960 <&mmcc CAMSS_CCI_CLK>;
2289 assigned-clock-rates 1961 assigned-clock-rates = <80000000>, <37500000>;
2290 pinctrl-names = "defa 1962 pinctrl-names = "default";
2291 pinctrl-0 = <&cci0_de 1963 pinctrl-0 = <&cci0_default &cci1_default>;
2292 status = "disabled"; 1964 status = "disabled";
2293 1965
2294 cci_i2c0: i2c-bus@0 { 1966 cci_i2c0: i2c-bus@0 {
2295 reg = <0>; 1967 reg = <0>;
2296 clock-frequen 1968 clock-frequency = <400000>;
2297 #address-cell 1969 #address-cells = <1>;
2298 #size-cells = 1970 #size-cells = <0>;
2299 }; 1971 };
2300 1972
2301 cci_i2c1: i2c-bus@1 { 1973 cci_i2c1: i2c-bus@1 {
2302 reg = <1>; 1974 reg = <1>;
2303 clock-frequen 1975 clock-frequency = <400000>;
2304 #address-cell 1976 #address-cells = <1>;
2305 #size-cells = 1977 #size-cells = <0>;
2306 }; 1978 };
2307 }; 1979 };
2308 1980
2309 adreno_smmu: iommu@b40000 { 1981 adreno_smmu: iommu@b40000 {
2310 compatible = "qcom,ms 1982 compatible = "qcom,msm8996-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
2311 reg = <0x00b40000 0x1 1983 reg = <0x00b40000 0x10000>;
2312 1984
2313 #global-interrupts = 1985 #global-interrupts = <1>;
2314 interrupts = <GIC_SPI 1986 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
2315 <GIC_SPI 1987 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
2316 <GIC_SPI 1988 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
2317 #iommu-cells = <1>; 1989 #iommu-cells = <1>;
2318 1990
2319 clocks = <&gcc GCC_MM !! 1991 clocks = <&mmcc GPU_AHB_CLK>,
2320 <&mmcc GPU_A !! 1992 <&gcc GCC_MMSS_BIMC_GFX_CLK>;
2321 clock-names = "bus", !! 1993 clock-names = "iface", "bus";
2322 1994
2323 power-domains = <&mmc 1995 power-domains = <&mmcc GPU_GDSC>;
2324 }; 1996 };
2325 1997
2326 venus: video-codec@c00000 { 1998 venus: video-codec@c00000 {
2327 compatible = "qcom,ms 1999 compatible = "qcom,msm8996-venus";
2328 reg = <0x00c00000 0xf 2000 reg = <0x00c00000 0xff000>;
2329 interrupts = <GIC_SPI 2001 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
2330 power-domains = <&mmc 2002 power-domains = <&mmcc VENUS_GDSC>;
2331 clocks = <&mmcc VIDEO 2003 clocks = <&mmcc VIDEO_CORE_CLK>,
2332 <&mmcc VIDEO 2004 <&mmcc VIDEO_AHB_CLK>,
2333 <&mmcc VIDEO 2005 <&mmcc VIDEO_AXI_CLK>,
2334 <&mmcc VIDEO 2006 <&mmcc VIDEO_MAXI_CLK>;
2335 clock-names = "core", 2007 clock-names = "core", "iface", "bus", "mbus";
2336 interconnects = <&mno <<
2337 <&bim <<
2338 interconnect-names = <<
2339 iommus = <&venus_smmu 2008 iommus = <&venus_smmu 0x00>,
2340 <&venus_smmu 2009 <&venus_smmu 0x01>,
2341 <&venus_smmu 2010 <&venus_smmu 0x0a>,
2342 <&venus_smmu 2011 <&venus_smmu 0x07>,
2343 <&venus_smmu 2012 <&venus_smmu 0x0e>,
2344 <&venus_smmu 2013 <&venus_smmu 0x0f>,
2345 <&venus_smmu 2014 <&venus_smmu 0x08>,
2346 <&venus_smmu 2015 <&venus_smmu 0x09>,
2347 <&venus_smmu 2016 <&venus_smmu 0x0b>,
2348 <&venus_smmu 2017 <&venus_smmu 0x0c>,
2349 <&venus_smmu 2018 <&venus_smmu 0x0d>,
2350 <&venus_smmu 2019 <&venus_smmu 0x10>,
2351 <&venus_smmu 2020 <&venus_smmu 0x11>,
2352 <&venus_smmu 2021 <&venus_smmu 0x21>,
2353 <&venus_smmu 2022 <&venus_smmu 0x28>,
2354 <&venus_smmu 2023 <&venus_smmu 0x29>,
2355 <&venus_smmu 2024 <&venus_smmu 0x2b>,
2356 <&venus_smmu 2025 <&venus_smmu 0x2c>,
2357 <&venus_smmu 2026 <&venus_smmu 0x2d>,
2358 <&venus_smmu 2027 <&venus_smmu 0x31>;
2359 memory-region = <&ven !! 2028 memory-region = <&venus_region>;
2360 status = "disabled"; 2029 status = "disabled";
2361 2030
2362 video-decoder { 2031 video-decoder {
2363 compatible = 2032 compatible = "venus-decoder";
2364 clocks = <&mm 2033 clocks = <&mmcc VIDEO_SUBCORE0_CLK>;
2365 clock-names = 2034 clock-names = "core";
2366 power-domains 2035 power-domains = <&mmcc VENUS_CORE0_GDSC>;
2367 }; 2036 };
2368 2037
2369 video-encoder { 2038 video-encoder {
2370 compatible = 2039 compatible = "venus-encoder";
2371 clocks = <&mm 2040 clocks = <&mmcc VIDEO_SUBCORE1_CLK>;
2372 clock-names = 2041 clock-names = "core";
2373 power-domains 2042 power-domains = <&mmcc VENUS_CORE1_GDSC>;
2374 }; 2043 };
2375 }; 2044 };
2376 2045
2377 mdp_smmu: iommu@d00000 { 2046 mdp_smmu: iommu@d00000 {
2378 compatible = "qcom,ms 2047 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2379 reg = <0x00d00000 0x1 2048 reg = <0x00d00000 0x10000>;
2380 2049
2381 #global-interrupts = 2050 #global-interrupts = <1>;
2382 interrupts = <GIC_SPI 2051 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
2383 <GIC_SPI 2052 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
2384 <GIC_SPI 2053 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
2385 #iommu-cells = <1>; 2054 #iommu-cells = <1>;
2386 clocks = <&mmcc SMMU_ !! 2055 clocks = <&mmcc SMMU_MDP_AHB_CLK>,
2387 <&mmcc SMMU_ !! 2056 <&mmcc SMMU_MDP_AXI_CLK>;
2388 clock-names = "bus", !! 2057 clock-names = "iface", "bus";
2389 2058
2390 power-domains = <&mmc 2059 power-domains = <&mmcc MDSS_GDSC>;
2391 }; 2060 };
2392 2061
2393 venus_smmu: iommu@d40000 { 2062 venus_smmu: iommu@d40000 {
2394 compatible = "qcom,ms 2063 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2395 reg = <0x00d40000 0x2 2064 reg = <0x00d40000 0x20000>;
2396 #global-interrupts = 2065 #global-interrupts = <1>;
2397 interrupts = <GIC_SPI 2066 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>,
2398 <GIC_SPI 2067 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
2399 <GIC_SPI 2068 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
2400 <GIC_SPI 2069 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
2401 <GIC_SPI 2070 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
2402 <GIC_SPI 2071 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
2403 <GIC_SPI 2072 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
2404 <GIC_SPI 2073 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
2405 power-domains = <&mmc 2074 power-domains = <&mmcc MMAGIC_VIDEO_GDSC>;
2406 clocks = <&mmcc SMMU_ !! 2075 clocks = <&mmcc SMMU_VIDEO_AHB_CLK>,
2407 <&mmcc SMMU_ !! 2076 <&mmcc SMMU_VIDEO_AXI_CLK>;
2408 clock-names = "bus", !! 2077 clock-names = "iface", "bus";
2409 #iommu-cells = <1>; 2078 #iommu-cells = <1>;
2410 status = "okay"; 2079 status = "okay";
2411 }; 2080 };
2412 2081
2413 vfe_smmu: iommu@da0000 { 2082 vfe_smmu: iommu@da0000 {
2414 compatible = "qcom,ms 2083 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2415 reg = <0x00da0000 0x1 2084 reg = <0x00da0000 0x10000>;
2416 2085
2417 #global-interrupts = 2086 #global-interrupts = <1>;
2418 interrupts = <GIC_SPI 2087 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
2419 <GIC_SPI 2088 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
2420 <GIC_SPI 2089 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
2421 power-domains = <&mmc 2090 power-domains = <&mmcc MMAGIC_CAMSS_GDSC>;
2422 clocks = <&mmcc SMMU_ !! 2091 clocks = <&mmcc SMMU_VFE_AHB_CLK>,
2423 <&mmcc SMMU_ !! 2092 <&mmcc SMMU_VFE_AXI_CLK>;
2424 clock-names = "bus", !! 2093 clock-names = "iface",
>> 2094 "bus";
2425 #iommu-cells = <1>; 2095 #iommu-cells = <1>;
2426 }; 2096 };
2427 2097
2428 lpass_q6_smmu: iommu@1600000 2098 lpass_q6_smmu: iommu@1600000 {
2429 compatible = "qcom,ms 2099 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2430 reg = <0x01600000 0x2 2100 reg = <0x01600000 0x20000>;
2431 #iommu-cells = <1>; 2101 #iommu-cells = <1>;
2432 power-domains = <&gcc 2102 power-domains = <&gcc HLOS1_VOTE_LPASS_CORE_GDSC>;
2433 2103
2434 #global-interrupts = 2104 #global-interrupts = <1>;
2435 interrupts = <GIC_SPI 2105 interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
2436 <GIC_SPI 226 2106 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,
2437 <GIC_SPI 393 2107 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
2438 <GIC_SPI 394 2108 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
2439 <GIC_SPI 395 2109 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
2440 <GIC_SPI 396 2110 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
2441 <GIC_SPI 397 2111 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
2442 <GIC_SPI 398 2112 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
2443 <GIC_SPI 399 2113 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
2444 <GIC_SPI 400 2114 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
2445 <GIC_SPI 401 2115 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
2446 <GIC_SPI 402 2116 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
2447 <GIC_SPI 403 2117 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>;
2448 2118
2449 clocks = <&gcc GCC_HL !! 2119 clocks = <&gcc GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK>,
2450 <&gcc GCC_HL !! 2120 <&gcc GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>;
2451 clock-names = "bus", !! 2121 clock-names = "iface", "bus";
2452 }; <<
2453 <<
2454 slpi_pil: remoteproc@1c00000 <<
2455 compatible = "qcom,ms <<
2456 reg = <0x01c00000 0x4 <<
2457 <<
2458 interrupts-extended = <<
2459 <<
2460 <<
2461 <<
2462 <<
2463 interrupt-names = "wd <<
2464 "fa <<
2465 "re <<
2466 "ha <<
2467 "st <<
2468 <<
2469 clocks = <&xo_board>; <<
2470 clock-names = "xo"; <<
2471 <<
2472 memory-region = <&slp <<
2473 <<
2474 qcom,smem-states = <& <<
2475 qcom,smem-state-names <<
2476 <<
2477 power-domains = <&rpm <<
2478 power-domain-names = <<
2479 <<
2480 status = "disabled"; <<
2481 <<
2482 glink-edge { <<
2483 interrupts = <<
2484 label = "dsps <<
2485 qcom,remote-p <<
2486 mboxes = <&ap <<
2487 }; <<
2488 <<
2489 smd-edge { <<
2490 interrupts = <<
2491 <<
2492 label = "dsps <<
2493 mboxes = <&ap <<
2494 qcom,smd-edge <<
2495 qcom,remote-p <<
2496 }; <<
2497 }; <<
2498 <<
2499 mss_pil: remoteproc@2080000 { <<
2500 compatible = "qcom,ms <<
2501 reg = <0x2080000 0x10 <<
2502 <0x2180000 0x02 <<
2503 reg-names = "qdsp6", <<
2504 <<
2505 interrupts-extended = <<
2506 <<
2507 <<
2508 <<
2509 <<
2510 <<
2511 interrupt-names = "wd <<
2512 "ha <<
2513 "sh <<
2514 <<
2515 clocks = <&gcc GCC_MS <<
2516 <&gcc GCC_MS <<
2517 <&gcc GCC_BO <<
2518 <&xo_board>, <<
2519 <&gcc GCC_MS <<
2520 <&gcc GCC_MS <<
2521 <&gcc GCC_MS <<
2522 <&rpmcc RPM_ <<
2523 clock-names = "iface" <<
2524 "bus", <<
2525 "mem", <<
2526 "xo", <<
2527 "gpll0_ <<
2528 "snoc_a <<
2529 "mnoc_a <<
2530 "qdss"; <<
2531 <<
2532 resets = <&gcc GCC_MS <<
2533 reset-names = "mss_re <<
2534 <<
2535 power-domains = <&rpm <<
2536 <&rpm <<
2537 power-domain-names = <<
2538 <<
2539 qcom,smem-states = <& <<
2540 qcom,smem-state-names <<
2541 <<
2542 qcom,halt-regs = <&tc <<
2543 <<
2544 status = "disabled"; <<
2545 <<
2546 mba { <<
2547 memory-region <<
2548 }; <<
2549 <<
2550 mpss { <<
2551 memory-region <<
2552 }; <<
2553 <<
2554 metadata { <<
2555 memory-region <<
2556 }; <<
2557 <<
2558 glink-edge { <<
2559 interrupts = <<
2560 label = "mode <<
2561 qcom,remote-p <<
2562 mboxes = <&ap <<
2563 }; <<
2564 <<
2565 smd-edge { <<
2566 interrupts = <<
2567 <<
2568 label = "mpss <<
2569 mboxes = <&ap <<
2570 qcom,smd-edge <<
2571 qcom,remote-p <<
2572 }; <<
2573 }; 2122 };
2574 2123
2575 stm@3002000 { 2124 stm@3002000 {
2576 compatible = "arm,cor 2125 compatible = "arm,coresight-stm", "arm,primecell";
2577 reg = <0x3002000 0x10 2126 reg = <0x3002000 0x1000>,
2578 <0x8280000 0x18 2127 <0x8280000 0x180000>;
2579 reg-names = "stm-base 2128 reg-names = "stm-base", "stm-stimulus-base";
2580 2129
2581 clocks = <&rpmcc RPM_ 2130 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2582 clock-names = "apb_pc 2131 clock-names = "apb_pclk", "atclk";
2583 2132
2584 out-ports { 2133 out-ports {
2585 port { 2134 port {
2586 stm_o 2135 stm_out: endpoint {
2587 2136 remote-endpoint =
2588 2137 <&funnel0_in>;
2589 }; 2138 };
2590 }; 2139 };
2591 }; 2140 };
2592 }; 2141 };
2593 2142
2594 tpiu@3020000 { 2143 tpiu@3020000 {
2595 compatible = "arm,cor 2144 compatible = "arm,coresight-tpiu", "arm,primecell";
2596 reg = <0x3020000 0x10 2145 reg = <0x3020000 0x1000>;
2597 2146
2598 clocks = <&rpmcc RPM_ 2147 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2599 clock-names = "apb_pc 2148 clock-names = "apb_pclk", "atclk";
2600 2149
2601 in-ports { 2150 in-ports {
2602 port { 2151 port {
2603 tpiu_ 2152 tpiu_in: endpoint {
2604 2153 remote-endpoint =
2605 2154 <&replicator_out1>;
2606 }; 2155 };
2607 }; 2156 };
2608 }; 2157 };
2609 }; 2158 };
2610 2159
2611 funnel@3021000 { 2160 funnel@3021000 {
2612 compatible = "arm,cor 2161 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2613 reg = <0x3021000 0x10 2162 reg = <0x3021000 0x1000>;
2614 2163
2615 clocks = <&rpmcc RPM_ 2164 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2616 clock-names = "apb_pc 2165 clock-names = "apb_pclk", "atclk";
2617 2166
2618 in-ports { 2167 in-ports {
2619 #address-cell 2168 #address-cells = <1>;
2620 #size-cells = 2169 #size-cells = <0>;
2621 2170
2622 port@7 { 2171 port@7 {
2623 reg = 2172 reg = <7>;
2624 funne 2173 funnel0_in: endpoint {
2625 2174 remote-endpoint =
2626 2175 <&stm_out>;
2627 }; 2176 };
2628 }; 2177 };
2629 }; 2178 };
2630 2179
2631 out-ports { 2180 out-ports {
2632 port { 2181 port {
2633 funne 2182 funnel0_out: endpoint {
2634 2183 remote-endpoint =
2635 2184 <&merge_funnel_in0>;
2636 }; 2185 };
2637 }; 2186 };
2638 }; 2187 };
2639 }; 2188 };
2640 2189
2641 funnel@3022000 { 2190 funnel@3022000 {
2642 compatible = "arm,cor 2191 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2643 reg = <0x3022000 0x10 2192 reg = <0x3022000 0x1000>;
2644 2193
2645 clocks = <&rpmcc RPM_ 2194 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2646 clock-names = "apb_pc 2195 clock-names = "apb_pclk", "atclk";
2647 2196
2648 in-ports { 2197 in-ports {
2649 #address-cell 2198 #address-cells = <1>;
2650 #size-cells = 2199 #size-cells = <0>;
2651 2200
2652 port@6 { 2201 port@6 {
2653 reg = 2202 reg = <6>;
2654 funne 2203 funnel1_in: endpoint {
2655 2204 remote-endpoint =
2656 2205 <&apss_merge_funnel_out>;
2657 }; 2206 };
2658 }; 2207 };
2659 }; 2208 };
2660 2209
2661 out-ports { 2210 out-ports {
2662 port { 2211 port {
2663 funne 2212 funnel1_out: endpoint {
2664 2213 remote-endpoint =
2665 2214 <&merge_funnel_in1>;
2666 }; 2215 };
2667 }; 2216 };
2668 }; 2217 };
2669 }; 2218 };
2670 2219
2671 funnel@3023000 { 2220 funnel@3023000 {
2672 compatible = "arm,cor 2221 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2673 reg = <0x3023000 0x10 2222 reg = <0x3023000 0x1000>;
2674 2223
2675 clocks = <&rpmcc RPM_ 2224 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2676 clock-names = "apb_pc 2225 clock-names = "apb_pclk", "atclk";
2677 2226
2678 in-ports { <<
2679 port { <<
2680 funne <<
2681 <<
2682 <<
2683 }; <<
2684 }; <<
2685 }; <<
2686 2227
2687 out-ports { 2228 out-ports {
2688 port { 2229 port {
2689 funne 2230 funnel2_out: endpoint {
2690 2231 remote-endpoint =
2691 2232 <&merge_funnel_in2>;
2692 }; 2233 };
2693 }; 2234 };
2694 }; 2235 };
2695 }; 2236 };
2696 2237
2697 funnel@3025000 { 2238 funnel@3025000 {
2698 compatible = "arm,cor 2239 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2699 reg = <0x3025000 0x10 2240 reg = <0x3025000 0x1000>;
2700 2241
2701 clocks = <&rpmcc RPM_ 2242 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2702 clock-names = "apb_pc 2243 clock-names = "apb_pclk", "atclk";
2703 2244
2704 in-ports { 2245 in-ports {
2705 #address-cell 2246 #address-cells = <1>;
2706 #size-cells = 2247 #size-cells = <0>;
2707 2248
2708 port@0 { 2249 port@0 {
2709 reg = 2250 reg = <0>;
2710 merge 2251 merge_funnel_in0: endpoint {
2711 2252 remote-endpoint =
2712 2253 <&funnel0_out>;
2713 }; 2254 };
2714 }; 2255 };
2715 2256
2716 port@1 { 2257 port@1 {
2717 reg = 2258 reg = <1>;
2718 merge 2259 merge_funnel_in1: endpoint {
2719 2260 remote-endpoint =
2720 2261 <&funnel1_out>;
2721 }; 2262 };
2722 }; 2263 };
2723 2264
2724 port@2 { 2265 port@2 {
2725 reg = 2266 reg = <2>;
2726 merge 2267 merge_funnel_in2: endpoint {
2727 2268 remote-endpoint =
2728 2269 <&funnel2_out>;
2729 }; 2270 };
2730 }; 2271 };
2731 }; 2272 };
2732 2273
2733 out-ports { 2274 out-ports {
2734 port { 2275 port {
2735 merge 2276 merge_funnel_out: endpoint {
2736 2277 remote-endpoint =
2737 2278 <&etf_in>;
2738 }; 2279 };
2739 }; 2280 };
2740 }; 2281 };
2741 }; 2282 };
2742 2283
2743 replicator@3026000 { 2284 replicator@3026000 {
2744 compatible = "arm,cor 2285 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2745 reg = <0x3026000 0x10 2286 reg = <0x3026000 0x1000>;
2746 2287
2747 clocks = <&rpmcc RPM_ 2288 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2748 clock-names = "apb_pc 2289 clock-names = "apb_pclk", "atclk";
2749 2290
2750 in-ports { 2291 in-ports {
2751 port { 2292 port {
2752 repli 2293 replicator_in: endpoint {
2753 2294 remote-endpoint =
2754 2295 <&etf_out>;
2755 }; 2296 };
2756 }; 2297 };
2757 }; 2298 };
2758 2299
2759 out-ports { 2300 out-ports {
2760 #address-cell 2301 #address-cells = <1>;
2761 #size-cells = 2302 #size-cells = <0>;
2762 2303
2763 port@0 { 2304 port@0 {
2764 reg = 2305 reg = <0>;
2765 repli 2306 replicator_out0: endpoint {
2766 2307 remote-endpoint =
2767 2308 <&etr_in>;
2768 }; 2309 };
2769 }; 2310 };
2770 2311
2771 port@1 { 2312 port@1 {
2772 reg = 2313 reg = <1>;
2773 repli 2314 replicator_out1: endpoint {
2774 2315 remote-endpoint =
2775 2316 <&tpiu_in>;
2776 }; 2317 };
2777 }; 2318 };
2778 }; 2319 };
2779 }; 2320 };
2780 2321
2781 etf@3027000 { 2322 etf@3027000 {
2782 compatible = "arm,cor 2323 compatible = "arm,coresight-tmc", "arm,primecell";
2783 reg = <0x3027000 0x10 2324 reg = <0x3027000 0x1000>;
2784 2325
2785 clocks = <&rpmcc RPM_ 2326 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2786 clock-names = "apb_pc 2327 clock-names = "apb_pclk", "atclk";
2787 2328
2788 in-ports { 2329 in-ports {
2789 port { 2330 port {
2790 etf_i 2331 etf_in: endpoint {
2791 2332 remote-endpoint =
2792 2333 <&merge_funnel_out>;
2793 }; 2334 };
2794 }; 2335 };
2795 }; 2336 };
2796 2337
2797 out-ports { 2338 out-ports {
2798 port { 2339 port {
2799 etf_o 2340 etf_out: endpoint {
2800 2341 remote-endpoint =
2801 2342 <&replicator_in>;
2802 }; 2343 };
2803 }; 2344 };
2804 }; 2345 };
2805 }; 2346 };
2806 2347
2807 etr@3028000 { 2348 etr@3028000 {
2808 compatible = "arm,cor 2349 compatible = "arm,coresight-tmc", "arm,primecell";
2809 reg = <0x3028000 0x10 2350 reg = <0x3028000 0x1000>;
2810 2351
2811 clocks = <&rpmcc RPM_ 2352 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2812 clock-names = "apb_pc 2353 clock-names = "apb_pclk", "atclk";
2813 arm,scatter-gather; 2354 arm,scatter-gather;
2814 2355
2815 in-ports { 2356 in-ports {
2816 port { 2357 port {
2817 etr_i 2358 etr_in: endpoint {
2818 2359 remote-endpoint =
2819 2360 <&replicator_out0>;
2820 }; 2361 };
2821 }; 2362 };
2822 }; 2363 };
2823 }; 2364 };
2824 2365
2825 debug@3810000 { 2366 debug@3810000 {
2826 compatible = "arm,cor 2367 compatible = "arm,coresight-cpu-debug", "arm,primecell";
2827 reg = <0x3810000 0x10 2368 reg = <0x3810000 0x1000>;
2828 2369
2829 clocks = <&rpmcc RPM_ 2370 clocks = <&rpmcc RPM_QDSS_CLK>;
2830 clock-names = "apb_pc 2371 clock-names = "apb_pclk";
2831 2372
2832 cpu = <&CPU0>; 2373 cpu = <&CPU0>;
2833 }; 2374 };
2834 2375
2835 etm@3840000 { 2376 etm@3840000 {
2836 compatible = "arm,cor 2377 compatible = "arm,coresight-etm4x", "arm,primecell";
2837 reg = <0x3840000 0x10 2378 reg = <0x3840000 0x1000>;
2838 2379
2839 clocks = <&rpmcc RPM_ 2380 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2840 clock-names = "apb_pc 2381 clock-names = "apb_pclk", "atclk";
2841 2382
2842 cpu = <&CPU0>; 2383 cpu = <&CPU0>;
2843 2384
2844 out-ports { 2385 out-ports {
2845 port { 2386 port {
2846 etm0_ 2387 etm0_out: endpoint {
2847 2388 remote-endpoint =
2848 2389 <&apss_funnel0_in0>;
2849 }; 2390 };
2850 }; 2391 };
2851 }; 2392 };
2852 }; 2393 };
2853 2394
2854 debug@3910000 { 2395 debug@3910000 {
2855 compatible = "arm,cor 2396 compatible = "arm,coresight-cpu-debug", "arm,primecell";
2856 reg = <0x3910000 0x10 2397 reg = <0x3910000 0x1000>;
2857 2398
2858 clocks = <&rpmcc RPM_ 2399 clocks = <&rpmcc RPM_QDSS_CLK>;
2859 clock-names = "apb_pc 2400 clock-names = "apb_pclk";
2860 2401
2861 cpu = <&CPU1>; 2402 cpu = <&CPU1>;
2862 }; 2403 };
2863 2404
2864 etm@3940000 { 2405 etm@3940000 {
2865 compatible = "arm,cor 2406 compatible = "arm,coresight-etm4x", "arm,primecell";
2866 reg = <0x3940000 0x10 2407 reg = <0x3940000 0x1000>;
2867 2408
2868 clocks = <&rpmcc RPM_ 2409 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2869 clock-names = "apb_pc 2410 clock-names = "apb_pclk", "atclk";
2870 2411
2871 cpu = <&CPU1>; 2412 cpu = <&CPU1>;
2872 2413
2873 out-ports { 2414 out-ports {
2874 port { 2415 port {
2875 etm1_ 2416 etm1_out: endpoint {
2876 2417 remote-endpoint =
2877 2418 <&apss_funnel0_in1>;
2878 }; 2419 };
2879 }; 2420 };
2880 }; 2421 };
2881 }; 2422 };
2882 2423
2883 funnel@39b0000 { /* APSS Funn 2424 funnel@39b0000 { /* APSS Funnel 0 */
2884 compatible = "arm,cor 2425 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2885 reg = <0x39b0000 0x10 2426 reg = <0x39b0000 0x1000>;
2886 2427
2887 clocks = <&rpmcc RPM_ 2428 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2888 clock-names = "apb_pc 2429 clock-names = "apb_pclk", "atclk";
2889 2430
2890 in-ports { 2431 in-ports {
2891 #address-cell 2432 #address-cells = <1>;
2892 #size-cells = 2433 #size-cells = <0>;
2893 2434
2894 port@0 { 2435 port@0 {
2895 reg = 2436 reg = <0>;
2896 apss_ 2437 apss_funnel0_in0: endpoint {
2897 2438 remote-endpoint = <&etm0_out>;
2898 }; 2439 };
2899 }; 2440 };
2900 2441
2901 port@1 { 2442 port@1 {
2902 reg = 2443 reg = <1>;
2903 apss_ 2444 apss_funnel0_in1: endpoint {
2904 2445 remote-endpoint = <&etm1_out>;
2905 }; 2446 };
2906 }; 2447 };
2907 }; 2448 };
2908 2449
2909 out-ports { 2450 out-ports {
2910 port { 2451 port {
2911 apss_ 2452 apss_funnel0_out: endpoint {
2912 2453 remote-endpoint =
2913 2454 <&apss_merge_funnel_in0>;
2914 }; 2455 };
2915 }; 2456 };
2916 }; 2457 };
2917 }; 2458 };
2918 2459
2919 debug@3a10000 { 2460 debug@3a10000 {
2920 compatible = "arm,cor 2461 compatible = "arm,coresight-cpu-debug", "arm,primecell";
2921 reg = <0x3a10000 0x10 2462 reg = <0x3a10000 0x1000>;
2922 2463
2923 clocks = <&rpmcc RPM_ 2464 clocks = <&rpmcc RPM_QDSS_CLK>;
2924 clock-names = "apb_pc 2465 clock-names = "apb_pclk";
2925 2466
2926 cpu = <&CPU2>; 2467 cpu = <&CPU2>;
2927 }; 2468 };
2928 2469
2929 etm@3a40000 { 2470 etm@3a40000 {
2930 compatible = "arm,cor 2471 compatible = "arm,coresight-etm4x", "arm,primecell";
2931 reg = <0x3a40000 0x10 2472 reg = <0x3a40000 0x1000>;
2932 2473
2933 clocks = <&rpmcc RPM_ 2474 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2934 clock-names = "apb_pc 2475 clock-names = "apb_pclk", "atclk";
2935 2476
2936 cpu = <&CPU2>; 2477 cpu = <&CPU2>;
2937 2478
2938 out-ports { 2479 out-ports {
2939 port { 2480 port {
2940 etm2_ 2481 etm2_out: endpoint {
2941 2482 remote-endpoint =
2942 2483 <&apss_funnel1_in0>;
2943 }; 2484 };
2944 }; 2485 };
2945 }; 2486 };
2946 }; 2487 };
2947 2488
2948 debug@3b10000 { 2489 debug@3b10000 {
2949 compatible = "arm,cor 2490 compatible = "arm,coresight-cpu-debug", "arm,primecell";
2950 reg = <0x3b10000 0x10 2491 reg = <0x3b10000 0x1000>;
2951 2492
2952 clocks = <&rpmcc RPM_ 2493 clocks = <&rpmcc RPM_QDSS_CLK>;
2953 clock-names = "apb_pc 2494 clock-names = "apb_pclk";
2954 2495
2955 cpu = <&CPU3>; 2496 cpu = <&CPU3>;
2956 }; 2497 };
2957 2498
2958 etm@3b40000 { 2499 etm@3b40000 {
2959 compatible = "arm,cor 2500 compatible = "arm,coresight-etm4x", "arm,primecell";
2960 reg = <0x3b40000 0x10 2501 reg = <0x3b40000 0x1000>;
2961 2502
2962 clocks = <&rpmcc RPM_ 2503 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2963 clock-names = "apb_pc 2504 clock-names = "apb_pclk", "atclk";
2964 2505
2965 cpu = <&CPU3>; 2506 cpu = <&CPU3>;
2966 2507
2967 out-ports { 2508 out-ports {
2968 port { 2509 port {
2969 etm3_ 2510 etm3_out: endpoint {
2970 2511 remote-endpoint =
2971 2512 <&apss_funnel1_in1>;
2972 }; 2513 };
2973 }; 2514 };
2974 }; 2515 };
2975 }; 2516 };
2976 2517
2977 funnel@3bb0000 { /* APSS Funn 2518 funnel@3bb0000 { /* APSS Funnel 1 */
2978 compatible = "arm,cor 2519 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2979 reg = <0x3bb0000 0x10 2520 reg = <0x3bb0000 0x1000>;
2980 2521
2981 clocks = <&rpmcc RPM_ 2522 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2982 clock-names = "apb_pc 2523 clock-names = "apb_pclk", "atclk";
2983 2524
2984 in-ports { 2525 in-ports {
2985 #address-cell 2526 #address-cells = <1>;
2986 #size-cells = 2527 #size-cells = <0>;
2987 2528
2988 port@0 { 2529 port@0 {
2989 reg = 2530 reg = <0>;
2990 apss_ 2531 apss_funnel1_in0: endpoint {
2991 2532 remote-endpoint = <&etm2_out>;
2992 }; 2533 };
2993 }; 2534 };
2994 2535
2995 port@1 { 2536 port@1 {
2996 reg = 2537 reg = <1>;
2997 apss_ 2538 apss_funnel1_in1: endpoint {
2998 2539 remote-endpoint = <&etm3_out>;
2999 }; 2540 };
3000 }; 2541 };
3001 }; 2542 };
3002 2543
3003 out-ports { 2544 out-ports {
3004 port { 2545 port {
3005 apss_ 2546 apss_funnel1_out: endpoint {
3006 2547 remote-endpoint =
3007 2548 <&apss_merge_funnel_in1>;
3008 }; 2549 };
3009 }; 2550 };
3010 }; 2551 };
3011 }; 2552 };
3012 2553
3013 funnel@3bc0000 { 2554 funnel@3bc0000 {
3014 compatible = "arm,cor 2555 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3015 reg = <0x3bc0000 0x10 2556 reg = <0x3bc0000 0x1000>;
3016 2557
3017 clocks = <&rpmcc RPM_ 2558 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
3018 clock-names = "apb_pc 2559 clock-names = "apb_pclk", "atclk";
3019 2560
3020 in-ports { 2561 in-ports {
3021 #address-cell 2562 #address-cells = <1>;
3022 #size-cells = 2563 #size-cells = <0>;
3023 2564
3024 port@0 { 2565 port@0 {
3025 reg = 2566 reg = <0>;
3026 apss_ 2567 apss_merge_funnel_in0: endpoint {
3027 2568 remote-endpoint =
3028 2569 <&apss_funnel0_out>;
3029 }; 2570 };
3030 }; 2571 };
3031 2572
3032 port@1 { 2573 port@1 {
3033 reg = 2574 reg = <1>;
3034 apss_ 2575 apss_merge_funnel_in1: endpoint {
3035 2576 remote-endpoint =
3036 2577 <&apss_funnel1_out>;
3037 }; 2578 };
3038 }; 2579 };
3039 }; 2580 };
3040 2581
3041 out-ports { 2582 out-ports {
3042 port { 2583 port {
3043 apss_ 2584 apss_merge_funnel_out: endpoint {
3044 2585 remote-endpoint =
3045 2586 <&funnel1_in>;
3046 }; 2587 };
3047 }; 2588 };
3048 }; 2589 };
3049 }; 2590 };
3050 2591
3051 kryocc: clock-controller@6400 2592 kryocc: clock-controller@6400000 {
3052 compatible = "qcom,ms 2593 compatible = "qcom,msm8996-apcc";
3053 reg = <0x06400000 0x9 2594 reg = <0x06400000 0x90000>;
3054 2595
3055 clock-names = "xo", " !! 2596 clock-names = "xo";
3056 clocks = <&rpmcc RPM_ !! 2597 clocks = <&xo_board>;
3057 2598
3058 #clock-cells = <1>; 2599 #clock-cells = <1>;
3059 }; 2600 };
3060 2601
3061 usb3: usb@6af8800 { 2602 usb3: usb@6af8800 {
3062 compatible = "qcom,ms 2603 compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
3063 reg = <0x06af8800 0x4 2604 reg = <0x06af8800 0x400>;
3064 #address-cells = <1>; 2605 #address-cells = <1>;
3065 #size-cells = <1>; 2606 #size-cells = <1>;
3066 ranges; 2607 ranges;
3067 2608
3068 interrupts = <GIC_SPI 2609 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
3069 <GIC_SPI 2610 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
3070 interrupt-names = "hs 2611 interrupt-names = "hs_phy_irq", "ss_phy_irq";
3071 2612
3072 clocks = <&gcc GCC_SY 2613 clocks = <&gcc GCC_SYS_NOC_USB3_AXI_CLK>,
3073 <&gcc GCC_US !! 2614 <&gcc GCC_USB30_MASTER_CLK>,
3074 <&gcc GCC_AG !! 2615 <&gcc GCC_AGGRE2_USB3_AXI_CLK>,
3075 <&gcc GCC_US !! 2616 <&gcc GCC_USB30_MOCK_UTMI_CLK>,
3076 <&gcc GCC_US !! 2617 <&gcc GCC_USB30_SLEEP_CLK>,
3077 clock-names = "cfg_no !! 2618 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
3078 "core", <<
3079 "iface" <<
3080 "sleep" <<
3081 "mock_u <<
3082 2619
3083 assigned-clocks = <&g 2620 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
3084 <&g 2621 <&gcc GCC_USB30_MASTER_CLK>;
3085 assigned-clock-rates 2622 assigned-clock-rates = <19200000>, <120000000>;
3086 2623
3087 interconnects = <&a2n <<
3088 <&bim <<
3089 interconnect-names = <<
3090 <<
3091 power-domains = <&gcc 2624 power-domains = <&gcc USB30_GDSC>;
3092 status = "disabled"; 2625 status = "disabled";
3093 2626
3094 usb3_dwc3: usb@6a0000 !! 2627 usb3_dwc3: dwc3@6a00000 {
3095 compatible = 2628 compatible = "snps,dwc3";
3096 reg = <0x06a0 2629 reg = <0x06a00000 0xcc00>;
3097 interrupts = !! 2630 interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>;
3098 phys = <&hsus !! 2631 phys = <&hsusb_phy1>, <&ssusb_phy_0>;
3099 phy-names = " 2632 phy-names = "usb2-phy", "usb3-phy";
3100 snps,hird-thr <<
3101 snps,dis_u2_s 2633 snps,dis_u2_susphy_quirk;
3102 snps,dis_enbl 2634 snps,dis_enblslpm_quirk;
3103 snps,is-utmi- <<
3104 snps,parkmode <<
3105 tx-fifo-resiz <<
3106 }; 2635 };
3107 }; 2636 };
3108 2637
3109 usb3phy: phy@7410000 { 2638 usb3phy: phy@7410000 {
3110 compatible = "qcom,ms 2639 compatible = "qcom,msm8996-qmp-usb3-phy";
3111 reg = <0x07410000 0x1 !! 2640 reg = <0x07410000 0x1c4>;
>> 2641 #address-cells = <1>;
>> 2642 #size-cells = <1>;
>> 2643 ranges;
3112 2644
3113 clocks = <&gcc GCC_US 2645 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
3114 <&gcc GCC_US !! 2646 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
3115 <&gcc GCC_US !! 2647 <&gcc GCC_USB3_CLKREF_CLK>;
3116 <&gcc GCC_US !! 2648 clock-names = "aux", "cfg_ahb", "ref";
3117 clock-names = "aux", <<
3118 "ref", <<
3119 "cfg_ah <<
3120 "pipe"; <<
3121 clock-output-names = <<
3122 #clock-cells = <0>; <<
3123 #phy-cells = <0>; <<
3124 2649
3125 resets = <&gcc GCC_US 2650 resets = <&gcc GCC_USB3_PHY_BCR>,
3126 <&gcc GCC_US !! 2651 <&gcc GCC_USB3PHY_PHY_BCR>;
3127 reset-names = "phy", !! 2652 reset-names = "phy", "common";
3128 "phy_ph <<
3129 <<
3130 status = "disabled"; 2653 status = "disabled";
>> 2654
>> 2655 ssusb_phy_0: phy@7410200 {
>> 2656 reg = <0x07410200 0x200>,
>> 2657 <0x07410400 0x130>,
>> 2658 <0x07410600 0x1a8>;
>> 2659 #phy-cells = <0>;
>> 2660
>> 2661 #clock-cells = <1>;
>> 2662 clock-output-names = "usb3_phy_pipe_clk_src";
>> 2663 clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
>> 2664 clock-names = "pipe0";
>> 2665 };
3131 }; 2666 };
3132 2667
3133 hsusb_phy1: phy@7411000 { 2668 hsusb_phy1: phy@7411000 {
3134 compatible = "qcom,ms 2669 compatible = "qcom,msm8996-qusb2-phy";
3135 reg = <0x07411000 0x1 2670 reg = <0x07411000 0x180>;
3136 #phy-cells = <0>; 2671 #phy-cells = <0>;
3137 2672
3138 clocks = <&gcc GCC_US 2673 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
3139 <&gcc GCC_RX1 2674 <&gcc GCC_RX1_USB2_CLKREF_CLK>;
3140 clock-names = "cfg_ah 2675 clock-names = "cfg_ahb", "ref";
3141 2676
3142 resets = <&gcc GCC_QU 2677 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
3143 nvmem-cells = <&qusb2 2678 nvmem-cells = <&qusb2p_hstx_trim>;
3144 status = "disabled"; 2679 status = "disabled";
3145 }; 2680 };
3146 2681
3147 hsusb_phy2: phy@7412000 { 2682 hsusb_phy2: phy@7412000 {
3148 compatible = "qcom,ms 2683 compatible = "qcom,msm8996-qusb2-phy";
3149 reg = <0x07412000 0x1 2684 reg = <0x07412000 0x180>;
3150 #phy-cells = <0>; 2685 #phy-cells = <0>;
3151 2686
3152 clocks = <&gcc GCC_US 2687 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
3153 <&gcc GCC_RX2 2688 <&gcc GCC_RX2_USB2_CLKREF_CLK>;
3154 clock-names = "cfg_ah 2689 clock-names = "cfg_ahb", "ref";
3155 2690
3156 resets = <&gcc GCC_QU 2691 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
3157 nvmem-cells = <&qusb2 2692 nvmem-cells = <&qusb2s_hstx_trim>;
3158 status = "disabled"; 2693 status = "disabled";
3159 }; 2694 };
3160 2695
3161 sdhc1: mmc@7464900 { !! 2696 sdhc1: sdhci@7464900 {
3162 compatible = "qcom,ms !! 2697 compatible = "qcom,sdhci-msm-v4";
3163 reg = <0x07464900 0x1 2698 reg = <0x07464900 0x11c>, <0x07464000 0x800>;
3164 reg-names = "hc", "co !! 2699 reg-names = "hc_mem", "core_mem";
3165 2700
3166 interrupts = <GIC_SPI 2701 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
3167 <GIC_ 2702 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
3168 interrupt-names = "hc 2703 interrupt-names = "hc_irq", "pwr_irq";
3169 2704
3170 clock-names = "iface" 2705 clock-names = "iface", "core", "xo";
3171 clocks = <&gcc GCC_SD 2706 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
3172 <&gcc GCC_SDC 2707 <&gcc GCC_SDCC1_APPS_CLK>,
3173 <&rpmcc RPM_S !! 2708 <&xo_board>;
3174 resets = <&gcc GCC_SD <<
3175 2709
3176 pinctrl-names = "defa 2710 pinctrl-names = "default", "sleep";
3177 pinctrl-0 = <&sdc1_st 2711 pinctrl-0 = <&sdc1_state_on>;
3178 pinctrl-1 = <&sdc1_st 2712 pinctrl-1 = <&sdc1_state_off>;
3179 2713
3180 bus-width = <8>; 2714 bus-width = <8>;
3181 non-removable; 2715 non-removable;
3182 status = "disabled"; 2716 status = "disabled";
3183 }; 2717 };
3184 2718
3185 sdhc2: mmc@74a4900 { !! 2719 sdhc2: sdhci@74a4900 {
3186 compatible = "qcom,ms !! 2720 compatible = "qcom,sdhci-msm-v4";
3187 reg = <0x074a4900 0x3 2721 reg = <0x074a4900 0x314>, <0x074a4000 0x800>;
3188 reg-names = "hc", "co !! 2722 reg-names = "hc_mem", "core_mem";
3189 2723
3190 interrupts = <GIC_SPI 2724 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
3191 <GIC_SP 2725 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
3192 interrupt-names = "hc 2726 interrupt-names = "hc_irq", "pwr_irq";
3193 2727
3194 clock-names = "iface" 2728 clock-names = "iface", "core", "xo";
3195 clocks = <&gcc GCC_SD 2729 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
3196 <&gcc GCC_SDC 2730 <&gcc GCC_SDCC2_APPS_CLK>,
3197 <&rpmcc RPM_S !! 2731 <&xo_board>;
3198 resets = <&gcc GCC_SD <<
3199 2732
3200 pinctrl-names = "defa 2733 pinctrl-names = "default", "sleep";
3201 pinctrl-0 = <&sdc2_st 2734 pinctrl-0 = <&sdc2_state_on>;
3202 pinctrl-1 = <&sdc2_st 2735 pinctrl-1 = <&sdc2_state_off>;
3203 2736
3204 bus-width = <4>; 2737 bus-width = <4>;
3205 status = "disabled"; 2738 status = "disabled";
3206 }; 2739 };
3207 2740
3208 blsp1_dma: dma-controller@754 2741 blsp1_dma: dma-controller@7544000 {
3209 compatible = "qcom,ba 2742 compatible = "qcom,bam-v1.7.0";
3210 reg = <0x07544000 0x2 2743 reg = <0x07544000 0x2b000>;
3211 interrupts = <GIC_SPI 2744 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
3212 clocks = <&gcc GCC_BL 2745 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
3213 clock-names = "bam_cl 2746 clock-names = "bam_clk";
3214 qcom,controlled-remot 2747 qcom,controlled-remotely;
3215 #dma-cells = <1>; 2748 #dma-cells = <1>;
3216 qcom,ee = <0>; 2749 qcom,ee = <0>;
3217 }; 2750 };
3218 2751
3219 blsp1_uart2: serial@7570000 { 2752 blsp1_uart2: serial@7570000 {
3220 compatible = "qcom,ms 2753 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
3221 reg = <0x07570000 0x1 2754 reg = <0x07570000 0x1000>;
3222 interrupts = <GIC_SPI 2755 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
3223 clocks = <&gcc GCC_BL 2756 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
3224 <&gcc GCC_BL 2757 <&gcc GCC_BLSP1_AHB_CLK>;
3225 clock-names = "core", 2758 clock-names = "core", "iface";
3226 pinctrl-names = "defa 2759 pinctrl-names = "default", "sleep";
3227 pinctrl-0 = <&blsp1_u 2760 pinctrl-0 = <&blsp1_uart2_default>;
3228 pinctrl-1 = <&blsp1_u 2761 pinctrl-1 = <&blsp1_uart2_sleep>;
3229 dmas = <&blsp1_dma 2> 2762 dmas = <&blsp1_dma 2>, <&blsp1_dma 3>;
3230 dma-names = "tx", "rx 2763 dma-names = "tx", "rx";
3231 status = "disabled"; 2764 status = "disabled";
3232 }; 2765 };
3233 2766
3234 blsp1_spi1: spi@7575000 { 2767 blsp1_spi1: spi@7575000 {
3235 compatible = "qcom,sp 2768 compatible = "qcom,spi-qup-v2.2.1";
3236 reg = <0x07575000 0x6 2769 reg = <0x07575000 0x600>;
3237 interrupts = <GIC_SPI 2770 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
3238 clocks = <&gcc GCC_BL 2771 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
3239 <&gcc GCC_BL 2772 <&gcc GCC_BLSP1_AHB_CLK>;
3240 clock-names = "core", 2773 clock-names = "core", "iface";
3241 pinctrl-names = "defa 2774 pinctrl-names = "default", "sleep";
3242 pinctrl-0 = <&blsp1_s 2775 pinctrl-0 = <&blsp1_spi1_default>;
3243 pinctrl-1 = <&blsp1_s 2776 pinctrl-1 = <&blsp1_spi1_sleep>;
3244 dmas = <&blsp1_dma 12 2777 dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
3245 dma-names = "tx", "rx 2778 dma-names = "tx", "rx";
3246 #address-cells = <1>; 2779 #address-cells = <1>;
3247 #size-cells = <0>; 2780 #size-cells = <0>;
3248 status = "disabled"; 2781 status = "disabled";
3249 }; 2782 };
3250 2783
3251 blsp1_i2c3: i2c@7577000 { 2784 blsp1_i2c3: i2c@7577000 {
3252 compatible = "qcom,i2 2785 compatible = "qcom,i2c-qup-v2.2.1";
3253 reg = <0x07577000 0x1 2786 reg = <0x07577000 0x1000>;
3254 interrupts = <GIC_SPI 2787 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
3255 clocks = <&gcc GCC_BL !! 2788 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
3256 <&gcc GCC_BL !! 2789 <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
3257 clock-names = "core", !! 2790 clock-names = "iface", "core";
3258 pinctrl-names = "defa 2791 pinctrl-names = "default", "sleep";
3259 pinctrl-0 = <&blsp1_i 2792 pinctrl-0 = <&blsp1_i2c3_default>;
3260 pinctrl-1 = <&blsp1_i 2793 pinctrl-1 = <&blsp1_i2c3_sleep>;
3261 dmas = <&blsp1_dma 16 2794 dmas = <&blsp1_dma 16>, <&blsp1_dma 17>;
3262 dma-names = "tx", "rx 2795 dma-names = "tx", "rx";
3263 #address-cells = <1>; 2796 #address-cells = <1>;
3264 #size-cells = <0>; 2797 #size-cells = <0>;
3265 status = "disabled"; 2798 status = "disabled";
3266 }; 2799 };
3267 2800
3268 blsp1_i2c6: i2c@757a000 { <<
3269 compatible = "qcom,i2 <<
3270 reg = <0x757a000 0x10 <<
3271 interrupts = <GIC_SPI <<
3272 clocks = <&gcc GCC_BL <<
3273 <&gcc GCC_BL <<
3274 clock-names = "core", <<
3275 pinctrl-names = "defa <<
3276 pinctrl-0 = <&blsp1_i <<
3277 pinctrl-1 = <&blsp1_i <<
3278 dmas = <&blsp1_dma 22 <<
3279 dma-names = "tx", "rx <<
3280 #address-cells = <1>; <<
3281 #size-cells = <0>; <<
3282 status = "disabled"; <<
3283 }; <<
3284 <<
3285 blsp2_dma: dma-controller@758 2801 blsp2_dma: dma-controller@7584000 {
3286 compatible = "qcom,ba 2802 compatible = "qcom,bam-v1.7.0";
3287 reg = <0x07584000 0x2 2803 reg = <0x07584000 0x2b000>;
3288 interrupts = <GIC_SPI 2804 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
3289 clocks = <&gcc GCC_BL 2805 clocks = <&gcc GCC_BLSP2_AHB_CLK>;
3290 clock-names = "bam_cl 2806 clock-names = "bam_clk";
3291 qcom,controlled-remot 2807 qcom,controlled-remotely;
3292 #dma-cells = <1>; 2808 #dma-cells = <1>;
3293 qcom,ee = <0>; 2809 qcom,ee = <0>;
3294 }; 2810 };
3295 2811
3296 blsp2_uart2: serial@75b0000 { 2812 blsp2_uart2: serial@75b0000 {
3297 compatible = "qcom,ms 2813 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
3298 reg = <0x075b0000 0x1 2814 reg = <0x075b0000 0x1000>;
3299 interrupts = <GIC_SPI 2815 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
3300 clocks = <&gcc GCC_BL 2816 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
3301 <&gcc GCC_BL 2817 <&gcc GCC_BLSP2_AHB_CLK>;
3302 clock-names = "core", 2818 clock-names = "core", "iface";
3303 status = "disabled"; 2819 status = "disabled";
3304 }; 2820 };
3305 2821
3306 blsp2_uart3: serial@75b1000 { 2822 blsp2_uart3: serial@75b1000 {
3307 compatible = "qcom,ms 2823 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
3308 reg = <0x075b1000 0x1 2824 reg = <0x075b1000 0x1000>;
3309 interrupts = <GIC_SPI 2825 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
3310 clocks = <&gcc GCC_BL 2826 clocks = <&gcc GCC_BLSP2_UART3_APPS_CLK>,
3311 <&gcc GCC_BL 2827 <&gcc GCC_BLSP2_AHB_CLK>;
3312 clock-names = "core", 2828 clock-names = "core", "iface";
3313 status = "disabled"; 2829 status = "disabled";
3314 }; 2830 };
3315 2831
3316 blsp2_i2c1: i2c@75b5000 { 2832 blsp2_i2c1: i2c@75b5000 {
3317 compatible = "qcom,i2 2833 compatible = "qcom,i2c-qup-v2.2.1";
3318 reg = <0x075b5000 0x1 2834 reg = <0x075b5000 0x1000>;
3319 interrupts = <GIC_SPI 2835 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
3320 clocks = <&gcc GCC_BL !! 2836 clocks = <&gcc GCC_BLSP2_AHB_CLK>,
3321 <&gcc GCC_BL !! 2837 <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>;
3322 clock-names = "core", !! 2838 clock-names = "iface", "core";
3323 pinctrl-names = "defa 2839 pinctrl-names = "default", "sleep";
3324 pinctrl-0 = <&blsp2_i 2840 pinctrl-0 = <&blsp2_i2c1_default>;
3325 pinctrl-1 = <&blsp2_i 2841 pinctrl-1 = <&blsp2_i2c1_sleep>;
3326 dmas = <&blsp2_dma 12 2842 dmas = <&blsp2_dma 12>, <&blsp2_dma 13>;
3327 dma-names = "tx", "rx 2843 dma-names = "tx", "rx";
3328 #address-cells = <1>; 2844 #address-cells = <1>;
3329 #size-cells = <0>; 2845 #size-cells = <0>;
3330 status = "disabled"; 2846 status = "disabled";
3331 }; 2847 };
3332 2848
3333 blsp2_i2c2: i2c@75b6000 { 2849 blsp2_i2c2: i2c@75b6000 {
3334 compatible = "qcom,i2 2850 compatible = "qcom,i2c-qup-v2.2.1";
3335 reg = <0x075b6000 0x1 2851 reg = <0x075b6000 0x1000>;
3336 interrupts = <GIC_SPI 2852 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
3337 clocks = <&gcc GCC_BL !! 2853 clocks = <&gcc GCC_BLSP2_AHB_CLK>,
3338 <&gcc GCC_BL !! 2854 <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>;
3339 clock-names = "core", !! 2855 clock-names = "iface", "core";
3340 pinctrl-names = "defa 2856 pinctrl-names = "default", "sleep";
3341 pinctrl-0 = <&blsp2_i 2857 pinctrl-0 = <&blsp2_i2c2_default>;
3342 pinctrl-1 = <&blsp2_i 2858 pinctrl-1 = <&blsp2_i2c2_sleep>;
3343 dmas = <&blsp2_dma 14 2859 dmas = <&blsp2_dma 14>, <&blsp2_dma 15>;
3344 dma-names = "tx", "rx 2860 dma-names = "tx", "rx";
3345 #address-cells = <1>; 2861 #address-cells = <1>;
3346 #size-cells = <0>; 2862 #size-cells = <0>;
3347 status = "disabled"; 2863 status = "disabled";
3348 }; 2864 };
3349 2865
3350 blsp2_i2c3: i2c@75b7000 { 2866 blsp2_i2c3: i2c@75b7000 {
3351 compatible = "qcom,i2 2867 compatible = "qcom,i2c-qup-v2.2.1";
3352 reg = <0x075b7000 0x1 2868 reg = <0x075b7000 0x1000>;
3353 interrupts = <GIC_SPI 2869 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
3354 clocks = <&gcc GCC_BL !! 2870 clocks = <&gcc GCC_BLSP2_AHB_CLK>,
3355 <&gcc GCC_BL !! 2871 <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>;
3356 clock-names = "core", !! 2872 clock-names = "iface", "core";
3357 clock-frequency = <40 2873 clock-frequency = <400000>;
3358 pinctrl-names = "defa 2874 pinctrl-names = "default", "sleep";
3359 pinctrl-0 = <&blsp2_i 2875 pinctrl-0 = <&blsp2_i2c3_default>;
3360 pinctrl-1 = <&blsp2_i 2876 pinctrl-1 = <&blsp2_i2c3_sleep>;
3361 dmas = <&blsp2_dma 16 2877 dmas = <&blsp2_dma 16>, <&blsp2_dma 17>;
3362 dma-names = "tx", "rx 2878 dma-names = "tx", "rx";
3363 #address-cells = <1>; 2879 #address-cells = <1>;
3364 #size-cells = <0>; 2880 #size-cells = <0>;
3365 status = "disabled"; 2881 status = "disabled";
3366 }; 2882 };
3367 2883
3368 blsp2_i2c5: i2c@75b9000 { 2884 blsp2_i2c5: i2c@75b9000 {
3369 compatible = "qcom,i2 2885 compatible = "qcom,i2c-qup-v2.2.1";
3370 reg = <0x75b9000 0x10 2886 reg = <0x75b9000 0x1000>;
3371 interrupts = <GIC_SPI 2887 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
3372 clocks = <&gcc GCC_BL !! 2888 clocks = <&gcc GCC_BLSP2_AHB_CLK>,
3373 <&gcc GCC_BL !! 2889 <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>;
3374 clock-names = "core", !! 2890 clock-names = "iface", "core";
3375 pinctrl-names = "defa 2891 pinctrl-names = "default";
3376 pinctrl-0 = <&blsp2_i 2892 pinctrl-0 = <&blsp2_i2c5_default>;
3377 dmas = <&blsp2_dma 20 2893 dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
3378 dma-names = "tx", "rx 2894 dma-names = "tx", "rx";
3379 #address-cells = <1>; 2895 #address-cells = <1>;
3380 #size-cells = <0>; 2896 #size-cells = <0>;
3381 status = "disabled"; 2897 status = "disabled";
3382 }; 2898 };
3383 2899
3384 blsp2_i2c6: i2c@75ba000 { 2900 blsp2_i2c6: i2c@75ba000 {
3385 compatible = "qcom,i2 2901 compatible = "qcom,i2c-qup-v2.2.1";
3386 reg = <0x75ba000 0x10 2902 reg = <0x75ba000 0x1000>;
3387 interrupts = <GIC_SPI 2903 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
3388 clocks = <&gcc GCC_BL !! 2904 clocks = <&gcc GCC_BLSP2_AHB_CLK>,
3389 <&gcc GCC_BL !! 2905 <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>;
3390 clock-names = "core", !! 2906 clock-names = "iface", "core";
3391 pinctrl-names = "defa 2907 pinctrl-names = "default", "sleep";
3392 pinctrl-0 = <&blsp2_i 2908 pinctrl-0 = <&blsp2_i2c6_default>;
3393 pinctrl-1 = <&blsp2_i 2909 pinctrl-1 = <&blsp2_i2c6_sleep>;
3394 dmas = <&blsp2_dma 22 2910 dmas = <&blsp2_dma 22>, <&blsp2_dma 23>;
3395 dma-names = "tx", "rx 2911 dma-names = "tx", "rx";
3396 #address-cells = <1>; 2912 #address-cells = <1>;
3397 #size-cells = <0>; 2913 #size-cells = <0>;
3398 status = "disabled"; 2914 status = "disabled";
3399 }; 2915 };
3400 2916
3401 blsp2_spi6: spi@75ba000 { !! 2917 blsp2_spi6: spi@75ba000{
3402 compatible = "qcom,sp 2918 compatible = "qcom,spi-qup-v2.2.1";
3403 reg = <0x075ba000 0x6 2919 reg = <0x075ba000 0x600>;
3404 interrupts = <GIC_SPI 2920 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
3405 clocks = <&gcc GCC_BL 2921 clocks = <&gcc GCC_BLSP2_QUP6_SPI_APPS_CLK>,
3406 <&gcc GCC_BL 2922 <&gcc GCC_BLSP2_AHB_CLK>;
3407 clock-names = "core", 2923 clock-names = "core", "iface";
3408 pinctrl-names = "defa 2924 pinctrl-names = "default", "sleep";
3409 pinctrl-0 = <&blsp2_s 2925 pinctrl-0 = <&blsp2_spi6_default>;
3410 pinctrl-1 = <&blsp2_s 2926 pinctrl-1 = <&blsp2_spi6_sleep>;
3411 dmas = <&blsp2_dma 22 2927 dmas = <&blsp2_dma 22>, <&blsp2_dma 23>;
3412 dma-names = "tx", "rx 2928 dma-names = "tx", "rx";
3413 #address-cells = <1>; 2929 #address-cells = <1>;
3414 #size-cells = <0>; 2930 #size-cells = <0>;
3415 status = "disabled"; 2931 status = "disabled";
3416 }; 2932 };
3417 2933
3418 usb2: usb@76f8800 { 2934 usb2: usb@76f8800 {
3419 compatible = "qcom,ms 2935 compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
3420 reg = <0x076f8800 0x4 2936 reg = <0x076f8800 0x400>;
3421 #address-cells = <1>; 2937 #address-cells = <1>;
3422 #size-cells = <1>; 2938 #size-cells = <1>;
3423 ranges; 2939 ranges;
3424 2940
3425 interrupts = <GIC_SPI <<
3426 <GIC_SPI <<
3427 <GIC_SPI <<
3428 interrupt-names = "pw <<
3429 "qu <<
3430 "hs <<
3431 <<
3432 clocks = <&gcc GCC_PE 2941 clocks = <&gcc GCC_PERIPH_NOC_USB20_AHB_CLK>,
3433 <&gcc GCC_USB 2942 <&gcc GCC_USB20_MASTER_CLK>,
3434 <&gcc GCC_USB 2943 <&gcc GCC_USB20_MOCK_UTMI_CLK>,
3435 <&gcc GCC_USB 2944 <&gcc GCC_USB20_SLEEP_CLK>,
3436 <&gcc GCC_USB 2945 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
3437 clock-names = "cfg_no <<
3438 "core", <<
3439 "iface" <<
3440 "sleep" <<
3441 "mock_u <<
3442 2946
3443 assigned-clocks = <&g 2947 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
3444 <&g 2948 <&gcc GCC_USB20_MASTER_CLK>;
3445 assigned-clock-rates 2949 assigned-clock-rates = <19200000>, <60000000>;
3446 2950
3447 power-domains = <&gcc 2951 power-domains = <&gcc USB30_GDSC>;
3448 qcom,select-utmi-as-p 2952 qcom,select-utmi-as-pipe-clk;
3449 status = "disabled"; 2953 status = "disabled";
3450 2954
3451 usb2_dwc3: usb@760000 !! 2955 dwc3@7600000 {
3452 compatible = 2956 compatible = "snps,dwc3";
3453 reg = <0x0760 2957 reg = <0x07600000 0xcc00>;
3454 interrupts = !! 2958 interrupts = <0 138 IRQ_TYPE_LEVEL_HIGH>;
3455 phys = <&hsus 2959 phys = <&hsusb_phy2>;
3456 phy-names = " 2960 phy-names = "usb2-phy";
3457 maximum-speed 2961 maximum-speed = "high-speed";
3458 snps,dis_u2_s 2962 snps,dis_u2_susphy_quirk;
3459 snps,dis_enbl 2963 snps,dis_enblslpm_quirk;
3460 }; 2964 };
3461 }; 2965 };
3462 2966
3463 slimbam: dma-controller@91840 2967 slimbam: dma-controller@9184000 {
3464 compatible = "qcom,ba 2968 compatible = "qcom,bam-v1.7.0";
3465 qcom,controlled-remot 2969 qcom,controlled-remotely;
3466 reg = <0x09184000 0x3 2970 reg = <0x09184000 0x32000>;
3467 num-channels = <31>; !! 2971 num-channels = <31>;
3468 interrupts = <GIC_SPI !! 2972 interrupts = <0 164 IRQ_TYPE_LEVEL_HIGH>;
3469 #dma-cells = <1>; 2973 #dma-cells = <1>;
3470 qcom,ee = <1>; 2974 qcom,ee = <1>;
3471 qcom,num-ees = <2>; 2975 qcom,num-ees = <2>;
3472 }; 2976 };
3473 2977
3474 slim_msm: slim-ngd@91c0000 { !! 2978 slim_msm: slim@91c0000 {
3475 compatible = "qcom,sl 2979 compatible = "qcom,slim-ngd-v1.5.0";
3476 reg = <0x091c0000 0x2 !! 2980 reg = <0x091c0000 0x2C000>;
3477 interrupts = <GIC_SPI !! 2981 reg-names = "ctrl";
3478 dmas = <&slimbam 3>, !! 2982 interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>;
3479 dma-names = "rx", "tx !! 2983 dmas = <&slimbam 3>, <&slimbam 4>,
>> 2984 <&slimbam 5>, <&slimbam 6>;
>> 2985 dma-names = "rx", "tx", "tx2", "rx2";
3480 #address-cells = <1>; 2986 #address-cells = <1>;
3481 #size-cells = <0>; 2987 #size-cells = <0>;
>> 2988 ngd@1 {
>> 2989 reg = <1>;
>> 2990 #address-cells = <1>;
>> 2991 #size-cells = <1>;
3482 2992
3483 status = "disabled"; !! 2993 tasha_ifd: tas-ifd {
>> 2994 compatible = "slim217,1a0";
>> 2995 reg = <0 0>;
>> 2996 };
>> 2997
>> 2998 wcd9335: codec@1{
>> 2999 pinctrl-0 = <&cdc_reset_active &wcd_intr_default>;
>> 3000 pinctrl-names = "default";
>> 3001
>> 3002 compatible = "slim217,1a0";
>> 3003 reg = <1 0>;
>> 3004
>> 3005 interrupt-parent = <&tlmm>;
>> 3006 interrupts = <54 IRQ_TYPE_LEVEL_HIGH>,
>> 3007 <53 IRQ_TYPE_LEVEL_HIGH>;
>> 3008 interrupt-names = "intr1", "intr2";
>> 3009 interrupt-controller;
>> 3010 #interrupt-cells = <1>;
>> 3011 reset-gpios = <&tlmm 64 0>;
>> 3012
>> 3013 slim-ifc-dev = <&tasha_ifd>;
>> 3014
>> 3015 #sound-dai-cells = <1>;
>> 3016 };
>> 3017 };
3484 }; 3018 };
3485 3019
3486 adsp_pil: remoteproc@9300000 3020 adsp_pil: remoteproc@9300000 {
3487 compatible = "qcom,ms 3021 compatible = "qcom,msm8996-adsp-pil";
3488 reg = <0x09300000 0x8 3022 reg = <0x09300000 0x80000>;
3489 3023
3490 interrupts-extended = 3024 interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>,
3491 !! 3025 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
3492 !! 3026 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
3493 !! 3027 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
3494 !! 3028 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
3495 interrupt-names = "wd 3029 interrupt-names = "wdog", "fatal", "ready",
3496 "ha 3030 "handover", "stop-ack";
3497 3031
3498 clocks = <&rpmcc RPM_ !! 3032 clocks = <&xo_board>;
3499 clock-names = "xo"; 3033 clock-names = "xo";
3500 3034
3501 memory-region = <&ads !! 3035 memory-region = <&adsp_region>;
3502 3036
3503 qcom,smem-states = <& !! 3037 qcom,smem-states = <&smp2p_adsp_out 0>;
3504 qcom,smem-state-names 3038 qcom,smem-state-names = "stop";
3505 3039
3506 power-domains = <&rpm 3040 power-domains = <&rpmpd MSM8996_VDDCX>;
3507 power-domain-names = 3041 power-domain-names = "cx";
3508 3042
3509 status = "disabled"; 3043 status = "disabled";
3510 3044
3511 glink-edge { <<
3512 interrupts = <<
3513 label = "lpas <<
3514 qcom,remote-p <<
3515 mboxes = <&ap <<
3516 }; <<
3517 <<
3518 <<
3519 smd-edge { 3045 smd-edge {
3520 interrupts = 3046 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
3521 3047
3522 label = "lpas 3048 label = "lpass";
3523 mboxes = <&ap 3049 mboxes = <&apcs_glb 8>;
3524 qcom,smd-edge 3050 qcom,smd-edge = <1>;
3525 qcom,remote-p 3051 qcom,remote-pid = <2>;
3526 !! 3052 #address-cells = <1>;
>> 3053 #size-cells = <0>;
3527 apr { 3054 apr {
3528 power 3055 power-domains = <&gcc HLOS1_VOTE_LPASS_ADSP_GDSC>;
3529 compa 3056 compatible = "qcom,apr-v2";
3530 qcom, 3057 qcom,smd-channels = "apr_audio_svc";
3531 qcom, !! 3058 qcom,apr-domain = <APR_DOMAIN_ADSP>;
3532 #addr 3059 #address-cells = <1>;
3533 #size 3060 #size-cells = <0>;
3534 3061
3535 servi !! 3062 q6core {
3536 3063 reg = <APR_SVC_ADSP_CORE>;
3537 3064 compatible = "qcom,q6core";
3538 }; 3065 };
3539 3066
3540 q6afe !! 3067 q6afe: q6afe {
3541 3068 compatible = "qcom,q6afe";
3542 3069 reg = <APR_SVC_AFE>;
3543 3070 q6afedai: dais {
3544 3071 compatible = "qcom,q6afe-dais";
3545 3072 #address-cells = <1>;
3546 3073 #size-cells = <0>;
3547 3074 #sound-dai-cells = <1>;
3548 !! 3075 hdmi@1 {
3549 3076 reg = <1>;
3550 3077 };
3551 3078 };
3552 }; 3079 };
3553 3080
3554 q6asm !! 3081 q6asm: q6asm {
3555 3082 compatible = "qcom,q6asm";
3556 3083 reg = <APR_SVC_ASM>;
3557 3084 q6asmdai: dais {
3558 3085 compatible = "qcom,q6asm-dais";
3559 3086 #address-cells = <1>;
3560 3087 #size-cells = <0>;
3561 3088 #sound-dai-cells = <1>;
3562 3089 iommus = <&lpass_q6_smmu 1>;
3563 3090 };
3564 }; 3091 };
3565 3092
3566 q6adm !! 3093 q6adm: q6adm {
3567 3094 compatible = "qcom,q6adm";
3568 3095 reg = <APR_SVC_ADM>;
3569 3096 q6routing: routing {
3570 3097 compatible = "qcom,q6adm-routing";
3571 3098 #sound-dai-cells = <0>;
3572 3099 };
3573 }; 3100 };
3574 }; 3101 };
3575 3102
3576 fastrpc { <<
3577 compa <<
3578 qcom, <<
3579 label <<
3580 qcom, <<
3581 #addr <<
3582 #size <<
3583 <<
3584 cb@5 <<
3585 <<
3586 <<
3587 <<
3588 }; <<
3589 <<
3590 cb@6 <<
3591 <<
3592 <<
3593 <<
3594 }; <<
3595 <<
3596 cb@7 <<
3597 <<
3598 <<
3599 <<
3600 }; <<
3601 <<
3602 cb@8 <<
3603 <<
3604 <<
3605 <<
3606 }; <<
3607 <<
3608 cb@9 <<
3609 <<
3610 <<
3611 <<
3612 }; <<
3613 <<
3614 cb@10 <<
3615 <<
3616 <<
3617 <<
3618 }; <<
3619 <<
3620 cb@11 <<
3621 <<
3622 <<
3623 <<
3624 }; <<
3625 <<
3626 cb@12 <<
3627 <<
3628 <<
3629 <<
3630 }; <<
3631 }; <<
3632 }; 3103 };
3633 }; 3104 };
3634 3105
3635 apcs_glb: mailbox@9820000 { 3106 apcs_glb: mailbox@9820000 {
3636 compatible = "qcom,ms 3107 compatible = "qcom,msm8996-apcs-hmss-global";
3637 reg = <0x09820000 0x1 3108 reg = <0x09820000 0x1000>;
3638 3109
3639 #mbox-cells = <1>; 3110 #mbox-cells = <1>;
3640 #clock-cells = <0>; <<
3641 }; 3111 };
3642 3112
3643 timer@9840000 { 3113 timer@9840000 {
3644 #address-cells = <1>; 3114 #address-cells = <1>;
3645 #size-cells = <1>; 3115 #size-cells = <1>;
3646 ranges; 3116 ranges;
3647 compatible = "arm,arm 3117 compatible = "arm,armv7-timer-mem";
3648 reg = <0x09840000 0x1 3118 reg = <0x09840000 0x1000>;
3649 clock-frequency = <19 3119 clock-frequency = <19200000>;
3650 3120
3651 frame@9850000 { 3121 frame@9850000 {
3652 frame-number 3122 frame-number = <0>;
3653 interrupts = 3123 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
3654 3124 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
3655 reg = <0x0985 3125 reg = <0x09850000 0x1000>,
3656 <0x0986 3126 <0x09860000 0x1000>;
3657 }; 3127 };
3658 3128
3659 frame@9870000 { 3129 frame@9870000 {
3660 frame-number 3130 frame-number = <1>;
3661 interrupts = 3131 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
3662 reg = <0x0987 3132 reg = <0x09870000 0x1000>;
3663 status = "dis 3133 status = "disabled";
3664 }; 3134 };
3665 3135
3666 frame@9880000 { 3136 frame@9880000 {
3667 frame-number 3137 frame-number = <2>;
3668 interrupts = 3138 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
3669 reg = <0x0988 3139 reg = <0x09880000 0x1000>;
3670 status = "dis 3140 status = "disabled";
3671 }; 3141 };
3672 3142
3673 frame@9890000 { 3143 frame@9890000 {
3674 frame-number 3144 frame-number = <3>;
3675 interrupts = 3145 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
3676 reg = <0x0989 3146 reg = <0x09890000 0x1000>;
3677 status = "dis 3147 status = "disabled";
3678 }; 3148 };
3679 3149
3680 frame@98a0000 { 3150 frame@98a0000 {
3681 frame-number 3151 frame-number = <4>;
3682 interrupts = 3152 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
3683 reg = <0x098a 3153 reg = <0x098a0000 0x1000>;
3684 status = "dis 3154 status = "disabled";
3685 }; 3155 };
3686 3156
3687 frame@98b0000 { 3157 frame@98b0000 {
3688 frame-number 3158 frame-number = <5>;
3689 interrupts = 3159 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
3690 reg = <0x098b 3160 reg = <0x098b0000 0x1000>;
3691 status = "dis 3161 status = "disabled";
3692 }; 3162 };
3693 3163
3694 frame@98c0000 { 3164 frame@98c0000 {
3695 frame-number 3165 frame-number = <6>;
3696 interrupts = 3166 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
3697 reg = <0x098c 3167 reg = <0x098c0000 0x1000>;
3698 status = "dis 3168 status = "disabled";
3699 }; 3169 };
3700 }; 3170 };
3701 3171
3702 saw3: syscon@9a10000 { 3172 saw3: syscon@9a10000 {
3703 compatible = "syscon" 3173 compatible = "syscon";
3704 reg = <0x09a10000 0x1 3174 reg = <0x09a10000 0x1000>;
3705 }; 3175 };
3706 3176
3707 cbf: clock-controller@9a11000 <<
3708 compatible = "qcom,ms <<
3709 reg = <0x09a11000 0x1 <<
3710 clocks = <&rpmcc RPM_ <<
3711 #clock-cells = <0>; <<
3712 #interconnect-cells = <<
3713 }; <<
3714 <<
3715 intc: interrupt-controller@9b 3177 intc: interrupt-controller@9bc0000 {
3716 compatible = "qcom,ms 3178 compatible = "qcom,msm8996-gic-v3", "arm,gic-v3";
3717 #interrupt-cells = <3 3179 #interrupt-cells = <3>;
3718 interrupt-controller; 3180 interrupt-controller;
3719 #redistributor-region 3181 #redistributor-regions = <1>;
3720 redistributor-stride 3182 redistributor-stride = <0x0 0x40000>;
3721 reg = <0x09bc0000 0x1 3183 reg = <0x09bc0000 0x10000>,
3722 <0x09c00000 0x1 3184 <0x09c00000 0x100000>;
3723 interrupts = <GIC_PPI 3185 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
3724 }; 3186 };
3725 }; 3187 };
3726 3188
3727 sound: sound { 3189 sound: sound {
3728 }; 3190 };
3729 3191
3730 thermal-zones { 3192 thermal-zones {
3731 cpu0-thermal { 3193 cpu0-thermal {
3732 polling-delay-passive 3194 polling-delay-passive = <250>;
>> 3195 polling-delay = <1000>;
3733 3196
3734 thermal-sensors = <&t 3197 thermal-sensors = <&tsens0 3>;
3735 3198
3736 trips { 3199 trips {
3737 cpu0_alert0: 3200 cpu0_alert0: trip-point0 {
3738 tempe 3201 temperature = <75000>;
3739 hyste 3202 hysteresis = <2000>;
3740 type 3203 type = "passive";
3741 }; 3204 };
3742 3205
3743 cpu0_crit: cp !! 3206 cpu0_crit: cpu_crit {
3744 tempe 3207 temperature = <110000>;
3745 hyste 3208 hysteresis = <2000>;
3746 type 3209 type = "critical";
3747 }; 3210 };
3748 }; 3211 };
3749 }; 3212 };
3750 3213
3751 cpu1-thermal { 3214 cpu1-thermal {
3752 polling-delay-passive 3215 polling-delay-passive = <250>;
>> 3216 polling-delay = <1000>;
3753 3217
3754 thermal-sensors = <&t 3218 thermal-sensors = <&tsens0 5>;
3755 3219
3756 trips { 3220 trips {
3757 cpu1_alert0: 3221 cpu1_alert0: trip-point0 {
3758 tempe 3222 temperature = <75000>;
3759 hyste 3223 hysteresis = <2000>;
3760 type 3224 type = "passive";
3761 }; 3225 };
3762 3226
3763 cpu1_crit: cp !! 3227 cpu1_crit: cpu_crit {
3764 tempe 3228 temperature = <110000>;
3765 hyste 3229 hysteresis = <2000>;
3766 type 3230 type = "critical";
3767 }; 3231 };
3768 }; 3232 };
3769 }; 3233 };
3770 3234
3771 cpu2-thermal { 3235 cpu2-thermal {
3772 polling-delay-passive 3236 polling-delay-passive = <250>;
>> 3237 polling-delay = <1000>;
3773 3238
3774 thermal-sensors = <&t 3239 thermal-sensors = <&tsens0 8>;
3775 3240
3776 trips { 3241 trips {
3777 cpu2_alert0: 3242 cpu2_alert0: trip-point0 {
3778 tempe 3243 temperature = <75000>;
3779 hyste 3244 hysteresis = <2000>;
3780 type 3245 type = "passive";
3781 }; 3246 };
3782 3247
3783 cpu2_crit: cp !! 3248 cpu2_crit: cpu_crit {
3784 tempe 3249 temperature = <110000>;
3785 hyste 3250 hysteresis = <2000>;
3786 type 3251 type = "critical";
3787 }; 3252 };
3788 }; 3253 };
3789 }; 3254 };
3790 3255
3791 cpu3-thermal { 3256 cpu3-thermal {
3792 polling-delay-passive 3257 polling-delay-passive = <250>;
>> 3258 polling-delay = <1000>;
3793 3259
3794 thermal-sensors = <&t 3260 thermal-sensors = <&tsens0 10>;
3795 3261
3796 trips { 3262 trips {
3797 cpu3_alert0: 3263 cpu3_alert0: trip-point0 {
3798 tempe 3264 temperature = <75000>;
3799 hyste 3265 hysteresis = <2000>;
3800 type 3266 type = "passive";
3801 }; 3267 };
3802 3268
3803 cpu3_crit: cp !! 3269 cpu3_crit: cpu_crit {
3804 tempe 3270 temperature = <110000>;
3805 hyste 3271 hysteresis = <2000>;
3806 type 3272 type = "critical";
3807 }; 3273 };
3808 }; 3274 };
3809 }; 3275 };
3810 3276
3811 gpu-top-thermal { !! 3277 gpu-thermal-top {
3812 polling-delay-passive 3278 polling-delay-passive = <250>;
>> 3279 polling-delay = <1000>;
3813 3280
3814 thermal-sensors = <&t 3281 thermal-sensors = <&tsens1 6>;
3815 3282
3816 trips { 3283 trips {
3817 gpu1_alert0: 3284 gpu1_alert0: trip-point0 {
3818 tempe 3285 temperature = <90000>;
3819 hyste 3286 hysteresis = <2000>;
3820 type 3287 type = "passive";
3821 }; 3288 };
3822 }; 3289 };
3823 3290
3824 cooling-maps { 3291 cooling-maps {
3825 map0 { 3292 map0 {
3826 trip 3293 trip = <&gpu1_alert0>;
3827 cooli 3294 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3828 }; 3295 };
3829 }; 3296 };
3830 }; 3297 };
3831 3298
3832 gpu-bottom-thermal { !! 3299 gpu-thermal-bottom {
3833 polling-delay-passive 3300 polling-delay-passive = <250>;
>> 3301 polling-delay = <1000>;
3834 3302
3835 thermal-sensors = <&t 3303 thermal-sensors = <&tsens1 7>;
3836 3304
3837 trips { 3305 trips {
3838 gpu2_alert0: 3306 gpu2_alert0: trip-point0 {
3839 tempe 3307 temperature = <90000>;
3840 hyste 3308 hysteresis = <2000>;
3841 type 3309 type = "passive";
3842 }; 3310 };
3843 }; 3311 };
3844 3312
3845 cooling-maps { 3313 cooling-maps {
3846 map0 { 3314 map0 {
3847 trip 3315 trip = <&gpu2_alert0>;
3848 cooli 3316 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3849 }; 3317 };
3850 }; 3318 };
3851 }; 3319 };
3852 3320
3853 m4m-thermal { 3321 m4m-thermal {
3854 polling-delay-passive 3322 polling-delay-passive = <250>;
>> 3323 polling-delay = <1000>;
3855 3324
3856 thermal-sensors = <&t 3325 thermal-sensors = <&tsens0 1>;
3857 3326
3858 trips { 3327 trips {
3859 m4m_alert0: t 3328 m4m_alert0: trip-point0 {
3860 tempe 3329 temperature = <90000>;
3861 hyste 3330 hysteresis = <2000>;
3862 type 3331 type = "hot";
3863 }; 3332 };
3864 }; 3333 };
3865 }; 3334 };
3866 3335
3867 l3-or-venus-thermal { 3336 l3-or-venus-thermal {
3868 polling-delay-passive 3337 polling-delay-passive = <250>;
>> 3338 polling-delay = <1000>;
3869 3339
3870 thermal-sensors = <&t 3340 thermal-sensors = <&tsens0 2>;
3871 3341
3872 trips { 3342 trips {
3873 l3_or_venus_a 3343 l3_or_venus_alert0: trip-point0 {
3874 tempe 3344 temperature = <90000>;
3875 hyste 3345 hysteresis = <2000>;
3876 type 3346 type = "hot";
3877 }; 3347 };
3878 }; 3348 };
3879 }; 3349 };
3880 3350
3881 cluster0-l2-thermal { 3351 cluster0-l2-thermal {
3882 polling-delay-passive 3352 polling-delay-passive = <250>;
>> 3353 polling-delay = <1000>;
3883 3354
3884 thermal-sensors = <&t 3355 thermal-sensors = <&tsens0 7>;
3885 3356
3886 trips { 3357 trips {
3887 cluster0_l2_a 3358 cluster0_l2_alert0: trip-point0 {
3888 tempe 3359 temperature = <90000>;
3889 hyste 3360 hysteresis = <2000>;
3890 type 3361 type = "hot";
3891 }; 3362 };
3892 }; 3363 };
3893 }; 3364 };
3894 3365
3895 cluster1-l2-thermal { 3366 cluster1-l2-thermal {
3896 polling-delay-passive 3367 polling-delay-passive = <250>;
>> 3368 polling-delay = <1000>;
3897 3369
3898 thermal-sensors = <&t 3370 thermal-sensors = <&tsens0 12>;
3899 3371
3900 trips { 3372 trips {
3901 cluster1_l2_a 3373 cluster1_l2_alert0: trip-point0 {
3902 tempe 3374 temperature = <90000>;
3903 hyste 3375 hysteresis = <2000>;
3904 type 3376 type = "hot";
3905 }; 3377 };
3906 }; 3378 };
3907 }; 3379 };
3908 3380
3909 camera-thermal { 3381 camera-thermal {
3910 polling-delay-passive 3382 polling-delay-passive = <250>;
>> 3383 polling-delay = <1000>;
3911 3384
3912 thermal-sensors = <&t 3385 thermal-sensors = <&tsens1 1>;
3913 3386
3914 trips { 3387 trips {
3915 camera_alert0 3388 camera_alert0: trip-point0 {
3916 tempe 3389 temperature = <90000>;
3917 hyste 3390 hysteresis = <2000>;
3918 type 3391 type = "hot";
3919 }; 3392 };
3920 }; 3393 };
3921 }; 3394 };
3922 3395
3923 q6-dsp-thermal { 3396 q6-dsp-thermal {
3924 polling-delay-passive 3397 polling-delay-passive = <250>;
>> 3398 polling-delay = <1000>;
3925 3399
3926 thermal-sensors = <&t 3400 thermal-sensors = <&tsens1 2>;
3927 3401
3928 trips { 3402 trips {
3929 q6_dsp_alert0 3403 q6_dsp_alert0: trip-point0 {
3930 tempe 3404 temperature = <90000>;
3931 hyste 3405 hysteresis = <2000>;
3932 type 3406 type = "hot";
3933 }; 3407 };
3934 }; 3408 };
3935 }; 3409 };
3936 3410
3937 mem-thermal { 3411 mem-thermal {
3938 polling-delay-passive 3412 polling-delay-passive = <250>;
>> 3413 polling-delay = <1000>;
3939 3414
3940 thermal-sensors = <&t 3415 thermal-sensors = <&tsens1 3>;
3941 3416
3942 trips { 3417 trips {
3943 mem_alert0: t 3418 mem_alert0: trip-point0 {
3944 tempe 3419 temperature = <90000>;
3945 hyste 3420 hysteresis = <2000>;
3946 type 3421 type = "hot";
3947 }; 3422 };
3948 }; 3423 };
3949 }; 3424 };
3950 3425
3951 modemtx-thermal { 3426 modemtx-thermal {
3952 polling-delay-passive 3427 polling-delay-passive = <250>;
>> 3428 polling-delay = <1000>;
3953 3429
3954 thermal-sensors = <&t 3430 thermal-sensors = <&tsens1 4>;
3955 3431
3956 trips { 3432 trips {
3957 modemtx_alert 3433 modemtx_alert0: trip-point0 {
3958 tempe 3434 temperature = <90000>;
3959 hyste 3435 hysteresis = <2000>;
3960 type 3436 type = "hot";
3961 }; 3437 };
3962 }; 3438 };
3963 }; 3439 };
3964 }; 3440 };
3965 3441
3966 timer { 3442 timer {
3967 compatible = "arm,armv8-timer 3443 compatible = "arm,armv8-timer";
3968 interrupts = <GIC_PPI 13 IRQ_ 3444 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
3969 <GIC_PPI 14 IRQ_ 3445 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
3970 <GIC_PPI 11 IRQ_ 3446 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
3971 <GIC_PPI 10 IRQ_ 3447 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
3972 }; 3448 };
3973 }; 3449 };
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