1 // SPDX-License-Identifier: GPL-2.0-only 1 // SPDX-License-Identifier: GPL-2.0-only
2 /* !! 2 /* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
3 * Copyright (c) 2014-2015, The Linux Foundati <<
4 */ 3 */
5 4
6 #include <dt-bindings/interrupt-controller/arm 5 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,gcc-msm8996.h 6 #include <dt-bindings/clock/qcom,gcc-msm8996.h>
8 #include <dt-bindings/clock/qcom,mmcc-msm8996. 7 #include <dt-bindings/clock/qcom,mmcc-msm8996.h>
9 #include <dt-bindings/clock/qcom,rpmcc.h> 8 #include <dt-bindings/clock/qcom,rpmcc.h>
10 #include <dt-bindings/interconnect/qcom,msm899 <<
11 #include <dt-bindings/interconnect/qcom,msm899 <<
12 #include <dt-bindings/firmware/qcom,scm.h> <<
13 #include <dt-bindings/gpio/gpio.h> <<
14 #include <dt-bindings/power/qcom-rpmpd.h> 9 #include <dt-bindings/power/qcom-rpmpd.h>
15 #include <dt-bindings/soc/qcom,apr.h> 10 #include <dt-bindings/soc/qcom,apr.h>
16 #include <dt-bindings/thermal/thermal.h> 11 #include <dt-bindings/thermal/thermal.h>
17 12
18 / { 13 / {
19 interrupt-parent = <&intc>; 14 interrupt-parent = <&intc>;
20 15
21 #address-cells = <2>; 16 #address-cells = <2>;
22 #size-cells = <2>; 17 #size-cells = <2>;
23 18
24 chosen { }; 19 chosen { };
25 20
26 clocks { 21 clocks {
27 xo_board: xo-board { 22 xo_board: xo-board {
28 compatible = "fixed-cl 23 compatible = "fixed-clock";
29 #clock-cells = <0>; 24 #clock-cells = <0>;
30 clock-frequency = <192 25 clock-frequency = <19200000>;
31 clock-output-names = " 26 clock-output-names = "xo_board";
32 }; 27 };
33 28
34 sleep_clk: sleep-clk { 29 sleep_clk: sleep-clk {
35 compatible = "fixed-cl 30 compatible = "fixed-clock";
36 #clock-cells = <0>; 31 #clock-cells = <0>;
37 clock-frequency = <327 32 clock-frequency = <32764>;
38 clock-output-names = " 33 clock-output-names = "sleep_clk";
39 }; 34 };
40 }; 35 };
41 36
42 cpus { 37 cpus {
43 #address-cells = <2>; 38 #address-cells = <2>;
44 #size-cells = <0>; 39 #size-cells = <0>;
45 40
46 CPU0: cpu@0 { 41 CPU0: cpu@0 {
47 device_type = "cpu"; 42 device_type = "cpu";
48 compatible = "qcom,kry 43 compatible = "qcom,kryo";
49 reg = <0x0 0x0>; 44 reg = <0x0 0x0>;
50 enable-method = "psci" 45 enable-method = "psci";
51 cpu-idle-states = <&CP 46 cpu-idle-states = <&CPU_SLEEP_0>;
52 capacity-dmips-mhz = < 47 capacity-dmips-mhz = <1024>;
53 clocks = <&kryocc 0>; 48 clocks = <&kryocc 0>;
54 interconnects = <&cbf <<
55 operating-points-v2 = 49 operating-points-v2 = <&cluster0_opp>;
56 #cooling-cells = <2>; 50 #cooling-cells = <2>;
57 next-level-cache = <&L 51 next-level-cache = <&L2_0>;
58 L2_0: l2-cache { 52 L2_0: l2-cache {
59 compatible = " !! 53 compatible = "cache";
60 cache-level = !! 54 cache-level = <2>;
61 cache-unified; <<
62 }; 55 };
63 }; 56 };
64 57
65 CPU1: cpu@1 { 58 CPU1: cpu@1 {
66 device_type = "cpu"; 59 device_type = "cpu";
67 compatible = "qcom,kry 60 compatible = "qcom,kryo";
68 reg = <0x0 0x1>; 61 reg = <0x0 0x1>;
69 enable-method = "psci" 62 enable-method = "psci";
70 cpu-idle-states = <&CP 63 cpu-idle-states = <&CPU_SLEEP_0>;
71 capacity-dmips-mhz = < 64 capacity-dmips-mhz = <1024>;
72 clocks = <&kryocc 0>; 65 clocks = <&kryocc 0>;
73 interconnects = <&cbf <<
74 operating-points-v2 = 66 operating-points-v2 = <&cluster0_opp>;
75 #cooling-cells = <2>; 67 #cooling-cells = <2>;
76 next-level-cache = <&L 68 next-level-cache = <&L2_0>;
77 }; 69 };
78 70
79 CPU2: cpu@100 { 71 CPU2: cpu@100 {
80 device_type = "cpu"; 72 device_type = "cpu";
81 compatible = "qcom,kry 73 compatible = "qcom,kryo";
82 reg = <0x0 0x100>; 74 reg = <0x0 0x100>;
83 enable-method = "psci" 75 enable-method = "psci";
84 cpu-idle-states = <&CP 76 cpu-idle-states = <&CPU_SLEEP_0>;
85 capacity-dmips-mhz = < 77 capacity-dmips-mhz = <1024>;
86 clocks = <&kryocc 1>; 78 clocks = <&kryocc 1>;
87 interconnects = <&cbf <<
88 operating-points-v2 = 79 operating-points-v2 = <&cluster1_opp>;
89 #cooling-cells = <2>; 80 #cooling-cells = <2>;
90 next-level-cache = <&L 81 next-level-cache = <&L2_1>;
91 L2_1: l2-cache { 82 L2_1: l2-cache {
92 compatible = " !! 83 compatible = "cache";
93 cache-level = !! 84 cache-level = <2>;
94 cache-unified; <<
95 }; 85 };
96 }; 86 };
97 87
98 CPU3: cpu@101 { 88 CPU3: cpu@101 {
99 device_type = "cpu"; 89 device_type = "cpu";
100 compatible = "qcom,kry 90 compatible = "qcom,kryo";
101 reg = <0x0 0x101>; 91 reg = <0x0 0x101>;
102 enable-method = "psci" 92 enable-method = "psci";
103 cpu-idle-states = <&CP 93 cpu-idle-states = <&CPU_SLEEP_0>;
104 capacity-dmips-mhz = < 94 capacity-dmips-mhz = <1024>;
105 clocks = <&kryocc 1>; 95 clocks = <&kryocc 1>;
106 interconnects = <&cbf <<
107 operating-points-v2 = 96 operating-points-v2 = <&cluster1_opp>;
108 #cooling-cells = <2>; 97 #cooling-cells = <2>;
109 next-level-cache = <&L 98 next-level-cache = <&L2_1>;
110 }; 99 };
111 100
112 cpu-map { 101 cpu-map {
113 cluster0 { 102 cluster0 {
114 core0 { 103 core0 {
115 cpu = 104 cpu = <&CPU0>;
116 }; 105 };
117 106
118 core1 { 107 core1 {
119 cpu = 108 cpu = <&CPU1>;
120 }; 109 };
121 }; 110 };
122 111
123 cluster1 { 112 cluster1 {
124 core0 { 113 core0 {
125 cpu = 114 cpu = <&CPU2>;
126 }; 115 };
127 116
128 core1 { 117 core1 {
129 cpu = 118 cpu = <&CPU3>;
130 }; 119 };
131 }; 120 };
132 }; 121 };
133 122
134 idle-states { 123 idle-states {
135 entry-method = "psci"; 124 entry-method = "psci";
136 125
137 CPU_SLEEP_0: cpu-sleep 126 CPU_SLEEP_0: cpu-sleep-0 {
138 compatible = " 127 compatible = "arm,idle-state";
139 idle-state-nam 128 idle-state-name = "standalone-power-collapse";
140 arm,psci-suspe 129 arm,psci-suspend-param = <0x00000004>;
141 entry-latency- 130 entry-latency-us = <130>;
142 exit-latency-u 131 exit-latency-us = <80>;
143 min-residency- 132 min-residency-us = <300>;
144 }; 133 };
145 }; 134 };
146 }; 135 };
147 136
148 cluster0_opp: opp-table-cluster0 { 137 cluster0_opp: opp-table-cluster0 {
149 compatible = "operating-points 138 compatible = "operating-points-v2-kryo-cpu";
150 nvmem-cells = <&speedbin_efuse 139 nvmem-cells = <&speedbin_efuse>;
151 opp-shared; 140 opp-shared;
152 141
153 /* Nominal fmax for now */ 142 /* Nominal fmax for now */
154 opp-307200000 { 143 opp-307200000 {
155 opp-hz = /bits/ 64 <30 144 opp-hz = /bits/ 64 <307200000>;
156 opp-supported-hw = <0x !! 145 opp-supported-hw = <0x77>;
157 clock-latency-ns = <20 146 clock-latency-ns = <200000>;
158 opp-peak-kBps = <30720 <<
159 }; 147 };
160 opp-422400000 { 148 opp-422400000 {
161 opp-hz = /bits/ 64 <42 149 opp-hz = /bits/ 64 <422400000>;
162 opp-supported-hw = <0x !! 150 opp-supported-hw = <0x77>;
163 clock-latency-ns = <20 151 clock-latency-ns = <200000>;
164 opp-peak-kBps = <30720 <<
165 }; 152 };
166 opp-480000000 { 153 opp-480000000 {
167 opp-hz = /bits/ 64 <48 154 opp-hz = /bits/ 64 <480000000>;
168 opp-supported-hw = <0x !! 155 opp-supported-hw = <0x77>;
169 clock-latency-ns = <20 156 clock-latency-ns = <200000>;
170 opp-peak-kBps = <30720 <<
171 }; 157 };
172 opp-556800000 { 158 opp-556800000 {
173 opp-hz = /bits/ 64 <55 159 opp-hz = /bits/ 64 <556800000>;
174 opp-supported-hw = <0x !! 160 opp-supported-hw = <0x77>;
175 clock-latency-ns = <20 161 clock-latency-ns = <200000>;
176 opp-peak-kBps = <30720 <<
177 }; 162 };
178 opp-652800000 { 163 opp-652800000 {
179 opp-hz = /bits/ 64 <65 164 opp-hz = /bits/ 64 <652800000>;
180 opp-supported-hw = <0x !! 165 opp-supported-hw = <0x77>;
181 clock-latency-ns = <20 166 clock-latency-ns = <200000>;
182 opp-peak-kBps = <38400 <<
183 }; 167 };
184 opp-729600000 { 168 opp-729600000 {
185 opp-hz = /bits/ 64 <72 169 opp-hz = /bits/ 64 <729600000>;
186 opp-supported-hw = <0x !! 170 opp-supported-hw = <0x77>;
187 clock-latency-ns = <20 171 clock-latency-ns = <200000>;
188 opp-peak-kBps = <46080 <<
189 }; 172 };
190 opp-844800000 { 173 opp-844800000 {
191 opp-hz = /bits/ 64 <84 174 opp-hz = /bits/ 64 <844800000>;
192 opp-supported-hw = <0x !! 175 opp-supported-hw = <0x77>;
193 clock-latency-ns = <20 176 clock-latency-ns = <200000>;
194 opp-peak-kBps = <53760 <<
195 }; 177 };
196 opp-960000000 { 178 opp-960000000 {
197 opp-hz = /bits/ 64 <96 179 opp-hz = /bits/ 64 <960000000>;
198 opp-supported-hw = <0x !! 180 opp-supported-hw = <0x77>;
199 clock-latency-ns = <20 181 clock-latency-ns = <200000>;
200 opp-peak-kBps = <67200 <<
201 }; 182 };
202 opp-1036800000 { 183 opp-1036800000 {
203 opp-hz = /bits/ 64 <10 184 opp-hz = /bits/ 64 <1036800000>;
204 opp-supported-hw = <0x !! 185 opp-supported-hw = <0x77>;
205 clock-latency-ns = <20 186 clock-latency-ns = <200000>;
206 opp-peak-kBps = <67200 <<
207 }; 187 };
208 opp-1113600000 { 188 opp-1113600000 {
209 opp-hz = /bits/ 64 <11 189 opp-hz = /bits/ 64 <1113600000>;
210 opp-supported-hw = <0x !! 190 opp-supported-hw = <0x77>;
211 clock-latency-ns = <20 191 clock-latency-ns = <200000>;
212 opp-peak-kBps = <82560 <<
213 }; 192 };
214 opp-1190400000 { 193 opp-1190400000 {
215 opp-hz = /bits/ 64 <11 194 opp-hz = /bits/ 64 <1190400000>;
216 opp-supported-hw = <0x !! 195 opp-supported-hw = <0x77>;
217 clock-latency-ns = <20 196 clock-latency-ns = <200000>;
218 opp-peak-kBps = <82560 <<
219 }; 197 };
220 opp-1228800000 { 198 opp-1228800000 {
221 opp-hz = /bits/ 64 <12 199 opp-hz = /bits/ 64 <1228800000>;
222 opp-supported-hw = <0x !! 200 opp-supported-hw = <0x77>;
223 clock-latency-ns = <20 201 clock-latency-ns = <200000>;
224 opp-peak-kBps = <90240 <<
225 }; 202 };
226 opp-1324800000 { 203 opp-1324800000 {
227 opp-hz = /bits/ 64 <13 204 opp-hz = /bits/ 64 <1324800000>;
228 opp-supported-hw = <0x !! 205 opp-supported-hw = <0x77>;
229 clock-latency-ns = <20 206 clock-latency-ns = <200000>;
230 opp-peak-kBps = <10560 <<
231 }; <<
232 opp-1363200000 { <<
233 opp-hz = /bits/ 64 <13 <<
234 opp-supported-hw = <0x <<
235 clock-latency-ns = <20 <<
236 opp-peak-kBps = <11328 <<
237 }; 207 };
238 opp-1401600000 { 208 opp-1401600000 {
239 opp-hz = /bits/ 64 <14 209 opp-hz = /bits/ 64 <1401600000>;
240 opp-supported-hw = <0x !! 210 opp-supported-hw = <0x77>;
241 clock-latency-ns = <20 211 clock-latency-ns = <200000>;
242 opp-peak-kBps = <11328 <<
243 }; 212 };
244 opp-1478400000 { 213 opp-1478400000 {
245 opp-hz = /bits/ 64 <14 214 opp-hz = /bits/ 64 <1478400000>;
246 opp-supported-hw = <0x !! 215 opp-supported-hw = <0x77>;
247 clock-latency-ns = <20 <<
248 opp-peak-kBps = <11904 <<
249 }; <<
250 opp-1497600000 { <<
251 opp-hz = /bits/ 64 <14 <<
252 opp-supported-hw = <0x <<
253 clock-latency-ns = <20 216 clock-latency-ns = <200000>;
254 opp-peak-kBps = <13056 <<
255 }; 217 };
256 opp-1593600000 { 218 opp-1593600000 {
257 opp-hz = /bits/ 64 <15 219 opp-hz = /bits/ 64 <1593600000>;
258 opp-supported-hw = <0x !! 220 opp-supported-hw = <0x77>;
259 clock-latency-ns = <20 221 clock-latency-ns = <200000>;
260 opp-peak-kBps = <13824 <<
261 }; 222 };
262 }; 223 };
263 224
264 cluster1_opp: opp-table-cluster1 { 225 cluster1_opp: opp-table-cluster1 {
265 compatible = "operating-points 226 compatible = "operating-points-v2-kryo-cpu";
266 nvmem-cells = <&speedbin_efuse 227 nvmem-cells = <&speedbin_efuse>;
267 opp-shared; 228 opp-shared;
268 229
269 /* Nominal fmax for now */ 230 /* Nominal fmax for now */
270 opp-307200000 { 231 opp-307200000 {
271 opp-hz = /bits/ 64 <30 232 opp-hz = /bits/ 64 <307200000>;
272 opp-supported-hw = <0x !! 233 opp-supported-hw = <0x77>;
273 clock-latency-ns = <20 234 clock-latency-ns = <200000>;
274 opp-peak-kBps = <30720 <<
275 }; 235 };
276 opp-403200000 { 236 opp-403200000 {
277 opp-hz = /bits/ 64 <40 237 opp-hz = /bits/ 64 <403200000>;
278 opp-supported-hw = <0x !! 238 opp-supported-hw = <0x77>;
279 clock-latency-ns = <20 239 clock-latency-ns = <200000>;
280 opp-peak-kBps = <30720 <<
281 }; 240 };
282 opp-480000000 { 241 opp-480000000 {
283 opp-hz = /bits/ 64 <48 242 opp-hz = /bits/ 64 <480000000>;
284 opp-supported-hw = <0x !! 243 opp-supported-hw = <0x77>;
285 clock-latency-ns = <20 244 clock-latency-ns = <200000>;
286 opp-peak-kBps = <30720 <<
287 }; 245 };
288 opp-556800000 { 246 opp-556800000 {
289 opp-hz = /bits/ 64 <55 247 opp-hz = /bits/ 64 <556800000>;
290 opp-supported-hw = <0x !! 248 opp-supported-hw = <0x77>;
291 clock-latency-ns = <20 249 clock-latency-ns = <200000>;
292 opp-peak-kBps = <30720 <<
293 }; 250 };
294 opp-652800000 { 251 opp-652800000 {
295 opp-hz = /bits/ 64 <65 252 opp-hz = /bits/ 64 <652800000>;
296 opp-supported-hw = <0x !! 253 opp-supported-hw = <0x77>;
297 clock-latency-ns = <20 254 clock-latency-ns = <200000>;
298 opp-peak-kBps = <30720 <<
299 }; 255 };
300 opp-729600000 { 256 opp-729600000 {
301 opp-hz = /bits/ 64 <72 257 opp-hz = /bits/ 64 <729600000>;
302 opp-supported-hw = <0x !! 258 opp-supported-hw = <0x77>;
303 clock-latency-ns = <20 259 clock-latency-ns = <200000>;
304 opp-peak-kBps = <30720 <<
305 }; 260 };
306 opp-806400000 { 261 opp-806400000 {
307 opp-hz = /bits/ 64 <80 262 opp-hz = /bits/ 64 <806400000>;
308 opp-supported-hw = <0x !! 263 opp-supported-hw = <0x77>;
309 clock-latency-ns = <20 264 clock-latency-ns = <200000>;
310 opp-peak-kBps = <38400 <<
311 }; 265 };
312 opp-883200000 { 266 opp-883200000 {
313 opp-hz = /bits/ 64 <88 267 opp-hz = /bits/ 64 <883200000>;
314 opp-supported-hw = <0x !! 268 opp-supported-hw = <0x77>;
315 clock-latency-ns = <20 269 clock-latency-ns = <200000>;
316 opp-peak-kBps = <46080 <<
317 }; 270 };
318 opp-940800000 { 271 opp-940800000 {
319 opp-hz = /bits/ 64 <94 272 opp-hz = /bits/ 64 <940800000>;
320 opp-supported-hw = <0x !! 273 opp-supported-hw = <0x77>;
321 clock-latency-ns = <20 274 clock-latency-ns = <200000>;
322 opp-peak-kBps = <53760 <<
323 }; 275 };
324 opp-1036800000 { 276 opp-1036800000 {
325 opp-hz = /bits/ 64 <10 277 opp-hz = /bits/ 64 <1036800000>;
326 opp-supported-hw = <0x !! 278 opp-supported-hw = <0x77>;
327 clock-latency-ns = <20 279 clock-latency-ns = <200000>;
328 opp-peak-kBps = <59520 <<
329 }; 280 };
330 opp-1113600000 { 281 opp-1113600000 {
331 opp-hz = /bits/ 64 <11 282 opp-hz = /bits/ 64 <1113600000>;
332 opp-supported-hw = <0x !! 283 opp-supported-hw = <0x77>;
333 clock-latency-ns = <20 284 clock-latency-ns = <200000>;
334 opp-peak-kBps = <67200 <<
335 }; 285 };
336 opp-1190400000 { 286 opp-1190400000 {
337 opp-hz = /bits/ 64 <11 287 opp-hz = /bits/ 64 <1190400000>;
338 opp-supported-hw = <0x !! 288 opp-supported-hw = <0x77>;
339 clock-latency-ns = <20 289 clock-latency-ns = <200000>;
340 opp-peak-kBps = <67200 <<
341 }; 290 };
342 opp-1248000000 { 291 opp-1248000000 {
343 opp-hz = /bits/ 64 <12 292 opp-hz = /bits/ 64 <1248000000>;
344 opp-supported-hw = <0x !! 293 opp-supported-hw = <0x77>;
345 clock-latency-ns = <20 294 clock-latency-ns = <200000>;
346 opp-peak-kBps = <74880 <<
347 }; 295 };
348 opp-1324800000 { 296 opp-1324800000 {
349 opp-hz = /bits/ 64 <13 297 opp-hz = /bits/ 64 <1324800000>;
350 opp-supported-hw = <0x !! 298 opp-supported-hw = <0x77>;
351 clock-latency-ns = <20 299 clock-latency-ns = <200000>;
352 opp-peak-kBps = <82560 <<
353 }; 300 };
354 opp-1401600000 { 301 opp-1401600000 {
355 opp-hz = /bits/ 64 <14 302 opp-hz = /bits/ 64 <1401600000>;
356 opp-supported-hw = <0x !! 303 opp-supported-hw = <0x77>;
357 clock-latency-ns = <20 304 clock-latency-ns = <200000>;
358 opp-peak-kBps = <90240 <<
359 }; 305 };
360 opp-1478400000 { 306 opp-1478400000 {
361 opp-hz = /bits/ 64 <14 307 opp-hz = /bits/ 64 <1478400000>;
362 opp-supported-hw = <0x !! 308 opp-supported-hw = <0x77>;
363 clock-latency-ns = <20 309 clock-latency-ns = <200000>;
364 opp-peak-kBps = <97920 <<
365 }; 310 };
366 opp-1555200000 { 311 opp-1555200000 {
367 opp-hz = /bits/ 64 <15 312 opp-hz = /bits/ 64 <1555200000>;
368 opp-supported-hw = <0x !! 313 opp-supported-hw = <0x77>;
369 clock-latency-ns = <20 314 clock-latency-ns = <200000>;
370 opp-peak-kBps = <10560 <<
371 }; 315 };
372 opp-1632000000 { 316 opp-1632000000 {
373 opp-hz = /bits/ 64 <16 317 opp-hz = /bits/ 64 <1632000000>;
374 opp-supported-hw = <0x !! 318 opp-supported-hw = <0x77>;
375 clock-latency-ns = <20 319 clock-latency-ns = <200000>;
376 opp-peak-kBps = <11904 <<
377 }; 320 };
378 opp-1708800000 { 321 opp-1708800000 {
379 opp-hz = /bits/ 64 <17 322 opp-hz = /bits/ 64 <1708800000>;
380 opp-supported-hw = <0x !! 323 opp-supported-hw = <0x77>;
381 clock-latency-ns = <20 324 clock-latency-ns = <200000>;
382 opp-peak-kBps = <12288 <<
383 }; 325 };
384 opp-1785600000 { 326 opp-1785600000 {
385 opp-hz = /bits/ 64 <17 327 opp-hz = /bits/ 64 <1785600000>;
386 opp-supported-hw = <0x !! 328 opp-supported-hw = <0x77>;
387 clock-latency-ns = <20 <<
388 opp-peak-kBps = <13056 <<
389 }; <<
390 opp-1804800000 { <<
391 opp-hz = /bits/ 64 <18 <<
392 opp-supported-hw = <0x <<
393 clock-latency-ns = <20 329 clock-latency-ns = <200000>;
394 opp-peak-kBps = <13056 <<
395 }; 330 };
396 opp-1824000000 { 331 opp-1824000000 {
397 opp-hz = /bits/ 64 <18 332 opp-hz = /bits/ 64 <1824000000>;
398 opp-supported-hw = <0x !! 333 opp-supported-hw = <0x77>;
399 clock-latency-ns = <20 334 clock-latency-ns = <200000>;
400 opp-peak-kBps = <13824 <<
401 }; <<
402 opp-1900800000 { <<
403 opp-hz = /bits/ 64 <19 <<
404 opp-supported-hw = <0x <<
405 clock-latency-ns = <20 <<
406 opp-peak-kBps = <13056 <<
407 }; 335 };
408 opp-1920000000 { 336 opp-1920000000 {
409 opp-hz = /bits/ 64 <19 337 opp-hz = /bits/ 64 <1920000000>;
410 opp-supported-hw = <0x !! 338 opp-supported-hw = <0x77>;
411 clock-latency-ns = <20 339 clock-latency-ns = <200000>;
412 opp-peak-kBps = <14592 <<
413 }; 340 };
414 opp-1996800000 { 341 opp-1996800000 {
415 opp-hz = /bits/ 64 <19 342 opp-hz = /bits/ 64 <1996800000>;
416 opp-supported-hw = <0x !! 343 opp-supported-hw = <0x77>;
417 clock-latency-ns = <20 344 clock-latency-ns = <200000>;
418 opp-peak-kBps = <15936 <<
419 }; 345 };
420 opp-2073600000 { 346 opp-2073600000 {
421 opp-hz = /bits/ 64 <20 347 opp-hz = /bits/ 64 <2073600000>;
422 opp-supported-hw = <0x !! 348 opp-supported-hw = <0x77>;
423 clock-latency-ns = <20 349 clock-latency-ns = <200000>;
424 opp-peak-kBps = <15936 <<
425 }; 350 };
426 opp-2150400000 { 351 opp-2150400000 {
427 opp-hz = /bits/ 64 <21 352 opp-hz = /bits/ 64 <2150400000>;
428 opp-supported-hw = <0x !! 353 opp-supported-hw = <0x77>;
429 clock-latency-ns = <20 354 clock-latency-ns = <200000>;
430 opp-peak-kBps = <15936 <<
431 }; 355 };
432 }; 356 };
433 357
434 firmware { 358 firmware {
435 scm { 359 scm {
436 compatible = "qcom,scm !! 360 compatible = "qcom,scm-msm8996";
437 qcom,dload-mode = <&tc !! 361 qcom,dload-mode = <&tcsr 0x13000>;
438 }; 362 };
439 }; 363 };
440 364
>> 365 tcsr_mutex: hwlock {
>> 366 compatible = "qcom,tcsr-mutex";
>> 367 syscon = <&tcsr_mutex_regs 0 0x1000>;
>> 368 #hwlock-cells = <1>;
>> 369 };
>> 370
441 memory@80000000 { 371 memory@80000000 {
442 device_type = "memory"; 372 device_type = "memory";
443 /* We expect the bootloader to 373 /* We expect the bootloader to fill in the reg */
444 reg = <0x0 0x80000000 0x0 0x0> 374 reg = <0x0 0x80000000 0x0 0x0>;
445 }; 375 };
446 376
447 etm { <<
448 compatible = "qcom,coresight-r <<
449 <<
450 out-ports { <<
451 port { <<
452 modem_etm_out_ <<
453 remote <<
454 <&fu <<
455 }; <<
456 }; <<
457 }; <<
458 }; <<
459 <<
460 psci { 377 psci {
461 compatible = "arm,psci-1.0"; 378 compatible = "arm,psci-1.0";
462 method = "smc"; 379 method = "smc";
463 }; 380 };
464 381
465 rpm: remoteproc { <<
466 compatible = "qcom,msm8996-rpm <<
467 <<
468 glink-edge { <<
469 compatible = "qcom,gli <<
470 interrupts = <GIC_SPI <<
471 qcom,rpm-msg-ram = <&r <<
472 mboxes = <&apcs_glb 0> <<
473 <<
474 rpm_requests: rpm-requ <<
475 compatible = " <<
476 qcom,glink-cha <<
477 <<
478 rpmcc: clock-c <<
479 compat <<
480 #clock <<
481 clocks <<
482 clock- <<
483 }; <<
484 <<
485 rpmpd: power-c <<
486 compat <<
487 #power <<
488 operat <<
489 <<
490 rpmpd_ <<
491 <<
492 <<
493 <<
494 <<
495 <<
496 <<
497 <<
498 <<
499 <<
500 <<
501 <<
502 <<
503 <<
504 <<
505 <<
506 <<
507 <<
508 <<
509 <<
510 <<
511 <<
512 <<
513 <<
514 <<
515 <<
516 }; <<
517 }; <<
518 }; <<
519 }; <<
520 }; <<
521 <<
522 reserved-memory { 382 reserved-memory {
523 #address-cells = <2>; 383 #address-cells = <2>;
524 #size-cells = <2>; 384 #size-cells = <2>;
525 ranges; 385 ranges;
526 386
527 hyp_mem: memory@85800000 { !! 387 mba_region: mba@91500000 {
528 reg = <0x0 0x85800000 !! 388 reg = <0x0 0x91500000 0x0 0x200000>;
>> 389 no-map;
>> 390 };
>> 391
>> 392 slpi_region: slpi@90b00000 {
>> 393 reg = <0x0 0x90b00000 0x0 0xa00000>;
>> 394 no-map;
>> 395 };
>> 396
>> 397 venus_region: venus@90400000 {
>> 398 reg = <0x0 0x90400000 0x0 0x700000>;
>> 399 no-map;
>> 400 };
>> 401
>> 402 adsp_region: adsp@8ea00000 {
>> 403 reg = <0x0 0x8ea00000 0x0 0x1a00000>;
529 no-map; 404 no-map;
530 }; 405 };
531 406
532 xbl_mem: memory@85e00000 { !! 407 mpss_region: mpss@88800000 {
533 reg = <0x0 0x85e00000 !! 408 reg = <0x0 0x88800000 0x0 0x6200000>;
534 no-map; 409 no-map;
535 }; 410 };
536 411
537 smem_mem: smem-mem@86000000 { 412 smem_mem: smem-mem@86000000 {
538 reg = <0x0 0x86000000 413 reg = <0x0 0x86000000 0x0 0x200000>;
539 no-map; 414 no-map;
540 }; 415 };
541 416
542 tz_mem: memory@86200000 { !! 417 memory@85800000 {
>> 418 reg = <0x0 0x85800000 0x0 0x800000>;
>> 419 no-map;
>> 420 };
>> 421
>> 422 memory@86200000 {
543 reg = <0x0 0x86200000 423 reg = <0x0 0x86200000 0x0 0x2600000>;
544 no-map; 424 no-map;
545 }; 425 };
546 426
547 rmtfs_mem: rmtfs { !! 427 rmtfs@86700000 {
548 compatible = "qcom,rmt 428 compatible = "qcom,rmtfs-mem";
549 429
550 size = <0x0 0x200000>; 430 size = <0x0 0x200000>;
551 alloc-ranges = <0x0 0x 431 alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>;
552 no-map; 432 no-map;
553 433
554 qcom,client-id = <1>; 434 qcom,client-id = <1>;
555 qcom,vmid = <QCOM_SCM_ !! 435 qcom,vmid = <15>;
556 }; 436 };
557 437
558 mpss_mem: mpss@88800000 { !! 438 zap_shader_region: gpu@8f200000 {
559 reg = <0x0 0x88800000 !! 439 compatible = "shared-dma-pool";
>> 440 reg = <0x0 0x90b00000 0x0 0xa00000>;
560 no-map; 441 no-map;
561 }; 442 };
>> 443 };
562 444
563 adsp_mem: adsp@8ea00000 { !! 445 rpm-glink {
564 reg = <0x0 0x8ea00000 !! 446 compatible = "qcom,glink-rpm";
565 no-map; <<
566 }; <<
567 447
568 slpi_mem: slpi@90500000 { !! 448 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
569 reg = <0x0 0x90500000 <<
570 no-map; <<
571 }; <<
572 449
573 gpu_mem: gpu@90f00000 { !! 450 qcom,rpm-msg-ram = <&rpm_msg_ram>;
574 compatible = "shared-d <<
575 reg = <0x0 0x90f00000 <<
576 no-map; <<
577 }; <<
578 451
579 venus_mem: venus@91000000 { !! 452 mboxes = <&apcs_glb 0>;
580 reg = <0x0 0x91000000 <<
581 no-map; <<
582 }; <<
583 453
584 mba_mem: mba@91500000 { !! 454 rpm_requests: rpm-requests {
585 reg = <0x0 0x91500000 !! 455 compatible = "qcom,rpm-msm8996";
586 no-map; !! 456 qcom,glink-channels = "rpm_requests";
587 }; <<
588 457
589 mdata_mem: mpss-metadata { !! 458 rpmcc: qcom,rpmcc {
590 alloc-ranges = <0x0 0x !! 459 compatible = "qcom,rpmcc-msm8996";
591 size = <0x0 0x4000>; !! 460 #clock-cells = <1>;
592 no-map; !! 461 };
>> 462
>> 463 rpmpd: power-controller {
>> 464 compatible = "qcom,msm8996-rpmpd";
>> 465 #power-domain-cells = <1>;
>> 466 operating-points-v2 = <&rpmpd_opp_table>;
>> 467
>> 468 rpmpd_opp_table: opp-table {
>> 469 compatible = "operating-points-v2";
>> 470
>> 471 rpmpd_opp1: opp1 {
>> 472 opp-level = <1>;
>> 473 };
>> 474
>> 475 rpmpd_opp2: opp2 {
>> 476 opp-level = <2>;
>> 477 };
>> 478
>> 479 rpmpd_opp3: opp3 {
>> 480 opp-level = <3>;
>> 481 };
>> 482
>> 483 rpmpd_opp4: opp4 {
>> 484 opp-level = <4>;
>> 485 };
>> 486
>> 487 rpmpd_opp5: opp5 {
>> 488 opp-level = <5>;
>> 489 };
>> 490
>> 491 rpmpd_opp6: opp6 {
>> 492 opp-level = <6>;
>> 493 };
>> 494 };
>> 495 };
593 }; 496 };
594 }; 497 };
595 498
596 smem { 499 smem {
597 compatible = "qcom,smem"; 500 compatible = "qcom,smem";
598 memory-region = <&smem_mem>; 501 memory-region = <&smem_mem>;
599 hwlocks = <&tcsr_mutex 3>; 502 hwlocks = <&tcsr_mutex 3>;
600 }; 503 };
601 504
602 smp2p-adsp { 505 smp2p-adsp {
603 compatible = "qcom,smp2p"; 506 compatible = "qcom,smp2p";
604 qcom,smem = <443>, <429>; 507 qcom,smem = <443>, <429>;
605 508
606 interrupts = <GIC_SPI 158 IRQ_ !! 509 interrupts = <0 158 IRQ_TYPE_EDGE_RISING>;
607 510
608 mboxes = <&apcs_glb 10>; 511 mboxes = <&apcs_glb 10>;
609 512
610 qcom,local-pid = <0>; 513 qcom,local-pid = <0>;
611 qcom,remote-pid = <2>; 514 qcom,remote-pid = <2>;
612 515
613 adsp_smp2p_out: master-kernel !! 516 smp2p_adsp_out: master-kernel {
614 qcom,entry-name = "mas 517 qcom,entry-name = "master-kernel";
615 #qcom,smem-state-cells 518 #qcom,smem-state-cells = <1>;
616 }; 519 };
617 520
618 adsp_smp2p_in: slave-kernel { !! 521 smp2p_adsp_in: slave-kernel {
619 qcom,entry-name = "sla 522 qcom,entry-name = "slave-kernel";
620 523
621 interrupt-controller; 524 interrupt-controller;
622 #interrupt-cells = <2> 525 #interrupt-cells = <2>;
623 }; 526 };
624 }; 527 };
625 528
626 smp2p-mpss { !! 529 smp2p-modem {
627 compatible = "qcom,smp2p"; 530 compatible = "qcom,smp2p";
628 qcom,smem = <435>, <428>; 531 qcom,smem = <435>, <428>;
629 532
630 interrupts = <GIC_SPI 451 IRQ_ 533 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
631 534
632 mboxes = <&apcs_glb 14>; 535 mboxes = <&apcs_glb 14>;
633 536
634 qcom,local-pid = <0>; 537 qcom,local-pid = <0>;
635 qcom,remote-pid = <1>; 538 qcom,remote-pid = <1>;
636 539
637 mpss_smp2p_out: master-kernel !! 540 modem_smp2p_out: master-kernel {
638 qcom,entry-name = "mas 541 qcom,entry-name = "master-kernel";
639 #qcom,smem-state-cells 542 #qcom,smem-state-cells = <1>;
640 }; 543 };
641 544
642 mpss_smp2p_in: slave-kernel { !! 545 modem_smp2p_in: slave-kernel {
643 qcom,entry-name = "sla 546 qcom,entry-name = "slave-kernel";
644 547
645 interrupt-controller; 548 interrupt-controller;
646 #interrupt-cells = <2> 549 #interrupt-cells = <2>;
647 }; 550 };
648 }; 551 };
649 552
650 smp2p-slpi { 553 smp2p-slpi {
651 compatible = "qcom,smp2p"; 554 compatible = "qcom,smp2p";
652 qcom,smem = <481>, <430>; 555 qcom,smem = <481>, <430>;
653 556
654 interrupts = <GIC_SPI 178 IRQ_ 557 interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>;
655 558
656 mboxes = <&apcs_glb 26>; 559 mboxes = <&apcs_glb 26>;
657 560
658 qcom,local-pid = <0>; 561 qcom,local-pid = <0>;
659 qcom,remote-pid = <3>; 562 qcom,remote-pid = <3>;
660 563
661 slpi_smp2p_out: master-kernel !! 564 smp2p_slpi_in: slave-kernel {
662 qcom,entry-name = "mas <<
663 #qcom,smem-state-cells <<
664 }; <<
665 <<
666 slpi_smp2p_in: slave-kernel { <<
667 qcom,entry-name = "sla 565 qcom,entry-name = "slave-kernel";
668 <<
669 interrupt-controller; 566 interrupt-controller;
670 #interrupt-cells = <2> 567 #interrupt-cells = <2>;
671 }; 568 };
>> 569
>> 570 smp2p_slpi_out: master-kernel {
>> 571 qcom,entry-name = "master-kernel";
>> 572 #qcom,smem-state-cells = <1>;
>> 573 };
672 }; 574 };
673 575
674 soc: soc@0 { !! 576 soc: soc {
675 #address-cells = <1>; 577 #address-cells = <1>;
676 #size-cells = <1>; 578 #size-cells = <1>;
677 ranges = <0 0 0 0xffffffff>; 579 ranges = <0 0 0 0xffffffff>;
678 compatible = "simple-bus"; 580 compatible = "simple-bus";
679 581
680 pcie_phy: phy-wrapper@34000 { !! 582 pcie_phy: phy@34000 {
681 compatible = "qcom,msm 583 compatible = "qcom,msm8996-qmp-pcie-phy";
682 reg = <0x00034000 0x48 584 reg = <0x00034000 0x488>;
683 #address-cells = <1>; 585 #address-cells = <1>;
684 #size-cells = <1>; 586 #size-cells = <1>;
685 ranges = <0x0 0x000340 !! 587 ranges;
686 588
687 clocks = <&gcc GCC_PCI 589 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
688 <&gcc GCC_PCIE 590 <&gcc GCC_PCIE_PHY_CFG_AHB_CLK>,
689 <&gcc GCC_PCIE 591 <&gcc GCC_PCIE_CLKREF_CLK>;
690 clock-names = "aux", " 592 clock-names = "aux", "cfg_ahb", "ref";
691 593
692 resets = <&gcc GCC_PCI 594 resets = <&gcc GCC_PCIE_PHY_BCR>,
693 <&gcc GCC_PCIE 595 <&gcc GCC_PCIE_PHY_COM_BCR>,
694 <&gcc GCC_PCIE 596 <&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>;
695 reset-names = "phy", " 597 reset-names = "phy", "common", "cfg";
696 <<
697 status = "disabled"; 598 status = "disabled";
698 599
699 pciephy_0: phy@1000 { !! 600 pciephy_0: phy@35000 {
700 reg = <0x1000 !! 601 reg = <0x00035000 0x130>,
701 <0x1200 !! 602 <0x00035200 0x200>,
702 <0x1400 !! 603 <0x00035400 0x1dc>;
>> 604 #phy-cells = <0>;
703 605
>> 606 #clock-cells = <0>;
>> 607 clock-output-names = "pcie_0_pipe_clk_src";
704 clocks = <&gcc 608 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
705 clock-names = 609 clock-names = "pipe0";
706 resets = <&gcc 610 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
707 reset-names = 611 reset-names = "lane0";
708 <<
709 #clock-cells = <<
710 clock-output-n <<
711 <<
712 #phy-cells = < <<
713 }; 612 };
714 613
715 pciephy_1: phy@2000 { !! 614 pciephy_1: phy@36000 {
716 reg = <0x2000 !! 615 reg = <0x00036000 0x130>,
717 <0x2200 !! 616 <0x00036200 0x200>,
718 <0x2400 !! 617 <0x00036400 0x1dc>;
>> 618 #phy-cells = <0>;
719 619
>> 620 #clock-cells = <0>;
>> 621 clock-output-names = "pcie_1_pipe_clk_src";
720 clocks = <&gcc 622 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
721 clock-names = 623 clock-names = "pipe1";
722 resets = <&gcc 624 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
723 reset-names = 625 reset-names = "lane1";
724 <<
725 #clock-cells = <<
726 clock-output-n <<
727 <<
728 #phy-cells = < <<
729 }; 626 };
730 627
731 pciephy_2: phy@3000 { !! 628 pciephy_2: phy@37000 {
732 reg = <0x3000 !! 629 reg = <0x00037000 0x130>,
733 <0x3200 !! 630 <0x00037200 0x200>,
734 <0x3400 !! 631 <0x00037400 0x1dc>;
>> 632 #phy-cells = <0>;
735 633
>> 634 #clock-cells = <0>;
>> 635 clock-output-names = "pcie_2_pipe_clk_src";
736 clocks = <&gcc 636 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>;
737 clock-names = 637 clock-names = "pipe2";
738 resets = <&gcc 638 resets = <&gcc GCC_PCIE_2_PHY_BCR>;
739 reset-names = 639 reset-names = "lane2";
740 <<
741 #clock-cells = <<
742 clock-output-n <<
743 <<
744 #phy-cells = < <<
745 }; 640 };
746 }; 641 };
747 642
748 rpm_msg_ram: sram@68000 { 643 rpm_msg_ram: sram@68000 {
749 compatible = "qcom,rpm 644 compatible = "qcom,rpm-msg-ram";
750 reg = <0x00068000 0x60 645 reg = <0x00068000 0x6000>;
751 }; 646 };
752 647
753 qfprom@74000 { 648 qfprom@74000 {
754 compatible = "qcom,msm !! 649 compatible = "qcom,qfprom";
755 reg = <0x00074000 0x8f 650 reg = <0x00074000 0x8ff>;
756 #address-cells = <1>; 651 #address-cells = <1>;
757 #size-cells = <1>; 652 #size-cells = <1>;
758 653
759 qusb2p_hstx_trim: hstx !! 654 qusb2p_hstx_trim: hstx_trim@24e {
760 reg = <0x24e 0 655 reg = <0x24e 0x2>;
761 bits = <5 4>; 656 bits = <5 4>;
762 }; 657 };
763 658
764 qusb2s_hstx_trim: hstx !! 659 qusb2s_hstx_trim: hstx_trim@24f {
765 reg = <0x24f 0 660 reg = <0x24f 0x1>;
766 bits = <1 4>; 661 bits = <1 4>;
767 }; 662 };
768 663
769 speedbin_efuse: speedb 664 speedbin_efuse: speedbin@133 {
770 reg = <0x133 0 665 reg = <0x133 0x1>;
771 bits = <5 3>; 666 bits = <5 3>;
772 }; 667 };
773 }; 668 };
774 669
775 rng: rng@83000 { 670 rng: rng@83000 {
776 compatible = "qcom,prn 671 compatible = "qcom,prng-ee";
777 reg = <0x00083000 0x10 672 reg = <0x00083000 0x1000>;
778 clocks = <&gcc GCC_PRN 673 clocks = <&gcc GCC_PRNG_AHB_CLK>;
779 clock-names = "core"; 674 clock-names = "core";
780 }; 675 };
781 676
782 gcc: clock-controller@300000 { 677 gcc: clock-controller@300000 {
783 compatible = "qcom,gcc 678 compatible = "qcom,gcc-msm8996";
784 #clock-cells = <1>; 679 #clock-cells = <1>;
785 #reset-cells = <1>; 680 #reset-cells = <1>;
786 #power-domain-cells = 681 #power-domain-cells = <1>;
787 reg = <0x00300000 0x90 682 reg = <0x00300000 0x90000>;
788 683
789 clocks = <&rpmcc RPM_S !! 684 clocks = <&rpmcc RPM_SMD_BB_CLK1>,
790 <&rpmcc RPM_S 685 <&rpmcc RPM_SMD_LN_BB_CLK>,
791 <&sleep_clk>, !! 686 <&sleep_clk>;
792 <&pciephy_0>, !! 687 clock-names = "cxo", "cxo2", "sleep_clk";
793 <&pciephy_1>, <<
794 <&pciephy_2>, <<
795 <&usb3phy>, <<
796 <&ufsphy 0>, <<
797 <&ufsphy 1>, <<
798 <&ufsphy 2>; <<
799 clock-names = "cxo", <<
800 "cxo2", <<
801 "sleep_c <<
802 "pcie_0_ <<
803 "pcie_1_ <<
804 "pcie_2_ <<
805 "usb3_ph <<
806 "ufs_rx_ <<
807 "ufs_rx_ <<
808 "ufs_tx_ <<
809 }; <<
810 <<
811 bimc: interconnect@408000 { <<
812 compatible = "qcom,msm <<
813 reg = <0x00408000 0x5a <<
814 #interconnect-cells = <<
815 }; 688 };
816 689
817 tsens0: thermal-sensor@4a9000 690 tsens0: thermal-sensor@4a9000 {
818 compatible = "qcom,msm 691 compatible = "qcom,msm8996-tsens", "qcom,tsens-v2";
819 reg = <0x004a9000 0x10 692 reg = <0x004a9000 0x1000>, /* TM */
820 <0x004a8000 0x10 693 <0x004a8000 0x1000>; /* SROT */
821 #qcom,sensors = <13>; 694 #qcom,sensors = <13>;
822 interrupts = <GIC_SPI 695 interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
823 <GIC_SPI 696 <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
824 interrupt-names = "upl 697 interrupt-names = "uplow", "critical";
825 #thermal-sensor-cells 698 #thermal-sensor-cells = <1>;
826 }; 699 };
827 700
828 tsens1: thermal-sensor@4ad000 701 tsens1: thermal-sensor@4ad000 {
829 compatible = "qcom,msm 702 compatible = "qcom,msm8996-tsens", "qcom,tsens-v2";
830 reg = <0x004ad000 0x10 703 reg = <0x004ad000 0x1000>, /* TM */
831 <0x004ac000 0x10 704 <0x004ac000 0x1000>; /* SROT */
832 #qcom,sensors = <8>; 705 #qcom,sensors = <8>;
833 interrupts = <GIC_SPI 706 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
834 <GIC_SPI 707 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>;
835 interrupt-names = "upl 708 interrupt-names = "uplow", "critical";
836 #thermal-sensor-cells 709 #thermal-sensor-cells = <1>;
837 }; 710 };
838 711
839 cryptobam: dma-controller@6440 !! 712 cryptobam: dma@644000 {
840 compatible = "qcom,bam 713 compatible = "qcom,bam-v1.7.0";
841 reg = <0x00644000 0x24 714 reg = <0x00644000 0x24000>;
842 interrupts = <GIC_SPI 715 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
843 clocks = <&gcc GCC_CE1 716 clocks = <&gcc GCC_CE1_CLK>;
844 clock-names = "bam_clk 717 clock-names = "bam_clk";
845 #dma-cells = <1>; 718 #dma-cells = <1>;
846 qcom,ee = <0>; 719 qcom,ee = <0>;
847 qcom,controlled-remote 720 qcom,controlled-remotely;
848 }; 721 };
849 722
850 crypto: crypto@67a000 { 723 crypto: crypto@67a000 {
851 compatible = "qcom,cry 724 compatible = "qcom,crypto-v5.4";
852 reg = <0x0067a000 0x60 725 reg = <0x0067a000 0x6000>;
853 clocks = <&gcc GCC_CE1 726 clocks = <&gcc GCC_CE1_AHB_CLK>,
854 <&gcc GCC_CE1 727 <&gcc GCC_CE1_AXI_CLK>,
855 <&gcc GCC_CE1 728 <&gcc GCC_CE1_CLK>;
856 clock-names = "iface", 729 clock-names = "iface", "bus", "core";
857 dmas = <&cryptobam 6>, 730 dmas = <&cryptobam 6>, <&cryptobam 7>;
858 dma-names = "rx", "tx" 731 dma-names = "rx", "tx";
859 }; 732 };
860 733
861 cnoc: interconnect@500000 { !! 734 tcsr_mutex_regs: syscon@740000 {
862 compatible = "qcom,msm !! 735 compatible = "syscon";
863 reg = <0x00500000 0x10 !! 736 reg = <0x00740000 0x40000>;
864 #interconnect-cells = <<
865 }; <<
866 <<
867 snoc: interconnect@524000 { <<
868 compatible = "qcom,msm <<
869 reg = <0x00524000 0x1c <<
870 #interconnect-cells = <<
871 }; <<
872 <<
873 a0noc: interconnect@543000 { <<
874 compatible = "qcom,msm <<
875 reg = <0x00543000 0x60 <<
876 #interconnect-cells = <<
877 clock-names = "aggre0_ <<
878 "aggre0_ <<
879 "aggre0_ <<
880 clocks = <&gcc GCC_AGG <<
881 <&gcc GCC_AGG <<
882 <&gcc GCC_AGG <<
883 power-domains = <&gcc <<
884 }; <<
885 <<
886 a1noc: interconnect@562000 { <<
887 compatible = "qcom,msm <<
888 reg = <0x00562000 0x50 <<
889 #interconnect-cells = <<
890 }; <<
891 <<
892 a2noc: interconnect@583000 { <<
893 compatible = "qcom,msm <<
894 reg = <0x00583000 0x70 <<
895 #interconnect-cells = <<
896 clock-names = "aggre2_ <<
897 clocks = <&gcc GCC_AGG <<
898 <&gcc GCC_UFS <<
899 }; <<
900 <<
901 mnoc: interconnect@5a4000 { <<
902 compatible = "qcom,msm <<
903 reg = <0x005a4000 0x1c <<
904 #interconnect-cells = <<
905 clock-names = "iface"; <<
906 clocks = <&mmcc AHB_CL <<
907 }; <<
908 <<
909 pnoc: interconnect@5c0000 { <<
910 compatible = "qcom,msm <<
911 reg = <0x005c0000 0x30 <<
912 #interconnect-cells = <<
913 }; <<
914 <<
915 tcsr_mutex: hwlock@740000 { <<
916 compatible = "qcom,tcs <<
917 reg = <0x00740000 0x20 <<
918 #hwlock-cells = <1>; <<
919 }; <<
920 <<
921 tcsr_1: syscon@760000 { <<
922 compatible = "qcom,tcs <<
923 reg = <0x00760000 0x20 <<
924 }; 737 };
925 738
926 tcsr_2: syscon@7a0000 { !! 739 tcsr: syscon@7a0000 {
927 compatible = "qcom,tcs 740 compatible = "qcom,tcsr-msm8996", "syscon";
928 reg = <0x007a0000 0x18 741 reg = <0x007a0000 0x18000>;
929 }; 742 };
930 743
931 mmcc: clock-controller@8c0000 744 mmcc: clock-controller@8c0000 {
932 compatible = "qcom,mmc 745 compatible = "qcom,mmcc-msm8996";
933 #clock-cells = <1>; 746 #clock-cells = <1>;
934 #reset-cells = <1>; 747 #reset-cells = <1>;
935 #power-domain-cells = 748 #power-domain-cells = <1>;
936 reg = <0x008c0000 0x40 749 reg = <0x008c0000 0x40000>;
937 clocks = <&xo_board>, <<
938 <&gcc GPLL0>, <<
939 <&gcc GCC_MMS <<
940 <&mdss_dsi0_p <<
941 <&mdss_dsi0_p <<
942 <&mdss_dsi1_p <<
943 <&mdss_dsi1_p <<
944 <&mdss_hdmi_p <<
945 clock-names = "xo", <<
946 "gpll0", <<
947 "gcc_mms <<
948 "dsi0pll <<
949 "dsi0pll <<
950 "dsi1pll <<
951 "dsi1pll <<
952 "hdmipll <<
953 assigned-clocks = <&mm 750 assigned-clocks = <&mmcc MMPLL9_PLL>,
954 <&mm 751 <&mmcc MMPLL1_PLL>,
955 <&mm 752 <&mmcc MMPLL3_PLL>,
956 <&mm 753 <&mmcc MMPLL4_PLL>,
957 <&mm 754 <&mmcc MMPLL5_PLL>;
958 assigned-clock-rates = 755 assigned-clock-rates = <624000000>,
959 756 <810000000>,
960 757 <980000000>,
961 758 <960000000>,
962 759 <825000000>;
963 }; 760 };
964 761
965 mdss: display-subsystem@900000 !! 762 mdss: mdss@900000 {
966 compatible = "qcom,mds 763 compatible = "qcom,mdss";
967 764
968 reg = <0x00900000 0x10 765 reg = <0x00900000 0x1000>,
969 <0x009b0000 0x10 766 <0x009b0000 0x1040>,
970 <0x009b8000 0x10 767 <0x009b8000 0x1040>;
971 reg-names = "mdss_phys 768 reg-names = "mdss_phys",
972 "vbif_phys 769 "vbif_phys",
973 "vbif_nrt_ 770 "vbif_nrt_phys";
974 771
975 power-domains = <&mmcc 772 power-domains = <&mmcc MDSS_GDSC>;
976 interrupts = <GIC_SPI 773 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
977 774
978 interrupt-controller; 775 interrupt-controller;
979 #interrupt-cells = <1> 776 #interrupt-cells = <1>;
980 777
981 clocks = <&mmcc MDSS_A !! 778 clocks = <&mmcc MDSS_AHB_CLK>;
982 <&mmcc MDSS_M !! 779 clock-names = "iface";
983 clock-names = "iface", <<
984 <<
985 resets = <&mmcc MDSS_B <<
986 780
987 #address-cells = <1>; 781 #address-cells = <1>;
988 #size-cells = <1>; 782 #size-cells = <1>;
989 ranges; 783 ranges;
990 784
991 status = "disabled"; 785 status = "disabled";
992 786
993 mdp: display-controlle !! 787 mdp: mdp@901000 {
994 compatible = " !! 788 compatible = "qcom,mdp5";
995 reg = <0x00901 789 reg = <0x00901000 0x90000>;
996 reg-names = "m 790 reg-names = "mdp_phys";
997 791
998 interrupt-pare 792 interrupt-parent = <&mdss>;
999 interrupts = < !! 793 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
1000 794
1001 clocks = <&mm 795 clocks = <&mmcc MDSS_AHB_CLK>,
1002 <&mm 796 <&mmcc MDSS_AXI_CLK>,
1003 <&mm 797 <&mmcc MDSS_MDP_CLK>,
1004 <&mm 798 <&mmcc SMMU_MDP_AXI_CLK>,
1005 <&mm 799 <&mmcc MDSS_VSYNC_CLK>;
1006 clock-names = 800 clock-names = "iface",
1007 801 "bus",
1008 802 "core",
1009 803 "iommu",
1010 804 "vsync";
1011 805
1012 iommus = <&md 806 iommus = <&mdp_smmu 0>;
1013 807
1014 assigned-cloc 808 assigned-clocks = <&mmcc MDSS_MDP_CLK>,
1015 <&mm 809 <&mmcc MDSS_VSYNC_CLK>;
1016 assigned-cloc 810 assigned-clock-rates = <300000000>,
1017 <192 811 <19200000>;
1018 812
1019 interconnects <<
1020 <<
1021 <<
1022 interconnect- <<
1023 <<
1024 ports { 813 ports {
1025 #addr 814 #address-cells = <1>;
1026 #size 815 #size-cells = <0>;
1027 816
1028 port@ 817 port@0 {
1029 818 reg = <0>;
1030 819 mdp5_intf3_out: endpoint {
1031 !! 820 remote-endpoint = <&hdmi_in>;
1032 821 };
1033 }; 822 };
1034 823
1035 port@ 824 port@1 {
1036 825 reg = <1>;
1037 826 mdp5_intf1_out: endpoint {
1038 !! 827 remote-endpoint = <&dsi0_in>;
1039 <<
1040 }; <<
1041 <<
1042 port@ <<
1043 <<
1044 <<
1045 <<
1046 828 };
1047 }; 829 };
1048 }; 830 };
1049 }; 831 };
1050 832
1051 mdss_dsi0: dsi@994000 !! 833 dsi0: dsi@994000 {
1052 compatible = !! 834 compatible = "qcom,mdss-dsi-ctrl";
1053 <<
1054 reg = <0x0099 835 reg = <0x00994000 0x400>;
1055 reg-names = " 836 reg-names = "dsi_ctrl";
1056 837
1057 interrupt-par 838 interrupt-parent = <&mdss>;
1058 interrupts = !! 839 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
1059 840
1060 clocks = <&mm 841 clocks = <&mmcc MDSS_MDP_CLK>,
1061 <&mm 842 <&mmcc MDSS_BYTE0_CLK>,
1062 <&mm 843 <&mmcc MDSS_AHB_CLK>,
1063 <&mm 844 <&mmcc MDSS_AXI_CLK>,
1064 <&mm 845 <&mmcc MMSS_MISC_AHB_CLK>,
1065 <&mm 846 <&mmcc MDSS_PCLK0_CLK>,
1066 <&mm 847 <&mmcc MDSS_ESC0_CLK>;
1067 clock-names = 848 clock-names = "mdp_core",
1068 849 "byte",
1069 850 "iface",
1070 851 "bus",
1071 852 "core_mmss",
1072 853 "pixel",
1073 854 "core";
1074 assigned-cloc <<
1075 assigned-cloc <<
1076 855
1077 phys = <&mdss !! 856 phys = <&dsi0_phy>;
>> 857 phy-names = "dsi";
1078 status = "dis 858 status = "disabled";
1079 859
1080 #address-cell 860 #address-cells = <1>;
1081 #size-cells = 861 #size-cells = <0>;
1082 862
1083 ports { 863 ports {
1084 #addr 864 #address-cells = <1>;
1085 #size 865 #size-cells = <0>;
1086 866
1087 port@ 867 port@0 {
1088 868 reg = <0>;
1089 !! 869 dsi0_in: endpoint {
1090 870 remote-endpoint = <&mdp5_intf1_out>;
1091 871 };
1092 }; 872 };
1093 873
1094 port@ 874 port@1 {
1095 875 reg = <1>;
1096 !! 876 dsi0_out: endpoint {
1097 877 };
1098 }; 878 };
1099 }; 879 };
1100 }; 880 };
1101 881
1102 mdss_dsi0_phy: phy@99 !! 882 dsi0_phy: dsi-phy@994400 {
1103 compatible = 883 compatible = "qcom,dsi-phy-14nm";
1104 reg = <0x0099 884 reg = <0x00994400 0x100>,
1105 <0x0099 885 <0x00994500 0x300>,
1106 <0x0099 886 <0x00994800 0x188>;
1107 reg-names = " 887 reg-names = "dsi_phy",
1108 " 888 "dsi_phy_lane",
1109 " 889 "dsi_pll";
1110 890
1111 #clock-cells 891 #clock-cells = <1>;
1112 #phy-cells = 892 #phy-cells = <0>;
1113 893
1114 clocks = <&mm !! 894 clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_BB_CLK1>;
1115 clock-names = <<
1116 status = "dis <<
1117 }; <<
1118 <<
1119 mdss_dsi1: dsi@996000 <<
1120 compatible = <<
1121 <<
1122 reg = <0x0099 <<
1123 reg-names = " <<
1124 <<
1125 interrupt-par <<
1126 interrupts = <<
1127 <<
1128 clocks = <&mm <<
1129 <&mm <<
1130 <&mm <<
1131 <&mm <<
1132 <&mm <<
1133 <&mm <<
1134 <&mm <<
1135 clock-names = <<
1136 <<
1137 <<
1138 <<
1139 <<
1140 <<
1141 <<
1142 assigned-cloc <<
1143 assigned-cloc <<
1144 <<
1145 phys = <&mdss <<
1146 status = "dis <<
1147 <<
1148 #address-cell <<
1149 #size-cells = <<
1150 <<
1151 ports { <<
1152 #addr <<
1153 #size <<
1154 <<
1155 port@ <<
1156 <<
1157 <<
1158 <<
1159 <<
1160 }; <<
1161 <<
1162 port@ <<
1163 <<
1164 <<
1165 <<
1166 }; <<
1167 }; <<
1168 }; <<
1169 <<
1170 mdss_dsi1_phy: phy@99 <<
1171 compatible = <<
1172 reg = <0x0099 <<
1173 <0x0099 <<
1174 <0x0099 <<
1175 reg-names = " <<
1176 " <<
1177 " <<
1178 <<
1179 #clock-cells <<
1180 #phy-cells = <<
1181 <<
1182 clocks = <&mm <<
1183 clock-names = 895 clock-names = "iface", "ref";
1184 status = "dis 896 status = "disabled";
1185 }; 897 };
1186 898
1187 mdss_hdmi: hdmi-tx@9a !! 899 hdmi: hdmi-tx@9a0000 {
1188 compatible = 900 compatible = "qcom,hdmi-tx-8996";
1189 reg = <0x009a !! 901 reg = <0x009a0000 0x50c>,
1190 <0x0007 !! 902 <0x00070000 0x6158>,
1191 <0x009e !! 903 <0x009e0000 0xfff>;
1192 reg-names = " 904 reg-names = "core_physical",
1193 " 905 "qfprom_physical",
1194 " 906 "hdcp_physical";
1195 907
1196 interrupt-par 908 interrupt-parent = <&mdss>;
1197 interrupts = !! 909 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
1198 910
1199 clocks = <&mm 911 clocks = <&mmcc MDSS_MDP_CLK>,
1200 <&mm 912 <&mmcc MDSS_AHB_CLK>,
1201 <&mm 913 <&mmcc MDSS_HDMI_CLK>,
1202 <&mm 914 <&mmcc MDSS_HDMI_AHB_CLK>,
1203 <&mm 915 <&mmcc MDSS_EXTPCLK_CLK>;
1204 clock-names = 916 clock-names =
1205 "mdp_ 917 "mdp_core",
1206 "ifac 918 "iface",
1207 "core 919 "core",
1208 "alt_ 920 "alt_iface",
1209 "extp 921 "extp";
1210 922
1211 phys = <&mdss !! 923 phys = <&hdmi_phy>;
>> 924 phy-names = "hdmi_phy";
1212 #sound-dai-ce 925 #sound-dai-cells = <1>;
1213 926
1214 status = "dis 927 status = "disabled";
1215 928
1216 ports { 929 ports {
1217 #addr 930 #address-cells = <1>;
1218 #size 931 #size-cells = <0>;
1219 932
1220 port@ 933 port@0 {
1221 934 reg = <0>;
1222 !! 935 hdmi_in: endpoint {
1223 936 remote-endpoint = <&mdp5_intf3_out>;
1224 937 };
1225 }; 938 };
1226 }; 939 };
1227 }; 940 };
1228 941
1229 mdss_hdmi_phy: phy@9a !! 942 hdmi_phy: hdmi-phy@9a0600 {
1230 #phy-cells = 943 #phy-cells = <0>;
1231 compatible = 944 compatible = "qcom,hdmi-phy-8996";
1232 reg = <0x009a 945 reg = <0x009a0600 0x1c4>,
1233 <0x009a 946 <0x009a0a00 0x124>,
1234 <0x009a 947 <0x009a0c00 0x124>,
1235 <0x009a 948 <0x009a0e00 0x124>,
1236 <0x009a 949 <0x009a1000 0x124>,
1237 <0x009a 950 <0x009a1200 0x0c8>;
1238 reg-names = " 951 reg-names = "hdmi_pll",
1239 " 952 "hdmi_tx_l0",
1240 " 953 "hdmi_tx_l1",
1241 " 954 "hdmi_tx_l2",
1242 " 955 "hdmi_tx_l3",
1243 " 956 "hdmi_phy";
1244 957
1245 clocks = <&mm 958 clocks = <&mmcc MDSS_AHB_CLK>,
1246 <&gc !! 959 <&gcc GCC_HDMI_CLKREF_CLK>;
1247 <&xo <<
1248 clock-names = 960 clock-names = "iface",
1249 !! 961 "ref";
1250 <<
1251 <<
1252 #clock-cells <<
1253 962
1254 status = "dis 963 status = "disabled";
1255 }; 964 };
1256 }; 965 };
1257 966
1258 gpu: gpu@b00000 { 967 gpu: gpu@b00000 {
1259 compatible = "qcom,ad 968 compatible = "qcom,adreno-530.2", "qcom,adreno";
1260 969
1261 reg = <0x00b00000 0x3 970 reg = <0x00b00000 0x3f000>;
1262 reg-names = "kgsl_3d0 971 reg-names = "kgsl_3d0_reg_memory";
1263 972
1264 interrupts = <GIC_SPI !! 973 interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;
1265 974
1266 clocks = <&mmcc GPU_G 975 clocks = <&mmcc GPU_GX_GFX3D_CLK>,
1267 <&mmcc GPU_AH 976 <&mmcc GPU_AHB_CLK>,
1268 <&mmcc GPU_GX 977 <&mmcc GPU_GX_RBBMTIMER_CLK>,
1269 <&gcc GCC_BIM 978 <&gcc GCC_BIMC_GFX_CLK>,
1270 <&gcc GCC_MMS 979 <&gcc GCC_MMSS_BIMC_GFX_CLK>;
1271 980
1272 clock-names = "core", 981 clock-names = "core",
1273 "iface", 982 "iface",
1274 "rbbmtimer", 983 "rbbmtimer",
1275 "mem", 984 "mem",
1276 "mem_iface"; 985 "mem_iface";
1277 986
1278 interconnects = <&bim <<
1279 interconnect-names = <<
1280 <<
1281 power-domains = <&mmc 987 power-domains = <&mmcc GPU_GX_GDSC>;
1282 iommus = <&adreno_smm 988 iommus = <&adreno_smmu 0>;
1283 989
1284 nvmem-cells = <&speed 990 nvmem-cells = <&speedbin_efuse>;
1285 nvmem-cell-names = "s 991 nvmem-cell-names = "speed_bin";
1286 992
1287 operating-points-v2 = 993 operating-points-v2 = <&gpu_opp_table>;
1288 994
1289 status = "disabled"; 995 status = "disabled";
1290 996
1291 #cooling-cells = <2>; 997 #cooling-cells = <2>;
1292 998
1293 gpu_opp_table: opp-ta 999 gpu_opp_table: opp-table {
1294 compatible = !! 1000 compatible ="operating-points-v2";
1295 1001
1296 /* 1002 /*
1297 * 624Mhz is !! 1003 * 624Mhz and 560Mhz are only available on speed
1298 * 560Mhz is !! 1004 * bin (1 << 0). All the rest are available on
1299 * All the re !! 1005 * all bins of the hardware
1300 */ 1006 */
1301 opp-624000000 1007 opp-624000000 {
1302 opp-h 1008 opp-hz = /bits/ 64 <624000000>;
1303 opp-s !! 1009 opp-supported-hw = <0x01>;
1304 }; 1010 };
1305 opp-560000000 1011 opp-560000000 {
1306 opp-h 1012 opp-hz = /bits/ 64 <560000000>;
1307 opp-s !! 1013 opp-supported-hw = <0x01>;
1308 }; 1014 };
1309 opp-510000000 1015 opp-510000000 {
1310 opp-h 1016 opp-hz = /bits/ 64 <510000000>;
1311 opp-s !! 1017 opp-supported-hw = <0xFF>;
1312 }; 1018 };
1313 opp-401800000 1019 opp-401800000 {
1314 opp-h 1020 opp-hz = /bits/ 64 <401800000>;
1315 opp-s !! 1021 opp-supported-hw = <0xFF>;
1316 }; 1022 };
1317 opp-315000000 1023 opp-315000000 {
1318 opp-h 1024 opp-hz = /bits/ 64 <315000000>;
1319 opp-s !! 1025 opp-supported-hw = <0xFF>;
1320 }; 1026 };
1321 opp-214000000 1027 opp-214000000 {
1322 opp-h 1028 opp-hz = /bits/ 64 <214000000>;
1323 opp-s !! 1029 opp-supported-hw = <0xFF>;
1324 }; 1030 };
1325 opp-133000000 1031 opp-133000000 {
1326 opp-h 1032 opp-hz = /bits/ 64 <133000000>;
1327 opp-s !! 1033 opp-supported-hw = <0xFF>;
1328 }; 1034 };
1329 }; 1035 };
1330 1036
1331 zap-shader { 1037 zap-shader {
1332 memory-region !! 1038 memory-region = <&zap_shader_region>;
1333 }; 1039 };
1334 }; 1040 };
1335 1041
1336 tlmm: pinctrl@1010000 { 1042 tlmm: pinctrl@1010000 {
1337 compatible = "qcom,ms 1043 compatible = "qcom,msm8996-pinctrl";
1338 reg = <0x01010000 0x3 1044 reg = <0x01010000 0x300000>;
1339 interrupts = <GIC_SPI 1045 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1340 gpio-controller; 1046 gpio-controller;
1341 gpio-ranges = <&tlmm 1047 gpio-ranges = <&tlmm 0 0 150>;
1342 #gpio-cells = <2>; 1048 #gpio-cells = <2>;
1343 interrupt-controller; 1049 interrupt-controller;
1344 #interrupt-cells = <2 1050 #interrupt-cells = <2>;
1345 1051
1346 blsp1_spi1_default: b !! 1052 blsp1_spi1_default: blsp1-spi1-default {
1347 spi-pins { !! 1053 spi {
1348 pins 1054 pins = "gpio0", "gpio1", "gpio3";
1349 funct 1055 function = "blsp_spi1";
1350 drive 1056 drive-strength = <12>;
1351 bias- 1057 bias-disable;
1352 }; 1058 };
1353 1059
1354 cs-pins { !! 1060 cs {
1355 pins 1061 pins = "gpio2";
1356 funct 1062 function = "gpio";
1357 drive 1063 drive-strength = <16>;
1358 bias- 1064 bias-disable;
1359 outpu 1065 output-high;
1360 }; 1066 };
1361 }; 1067 };
1362 1068
1363 blsp1_spi1_sleep: bls !! 1069 blsp1_spi1_sleep: blsp1-spi1-sleep {
1364 pins = "gpio0 1070 pins = "gpio0", "gpio1", "gpio2", "gpio3";
1365 function = "g 1071 function = "gpio";
1366 drive-strengt 1072 drive-strength = <2>;
1367 bias-pull-dow 1073 bias-pull-down;
1368 }; 1074 };
1369 1075
1370 blsp2_uart2_2pins_def !! 1076 blsp2_uart2_2pins_default: blsp2-uart1-2pins {
1371 pins = "gpio4 1077 pins = "gpio4", "gpio5";
1372 function = "b 1078 function = "blsp_uart8";
1373 drive-strengt 1079 drive-strength = <16>;
1374 bias-disable; 1080 bias-disable;
1375 }; 1081 };
1376 1082
1377 blsp2_uart2_2pins_sle !! 1083 blsp2_uart2_2pins_sleep: blsp2-uart1-2pins-sleep {
1378 pins = "gpio4 1084 pins = "gpio4", "gpio5";
1379 function = "g 1085 function = "gpio";
1380 drive-strengt 1086 drive-strength = <2>;
1381 bias-disable; 1087 bias-disable;
1382 }; 1088 };
1383 1089
1384 blsp2_i2c2_default: b !! 1090 blsp2_i2c2_default: blsp2-i2c2 {
1385 pins = "gpio6 1091 pins = "gpio6", "gpio7";
1386 function = "b 1092 function = "blsp_i2c8";
1387 drive-strengt 1093 drive-strength = <16>;
1388 bias-disable; 1094 bias-disable;
1389 }; 1095 };
1390 1096
1391 blsp2_i2c2_sleep: bls !! 1097 blsp2_i2c2_sleep: blsp2-i2c2-sleep {
1392 pins = "gpio6 1098 pins = "gpio6", "gpio7";
1393 function = "g 1099 function = "gpio";
1394 drive-strengt 1100 drive-strength = <2>;
1395 bias-disable; 1101 bias-disable;
1396 }; 1102 };
1397 1103
1398 blsp1_i2c6_default: b !! 1104 cci0_default: cci0-default {
1399 pins = "gpio2 <<
1400 function = "b <<
1401 drive-strengt <<
1402 bias-disable; <<
1403 }; <<
1404 <<
1405 blsp1_i2c6_sleep: bls <<
1406 pins = "gpio2 <<
1407 function = "g <<
1408 drive-strengt <<
1409 bias-pull-up; <<
1410 }; <<
1411 <<
1412 cci0_default: cci0-de <<
1413 pins = "gpio1 1105 pins = "gpio17", "gpio18";
1414 function = "c 1106 function = "cci_i2c";
1415 drive-strengt 1107 drive-strength = <16>;
1416 bias-disable; 1108 bias-disable;
1417 }; 1109 };
1418 1110
1419 camera0_state_on: 1111 camera0_state_on:
1420 camera_rear_default: !! 1112 camera_rear_default: camera-rear-default {
1421 camera0_mclk: !! 1113 camera0_mclk: mclk0 {
1422 pins 1114 pins = "gpio13";
1423 funct 1115 function = "cam_mclk";
1424 drive 1116 drive-strength = <16>;
1425 bias- 1117 bias-disable;
1426 }; 1118 };
1427 1119
1428 camera0_rst: !! 1120 camera0_rst: rst {
1429 pins 1121 pins = "gpio25";
1430 funct 1122 function = "gpio";
1431 drive 1123 drive-strength = <16>;
1432 bias- 1124 bias-disable;
1433 }; 1125 };
1434 1126
1435 camera0_pwdn: !! 1127 camera0_pwdn: pwdn {
1436 pins 1128 pins = "gpio26";
1437 funct 1129 function = "gpio";
1438 drive 1130 drive-strength = <16>;
1439 bias- 1131 bias-disable;
1440 }; 1132 };
1441 }; 1133 };
1442 1134
1443 cci1_default: cci1-de !! 1135 cci1_default: cci1-default {
1444 pins = "gpio1 1136 pins = "gpio19", "gpio20";
1445 function = "c 1137 function = "cci_i2c";
1446 drive-strengt 1138 drive-strength = <16>;
1447 bias-disable; 1139 bias-disable;
1448 }; 1140 };
1449 1141
1450 camera1_state_on: 1142 camera1_state_on:
1451 camera_board_default: !! 1143 camera_board_default: camera-board-default {
1452 mclk1-pins { !! 1144 mclk1 {
1453 pins 1145 pins = "gpio14";
1454 funct 1146 function = "cam_mclk";
1455 drive 1147 drive-strength = <16>;
1456 bias- 1148 bias-disable;
1457 }; 1149 };
1458 1150
1459 pwdn-pins { !! 1151 pwdn {
1460 pins 1152 pins = "gpio98";
1461 funct 1153 function = "gpio";
1462 drive 1154 drive-strength = <16>;
1463 bias- 1155 bias-disable;
1464 }; 1156 };
1465 1157
1466 rst-pins { !! 1158 rst {
1467 pins 1159 pins = "gpio104";
1468 funct 1160 function = "gpio";
1469 drive 1161 drive-strength = <16>;
1470 bias- 1162 bias-disable;
1471 }; 1163 };
1472 }; 1164 };
1473 1165
1474 camera2_state_on: 1166 camera2_state_on:
1475 camera_front_default: !! 1167 camera_front_default: camera-front-default {
1476 camera2_mclk: !! 1168 camera2_mclk: mclk2 {
1477 pins 1169 pins = "gpio15";
1478 funct 1170 function = "cam_mclk";
1479 drive 1171 drive-strength = <16>;
1480 bias- 1172 bias-disable;
1481 }; 1173 };
1482 1174
1483 camera2_rst: !! 1175 camera2_rst: rst {
1484 pins 1176 pins = "gpio23";
1485 funct 1177 function = "gpio";
1486 drive 1178 drive-strength = <16>;
1487 bias- 1179 bias-disable;
1488 }; 1180 };
1489 1181
1490 pwdn-pins { !! 1182 pwdn {
1491 pins 1183 pins = "gpio133";
1492 funct 1184 function = "gpio";
1493 drive 1185 drive-strength = <16>;
1494 bias- 1186 bias-disable;
1495 }; 1187 };
1496 }; 1188 };
1497 1189
1498 pcie0_state_on: pcie0 !! 1190 pcie0_state_on: pcie0-state-on {
1499 perst-pins { !! 1191 perst {
1500 pins 1192 pins = "gpio35";
1501 funct 1193 function = "gpio";
1502 drive 1194 drive-strength = <2>;
1503 bias- 1195 bias-pull-down;
1504 }; 1196 };
1505 1197
1506 clkreq-pins { !! 1198 clkreq {
1507 pins 1199 pins = "gpio36";
1508 funct 1200 function = "pci_e0";
1509 drive 1201 drive-strength = <2>;
1510 bias- 1202 bias-pull-up;
1511 }; 1203 };
1512 1204
1513 wake-pins { !! 1205 wake {
1514 pins 1206 pins = "gpio37";
1515 funct 1207 function = "gpio";
1516 drive 1208 drive-strength = <2>;
1517 bias- 1209 bias-pull-up;
1518 }; 1210 };
1519 }; 1211 };
1520 1212
1521 pcie0_state_off: pcie !! 1213 pcie0_state_off: pcie0-state-off {
1522 perst-pins { !! 1214 perst {
1523 pins 1215 pins = "gpio35";
1524 funct 1216 function = "gpio";
1525 drive 1217 drive-strength = <2>;
1526 bias- 1218 bias-pull-down;
1527 }; 1219 };
1528 1220
1529 clkreq-pins { !! 1221 clkreq {
1530 pins 1222 pins = "gpio36";
1531 funct 1223 function = "gpio";
1532 drive 1224 drive-strength = <2>;
1533 bias- 1225 bias-disable;
1534 }; 1226 };
1535 1227
1536 wake-pins { !! 1228 wake {
1537 pins 1229 pins = "gpio37";
1538 funct 1230 function = "gpio";
1539 drive 1231 drive-strength = <2>;
1540 bias- 1232 bias-disable;
1541 }; 1233 };
1542 }; 1234 };
1543 1235
1544 blsp1_uart2_default: !! 1236 blsp1_uart2_default: blsp1-uart2-default {
1545 pins = "gpio4 1237 pins = "gpio41", "gpio42", "gpio43", "gpio44";
1546 function = "b 1238 function = "blsp_uart2";
1547 drive-strengt 1239 drive-strength = <16>;
1548 bias-disable; 1240 bias-disable;
1549 }; 1241 };
1550 1242
1551 blsp1_uart2_sleep: bl !! 1243 blsp1_uart2_sleep: blsp1-uart2-sleep {
1552 pins = "gpio4 1244 pins = "gpio41", "gpio42", "gpio43", "gpio44";
1553 function = "g 1245 function = "gpio";
1554 drive-strengt 1246 drive-strength = <2>;
1555 bias-disable; 1247 bias-disable;
1556 }; 1248 };
1557 1249
1558 blsp1_i2c3_default: b !! 1250 blsp1_i2c3_default: blsp1-i2c2-default {
1559 pins = "gpio4 1251 pins = "gpio47", "gpio48";
1560 function = "b 1252 function = "blsp_i2c3";
1561 drive-strengt 1253 drive-strength = <16>;
1562 bias-disable; 1254 bias-disable;
1563 }; 1255 };
1564 1256
1565 blsp1_i2c3_sleep: bls !! 1257 blsp1_i2c3_sleep: blsp1-i2c2-sleep {
1566 pins = "gpio4 1258 pins = "gpio47", "gpio48";
1567 function = "g 1259 function = "gpio";
1568 drive-strengt 1260 drive-strength = <2>;
1569 bias-disable; 1261 bias-disable;
1570 }; 1262 };
1571 1263
1572 blsp2_uart3_4pins_def !! 1264 blsp2_uart3_4pins_default: blsp2-uart2-4pins {
1573 pins = "gpio4 1265 pins = "gpio49", "gpio50", "gpio51", "gpio52";
1574 function = "b 1266 function = "blsp_uart9";
1575 drive-strengt 1267 drive-strength = <16>;
1576 bias-disable; 1268 bias-disable;
1577 }; 1269 };
1578 1270
1579 blsp2_uart3_4pins_sle !! 1271 blsp2_uart3_4pins_sleep: blsp2-uart2-4pins-sleep {
1580 pins = "gpio4 1272 pins = "gpio49", "gpio50", "gpio51", "gpio52";
1581 function = "b 1273 function = "blsp_uart9";
1582 drive-strengt 1274 drive-strength = <2>;
1583 bias-disable; 1275 bias-disable;
1584 }; 1276 };
1585 1277
1586 blsp2_i2c3_default: b !! 1278 blsp2_i2c3_default: blsp2-i2c3 {
1587 pins = "gpio5 1279 pins = "gpio51", "gpio52";
1588 function = "b 1280 function = "blsp_i2c9";
1589 drive-strengt 1281 drive-strength = <16>;
1590 bias-disable; 1282 bias-disable;
1591 }; 1283 };
1592 1284
1593 blsp2_i2c3_sleep: bls !! 1285 blsp2_i2c3_sleep: blsp2-i2c3-sleep {
1594 pins = "gpio5 1286 pins = "gpio51", "gpio52";
1595 function = "g 1287 function = "gpio";
1596 drive-strengt 1288 drive-strength = <2>;
1597 bias-disable; 1289 bias-disable;
1598 }; 1290 };
1599 1291
1600 wcd_intr_default: wcd !! 1292 wcd_intr_default: wcd-intr-default{
1601 pins = "gpio5 1293 pins = "gpio54";
1602 function = "g 1294 function = "gpio";
1603 drive-strengt 1295 drive-strength = <2>;
1604 bias-pull-dow 1296 bias-pull-down;
>> 1297 input-enable;
1605 }; 1298 };
1606 1299
1607 blsp2_i2c1_default: b !! 1300 blsp2_i2c1_default: blsp2-i2c1 {
1608 pins = "gpio5 1301 pins = "gpio55", "gpio56";
1609 function = "b 1302 function = "blsp_i2c7";
1610 drive-strengt 1303 drive-strength = <16>;
1611 bias-disable; 1304 bias-disable;
1612 }; 1305 };
1613 1306
1614 blsp2_i2c1_sleep: bls !! 1307 blsp2_i2c1_sleep: blsp2-i2c0-sleep {
1615 pins = "gpio5 1308 pins = "gpio55", "gpio56";
1616 function = "g 1309 function = "gpio";
1617 drive-strengt 1310 drive-strength = <2>;
1618 bias-disable; 1311 bias-disable;
1619 }; 1312 };
1620 1313
1621 blsp2_i2c5_default: b !! 1314 blsp2_i2c5_default: blsp2-i2c5 {
1622 pins = "gpio6 1315 pins = "gpio60", "gpio61";
1623 function = "b 1316 function = "blsp_i2c11";
1624 drive-strengt 1317 drive-strength = <2>;
1625 bias-disable; 1318 bias-disable;
1626 }; 1319 };
1627 1320
1628 /* Sleep state for BL 1321 /* Sleep state for BLSP2_I2C5 is missing.. */
1629 1322
1630 cdc_reset_active: cdc !! 1323 cdc_reset_active: cdc-reset-active {
1631 pins = "gpio6 1324 pins = "gpio64";
1632 function = "g 1325 function = "gpio";
1633 drive-strengt 1326 drive-strength = <16>;
1634 bias-pull-dow 1327 bias-pull-down;
1635 output-high; 1328 output-high;
1636 }; 1329 };
1637 1330
1638 cdc_reset_sleep: cdc- !! 1331 cdc_reset_sleep: cdc-reset-sleep {
1639 pins = "gpio6 1332 pins = "gpio64";
1640 function = "g 1333 function = "gpio";
1641 drive-strengt 1334 drive-strength = <16>;
1642 bias-disable; 1335 bias-disable;
1643 output-low; 1336 output-low;
1644 }; 1337 };
1645 1338
1646 blsp2_spi6_default: b !! 1339 blsp2_spi6_default: blsp2-spi5-default {
1647 spi-pins { !! 1340 spi {
1648 pins 1341 pins = "gpio85", "gpio86", "gpio88";
1649 funct 1342 function = "blsp_spi12";
1650 drive 1343 drive-strength = <12>;
1651 bias- 1344 bias-disable;
1652 }; 1345 };
1653 1346
1654 cs-pins { !! 1347 cs {
1655 pins 1348 pins = "gpio87";
1656 funct 1349 function = "gpio";
1657 drive 1350 drive-strength = <16>;
1658 bias- 1351 bias-disable;
1659 outpu 1352 output-high;
1660 }; 1353 };
1661 }; 1354 };
1662 1355
1663 blsp2_spi6_sleep: bls !! 1356 blsp2_spi6_sleep: blsp2-spi5-sleep {
1664 pins = "gpio8 1357 pins = "gpio85", "gpio86", "gpio87", "gpio88";
1665 function = "g 1358 function = "gpio";
1666 drive-strengt 1359 drive-strength = <2>;
1667 bias-pull-dow 1360 bias-pull-down;
1668 }; 1361 };
1669 1362
1670 blsp2_i2c6_default: b !! 1363 blsp2_i2c6_default: blsp2-i2c6 {
1671 pins = "gpio8 1364 pins = "gpio87", "gpio88";
1672 function = "b 1365 function = "blsp_i2c12";
1673 drive-strengt 1366 drive-strength = <16>;
1674 bias-disable; 1367 bias-disable;
1675 }; 1368 };
1676 1369
1677 blsp2_i2c6_sleep: bls !! 1370 blsp2_i2c6_sleep: blsp2-i2c6-sleep {
1678 pins = "gpio8 1371 pins = "gpio87", "gpio88";
1679 function = "g 1372 function = "gpio";
1680 drive-strengt 1373 drive-strength = <2>;
1681 bias-disable; 1374 bias-disable;
1682 }; 1375 };
1683 1376
1684 pcie1_state_on: pcie1 !! 1377 pcie1_state_on: pcie1-state-on {
1685 perst-pins { !! 1378 perst {
1686 pins 1379 pins = "gpio130";
1687 funct 1380 function = "gpio";
1688 drive 1381 drive-strength = <2>;
1689 bias- 1382 bias-pull-down;
1690 }; 1383 };
1691 1384
1692 clkreq-pins { !! 1385 clkreq {
1693 pins 1386 pins = "gpio131";
1694 funct 1387 function = "pci_e1";
1695 drive 1388 drive-strength = <2>;
1696 bias- 1389 bias-pull-up;
1697 }; 1390 };
1698 1391
1699 wake-pins { !! 1392 wake {
1700 pins 1393 pins = "gpio132";
1701 funct 1394 function = "gpio";
1702 drive 1395 drive-strength = <2>;
1703 bias- 1396 bias-pull-down;
1704 }; 1397 };
1705 }; 1398 };
1706 1399
1707 pcie1_state_off: pcie !! 1400 pcie1_state_off: pcie1-state-off {
1708 /* Perst is m 1401 /* Perst is missing? */
1709 clkreq-pins { !! 1402 clkreq {
1710 pins 1403 pins = "gpio131";
1711 funct 1404 function = "gpio";
1712 drive 1405 drive-strength = <2>;
1713 bias- 1406 bias-disable;
1714 }; 1407 };
1715 1408
1716 wake-pins { !! 1409 wake {
1717 pins 1410 pins = "gpio132";
1718 funct 1411 function = "gpio";
1719 drive 1412 drive-strength = <2>;
1720 bias- 1413 bias-disable;
1721 }; 1414 };
1722 }; 1415 };
1723 1416
1724 pcie2_state_on: pcie2 !! 1417 pcie2_state_on: pcie2-state-on {
1725 perst-pins { !! 1418 perst {
1726 pins 1419 pins = "gpio114";
1727 funct 1420 function = "gpio";
1728 drive 1421 drive-strength = <2>;
1729 bias- 1422 bias-pull-down;
1730 }; 1423 };
1731 1424
1732 clkreq-pins { !! 1425 clkreq {
1733 pins 1426 pins = "gpio115";
1734 funct 1427 function = "pci_e2";
1735 drive 1428 drive-strength = <2>;
1736 bias- 1429 bias-pull-up;
1737 }; 1430 };
1738 1431
1739 wake-pins { !! 1432 wake {
1740 pins 1433 pins = "gpio116";
1741 funct 1434 function = "gpio";
1742 drive 1435 drive-strength = <2>;
1743 bias- 1436 bias-pull-down;
1744 }; 1437 };
1745 }; 1438 };
1746 1439
1747 pcie2_state_off: pcie !! 1440 pcie2_state_off: pcie2-state-off {
1748 /* Perst is m 1441 /* Perst is missing? */
1749 clkreq-pins { !! 1442 clkreq {
1750 pins 1443 pins = "gpio115";
1751 funct 1444 function = "gpio";
1752 drive 1445 drive-strength = <2>;
1753 bias- 1446 bias-disable;
1754 }; 1447 };
1755 1448
1756 wake-pins { !! 1449 wake {
1757 pins 1450 pins = "gpio116";
1758 funct 1451 function = "gpio";
1759 drive 1452 drive-strength = <2>;
1760 bias- 1453 bias-disable;
1761 }; 1454 };
1762 }; 1455 };
1763 1456
1764 sdc1_state_on: sdc1-o !! 1457 sdc1_state_on: sdc1-state-on {
1765 clk-pins { !! 1458 clk {
1766 pins 1459 pins = "sdc1_clk";
1767 bias- 1460 bias-disable;
1768 drive 1461 drive-strength = <16>;
1769 }; 1462 };
1770 1463
1771 cmd-pins { !! 1464 cmd {
1772 pins 1465 pins = "sdc1_cmd";
1773 bias- 1466 bias-pull-up;
1774 drive 1467 drive-strength = <10>;
1775 }; 1468 };
1776 1469
1777 data-pins { !! 1470 data {
1778 pins 1471 pins = "sdc1_data";
1779 bias- 1472 bias-pull-up;
1780 drive 1473 drive-strength = <10>;
1781 }; 1474 };
1782 1475
1783 rclk-pins { !! 1476 rclk {
1784 pins 1477 pins = "sdc1_rclk";
1785 bias- 1478 bias-pull-down;
1786 }; 1479 };
1787 }; 1480 };
1788 1481
1789 sdc1_state_off: sdc1- !! 1482 sdc1_state_off: sdc1-state-off {
1790 clk-pins { !! 1483 clk {
1791 pins 1484 pins = "sdc1_clk";
1792 bias- 1485 bias-disable;
1793 drive 1486 drive-strength = <2>;
1794 }; 1487 };
1795 1488
1796 cmd-pins { !! 1489 cmd {
1797 pins 1490 pins = "sdc1_cmd";
1798 bias- 1491 bias-pull-up;
1799 drive 1492 drive-strength = <2>;
1800 }; 1493 };
1801 1494
1802 data-pins { !! 1495 data {
1803 pins 1496 pins = "sdc1_data";
1804 bias- 1497 bias-pull-up;
1805 drive 1498 drive-strength = <2>;
1806 }; 1499 };
1807 1500
1808 rclk-pins { !! 1501 rclk {
1809 pins 1502 pins = "sdc1_rclk";
1810 bias- 1503 bias-pull-down;
1811 }; 1504 };
1812 }; 1505 };
1813 1506
1814 sdc2_state_on: sdc2-o !! 1507 sdc2_state_on: sdc2-clk-on {
1815 clk-pins { !! 1508 clk {
1816 pins 1509 pins = "sdc2_clk";
1817 bias- 1510 bias-disable;
1818 drive 1511 drive-strength = <16>;
1819 }; 1512 };
1820 1513
1821 cmd-pins { !! 1514 cmd {
1822 pins 1515 pins = "sdc2_cmd";
1823 bias- 1516 bias-pull-up;
1824 drive 1517 drive-strength = <10>;
1825 }; 1518 };
1826 1519
1827 data-pins { !! 1520 data {
1828 pins 1521 pins = "sdc2_data";
1829 bias- 1522 bias-pull-up;
1830 drive 1523 drive-strength = <10>;
1831 }; 1524 };
1832 }; 1525 };
1833 1526
1834 sdc2_state_off: sdc2- !! 1527 sdc2_state_off: sdc2-clk-off {
1835 clk-pins { !! 1528 clk {
1836 pins 1529 pins = "sdc2_clk";
1837 bias- 1530 bias-disable;
1838 drive 1531 drive-strength = <2>;
1839 }; 1532 };
1840 1533
1841 cmd-pins { !! 1534 cmd {
1842 pins 1535 pins = "sdc2_cmd";
1843 bias- 1536 bias-pull-up;
1844 drive 1537 drive-strength = <2>;
1845 }; 1538 };
1846 1539
1847 data-pins { !! 1540 data {
1848 pins 1541 pins = "sdc2_data";
1849 bias- 1542 bias-pull-up;
1850 drive 1543 drive-strength = <2>;
1851 }; 1544 };
1852 }; 1545 };
1853 }; 1546 };
1854 1547
1855 sram@290000 { 1548 sram@290000 {
1856 compatible = "qcom,rp 1549 compatible = "qcom,rpm-stats";
1857 reg = <0x00290000 0x1 1550 reg = <0x00290000 0x10000>;
1858 }; 1551 };
1859 1552
1860 spmi_bus: spmi@400f000 { 1553 spmi_bus: spmi@400f000 {
1861 compatible = "qcom,sp 1554 compatible = "qcom,spmi-pmic-arb";
1862 reg = <0x0400f000 0x1 1555 reg = <0x0400f000 0x1000>,
1863 <0x04400000 0x8 1556 <0x04400000 0x800000>,
1864 <0x04c00000 0x8 1557 <0x04c00000 0x800000>,
1865 <0x05800000 0x2 1558 <0x05800000 0x200000>,
1866 <0x0400a000 0x0 1559 <0x0400a000 0x002100>;
1867 reg-names = "core", " 1560 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1868 interrupt-names = "pe 1561 interrupt-names = "periph_irq";
1869 interrupts = <GIC_SPI 1562 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
1870 qcom,ee = <0>; 1563 qcom,ee = <0>;
1871 qcom,channel = <0>; 1564 qcom,channel = <0>;
1872 #address-cells = <2>; 1565 #address-cells = <2>;
1873 #size-cells = <0>; 1566 #size-cells = <0>;
1874 interrupt-controller; 1567 interrupt-controller;
1875 #interrupt-cells = <4 1568 #interrupt-cells = <4>;
1876 }; 1569 };
1877 1570
1878 bus@0 { !! 1571 agnoc@0 {
1879 power-domains = <&gcc 1572 power-domains = <&gcc AGGRE0_NOC_GDSC>;
1880 compatible = "simple- 1573 compatible = "simple-pm-bus";
1881 #address-cells = <1>; 1574 #address-cells = <1>;
1882 #size-cells = <1>; 1575 #size-cells = <1>;
1883 ranges = <0x0 0x0 0xf !! 1576 ranges;
1884 1577
1885 pcie0: pcie@600000 { 1578 pcie0: pcie@600000 {
1886 compatible = !! 1579 compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
1887 status = "dis 1580 status = "disabled";
1888 power-domains 1581 power-domains = <&gcc PCIE0_GDSC>;
1889 bus-range = < 1582 bus-range = <0x00 0xff>;
1890 num-lanes = < 1583 num-lanes = <1>;
1891 1584
1892 reg = <0x0060 1585 reg = <0x00600000 0x2000>,
1893 <0x0c00 1586 <0x0c000000 0xf1d>,
1894 <0x0c00 1587 <0x0c000f20 0xa8>,
1895 <0x0c10 1588 <0x0c100000 0x100000>;
1896 reg-names = " 1589 reg-names = "parf", "dbi", "elbi","config";
1897 1590
1898 phys = <&pcie 1591 phys = <&pciephy_0>;
1899 phy-names = " 1592 phy-names = "pciephy";
1900 1593
1901 #address-cell 1594 #address-cells = <3>;
1902 #size-cells = 1595 #size-cells = <2>;
1903 ranges = <0x0 !! 1596 ranges = <0x01000000 0x0 0x0c200000 0x0c200000 0x0 0x100000>,
1904 <0x0 !! 1597 <0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>;
1905 1598
1906 device_type = 1599 device_type = "pci";
1907 1600
1908 interrupts = 1601 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
1909 interrupt-nam 1602 interrupt-names = "msi";
1910 #interrupt-ce 1603 #interrupt-cells = <1>;
1911 interrupt-map 1604 interrupt-map-mask = <0 0 0 0x7>;
1912 interrupt-map 1605 interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1913 1606 <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1914 1607 <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1915 1608 <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1916 1609
1917 pinctrl-names 1610 pinctrl-names = "default", "sleep";
1918 pinctrl-0 = < 1611 pinctrl-0 = <&pcie0_state_on>;
1919 pinctrl-1 = < 1612 pinctrl-1 = <&pcie0_state_off>;
1920 1613
1921 linux,pci-dom 1614 linux,pci-domain = <0>;
1922 1615
1923 clocks = <&gc 1616 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
1924 <&gcc 1617 <&gcc GCC_PCIE_0_AUX_CLK>,
1925 <&gcc 1618 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1926 <&gcc 1619 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1927 <&gcc 1620 <&gcc GCC_PCIE_0_SLV_AXI_CLK>;
1928 1621
1929 clock-names = !! 1622 clock-names = "pipe",
1930 1623 "aux",
1931 1624 "cfg",
1932 1625 "bus_master",
1933 1626 "bus_slave";
1934 1627
1935 pcie@0 { <<
1936 devic <<
1937 reg = <<
1938 bus-r <<
1939 <<
1940 #addr <<
1941 #size <<
1942 range <<
1943 }; <<
1944 }; 1628 };
1945 1629
1946 pcie1: pcie@608000 { 1630 pcie1: pcie@608000 {
1947 compatible = !! 1631 compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
1948 power-domains 1632 power-domains = <&gcc PCIE1_GDSC>;
1949 bus-range = < 1633 bus-range = <0x00 0xff>;
1950 num-lanes = < 1634 num-lanes = <1>;
1951 1635
1952 status = "dis !! 1636 status = "disabled";
1953 1637
1954 reg = <0x0060 1638 reg = <0x00608000 0x2000>,
1955 <0x0d00 1639 <0x0d000000 0xf1d>,
1956 <0x0d00 1640 <0x0d000f20 0xa8>,
1957 <0x0d10 1641 <0x0d100000 0x100000>;
1958 1642
1959 reg-names = " 1643 reg-names = "parf", "dbi", "elbi","config";
1960 1644
1961 phys = <&pcie 1645 phys = <&pciephy_1>;
1962 phy-names = " 1646 phy-names = "pciephy";
1963 1647
1964 #address-cell 1648 #address-cells = <3>;
1965 #size-cells = 1649 #size-cells = <2>;
1966 ranges = <0x0 !! 1650 ranges = <0x01000000 0x0 0x0d200000 0x0d200000 0x0 0x100000>,
1967 <0x0 !! 1651 <0x02000000 0x0 0x0d300000 0x0d300000 0x0 0xd00000>;
1968 1652
1969 device_type = 1653 device_type = "pci";
1970 1654
1971 interrupts = 1655 interrupts = <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>;
1972 interrupt-nam 1656 interrupt-names = "msi";
1973 #interrupt-ce 1657 #interrupt-cells = <1>;
1974 interrupt-map 1658 interrupt-map-mask = <0 0 0 0x7>;
1975 interrupt-map 1659 interrupt-map = <0 0 0 1 &intc 0 272 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1976 1660 <0 0 0 2 &intc 0 273 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1977 1661 <0 0 0 3 &intc 0 274 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1978 1662 <0 0 0 4 &intc 0 275 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1979 1663
1980 pinctrl-names 1664 pinctrl-names = "default", "sleep";
1981 pinctrl-0 = < 1665 pinctrl-0 = <&pcie1_state_on>;
1982 pinctrl-1 = < 1666 pinctrl-1 = <&pcie1_state_off>;
1983 1667
1984 linux,pci-dom 1668 linux,pci-domain = <1>;
1985 1669
1986 clocks = <&gc 1670 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
1987 <&gcc 1671 <&gcc GCC_PCIE_1_AUX_CLK>,
1988 <&gcc 1672 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1989 <&gcc 1673 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
1990 <&gcc 1674 <&gcc GCC_PCIE_1_SLV_AXI_CLK>;
1991 1675
1992 clock-names = !! 1676 clock-names = "pipe",
1993 1677 "aux",
1994 1678 "cfg",
1995 1679 "bus_master",
1996 1680 "bus_slave";
1997 <<
1998 pcie@0 { <<
1999 devic <<
2000 reg = <<
2001 bus-r <<
2002 <<
2003 #addr <<
2004 #size <<
2005 range <<
2006 }; <<
2007 }; 1681 };
2008 1682
2009 pcie2: pcie@610000 { 1683 pcie2: pcie@610000 {
2010 compatible = !! 1684 compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
2011 power-domains 1685 power-domains = <&gcc PCIE2_GDSC>;
2012 bus-range = < 1686 bus-range = <0x00 0xff>;
2013 num-lanes = < 1687 num-lanes = <1>;
2014 status = "dis 1688 status = "disabled";
2015 reg = <0x0061 1689 reg = <0x00610000 0x2000>,
2016 <0x0e00 1690 <0x0e000000 0xf1d>,
2017 <0x0e00 1691 <0x0e000f20 0xa8>,
2018 <0x0e10 1692 <0x0e100000 0x100000>;
2019 1693
2020 reg-names = " 1694 reg-names = "parf", "dbi", "elbi","config";
2021 1695
2022 phys = <&pcie 1696 phys = <&pciephy_2>;
2023 phy-names = " 1697 phy-names = "pciephy";
2024 1698
2025 #address-cell 1699 #address-cells = <3>;
2026 #size-cells = 1700 #size-cells = <2>;
2027 ranges = <0x0 !! 1701 ranges = <0x01000000 0x0 0x0e200000 0x0e200000 0x0 0x100000>,
2028 <0x0 !! 1702 <0x02000000 0x0 0x0e300000 0x0e300000 0x0 0x1d00000>;
2029 1703
2030 device_type = 1704 device_type = "pci";
2031 1705
2032 interrupts = 1706 interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
2033 interrupt-nam 1707 interrupt-names = "msi";
2034 #interrupt-ce 1708 #interrupt-cells = <1>;
2035 interrupt-map 1709 interrupt-map-mask = <0 0 0 0x7>;
2036 interrupt-map 1710 interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2037 1711 <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2038 1712 <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2039 1713 <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2040 1714
2041 pinctrl-names 1715 pinctrl-names = "default", "sleep";
2042 pinctrl-0 = < 1716 pinctrl-0 = <&pcie2_state_on>;
2043 pinctrl-1 = < 1717 pinctrl-1 = <&pcie2_state_off>;
2044 1718
2045 linux,pci-dom 1719 linux,pci-domain = <2>;
2046 clocks = <&gc 1720 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,
2047 <&gcc 1721 <&gcc GCC_PCIE_2_AUX_CLK>,
2048 <&gcc 1722 <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
2049 <&gcc 1723 <&gcc GCC_PCIE_2_MSTR_AXI_CLK>,
2050 <&gcc 1724 <&gcc GCC_PCIE_2_SLV_AXI_CLK>;
2051 1725
2052 clock-names = !! 1726 clock-names = "pipe",
2053 1727 "aux",
2054 1728 "cfg",
2055 1729 "bus_master",
2056 1730 "bus_slave";
2057 <<
2058 pcie@0 { <<
2059 devic <<
2060 reg = <<
2061 bus-r <<
2062 <<
2063 #addr <<
2064 #size <<
2065 range <<
2066 }; <<
2067 }; 1731 };
2068 }; 1732 };
2069 1733
2070 ufshc: ufshc@624000 { 1734 ufshc: ufshc@624000 {
2071 compatible = "qcom,ms !! 1735 compatible = "qcom,ufshc";
2072 "jedec,u <<
2073 reg = <0x00624000 0x2 1736 reg = <0x00624000 0x2500>;
2074 interrupts = <GIC_SPI 1737 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
2075 1738
2076 phys = <&ufsphy>; !! 1739 phys = <&ufsphy_lane>;
2077 phy-names = "ufsphy"; 1740 phy-names = "ufsphy";
2078 1741
2079 power-domains = <&gcc 1742 power-domains = <&gcc UFS_GDSC>;
2080 1743
2081 clock-names = 1744 clock-names =
>> 1745 "core_clk_src",
2082 "core_clk", 1746 "core_clk",
2083 "bus_clk", 1747 "bus_clk",
2084 "bus_aggr_clk 1748 "bus_aggr_clk",
2085 "iface_clk", 1749 "iface_clk",
>> 1750 "core_clk_unipro_src",
2086 "core_clk_uni 1751 "core_clk_unipro",
2087 "core_clk_ice 1752 "core_clk_ice",
2088 "ref_clk", 1753 "ref_clk",
2089 "tx_lane0_syn 1754 "tx_lane0_sync_clk",
2090 "rx_lane0_syn 1755 "rx_lane0_sync_clk";
2091 clocks = 1756 clocks =
>> 1757 <&gcc UFS_AXI_CLK_SRC>,
2092 <&gcc GCC_UFS 1758 <&gcc GCC_UFS_AXI_CLK>,
2093 <&gcc GCC_SYS 1759 <&gcc GCC_SYS_NOC_UFS_AXI_CLK>,
2094 <&gcc GCC_AGG 1760 <&gcc GCC_AGGRE2_UFS_AXI_CLK>,
2095 <&gcc GCC_UFS 1761 <&gcc GCC_UFS_AHB_CLK>,
>> 1762 <&gcc UFS_ICE_CORE_CLK_SRC>,
2096 <&gcc GCC_UFS 1763 <&gcc GCC_UFS_UNIPRO_CORE_CLK>,
2097 <&gcc GCC_UFS 1764 <&gcc GCC_UFS_ICE_CORE_CLK>,
2098 <&rpmcc RPM_S 1765 <&rpmcc RPM_SMD_LN_BB_CLK>,
2099 <&gcc GCC_UFS 1766 <&gcc GCC_UFS_TX_SYMBOL_0_CLK>,
2100 <&gcc GCC_UFS 1767 <&gcc GCC_UFS_RX_SYMBOL_0_CLK>;
2101 freq-table-hz = 1768 freq-table-hz =
2102 <100000000 20 1769 <100000000 200000000>,
2103 <0 0>, 1770 <0 0>,
2104 <0 0>, 1771 <0 0>,
2105 <0 0>, 1772 <0 0>,
2106 <75000000 150 !! 1773 <0 0>,
2107 <150000000 30 1774 <150000000 300000000>,
2108 <0 0>, 1775 <0 0>,
2109 <0 0>, 1776 <0 0>,
>> 1777 <0 0>,
>> 1778 <0 0>,
2110 <0 0>; 1779 <0 0>;
2111 1780
2112 interconnects = <&a2n <<
2113 <&bim <<
2114 interconnect-names = <<
2115 <<
2116 lanes-per-direction = 1781 lanes-per-direction = <1>;
2117 #reset-cells = <1>; 1782 #reset-cells = <1>;
2118 status = "disabled"; 1783 status = "disabled";
>> 1784
>> 1785 ufs_variant {
>> 1786 compatible = "qcom,ufs_variant";
>> 1787 };
2119 }; 1788 };
2120 1789
2121 ufsphy: phy@627000 { 1790 ufsphy: phy@627000 {
2122 compatible = "qcom,ms 1791 compatible = "qcom,msm8996-qmp-ufs-phy";
2123 reg = <0x00627000 0x1 !! 1792 reg = <0x00627000 0x1c4>;
>> 1793 #address-cells = <1>;
>> 1794 #size-cells = <1>;
>> 1795 ranges;
2124 1796
2125 clocks = <&rpmcc RPM_ !! 1797 clocks = <&gcc GCC_UFS_CLKREF_CLK>;
2126 clock-names = "ref", !! 1798 clock-names = "ref";
2127 1799
2128 resets = <&ufshc 0>; 1800 resets = <&ufshc 0>;
2129 reset-names = "ufsphy 1801 reset-names = "ufsphy";
2130 <<
2131 #clock-cells = <1>; <<
2132 #phy-cells = <0>; <<
2133 <<
2134 status = "disabled"; 1802 status = "disabled";
>> 1803
>> 1804 ufsphy_lane: phy@627400 {
>> 1805 reg = <0x627400 0x12c>,
>> 1806 <0x627600 0x200>,
>> 1807 <0x627c00 0x1b4>;
>> 1808 #phy-cells = <0>;
>> 1809 };
2135 }; 1810 };
2136 1811
2137 camss: camss@a34000 { !! 1812 camss: camss@a00000 {
2138 compatible = "qcom,ms 1813 compatible = "qcom,msm8996-camss";
2139 reg = <0x00a34000 0x1 1814 reg = <0x00a34000 0x1000>,
2140 <0x00a00030 0x4 1815 <0x00a00030 0x4>,
2141 <0x00a35000 0x1 1816 <0x00a35000 0x1000>,
2142 <0x00a00038 0x4 1817 <0x00a00038 0x4>,
2143 <0x00a36000 0x1 1818 <0x00a36000 0x1000>,
2144 <0x00a00040 0x4 1819 <0x00a00040 0x4>,
2145 <0x00a30000 0x1 1820 <0x00a30000 0x100>,
2146 <0x00a30400 0x1 1821 <0x00a30400 0x100>,
2147 <0x00a30800 0x1 1822 <0x00a30800 0x100>,
2148 <0x00a30c00 0x1 1823 <0x00a30c00 0x100>,
2149 <0x00a31000 0x5 1824 <0x00a31000 0x500>,
2150 <0x00a00020 0x1 1825 <0x00a00020 0x10>,
2151 <0x00a10000 0x1 1826 <0x00a10000 0x1000>,
2152 <0x00a14000 0x1 1827 <0x00a14000 0x1000>;
2153 reg-names = "csiphy0" 1828 reg-names = "csiphy0",
2154 "csiphy0_clk_ 1829 "csiphy0_clk_mux",
2155 "csiphy1", 1830 "csiphy1",
2156 "csiphy1_clk_ 1831 "csiphy1_clk_mux",
2157 "csiphy2", 1832 "csiphy2",
2158 "csiphy2_clk_ 1833 "csiphy2_clk_mux",
2159 "csid0", 1834 "csid0",
2160 "csid1", 1835 "csid1",
2161 "csid2", 1836 "csid2",
2162 "csid3", 1837 "csid3",
2163 "ispif", 1838 "ispif",
2164 "csi_clk_mux" 1839 "csi_clk_mux",
2165 "vfe0", 1840 "vfe0",
2166 "vfe1"; 1841 "vfe1";
2167 interrupts = <GIC_SPI 1842 interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
2168 <GIC_SPI 79 I 1843 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
2169 <GIC_SPI 80 I 1844 <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>,
2170 <GIC_SPI 296 1845 <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>,
2171 <GIC_SPI 297 1846 <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>,
2172 <GIC_SPI 298 1847 <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>,
2173 <GIC_SPI 299 1848 <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>,
2174 <GIC_SPI 309 1849 <GIC_SPI 309 IRQ_TYPE_EDGE_RISING>,
2175 <GIC_SPI 314 1850 <GIC_SPI 314 IRQ_TYPE_EDGE_RISING>,
2176 <GIC_SPI 315 1851 <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>;
2177 interrupt-names = "cs 1852 interrupt-names = "csiphy0",
2178 "csiphy1", 1853 "csiphy1",
2179 "csiphy2", 1854 "csiphy2",
2180 "csid0", 1855 "csid0",
2181 "csid1", 1856 "csid1",
2182 "csid2", 1857 "csid2",
2183 "csid3", 1858 "csid3",
2184 "ispif", 1859 "ispif",
2185 "vfe0", 1860 "vfe0",
2186 "vfe1"; 1861 "vfe1";
2187 power-domains = <&mmc 1862 power-domains = <&mmcc VFE0_GDSC>,
2188 <&mmc 1863 <&mmcc VFE1_GDSC>;
2189 clocks = <&mmcc CAMSS 1864 clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
2190 <&mmcc CAMSS_ 1865 <&mmcc CAMSS_ISPIF_AHB_CLK>,
2191 <&mmcc CAMSS_ 1866 <&mmcc CAMSS_CSI0PHYTIMER_CLK>,
2192 <&mmcc CAMSS_ 1867 <&mmcc CAMSS_CSI1PHYTIMER_CLK>,
2193 <&mmcc CAMSS_ 1868 <&mmcc CAMSS_CSI2PHYTIMER_CLK>,
2194 <&mmcc CAMSS_ 1869 <&mmcc CAMSS_CSI0_AHB_CLK>,
2195 <&mmcc CAMSS_ 1870 <&mmcc CAMSS_CSI0_CLK>,
2196 <&mmcc CAMSS_ 1871 <&mmcc CAMSS_CSI0PHY_CLK>,
2197 <&mmcc CAMSS_ 1872 <&mmcc CAMSS_CSI0PIX_CLK>,
2198 <&mmcc CAMSS_ 1873 <&mmcc CAMSS_CSI0RDI_CLK>,
2199 <&mmcc CAMSS_ 1874 <&mmcc CAMSS_CSI1_AHB_CLK>,
2200 <&mmcc CAMSS_ 1875 <&mmcc CAMSS_CSI1_CLK>,
2201 <&mmcc CAMSS_ 1876 <&mmcc CAMSS_CSI1PHY_CLK>,
2202 <&mmcc CAMSS_ 1877 <&mmcc CAMSS_CSI1PIX_CLK>,
2203 <&mmcc CAMSS_ 1878 <&mmcc CAMSS_CSI1RDI_CLK>,
2204 <&mmcc CAMSS_ 1879 <&mmcc CAMSS_CSI2_AHB_CLK>,
2205 <&mmcc CAMSS_ 1880 <&mmcc CAMSS_CSI2_CLK>,
2206 <&mmcc CAMSS_ 1881 <&mmcc CAMSS_CSI2PHY_CLK>,
2207 <&mmcc CAMSS_ 1882 <&mmcc CAMSS_CSI2PIX_CLK>,
2208 <&mmcc CAMSS_ 1883 <&mmcc CAMSS_CSI2RDI_CLK>,
2209 <&mmcc CAMSS_ 1884 <&mmcc CAMSS_CSI3_AHB_CLK>,
2210 <&mmcc CAMSS_ 1885 <&mmcc CAMSS_CSI3_CLK>,
2211 <&mmcc CAMSS_ 1886 <&mmcc CAMSS_CSI3PHY_CLK>,
2212 <&mmcc CAMSS_ 1887 <&mmcc CAMSS_CSI3PIX_CLK>,
2213 <&mmcc CAMSS_ 1888 <&mmcc CAMSS_CSI3RDI_CLK>,
2214 <&mmcc CAMSS_ 1889 <&mmcc CAMSS_AHB_CLK>,
2215 <&mmcc CAMSS_ 1890 <&mmcc CAMSS_VFE0_CLK>,
2216 <&mmcc CAMSS_ 1891 <&mmcc CAMSS_CSI_VFE0_CLK>,
2217 <&mmcc CAMSS_ 1892 <&mmcc CAMSS_VFE0_AHB_CLK>,
2218 <&mmcc CAMSS_ 1893 <&mmcc CAMSS_VFE0_STREAM_CLK>,
2219 <&mmcc CAMSS_ 1894 <&mmcc CAMSS_VFE1_CLK>,
2220 <&mmcc CAMSS_ 1895 <&mmcc CAMSS_CSI_VFE1_CLK>,
2221 <&mmcc CAMSS_ 1896 <&mmcc CAMSS_VFE1_AHB_CLK>,
2222 <&mmcc CAMSS_ 1897 <&mmcc CAMSS_VFE1_STREAM_CLK>,
2223 <&mmcc CAMSS_ 1898 <&mmcc CAMSS_VFE_AHB_CLK>,
2224 <&mmcc CAMSS_ 1899 <&mmcc CAMSS_VFE_AXI_CLK>;
2225 clock-names = "top_ah 1900 clock-names = "top_ahb",
2226 "ispif_ahb", 1901 "ispif_ahb",
2227 "csiphy0_time 1902 "csiphy0_timer",
2228 "csiphy1_time 1903 "csiphy1_timer",
2229 "csiphy2_time 1904 "csiphy2_timer",
2230 "csi0_ahb", 1905 "csi0_ahb",
2231 "csi0", 1906 "csi0",
2232 "csi0_phy", 1907 "csi0_phy",
2233 "csi0_pix", 1908 "csi0_pix",
2234 "csi0_rdi", 1909 "csi0_rdi",
2235 "csi1_ahb", 1910 "csi1_ahb",
2236 "csi1", 1911 "csi1",
2237 "csi1_phy", 1912 "csi1_phy",
2238 "csi1_pix", 1913 "csi1_pix",
2239 "csi1_rdi", 1914 "csi1_rdi",
2240 "csi2_ahb", 1915 "csi2_ahb",
2241 "csi2", 1916 "csi2",
2242 "csi2_phy", 1917 "csi2_phy",
2243 "csi2_pix", 1918 "csi2_pix",
2244 "csi2_rdi", 1919 "csi2_rdi",
2245 "csi3_ahb", 1920 "csi3_ahb",
2246 "csi3", 1921 "csi3",
2247 "csi3_phy", 1922 "csi3_phy",
2248 "csi3_pix", 1923 "csi3_pix",
2249 "csi3_rdi", 1924 "csi3_rdi",
2250 "ahb", 1925 "ahb",
2251 "vfe0", 1926 "vfe0",
2252 "csi_vfe0", 1927 "csi_vfe0",
2253 "vfe0_ahb", 1928 "vfe0_ahb",
2254 "vfe0_stream" 1929 "vfe0_stream",
2255 "vfe1", 1930 "vfe1",
2256 "csi_vfe1", 1931 "csi_vfe1",
2257 "vfe1_ahb", 1932 "vfe1_ahb",
2258 "vfe1_stream" 1933 "vfe1_stream",
2259 "vfe_ahb", 1934 "vfe_ahb",
2260 "vfe_axi"; 1935 "vfe_axi";
2261 iommus = <&vfe_smmu 0 1936 iommus = <&vfe_smmu 0>,
2262 <&vfe_smmu 1 1937 <&vfe_smmu 1>,
2263 <&vfe_smmu 2 1938 <&vfe_smmu 2>,
2264 <&vfe_smmu 3 1939 <&vfe_smmu 3>;
2265 status = "disabled"; 1940 status = "disabled";
2266 ports { 1941 ports {
2267 #address-cell 1942 #address-cells = <1>;
2268 #size-cells = 1943 #size-cells = <0>;
2269 }; 1944 };
2270 }; 1945 };
2271 1946
2272 cci: cci@a0c000 { 1947 cci: cci@a0c000 {
2273 compatible = "qcom,ms 1948 compatible = "qcom,msm8996-cci";
2274 #address-cells = <1>; 1949 #address-cells = <1>;
2275 #size-cells = <0>; 1950 #size-cells = <0>;
2276 reg = <0xa0c000 0x100 1951 reg = <0xa0c000 0x1000>;
2277 interrupts = <GIC_SPI 1952 interrupts = <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>;
2278 power-domains = <&mmc 1953 power-domains = <&mmcc CAMSS_GDSC>;
2279 clocks = <&mmcc CAMSS 1954 clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
2280 <&mmcc CAMSS 1955 <&mmcc CAMSS_CCI_AHB_CLK>,
2281 <&mmcc CAMSS 1956 <&mmcc CAMSS_CCI_CLK>,
2282 <&mmcc CAMSS 1957 <&mmcc CAMSS_AHB_CLK>;
2283 clock-names = "camss_ 1958 clock-names = "camss_top_ahb",
2284 "cci_ah 1959 "cci_ahb",
2285 "cci", 1960 "cci",
2286 "camss_ 1961 "camss_ahb";
2287 assigned-clocks = <&m 1962 assigned-clocks = <&mmcc CAMSS_CCI_AHB_CLK>,
2288 <&m 1963 <&mmcc CAMSS_CCI_CLK>;
2289 assigned-clock-rates 1964 assigned-clock-rates = <80000000>, <37500000>;
2290 pinctrl-names = "defa 1965 pinctrl-names = "default";
2291 pinctrl-0 = <&cci0_de 1966 pinctrl-0 = <&cci0_default &cci1_default>;
2292 status = "disabled"; 1967 status = "disabled";
2293 1968
2294 cci_i2c0: i2c-bus@0 { 1969 cci_i2c0: i2c-bus@0 {
2295 reg = <0>; 1970 reg = <0>;
2296 clock-frequen 1971 clock-frequency = <400000>;
2297 #address-cell 1972 #address-cells = <1>;
2298 #size-cells = 1973 #size-cells = <0>;
2299 }; 1974 };
2300 1975
2301 cci_i2c1: i2c-bus@1 { 1976 cci_i2c1: i2c-bus@1 {
2302 reg = <1>; 1977 reg = <1>;
2303 clock-frequen 1978 clock-frequency = <400000>;
2304 #address-cell 1979 #address-cells = <1>;
2305 #size-cells = 1980 #size-cells = <0>;
2306 }; 1981 };
2307 }; 1982 };
2308 1983
2309 adreno_smmu: iommu@b40000 { 1984 adreno_smmu: iommu@b40000 {
2310 compatible = "qcom,ms 1985 compatible = "qcom,msm8996-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
2311 reg = <0x00b40000 0x1 1986 reg = <0x00b40000 0x10000>;
2312 1987
2313 #global-interrupts = 1988 #global-interrupts = <1>;
2314 interrupts = <GIC_SPI 1989 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
2315 <GIC_SPI 1990 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
2316 <GIC_SPI 1991 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
2317 #iommu-cells = <1>; 1992 #iommu-cells = <1>;
2318 1993
2319 clocks = <&gcc GCC_MM !! 1994 clocks = <&mmcc GPU_AHB_CLK>,
2320 <&mmcc GPU_A !! 1995 <&gcc GCC_MMSS_BIMC_GFX_CLK>;
2321 clock-names = "bus", !! 1996 clock-names = "iface", "bus";
2322 1997
2323 power-domains = <&mmc 1998 power-domains = <&mmcc GPU_GDSC>;
2324 }; 1999 };
2325 2000
2326 venus: video-codec@c00000 { 2001 venus: video-codec@c00000 {
2327 compatible = "qcom,ms 2002 compatible = "qcom,msm8996-venus";
2328 reg = <0x00c00000 0xf 2003 reg = <0x00c00000 0xff000>;
2329 interrupts = <GIC_SPI 2004 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
2330 power-domains = <&mmc 2005 power-domains = <&mmcc VENUS_GDSC>;
2331 clocks = <&mmcc VIDEO 2006 clocks = <&mmcc VIDEO_CORE_CLK>,
2332 <&mmcc VIDEO 2007 <&mmcc VIDEO_AHB_CLK>,
2333 <&mmcc VIDEO 2008 <&mmcc VIDEO_AXI_CLK>,
2334 <&mmcc VIDEO 2009 <&mmcc VIDEO_MAXI_CLK>;
2335 clock-names = "core", 2010 clock-names = "core", "iface", "bus", "mbus";
2336 interconnects = <&mno <<
2337 <&bim <<
2338 interconnect-names = <<
2339 iommus = <&venus_smmu 2011 iommus = <&venus_smmu 0x00>,
2340 <&venus_smmu 2012 <&venus_smmu 0x01>,
2341 <&venus_smmu 2013 <&venus_smmu 0x0a>,
2342 <&venus_smmu 2014 <&venus_smmu 0x07>,
2343 <&venus_smmu 2015 <&venus_smmu 0x0e>,
2344 <&venus_smmu 2016 <&venus_smmu 0x0f>,
2345 <&venus_smmu 2017 <&venus_smmu 0x08>,
2346 <&venus_smmu 2018 <&venus_smmu 0x09>,
2347 <&venus_smmu 2019 <&venus_smmu 0x0b>,
2348 <&venus_smmu 2020 <&venus_smmu 0x0c>,
2349 <&venus_smmu 2021 <&venus_smmu 0x0d>,
2350 <&venus_smmu 2022 <&venus_smmu 0x10>,
2351 <&venus_smmu 2023 <&venus_smmu 0x11>,
2352 <&venus_smmu 2024 <&venus_smmu 0x21>,
2353 <&venus_smmu 2025 <&venus_smmu 0x28>,
2354 <&venus_smmu 2026 <&venus_smmu 0x29>,
2355 <&venus_smmu 2027 <&venus_smmu 0x2b>,
2356 <&venus_smmu 2028 <&venus_smmu 0x2c>,
2357 <&venus_smmu 2029 <&venus_smmu 0x2d>,
2358 <&venus_smmu 2030 <&venus_smmu 0x31>;
2359 memory-region = <&ven !! 2031 memory-region = <&venus_region>;
2360 status = "disabled"; 2032 status = "disabled";
2361 2033
2362 video-decoder { 2034 video-decoder {
2363 compatible = 2035 compatible = "venus-decoder";
2364 clocks = <&mm 2036 clocks = <&mmcc VIDEO_SUBCORE0_CLK>;
2365 clock-names = 2037 clock-names = "core";
2366 power-domains 2038 power-domains = <&mmcc VENUS_CORE0_GDSC>;
2367 }; 2039 };
2368 2040
2369 video-encoder { 2041 video-encoder {
2370 compatible = 2042 compatible = "venus-encoder";
2371 clocks = <&mm 2043 clocks = <&mmcc VIDEO_SUBCORE1_CLK>;
2372 clock-names = 2044 clock-names = "core";
2373 power-domains 2045 power-domains = <&mmcc VENUS_CORE1_GDSC>;
2374 }; 2046 };
2375 }; 2047 };
2376 2048
2377 mdp_smmu: iommu@d00000 { 2049 mdp_smmu: iommu@d00000 {
2378 compatible = "qcom,ms 2050 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2379 reg = <0x00d00000 0x1 2051 reg = <0x00d00000 0x10000>;
2380 2052
2381 #global-interrupts = 2053 #global-interrupts = <1>;
2382 interrupts = <GIC_SPI 2054 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
2383 <GIC_SPI 2055 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
2384 <GIC_SPI 2056 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
2385 #iommu-cells = <1>; 2057 #iommu-cells = <1>;
2386 clocks = <&mmcc SMMU_ !! 2058 clocks = <&mmcc SMMU_MDP_AHB_CLK>,
2387 <&mmcc SMMU_ !! 2059 <&mmcc SMMU_MDP_AXI_CLK>;
2388 clock-names = "bus", !! 2060 clock-names = "iface", "bus";
2389 2061
2390 power-domains = <&mmc 2062 power-domains = <&mmcc MDSS_GDSC>;
2391 }; 2063 };
2392 2064
2393 venus_smmu: iommu@d40000 { 2065 venus_smmu: iommu@d40000 {
2394 compatible = "qcom,ms 2066 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2395 reg = <0x00d40000 0x2 2067 reg = <0x00d40000 0x20000>;
2396 #global-interrupts = 2068 #global-interrupts = <1>;
2397 interrupts = <GIC_SPI 2069 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>,
2398 <GIC_SPI 2070 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
2399 <GIC_SPI 2071 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
2400 <GIC_SPI 2072 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
2401 <GIC_SPI 2073 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
2402 <GIC_SPI 2074 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
2403 <GIC_SPI 2075 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
2404 <GIC_SPI 2076 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
2405 power-domains = <&mmc 2077 power-domains = <&mmcc MMAGIC_VIDEO_GDSC>;
2406 clocks = <&mmcc SMMU_ !! 2078 clocks = <&mmcc SMMU_VIDEO_AHB_CLK>,
2407 <&mmcc SMMU_ !! 2079 <&mmcc SMMU_VIDEO_AXI_CLK>;
2408 clock-names = "bus", !! 2080 clock-names = "iface", "bus";
2409 #iommu-cells = <1>; 2081 #iommu-cells = <1>;
2410 status = "okay"; 2082 status = "okay";
2411 }; 2083 };
2412 2084
2413 vfe_smmu: iommu@da0000 { 2085 vfe_smmu: iommu@da0000 {
2414 compatible = "qcom,ms 2086 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2415 reg = <0x00da0000 0x1 2087 reg = <0x00da0000 0x10000>;
2416 2088
2417 #global-interrupts = 2089 #global-interrupts = <1>;
2418 interrupts = <GIC_SPI 2090 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
2419 <GIC_SPI 2091 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
2420 <GIC_SPI 2092 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
2421 power-domains = <&mmc 2093 power-domains = <&mmcc MMAGIC_CAMSS_GDSC>;
2422 clocks = <&mmcc SMMU_ !! 2094 clocks = <&mmcc SMMU_VFE_AHB_CLK>,
2423 <&mmcc SMMU_ !! 2095 <&mmcc SMMU_VFE_AXI_CLK>;
2424 clock-names = "bus", !! 2096 clock-names = "iface",
>> 2097 "bus";
2425 #iommu-cells = <1>; 2098 #iommu-cells = <1>;
2426 }; 2099 };
2427 2100
2428 lpass_q6_smmu: iommu@1600000 2101 lpass_q6_smmu: iommu@1600000 {
2429 compatible = "qcom,ms 2102 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2430 reg = <0x01600000 0x2 2103 reg = <0x01600000 0x20000>;
2431 #iommu-cells = <1>; 2104 #iommu-cells = <1>;
2432 power-domains = <&gcc 2105 power-domains = <&gcc HLOS1_VOTE_LPASS_CORE_GDSC>;
2433 2106
2434 #global-interrupts = 2107 #global-interrupts = <1>;
2435 interrupts = <GIC_SPI 2108 interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
2436 <GIC_SPI 226 2109 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,
2437 <GIC_SPI 393 2110 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
2438 <GIC_SPI 394 2111 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
2439 <GIC_SPI 395 2112 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
2440 <GIC_SPI 396 2113 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
2441 <GIC_SPI 397 2114 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
2442 <GIC_SPI 398 2115 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
2443 <GIC_SPI 399 2116 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
2444 <GIC_SPI 400 2117 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
2445 <GIC_SPI 401 2118 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
2446 <GIC_SPI 402 2119 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
2447 <GIC_SPI 403 2120 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>;
2448 2121
2449 clocks = <&gcc GCC_HL !! 2122 clocks = <&gcc GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK>,
2450 <&gcc GCC_HL !! 2123 <&gcc GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>;
2451 clock-names = "bus", !! 2124 clock-names = "iface", "bus";
2452 }; <<
2453 <<
2454 slpi_pil: remoteproc@1c00000 <<
2455 compatible = "qcom,ms <<
2456 reg = <0x01c00000 0x4 <<
2457 <<
2458 interrupts-extended = <<
2459 <<
2460 <<
2461 <<
2462 <<
2463 interrupt-names = "wd <<
2464 "fa <<
2465 "re <<
2466 "ha <<
2467 "st <<
2468 <<
2469 clocks = <&xo_board>; <<
2470 clock-names = "xo"; <<
2471 <<
2472 memory-region = <&slp <<
2473 <<
2474 qcom,smem-states = <& <<
2475 qcom,smem-state-names <<
2476 <<
2477 power-domains = <&rpm <<
2478 power-domain-names = <<
2479 <<
2480 status = "disabled"; <<
2481 <<
2482 glink-edge { <<
2483 interrupts = <<
2484 label = "dsps <<
2485 qcom,remote-p <<
2486 mboxes = <&ap <<
2487 }; <<
2488 <<
2489 smd-edge { <<
2490 interrupts = <<
2491 <<
2492 label = "dsps <<
2493 mboxes = <&ap <<
2494 qcom,smd-edge <<
2495 qcom,remote-p <<
2496 }; <<
2497 }; <<
2498 <<
2499 mss_pil: remoteproc@2080000 { <<
2500 compatible = "qcom,ms <<
2501 reg = <0x2080000 0x10 <<
2502 <0x2180000 0x02 <<
2503 reg-names = "qdsp6", <<
2504 <<
2505 interrupts-extended = <<
2506 <<
2507 <<
2508 <<
2509 <<
2510 <<
2511 interrupt-names = "wd <<
2512 "ha <<
2513 "sh <<
2514 <<
2515 clocks = <&gcc GCC_MS <<
2516 <&gcc GCC_MS <<
2517 <&gcc GCC_BO <<
2518 <&xo_board>, <<
2519 <&gcc GCC_MS <<
2520 <&gcc GCC_MS <<
2521 <&gcc GCC_MS <<
2522 <&rpmcc RPM_ <<
2523 clock-names = "iface" <<
2524 "bus", <<
2525 "mem", <<
2526 "xo", <<
2527 "gpll0_ <<
2528 "snoc_a <<
2529 "mnoc_a <<
2530 "qdss"; <<
2531 <<
2532 resets = <&gcc GCC_MS <<
2533 reset-names = "mss_re <<
2534 <<
2535 power-domains = <&rpm <<
2536 <&rpm <<
2537 power-domain-names = <<
2538 <<
2539 qcom,smem-states = <& <<
2540 qcom,smem-state-names <<
2541 <<
2542 qcom,halt-regs = <&tc <<
2543 <<
2544 status = "disabled"; <<
2545 <<
2546 mba { <<
2547 memory-region <<
2548 }; <<
2549 <<
2550 mpss { <<
2551 memory-region <<
2552 }; <<
2553 <<
2554 metadata { <<
2555 memory-region <<
2556 }; <<
2557 <<
2558 glink-edge { <<
2559 interrupts = <<
2560 label = "mode <<
2561 qcom,remote-p <<
2562 mboxes = <&ap <<
2563 }; <<
2564 <<
2565 smd-edge { <<
2566 interrupts = <<
2567 <<
2568 label = "mpss <<
2569 mboxes = <&ap <<
2570 qcom,smd-edge <<
2571 qcom,remote-p <<
2572 }; <<
2573 }; 2125 };
2574 2126
2575 stm@3002000 { 2127 stm@3002000 {
2576 compatible = "arm,cor 2128 compatible = "arm,coresight-stm", "arm,primecell";
2577 reg = <0x3002000 0x10 2129 reg = <0x3002000 0x1000>,
2578 <0x8280000 0x18 2130 <0x8280000 0x180000>;
2579 reg-names = "stm-base 2131 reg-names = "stm-base", "stm-stimulus-base";
2580 2132
2581 clocks = <&rpmcc RPM_ 2133 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2582 clock-names = "apb_pc 2134 clock-names = "apb_pclk", "atclk";
2583 2135
2584 out-ports { 2136 out-ports {
2585 port { 2137 port {
2586 stm_o 2138 stm_out: endpoint {
2587 2139 remote-endpoint =
2588 2140 <&funnel0_in>;
2589 }; 2141 };
2590 }; 2142 };
2591 }; 2143 };
2592 }; 2144 };
2593 2145
2594 tpiu@3020000 { 2146 tpiu@3020000 {
2595 compatible = "arm,cor 2147 compatible = "arm,coresight-tpiu", "arm,primecell";
2596 reg = <0x3020000 0x10 2148 reg = <0x3020000 0x1000>;
2597 2149
2598 clocks = <&rpmcc RPM_ 2150 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2599 clock-names = "apb_pc 2151 clock-names = "apb_pclk", "atclk";
2600 2152
2601 in-ports { 2153 in-ports {
2602 port { 2154 port {
2603 tpiu_ 2155 tpiu_in: endpoint {
2604 2156 remote-endpoint =
2605 2157 <&replicator_out1>;
2606 }; 2158 };
2607 }; 2159 };
2608 }; 2160 };
2609 }; 2161 };
2610 2162
2611 funnel@3021000 { 2163 funnel@3021000 {
2612 compatible = "arm,cor 2164 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2613 reg = <0x3021000 0x10 2165 reg = <0x3021000 0x1000>;
2614 2166
2615 clocks = <&rpmcc RPM_ 2167 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2616 clock-names = "apb_pc 2168 clock-names = "apb_pclk", "atclk";
2617 2169
2618 in-ports { 2170 in-ports {
2619 #address-cell 2171 #address-cells = <1>;
2620 #size-cells = 2172 #size-cells = <0>;
2621 2173
2622 port@7 { 2174 port@7 {
2623 reg = 2175 reg = <7>;
2624 funne 2176 funnel0_in: endpoint {
2625 2177 remote-endpoint =
2626 2178 <&stm_out>;
2627 }; 2179 };
2628 }; 2180 };
2629 }; 2181 };
2630 2182
2631 out-ports { 2183 out-ports {
2632 port { 2184 port {
2633 funne 2185 funnel0_out: endpoint {
2634 2186 remote-endpoint =
2635 2187 <&merge_funnel_in0>;
2636 }; 2188 };
2637 }; 2189 };
2638 }; 2190 };
2639 }; 2191 };
2640 2192
2641 funnel@3022000 { 2193 funnel@3022000 {
2642 compatible = "arm,cor 2194 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2643 reg = <0x3022000 0x10 2195 reg = <0x3022000 0x1000>;
2644 2196
2645 clocks = <&rpmcc RPM_ 2197 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2646 clock-names = "apb_pc 2198 clock-names = "apb_pclk", "atclk";
2647 2199
2648 in-ports { 2200 in-ports {
2649 #address-cell 2201 #address-cells = <1>;
2650 #size-cells = 2202 #size-cells = <0>;
2651 2203
2652 port@6 { 2204 port@6 {
2653 reg = 2205 reg = <6>;
2654 funne 2206 funnel1_in: endpoint {
2655 2207 remote-endpoint =
2656 2208 <&apss_merge_funnel_out>;
2657 }; 2209 };
2658 }; 2210 };
2659 }; 2211 };
2660 2212
2661 out-ports { 2213 out-ports {
2662 port { 2214 port {
2663 funne 2215 funnel1_out: endpoint {
2664 2216 remote-endpoint =
2665 2217 <&merge_funnel_in1>;
2666 }; 2218 };
2667 }; 2219 };
2668 }; 2220 };
2669 }; 2221 };
2670 2222
2671 funnel@3023000 { 2223 funnel@3023000 {
2672 compatible = "arm,cor 2224 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2673 reg = <0x3023000 0x10 2225 reg = <0x3023000 0x1000>;
2674 2226
2675 clocks = <&rpmcc RPM_ 2227 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2676 clock-names = "apb_pc 2228 clock-names = "apb_pclk", "atclk";
2677 2229
2678 in-ports { <<
2679 port { <<
2680 funne <<
2681 <<
2682 <<
2683 }; <<
2684 }; <<
2685 }; <<
2686 2230
2687 out-ports { 2231 out-ports {
2688 port { 2232 port {
2689 funne 2233 funnel2_out: endpoint {
2690 2234 remote-endpoint =
2691 2235 <&merge_funnel_in2>;
2692 }; 2236 };
2693 }; 2237 };
2694 }; 2238 };
2695 }; 2239 };
2696 2240
2697 funnel@3025000 { 2241 funnel@3025000 {
2698 compatible = "arm,cor 2242 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2699 reg = <0x3025000 0x10 2243 reg = <0x3025000 0x1000>;
2700 2244
2701 clocks = <&rpmcc RPM_ 2245 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2702 clock-names = "apb_pc 2246 clock-names = "apb_pclk", "atclk";
2703 2247
2704 in-ports { 2248 in-ports {
2705 #address-cell 2249 #address-cells = <1>;
2706 #size-cells = 2250 #size-cells = <0>;
2707 2251
2708 port@0 { 2252 port@0 {
2709 reg = 2253 reg = <0>;
2710 merge 2254 merge_funnel_in0: endpoint {
2711 2255 remote-endpoint =
2712 2256 <&funnel0_out>;
2713 }; 2257 };
2714 }; 2258 };
2715 2259
2716 port@1 { 2260 port@1 {
2717 reg = 2261 reg = <1>;
2718 merge 2262 merge_funnel_in1: endpoint {
2719 2263 remote-endpoint =
2720 2264 <&funnel1_out>;
2721 }; 2265 };
2722 }; 2266 };
2723 2267
2724 port@2 { 2268 port@2 {
2725 reg = 2269 reg = <2>;
2726 merge 2270 merge_funnel_in2: endpoint {
2727 2271 remote-endpoint =
2728 2272 <&funnel2_out>;
2729 }; 2273 };
2730 }; 2274 };
2731 }; 2275 };
2732 2276
2733 out-ports { 2277 out-ports {
2734 port { 2278 port {
2735 merge 2279 merge_funnel_out: endpoint {
2736 2280 remote-endpoint =
2737 2281 <&etf_in>;
2738 }; 2282 };
2739 }; 2283 };
2740 }; 2284 };
2741 }; 2285 };
2742 2286
2743 replicator@3026000 { 2287 replicator@3026000 {
2744 compatible = "arm,cor 2288 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2745 reg = <0x3026000 0x10 2289 reg = <0x3026000 0x1000>;
2746 2290
2747 clocks = <&rpmcc RPM_ 2291 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2748 clock-names = "apb_pc 2292 clock-names = "apb_pclk", "atclk";
2749 2293
2750 in-ports { 2294 in-ports {
2751 port { 2295 port {
2752 repli 2296 replicator_in: endpoint {
2753 2297 remote-endpoint =
2754 2298 <&etf_out>;
2755 }; 2299 };
2756 }; 2300 };
2757 }; 2301 };
2758 2302
2759 out-ports { 2303 out-ports {
2760 #address-cell 2304 #address-cells = <1>;
2761 #size-cells = 2305 #size-cells = <0>;
2762 2306
2763 port@0 { 2307 port@0 {
2764 reg = 2308 reg = <0>;
2765 repli 2309 replicator_out0: endpoint {
2766 2310 remote-endpoint =
2767 2311 <&etr_in>;
2768 }; 2312 };
2769 }; 2313 };
2770 2314
2771 port@1 { 2315 port@1 {
2772 reg = 2316 reg = <1>;
2773 repli 2317 replicator_out1: endpoint {
2774 2318 remote-endpoint =
2775 2319 <&tpiu_in>;
2776 }; 2320 };
2777 }; 2321 };
2778 }; 2322 };
2779 }; 2323 };
2780 2324
2781 etf@3027000 { 2325 etf@3027000 {
2782 compatible = "arm,cor 2326 compatible = "arm,coresight-tmc", "arm,primecell";
2783 reg = <0x3027000 0x10 2327 reg = <0x3027000 0x1000>;
2784 2328
2785 clocks = <&rpmcc RPM_ 2329 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2786 clock-names = "apb_pc 2330 clock-names = "apb_pclk", "atclk";
2787 2331
2788 in-ports { 2332 in-ports {
2789 port { 2333 port {
2790 etf_i 2334 etf_in: endpoint {
2791 2335 remote-endpoint =
2792 2336 <&merge_funnel_out>;
2793 }; 2337 };
2794 }; 2338 };
2795 }; 2339 };
2796 2340
2797 out-ports { 2341 out-ports {
2798 port { 2342 port {
2799 etf_o 2343 etf_out: endpoint {
2800 2344 remote-endpoint =
2801 2345 <&replicator_in>;
2802 }; 2346 };
2803 }; 2347 };
2804 }; 2348 };
2805 }; 2349 };
2806 2350
2807 etr@3028000 { 2351 etr@3028000 {
2808 compatible = "arm,cor 2352 compatible = "arm,coresight-tmc", "arm,primecell";
2809 reg = <0x3028000 0x10 2353 reg = <0x3028000 0x1000>;
2810 2354
2811 clocks = <&rpmcc RPM_ 2355 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2812 clock-names = "apb_pc 2356 clock-names = "apb_pclk", "atclk";
2813 arm,scatter-gather; 2357 arm,scatter-gather;
2814 2358
2815 in-ports { 2359 in-ports {
2816 port { 2360 port {
2817 etr_i 2361 etr_in: endpoint {
2818 2362 remote-endpoint =
2819 2363 <&replicator_out0>;
2820 }; 2364 };
2821 }; 2365 };
2822 }; 2366 };
2823 }; 2367 };
2824 2368
2825 debug@3810000 { 2369 debug@3810000 {
2826 compatible = "arm,cor 2370 compatible = "arm,coresight-cpu-debug", "arm,primecell";
2827 reg = <0x3810000 0x10 2371 reg = <0x3810000 0x1000>;
2828 2372
2829 clocks = <&rpmcc RPM_ 2373 clocks = <&rpmcc RPM_QDSS_CLK>;
2830 clock-names = "apb_pc 2374 clock-names = "apb_pclk";
2831 2375
2832 cpu = <&CPU0>; 2376 cpu = <&CPU0>;
2833 }; 2377 };
2834 2378
2835 etm@3840000 { 2379 etm@3840000 {
2836 compatible = "arm,cor 2380 compatible = "arm,coresight-etm4x", "arm,primecell";
2837 reg = <0x3840000 0x10 2381 reg = <0x3840000 0x1000>;
2838 2382
2839 clocks = <&rpmcc RPM_ 2383 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2840 clock-names = "apb_pc 2384 clock-names = "apb_pclk", "atclk";
2841 2385
2842 cpu = <&CPU0>; 2386 cpu = <&CPU0>;
2843 2387
2844 out-ports { 2388 out-ports {
2845 port { 2389 port {
2846 etm0_ 2390 etm0_out: endpoint {
2847 2391 remote-endpoint =
2848 2392 <&apss_funnel0_in0>;
2849 }; 2393 };
2850 }; 2394 };
2851 }; 2395 };
2852 }; 2396 };
2853 2397
2854 debug@3910000 { 2398 debug@3910000 {
2855 compatible = "arm,cor 2399 compatible = "arm,coresight-cpu-debug", "arm,primecell";
2856 reg = <0x3910000 0x10 2400 reg = <0x3910000 0x1000>;
2857 2401
2858 clocks = <&rpmcc RPM_ 2402 clocks = <&rpmcc RPM_QDSS_CLK>;
2859 clock-names = "apb_pc 2403 clock-names = "apb_pclk";
2860 2404
2861 cpu = <&CPU1>; 2405 cpu = <&CPU1>;
2862 }; 2406 };
2863 2407
2864 etm@3940000 { 2408 etm@3940000 {
2865 compatible = "arm,cor 2409 compatible = "arm,coresight-etm4x", "arm,primecell";
2866 reg = <0x3940000 0x10 2410 reg = <0x3940000 0x1000>;
2867 2411
2868 clocks = <&rpmcc RPM_ 2412 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2869 clock-names = "apb_pc 2413 clock-names = "apb_pclk", "atclk";
2870 2414
2871 cpu = <&CPU1>; 2415 cpu = <&CPU1>;
2872 2416
2873 out-ports { 2417 out-ports {
2874 port { 2418 port {
2875 etm1_ 2419 etm1_out: endpoint {
2876 2420 remote-endpoint =
2877 2421 <&apss_funnel0_in1>;
2878 }; 2422 };
2879 }; 2423 };
2880 }; 2424 };
2881 }; 2425 };
2882 2426
2883 funnel@39b0000 { /* APSS Funn 2427 funnel@39b0000 { /* APSS Funnel 0 */
2884 compatible = "arm,cor 2428 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2885 reg = <0x39b0000 0x10 2429 reg = <0x39b0000 0x1000>;
2886 2430
2887 clocks = <&rpmcc RPM_ 2431 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2888 clock-names = "apb_pc 2432 clock-names = "apb_pclk", "atclk";
2889 2433
2890 in-ports { 2434 in-ports {
2891 #address-cell 2435 #address-cells = <1>;
2892 #size-cells = 2436 #size-cells = <0>;
2893 2437
2894 port@0 { 2438 port@0 {
2895 reg = 2439 reg = <0>;
2896 apss_ 2440 apss_funnel0_in0: endpoint {
2897 2441 remote-endpoint = <&etm0_out>;
2898 }; 2442 };
2899 }; 2443 };
2900 2444
2901 port@1 { 2445 port@1 {
2902 reg = 2446 reg = <1>;
2903 apss_ 2447 apss_funnel0_in1: endpoint {
2904 2448 remote-endpoint = <&etm1_out>;
2905 }; 2449 };
2906 }; 2450 };
2907 }; 2451 };
2908 2452
2909 out-ports { 2453 out-ports {
2910 port { 2454 port {
2911 apss_ 2455 apss_funnel0_out: endpoint {
2912 2456 remote-endpoint =
2913 2457 <&apss_merge_funnel_in0>;
2914 }; 2458 };
2915 }; 2459 };
2916 }; 2460 };
2917 }; 2461 };
2918 2462
2919 debug@3a10000 { 2463 debug@3a10000 {
2920 compatible = "arm,cor 2464 compatible = "arm,coresight-cpu-debug", "arm,primecell";
2921 reg = <0x3a10000 0x10 2465 reg = <0x3a10000 0x1000>;
2922 2466
2923 clocks = <&rpmcc RPM_ 2467 clocks = <&rpmcc RPM_QDSS_CLK>;
2924 clock-names = "apb_pc 2468 clock-names = "apb_pclk";
2925 2469
2926 cpu = <&CPU2>; 2470 cpu = <&CPU2>;
2927 }; 2471 };
2928 2472
2929 etm@3a40000 { 2473 etm@3a40000 {
2930 compatible = "arm,cor 2474 compatible = "arm,coresight-etm4x", "arm,primecell";
2931 reg = <0x3a40000 0x10 2475 reg = <0x3a40000 0x1000>;
2932 2476
2933 clocks = <&rpmcc RPM_ 2477 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2934 clock-names = "apb_pc 2478 clock-names = "apb_pclk", "atclk";
2935 2479
2936 cpu = <&CPU2>; 2480 cpu = <&CPU2>;
2937 2481
2938 out-ports { 2482 out-ports {
2939 port { 2483 port {
2940 etm2_ 2484 etm2_out: endpoint {
2941 2485 remote-endpoint =
2942 2486 <&apss_funnel1_in0>;
2943 }; 2487 };
2944 }; 2488 };
2945 }; 2489 };
2946 }; 2490 };
2947 2491
2948 debug@3b10000 { 2492 debug@3b10000 {
2949 compatible = "arm,cor 2493 compatible = "arm,coresight-cpu-debug", "arm,primecell";
2950 reg = <0x3b10000 0x10 2494 reg = <0x3b10000 0x1000>;
2951 2495
2952 clocks = <&rpmcc RPM_ 2496 clocks = <&rpmcc RPM_QDSS_CLK>;
2953 clock-names = "apb_pc 2497 clock-names = "apb_pclk";
2954 2498
2955 cpu = <&CPU3>; 2499 cpu = <&CPU3>;
2956 }; 2500 };
2957 2501
2958 etm@3b40000 { 2502 etm@3b40000 {
2959 compatible = "arm,cor 2503 compatible = "arm,coresight-etm4x", "arm,primecell";
2960 reg = <0x3b40000 0x10 2504 reg = <0x3b40000 0x1000>;
2961 2505
2962 clocks = <&rpmcc RPM_ 2506 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2963 clock-names = "apb_pc 2507 clock-names = "apb_pclk", "atclk";
2964 2508
2965 cpu = <&CPU3>; 2509 cpu = <&CPU3>;
2966 2510
2967 out-ports { 2511 out-ports {
2968 port { 2512 port {
2969 etm3_ 2513 etm3_out: endpoint {
2970 2514 remote-endpoint =
2971 2515 <&apss_funnel1_in1>;
2972 }; 2516 };
2973 }; 2517 };
2974 }; 2518 };
2975 }; 2519 };
2976 2520
2977 funnel@3bb0000 { /* APSS Funn 2521 funnel@3bb0000 { /* APSS Funnel 1 */
2978 compatible = "arm,cor 2522 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2979 reg = <0x3bb0000 0x10 2523 reg = <0x3bb0000 0x1000>;
2980 2524
2981 clocks = <&rpmcc RPM_ 2525 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2982 clock-names = "apb_pc 2526 clock-names = "apb_pclk", "atclk";
2983 2527
2984 in-ports { 2528 in-ports {
2985 #address-cell 2529 #address-cells = <1>;
2986 #size-cells = 2530 #size-cells = <0>;
2987 2531
2988 port@0 { 2532 port@0 {
2989 reg = 2533 reg = <0>;
2990 apss_ 2534 apss_funnel1_in0: endpoint {
2991 2535 remote-endpoint = <&etm2_out>;
2992 }; 2536 };
2993 }; 2537 };
2994 2538
2995 port@1 { 2539 port@1 {
2996 reg = 2540 reg = <1>;
2997 apss_ 2541 apss_funnel1_in1: endpoint {
2998 2542 remote-endpoint = <&etm3_out>;
2999 }; 2543 };
3000 }; 2544 };
3001 }; 2545 };
3002 2546
3003 out-ports { 2547 out-ports {
3004 port { 2548 port {
3005 apss_ 2549 apss_funnel1_out: endpoint {
3006 2550 remote-endpoint =
3007 2551 <&apss_merge_funnel_in1>;
3008 }; 2552 };
3009 }; 2553 };
3010 }; 2554 };
3011 }; 2555 };
3012 2556
3013 funnel@3bc0000 { 2557 funnel@3bc0000 {
3014 compatible = "arm,cor 2558 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3015 reg = <0x3bc0000 0x10 2559 reg = <0x3bc0000 0x1000>;
3016 2560
3017 clocks = <&rpmcc RPM_ 2561 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
3018 clock-names = "apb_pc 2562 clock-names = "apb_pclk", "atclk";
3019 2563
3020 in-ports { 2564 in-ports {
3021 #address-cell 2565 #address-cells = <1>;
3022 #size-cells = 2566 #size-cells = <0>;
3023 2567
3024 port@0 { 2568 port@0 {
3025 reg = 2569 reg = <0>;
3026 apss_ 2570 apss_merge_funnel_in0: endpoint {
3027 2571 remote-endpoint =
3028 2572 <&apss_funnel0_out>;
3029 }; 2573 };
3030 }; 2574 };
3031 2575
3032 port@1 { 2576 port@1 {
3033 reg = 2577 reg = <1>;
3034 apss_ 2578 apss_merge_funnel_in1: endpoint {
3035 2579 remote-endpoint =
3036 2580 <&apss_funnel1_out>;
3037 }; 2581 };
3038 }; 2582 };
3039 }; 2583 };
3040 2584
3041 out-ports { 2585 out-ports {
3042 port { 2586 port {
3043 apss_ 2587 apss_merge_funnel_out: endpoint {
3044 2588 remote-endpoint =
3045 2589 <&funnel1_in>;
3046 }; 2590 };
3047 }; 2591 };
3048 }; 2592 };
3049 }; 2593 };
3050 2594
3051 kryocc: clock-controller@6400 2595 kryocc: clock-controller@6400000 {
3052 compatible = "qcom,ms 2596 compatible = "qcom,msm8996-apcc";
3053 reg = <0x06400000 0x9 2597 reg = <0x06400000 0x90000>;
3054 2598
3055 clock-names = "xo", " !! 2599 clock-names = "xo";
3056 clocks = <&rpmcc RPM_ !! 2600 clocks = <&rpmcc RPM_SMD_BB_CLK1>;
3057 2601
3058 #clock-cells = <1>; 2602 #clock-cells = <1>;
3059 }; 2603 };
3060 2604
3061 usb3: usb@6af8800 { 2605 usb3: usb@6af8800 {
3062 compatible = "qcom,ms 2606 compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
3063 reg = <0x06af8800 0x4 2607 reg = <0x06af8800 0x400>;
3064 #address-cells = <1>; 2608 #address-cells = <1>;
3065 #size-cells = <1>; 2609 #size-cells = <1>;
3066 ranges; 2610 ranges;
3067 2611
3068 interrupts = <GIC_SPI 2612 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
3069 <GIC_SPI 2613 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
3070 interrupt-names = "hs 2614 interrupt-names = "hs_phy_irq", "ss_phy_irq";
3071 2615
3072 clocks = <&gcc GCC_SY 2616 clocks = <&gcc GCC_SYS_NOC_USB3_AXI_CLK>,
3073 <&gcc GCC_US !! 2617 <&gcc GCC_USB30_MASTER_CLK>,
3074 <&gcc GCC_AG !! 2618 <&gcc GCC_AGGRE2_USB3_AXI_CLK>,
3075 <&gcc GCC_US !! 2619 <&gcc GCC_USB30_MOCK_UTMI_CLK>,
3076 <&gcc GCC_US !! 2620 <&gcc GCC_USB30_SLEEP_CLK>,
3077 clock-names = "cfg_no !! 2621 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
3078 "core", <<
3079 "iface" <<
3080 "sleep" <<
3081 "mock_u <<
3082 2622
3083 assigned-clocks = <&g 2623 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
3084 <&g 2624 <&gcc GCC_USB30_MASTER_CLK>;
3085 assigned-clock-rates 2625 assigned-clock-rates = <19200000>, <120000000>;
3086 2626
3087 interconnects = <&a2n <<
3088 <&bim <<
3089 interconnect-names = <<
3090 <<
3091 power-domains = <&gcc 2627 power-domains = <&gcc USB30_GDSC>;
3092 status = "disabled"; 2628 status = "disabled";
3093 2629
3094 usb3_dwc3: usb@6a0000 !! 2630 usb3_dwc3: dwc3@6a00000 {
3095 compatible = 2631 compatible = "snps,dwc3";
3096 reg = <0x06a0 2632 reg = <0x06a00000 0xcc00>;
3097 interrupts = !! 2633 interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>;
3098 phys = <&hsus !! 2634 phys = <&hsusb_phy1>, <&ssusb_phy_0>;
3099 phy-names = " 2635 phy-names = "usb2-phy", "usb3-phy";
3100 snps,hird-thr <<
3101 snps,dis_u2_s 2636 snps,dis_u2_susphy_quirk;
3102 snps,dis_enbl 2637 snps,dis_enblslpm_quirk;
3103 snps,is-utmi- <<
3104 snps,parkmode <<
3105 tx-fifo-resiz <<
3106 }; 2638 };
3107 }; 2639 };
3108 2640
3109 usb3phy: phy@7410000 { 2641 usb3phy: phy@7410000 {
3110 compatible = "qcom,ms 2642 compatible = "qcom,msm8996-qmp-usb3-phy";
3111 reg = <0x07410000 0x1 !! 2643 reg = <0x07410000 0x1c4>;
>> 2644 #address-cells = <1>;
>> 2645 #size-cells = <1>;
>> 2646 ranges;
3112 2647
3113 clocks = <&gcc GCC_US 2648 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
3114 <&gcc GCC_US !! 2649 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
3115 <&gcc GCC_US !! 2650 <&gcc GCC_USB3_CLKREF_CLK>;
3116 <&gcc GCC_US !! 2651 clock-names = "aux", "cfg_ahb", "ref";
3117 clock-names = "aux", <<
3118 "ref", <<
3119 "cfg_ah <<
3120 "pipe"; <<
3121 clock-output-names = <<
3122 #clock-cells = <0>; <<
3123 #phy-cells = <0>; <<
3124 2652
3125 resets = <&gcc GCC_US 2653 resets = <&gcc GCC_USB3_PHY_BCR>,
3126 <&gcc GCC_US !! 2654 <&gcc GCC_USB3PHY_PHY_BCR>;
3127 reset-names = "phy", !! 2655 reset-names = "phy", "common";
3128 "phy_ph <<
3129 <<
3130 status = "disabled"; 2656 status = "disabled";
>> 2657
>> 2658 ssusb_phy_0: phy@7410200 {
>> 2659 reg = <0x07410200 0x200>,
>> 2660 <0x07410400 0x130>,
>> 2661 <0x07410600 0x1a8>;
>> 2662 #phy-cells = <0>;
>> 2663
>> 2664 #clock-cells = <0>;
>> 2665 clock-output-names = "usb3_phy_pipe_clk_src";
>> 2666 clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
>> 2667 clock-names = "pipe0";
>> 2668 };
3131 }; 2669 };
3132 2670
3133 hsusb_phy1: phy@7411000 { 2671 hsusb_phy1: phy@7411000 {
3134 compatible = "qcom,ms 2672 compatible = "qcom,msm8996-qusb2-phy";
3135 reg = <0x07411000 0x1 2673 reg = <0x07411000 0x180>;
3136 #phy-cells = <0>; 2674 #phy-cells = <0>;
3137 2675
3138 clocks = <&gcc GCC_US 2676 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
3139 <&gcc GCC_RX1 2677 <&gcc GCC_RX1_USB2_CLKREF_CLK>;
3140 clock-names = "cfg_ah 2678 clock-names = "cfg_ahb", "ref";
3141 2679
3142 resets = <&gcc GCC_QU 2680 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
3143 nvmem-cells = <&qusb2 2681 nvmem-cells = <&qusb2p_hstx_trim>;
3144 status = "disabled"; 2682 status = "disabled";
3145 }; 2683 };
3146 2684
3147 hsusb_phy2: phy@7412000 { 2685 hsusb_phy2: phy@7412000 {
3148 compatible = "qcom,ms 2686 compatible = "qcom,msm8996-qusb2-phy";
3149 reg = <0x07412000 0x1 2687 reg = <0x07412000 0x180>;
3150 #phy-cells = <0>; 2688 #phy-cells = <0>;
3151 2689
3152 clocks = <&gcc GCC_US 2690 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
3153 <&gcc GCC_RX2 2691 <&gcc GCC_RX2_USB2_CLKREF_CLK>;
3154 clock-names = "cfg_ah 2692 clock-names = "cfg_ahb", "ref";
3155 2693
3156 resets = <&gcc GCC_QU 2694 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
3157 nvmem-cells = <&qusb2 2695 nvmem-cells = <&qusb2s_hstx_trim>;
3158 status = "disabled"; 2696 status = "disabled";
3159 }; 2697 };
3160 2698
3161 sdhc1: mmc@7464900 { !! 2699 sdhc1: sdhci@7464900 {
3162 compatible = "qcom,ms 2700 compatible = "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4";
3163 reg = <0x07464900 0x1 2701 reg = <0x07464900 0x11c>, <0x07464000 0x800>;
3164 reg-names = "hc", "co !! 2702 reg-names = "hc_mem", "core_mem";
3165 2703
3166 interrupts = <GIC_SPI 2704 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
3167 <GIC_ 2705 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
3168 interrupt-names = "hc 2706 interrupt-names = "hc_irq", "pwr_irq";
3169 2707
3170 clock-names = "iface" 2708 clock-names = "iface", "core", "xo";
3171 clocks = <&gcc GCC_SD 2709 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
3172 <&gcc GCC_SDC 2710 <&gcc GCC_SDCC1_APPS_CLK>,
3173 <&rpmcc RPM_S !! 2711 <&rpmcc RPM_SMD_BB_CLK1>;
3174 resets = <&gcc GCC_SD <<
3175 2712
3176 pinctrl-names = "defa 2713 pinctrl-names = "default", "sleep";
3177 pinctrl-0 = <&sdc1_st 2714 pinctrl-0 = <&sdc1_state_on>;
3178 pinctrl-1 = <&sdc1_st 2715 pinctrl-1 = <&sdc1_state_off>;
3179 2716
3180 bus-width = <8>; 2717 bus-width = <8>;
3181 non-removable; 2718 non-removable;
3182 status = "disabled"; 2719 status = "disabled";
3183 }; 2720 };
3184 2721
3185 sdhc2: mmc@74a4900 { !! 2722 sdhc2: sdhci@74a4900 {
3186 compatible = "qcom,ms 2723 compatible = "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4";
3187 reg = <0x074a4900 0x3 2724 reg = <0x074a4900 0x314>, <0x074a4000 0x800>;
3188 reg-names = "hc", "co !! 2725 reg-names = "hc_mem", "core_mem";
3189 2726
3190 interrupts = <GIC_SPI 2727 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
3191 <GIC_SP 2728 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
3192 interrupt-names = "hc 2729 interrupt-names = "hc_irq", "pwr_irq";
3193 2730
3194 clock-names = "iface" 2731 clock-names = "iface", "core", "xo";
3195 clocks = <&gcc GCC_SD 2732 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
3196 <&gcc GCC_SDC 2733 <&gcc GCC_SDCC2_APPS_CLK>,
3197 <&rpmcc RPM_S !! 2734 <&rpmcc RPM_SMD_BB_CLK1>;
3198 resets = <&gcc GCC_SD <<
3199 2735
3200 pinctrl-names = "defa 2736 pinctrl-names = "default", "sleep";
3201 pinctrl-0 = <&sdc2_st 2737 pinctrl-0 = <&sdc2_state_on>;
3202 pinctrl-1 = <&sdc2_st 2738 pinctrl-1 = <&sdc2_state_off>;
3203 2739
3204 bus-width = <4>; 2740 bus-width = <4>;
3205 status = "disabled"; 2741 status = "disabled";
3206 }; 2742 };
3207 2743
3208 blsp1_dma: dma-controller@754 2744 blsp1_dma: dma-controller@7544000 {
3209 compatible = "qcom,ba 2745 compatible = "qcom,bam-v1.7.0";
3210 reg = <0x07544000 0x2 2746 reg = <0x07544000 0x2b000>;
3211 interrupts = <GIC_SPI 2747 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
3212 clocks = <&gcc GCC_BL 2748 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
3213 clock-names = "bam_cl 2749 clock-names = "bam_clk";
3214 qcom,controlled-remot 2750 qcom,controlled-remotely;
3215 #dma-cells = <1>; 2751 #dma-cells = <1>;
3216 qcom,ee = <0>; 2752 qcom,ee = <0>;
3217 }; 2753 };
3218 2754
3219 blsp1_uart2: serial@7570000 { 2755 blsp1_uart2: serial@7570000 {
3220 compatible = "qcom,ms 2756 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
3221 reg = <0x07570000 0x1 2757 reg = <0x07570000 0x1000>;
3222 interrupts = <GIC_SPI 2758 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
3223 clocks = <&gcc GCC_BL 2759 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
3224 <&gcc GCC_BL 2760 <&gcc GCC_BLSP1_AHB_CLK>;
3225 clock-names = "core", 2761 clock-names = "core", "iface";
3226 pinctrl-names = "defa 2762 pinctrl-names = "default", "sleep";
3227 pinctrl-0 = <&blsp1_u 2763 pinctrl-0 = <&blsp1_uart2_default>;
3228 pinctrl-1 = <&blsp1_u 2764 pinctrl-1 = <&blsp1_uart2_sleep>;
3229 dmas = <&blsp1_dma 2> 2765 dmas = <&blsp1_dma 2>, <&blsp1_dma 3>;
3230 dma-names = "tx", "rx 2766 dma-names = "tx", "rx";
3231 status = "disabled"; 2767 status = "disabled";
3232 }; 2768 };
3233 2769
3234 blsp1_spi1: spi@7575000 { 2770 blsp1_spi1: spi@7575000 {
3235 compatible = "qcom,sp 2771 compatible = "qcom,spi-qup-v2.2.1";
3236 reg = <0x07575000 0x6 2772 reg = <0x07575000 0x600>;
3237 interrupts = <GIC_SPI 2773 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
3238 clocks = <&gcc GCC_BL 2774 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
3239 <&gcc GCC_BL 2775 <&gcc GCC_BLSP1_AHB_CLK>;
3240 clock-names = "core", 2776 clock-names = "core", "iface";
3241 pinctrl-names = "defa 2777 pinctrl-names = "default", "sleep";
3242 pinctrl-0 = <&blsp1_s 2778 pinctrl-0 = <&blsp1_spi1_default>;
3243 pinctrl-1 = <&blsp1_s 2779 pinctrl-1 = <&blsp1_spi1_sleep>;
3244 dmas = <&blsp1_dma 12 2780 dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
3245 dma-names = "tx", "rx 2781 dma-names = "tx", "rx";
3246 #address-cells = <1>; 2782 #address-cells = <1>;
3247 #size-cells = <0>; 2783 #size-cells = <0>;
3248 status = "disabled"; 2784 status = "disabled";
3249 }; 2785 };
3250 2786
3251 blsp1_i2c3: i2c@7577000 { 2787 blsp1_i2c3: i2c@7577000 {
3252 compatible = "qcom,i2 2788 compatible = "qcom,i2c-qup-v2.2.1";
3253 reg = <0x07577000 0x1 2789 reg = <0x07577000 0x1000>;
3254 interrupts = <GIC_SPI 2790 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
3255 clocks = <&gcc GCC_BL !! 2791 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
3256 <&gcc GCC_BL !! 2792 <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
3257 clock-names = "core", !! 2793 clock-names = "iface", "core";
3258 pinctrl-names = "defa 2794 pinctrl-names = "default", "sleep";
3259 pinctrl-0 = <&blsp1_i 2795 pinctrl-0 = <&blsp1_i2c3_default>;
3260 pinctrl-1 = <&blsp1_i 2796 pinctrl-1 = <&blsp1_i2c3_sleep>;
3261 dmas = <&blsp1_dma 16 2797 dmas = <&blsp1_dma 16>, <&blsp1_dma 17>;
3262 dma-names = "tx", "rx 2798 dma-names = "tx", "rx";
3263 #address-cells = <1>; 2799 #address-cells = <1>;
3264 #size-cells = <0>; 2800 #size-cells = <0>;
3265 status = "disabled"; 2801 status = "disabled";
3266 }; 2802 };
3267 2803
3268 blsp1_i2c6: i2c@757a000 { <<
3269 compatible = "qcom,i2 <<
3270 reg = <0x757a000 0x10 <<
3271 interrupts = <GIC_SPI <<
3272 clocks = <&gcc GCC_BL <<
3273 <&gcc GCC_BL <<
3274 clock-names = "core", <<
3275 pinctrl-names = "defa <<
3276 pinctrl-0 = <&blsp1_i <<
3277 pinctrl-1 = <&blsp1_i <<
3278 dmas = <&blsp1_dma 22 <<
3279 dma-names = "tx", "rx <<
3280 #address-cells = <1>; <<
3281 #size-cells = <0>; <<
3282 status = "disabled"; <<
3283 }; <<
3284 <<
3285 blsp2_dma: dma-controller@758 2804 blsp2_dma: dma-controller@7584000 {
3286 compatible = "qcom,ba 2805 compatible = "qcom,bam-v1.7.0";
3287 reg = <0x07584000 0x2 2806 reg = <0x07584000 0x2b000>;
3288 interrupts = <GIC_SPI 2807 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
3289 clocks = <&gcc GCC_BL 2808 clocks = <&gcc GCC_BLSP2_AHB_CLK>;
3290 clock-names = "bam_cl 2809 clock-names = "bam_clk";
3291 qcom,controlled-remot 2810 qcom,controlled-remotely;
3292 #dma-cells = <1>; 2811 #dma-cells = <1>;
3293 qcom,ee = <0>; 2812 qcom,ee = <0>;
3294 }; 2813 };
3295 2814
3296 blsp2_uart2: serial@75b0000 { 2815 blsp2_uart2: serial@75b0000 {
3297 compatible = "qcom,ms 2816 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
3298 reg = <0x075b0000 0x1 2817 reg = <0x075b0000 0x1000>;
3299 interrupts = <GIC_SPI 2818 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
3300 clocks = <&gcc GCC_BL 2819 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
3301 <&gcc GCC_BL 2820 <&gcc GCC_BLSP2_AHB_CLK>;
3302 clock-names = "core", 2821 clock-names = "core", "iface";
3303 status = "disabled"; 2822 status = "disabled";
3304 }; 2823 };
3305 2824
3306 blsp2_uart3: serial@75b1000 { 2825 blsp2_uart3: serial@75b1000 {
3307 compatible = "qcom,ms 2826 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
3308 reg = <0x075b1000 0x1 2827 reg = <0x075b1000 0x1000>;
3309 interrupts = <GIC_SPI 2828 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
3310 clocks = <&gcc GCC_BL 2829 clocks = <&gcc GCC_BLSP2_UART3_APPS_CLK>,
3311 <&gcc GCC_BL 2830 <&gcc GCC_BLSP2_AHB_CLK>;
3312 clock-names = "core", 2831 clock-names = "core", "iface";
3313 status = "disabled"; 2832 status = "disabled";
3314 }; 2833 };
3315 2834
3316 blsp2_i2c1: i2c@75b5000 { 2835 blsp2_i2c1: i2c@75b5000 {
3317 compatible = "qcom,i2 2836 compatible = "qcom,i2c-qup-v2.2.1";
3318 reg = <0x075b5000 0x1 2837 reg = <0x075b5000 0x1000>;
3319 interrupts = <GIC_SPI 2838 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
3320 clocks = <&gcc GCC_BL !! 2839 clocks = <&gcc GCC_BLSP2_AHB_CLK>,
3321 <&gcc GCC_BL !! 2840 <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>;
3322 clock-names = "core", !! 2841 clock-names = "iface", "core";
3323 pinctrl-names = "defa 2842 pinctrl-names = "default", "sleep";
3324 pinctrl-0 = <&blsp2_i 2843 pinctrl-0 = <&blsp2_i2c1_default>;
3325 pinctrl-1 = <&blsp2_i 2844 pinctrl-1 = <&blsp2_i2c1_sleep>;
3326 dmas = <&blsp2_dma 12 2845 dmas = <&blsp2_dma 12>, <&blsp2_dma 13>;
3327 dma-names = "tx", "rx 2846 dma-names = "tx", "rx";
3328 #address-cells = <1>; 2847 #address-cells = <1>;
3329 #size-cells = <0>; 2848 #size-cells = <0>;
3330 status = "disabled"; 2849 status = "disabled";
3331 }; 2850 };
3332 2851
3333 blsp2_i2c2: i2c@75b6000 { 2852 blsp2_i2c2: i2c@75b6000 {
3334 compatible = "qcom,i2 2853 compatible = "qcom,i2c-qup-v2.2.1";
3335 reg = <0x075b6000 0x1 2854 reg = <0x075b6000 0x1000>;
3336 interrupts = <GIC_SPI 2855 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
3337 clocks = <&gcc GCC_BL !! 2856 clocks = <&gcc GCC_BLSP2_AHB_CLK>,
3338 <&gcc GCC_BL !! 2857 <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>;
3339 clock-names = "core", !! 2858 clock-names = "iface", "core";
3340 pinctrl-names = "defa 2859 pinctrl-names = "default", "sleep";
3341 pinctrl-0 = <&blsp2_i 2860 pinctrl-0 = <&blsp2_i2c2_default>;
3342 pinctrl-1 = <&blsp2_i 2861 pinctrl-1 = <&blsp2_i2c2_sleep>;
3343 dmas = <&blsp2_dma 14 2862 dmas = <&blsp2_dma 14>, <&blsp2_dma 15>;
3344 dma-names = "tx", "rx 2863 dma-names = "tx", "rx";
3345 #address-cells = <1>; 2864 #address-cells = <1>;
3346 #size-cells = <0>; 2865 #size-cells = <0>;
3347 status = "disabled"; 2866 status = "disabled";
3348 }; 2867 };
3349 2868
3350 blsp2_i2c3: i2c@75b7000 { 2869 blsp2_i2c3: i2c@75b7000 {
3351 compatible = "qcom,i2 2870 compatible = "qcom,i2c-qup-v2.2.1";
3352 reg = <0x075b7000 0x1 2871 reg = <0x075b7000 0x1000>;
3353 interrupts = <GIC_SPI 2872 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
3354 clocks = <&gcc GCC_BL !! 2873 clocks = <&gcc GCC_BLSP2_AHB_CLK>,
3355 <&gcc GCC_BL !! 2874 <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>;
3356 clock-names = "core", !! 2875 clock-names = "iface", "core";
3357 clock-frequency = <40 2876 clock-frequency = <400000>;
3358 pinctrl-names = "defa 2877 pinctrl-names = "default", "sleep";
3359 pinctrl-0 = <&blsp2_i 2878 pinctrl-0 = <&blsp2_i2c3_default>;
3360 pinctrl-1 = <&blsp2_i 2879 pinctrl-1 = <&blsp2_i2c3_sleep>;
3361 dmas = <&blsp2_dma 16 2880 dmas = <&blsp2_dma 16>, <&blsp2_dma 17>;
3362 dma-names = "tx", "rx 2881 dma-names = "tx", "rx";
3363 #address-cells = <1>; 2882 #address-cells = <1>;
3364 #size-cells = <0>; 2883 #size-cells = <0>;
3365 status = "disabled"; 2884 status = "disabled";
3366 }; 2885 };
3367 2886
3368 blsp2_i2c5: i2c@75b9000 { 2887 blsp2_i2c5: i2c@75b9000 {
3369 compatible = "qcom,i2 2888 compatible = "qcom,i2c-qup-v2.2.1";
3370 reg = <0x75b9000 0x10 2889 reg = <0x75b9000 0x1000>;
3371 interrupts = <GIC_SPI 2890 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
3372 clocks = <&gcc GCC_BL !! 2891 clocks = <&gcc GCC_BLSP2_AHB_CLK>,
3373 <&gcc GCC_BL !! 2892 <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>;
3374 clock-names = "core", !! 2893 clock-names = "iface", "core";
3375 pinctrl-names = "defa 2894 pinctrl-names = "default";
3376 pinctrl-0 = <&blsp2_i 2895 pinctrl-0 = <&blsp2_i2c5_default>;
3377 dmas = <&blsp2_dma 20 2896 dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
3378 dma-names = "tx", "rx 2897 dma-names = "tx", "rx";
3379 #address-cells = <1>; 2898 #address-cells = <1>;
3380 #size-cells = <0>; 2899 #size-cells = <0>;
3381 status = "disabled"; 2900 status = "disabled";
3382 }; 2901 };
3383 2902
3384 blsp2_i2c6: i2c@75ba000 { 2903 blsp2_i2c6: i2c@75ba000 {
3385 compatible = "qcom,i2 2904 compatible = "qcom,i2c-qup-v2.2.1";
3386 reg = <0x75ba000 0x10 2905 reg = <0x75ba000 0x1000>;
3387 interrupts = <GIC_SPI 2906 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
3388 clocks = <&gcc GCC_BL !! 2907 clocks = <&gcc GCC_BLSP2_AHB_CLK>,
3389 <&gcc GCC_BL !! 2908 <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>;
3390 clock-names = "core", !! 2909 clock-names = "iface", "core";
3391 pinctrl-names = "defa 2910 pinctrl-names = "default", "sleep";
3392 pinctrl-0 = <&blsp2_i 2911 pinctrl-0 = <&blsp2_i2c6_default>;
3393 pinctrl-1 = <&blsp2_i 2912 pinctrl-1 = <&blsp2_i2c6_sleep>;
3394 dmas = <&blsp2_dma 22 2913 dmas = <&blsp2_dma 22>, <&blsp2_dma 23>;
3395 dma-names = "tx", "rx 2914 dma-names = "tx", "rx";
3396 #address-cells = <1>; 2915 #address-cells = <1>;
3397 #size-cells = <0>; 2916 #size-cells = <0>;
3398 status = "disabled"; 2917 status = "disabled";
3399 }; 2918 };
3400 2919
3401 blsp2_spi6: spi@75ba000 { !! 2920 blsp2_spi6: spi@75ba000{
3402 compatible = "qcom,sp 2921 compatible = "qcom,spi-qup-v2.2.1";
3403 reg = <0x075ba000 0x6 2922 reg = <0x075ba000 0x600>;
3404 interrupts = <GIC_SPI 2923 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
3405 clocks = <&gcc GCC_BL 2924 clocks = <&gcc GCC_BLSP2_QUP6_SPI_APPS_CLK>,
3406 <&gcc GCC_BL 2925 <&gcc GCC_BLSP2_AHB_CLK>;
3407 clock-names = "core", 2926 clock-names = "core", "iface";
3408 pinctrl-names = "defa 2927 pinctrl-names = "default", "sleep";
3409 pinctrl-0 = <&blsp2_s 2928 pinctrl-0 = <&blsp2_spi6_default>;
3410 pinctrl-1 = <&blsp2_s 2929 pinctrl-1 = <&blsp2_spi6_sleep>;
3411 dmas = <&blsp2_dma 22 2930 dmas = <&blsp2_dma 22>, <&blsp2_dma 23>;
3412 dma-names = "tx", "rx 2931 dma-names = "tx", "rx";
3413 #address-cells = <1>; 2932 #address-cells = <1>;
3414 #size-cells = <0>; 2933 #size-cells = <0>;
3415 status = "disabled"; 2934 status = "disabled";
3416 }; 2935 };
3417 2936
3418 usb2: usb@76f8800 { 2937 usb2: usb@76f8800 {
3419 compatible = "qcom,ms 2938 compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
3420 reg = <0x076f8800 0x4 2939 reg = <0x076f8800 0x400>;
3421 #address-cells = <1>; 2940 #address-cells = <1>;
3422 #size-cells = <1>; 2941 #size-cells = <1>;
3423 ranges; 2942 ranges;
3424 2943
3425 interrupts = <GIC_SPI <<
3426 <GIC_SPI <<
3427 <GIC_SPI <<
3428 interrupt-names = "pw <<
3429 "qu <<
3430 "hs <<
3431 <<
3432 clocks = <&gcc GCC_PE 2944 clocks = <&gcc GCC_PERIPH_NOC_USB20_AHB_CLK>,
3433 <&gcc GCC_USB 2945 <&gcc GCC_USB20_MASTER_CLK>,
3434 <&gcc GCC_USB 2946 <&gcc GCC_USB20_MOCK_UTMI_CLK>,
3435 <&gcc GCC_USB 2947 <&gcc GCC_USB20_SLEEP_CLK>,
3436 <&gcc GCC_USB 2948 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
3437 clock-names = "cfg_no <<
3438 "core", <<
3439 "iface" <<
3440 "sleep" <<
3441 "mock_u <<
3442 2949
3443 assigned-clocks = <&g 2950 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
3444 <&g 2951 <&gcc GCC_USB20_MASTER_CLK>;
3445 assigned-clock-rates 2952 assigned-clock-rates = <19200000>, <60000000>;
3446 2953
3447 power-domains = <&gcc 2954 power-domains = <&gcc USB30_GDSC>;
3448 qcom,select-utmi-as-p 2955 qcom,select-utmi-as-pipe-clk;
3449 status = "disabled"; 2956 status = "disabled";
3450 2957
3451 usb2_dwc3: usb@760000 !! 2958 dwc3@7600000 {
3452 compatible = 2959 compatible = "snps,dwc3";
3453 reg = <0x0760 2960 reg = <0x07600000 0xcc00>;
3454 interrupts = !! 2961 interrupts = <0 138 IRQ_TYPE_LEVEL_HIGH>;
3455 phys = <&hsus 2962 phys = <&hsusb_phy2>;
3456 phy-names = " 2963 phy-names = "usb2-phy";
3457 maximum-speed 2964 maximum-speed = "high-speed";
3458 snps,dis_u2_s 2965 snps,dis_u2_susphy_quirk;
3459 snps,dis_enbl 2966 snps,dis_enblslpm_quirk;
3460 }; 2967 };
3461 }; 2968 };
3462 2969
3463 slimbam: dma-controller@91840 2970 slimbam: dma-controller@9184000 {
3464 compatible = "qcom,ba 2971 compatible = "qcom,bam-v1.7.0";
3465 qcom,controlled-remot 2972 qcom,controlled-remotely;
3466 reg = <0x09184000 0x3 2973 reg = <0x09184000 0x32000>;
3467 num-channels = <31>; !! 2974 num-channels = <31>;
3468 interrupts = <GIC_SPI !! 2975 interrupts = <0 164 IRQ_TYPE_LEVEL_HIGH>;
3469 #dma-cells = <1>; 2976 #dma-cells = <1>;
3470 qcom,ee = <1>; 2977 qcom,ee = <1>;
3471 qcom,num-ees = <2>; 2978 qcom,num-ees = <2>;
3472 }; 2979 };
3473 2980
3474 slim_msm: slim-ngd@91c0000 { !! 2981 slim_msm: slim@91c0000 {
3475 compatible = "qcom,sl 2982 compatible = "qcom,slim-ngd-v1.5.0";
3476 reg = <0x091c0000 0x2 !! 2983 reg = <0x091c0000 0x2C000>;
3477 interrupts = <GIC_SPI !! 2984 reg-names = "ctrl";
3478 dmas = <&slimbam 3>, !! 2985 interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>;
3479 dma-names = "rx", "tx !! 2986 dmas = <&slimbam 3>, <&slimbam 4>,
>> 2987 <&slimbam 5>, <&slimbam 6>;
>> 2988 dma-names = "rx", "tx", "tx2", "rx2";
3480 #address-cells = <1>; 2989 #address-cells = <1>;
3481 #size-cells = <0>; 2990 #size-cells = <0>;
>> 2991 ngd@1 {
>> 2992 reg = <1>;
>> 2993 #address-cells = <1>;
>> 2994 #size-cells = <1>;
3482 2995
3483 status = "disabled"; !! 2996 tasha_ifd: tas-ifd {
>> 2997 compatible = "slim217,1a0";
>> 2998 reg = <0 0>;
>> 2999 };
>> 3000
>> 3001 wcd9335: codec@1{
>> 3002 pinctrl-0 = <&cdc_reset_active &wcd_intr_default>;
>> 3003 pinctrl-names = "default";
>> 3004
>> 3005 compatible = "slim217,1a0";
>> 3006 reg = <1 0>;
>> 3007
>> 3008 interrupt-parent = <&tlmm>;
>> 3009 interrupts = <54 IRQ_TYPE_LEVEL_HIGH>,
>> 3010 <53 IRQ_TYPE_LEVEL_HIGH>;
>> 3011 interrupt-names = "intr1", "intr2";
>> 3012 interrupt-controller;
>> 3013 #interrupt-cells = <1>;
>> 3014 reset-gpios = <&tlmm 64 0>;
>> 3015
>> 3016 slim-ifc-dev = <&tasha_ifd>;
>> 3017
>> 3018 #sound-dai-cells = <1>;
>> 3019 };
>> 3020 };
3484 }; 3021 };
3485 3022
3486 adsp_pil: remoteproc@9300000 3023 adsp_pil: remoteproc@9300000 {
3487 compatible = "qcom,ms 3024 compatible = "qcom,msm8996-adsp-pil";
3488 reg = <0x09300000 0x8 3025 reg = <0x09300000 0x80000>;
3489 3026
3490 interrupts-extended = 3027 interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>,
3491 !! 3028 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
3492 !! 3029 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
3493 !! 3030 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
3494 !! 3031 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
3495 interrupt-names = "wd 3032 interrupt-names = "wdog", "fatal", "ready",
3496 "ha 3033 "handover", "stop-ack";
3497 3034
3498 clocks = <&rpmcc RPM_ !! 3035 clocks = <&rpmcc RPM_SMD_BB_CLK1>;
3499 clock-names = "xo"; 3036 clock-names = "xo";
3500 3037
3501 memory-region = <&ads !! 3038 memory-region = <&adsp_region>;
3502 3039
3503 qcom,smem-states = <& !! 3040 qcom,smem-states = <&smp2p_adsp_out 0>;
3504 qcom,smem-state-names 3041 qcom,smem-state-names = "stop";
3505 3042
3506 power-domains = <&rpm 3043 power-domains = <&rpmpd MSM8996_VDDCX>;
3507 power-domain-names = 3044 power-domain-names = "cx";
3508 3045
3509 status = "disabled"; 3046 status = "disabled";
3510 3047
3511 glink-edge { <<
3512 interrupts = <<
3513 label = "lpas <<
3514 qcom,remote-p <<
3515 mboxes = <&ap <<
3516 }; <<
3517 <<
3518 <<
3519 smd-edge { 3048 smd-edge {
3520 interrupts = 3049 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
3521 3050
3522 label = "lpas 3051 label = "lpass";
3523 mboxes = <&ap 3052 mboxes = <&apcs_glb 8>;
3524 qcom,smd-edge 3053 qcom,smd-edge = <1>;
3525 qcom,remote-p 3054 qcom,remote-pid = <2>;
3526 !! 3055 #address-cells = <1>;
>> 3056 #size-cells = <0>;
3527 apr { 3057 apr {
3528 power 3058 power-domains = <&gcc HLOS1_VOTE_LPASS_ADSP_GDSC>;
3529 compa 3059 compatible = "qcom,apr-v2";
3530 qcom, 3060 qcom,smd-channels = "apr_audio_svc";
3531 qcom, 3061 qcom,domain = <APR_DOMAIN_ADSP>;
3532 #addr 3062 #address-cells = <1>;
3533 #size 3063 #size-cells = <0>;
3534 3064
3535 servi !! 3065 q6core {
3536 3066 reg = <APR_SVC_ADSP_CORE>;
3537 3067 compatible = "qcom,q6core";
3538 }; 3068 };
3539 3069
3540 q6afe !! 3070 q6afe: q6afe {
3541 3071 compatible = "qcom,q6afe";
3542 3072 reg = <APR_SVC_AFE>;
3543 3073 q6afedai: dais {
3544 3074 compatible = "qcom,q6afe-dais";
3545 3075 #address-cells = <1>;
3546 3076 #size-cells = <0>;
3547 3077 #sound-dai-cells = <1>;
3548 !! 3078 hdmi@1 {
3549 3079 reg = <1>;
3550 3080 };
3551 3081 };
3552 }; 3082 };
3553 3083
3554 q6asm !! 3084 q6asm: q6asm {
3555 3085 compatible = "qcom,q6asm";
3556 3086 reg = <APR_SVC_ASM>;
3557 3087 q6asmdai: dais {
3558 3088 compatible = "qcom,q6asm-dais";
3559 3089 #address-cells = <1>;
3560 3090 #size-cells = <0>;
3561 3091 #sound-dai-cells = <1>;
3562 3092 iommus = <&lpass_q6_smmu 1>;
3563 3093 };
3564 }; 3094 };
3565 3095
3566 q6adm !! 3096 q6adm: q6adm {
3567 3097 compatible = "qcom,q6adm";
3568 3098 reg = <APR_SVC_ADM>;
3569 3099 q6routing: routing {
3570 3100 compatible = "qcom,q6adm-routing";
3571 3101 #sound-dai-cells = <0>;
3572 3102 };
3573 }; 3103 };
3574 }; 3104 };
3575 3105
3576 fastrpc { <<
3577 compa <<
3578 qcom, <<
3579 label <<
3580 qcom, <<
3581 #addr <<
3582 #size <<
3583 <<
3584 cb@5 <<
3585 <<
3586 <<
3587 <<
3588 }; <<
3589 <<
3590 cb@6 <<
3591 <<
3592 <<
3593 <<
3594 }; <<
3595 <<
3596 cb@7 <<
3597 <<
3598 <<
3599 <<
3600 }; <<
3601 <<
3602 cb@8 <<
3603 <<
3604 <<
3605 <<
3606 }; <<
3607 <<
3608 cb@9 <<
3609 <<
3610 <<
3611 <<
3612 }; <<
3613 <<
3614 cb@10 <<
3615 <<
3616 <<
3617 <<
3618 }; <<
3619 <<
3620 cb@11 <<
3621 <<
3622 <<
3623 <<
3624 }; <<
3625 <<
3626 cb@12 <<
3627 <<
3628 <<
3629 <<
3630 }; <<
3631 }; <<
3632 }; 3106 };
3633 }; 3107 };
3634 3108
3635 apcs_glb: mailbox@9820000 { 3109 apcs_glb: mailbox@9820000 {
3636 compatible = "qcom,ms 3110 compatible = "qcom,msm8996-apcs-hmss-global";
3637 reg = <0x09820000 0x1 3111 reg = <0x09820000 0x1000>;
3638 3112
3639 #mbox-cells = <1>; 3113 #mbox-cells = <1>;
3640 #clock-cells = <0>; <<
3641 }; 3114 };
3642 3115
3643 timer@9840000 { 3116 timer@9840000 {
3644 #address-cells = <1>; 3117 #address-cells = <1>;
3645 #size-cells = <1>; 3118 #size-cells = <1>;
3646 ranges; 3119 ranges;
3647 compatible = "arm,arm 3120 compatible = "arm,armv7-timer-mem";
3648 reg = <0x09840000 0x1 3121 reg = <0x09840000 0x1000>;
3649 clock-frequency = <19 3122 clock-frequency = <19200000>;
3650 3123
3651 frame@9850000 { 3124 frame@9850000 {
3652 frame-number 3125 frame-number = <0>;
3653 interrupts = 3126 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
3654 3127 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
3655 reg = <0x0985 3128 reg = <0x09850000 0x1000>,
3656 <0x0986 3129 <0x09860000 0x1000>;
3657 }; 3130 };
3658 3131
3659 frame@9870000 { 3132 frame@9870000 {
3660 frame-number 3133 frame-number = <1>;
3661 interrupts = 3134 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
3662 reg = <0x0987 3135 reg = <0x09870000 0x1000>;
3663 status = "dis 3136 status = "disabled";
3664 }; 3137 };
3665 3138
3666 frame@9880000 { 3139 frame@9880000 {
3667 frame-number 3140 frame-number = <2>;
3668 interrupts = 3141 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
3669 reg = <0x0988 3142 reg = <0x09880000 0x1000>;
3670 status = "dis 3143 status = "disabled";
3671 }; 3144 };
3672 3145
3673 frame@9890000 { 3146 frame@9890000 {
3674 frame-number 3147 frame-number = <3>;
3675 interrupts = 3148 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
3676 reg = <0x0989 3149 reg = <0x09890000 0x1000>;
3677 status = "dis 3150 status = "disabled";
3678 }; 3151 };
3679 3152
3680 frame@98a0000 { 3153 frame@98a0000 {
3681 frame-number 3154 frame-number = <4>;
3682 interrupts = 3155 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
3683 reg = <0x098a 3156 reg = <0x098a0000 0x1000>;
3684 status = "dis 3157 status = "disabled";
3685 }; 3158 };
3686 3159
3687 frame@98b0000 { 3160 frame@98b0000 {
3688 frame-number 3161 frame-number = <5>;
3689 interrupts = 3162 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
3690 reg = <0x098b 3163 reg = <0x098b0000 0x1000>;
3691 status = "dis 3164 status = "disabled";
3692 }; 3165 };
3693 3166
3694 frame@98c0000 { 3167 frame@98c0000 {
3695 frame-number 3168 frame-number = <6>;
3696 interrupts = 3169 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
3697 reg = <0x098c 3170 reg = <0x098c0000 0x1000>;
3698 status = "dis 3171 status = "disabled";
3699 }; 3172 };
3700 }; 3173 };
3701 3174
3702 saw3: syscon@9a10000 { 3175 saw3: syscon@9a10000 {
3703 compatible = "syscon" 3176 compatible = "syscon";
3704 reg = <0x09a10000 0x1 3177 reg = <0x09a10000 0x1000>;
3705 }; 3178 };
3706 3179
3707 cbf: clock-controller@9a11000 <<
3708 compatible = "qcom,ms <<
3709 reg = <0x09a11000 0x1 <<
3710 clocks = <&rpmcc RPM_ <<
3711 #clock-cells = <0>; <<
3712 #interconnect-cells = <<
3713 }; <<
3714 <<
3715 intc: interrupt-controller@9b 3180 intc: interrupt-controller@9bc0000 {
3716 compatible = "qcom,ms 3181 compatible = "qcom,msm8996-gic-v3", "arm,gic-v3";
3717 #interrupt-cells = <3 3182 #interrupt-cells = <3>;
3718 interrupt-controller; 3183 interrupt-controller;
3719 #redistributor-region 3184 #redistributor-regions = <1>;
3720 redistributor-stride 3185 redistributor-stride = <0x0 0x40000>;
3721 reg = <0x09bc0000 0x1 3186 reg = <0x09bc0000 0x10000>,
3722 <0x09c00000 0x1 3187 <0x09c00000 0x100000>;
3723 interrupts = <GIC_PPI 3188 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
3724 }; 3189 };
3725 }; 3190 };
3726 3191
3727 sound: sound { 3192 sound: sound {
3728 }; 3193 };
3729 3194
3730 thermal-zones { 3195 thermal-zones {
3731 cpu0-thermal { 3196 cpu0-thermal {
3732 polling-delay-passive 3197 polling-delay-passive = <250>;
>> 3198 polling-delay = <1000>;
3733 3199
3734 thermal-sensors = <&t 3200 thermal-sensors = <&tsens0 3>;
3735 3201
3736 trips { 3202 trips {
3737 cpu0_alert0: 3203 cpu0_alert0: trip-point0 {
3738 tempe 3204 temperature = <75000>;
3739 hyste 3205 hysteresis = <2000>;
3740 type 3206 type = "passive";
3741 }; 3207 };
3742 3208
3743 cpu0_crit: cp !! 3209 cpu0_crit: cpu_crit {
3744 tempe 3210 temperature = <110000>;
3745 hyste 3211 hysteresis = <2000>;
3746 type 3212 type = "critical";
3747 }; 3213 };
3748 }; 3214 };
3749 }; 3215 };
3750 3216
3751 cpu1-thermal { 3217 cpu1-thermal {
3752 polling-delay-passive 3218 polling-delay-passive = <250>;
>> 3219 polling-delay = <1000>;
3753 3220
3754 thermal-sensors = <&t 3221 thermal-sensors = <&tsens0 5>;
3755 3222
3756 trips { 3223 trips {
3757 cpu1_alert0: 3224 cpu1_alert0: trip-point0 {
3758 tempe 3225 temperature = <75000>;
3759 hyste 3226 hysteresis = <2000>;
3760 type 3227 type = "passive";
3761 }; 3228 };
3762 3229
3763 cpu1_crit: cp !! 3230 cpu1_crit: cpu_crit {
3764 tempe 3231 temperature = <110000>;
3765 hyste 3232 hysteresis = <2000>;
3766 type 3233 type = "critical";
3767 }; 3234 };
3768 }; 3235 };
3769 }; 3236 };
3770 3237
3771 cpu2-thermal { 3238 cpu2-thermal {
3772 polling-delay-passive 3239 polling-delay-passive = <250>;
>> 3240 polling-delay = <1000>;
3773 3241
3774 thermal-sensors = <&t 3242 thermal-sensors = <&tsens0 8>;
3775 3243
3776 trips { 3244 trips {
3777 cpu2_alert0: 3245 cpu2_alert0: trip-point0 {
3778 tempe 3246 temperature = <75000>;
3779 hyste 3247 hysteresis = <2000>;
3780 type 3248 type = "passive";
3781 }; 3249 };
3782 3250
3783 cpu2_crit: cp !! 3251 cpu2_crit: cpu_crit {
3784 tempe 3252 temperature = <110000>;
3785 hyste 3253 hysteresis = <2000>;
3786 type 3254 type = "critical";
3787 }; 3255 };
3788 }; 3256 };
3789 }; 3257 };
3790 3258
3791 cpu3-thermal { 3259 cpu3-thermal {
3792 polling-delay-passive 3260 polling-delay-passive = <250>;
>> 3261 polling-delay = <1000>;
3793 3262
3794 thermal-sensors = <&t 3263 thermal-sensors = <&tsens0 10>;
3795 3264
3796 trips { 3265 trips {
3797 cpu3_alert0: 3266 cpu3_alert0: trip-point0 {
3798 tempe 3267 temperature = <75000>;
3799 hyste 3268 hysteresis = <2000>;
3800 type 3269 type = "passive";
3801 }; 3270 };
3802 3271
3803 cpu3_crit: cp !! 3272 cpu3_crit: cpu_crit {
3804 tempe 3273 temperature = <110000>;
3805 hyste 3274 hysteresis = <2000>;
3806 type 3275 type = "critical";
3807 }; 3276 };
3808 }; 3277 };
3809 }; 3278 };
3810 3279
3811 gpu-top-thermal { 3280 gpu-top-thermal {
3812 polling-delay-passive 3281 polling-delay-passive = <250>;
>> 3282 polling-delay = <1000>;
3813 3283
3814 thermal-sensors = <&t 3284 thermal-sensors = <&tsens1 6>;
3815 3285
3816 trips { 3286 trips {
3817 gpu1_alert0: 3287 gpu1_alert0: trip-point0 {
3818 tempe 3288 temperature = <90000>;
3819 hyste 3289 hysteresis = <2000>;
3820 type 3290 type = "passive";
3821 }; 3291 };
3822 }; 3292 };
3823 3293
3824 cooling-maps { 3294 cooling-maps {
3825 map0 { 3295 map0 {
3826 trip 3296 trip = <&gpu1_alert0>;
3827 cooli 3297 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3828 }; 3298 };
3829 }; 3299 };
3830 }; 3300 };
3831 3301
3832 gpu-bottom-thermal { 3302 gpu-bottom-thermal {
3833 polling-delay-passive 3303 polling-delay-passive = <250>;
>> 3304 polling-delay = <1000>;
3834 3305
3835 thermal-sensors = <&t 3306 thermal-sensors = <&tsens1 7>;
3836 3307
3837 trips { 3308 trips {
3838 gpu2_alert0: 3309 gpu2_alert0: trip-point0 {
3839 tempe 3310 temperature = <90000>;
3840 hyste 3311 hysteresis = <2000>;
3841 type 3312 type = "passive";
3842 }; 3313 };
3843 }; 3314 };
3844 3315
3845 cooling-maps { 3316 cooling-maps {
3846 map0 { 3317 map0 {
3847 trip 3318 trip = <&gpu2_alert0>;
3848 cooli 3319 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3849 }; 3320 };
3850 }; 3321 };
3851 }; 3322 };
3852 3323
3853 m4m-thermal { 3324 m4m-thermal {
3854 polling-delay-passive 3325 polling-delay-passive = <250>;
>> 3326 polling-delay = <1000>;
3855 3327
3856 thermal-sensors = <&t 3328 thermal-sensors = <&tsens0 1>;
3857 3329
3858 trips { 3330 trips {
3859 m4m_alert0: t 3331 m4m_alert0: trip-point0 {
3860 tempe 3332 temperature = <90000>;
3861 hyste 3333 hysteresis = <2000>;
3862 type 3334 type = "hot";
3863 }; 3335 };
3864 }; 3336 };
3865 }; 3337 };
3866 3338
3867 l3-or-venus-thermal { 3339 l3-or-venus-thermal {
3868 polling-delay-passive 3340 polling-delay-passive = <250>;
>> 3341 polling-delay = <1000>;
3869 3342
3870 thermal-sensors = <&t 3343 thermal-sensors = <&tsens0 2>;
3871 3344
3872 trips { 3345 trips {
3873 l3_or_venus_a 3346 l3_or_venus_alert0: trip-point0 {
3874 tempe 3347 temperature = <90000>;
3875 hyste 3348 hysteresis = <2000>;
3876 type 3349 type = "hot";
3877 }; 3350 };
3878 }; 3351 };
3879 }; 3352 };
3880 3353
3881 cluster0-l2-thermal { 3354 cluster0-l2-thermal {
3882 polling-delay-passive 3355 polling-delay-passive = <250>;
>> 3356 polling-delay = <1000>;
3883 3357
3884 thermal-sensors = <&t 3358 thermal-sensors = <&tsens0 7>;
3885 3359
3886 trips { 3360 trips {
3887 cluster0_l2_a 3361 cluster0_l2_alert0: trip-point0 {
3888 tempe 3362 temperature = <90000>;
3889 hyste 3363 hysteresis = <2000>;
3890 type 3364 type = "hot";
3891 }; 3365 };
3892 }; 3366 };
3893 }; 3367 };
3894 3368
3895 cluster1-l2-thermal { 3369 cluster1-l2-thermal {
3896 polling-delay-passive 3370 polling-delay-passive = <250>;
>> 3371 polling-delay = <1000>;
3897 3372
3898 thermal-sensors = <&t 3373 thermal-sensors = <&tsens0 12>;
3899 3374
3900 trips { 3375 trips {
3901 cluster1_l2_a 3376 cluster1_l2_alert0: trip-point0 {
3902 tempe 3377 temperature = <90000>;
3903 hyste 3378 hysteresis = <2000>;
3904 type 3379 type = "hot";
3905 }; 3380 };
3906 }; 3381 };
3907 }; 3382 };
3908 3383
3909 camera-thermal { 3384 camera-thermal {
3910 polling-delay-passive 3385 polling-delay-passive = <250>;
>> 3386 polling-delay = <1000>;
3911 3387
3912 thermal-sensors = <&t 3388 thermal-sensors = <&tsens1 1>;
3913 3389
3914 trips { 3390 trips {
3915 camera_alert0 3391 camera_alert0: trip-point0 {
3916 tempe 3392 temperature = <90000>;
3917 hyste 3393 hysteresis = <2000>;
3918 type 3394 type = "hot";
3919 }; 3395 };
3920 }; 3396 };
3921 }; 3397 };
3922 3398
3923 q6-dsp-thermal { 3399 q6-dsp-thermal {
3924 polling-delay-passive 3400 polling-delay-passive = <250>;
>> 3401 polling-delay = <1000>;
3925 3402
3926 thermal-sensors = <&t 3403 thermal-sensors = <&tsens1 2>;
3927 3404
3928 trips { 3405 trips {
3929 q6_dsp_alert0 3406 q6_dsp_alert0: trip-point0 {
3930 tempe 3407 temperature = <90000>;
3931 hyste 3408 hysteresis = <2000>;
3932 type 3409 type = "hot";
3933 }; 3410 };
3934 }; 3411 };
3935 }; 3412 };
3936 3413
3937 mem-thermal { 3414 mem-thermal {
3938 polling-delay-passive 3415 polling-delay-passive = <250>;
>> 3416 polling-delay = <1000>;
3939 3417
3940 thermal-sensors = <&t 3418 thermal-sensors = <&tsens1 3>;
3941 3419
3942 trips { 3420 trips {
3943 mem_alert0: t 3421 mem_alert0: trip-point0 {
3944 tempe 3422 temperature = <90000>;
3945 hyste 3423 hysteresis = <2000>;
3946 type 3424 type = "hot";
3947 }; 3425 };
3948 }; 3426 };
3949 }; 3427 };
3950 3428
3951 modemtx-thermal { 3429 modemtx-thermal {
3952 polling-delay-passive 3430 polling-delay-passive = <250>;
>> 3431 polling-delay = <1000>;
3953 3432
3954 thermal-sensors = <&t 3433 thermal-sensors = <&tsens1 4>;
3955 3434
3956 trips { 3435 trips {
3957 modemtx_alert 3436 modemtx_alert0: trip-point0 {
3958 tempe 3437 temperature = <90000>;
3959 hyste 3438 hysteresis = <2000>;
3960 type 3439 type = "hot";
3961 }; 3440 };
3962 }; 3441 };
3963 }; 3442 };
3964 }; 3443 };
3965 3444
3966 timer { 3445 timer {
3967 compatible = "arm,armv8-timer 3446 compatible = "arm,armv8-timer";
3968 interrupts = <GIC_PPI 13 IRQ_ 3447 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
3969 <GIC_PPI 14 IRQ_ 3448 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
3970 <GIC_PPI 11 IRQ_ 3449 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
3971 <GIC_PPI 10 IRQ_ 3450 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
3972 }; 3451 };
3973 }; 3452 };
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