1 // SPDX-License-Identifier: GPL-2.0-only 1 // SPDX-License-Identifier: GPL-2.0-only
2 /* !! 2 /* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
3 * Copyright (c) 2014-2015, The Linux Foundati <<
4 */ 3 */
5 4
6 #include <dt-bindings/interrupt-controller/arm 5 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,gcc-msm8996.h 6 #include <dt-bindings/clock/qcom,gcc-msm8996.h>
8 #include <dt-bindings/clock/qcom,mmcc-msm8996. 7 #include <dt-bindings/clock/qcom,mmcc-msm8996.h>
9 #include <dt-bindings/clock/qcom,rpmcc.h> 8 #include <dt-bindings/clock/qcom,rpmcc.h>
10 #include <dt-bindings/interconnect/qcom,msm899 <<
11 #include <dt-bindings/interconnect/qcom,msm899 <<
12 #include <dt-bindings/firmware/qcom,scm.h> <<
13 #include <dt-bindings/gpio/gpio.h> <<
14 #include <dt-bindings/power/qcom-rpmpd.h> 9 #include <dt-bindings/power/qcom-rpmpd.h>
15 #include <dt-bindings/soc/qcom,apr.h> 10 #include <dt-bindings/soc/qcom,apr.h>
16 #include <dt-bindings/thermal/thermal.h> 11 #include <dt-bindings/thermal/thermal.h>
17 12
18 / { 13 / {
19 interrupt-parent = <&intc>; 14 interrupt-parent = <&intc>;
20 15
21 #address-cells = <2>; 16 #address-cells = <2>;
22 #size-cells = <2>; 17 #size-cells = <2>;
23 18
24 chosen { }; 19 chosen { };
25 20
26 clocks { 21 clocks {
27 xo_board: xo-board { 22 xo_board: xo-board {
28 compatible = "fixed-cl 23 compatible = "fixed-clock";
29 #clock-cells = <0>; 24 #clock-cells = <0>;
30 clock-frequency = <192 25 clock-frequency = <19200000>;
31 clock-output-names = " 26 clock-output-names = "xo_board";
32 }; 27 };
33 28
34 sleep_clk: sleep-clk { 29 sleep_clk: sleep-clk {
35 compatible = "fixed-cl 30 compatible = "fixed-clock";
36 #clock-cells = <0>; 31 #clock-cells = <0>;
37 clock-frequency = <327 32 clock-frequency = <32764>;
38 clock-output-names = " 33 clock-output-names = "sleep_clk";
39 }; 34 };
40 }; 35 };
41 36
42 cpus { 37 cpus {
43 #address-cells = <2>; 38 #address-cells = <2>;
44 #size-cells = <0>; 39 #size-cells = <0>;
45 40
46 CPU0: cpu@0 { 41 CPU0: cpu@0 {
47 device_type = "cpu"; 42 device_type = "cpu";
48 compatible = "qcom,kry 43 compatible = "qcom,kryo";
49 reg = <0x0 0x0>; 44 reg = <0x0 0x0>;
50 enable-method = "psci" 45 enable-method = "psci";
51 cpu-idle-states = <&CP 46 cpu-idle-states = <&CPU_SLEEP_0>;
52 capacity-dmips-mhz = < 47 capacity-dmips-mhz = <1024>;
53 clocks = <&kryocc 0>; 48 clocks = <&kryocc 0>;
54 interconnects = <&cbf <<
55 operating-points-v2 = 49 operating-points-v2 = <&cluster0_opp>;
56 #cooling-cells = <2>; 50 #cooling-cells = <2>;
57 next-level-cache = <&L 51 next-level-cache = <&L2_0>;
58 L2_0: l2-cache { 52 L2_0: l2-cache {
59 compatible = " !! 53 compatible = "cache";
60 cache-level = !! 54 cache-level = <2>;
61 cache-unified; <<
62 }; 55 };
63 }; 56 };
64 57
65 CPU1: cpu@1 { 58 CPU1: cpu@1 {
66 device_type = "cpu"; 59 device_type = "cpu";
67 compatible = "qcom,kry 60 compatible = "qcom,kryo";
68 reg = <0x0 0x1>; 61 reg = <0x0 0x1>;
69 enable-method = "psci" 62 enable-method = "psci";
70 cpu-idle-states = <&CP 63 cpu-idle-states = <&CPU_SLEEP_0>;
71 capacity-dmips-mhz = < 64 capacity-dmips-mhz = <1024>;
72 clocks = <&kryocc 0>; 65 clocks = <&kryocc 0>;
73 interconnects = <&cbf <<
74 operating-points-v2 = 66 operating-points-v2 = <&cluster0_opp>;
75 #cooling-cells = <2>; 67 #cooling-cells = <2>;
76 next-level-cache = <&L 68 next-level-cache = <&L2_0>;
77 }; 69 };
78 70
79 CPU2: cpu@100 { 71 CPU2: cpu@100 {
80 device_type = "cpu"; 72 device_type = "cpu";
81 compatible = "qcom,kry 73 compatible = "qcom,kryo";
82 reg = <0x0 0x100>; 74 reg = <0x0 0x100>;
83 enable-method = "psci" 75 enable-method = "psci";
84 cpu-idle-states = <&CP 76 cpu-idle-states = <&CPU_SLEEP_0>;
85 capacity-dmips-mhz = < 77 capacity-dmips-mhz = <1024>;
86 clocks = <&kryocc 1>; 78 clocks = <&kryocc 1>;
87 interconnects = <&cbf <<
88 operating-points-v2 = 79 operating-points-v2 = <&cluster1_opp>;
89 #cooling-cells = <2>; 80 #cooling-cells = <2>;
90 next-level-cache = <&L 81 next-level-cache = <&L2_1>;
91 L2_1: l2-cache { 82 L2_1: l2-cache {
92 compatible = " !! 83 compatible = "cache";
93 cache-level = !! 84 cache-level = <2>;
94 cache-unified; <<
95 }; 85 };
96 }; 86 };
97 87
98 CPU3: cpu@101 { 88 CPU3: cpu@101 {
99 device_type = "cpu"; 89 device_type = "cpu";
100 compatible = "qcom,kry 90 compatible = "qcom,kryo";
101 reg = <0x0 0x101>; 91 reg = <0x0 0x101>;
102 enable-method = "psci" 92 enable-method = "psci";
103 cpu-idle-states = <&CP 93 cpu-idle-states = <&CPU_SLEEP_0>;
104 capacity-dmips-mhz = < 94 capacity-dmips-mhz = <1024>;
105 clocks = <&kryocc 1>; 95 clocks = <&kryocc 1>;
106 interconnects = <&cbf <<
107 operating-points-v2 = 96 operating-points-v2 = <&cluster1_opp>;
108 #cooling-cells = <2>; 97 #cooling-cells = <2>;
109 next-level-cache = <&L 98 next-level-cache = <&L2_1>;
110 }; 99 };
111 100
112 cpu-map { 101 cpu-map {
113 cluster0 { 102 cluster0 {
114 core0 { 103 core0 {
115 cpu = 104 cpu = <&CPU0>;
116 }; 105 };
117 106
118 core1 { 107 core1 {
119 cpu = 108 cpu = <&CPU1>;
120 }; 109 };
121 }; 110 };
122 111
123 cluster1 { 112 cluster1 {
124 core0 { 113 core0 {
125 cpu = 114 cpu = <&CPU2>;
126 }; 115 };
127 116
128 core1 { 117 core1 {
129 cpu = 118 cpu = <&CPU3>;
130 }; 119 };
131 }; 120 };
132 }; 121 };
133 122
134 idle-states { 123 idle-states {
135 entry-method = "psci"; 124 entry-method = "psci";
136 125
137 CPU_SLEEP_0: cpu-sleep 126 CPU_SLEEP_0: cpu-sleep-0 {
138 compatible = " 127 compatible = "arm,idle-state";
139 idle-state-nam 128 idle-state-name = "standalone-power-collapse";
140 arm,psci-suspe 129 arm,psci-suspend-param = <0x00000004>;
141 entry-latency- 130 entry-latency-us = <130>;
142 exit-latency-u 131 exit-latency-us = <80>;
143 min-residency- 132 min-residency-us = <300>;
144 }; 133 };
145 }; 134 };
146 }; 135 };
147 136
148 cluster0_opp: opp-table-cluster0 { 137 cluster0_opp: opp-table-cluster0 {
149 compatible = "operating-points 138 compatible = "operating-points-v2-kryo-cpu";
150 nvmem-cells = <&speedbin_efuse 139 nvmem-cells = <&speedbin_efuse>;
151 opp-shared; 140 opp-shared;
152 141
153 /* Nominal fmax for now */ 142 /* Nominal fmax for now */
154 opp-307200000 { 143 opp-307200000 {
155 opp-hz = /bits/ 64 <30 144 opp-hz = /bits/ 64 <307200000>;
156 opp-supported-hw = <0x !! 145 opp-supported-hw = <0x77>;
157 clock-latency-ns = <20 146 clock-latency-ns = <200000>;
158 opp-peak-kBps = <30720 <<
159 }; 147 };
160 opp-422400000 { 148 opp-422400000 {
161 opp-hz = /bits/ 64 <42 149 opp-hz = /bits/ 64 <422400000>;
162 opp-supported-hw = <0x !! 150 opp-supported-hw = <0x77>;
163 clock-latency-ns = <20 151 clock-latency-ns = <200000>;
164 opp-peak-kBps = <30720 <<
165 }; 152 };
166 opp-480000000 { 153 opp-480000000 {
167 opp-hz = /bits/ 64 <48 154 opp-hz = /bits/ 64 <480000000>;
168 opp-supported-hw = <0x !! 155 opp-supported-hw = <0x77>;
169 clock-latency-ns = <20 156 clock-latency-ns = <200000>;
170 opp-peak-kBps = <30720 <<
171 }; 157 };
172 opp-556800000 { 158 opp-556800000 {
173 opp-hz = /bits/ 64 <55 159 opp-hz = /bits/ 64 <556800000>;
174 opp-supported-hw = <0x !! 160 opp-supported-hw = <0x77>;
175 clock-latency-ns = <20 161 clock-latency-ns = <200000>;
176 opp-peak-kBps = <30720 <<
177 }; 162 };
178 opp-652800000 { 163 opp-652800000 {
179 opp-hz = /bits/ 64 <65 164 opp-hz = /bits/ 64 <652800000>;
180 opp-supported-hw = <0x !! 165 opp-supported-hw = <0x77>;
181 clock-latency-ns = <20 166 clock-latency-ns = <200000>;
182 opp-peak-kBps = <38400 <<
183 }; 167 };
184 opp-729600000 { 168 opp-729600000 {
185 opp-hz = /bits/ 64 <72 169 opp-hz = /bits/ 64 <729600000>;
186 opp-supported-hw = <0x !! 170 opp-supported-hw = <0x77>;
187 clock-latency-ns = <20 171 clock-latency-ns = <200000>;
188 opp-peak-kBps = <46080 <<
189 }; 172 };
190 opp-844800000 { 173 opp-844800000 {
191 opp-hz = /bits/ 64 <84 174 opp-hz = /bits/ 64 <844800000>;
192 opp-supported-hw = <0x !! 175 opp-supported-hw = <0x77>;
193 clock-latency-ns = <20 176 clock-latency-ns = <200000>;
194 opp-peak-kBps = <53760 <<
195 }; 177 };
196 opp-960000000 { 178 opp-960000000 {
197 opp-hz = /bits/ 64 <96 179 opp-hz = /bits/ 64 <960000000>;
198 opp-supported-hw = <0x !! 180 opp-supported-hw = <0x77>;
199 clock-latency-ns = <20 181 clock-latency-ns = <200000>;
200 opp-peak-kBps = <67200 <<
201 }; 182 };
202 opp-1036800000 { 183 opp-1036800000 {
203 opp-hz = /bits/ 64 <10 184 opp-hz = /bits/ 64 <1036800000>;
204 opp-supported-hw = <0x !! 185 opp-supported-hw = <0x77>;
205 clock-latency-ns = <20 186 clock-latency-ns = <200000>;
206 opp-peak-kBps = <67200 <<
207 }; 187 };
208 opp-1113600000 { 188 opp-1113600000 {
209 opp-hz = /bits/ 64 <11 189 opp-hz = /bits/ 64 <1113600000>;
210 opp-supported-hw = <0x !! 190 opp-supported-hw = <0x77>;
211 clock-latency-ns = <20 191 clock-latency-ns = <200000>;
212 opp-peak-kBps = <82560 <<
213 }; 192 };
214 opp-1190400000 { 193 opp-1190400000 {
215 opp-hz = /bits/ 64 <11 194 opp-hz = /bits/ 64 <1190400000>;
216 opp-supported-hw = <0x !! 195 opp-supported-hw = <0x77>;
217 clock-latency-ns = <20 196 clock-latency-ns = <200000>;
218 opp-peak-kBps = <82560 <<
219 }; 197 };
220 opp-1228800000 { 198 opp-1228800000 {
221 opp-hz = /bits/ 64 <12 199 opp-hz = /bits/ 64 <1228800000>;
222 opp-supported-hw = <0x !! 200 opp-supported-hw = <0x77>;
223 clock-latency-ns = <20 201 clock-latency-ns = <200000>;
224 opp-peak-kBps = <90240 <<
225 }; 202 };
226 opp-1324800000 { 203 opp-1324800000 {
227 opp-hz = /bits/ 64 <13 204 opp-hz = /bits/ 64 <1324800000>;
228 opp-supported-hw = <0x !! 205 opp-supported-hw = <0x77>;
229 clock-latency-ns = <20 206 clock-latency-ns = <200000>;
230 opp-peak-kBps = <10560 <<
231 }; <<
232 opp-1363200000 { <<
233 opp-hz = /bits/ 64 <13 <<
234 opp-supported-hw = <0x <<
235 clock-latency-ns = <20 <<
236 opp-peak-kBps = <11328 <<
237 }; 207 };
238 opp-1401600000 { 208 opp-1401600000 {
239 opp-hz = /bits/ 64 <14 209 opp-hz = /bits/ 64 <1401600000>;
240 opp-supported-hw = <0x !! 210 opp-supported-hw = <0x77>;
241 clock-latency-ns = <20 211 clock-latency-ns = <200000>;
242 opp-peak-kBps = <11328 <<
243 }; 212 };
244 opp-1478400000 { 213 opp-1478400000 {
245 opp-hz = /bits/ 64 <14 214 opp-hz = /bits/ 64 <1478400000>;
246 opp-supported-hw = <0x !! 215 opp-supported-hw = <0x77>;
247 clock-latency-ns = <20 216 clock-latency-ns = <200000>;
248 opp-peak-kBps = <11904 <<
249 }; <<
250 opp-1497600000 { <<
251 opp-hz = /bits/ 64 <14 <<
252 opp-supported-hw = <0x <<
253 clock-latency-ns = <20 <<
254 opp-peak-kBps = <13056 <<
255 }; 217 };
256 opp-1593600000 { 218 opp-1593600000 {
257 opp-hz = /bits/ 64 <15 219 opp-hz = /bits/ 64 <1593600000>;
258 opp-supported-hw = <0x !! 220 opp-supported-hw = <0x77>;
259 clock-latency-ns = <20 221 clock-latency-ns = <200000>;
260 opp-peak-kBps = <13824 <<
261 }; 222 };
262 }; 223 };
263 224
264 cluster1_opp: opp-table-cluster1 { 225 cluster1_opp: opp-table-cluster1 {
265 compatible = "operating-points 226 compatible = "operating-points-v2-kryo-cpu";
266 nvmem-cells = <&speedbin_efuse 227 nvmem-cells = <&speedbin_efuse>;
267 opp-shared; 228 opp-shared;
268 229
269 /* Nominal fmax for now */ 230 /* Nominal fmax for now */
270 opp-307200000 { 231 opp-307200000 {
271 opp-hz = /bits/ 64 <30 232 opp-hz = /bits/ 64 <307200000>;
272 opp-supported-hw = <0x !! 233 opp-supported-hw = <0x77>;
273 clock-latency-ns = <20 234 clock-latency-ns = <200000>;
274 opp-peak-kBps = <30720 <<
275 }; 235 };
276 opp-403200000 { 236 opp-403200000 {
277 opp-hz = /bits/ 64 <40 237 opp-hz = /bits/ 64 <403200000>;
278 opp-supported-hw = <0x !! 238 opp-supported-hw = <0x77>;
279 clock-latency-ns = <20 239 clock-latency-ns = <200000>;
280 opp-peak-kBps = <30720 <<
281 }; 240 };
282 opp-480000000 { 241 opp-480000000 {
283 opp-hz = /bits/ 64 <48 242 opp-hz = /bits/ 64 <480000000>;
284 opp-supported-hw = <0x !! 243 opp-supported-hw = <0x77>;
285 clock-latency-ns = <20 244 clock-latency-ns = <200000>;
286 opp-peak-kBps = <30720 <<
287 }; 245 };
288 opp-556800000 { 246 opp-556800000 {
289 opp-hz = /bits/ 64 <55 247 opp-hz = /bits/ 64 <556800000>;
290 opp-supported-hw = <0x !! 248 opp-supported-hw = <0x77>;
291 clock-latency-ns = <20 249 clock-latency-ns = <200000>;
292 opp-peak-kBps = <30720 <<
293 }; 250 };
294 opp-652800000 { 251 opp-652800000 {
295 opp-hz = /bits/ 64 <65 252 opp-hz = /bits/ 64 <652800000>;
296 opp-supported-hw = <0x !! 253 opp-supported-hw = <0x77>;
297 clock-latency-ns = <20 254 clock-latency-ns = <200000>;
298 opp-peak-kBps = <30720 <<
299 }; 255 };
300 opp-729600000 { 256 opp-729600000 {
301 opp-hz = /bits/ 64 <72 257 opp-hz = /bits/ 64 <729600000>;
302 opp-supported-hw = <0x !! 258 opp-supported-hw = <0x77>;
303 clock-latency-ns = <20 259 clock-latency-ns = <200000>;
304 opp-peak-kBps = <30720 <<
305 }; 260 };
306 opp-806400000 { 261 opp-806400000 {
307 opp-hz = /bits/ 64 <80 262 opp-hz = /bits/ 64 <806400000>;
308 opp-supported-hw = <0x !! 263 opp-supported-hw = <0x77>;
309 clock-latency-ns = <20 264 clock-latency-ns = <200000>;
310 opp-peak-kBps = <38400 <<
311 }; 265 };
312 opp-883200000 { 266 opp-883200000 {
313 opp-hz = /bits/ 64 <88 267 opp-hz = /bits/ 64 <883200000>;
314 opp-supported-hw = <0x !! 268 opp-supported-hw = <0x77>;
315 clock-latency-ns = <20 269 clock-latency-ns = <200000>;
316 opp-peak-kBps = <46080 <<
317 }; 270 };
318 opp-940800000 { 271 opp-940800000 {
319 opp-hz = /bits/ 64 <94 272 opp-hz = /bits/ 64 <940800000>;
320 opp-supported-hw = <0x !! 273 opp-supported-hw = <0x77>;
321 clock-latency-ns = <20 274 clock-latency-ns = <200000>;
322 opp-peak-kBps = <53760 <<
323 }; 275 };
324 opp-1036800000 { 276 opp-1036800000 {
325 opp-hz = /bits/ 64 <10 277 opp-hz = /bits/ 64 <1036800000>;
326 opp-supported-hw = <0x !! 278 opp-supported-hw = <0x77>;
327 clock-latency-ns = <20 279 clock-latency-ns = <200000>;
328 opp-peak-kBps = <59520 <<
329 }; 280 };
330 opp-1113600000 { 281 opp-1113600000 {
331 opp-hz = /bits/ 64 <11 282 opp-hz = /bits/ 64 <1113600000>;
332 opp-supported-hw = <0x !! 283 opp-supported-hw = <0x77>;
333 clock-latency-ns = <20 284 clock-latency-ns = <200000>;
334 opp-peak-kBps = <67200 <<
335 }; 285 };
336 opp-1190400000 { 286 opp-1190400000 {
337 opp-hz = /bits/ 64 <11 287 opp-hz = /bits/ 64 <1190400000>;
338 opp-supported-hw = <0x !! 288 opp-supported-hw = <0x77>;
339 clock-latency-ns = <20 289 clock-latency-ns = <200000>;
340 opp-peak-kBps = <67200 <<
341 }; 290 };
342 opp-1248000000 { 291 opp-1248000000 {
343 opp-hz = /bits/ 64 <12 292 opp-hz = /bits/ 64 <1248000000>;
344 opp-supported-hw = <0x !! 293 opp-supported-hw = <0x77>;
345 clock-latency-ns = <20 294 clock-latency-ns = <200000>;
346 opp-peak-kBps = <74880 <<
347 }; 295 };
348 opp-1324800000 { 296 opp-1324800000 {
349 opp-hz = /bits/ 64 <13 297 opp-hz = /bits/ 64 <1324800000>;
350 opp-supported-hw = <0x !! 298 opp-supported-hw = <0x77>;
351 clock-latency-ns = <20 299 clock-latency-ns = <200000>;
352 opp-peak-kBps = <82560 <<
353 }; 300 };
354 opp-1401600000 { 301 opp-1401600000 {
355 opp-hz = /bits/ 64 <14 302 opp-hz = /bits/ 64 <1401600000>;
356 opp-supported-hw = <0x !! 303 opp-supported-hw = <0x77>;
357 clock-latency-ns = <20 304 clock-latency-ns = <200000>;
358 opp-peak-kBps = <90240 <<
359 }; 305 };
360 opp-1478400000 { 306 opp-1478400000 {
361 opp-hz = /bits/ 64 <14 307 opp-hz = /bits/ 64 <1478400000>;
362 opp-supported-hw = <0x !! 308 opp-supported-hw = <0x77>;
363 clock-latency-ns = <20 309 clock-latency-ns = <200000>;
364 opp-peak-kBps = <97920 <<
365 }; 310 };
366 opp-1555200000 { 311 opp-1555200000 {
367 opp-hz = /bits/ 64 <15 312 opp-hz = /bits/ 64 <1555200000>;
368 opp-supported-hw = <0x !! 313 opp-supported-hw = <0x77>;
369 clock-latency-ns = <20 314 clock-latency-ns = <200000>;
370 opp-peak-kBps = <10560 <<
371 }; 315 };
372 opp-1632000000 { 316 opp-1632000000 {
373 opp-hz = /bits/ 64 <16 317 opp-hz = /bits/ 64 <1632000000>;
374 opp-supported-hw = <0x !! 318 opp-supported-hw = <0x77>;
375 clock-latency-ns = <20 319 clock-latency-ns = <200000>;
376 opp-peak-kBps = <11904 <<
377 }; 320 };
378 opp-1708800000 { 321 opp-1708800000 {
379 opp-hz = /bits/ 64 <17 322 opp-hz = /bits/ 64 <1708800000>;
380 opp-supported-hw = <0x !! 323 opp-supported-hw = <0x77>;
381 clock-latency-ns = <20 324 clock-latency-ns = <200000>;
382 opp-peak-kBps = <12288 <<
383 }; 325 };
384 opp-1785600000 { 326 opp-1785600000 {
385 opp-hz = /bits/ 64 <17 327 opp-hz = /bits/ 64 <1785600000>;
386 opp-supported-hw = <0x !! 328 opp-supported-hw = <0x77>;
387 clock-latency-ns = <20 329 clock-latency-ns = <200000>;
388 opp-peak-kBps = <13056 <<
389 }; <<
390 opp-1804800000 { <<
391 opp-hz = /bits/ 64 <18 <<
392 opp-supported-hw = <0x <<
393 clock-latency-ns = <20 <<
394 opp-peak-kBps = <13056 <<
395 }; 330 };
396 opp-1824000000 { 331 opp-1824000000 {
397 opp-hz = /bits/ 64 <18 332 opp-hz = /bits/ 64 <1824000000>;
398 opp-supported-hw = <0x !! 333 opp-supported-hw = <0x77>;
399 clock-latency-ns = <20 <<
400 opp-peak-kBps = <13824 <<
401 }; <<
402 opp-1900800000 { <<
403 opp-hz = /bits/ 64 <19 <<
404 opp-supported-hw = <0x <<
405 clock-latency-ns = <20 334 clock-latency-ns = <200000>;
406 opp-peak-kBps = <13056 <<
407 }; 335 };
408 opp-1920000000 { 336 opp-1920000000 {
409 opp-hz = /bits/ 64 <19 337 opp-hz = /bits/ 64 <1920000000>;
410 opp-supported-hw = <0x !! 338 opp-supported-hw = <0x77>;
411 clock-latency-ns = <20 339 clock-latency-ns = <200000>;
412 opp-peak-kBps = <14592 <<
413 }; 340 };
414 opp-1996800000 { 341 opp-1996800000 {
415 opp-hz = /bits/ 64 <19 342 opp-hz = /bits/ 64 <1996800000>;
416 opp-supported-hw = <0x !! 343 opp-supported-hw = <0x77>;
417 clock-latency-ns = <20 344 clock-latency-ns = <200000>;
418 opp-peak-kBps = <15936 <<
419 }; 345 };
420 opp-2073600000 { 346 opp-2073600000 {
421 opp-hz = /bits/ 64 <20 347 opp-hz = /bits/ 64 <2073600000>;
422 opp-supported-hw = <0x !! 348 opp-supported-hw = <0x77>;
423 clock-latency-ns = <20 349 clock-latency-ns = <200000>;
424 opp-peak-kBps = <15936 <<
425 }; 350 };
426 opp-2150400000 { 351 opp-2150400000 {
427 opp-hz = /bits/ 64 <21 352 opp-hz = /bits/ 64 <2150400000>;
428 opp-supported-hw = <0x !! 353 opp-supported-hw = <0x77>;
429 clock-latency-ns = <20 354 clock-latency-ns = <200000>;
430 opp-peak-kBps = <15936 <<
431 }; 355 };
432 }; 356 };
433 357
434 firmware { 358 firmware {
435 scm { 359 scm {
436 compatible = "qcom,scm !! 360 compatible = "qcom,scm-msm8996";
437 qcom,dload-mode = <&tc !! 361 qcom,dload-mode = <&tcsr 0x13000>;
438 }; 362 };
439 }; 363 };
440 364
>> 365 tcsr_mutex: hwlock {
>> 366 compatible = "qcom,tcsr-mutex";
>> 367 syscon = <&tcsr_mutex_regs 0 0x1000>;
>> 368 #hwlock-cells = <1>;
>> 369 };
>> 370
441 memory@80000000 { 371 memory@80000000 {
442 device_type = "memory"; 372 device_type = "memory";
443 /* We expect the bootloader to 373 /* We expect the bootloader to fill in the reg */
444 reg = <0x0 0x80000000 0x0 0x0> 374 reg = <0x0 0x80000000 0x0 0x0>;
445 }; 375 };
446 376
447 etm { <<
448 compatible = "qcom,coresight-r <<
449 <<
450 out-ports { <<
451 port { <<
452 modem_etm_out_ <<
453 remote <<
454 <&fu <<
455 }; <<
456 }; <<
457 }; <<
458 }; <<
459 <<
460 psci { 377 psci {
461 compatible = "arm,psci-1.0"; 378 compatible = "arm,psci-1.0";
462 method = "smc"; 379 method = "smc";
463 }; 380 };
464 381
465 rpm: remoteproc { <<
466 compatible = "qcom,msm8996-rpm <<
467 <<
468 glink-edge { <<
469 compatible = "qcom,gli <<
470 interrupts = <GIC_SPI <<
471 qcom,rpm-msg-ram = <&r <<
472 mboxes = <&apcs_glb 0> <<
473 <<
474 rpm_requests: rpm-requ <<
475 compatible = " <<
476 qcom,glink-cha <<
477 <<
478 rpmcc: clock-c <<
479 compat <<
480 #clock <<
481 clocks <<
482 clock- <<
483 }; <<
484 <<
485 rpmpd: power-c <<
486 compat <<
487 #power <<
488 operat <<
489 <<
490 rpmpd_ <<
491 <<
492 <<
493 <<
494 <<
495 <<
496 <<
497 <<
498 <<
499 <<
500 <<
501 <<
502 <<
503 <<
504 <<
505 <<
506 <<
507 <<
508 <<
509 <<
510 <<
511 <<
512 <<
513 <<
514 <<
515 <<
516 }; <<
517 }; <<
518 }; <<
519 }; <<
520 }; <<
521 <<
522 reserved-memory { 382 reserved-memory {
523 #address-cells = <2>; 383 #address-cells = <2>;
524 #size-cells = <2>; 384 #size-cells = <2>;
525 ranges; 385 ranges;
526 386
527 hyp_mem: memory@85800000 { 387 hyp_mem: memory@85800000 {
528 reg = <0x0 0x85800000 388 reg = <0x0 0x85800000 0x0 0x600000>;
529 no-map; 389 no-map;
530 }; 390 };
531 391
532 xbl_mem: memory@85e00000 { 392 xbl_mem: memory@85e00000 {
533 reg = <0x0 0x85e00000 393 reg = <0x0 0x85e00000 0x0 0x200000>;
534 no-map; 394 no-map;
535 }; 395 };
536 396
537 smem_mem: smem-mem@86000000 { 397 smem_mem: smem-mem@86000000 {
538 reg = <0x0 0x86000000 398 reg = <0x0 0x86000000 0x0 0x200000>;
539 no-map; 399 no-map;
540 }; 400 };
541 401
542 tz_mem: memory@86200000 { 402 tz_mem: memory@86200000 {
543 reg = <0x0 0x86200000 403 reg = <0x0 0x86200000 0x0 0x2600000>;
544 no-map; 404 no-map;
545 }; 405 };
546 406
547 rmtfs_mem: rmtfs { 407 rmtfs_mem: rmtfs {
548 compatible = "qcom,rmt 408 compatible = "qcom,rmtfs-mem";
549 409
550 size = <0x0 0x200000>; 410 size = <0x0 0x200000>;
551 alloc-ranges = <0x0 0x 411 alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>;
552 no-map; 412 no-map;
553 413
554 qcom,client-id = <1>; 414 qcom,client-id = <1>;
555 qcom,vmid = <QCOM_SCM_ !! 415 qcom,vmid = <15>;
556 }; 416 };
557 417
558 mpss_mem: mpss@88800000 { 418 mpss_mem: mpss@88800000 {
559 reg = <0x0 0x88800000 419 reg = <0x0 0x88800000 0x0 0x6200000>;
560 no-map; 420 no-map;
561 }; 421 };
562 422
563 adsp_mem: adsp@8ea00000 { 423 adsp_mem: adsp@8ea00000 {
564 reg = <0x0 0x8ea00000 424 reg = <0x0 0x8ea00000 0x0 0x1b00000>;
565 no-map; 425 no-map;
566 }; 426 };
567 427
568 slpi_mem: slpi@90500000 { 428 slpi_mem: slpi@90500000 {
569 reg = <0x0 0x90500000 429 reg = <0x0 0x90500000 0x0 0xa00000>;
570 no-map; 430 no-map;
571 }; 431 };
572 432
573 gpu_mem: gpu@90f00000 { 433 gpu_mem: gpu@90f00000 {
574 compatible = "shared-d 434 compatible = "shared-dma-pool";
575 reg = <0x0 0x90f00000 435 reg = <0x0 0x90f00000 0x0 0x100000>;
576 no-map; 436 no-map;
577 }; 437 };
578 438
579 venus_mem: venus@91000000 { 439 venus_mem: venus@91000000 {
580 reg = <0x0 0x91000000 440 reg = <0x0 0x91000000 0x0 0x500000>;
581 no-map; 441 no-map;
582 }; 442 };
583 443
584 mba_mem: mba@91500000 { 444 mba_mem: mba@91500000 {
585 reg = <0x0 0x91500000 445 reg = <0x0 0x91500000 0x0 0x200000>;
586 no-map; 446 no-map;
587 }; 447 };
>> 448 };
588 449
589 mdata_mem: mpss-metadata { !! 450 rpm-glink {
590 alloc-ranges = <0x0 0x !! 451 compatible = "qcom,glink-rpm";
591 size = <0x0 0x4000>; !! 452
592 no-map; !! 453 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
>> 454
>> 455 qcom,rpm-msg-ram = <&rpm_msg_ram>;
>> 456
>> 457 mboxes = <&apcs_glb 0>;
>> 458
>> 459 rpm_requests: rpm-requests {
>> 460 compatible = "qcom,rpm-msm8996";
>> 461 qcom,glink-channels = "rpm_requests";
>> 462
>> 463 rpmcc: qcom,rpmcc {
>> 464 compatible = "qcom,rpmcc-msm8996", "qcom,rpmcc";
>> 465 #clock-cells = <1>;
>> 466 };
>> 467
>> 468 rpmpd: power-controller {
>> 469 compatible = "qcom,msm8996-rpmpd";
>> 470 #power-domain-cells = <1>;
>> 471 operating-points-v2 = <&rpmpd_opp_table>;
>> 472
>> 473 rpmpd_opp_table: opp-table {
>> 474 compatible = "operating-points-v2";
>> 475
>> 476 rpmpd_opp1: opp1 {
>> 477 opp-level = <1>;
>> 478 };
>> 479
>> 480 rpmpd_opp2: opp2 {
>> 481 opp-level = <2>;
>> 482 };
>> 483
>> 484 rpmpd_opp3: opp3 {
>> 485 opp-level = <3>;
>> 486 };
>> 487
>> 488 rpmpd_opp4: opp4 {
>> 489 opp-level = <4>;
>> 490 };
>> 491
>> 492 rpmpd_opp5: opp5 {
>> 493 opp-level = <5>;
>> 494 };
>> 495
>> 496 rpmpd_opp6: opp6 {
>> 497 opp-level = <6>;
>> 498 };
>> 499 };
>> 500 };
593 }; 501 };
594 }; 502 };
595 503
596 smem { 504 smem {
597 compatible = "qcom,smem"; 505 compatible = "qcom,smem";
598 memory-region = <&smem_mem>; 506 memory-region = <&smem_mem>;
599 hwlocks = <&tcsr_mutex 3>; 507 hwlocks = <&tcsr_mutex 3>;
600 }; 508 };
601 509
602 smp2p-adsp { 510 smp2p-adsp {
603 compatible = "qcom,smp2p"; 511 compatible = "qcom,smp2p";
604 qcom,smem = <443>, <429>; 512 qcom,smem = <443>, <429>;
605 513
606 interrupts = <GIC_SPI 158 IRQ_ !! 514 interrupts = <0 158 IRQ_TYPE_EDGE_RISING>;
607 515
608 mboxes = <&apcs_glb 10>; 516 mboxes = <&apcs_glb 10>;
609 517
610 qcom,local-pid = <0>; 518 qcom,local-pid = <0>;
611 qcom,remote-pid = <2>; 519 qcom,remote-pid = <2>;
612 520
613 adsp_smp2p_out: master-kernel 521 adsp_smp2p_out: master-kernel {
614 qcom,entry-name = "mas 522 qcom,entry-name = "master-kernel";
615 #qcom,smem-state-cells 523 #qcom,smem-state-cells = <1>;
616 }; 524 };
617 525
618 adsp_smp2p_in: slave-kernel { 526 adsp_smp2p_in: slave-kernel {
619 qcom,entry-name = "sla 527 qcom,entry-name = "slave-kernel";
620 528
621 interrupt-controller; 529 interrupt-controller;
622 #interrupt-cells = <2> 530 #interrupt-cells = <2>;
623 }; 531 };
624 }; 532 };
625 533
626 smp2p-mpss { 534 smp2p-mpss {
627 compatible = "qcom,smp2p"; 535 compatible = "qcom,smp2p";
628 qcom,smem = <435>, <428>; 536 qcom,smem = <435>, <428>;
629 537
630 interrupts = <GIC_SPI 451 IRQ_ 538 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
631 539
632 mboxes = <&apcs_glb 14>; 540 mboxes = <&apcs_glb 14>;
633 541
634 qcom,local-pid = <0>; 542 qcom,local-pid = <0>;
635 qcom,remote-pid = <1>; 543 qcom,remote-pid = <1>;
636 544
637 mpss_smp2p_out: master-kernel 545 mpss_smp2p_out: master-kernel {
638 qcom,entry-name = "mas 546 qcom,entry-name = "master-kernel";
639 #qcom,smem-state-cells 547 #qcom,smem-state-cells = <1>;
640 }; 548 };
641 549
642 mpss_smp2p_in: slave-kernel { 550 mpss_smp2p_in: slave-kernel {
643 qcom,entry-name = "sla 551 qcom,entry-name = "slave-kernel";
644 552
645 interrupt-controller; 553 interrupt-controller;
646 #interrupt-cells = <2> 554 #interrupt-cells = <2>;
647 }; 555 };
648 }; 556 };
649 557
650 smp2p-slpi { 558 smp2p-slpi {
651 compatible = "qcom,smp2p"; 559 compatible = "qcom,smp2p";
652 qcom,smem = <481>, <430>; 560 qcom,smem = <481>, <430>;
653 561
654 interrupts = <GIC_SPI 178 IRQ_ 562 interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>;
655 563
656 mboxes = <&apcs_glb 26>; 564 mboxes = <&apcs_glb 26>;
657 565
658 qcom,local-pid = <0>; 566 qcom,local-pid = <0>;
659 qcom,remote-pid = <3>; 567 qcom,remote-pid = <3>;
660 568
661 slpi_smp2p_out: master-kernel 569 slpi_smp2p_out: master-kernel {
662 qcom,entry-name = "mas 570 qcom,entry-name = "master-kernel";
663 #qcom,smem-state-cells 571 #qcom,smem-state-cells = <1>;
664 }; 572 };
665 573
666 slpi_smp2p_in: slave-kernel { 574 slpi_smp2p_in: slave-kernel {
667 qcom,entry-name = "sla 575 qcom,entry-name = "slave-kernel";
668 576
669 interrupt-controller; 577 interrupt-controller;
670 #interrupt-cells = <2> 578 #interrupt-cells = <2>;
671 }; 579 };
672 }; 580 };
673 581
674 soc: soc@0 { !! 582 soc: soc {
675 #address-cells = <1>; 583 #address-cells = <1>;
676 #size-cells = <1>; 584 #size-cells = <1>;
677 ranges = <0 0 0 0xffffffff>; 585 ranges = <0 0 0 0xffffffff>;
678 compatible = "simple-bus"; 586 compatible = "simple-bus";
679 587
680 pcie_phy: phy-wrapper@34000 { !! 588 pcie_phy: phy@34000 {
681 compatible = "qcom,msm 589 compatible = "qcom,msm8996-qmp-pcie-phy";
682 reg = <0x00034000 0x48 590 reg = <0x00034000 0x488>;
683 #address-cells = <1>; 591 #address-cells = <1>;
684 #size-cells = <1>; 592 #size-cells = <1>;
685 ranges = <0x0 0x000340 !! 593 ranges;
686 594
687 clocks = <&gcc GCC_PCI 595 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
688 <&gcc GCC_PCIE 596 <&gcc GCC_PCIE_PHY_CFG_AHB_CLK>,
689 <&gcc GCC_PCIE 597 <&gcc GCC_PCIE_CLKREF_CLK>;
690 clock-names = "aux", " 598 clock-names = "aux", "cfg_ahb", "ref";
691 599
692 resets = <&gcc GCC_PCI 600 resets = <&gcc GCC_PCIE_PHY_BCR>,
693 <&gcc GCC_PCIE 601 <&gcc GCC_PCIE_PHY_COM_BCR>,
694 <&gcc GCC_PCIE 602 <&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>;
695 reset-names = "phy", " 603 reset-names = "phy", "common", "cfg";
696 <<
697 status = "disabled"; 604 status = "disabled";
698 605
699 pciephy_0: phy@1000 { !! 606 pciephy_0: phy@35000 {
700 reg = <0x1000 !! 607 reg = <0x00035000 0x130>,
701 <0x1200 !! 608 <0x00035200 0x200>,
702 <0x1400 !! 609 <0x00035400 0x1dc>;
>> 610 #phy-cells = <0>;
703 611
>> 612 #clock-cells = <0>;
>> 613 clock-output-names = "pcie_0_pipe_clk_src";
704 clocks = <&gcc 614 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
705 clock-names = 615 clock-names = "pipe0";
706 resets = <&gcc 616 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
707 reset-names = 617 reset-names = "lane0";
708 <<
709 #clock-cells = <<
710 clock-output-n <<
711 <<
712 #phy-cells = < <<
713 }; 618 };
714 619
715 pciephy_1: phy@2000 { !! 620 pciephy_1: phy@36000 {
716 reg = <0x2000 !! 621 reg = <0x00036000 0x130>,
717 <0x2200 !! 622 <0x00036200 0x200>,
718 <0x2400 !! 623 <0x00036400 0x1dc>;
>> 624 #phy-cells = <0>;
719 625
>> 626 #clock-cells = <0>;
>> 627 clock-output-names = "pcie_1_pipe_clk_src";
720 clocks = <&gcc 628 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
721 clock-names = 629 clock-names = "pipe1";
722 resets = <&gcc 630 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
723 reset-names = 631 reset-names = "lane1";
724 <<
725 #clock-cells = <<
726 clock-output-n <<
727 <<
728 #phy-cells = < <<
729 }; 632 };
730 633
731 pciephy_2: phy@3000 { !! 634 pciephy_2: phy@37000 {
732 reg = <0x3000 !! 635 reg = <0x00037000 0x130>,
733 <0x3200 !! 636 <0x00037200 0x200>,
734 <0x3400 !! 637 <0x00037400 0x1dc>;
>> 638 #phy-cells = <0>;
735 639
>> 640 #clock-cells = <0>;
>> 641 clock-output-names = "pcie_2_pipe_clk_src";
736 clocks = <&gcc 642 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>;
737 clock-names = 643 clock-names = "pipe2";
738 resets = <&gcc 644 resets = <&gcc GCC_PCIE_2_PHY_BCR>;
739 reset-names = 645 reset-names = "lane2";
740 <<
741 #clock-cells = <<
742 clock-output-n <<
743 <<
744 #phy-cells = < <<
745 }; 646 };
746 }; 647 };
747 648
748 rpm_msg_ram: sram@68000 { 649 rpm_msg_ram: sram@68000 {
749 compatible = "qcom,rpm 650 compatible = "qcom,rpm-msg-ram";
750 reg = <0x00068000 0x60 651 reg = <0x00068000 0x6000>;
751 }; 652 };
752 653
753 qfprom@74000 { 654 qfprom@74000 {
754 compatible = "qcom,msm !! 655 compatible = "qcom,qfprom";
755 reg = <0x00074000 0x8f 656 reg = <0x00074000 0x8ff>;
756 #address-cells = <1>; 657 #address-cells = <1>;
757 #size-cells = <1>; 658 #size-cells = <1>;
758 659
759 qusb2p_hstx_trim: hstx !! 660 qusb2p_hstx_trim: hstx_trim@24e {
760 reg = <0x24e 0 661 reg = <0x24e 0x2>;
761 bits = <5 4>; 662 bits = <5 4>;
762 }; 663 };
763 664
764 qusb2s_hstx_trim: hstx !! 665 qusb2s_hstx_trim: hstx_trim@24f {
765 reg = <0x24f 0 666 reg = <0x24f 0x1>;
766 bits = <1 4>; 667 bits = <1 4>;
767 }; 668 };
768 669
769 speedbin_efuse: speedb 670 speedbin_efuse: speedbin@133 {
770 reg = <0x133 0 671 reg = <0x133 0x1>;
771 bits = <5 3>; 672 bits = <5 3>;
772 }; 673 };
773 }; 674 };
774 675
775 rng: rng@83000 { 676 rng: rng@83000 {
776 compatible = "qcom,prn 677 compatible = "qcom,prng-ee";
777 reg = <0x00083000 0x10 678 reg = <0x00083000 0x1000>;
778 clocks = <&gcc GCC_PRN 679 clocks = <&gcc GCC_PRNG_AHB_CLK>;
779 clock-names = "core"; 680 clock-names = "core";
780 }; 681 };
781 682
782 gcc: clock-controller@300000 { 683 gcc: clock-controller@300000 {
783 compatible = "qcom,gcc 684 compatible = "qcom,gcc-msm8996";
784 #clock-cells = <1>; 685 #clock-cells = <1>;
785 #reset-cells = <1>; 686 #reset-cells = <1>;
786 #power-domain-cells = 687 #power-domain-cells = <1>;
787 reg = <0x00300000 0x90 688 reg = <0x00300000 0x90000>;
788 689
789 clocks = <&rpmcc RPM_S !! 690 clocks = <&rpmcc RPM_SMD_BB_CLK1>,
790 <&rpmcc RPM_S 691 <&rpmcc RPM_SMD_LN_BB_CLK>,
791 <&sleep_clk>, !! 692 <&sleep_clk>;
792 <&pciephy_0>, !! 693 clock-names = "cxo", "cxo2", "sleep_clk";
793 <&pciephy_1>, <<
794 <&pciephy_2>, <<
795 <&usb3phy>, <<
796 <&ufsphy 0>, <<
797 <&ufsphy 1>, <<
798 <&ufsphy 2>; <<
799 clock-names = "cxo", <<
800 "cxo2", <<
801 "sleep_c <<
802 "pcie_0_ <<
803 "pcie_1_ <<
804 "pcie_2_ <<
805 "usb3_ph <<
806 "ufs_rx_ <<
807 "ufs_rx_ <<
808 "ufs_tx_ <<
809 }; <<
810 <<
811 bimc: interconnect@408000 { <<
812 compatible = "qcom,msm <<
813 reg = <0x00408000 0x5a <<
814 #interconnect-cells = <<
815 }; 694 };
816 695
817 tsens0: thermal-sensor@4a9000 696 tsens0: thermal-sensor@4a9000 {
818 compatible = "qcom,msm 697 compatible = "qcom,msm8996-tsens", "qcom,tsens-v2";
819 reg = <0x004a9000 0x10 698 reg = <0x004a9000 0x1000>, /* TM */
820 <0x004a8000 0x10 699 <0x004a8000 0x1000>; /* SROT */
821 #qcom,sensors = <13>; 700 #qcom,sensors = <13>;
822 interrupts = <GIC_SPI 701 interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
823 <GIC_SPI 702 <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
824 interrupt-names = "upl 703 interrupt-names = "uplow", "critical";
825 #thermal-sensor-cells 704 #thermal-sensor-cells = <1>;
826 }; 705 };
827 706
828 tsens1: thermal-sensor@4ad000 707 tsens1: thermal-sensor@4ad000 {
829 compatible = "qcom,msm 708 compatible = "qcom,msm8996-tsens", "qcom,tsens-v2";
830 reg = <0x004ad000 0x10 709 reg = <0x004ad000 0x1000>, /* TM */
831 <0x004ac000 0x10 710 <0x004ac000 0x1000>; /* SROT */
832 #qcom,sensors = <8>; 711 #qcom,sensors = <8>;
833 interrupts = <GIC_SPI 712 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
834 <GIC_SPI 713 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>;
835 interrupt-names = "upl 714 interrupt-names = "uplow", "critical";
836 #thermal-sensor-cells 715 #thermal-sensor-cells = <1>;
837 }; 716 };
838 717
839 cryptobam: dma-controller@6440 718 cryptobam: dma-controller@644000 {
840 compatible = "qcom,bam 719 compatible = "qcom,bam-v1.7.0";
841 reg = <0x00644000 0x24 720 reg = <0x00644000 0x24000>;
842 interrupts = <GIC_SPI 721 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
843 clocks = <&gcc GCC_CE1 722 clocks = <&gcc GCC_CE1_CLK>;
844 clock-names = "bam_clk 723 clock-names = "bam_clk";
845 #dma-cells = <1>; 724 #dma-cells = <1>;
846 qcom,ee = <0>; 725 qcom,ee = <0>;
847 qcom,controlled-remote 726 qcom,controlled-remotely;
848 }; 727 };
849 728
850 crypto: crypto@67a000 { 729 crypto: crypto@67a000 {
851 compatible = "qcom,cry 730 compatible = "qcom,crypto-v5.4";
852 reg = <0x0067a000 0x60 731 reg = <0x0067a000 0x6000>;
853 clocks = <&gcc GCC_CE1 732 clocks = <&gcc GCC_CE1_AHB_CLK>,
854 <&gcc GCC_CE1 733 <&gcc GCC_CE1_AXI_CLK>,
855 <&gcc GCC_CE1 734 <&gcc GCC_CE1_CLK>;
856 clock-names = "iface", 735 clock-names = "iface", "bus", "core";
857 dmas = <&cryptobam 6>, 736 dmas = <&cryptobam 6>, <&cryptobam 7>;
858 dma-names = "rx", "tx" 737 dma-names = "rx", "tx";
859 }; 738 };
860 739
861 cnoc: interconnect@500000 { !! 740 tcsr_mutex_regs: syscon@740000 {
862 compatible = "qcom,msm !! 741 compatible = "syscon";
863 reg = <0x00500000 0x10 !! 742 reg = <0x00740000 0x40000>;
864 #interconnect-cells = <<
865 }; <<
866 <<
867 snoc: interconnect@524000 { <<
868 compatible = "qcom,msm <<
869 reg = <0x00524000 0x1c <<
870 #interconnect-cells = <<
871 }; <<
872 <<
873 a0noc: interconnect@543000 { <<
874 compatible = "qcom,msm <<
875 reg = <0x00543000 0x60 <<
876 #interconnect-cells = <<
877 clock-names = "aggre0_ <<
878 "aggre0_ <<
879 "aggre0_ <<
880 clocks = <&gcc GCC_AGG <<
881 <&gcc GCC_AGG <<
882 <&gcc GCC_AGG <<
883 power-domains = <&gcc <<
884 }; <<
885 <<
886 a1noc: interconnect@562000 { <<
887 compatible = "qcom,msm <<
888 reg = <0x00562000 0x50 <<
889 #interconnect-cells = <<
890 }; <<
891 <<
892 a2noc: interconnect@583000 { <<
893 compatible = "qcom,msm <<
894 reg = <0x00583000 0x70 <<
895 #interconnect-cells = <<
896 clock-names = "aggre2_ <<
897 clocks = <&gcc GCC_AGG <<
898 <&gcc GCC_UFS <<
899 }; <<
900 <<
901 mnoc: interconnect@5a4000 { <<
902 compatible = "qcom,msm <<
903 reg = <0x005a4000 0x1c <<
904 #interconnect-cells = <<
905 clock-names = "iface"; <<
906 clocks = <&mmcc AHB_CL <<
907 }; <<
908 <<
909 pnoc: interconnect@5c0000 { <<
910 compatible = "qcom,msm <<
911 reg = <0x005c0000 0x30 <<
912 #interconnect-cells = <<
913 }; <<
914 <<
915 tcsr_mutex: hwlock@740000 { <<
916 compatible = "qcom,tcs <<
917 reg = <0x00740000 0x20 <<
918 #hwlock-cells = <1>; <<
919 }; <<
920 <<
921 tcsr_1: syscon@760000 { <<
922 compatible = "qcom,tcs <<
923 reg = <0x00760000 0x20 <<
924 }; 743 };
925 744
926 tcsr_2: syscon@7a0000 { !! 745 tcsr: syscon@7a0000 {
927 compatible = "qcom,tcs 746 compatible = "qcom,tcsr-msm8996", "syscon";
928 reg = <0x007a0000 0x18 747 reg = <0x007a0000 0x18000>;
929 }; 748 };
930 749
931 mmcc: clock-controller@8c0000 750 mmcc: clock-controller@8c0000 {
932 compatible = "qcom,mmc 751 compatible = "qcom,mmcc-msm8996";
933 #clock-cells = <1>; 752 #clock-cells = <1>;
934 #reset-cells = <1>; 753 #reset-cells = <1>;
935 #power-domain-cells = 754 #power-domain-cells = <1>;
936 reg = <0x008c0000 0x40 755 reg = <0x008c0000 0x40000>;
937 clocks = <&xo_board>, <<
938 <&gcc GPLL0>, <<
939 <&gcc GCC_MMS <<
940 <&mdss_dsi0_p <<
941 <&mdss_dsi0_p <<
942 <&mdss_dsi1_p <<
943 <&mdss_dsi1_p <<
944 <&mdss_hdmi_p <<
945 clock-names = "xo", <<
946 "gpll0", <<
947 "gcc_mms <<
948 "dsi0pll <<
949 "dsi0pll <<
950 "dsi1pll <<
951 "dsi1pll <<
952 "hdmipll <<
953 assigned-clocks = <&mm 756 assigned-clocks = <&mmcc MMPLL9_PLL>,
954 <&mm 757 <&mmcc MMPLL1_PLL>,
955 <&mm 758 <&mmcc MMPLL3_PLL>,
956 <&mm 759 <&mmcc MMPLL4_PLL>,
957 <&mm 760 <&mmcc MMPLL5_PLL>;
958 assigned-clock-rates = 761 assigned-clock-rates = <624000000>,
959 762 <810000000>,
960 763 <980000000>,
961 764 <960000000>,
962 765 <825000000>;
963 }; 766 };
964 767
965 mdss: display-subsystem@900000 !! 768 mdss: mdss@900000 {
966 compatible = "qcom,mds 769 compatible = "qcom,mdss";
967 770
968 reg = <0x00900000 0x10 771 reg = <0x00900000 0x1000>,
969 <0x009b0000 0x10 772 <0x009b0000 0x1040>,
970 <0x009b8000 0x10 773 <0x009b8000 0x1040>;
971 reg-names = "mdss_phys 774 reg-names = "mdss_phys",
972 "vbif_phys 775 "vbif_phys",
973 "vbif_nrt_ 776 "vbif_nrt_phys";
974 777
975 power-domains = <&mmcc 778 power-domains = <&mmcc MDSS_GDSC>;
976 interrupts = <GIC_SPI 779 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
977 780
978 interrupt-controller; 781 interrupt-controller;
979 #interrupt-cells = <1> 782 #interrupt-cells = <1>;
980 783
981 clocks = <&mmcc MDSS_A !! 784 clocks = <&mmcc MDSS_AHB_CLK>;
982 <&mmcc MDSS_M !! 785 clock-names = "iface";
983 clock-names = "iface", <<
984 <<
985 resets = <&mmcc MDSS_B <<
986 786
987 #address-cells = <1>; 787 #address-cells = <1>;
988 #size-cells = <1>; 788 #size-cells = <1>;
989 ranges; 789 ranges;
990 790
991 status = "disabled"; 791 status = "disabled";
992 792
993 mdp: display-controlle !! 793 mdp: mdp@901000 {
994 compatible = " !! 794 compatible = "qcom,mdp5";
995 reg = <0x00901 795 reg = <0x00901000 0x90000>;
996 reg-names = "m 796 reg-names = "mdp_phys";
997 797
998 interrupt-pare 798 interrupt-parent = <&mdss>;
999 interrupts = < 799 interrupts = <0>;
1000 800
1001 clocks = <&mm 801 clocks = <&mmcc MDSS_AHB_CLK>,
1002 <&mm 802 <&mmcc MDSS_AXI_CLK>,
1003 <&mm 803 <&mmcc MDSS_MDP_CLK>,
1004 <&mm 804 <&mmcc SMMU_MDP_AXI_CLK>,
1005 <&mm 805 <&mmcc MDSS_VSYNC_CLK>;
1006 clock-names = 806 clock-names = "iface",
1007 807 "bus",
1008 808 "core",
1009 809 "iommu",
1010 810 "vsync";
1011 811
1012 iommus = <&md 812 iommus = <&mdp_smmu 0>;
1013 813
1014 assigned-cloc 814 assigned-clocks = <&mmcc MDSS_MDP_CLK>,
1015 <&mm 815 <&mmcc MDSS_VSYNC_CLK>;
1016 assigned-cloc 816 assigned-clock-rates = <300000000>,
1017 <192 817 <19200000>;
1018 818
1019 interconnects <<
1020 <<
1021 <<
1022 interconnect- <<
1023 <<
1024 ports { 819 ports {
1025 #addr 820 #address-cells = <1>;
1026 #size 821 #size-cells = <0>;
1027 822
1028 port@ 823 port@0 {
1029 824 reg = <0>;
1030 825 mdp5_intf3_out: endpoint {
1031 !! 826 remote-endpoint = <&hdmi_in>;
1032 827 };
1033 }; 828 };
1034 829
1035 port@ 830 port@1 {
1036 831 reg = <1>;
1037 832 mdp5_intf1_out: endpoint {
1038 !! 833 remote-endpoint = <&dsi0_in>;
1039 <<
1040 }; <<
1041 <<
1042 port@ <<
1043 <<
1044 <<
1045 <<
1046 834 };
1047 }; 835 };
1048 }; 836 };
1049 }; 837 };
1050 838
1051 mdss_dsi0: dsi@994000 !! 839 dsi0: dsi@994000 {
1052 compatible = !! 840 compatible = "qcom,mdss-dsi-ctrl";
1053 <<
1054 reg = <0x0099 841 reg = <0x00994000 0x400>;
1055 reg-names = " 842 reg-names = "dsi_ctrl";
1056 843
1057 interrupt-par 844 interrupt-parent = <&mdss>;
1058 interrupts = 845 interrupts = <4>;
1059 846
1060 clocks = <&mm 847 clocks = <&mmcc MDSS_MDP_CLK>,
1061 <&mm 848 <&mmcc MDSS_BYTE0_CLK>,
1062 <&mm 849 <&mmcc MDSS_AHB_CLK>,
1063 <&mm 850 <&mmcc MDSS_AXI_CLK>,
1064 <&mm 851 <&mmcc MMSS_MISC_AHB_CLK>,
1065 <&mm 852 <&mmcc MDSS_PCLK0_CLK>,
1066 <&mm 853 <&mmcc MDSS_ESC0_CLK>;
1067 clock-names = 854 clock-names = "mdp_core",
1068 855 "byte",
1069 856 "iface",
1070 857 "bus",
1071 858 "core_mmss",
1072 859 "pixel",
1073 860 "core";
1074 assigned-cloc <<
1075 assigned-cloc <<
1076 861
1077 phys = <&mdss !! 862 phys = <&dsi0_phy>;
>> 863 phy-names = "dsi";
1078 status = "dis 864 status = "disabled";
1079 865
1080 #address-cell 866 #address-cells = <1>;
1081 #size-cells = 867 #size-cells = <0>;
1082 868
1083 ports { 869 ports {
1084 #addr 870 #address-cells = <1>;
1085 #size 871 #size-cells = <0>;
1086 872
1087 port@ 873 port@0 {
1088 874 reg = <0>;
1089 !! 875 dsi0_in: endpoint {
1090 876 remote-endpoint = <&mdp5_intf1_out>;
1091 877 };
1092 }; 878 };
1093 879
1094 port@ 880 port@1 {
1095 881 reg = <1>;
1096 !! 882 dsi0_out: endpoint {
1097 883 };
1098 }; 884 };
1099 }; 885 };
1100 }; 886 };
1101 887
1102 mdss_dsi0_phy: phy@99 !! 888 dsi0_phy: dsi-phy@994400 {
1103 compatible = 889 compatible = "qcom,dsi-phy-14nm";
1104 reg = <0x0099 890 reg = <0x00994400 0x100>,
1105 <0x0099 891 <0x00994500 0x300>,
1106 <0x0099 892 <0x00994800 0x188>;
1107 reg-names = " 893 reg-names = "dsi_phy",
1108 " 894 "dsi_phy_lane",
1109 " 895 "dsi_pll";
1110 896
1111 #clock-cells 897 #clock-cells = <1>;
1112 #phy-cells = 898 #phy-cells = <0>;
1113 899
1114 clocks = <&mm !! 900 clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_BB_CLK1>;
1115 clock-names = 901 clock-names = "iface", "ref";
1116 status = "dis 902 status = "disabled";
1117 }; 903 };
1118 904
1119 mdss_dsi1: dsi@996000 !! 905 hdmi: hdmi-tx@9a0000 {
1120 compatible = <<
1121 <<
1122 reg = <0x0099 <<
1123 reg-names = " <<
1124 <<
1125 interrupt-par <<
1126 interrupts = <<
1127 <<
1128 clocks = <&mm <<
1129 <&mm <<
1130 <&mm <<
1131 <&mm <<
1132 <&mm <<
1133 <&mm <<
1134 <&mm <<
1135 clock-names = <<
1136 <<
1137 <<
1138 <<
1139 <<
1140 <<
1141 <<
1142 assigned-cloc <<
1143 assigned-cloc <<
1144 <<
1145 phys = <&mdss <<
1146 status = "dis <<
1147 <<
1148 #address-cell <<
1149 #size-cells = <<
1150 <<
1151 ports { <<
1152 #addr <<
1153 #size <<
1154 <<
1155 port@ <<
1156 <<
1157 <<
1158 <<
1159 <<
1160 }; <<
1161 <<
1162 port@ <<
1163 <<
1164 <<
1165 <<
1166 }; <<
1167 }; <<
1168 }; <<
1169 <<
1170 mdss_dsi1_phy: phy@99 <<
1171 compatible = <<
1172 reg = <0x0099 <<
1173 <0x0099 <<
1174 <0x0099 <<
1175 reg-names = " <<
1176 " <<
1177 " <<
1178 <<
1179 #clock-cells <<
1180 #phy-cells = <<
1181 <<
1182 clocks = <&mm <<
1183 clock-names = <<
1184 status = "dis <<
1185 }; <<
1186 <<
1187 mdss_hdmi: hdmi-tx@9a <<
1188 compatible = 906 compatible = "qcom,hdmi-tx-8996";
1189 reg = <0x009a !! 907 reg = <0x009a0000 0x50c>,
1190 <0x0007 !! 908 <0x00070000 0x6158>,
1191 <0x009e !! 909 <0x009e0000 0xfff>;
1192 reg-names = " 910 reg-names = "core_physical",
1193 " 911 "qfprom_physical",
1194 " 912 "hdcp_physical";
1195 913
1196 interrupt-par 914 interrupt-parent = <&mdss>;
1197 interrupts = 915 interrupts = <8>;
1198 916
1199 clocks = <&mm 917 clocks = <&mmcc MDSS_MDP_CLK>,
1200 <&mm 918 <&mmcc MDSS_AHB_CLK>,
1201 <&mm 919 <&mmcc MDSS_HDMI_CLK>,
1202 <&mm 920 <&mmcc MDSS_HDMI_AHB_CLK>,
1203 <&mm 921 <&mmcc MDSS_EXTPCLK_CLK>;
1204 clock-names = 922 clock-names =
1205 "mdp_ 923 "mdp_core",
1206 "ifac 924 "iface",
1207 "core 925 "core",
1208 "alt_ 926 "alt_iface",
1209 "extp 927 "extp";
1210 928
1211 phys = <&mdss !! 929 phys = <&hdmi_phy>;
>> 930 phy-names = "hdmi_phy";
1212 #sound-dai-ce 931 #sound-dai-cells = <1>;
1213 932
1214 status = "dis 933 status = "disabled";
1215 934
1216 ports { 935 ports {
1217 #addr 936 #address-cells = <1>;
1218 #size 937 #size-cells = <0>;
1219 938
1220 port@ 939 port@0 {
1221 940 reg = <0>;
1222 !! 941 hdmi_in: endpoint {
1223 942 remote-endpoint = <&mdp5_intf3_out>;
1224 943 };
1225 }; 944 };
1226 }; 945 };
1227 }; 946 };
1228 947
1229 mdss_hdmi_phy: phy@9a !! 948 hdmi_phy: hdmi-phy@9a0600 {
1230 #phy-cells = 949 #phy-cells = <0>;
1231 compatible = 950 compatible = "qcom,hdmi-phy-8996";
1232 reg = <0x009a 951 reg = <0x009a0600 0x1c4>,
1233 <0x009a 952 <0x009a0a00 0x124>,
1234 <0x009a 953 <0x009a0c00 0x124>,
1235 <0x009a 954 <0x009a0e00 0x124>,
1236 <0x009a 955 <0x009a1000 0x124>,
1237 <0x009a 956 <0x009a1200 0x0c8>;
1238 reg-names = " 957 reg-names = "hdmi_pll",
1239 " 958 "hdmi_tx_l0",
1240 " 959 "hdmi_tx_l1",
1241 " 960 "hdmi_tx_l2",
1242 " 961 "hdmi_tx_l3",
1243 " 962 "hdmi_phy";
1244 963
1245 clocks = <&mm 964 clocks = <&mmcc MDSS_AHB_CLK>,
1246 <&gc !! 965 <&gcc GCC_HDMI_CLKREF_CLK>;
1247 <&xo <<
1248 clock-names = 966 clock-names = "iface",
1249 !! 967 "ref";
1250 <<
1251 <<
1252 #clock-cells <<
1253 968
1254 status = "dis 969 status = "disabled";
1255 }; 970 };
1256 }; 971 };
1257 972
1258 gpu: gpu@b00000 { 973 gpu: gpu@b00000 {
1259 compatible = "qcom,ad 974 compatible = "qcom,adreno-530.2", "qcom,adreno";
1260 975
1261 reg = <0x00b00000 0x3 976 reg = <0x00b00000 0x3f000>;
1262 reg-names = "kgsl_3d0 977 reg-names = "kgsl_3d0_reg_memory";
1263 978
1264 interrupts = <GIC_SPI !! 979 interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;
1265 980
1266 clocks = <&mmcc GPU_G 981 clocks = <&mmcc GPU_GX_GFX3D_CLK>,
1267 <&mmcc GPU_AH 982 <&mmcc GPU_AHB_CLK>,
1268 <&mmcc GPU_GX 983 <&mmcc GPU_GX_RBBMTIMER_CLK>,
1269 <&gcc GCC_BIM 984 <&gcc GCC_BIMC_GFX_CLK>,
1270 <&gcc GCC_MMS 985 <&gcc GCC_MMSS_BIMC_GFX_CLK>;
1271 986
1272 clock-names = "core", 987 clock-names = "core",
1273 "iface", 988 "iface",
1274 "rbbmtimer", 989 "rbbmtimer",
1275 "mem", 990 "mem",
1276 "mem_iface"; 991 "mem_iface";
1277 992
1278 interconnects = <&bim <<
1279 interconnect-names = <<
1280 <<
1281 power-domains = <&mmc 993 power-domains = <&mmcc GPU_GX_GDSC>;
1282 iommus = <&adreno_smm 994 iommus = <&adreno_smmu 0>;
1283 995
1284 nvmem-cells = <&speed 996 nvmem-cells = <&speedbin_efuse>;
1285 nvmem-cell-names = "s 997 nvmem-cell-names = "speed_bin";
1286 998
1287 operating-points-v2 = 999 operating-points-v2 = <&gpu_opp_table>;
1288 1000
1289 status = "disabled"; 1001 status = "disabled";
1290 1002
1291 #cooling-cells = <2>; 1003 #cooling-cells = <2>;
1292 1004
1293 gpu_opp_table: opp-ta 1005 gpu_opp_table: opp-table {
1294 compatible = !! 1006 compatible ="operating-points-v2";
1295 1007
1296 /* 1008 /*
1297 * 624Mhz is !! 1009 * 624Mhz and 560Mhz are only available on speed
1298 * 560Mhz is !! 1010 * bin (1 << 0). All the rest are available on
1299 * All the re !! 1011 * all bins of the hardware
1300 */ 1012 */
1301 opp-624000000 1013 opp-624000000 {
1302 opp-h 1014 opp-hz = /bits/ 64 <624000000>;
1303 opp-s !! 1015 opp-supported-hw = <0x01>;
1304 }; 1016 };
1305 opp-560000000 1017 opp-560000000 {
1306 opp-h 1018 opp-hz = /bits/ 64 <560000000>;
1307 opp-s !! 1019 opp-supported-hw = <0x01>;
1308 }; 1020 };
1309 opp-510000000 1021 opp-510000000 {
1310 opp-h 1022 opp-hz = /bits/ 64 <510000000>;
1311 opp-s !! 1023 opp-supported-hw = <0xFF>;
1312 }; 1024 };
1313 opp-401800000 1025 opp-401800000 {
1314 opp-h 1026 opp-hz = /bits/ 64 <401800000>;
1315 opp-s !! 1027 opp-supported-hw = <0xFF>;
1316 }; 1028 };
1317 opp-315000000 1029 opp-315000000 {
1318 opp-h 1030 opp-hz = /bits/ 64 <315000000>;
1319 opp-s !! 1031 opp-supported-hw = <0xFF>;
1320 }; 1032 };
1321 opp-214000000 1033 opp-214000000 {
1322 opp-h 1034 opp-hz = /bits/ 64 <214000000>;
1323 opp-s !! 1035 opp-supported-hw = <0xFF>;
1324 }; 1036 };
1325 opp-133000000 1037 opp-133000000 {
1326 opp-h 1038 opp-hz = /bits/ 64 <133000000>;
1327 opp-s !! 1039 opp-supported-hw = <0xFF>;
1328 }; 1040 };
1329 }; 1041 };
1330 1042
1331 zap-shader { 1043 zap-shader {
1332 memory-region 1044 memory-region = <&gpu_mem>;
1333 }; 1045 };
1334 }; 1046 };
1335 1047
1336 tlmm: pinctrl@1010000 { 1048 tlmm: pinctrl@1010000 {
1337 compatible = "qcom,ms 1049 compatible = "qcom,msm8996-pinctrl";
1338 reg = <0x01010000 0x3 1050 reg = <0x01010000 0x300000>;
1339 interrupts = <GIC_SPI 1051 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1340 gpio-controller; 1052 gpio-controller;
1341 gpio-ranges = <&tlmm 1053 gpio-ranges = <&tlmm 0 0 150>;
1342 #gpio-cells = <2>; 1054 #gpio-cells = <2>;
1343 interrupt-controller; 1055 interrupt-controller;
1344 #interrupt-cells = <2 1056 #interrupt-cells = <2>;
1345 1057
1346 blsp1_spi1_default: b !! 1058 blsp1_spi1_default: blsp1-spi1-default {
1347 spi-pins { !! 1059 spi {
1348 pins 1060 pins = "gpio0", "gpio1", "gpio3";
1349 funct 1061 function = "blsp_spi1";
1350 drive 1062 drive-strength = <12>;
1351 bias- 1063 bias-disable;
1352 }; 1064 };
1353 1065
1354 cs-pins { !! 1066 cs {
1355 pins 1067 pins = "gpio2";
1356 funct 1068 function = "gpio";
1357 drive 1069 drive-strength = <16>;
1358 bias- 1070 bias-disable;
1359 outpu 1071 output-high;
1360 }; 1072 };
1361 }; 1073 };
1362 1074
1363 blsp1_spi1_sleep: bls !! 1075 blsp1_spi1_sleep: blsp1-spi1-sleep {
1364 pins = "gpio0 1076 pins = "gpio0", "gpio1", "gpio2", "gpio3";
1365 function = "g 1077 function = "gpio";
1366 drive-strengt 1078 drive-strength = <2>;
1367 bias-pull-dow 1079 bias-pull-down;
1368 }; 1080 };
1369 1081
1370 blsp2_uart2_2pins_def !! 1082 blsp2_uart2_2pins_default: blsp2-uart1-2pins {
1371 pins = "gpio4 1083 pins = "gpio4", "gpio5";
1372 function = "b 1084 function = "blsp_uart8";
1373 drive-strengt 1085 drive-strength = <16>;
1374 bias-disable; 1086 bias-disable;
1375 }; 1087 };
1376 1088
1377 blsp2_uart2_2pins_sle !! 1089 blsp2_uart2_2pins_sleep: blsp2-uart1-2pins-sleep {
1378 pins = "gpio4 1090 pins = "gpio4", "gpio5";
1379 function = "g 1091 function = "gpio";
1380 drive-strengt 1092 drive-strength = <2>;
1381 bias-disable; 1093 bias-disable;
1382 }; 1094 };
1383 1095
1384 blsp2_i2c2_default: b !! 1096 blsp2_i2c2_default: blsp2-i2c2 {
1385 pins = "gpio6 1097 pins = "gpio6", "gpio7";
1386 function = "b 1098 function = "blsp_i2c8";
1387 drive-strengt 1099 drive-strength = <16>;
1388 bias-disable; 1100 bias-disable;
1389 }; 1101 };
1390 1102
1391 blsp2_i2c2_sleep: bls !! 1103 blsp2_i2c2_sleep: blsp2-i2c2-sleep {
1392 pins = "gpio6 1104 pins = "gpio6", "gpio7";
1393 function = "g 1105 function = "gpio";
1394 drive-strengt 1106 drive-strength = <2>;
1395 bias-disable; 1107 bias-disable;
1396 }; 1108 };
1397 1109
1398 blsp1_i2c6_default: b !! 1110 cci0_default: cci0-default {
1399 pins = "gpio2 <<
1400 function = "b <<
1401 drive-strengt <<
1402 bias-disable; <<
1403 }; <<
1404 <<
1405 blsp1_i2c6_sleep: bls <<
1406 pins = "gpio2 <<
1407 function = "g <<
1408 drive-strengt <<
1409 bias-pull-up; <<
1410 }; <<
1411 <<
1412 cci0_default: cci0-de <<
1413 pins = "gpio1 1111 pins = "gpio17", "gpio18";
1414 function = "c 1112 function = "cci_i2c";
1415 drive-strengt 1113 drive-strength = <16>;
1416 bias-disable; 1114 bias-disable;
1417 }; 1115 };
1418 1116
1419 camera0_state_on: 1117 camera0_state_on:
1420 camera_rear_default: !! 1118 camera_rear_default: camera-rear-default {
1421 camera0_mclk: !! 1119 camera0_mclk: mclk0 {
1422 pins 1120 pins = "gpio13";
1423 funct 1121 function = "cam_mclk";
1424 drive 1122 drive-strength = <16>;
1425 bias- 1123 bias-disable;
1426 }; 1124 };
1427 1125
1428 camera0_rst: !! 1126 camera0_rst: rst {
1429 pins 1127 pins = "gpio25";
1430 funct 1128 function = "gpio";
1431 drive 1129 drive-strength = <16>;
1432 bias- 1130 bias-disable;
1433 }; 1131 };
1434 1132
1435 camera0_pwdn: !! 1133 camera0_pwdn: pwdn {
1436 pins 1134 pins = "gpio26";
1437 funct 1135 function = "gpio";
1438 drive 1136 drive-strength = <16>;
1439 bias- 1137 bias-disable;
1440 }; 1138 };
1441 }; 1139 };
1442 1140
1443 cci1_default: cci1-de !! 1141 cci1_default: cci1-default {
1444 pins = "gpio1 1142 pins = "gpio19", "gpio20";
1445 function = "c 1143 function = "cci_i2c";
1446 drive-strengt 1144 drive-strength = <16>;
1447 bias-disable; 1145 bias-disable;
1448 }; 1146 };
1449 1147
1450 camera1_state_on: 1148 camera1_state_on:
1451 camera_board_default: !! 1149 camera_board_default: camera-board-default {
1452 mclk1-pins { !! 1150 mclk1 {
1453 pins 1151 pins = "gpio14";
1454 funct 1152 function = "cam_mclk";
1455 drive 1153 drive-strength = <16>;
1456 bias- 1154 bias-disable;
1457 }; 1155 };
1458 1156
1459 pwdn-pins { !! 1157 pwdn {
1460 pins 1158 pins = "gpio98";
1461 funct 1159 function = "gpio";
1462 drive 1160 drive-strength = <16>;
1463 bias- 1161 bias-disable;
1464 }; 1162 };
1465 1163
1466 rst-pins { !! 1164 rst {
1467 pins 1165 pins = "gpio104";
1468 funct 1166 function = "gpio";
1469 drive 1167 drive-strength = <16>;
1470 bias- 1168 bias-disable;
1471 }; 1169 };
1472 }; 1170 };
1473 1171
1474 camera2_state_on: 1172 camera2_state_on:
1475 camera_front_default: !! 1173 camera_front_default: camera-front-default {
1476 camera2_mclk: !! 1174 camera2_mclk: mclk2 {
1477 pins 1175 pins = "gpio15";
1478 funct 1176 function = "cam_mclk";
1479 drive 1177 drive-strength = <16>;
1480 bias- 1178 bias-disable;
1481 }; 1179 };
1482 1180
1483 camera2_rst: !! 1181 camera2_rst: rst {
1484 pins 1182 pins = "gpio23";
1485 funct 1183 function = "gpio";
1486 drive 1184 drive-strength = <16>;
1487 bias- 1185 bias-disable;
1488 }; 1186 };
1489 1187
1490 pwdn-pins { !! 1188 pwdn {
1491 pins 1189 pins = "gpio133";
1492 funct 1190 function = "gpio";
1493 drive 1191 drive-strength = <16>;
1494 bias- 1192 bias-disable;
1495 }; 1193 };
1496 }; 1194 };
1497 1195
1498 pcie0_state_on: pcie0 !! 1196 pcie0_state_on: pcie0-state-on {
1499 perst-pins { !! 1197 perst {
1500 pins 1198 pins = "gpio35";
1501 funct 1199 function = "gpio";
1502 drive 1200 drive-strength = <2>;
1503 bias- 1201 bias-pull-down;
1504 }; 1202 };
1505 1203
1506 clkreq-pins { !! 1204 clkreq {
1507 pins 1205 pins = "gpio36";
1508 funct 1206 function = "pci_e0";
1509 drive 1207 drive-strength = <2>;
1510 bias- 1208 bias-pull-up;
1511 }; 1209 };
1512 1210
1513 wake-pins { !! 1211 wake {
1514 pins 1212 pins = "gpio37";
1515 funct 1213 function = "gpio";
1516 drive 1214 drive-strength = <2>;
1517 bias- 1215 bias-pull-up;
1518 }; 1216 };
1519 }; 1217 };
1520 1218
1521 pcie0_state_off: pcie !! 1219 pcie0_state_off: pcie0-state-off {
1522 perst-pins { !! 1220 perst {
1523 pins 1221 pins = "gpio35";
1524 funct 1222 function = "gpio";
1525 drive 1223 drive-strength = <2>;
1526 bias- 1224 bias-pull-down;
1527 }; 1225 };
1528 1226
1529 clkreq-pins { !! 1227 clkreq {
1530 pins 1228 pins = "gpio36";
1531 funct 1229 function = "gpio";
1532 drive 1230 drive-strength = <2>;
1533 bias- 1231 bias-disable;
1534 }; 1232 };
1535 1233
1536 wake-pins { !! 1234 wake {
1537 pins 1235 pins = "gpio37";
1538 funct 1236 function = "gpio";
1539 drive 1237 drive-strength = <2>;
1540 bias- 1238 bias-disable;
1541 }; 1239 };
1542 }; 1240 };
1543 1241
1544 blsp1_uart2_default: !! 1242 blsp1_uart2_default: blsp1-uart2-default {
1545 pins = "gpio4 1243 pins = "gpio41", "gpio42", "gpio43", "gpio44";
1546 function = "b 1244 function = "blsp_uart2";
1547 drive-strengt 1245 drive-strength = <16>;
1548 bias-disable; 1246 bias-disable;
1549 }; 1247 };
1550 1248
1551 blsp1_uart2_sleep: bl !! 1249 blsp1_uart2_sleep: blsp1-uart2-sleep {
1552 pins = "gpio4 1250 pins = "gpio41", "gpio42", "gpio43", "gpio44";
1553 function = "g 1251 function = "gpio";
1554 drive-strengt 1252 drive-strength = <2>;
1555 bias-disable; 1253 bias-disable;
1556 }; 1254 };
1557 1255
1558 blsp1_i2c3_default: b !! 1256 blsp1_i2c3_default: blsp1-i2c2-default {
1559 pins = "gpio4 1257 pins = "gpio47", "gpio48";
1560 function = "b 1258 function = "blsp_i2c3";
1561 drive-strengt 1259 drive-strength = <16>;
1562 bias-disable; 1260 bias-disable;
1563 }; 1261 };
1564 1262
1565 blsp1_i2c3_sleep: bls !! 1263 blsp1_i2c3_sleep: blsp1-i2c2-sleep {
1566 pins = "gpio4 1264 pins = "gpio47", "gpio48";
1567 function = "g 1265 function = "gpio";
1568 drive-strengt 1266 drive-strength = <2>;
1569 bias-disable; 1267 bias-disable;
1570 }; 1268 };
1571 1269
1572 blsp2_uart3_4pins_def !! 1270 blsp2_uart3_4pins_default: blsp2-uart2-4pins {
1573 pins = "gpio4 1271 pins = "gpio49", "gpio50", "gpio51", "gpio52";
1574 function = "b 1272 function = "blsp_uart9";
1575 drive-strengt 1273 drive-strength = <16>;
1576 bias-disable; 1274 bias-disable;
1577 }; 1275 };
1578 1276
1579 blsp2_uart3_4pins_sle !! 1277 blsp2_uart3_4pins_sleep: blsp2-uart2-4pins-sleep {
1580 pins = "gpio4 1278 pins = "gpio49", "gpio50", "gpio51", "gpio52";
1581 function = "b 1279 function = "blsp_uart9";
1582 drive-strengt 1280 drive-strength = <2>;
1583 bias-disable; 1281 bias-disable;
1584 }; 1282 };
1585 1283
1586 blsp2_i2c3_default: b !! 1284 blsp2_i2c3_default: blsp2-i2c3 {
1587 pins = "gpio5 1285 pins = "gpio51", "gpio52";
1588 function = "b 1286 function = "blsp_i2c9";
1589 drive-strengt 1287 drive-strength = <16>;
1590 bias-disable; 1288 bias-disable;
1591 }; 1289 };
1592 1290
1593 blsp2_i2c3_sleep: bls !! 1291 blsp2_i2c3_sleep: blsp2-i2c3-sleep {
1594 pins = "gpio5 1292 pins = "gpio51", "gpio52";
1595 function = "g 1293 function = "gpio";
1596 drive-strengt 1294 drive-strength = <2>;
1597 bias-disable; 1295 bias-disable;
1598 }; 1296 };
1599 1297
1600 wcd_intr_default: wcd !! 1298 wcd_intr_default: wcd-intr-default{
1601 pins = "gpio5 1299 pins = "gpio54";
1602 function = "g 1300 function = "gpio";
1603 drive-strengt 1301 drive-strength = <2>;
1604 bias-pull-dow 1302 bias-pull-down;
>> 1303 input-enable;
1605 }; 1304 };
1606 1305
1607 blsp2_i2c1_default: b !! 1306 blsp2_i2c1_default: blsp2-i2c1 {
1608 pins = "gpio5 1307 pins = "gpio55", "gpio56";
1609 function = "b 1308 function = "blsp_i2c7";
1610 drive-strengt 1309 drive-strength = <16>;
1611 bias-disable; 1310 bias-disable;
1612 }; 1311 };
1613 1312
1614 blsp2_i2c1_sleep: bls !! 1313 blsp2_i2c1_sleep: blsp2-i2c0-sleep {
1615 pins = "gpio5 1314 pins = "gpio55", "gpio56";
1616 function = "g 1315 function = "gpio";
1617 drive-strengt 1316 drive-strength = <2>;
1618 bias-disable; 1317 bias-disable;
1619 }; 1318 };
1620 1319
1621 blsp2_i2c5_default: b !! 1320 blsp2_i2c5_default: blsp2-i2c5 {
1622 pins = "gpio6 1321 pins = "gpio60", "gpio61";
1623 function = "b 1322 function = "blsp_i2c11";
1624 drive-strengt 1323 drive-strength = <2>;
1625 bias-disable; 1324 bias-disable;
1626 }; 1325 };
1627 1326
1628 /* Sleep state for BL 1327 /* Sleep state for BLSP2_I2C5 is missing.. */
1629 1328
1630 cdc_reset_active: cdc !! 1329 cdc_reset_active: cdc-reset-active {
1631 pins = "gpio6 1330 pins = "gpio64";
1632 function = "g 1331 function = "gpio";
1633 drive-strengt 1332 drive-strength = <16>;
1634 bias-pull-dow 1333 bias-pull-down;
1635 output-high; 1334 output-high;
1636 }; 1335 };
1637 1336
1638 cdc_reset_sleep: cdc- !! 1337 cdc_reset_sleep: cdc-reset-sleep {
1639 pins = "gpio6 1338 pins = "gpio64";
1640 function = "g 1339 function = "gpio";
1641 drive-strengt 1340 drive-strength = <16>;
1642 bias-disable; 1341 bias-disable;
1643 output-low; 1342 output-low;
1644 }; 1343 };
1645 1344
1646 blsp2_spi6_default: b !! 1345 blsp2_spi6_default: blsp2-spi5-default {
1647 spi-pins { !! 1346 spi {
1648 pins 1347 pins = "gpio85", "gpio86", "gpio88";
1649 funct 1348 function = "blsp_spi12";
1650 drive 1349 drive-strength = <12>;
1651 bias- 1350 bias-disable;
1652 }; 1351 };
1653 1352
1654 cs-pins { !! 1353 cs {
1655 pins 1354 pins = "gpio87";
1656 funct 1355 function = "gpio";
1657 drive 1356 drive-strength = <16>;
1658 bias- 1357 bias-disable;
1659 outpu 1358 output-high;
1660 }; 1359 };
1661 }; 1360 };
1662 1361
1663 blsp2_spi6_sleep: bls !! 1362 blsp2_spi6_sleep: blsp2-spi5-sleep {
1664 pins = "gpio8 1363 pins = "gpio85", "gpio86", "gpio87", "gpio88";
1665 function = "g 1364 function = "gpio";
1666 drive-strengt 1365 drive-strength = <2>;
1667 bias-pull-dow 1366 bias-pull-down;
1668 }; 1367 };
1669 1368
1670 blsp2_i2c6_default: b !! 1369 blsp2_i2c6_default: blsp2-i2c6 {
1671 pins = "gpio8 1370 pins = "gpio87", "gpio88";
1672 function = "b 1371 function = "blsp_i2c12";
1673 drive-strengt 1372 drive-strength = <16>;
1674 bias-disable; 1373 bias-disable;
1675 }; 1374 };
1676 1375
1677 blsp2_i2c6_sleep: bls !! 1376 blsp2_i2c6_sleep: blsp2-i2c6-sleep {
1678 pins = "gpio8 1377 pins = "gpio87", "gpio88";
1679 function = "g 1378 function = "gpio";
1680 drive-strengt 1379 drive-strength = <2>;
1681 bias-disable; 1380 bias-disable;
1682 }; 1381 };
1683 1382
1684 pcie1_state_on: pcie1 !! 1383 pcie1_state_on: pcie1-state-on {
1685 perst-pins { !! 1384 perst {
1686 pins 1385 pins = "gpio130";
1687 funct 1386 function = "gpio";
1688 drive 1387 drive-strength = <2>;
1689 bias- 1388 bias-pull-down;
1690 }; 1389 };
1691 1390
1692 clkreq-pins { !! 1391 clkreq {
1693 pins 1392 pins = "gpio131";
1694 funct 1393 function = "pci_e1";
1695 drive 1394 drive-strength = <2>;
1696 bias- 1395 bias-pull-up;
1697 }; 1396 };
1698 1397
1699 wake-pins { !! 1398 wake {
1700 pins 1399 pins = "gpio132";
1701 funct 1400 function = "gpio";
1702 drive 1401 drive-strength = <2>;
1703 bias- 1402 bias-pull-down;
1704 }; 1403 };
1705 }; 1404 };
1706 1405
1707 pcie1_state_off: pcie !! 1406 pcie1_state_off: pcie1-state-off {
1708 /* Perst is m 1407 /* Perst is missing? */
1709 clkreq-pins { !! 1408 clkreq {
1710 pins 1409 pins = "gpio131";
1711 funct 1410 function = "gpio";
1712 drive 1411 drive-strength = <2>;
1713 bias- 1412 bias-disable;
1714 }; 1413 };
1715 1414
1716 wake-pins { !! 1415 wake {
1717 pins 1416 pins = "gpio132";
1718 funct 1417 function = "gpio";
1719 drive 1418 drive-strength = <2>;
1720 bias- 1419 bias-disable;
1721 }; 1420 };
1722 }; 1421 };
1723 1422
1724 pcie2_state_on: pcie2 !! 1423 pcie2_state_on: pcie2-state-on {
1725 perst-pins { !! 1424 perst {
1726 pins 1425 pins = "gpio114";
1727 funct 1426 function = "gpio";
1728 drive 1427 drive-strength = <2>;
1729 bias- 1428 bias-pull-down;
1730 }; 1429 };
1731 1430
1732 clkreq-pins { !! 1431 clkreq {
1733 pins 1432 pins = "gpio115";
1734 funct 1433 function = "pci_e2";
1735 drive 1434 drive-strength = <2>;
1736 bias- 1435 bias-pull-up;
1737 }; 1436 };
1738 1437
1739 wake-pins { !! 1438 wake {
1740 pins 1439 pins = "gpio116";
1741 funct 1440 function = "gpio";
1742 drive 1441 drive-strength = <2>;
1743 bias- 1442 bias-pull-down;
1744 }; 1443 };
1745 }; 1444 };
1746 1445
1747 pcie2_state_off: pcie !! 1446 pcie2_state_off: pcie2-state-off {
1748 /* Perst is m 1447 /* Perst is missing? */
1749 clkreq-pins { !! 1448 clkreq {
1750 pins 1449 pins = "gpio115";
1751 funct 1450 function = "gpio";
1752 drive 1451 drive-strength = <2>;
1753 bias- 1452 bias-disable;
1754 }; 1453 };
1755 1454
1756 wake-pins { !! 1455 wake {
1757 pins 1456 pins = "gpio116";
1758 funct 1457 function = "gpio";
1759 drive 1458 drive-strength = <2>;
1760 bias- 1459 bias-disable;
1761 }; 1460 };
1762 }; 1461 };
1763 1462
1764 sdc1_state_on: sdc1-o !! 1463 sdc1_state_on: sdc1-state-on {
1765 clk-pins { !! 1464 clk {
1766 pins 1465 pins = "sdc1_clk";
1767 bias- 1466 bias-disable;
1768 drive 1467 drive-strength = <16>;
1769 }; 1468 };
1770 1469
1771 cmd-pins { !! 1470 cmd {
1772 pins 1471 pins = "sdc1_cmd";
1773 bias- 1472 bias-pull-up;
1774 drive 1473 drive-strength = <10>;
1775 }; 1474 };
1776 1475
1777 data-pins { !! 1476 data {
1778 pins 1477 pins = "sdc1_data";
1779 bias- 1478 bias-pull-up;
1780 drive 1479 drive-strength = <10>;
1781 }; 1480 };
1782 1481
1783 rclk-pins { !! 1482 rclk {
1784 pins 1483 pins = "sdc1_rclk";
1785 bias- 1484 bias-pull-down;
1786 }; 1485 };
1787 }; 1486 };
1788 1487
1789 sdc1_state_off: sdc1- !! 1488 sdc1_state_off: sdc1-state-off {
1790 clk-pins { !! 1489 clk {
1791 pins 1490 pins = "sdc1_clk";
1792 bias- 1491 bias-disable;
1793 drive 1492 drive-strength = <2>;
1794 }; 1493 };
1795 1494
1796 cmd-pins { !! 1495 cmd {
1797 pins 1496 pins = "sdc1_cmd";
1798 bias- 1497 bias-pull-up;
1799 drive 1498 drive-strength = <2>;
1800 }; 1499 };
1801 1500
1802 data-pins { !! 1501 data {
1803 pins 1502 pins = "sdc1_data";
1804 bias- 1503 bias-pull-up;
1805 drive 1504 drive-strength = <2>;
1806 }; 1505 };
1807 1506
1808 rclk-pins { !! 1507 rclk {
1809 pins 1508 pins = "sdc1_rclk";
1810 bias- 1509 bias-pull-down;
1811 }; 1510 };
1812 }; 1511 };
1813 1512
1814 sdc2_state_on: sdc2-o !! 1513 sdc2_state_on: sdc2-clk-on {
1815 clk-pins { !! 1514 clk {
1816 pins 1515 pins = "sdc2_clk";
1817 bias- 1516 bias-disable;
1818 drive 1517 drive-strength = <16>;
1819 }; 1518 };
1820 1519
1821 cmd-pins { !! 1520 cmd {
1822 pins 1521 pins = "sdc2_cmd";
1823 bias- 1522 bias-pull-up;
1824 drive 1523 drive-strength = <10>;
1825 }; 1524 };
1826 1525
1827 data-pins { !! 1526 data {
1828 pins 1527 pins = "sdc2_data";
1829 bias- 1528 bias-pull-up;
1830 drive 1529 drive-strength = <10>;
1831 }; 1530 };
1832 }; 1531 };
1833 1532
1834 sdc2_state_off: sdc2- !! 1533 sdc2_state_off: sdc2-clk-off {
1835 clk-pins { !! 1534 clk {
1836 pins 1535 pins = "sdc2_clk";
1837 bias- 1536 bias-disable;
1838 drive 1537 drive-strength = <2>;
1839 }; 1538 };
1840 1539
1841 cmd-pins { !! 1540 cmd {
1842 pins 1541 pins = "sdc2_cmd";
1843 bias- 1542 bias-pull-up;
1844 drive 1543 drive-strength = <2>;
1845 }; 1544 };
1846 1545
1847 data-pins { !! 1546 data {
1848 pins 1547 pins = "sdc2_data";
1849 bias- 1548 bias-pull-up;
1850 drive 1549 drive-strength = <2>;
1851 }; 1550 };
1852 }; 1551 };
1853 }; 1552 };
1854 1553
1855 sram@290000 { 1554 sram@290000 {
1856 compatible = "qcom,rp 1555 compatible = "qcom,rpm-stats";
1857 reg = <0x00290000 0x1 1556 reg = <0x00290000 0x10000>;
1858 }; 1557 };
1859 1558
1860 spmi_bus: spmi@400f000 { 1559 spmi_bus: spmi@400f000 {
1861 compatible = "qcom,sp 1560 compatible = "qcom,spmi-pmic-arb";
1862 reg = <0x0400f000 0x1 1561 reg = <0x0400f000 0x1000>,
1863 <0x04400000 0x8 1562 <0x04400000 0x800000>,
1864 <0x04c00000 0x8 1563 <0x04c00000 0x800000>,
1865 <0x05800000 0x2 1564 <0x05800000 0x200000>,
1866 <0x0400a000 0x0 1565 <0x0400a000 0x002100>;
1867 reg-names = "core", " 1566 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1868 interrupt-names = "pe 1567 interrupt-names = "periph_irq";
1869 interrupts = <GIC_SPI 1568 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
1870 qcom,ee = <0>; 1569 qcom,ee = <0>;
1871 qcom,channel = <0>; 1570 qcom,channel = <0>;
1872 #address-cells = <2>; 1571 #address-cells = <2>;
1873 #size-cells = <0>; 1572 #size-cells = <0>;
1874 interrupt-controller; 1573 interrupt-controller;
1875 #interrupt-cells = <4 1574 #interrupt-cells = <4>;
1876 }; 1575 };
1877 1576
1878 bus@0 { !! 1577 agnoc@0 {
1879 power-domains = <&gcc 1578 power-domains = <&gcc AGGRE0_NOC_GDSC>;
1880 compatible = "simple- 1579 compatible = "simple-pm-bus";
1881 #address-cells = <1>; 1580 #address-cells = <1>;
1882 #size-cells = <1>; 1581 #size-cells = <1>;
1883 ranges = <0x0 0x0 0xf !! 1582 ranges;
1884 1583
1885 pcie0: pcie@600000 { 1584 pcie0: pcie@600000 {
1886 compatible = 1585 compatible = "qcom,pcie-msm8996";
1887 status = "dis 1586 status = "disabled";
1888 power-domains 1587 power-domains = <&gcc PCIE0_GDSC>;
1889 bus-range = < 1588 bus-range = <0x00 0xff>;
1890 num-lanes = < 1589 num-lanes = <1>;
1891 1590
1892 reg = <0x0060 1591 reg = <0x00600000 0x2000>,
1893 <0x0c00 1592 <0x0c000000 0xf1d>,
1894 <0x0c00 1593 <0x0c000f20 0xa8>,
1895 <0x0c10 1594 <0x0c100000 0x100000>;
1896 reg-names = " 1595 reg-names = "parf", "dbi", "elbi","config";
1897 1596
1898 phys = <&pcie 1597 phys = <&pciephy_0>;
1899 phy-names = " 1598 phy-names = "pciephy";
1900 1599
1901 #address-cell 1600 #address-cells = <3>;
1902 #size-cells = 1601 #size-cells = <2>;
1903 ranges = <0x0 !! 1602 ranges = <0x01000000 0x0 0x0c200000 0x0c200000 0x0 0x100000>,
1904 <0x0 !! 1603 <0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>;
1905 1604
1906 device_type = 1605 device_type = "pci";
1907 1606
1908 interrupts = 1607 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
1909 interrupt-nam 1608 interrupt-names = "msi";
1910 #interrupt-ce 1609 #interrupt-cells = <1>;
1911 interrupt-map 1610 interrupt-map-mask = <0 0 0 0x7>;
1912 interrupt-map 1611 interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1913 1612 <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1914 1613 <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1915 1614 <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1916 1615
1917 pinctrl-names 1616 pinctrl-names = "default", "sleep";
1918 pinctrl-0 = < 1617 pinctrl-0 = <&pcie0_state_on>;
1919 pinctrl-1 = < 1618 pinctrl-1 = <&pcie0_state_off>;
1920 1619
1921 linux,pci-dom 1620 linux,pci-domain = <0>;
1922 1621
1923 clocks = <&gc 1622 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
1924 <&gcc 1623 <&gcc GCC_PCIE_0_AUX_CLK>,
1925 <&gcc 1624 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1926 <&gcc 1625 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1927 <&gcc 1626 <&gcc GCC_PCIE_0_SLV_AXI_CLK>;
1928 1627
1929 clock-names = !! 1628 clock-names = "pipe",
1930 1629 "aux",
1931 1630 "cfg",
1932 1631 "bus_master",
1933 1632 "bus_slave";
1934 1633
1935 pcie@0 { <<
1936 devic <<
1937 reg = <<
1938 bus-r <<
1939 <<
1940 #addr <<
1941 #size <<
1942 range <<
1943 }; <<
1944 }; 1634 };
1945 1635
1946 pcie1: pcie@608000 { 1636 pcie1: pcie@608000 {
1947 compatible = 1637 compatible = "qcom,pcie-msm8996";
1948 power-domains 1638 power-domains = <&gcc PCIE1_GDSC>;
1949 bus-range = < 1639 bus-range = <0x00 0xff>;
1950 num-lanes = < 1640 num-lanes = <1>;
1951 1641
1952 status = "dis !! 1642 status = "disabled";
1953 1643
1954 reg = <0x0060 1644 reg = <0x00608000 0x2000>,
1955 <0x0d00 1645 <0x0d000000 0xf1d>,
1956 <0x0d00 1646 <0x0d000f20 0xa8>,
1957 <0x0d10 1647 <0x0d100000 0x100000>;
1958 1648
1959 reg-names = " 1649 reg-names = "parf", "dbi", "elbi","config";
1960 1650
1961 phys = <&pcie 1651 phys = <&pciephy_1>;
1962 phy-names = " 1652 phy-names = "pciephy";
1963 1653
1964 #address-cell 1654 #address-cells = <3>;
1965 #size-cells = 1655 #size-cells = <2>;
1966 ranges = <0x0 !! 1656 ranges = <0x01000000 0x0 0x0d200000 0x0d200000 0x0 0x100000>,
1967 <0x0 !! 1657 <0x02000000 0x0 0x0d300000 0x0d300000 0x0 0xd00000>;
1968 1658
1969 device_type = 1659 device_type = "pci";
1970 1660
1971 interrupts = 1661 interrupts = <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>;
1972 interrupt-nam 1662 interrupt-names = "msi";
1973 #interrupt-ce 1663 #interrupt-cells = <1>;
1974 interrupt-map 1664 interrupt-map-mask = <0 0 0 0x7>;
1975 interrupt-map 1665 interrupt-map = <0 0 0 1 &intc 0 272 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1976 1666 <0 0 0 2 &intc 0 273 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1977 1667 <0 0 0 3 &intc 0 274 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1978 1668 <0 0 0 4 &intc 0 275 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1979 1669
1980 pinctrl-names 1670 pinctrl-names = "default", "sleep";
1981 pinctrl-0 = < 1671 pinctrl-0 = <&pcie1_state_on>;
1982 pinctrl-1 = < 1672 pinctrl-1 = <&pcie1_state_off>;
1983 1673
1984 linux,pci-dom 1674 linux,pci-domain = <1>;
1985 1675
1986 clocks = <&gc 1676 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
1987 <&gcc 1677 <&gcc GCC_PCIE_1_AUX_CLK>,
1988 <&gcc 1678 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1989 <&gcc 1679 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
1990 <&gcc 1680 <&gcc GCC_PCIE_1_SLV_AXI_CLK>;
1991 1681
1992 clock-names = !! 1682 clock-names = "pipe",
1993 1683 "aux",
1994 1684 "cfg",
1995 1685 "bus_master",
1996 1686 "bus_slave";
1997 <<
1998 pcie@0 { <<
1999 devic <<
2000 reg = <<
2001 bus-r <<
2002 <<
2003 #addr <<
2004 #size <<
2005 range <<
2006 }; <<
2007 }; 1687 };
2008 1688
2009 pcie2: pcie@610000 { 1689 pcie2: pcie@610000 {
2010 compatible = 1690 compatible = "qcom,pcie-msm8996";
2011 power-domains 1691 power-domains = <&gcc PCIE2_GDSC>;
2012 bus-range = < 1692 bus-range = <0x00 0xff>;
2013 num-lanes = < 1693 num-lanes = <1>;
2014 status = "dis 1694 status = "disabled";
2015 reg = <0x0061 1695 reg = <0x00610000 0x2000>,
2016 <0x0e00 1696 <0x0e000000 0xf1d>,
2017 <0x0e00 1697 <0x0e000f20 0xa8>,
2018 <0x0e10 1698 <0x0e100000 0x100000>;
2019 1699
2020 reg-names = " 1700 reg-names = "parf", "dbi", "elbi","config";
2021 1701
2022 phys = <&pcie 1702 phys = <&pciephy_2>;
2023 phy-names = " 1703 phy-names = "pciephy";
2024 1704
2025 #address-cell 1705 #address-cells = <3>;
2026 #size-cells = 1706 #size-cells = <2>;
2027 ranges = <0x0 !! 1707 ranges = <0x01000000 0x0 0x0e200000 0x0e200000 0x0 0x100000>,
2028 <0x0 !! 1708 <0x02000000 0x0 0x0e300000 0x0e300000 0x0 0x1d00000>;
2029 1709
2030 device_type = 1710 device_type = "pci";
2031 1711
2032 interrupts = 1712 interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
2033 interrupt-nam 1713 interrupt-names = "msi";
2034 #interrupt-ce 1714 #interrupt-cells = <1>;
2035 interrupt-map 1715 interrupt-map-mask = <0 0 0 0x7>;
2036 interrupt-map 1716 interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2037 1717 <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2038 1718 <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2039 1719 <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2040 1720
2041 pinctrl-names 1721 pinctrl-names = "default", "sleep";
2042 pinctrl-0 = < 1722 pinctrl-0 = <&pcie2_state_on>;
2043 pinctrl-1 = < 1723 pinctrl-1 = <&pcie2_state_off>;
2044 1724
2045 linux,pci-dom 1725 linux,pci-domain = <2>;
2046 clocks = <&gc 1726 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,
2047 <&gcc 1727 <&gcc GCC_PCIE_2_AUX_CLK>,
2048 <&gcc 1728 <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
2049 <&gcc 1729 <&gcc GCC_PCIE_2_MSTR_AXI_CLK>,
2050 <&gcc 1730 <&gcc GCC_PCIE_2_SLV_AXI_CLK>;
2051 1731
2052 clock-names = !! 1732 clock-names = "pipe",
2053 1733 "aux",
2054 1734 "cfg",
2055 1735 "bus_master",
2056 1736 "bus_slave";
2057 <<
2058 pcie@0 { <<
2059 devic <<
2060 reg = <<
2061 bus-r <<
2062 <<
2063 #addr <<
2064 #size <<
2065 range <<
2066 }; <<
2067 }; 1737 };
2068 }; 1738 };
2069 1739
2070 ufshc: ufshc@624000 { 1740 ufshc: ufshc@624000 {
2071 compatible = "qcom,ms 1741 compatible = "qcom,msm8996-ufshc", "qcom,ufshc",
2072 "jedec,u 1742 "jedec,ufs-2.0";
2073 reg = <0x00624000 0x2 1743 reg = <0x00624000 0x2500>;
2074 interrupts = <GIC_SPI 1744 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
2075 1745
2076 phys = <&ufsphy>; !! 1746 phys = <&ufsphy_lane>;
2077 phy-names = "ufsphy"; 1747 phy-names = "ufsphy";
2078 1748
2079 power-domains = <&gcc 1749 power-domains = <&gcc UFS_GDSC>;
2080 1750
2081 clock-names = 1751 clock-names =
>> 1752 "core_clk_src",
2082 "core_clk", 1753 "core_clk",
2083 "bus_clk", 1754 "bus_clk",
2084 "bus_aggr_clk 1755 "bus_aggr_clk",
2085 "iface_clk", 1756 "iface_clk",
>> 1757 "core_clk_unipro_src",
2086 "core_clk_uni 1758 "core_clk_unipro",
2087 "core_clk_ice 1759 "core_clk_ice",
2088 "ref_clk", 1760 "ref_clk",
2089 "tx_lane0_syn 1761 "tx_lane0_sync_clk",
2090 "rx_lane0_syn 1762 "rx_lane0_sync_clk";
2091 clocks = 1763 clocks =
>> 1764 <&gcc UFS_AXI_CLK_SRC>,
2092 <&gcc GCC_UFS 1765 <&gcc GCC_UFS_AXI_CLK>,
2093 <&gcc GCC_SYS 1766 <&gcc GCC_SYS_NOC_UFS_AXI_CLK>,
2094 <&gcc GCC_AGG 1767 <&gcc GCC_AGGRE2_UFS_AXI_CLK>,
2095 <&gcc GCC_UFS 1768 <&gcc GCC_UFS_AHB_CLK>,
>> 1769 <&gcc UFS_ICE_CORE_CLK_SRC>,
2096 <&gcc GCC_UFS 1770 <&gcc GCC_UFS_UNIPRO_CORE_CLK>,
2097 <&gcc GCC_UFS 1771 <&gcc GCC_UFS_ICE_CORE_CLK>,
2098 <&rpmcc RPM_S 1772 <&rpmcc RPM_SMD_LN_BB_CLK>,
2099 <&gcc GCC_UFS 1773 <&gcc GCC_UFS_TX_SYMBOL_0_CLK>,
2100 <&gcc GCC_UFS 1774 <&gcc GCC_UFS_RX_SYMBOL_0_CLK>;
2101 freq-table-hz = 1775 freq-table-hz =
2102 <100000000 20 1776 <100000000 200000000>,
2103 <0 0>, 1777 <0 0>,
2104 <0 0>, 1778 <0 0>,
2105 <0 0>, 1779 <0 0>,
2106 <75000000 150 !! 1780 <0 0>,
2107 <150000000 30 1781 <150000000 300000000>,
2108 <0 0>, 1782 <0 0>,
2109 <0 0>, 1783 <0 0>,
>> 1784 <0 0>,
>> 1785 <0 0>,
2110 <0 0>; 1786 <0 0>;
2111 1787
2112 interconnects = <&a2n <<
2113 <&bim <<
2114 interconnect-names = <<
2115 <<
2116 lanes-per-direction = 1788 lanes-per-direction = <1>;
2117 #reset-cells = <1>; 1789 #reset-cells = <1>;
2118 status = "disabled"; 1790 status = "disabled";
>> 1791
>> 1792 ufs_variant {
>> 1793 compatible = "qcom,ufs_variant";
>> 1794 };
2119 }; 1795 };
2120 1796
2121 ufsphy: phy@627000 { 1797 ufsphy: phy@627000 {
2122 compatible = "qcom,ms 1798 compatible = "qcom,msm8996-qmp-ufs-phy";
2123 reg = <0x00627000 0x1 !! 1799 reg = <0x00627000 0x1c4>;
>> 1800 #address-cells = <1>;
>> 1801 #size-cells = <1>;
>> 1802 ranges;
2124 1803
2125 clocks = <&rpmcc RPM_ !! 1804 clocks = <&gcc GCC_UFS_CLKREF_CLK>;
2126 clock-names = "ref", !! 1805 clock-names = "ref";
2127 1806
2128 resets = <&ufshc 0>; 1807 resets = <&ufshc 0>;
2129 reset-names = "ufsphy 1808 reset-names = "ufsphy";
2130 <<
2131 #clock-cells = <1>; <<
2132 #phy-cells = <0>; <<
2133 <<
2134 status = "disabled"; 1809 status = "disabled";
>> 1810
>> 1811 ufsphy_lane: phy@627400 {
>> 1812 reg = <0x627400 0x12c>,
>> 1813 <0x627600 0x200>,
>> 1814 <0x627c00 0x1b4>;
>> 1815 #phy-cells = <0>;
>> 1816 };
2135 }; 1817 };
2136 1818
2137 camss: camss@a34000 { !! 1819 camss: camss@a00000 {
2138 compatible = "qcom,ms 1820 compatible = "qcom,msm8996-camss";
2139 reg = <0x00a34000 0x1 1821 reg = <0x00a34000 0x1000>,
2140 <0x00a00030 0x4 1822 <0x00a00030 0x4>,
2141 <0x00a35000 0x1 1823 <0x00a35000 0x1000>,
2142 <0x00a00038 0x4 1824 <0x00a00038 0x4>,
2143 <0x00a36000 0x1 1825 <0x00a36000 0x1000>,
2144 <0x00a00040 0x4 1826 <0x00a00040 0x4>,
2145 <0x00a30000 0x1 1827 <0x00a30000 0x100>,
2146 <0x00a30400 0x1 1828 <0x00a30400 0x100>,
2147 <0x00a30800 0x1 1829 <0x00a30800 0x100>,
2148 <0x00a30c00 0x1 1830 <0x00a30c00 0x100>,
2149 <0x00a31000 0x5 1831 <0x00a31000 0x500>,
2150 <0x00a00020 0x1 1832 <0x00a00020 0x10>,
2151 <0x00a10000 0x1 1833 <0x00a10000 0x1000>,
2152 <0x00a14000 0x1 1834 <0x00a14000 0x1000>;
2153 reg-names = "csiphy0" 1835 reg-names = "csiphy0",
2154 "csiphy0_clk_ 1836 "csiphy0_clk_mux",
2155 "csiphy1", 1837 "csiphy1",
2156 "csiphy1_clk_ 1838 "csiphy1_clk_mux",
2157 "csiphy2", 1839 "csiphy2",
2158 "csiphy2_clk_ 1840 "csiphy2_clk_mux",
2159 "csid0", 1841 "csid0",
2160 "csid1", 1842 "csid1",
2161 "csid2", 1843 "csid2",
2162 "csid3", 1844 "csid3",
2163 "ispif", 1845 "ispif",
2164 "csi_clk_mux" 1846 "csi_clk_mux",
2165 "vfe0", 1847 "vfe0",
2166 "vfe1"; 1848 "vfe1";
2167 interrupts = <GIC_SPI 1849 interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
2168 <GIC_SPI 79 I 1850 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
2169 <GIC_SPI 80 I 1851 <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>,
2170 <GIC_SPI 296 1852 <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>,
2171 <GIC_SPI 297 1853 <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>,
2172 <GIC_SPI 298 1854 <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>,
2173 <GIC_SPI 299 1855 <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>,
2174 <GIC_SPI 309 1856 <GIC_SPI 309 IRQ_TYPE_EDGE_RISING>,
2175 <GIC_SPI 314 1857 <GIC_SPI 314 IRQ_TYPE_EDGE_RISING>,
2176 <GIC_SPI 315 1858 <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>;
2177 interrupt-names = "cs 1859 interrupt-names = "csiphy0",
2178 "csiphy1", 1860 "csiphy1",
2179 "csiphy2", 1861 "csiphy2",
2180 "csid0", 1862 "csid0",
2181 "csid1", 1863 "csid1",
2182 "csid2", 1864 "csid2",
2183 "csid3", 1865 "csid3",
2184 "ispif", 1866 "ispif",
2185 "vfe0", 1867 "vfe0",
2186 "vfe1"; 1868 "vfe1";
2187 power-domains = <&mmc 1869 power-domains = <&mmcc VFE0_GDSC>,
2188 <&mmc 1870 <&mmcc VFE1_GDSC>;
2189 clocks = <&mmcc CAMSS 1871 clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
2190 <&mmcc CAMSS_ 1872 <&mmcc CAMSS_ISPIF_AHB_CLK>,
2191 <&mmcc CAMSS_ 1873 <&mmcc CAMSS_CSI0PHYTIMER_CLK>,
2192 <&mmcc CAMSS_ 1874 <&mmcc CAMSS_CSI1PHYTIMER_CLK>,
2193 <&mmcc CAMSS_ 1875 <&mmcc CAMSS_CSI2PHYTIMER_CLK>,
2194 <&mmcc CAMSS_ 1876 <&mmcc CAMSS_CSI0_AHB_CLK>,
2195 <&mmcc CAMSS_ 1877 <&mmcc CAMSS_CSI0_CLK>,
2196 <&mmcc CAMSS_ 1878 <&mmcc CAMSS_CSI0PHY_CLK>,
2197 <&mmcc CAMSS_ 1879 <&mmcc CAMSS_CSI0PIX_CLK>,
2198 <&mmcc CAMSS_ 1880 <&mmcc CAMSS_CSI0RDI_CLK>,
2199 <&mmcc CAMSS_ 1881 <&mmcc CAMSS_CSI1_AHB_CLK>,
2200 <&mmcc CAMSS_ 1882 <&mmcc CAMSS_CSI1_CLK>,
2201 <&mmcc CAMSS_ 1883 <&mmcc CAMSS_CSI1PHY_CLK>,
2202 <&mmcc CAMSS_ 1884 <&mmcc CAMSS_CSI1PIX_CLK>,
2203 <&mmcc CAMSS_ 1885 <&mmcc CAMSS_CSI1RDI_CLK>,
2204 <&mmcc CAMSS_ 1886 <&mmcc CAMSS_CSI2_AHB_CLK>,
2205 <&mmcc CAMSS_ 1887 <&mmcc CAMSS_CSI2_CLK>,
2206 <&mmcc CAMSS_ 1888 <&mmcc CAMSS_CSI2PHY_CLK>,
2207 <&mmcc CAMSS_ 1889 <&mmcc CAMSS_CSI2PIX_CLK>,
2208 <&mmcc CAMSS_ 1890 <&mmcc CAMSS_CSI2RDI_CLK>,
2209 <&mmcc CAMSS_ 1891 <&mmcc CAMSS_CSI3_AHB_CLK>,
2210 <&mmcc CAMSS_ 1892 <&mmcc CAMSS_CSI3_CLK>,
2211 <&mmcc CAMSS_ 1893 <&mmcc CAMSS_CSI3PHY_CLK>,
2212 <&mmcc CAMSS_ 1894 <&mmcc CAMSS_CSI3PIX_CLK>,
2213 <&mmcc CAMSS_ 1895 <&mmcc CAMSS_CSI3RDI_CLK>,
2214 <&mmcc CAMSS_ 1896 <&mmcc CAMSS_AHB_CLK>,
2215 <&mmcc CAMSS_ 1897 <&mmcc CAMSS_VFE0_CLK>,
2216 <&mmcc CAMSS_ 1898 <&mmcc CAMSS_CSI_VFE0_CLK>,
2217 <&mmcc CAMSS_ 1899 <&mmcc CAMSS_VFE0_AHB_CLK>,
2218 <&mmcc CAMSS_ 1900 <&mmcc CAMSS_VFE0_STREAM_CLK>,
2219 <&mmcc CAMSS_ 1901 <&mmcc CAMSS_VFE1_CLK>,
2220 <&mmcc CAMSS_ 1902 <&mmcc CAMSS_CSI_VFE1_CLK>,
2221 <&mmcc CAMSS_ 1903 <&mmcc CAMSS_VFE1_AHB_CLK>,
2222 <&mmcc CAMSS_ 1904 <&mmcc CAMSS_VFE1_STREAM_CLK>,
2223 <&mmcc CAMSS_ 1905 <&mmcc CAMSS_VFE_AHB_CLK>,
2224 <&mmcc CAMSS_ 1906 <&mmcc CAMSS_VFE_AXI_CLK>;
2225 clock-names = "top_ah 1907 clock-names = "top_ahb",
2226 "ispif_ahb", 1908 "ispif_ahb",
2227 "csiphy0_time 1909 "csiphy0_timer",
2228 "csiphy1_time 1910 "csiphy1_timer",
2229 "csiphy2_time 1911 "csiphy2_timer",
2230 "csi0_ahb", 1912 "csi0_ahb",
2231 "csi0", 1913 "csi0",
2232 "csi0_phy", 1914 "csi0_phy",
2233 "csi0_pix", 1915 "csi0_pix",
2234 "csi0_rdi", 1916 "csi0_rdi",
2235 "csi1_ahb", 1917 "csi1_ahb",
2236 "csi1", 1918 "csi1",
2237 "csi1_phy", 1919 "csi1_phy",
2238 "csi1_pix", 1920 "csi1_pix",
2239 "csi1_rdi", 1921 "csi1_rdi",
2240 "csi2_ahb", 1922 "csi2_ahb",
2241 "csi2", 1923 "csi2",
2242 "csi2_phy", 1924 "csi2_phy",
2243 "csi2_pix", 1925 "csi2_pix",
2244 "csi2_rdi", 1926 "csi2_rdi",
2245 "csi3_ahb", 1927 "csi3_ahb",
2246 "csi3", 1928 "csi3",
2247 "csi3_phy", 1929 "csi3_phy",
2248 "csi3_pix", 1930 "csi3_pix",
2249 "csi3_rdi", 1931 "csi3_rdi",
2250 "ahb", 1932 "ahb",
2251 "vfe0", 1933 "vfe0",
2252 "csi_vfe0", 1934 "csi_vfe0",
2253 "vfe0_ahb", 1935 "vfe0_ahb",
2254 "vfe0_stream" 1936 "vfe0_stream",
2255 "vfe1", 1937 "vfe1",
2256 "csi_vfe1", 1938 "csi_vfe1",
2257 "vfe1_ahb", 1939 "vfe1_ahb",
2258 "vfe1_stream" 1940 "vfe1_stream",
2259 "vfe_ahb", 1941 "vfe_ahb",
2260 "vfe_axi"; 1942 "vfe_axi";
2261 iommus = <&vfe_smmu 0 1943 iommus = <&vfe_smmu 0>,
2262 <&vfe_smmu 1 1944 <&vfe_smmu 1>,
2263 <&vfe_smmu 2 1945 <&vfe_smmu 2>,
2264 <&vfe_smmu 3 1946 <&vfe_smmu 3>;
2265 status = "disabled"; 1947 status = "disabled";
2266 ports { 1948 ports {
2267 #address-cell 1949 #address-cells = <1>;
2268 #size-cells = 1950 #size-cells = <0>;
2269 }; 1951 };
2270 }; 1952 };
2271 1953
2272 cci: cci@a0c000 { 1954 cci: cci@a0c000 {
2273 compatible = "qcom,ms 1955 compatible = "qcom,msm8996-cci";
2274 #address-cells = <1>; 1956 #address-cells = <1>;
2275 #size-cells = <0>; 1957 #size-cells = <0>;
2276 reg = <0xa0c000 0x100 1958 reg = <0xa0c000 0x1000>;
2277 interrupts = <GIC_SPI 1959 interrupts = <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>;
2278 power-domains = <&mmc 1960 power-domains = <&mmcc CAMSS_GDSC>;
2279 clocks = <&mmcc CAMSS 1961 clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
2280 <&mmcc CAMSS 1962 <&mmcc CAMSS_CCI_AHB_CLK>,
2281 <&mmcc CAMSS 1963 <&mmcc CAMSS_CCI_CLK>,
2282 <&mmcc CAMSS 1964 <&mmcc CAMSS_AHB_CLK>;
2283 clock-names = "camss_ 1965 clock-names = "camss_top_ahb",
2284 "cci_ah 1966 "cci_ahb",
2285 "cci", 1967 "cci",
2286 "camss_ 1968 "camss_ahb";
2287 assigned-clocks = <&m 1969 assigned-clocks = <&mmcc CAMSS_CCI_AHB_CLK>,
2288 <&m 1970 <&mmcc CAMSS_CCI_CLK>;
2289 assigned-clock-rates 1971 assigned-clock-rates = <80000000>, <37500000>;
2290 pinctrl-names = "defa 1972 pinctrl-names = "default";
2291 pinctrl-0 = <&cci0_de 1973 pinctrl-0 = <&cci0_default &cci1_default>;
2292 status = "disabled"; 1974 status = "disabled";
2293 1975
2294 cci_i2c0: i2c-bus@0 { 1976 cci_i2c0: i2c-bus@0 {
2295 reg = <0>; 1977 reg = <0>;
2296 clock-frequen 1978 clock-frequency = <400000>;
2297 #address-cell 1979 #address-cells = <1>;
2298 #size-cells = 1980 #size-cells = <0>;
2299 }; 1981 };
2300 1982
2301 cci_i2c1: i2c-bus@1 { 1983 cci_i2c1: i2c-bus@1 {
2302 reg = <1>; 1984 reg = <1>;
2303 clock-frequen 1985 clock-frequency = <400000>;
2304 #address-cell 1986 #address-cells = <1>;
2305 #size-cells = 1987 #size-cells = <0>;
2306 }; 1988 };
2307 }; 1989 };
2308 1990
2309 adreno_smmu: iommu@b40000 { 1991 adreno_smmu: iommu@b40000 {
2310 compatible = "qcom,ms 1992 compatible = "qcom,msm8996-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
2311 reg = <0x00b40000 0x1 1993 reg = <0x00b40000 0x10000>;
2312 1994
2313 #global-interrupts = 1995 #global-interrupts = <1>;
2314 interrupts = <GIC_SPI 1996 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
2315 <GIC_SPI 1997 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
2316 <GIC_SPI 1998 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
2317 #iommu-cells = <1>; 1999 #iommu-cells = <1>;
2318 2000
2319 clocks = <&gcc GCC_MM !! 2001 clocks = <&mmcc GPU_AHB_CLK>,
2320 <&mmcc GPU_A !! 2002 <&gcc GCC_MMSS_BIMC_GFX_CLK>;
2321 clock-names = "bus", !! 2003 clock-names = "iface", "bus";
2322 2004
2323 power-domains = <&mmc 2005 power-domains = <&mmcc GPU_GDSC>;
2324 }; 2006 };
2325 2007
2326 venus: video-codec@c00000 { 2008 venus: video-codec@c00000 {
2327 compatible = "qcom,ms 2009 compatible = "qcom,msm8996-venus";
2328 reg = <0x00c00000 0xf 2010 reg = <0x00c00000 0xff000>;
2329 interrupts = <GIC_SPI 2011 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
2330 power-domains = <&mmc 2012 power-domains = <&mmcc VENUS_GDSC>;
2331 clocks = <&mmcc VIDEO 2013 clocks = <&mmcc VIDEO_CORE_CLK>,
2332 <&mmcc VIDEO 2014 <&mmcc VIDEO_AHB_CLK>,
2333 <&mmcc VIDEO 2015 <&mmcc VIDEO_AXI_CLK>,
2334 <&mmcc VIDEO 2016 <&mmcc VIDEO_MAXI_CLK>;
2335 clock-names = "core", 2017 clock-names = "core", "iface", "bus", "mbus";
2336 interconnects = <&mno <<
2337 <&bim <<
2338 interconnect-names = <<
2339 iommus = <&venus_smmu 2018 iommus = <&venus_smmu 0x00>,
2340 <&venus_smmu 2019 <&venus_smmu 0x01>,
2341 <&venus_smmu 2020 <&venus_smmu 0x0a>,
2342 <&venus_smmu 2021 <&venus_smmu 0x07>,
2343 <&venus_smmu 2022 <&venus_smmu 0x0e>,
2344 <&venus_smmu 2023 <&venus_smmu 0x0f>,
2345 <&venus_smmu 2024 <&venus_smmu 0x08>,
2346 <&venus_smmu 2025 <&venus_smmu 0x09>,
2347 <&venus_smmu 2026 <&venus_smmu 0x0b>,
2348 <&venus_smmu 2027 <&venus_smmu 0x0c>,
2349 <&venus_smmu 2028 <&venus_smmu 0x0d>,
2350 <&venus_smmu 2029 <&venus_smmu 0x10>,
2351 <&venus_smmu 2030 <&venus_smmu 0x11>,
2352 <&venus_smmu 2031 <&venus_smmu 0x21>,
2353 <&venus_smmu 2032 <&venus_smmu 0x28>,
2354 <&venus_smmu 2033 <&venus_smmu 0x29>,
2355 <&venus_smmu 2034 <&venus_smmu 0x2b>,
2356 <&venus_smmu 2035 <&venus_smmu 0x2c>,
2357 <&venus_smmu 2036 <&venus_smmu 0x2d>,
2358 <&venus_smmu 2037 <&venus_smmu 0x31>;
2359 memory-region = <&ven 2038 memory-region = <&venus_mem>;
2360 status = "disabled"; 2039 status = "disabled";
2361 2040
2362 video-decoder { 2041 video-decoder {
2363 compatible = 2042 compatible = "venus-decoder";
2364 clocks = <&mm 2043 clocks = <&mmcc VIDEO_SUBCORE0_CLK>;
2365 clock-names = 2044 clock-names = "core";
2366 power-domains 2045 power-domains = <&mmcc VENUS_CORE0_GDSC>;
2367 }; 2046 };
2368 2047
2369 video-encoder { 2048 video-encoder {
2370 compatible = 2049 compatible = "venus-encoder";
2371 clocks = <&mm 2050 clocks = <&mmcc VIDEO_SUBCORE1_CLK>;
2372 clock-names = 2051 clock-names = "core";
2373 power-domains 2052 power-domains = <&mmcc VENUS_CORE1_GDSC>;
2374 }; 2053 };
2375 }; 2054 };
2376 2055
2377 mdp_smmu: iommu@d00000 { 2056 mdp_smmu: iommu@d00000 {
2378 compatible = "qcom,ms 2057 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2379 reg = <0x00d00000 0x1 2058 reg = <0x00d00000 0x10000>;
2380 2059
2381 #global-interrupts = 2060 #global-interrupts = <1>;
2382 interrupts = <GIC_SPI 2061 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
2383 <GIC_SPI 2062 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
2384 <GIC_SPI 2063 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
2385 #iommu-cells = <1>; 2064 #iommu-cells = <1>;
2386 clocks = <&mmcc SMMU_ !! 2065 clocks = <&mmcc SMMU_MDP_AHB_CLK>,
2387 <&mmcc SMMU_ !! 2066 <&mmcc SMMU_MDP_AXI_CLK>;
2388 clock-names = "bus", !! 2067 clock-names = "iface", "bus";
2389 2068
2390 power-domains = <&mmc 2069 power-domains = <&mmcc MDSS_GDSC>;
2391 }; 2070 };
2392 2071
2393 venus_smmu: iommu@d40000 { 2072 venus_smmu: iommu@d40000 {
2394 compatible = "qcom,ms 2073 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2395 reg = <0x00d40000 0x2 2074 reg = <0x00d40000 0x20000>;
2396 #global-interrupts = 2075 #global-interrupts = <1>;
2397 interrupts = <GIC_SPI 2076 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>,
2398 <GIC_SPI 2077 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
2399 <GIC_SPI 2078 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
2400 <GIC_SPI 2079 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
2401 <GIC_SPI 2080 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
2402 <GIC_SPI 2081 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
2403 <GIC_SPI 2082 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
2404 <GIC_SPI 2083 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
2405 power-domains = <&mmc 2084 power-domains = <&mmcc MMAGIC_VIDEO_GDSC>;
2406 clocks = <&mmcc SMMU_ !! 2085 clocks = <&mmcc SMMU_VIDEO_AHB_CLK>,
2407 <&mmcc SMMU_ !! 2086 <&mmcc SMMU_VIDEO_AXI_CLK>;
2408 clock-names = "bus", !! 2087 clock-names = "iface", "bus";
2409 #iommu-cells = <1>; 2088 #iommu-cells = <1>;
2410 status = "okay"; 2089 status = "okay";
2411 }; 2090 };
2412 2091
2413 vfe_smmu: iommu@da0000 { 2092 vfe_smmu: iommu@da0000 {
2414 compatible = "qcom,ms 2093 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2415 reg = <0x00da0000 0x1 2094 reg = <0x00da0000 0x10000>;
2416 2095
2417 #global-interrupts = 2096 #global-interrupts = <1>;
2418 interrupts = <GIC_SPI 2097 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
2419 <GIC_SPI 2098 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
2420 <GIC_SPI 2099 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
2421 power-domains = <&mmc 2100 power-domains = <&mmcc MMAGIC_CAMSS_GDSC>;
2422 clocks = <&mmcc SMMU_ !! 2101 clocks = <&mmcc SMMU_VFE_AHB_CLK>,
2423 <&mmcc SMMU_ !! 2102 <&mmcc SMMU_VFE_AXI_CLK>;
2424 clock-names = "bus", !! 2103 clock-names = "iface",
>> 2104 "bus";
2425 #iommu-cells = <1>; 2105 #iommu-cells = <1>;
2426 }; 2106 };
2427 2107
2428 lpass_q6_smmu: iommu@1600000 2108 lpass_q6_smmu: iommu@1600000 {
2429 compatible = "qcom,ms 2109 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2430 reg = <0x01600000 0x2 2110 reg = <0x01600000 0x20000>;
2431 #iommu-cells = <1>; 2111 #iommu-cells = <1>;
2432 power-domains = <&gcc 2112 power-domains = <&gcc HLOS1_VOTE_LPASS_CORE_GDSC>;
2433 2113
2434 #global-interrupts = 2114 #global-interrupts = <1>;
2435 interrupts = <GIC_SPI 2115 interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
2436 <GIC_SPI 226 2116 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,
2437 <GIC_SPI 393 2117 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
2438 <GIC_SPI 394 2118 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
2439 <GIC_SPI 395 2119 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
2440 <GIC_SPI 396 2120 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
2441 <GIC_SPI 397 2121 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
2442 <GIC_SPI 398 2122 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
2443 <GIC_SPI 399 2123 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
2444 <GIC_SPI 400 2124 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
2445 <GIC_SPI 401 2125 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
2446 <GIC_SPI 402 2126 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
2447 <GIC_SPI 403 2127 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>;
2448 2128
2449 clocks = <&gcc GCC_HL !! 2129 clocks = <&gcc GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK>,
2450 <&gcc GCC_HL !! 2130 <&gcc GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>;
2451 clock-names = "bus", !! 2131 clock-names = "iface", "bus";
2452 }; 2132 };
2453 2133
2454 slpi_pil: remoteproc@1c00000 2134 slpi_pil: remoteproc@1c00000 {
2455 compatible = "qcom,ms 2135 compatible = "qcom,msm8996-slpi-pil";
2456 reg = <0x01c00000 0x4 2136 reg = <0x01c00000 0x4000>;
2457 2137
2458 interrupts-extended = 2138 interrupts-extended = <&intc 0 390 IRQ_TYPE_EDGE_RISING>,
2459 2139 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2460 2140 <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2461 2141 <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2462 2142 <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
2463 interrupt-names = "wd 2143 interrupt-names = "wdog",
2464 "fa 2144 "fatal",
2465 "re 2145 "ready",
2466 "ha 2146 "handover",
2467 "st 2147 "stop-ack";
2468 2148
2469 clocks = <&xo_board>; !! 2149 clocks = <&xo_board>,
2470 clock-names = "xo"; !! 2150 <&rpmcc RPM_SMD_AGGR2_NOC_CLK>;
>> 2151 clock-names = "xo", "aggre2";
2471 2152
2472 memory-region = <&slp 2153 memory-region = <&slpi_mem>;
2473 2154
2474 qcom,smem-states = <& 2155 qcom,smem-states = <&slpi_smp2p_out 0>;
2475 qcom,smem-state-names 2156 qcom,smem-state-names = "stop";
2476 2157
2477 power-domains = <&rpm 2158 power-domains = <&rpmpd MSM8996_VDDSSCX>;
2478 power-domain-names = 2159 power-domain-names = "ssc_cx";
2479 2160
2480 status = "disabled"; 2161 status = "disabled";
2481 2162
2482 glink-edge { <<
2483 interrupts = <<
2484 label = "dsps <<
2485 qcom,remote-p <<
2486 mboxes = <&ap <<
2487 }; <<
2488 <<
2489 smd-edge { 2163 smd-edge {
2490 interrupts = 2164 interrupts = <GIC_SPI 176 IRQ_TYPE_EDGE_RISING>;
2491 2165
2492 label = "dsps 2166 label = "dsps";
2493 mboxes = <&ap 2167 mboxes = <&apcs_glb 25>;
2494 qcom,smd-edge 2168 qcom,smd-edge = <3>;
2495 qcom,remote-p 2169 qcom,remote-pid = <3>;
2496 }; 2170 };
2497 }; 2171 };
2498 2172
2499 mss_pil: remoteproc@2080000 { 2173 mss_pil: remoteproc@2080000 {
2500 compatible = "qcom,ms 2174 compatible = "qcom,msm8996-mss-pil";
2501 reg = <0x2080000 0x10 2175 reg = <0x2080000 0x100>,
2502 <0x2180000 0x02 2176 <0x2180000 0x020>;
2503 reg-names = "qdsp6", 2177 reg-names = "qdsp6", "rmb";
2504 2178
2505 interrupts-extended = 2179 interrupts-extended = <&intc 0 448 IRQ_TYPE_EDGE_RISING>,
2506 2180 <&mpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2507 2181 <&mpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2508 2182 <&mpss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2509 2183 <&mpss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
2510 2184 <&mpss_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
2511 interrupt-names = "wd 2185 interrupt-names = "wdog", "fatal", "ready",
2512 "ha 2186 "handover", "stop-ack",
2513 "sh 2187 "shutdown-ack";
2514 2188
2515 clocks = <&gcc GCC_MS 2189 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
2516 <&gcc GCC_MS 2190 <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>,
2517 <&gcc GCC_BO 2191 <&gcc GCC_BOOT_ROM_AHB_CLK>,
2518 <&xo_board>, 2192 <&xo_board>,
2519 <&gcc GCC_MS 2193 <&gcc GCC_MSS_GPLL0_DIV_CLK>,
2520 <&gcc GCC_MS 2194 <&gcc GCC_MSS_SNOC_AXI_CLK>,
2521 <&gcc GCC_MS 2195 <&gcc GCC_MSS_MNOC_BIMC_AXI_CLK>,
>> 2196 <&rpmcc RPM_SMD_PCNOC_CLK>,
2522 <&rpmcc RPM_ 2197 <&rpmcc RPM_SMD_QDSS_CLK>;
2523 clock-names = "iface" !! 2198 clock-names = "iface", "bus", "mem", "xo", "gpll0_mss",
2524 "bus", !! 2199 "snoc_axi", "mnoc_axi", "pnoc", "qdss";
2525 "mem", <<
2526 "xo", <<
2527 "gpll0_ <<
2528 "snoc_a <<
2529 "mnoc_a <<
2530 "qdss"; <<
2531 2200
2532 resets = <&gcc GCC_MS 2201 resets = <&gcc GCC_MSS_RESTART>;
2533 reset-names = "mss_re 2202 reset-names = "mss_restart";
2534 2203
2535 power-domains = <&rpm 2204 power-domains = <&rpmpd MSM8996_VDDCX>,
2536 <&rpm 2205 <&rpmpd MSM8996_VDDMX>;
2537 power-domain-names = 2206 power-domain-names = "cx", "mx";
2538 2207
2539 qcom,smem-states = <& 2208 qcom,smem-states = <&mpss_smp2p_out 0>;
2540 qcom,smem-state-names 2209 qcom,smem-state-names = "stop";
2541 2210
2542 qcom,halt-regs = <&tc !! 2211 qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>;
2543 2212
2544 status = "disabled"; 2213 status = "disabled";
2545 2214
2546 mba { 2215 mba {
2547 memory-region 2216 memory-region = <&mba_mem>;
2548 }; 2217 };
2549 2218
2550 mpss { 2219 mpss {
2551 memory-region 2220 memory-region = <&mpss_mem>;
2552 }; 2221 };
2553 2222
2554 metadata { <<
2555 memory-region <<
2556 }; <<
2557 <<
2558 glink-edge { <<
2559 interrupts = <<
2560 label = "mode <<
2561 qcom,remote-p <<
2562 mboxes = <&ap <<
2563 }; <<
2564 <<
2565 smd-edge { 2223 smd-edge {
2566 interrupts = 2224 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
2567 2225
2568 label = "mpss 2226 label = "mpss";
2569 mboxes = <&ap 2227 mboxes = <&apcs_glb 12>;
2570 qcom,smd-edge 2228 qcom,smd-edge = <0>;
2571 qcom,remote-p 2229 qcom,remote-pid = <1>;
2572 }; 2230 };
2573 }; 2231 };
2574 2232
2575 stm@3002000 { 2233 stm@3002000 {
2576 compatible = "arm,cor 2234 compatible = "arm,coresight-stm", "arm,primecell";
2577 reg = <0x3002000 0x10 2235 reg = <0x3002000 0x1000>,
2578 <0x8280000 0x18 2236 <0x8280000 0x180000>;
2579 reg-names = "stm-base 2237 reg-names = "stm-base", "stm-stimulus-base";
2580 2238
2581 clocks = <&rpmcc RPM_ 2239 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2582 clock-names = "apb_pc 2240 clock-names = "apb_pclk", "atclk";
2583 2241
2584 out-ports { 2242 out-ports {
2585 port { 2243 port {
2586 stm_o 2244 stm_out: endpoint {
2587 2245 remote-endpoint =
2588 2246 <&funnel0_in>;
2589 }; 2247 };
2590 }; 2248 };
2591 }; 2249 };
2592 }; 2250 };
2593 2251
2594 tpiu@3020000 { 2252 tpiu@3020000 {
2595 compatible = "arm,cor 2253 compatible = "arm,coresight-tpiu", "arm,primecell";
2596 reg = <0x3020000 0x10 2254 reg = <0x3020000 0x1000>;
2597 2255
2598 clocks = <&rpmcc RPM_ 2256 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2599 clock-names = "apb_pc 2257 clock-names = "apb_pclk", "atclk";
2600 2258
2601 in-ports { 2259 in-ports {
2602 port { 2260 port {
2603 tpiu_ 2261 tpiu_in: endpoint {
2604 2262 remote-endpoint =
2605 2263 <&replicator_out1>;
2606 }; 2264 };
2607 }; 2265 };
2608 }; 2266 };
2609 }; 2267 };
2610 2268
2611 funnel@3021000 { 2269 funnel@3021000 {
2612 compatible = "arm,cor 2270 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2613 reg = <0x3021000 0x10 2271 reg = <0x3021000 0x1000>;
2614 2272
2615 clocks = <&rpmcc RPM_ 2273 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2616 clock-names = "apb_pc 2274 clock-names = "apb_pclk", "atclk";
2617 2275
2618 in-ports { 2276 in-ports {
2619 #address-cell 2277 #address-cells = <1>;
2620 #size-cells = 2278 #size-cells = <0>;
2621 2279
2622 port@7 { 2280 port@7 {
2623 reg = 2281 reg = <7>;
2624 funne 2282 funnel0_in: endpoint {
2625 2283 remote-endpoint =
2626 2284 <&stm_out>;
2627 }; 2285 };
2628 }; 2286 };
2629 }; 2287 };
2630 2288
2631 out-ports { 2289 out-ports {
2632 port { 2290 port {
2633 funne 2291 funnel0_out: endpoint {
2634 2292 remote-endpoint =
2635 2293 <&merge_funnel_in0>;
2636 }; 2294 };
2637 }; 2295 };
2638 }; 2296 };
2639 }; 2297 };
2640 2298
2641 funnel@3022000 { 2299 funnel@3022000 {
2642 compatible = "arm,cor 2300 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2643 reg = <0x3022000 0x10 2301 reg = <0x3022000 0x1000>;
2644 2302
2645 clocks = <&rpmcc RPM_ 2303 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2646 clock-names = "apb_pc 2304 clock-names = "apb_pclk", "atclk";
2647 2305
2648 in-ports { 2306 in-ports {
2649 #address-cell 2307 #address-cells = <1>;
2650 #size-cells = 2308 #size-cells = <0>;
2651 2309
2652 port@6 { 2310 port@6 {
2653 reg = 2311 reg = <6>;
2654 funne 2312 funnel1_in: endpoint {
2655 2313 remote-endpoint =
2656 2314 <&apss_merge_funnel_out>;
2657 }; 2315 };
2658 }; 2316 };
2659 }; 2317 };
2660 2318
2661 out-ports { 2319 out-ports {
2662 port { 2320 port {
2663 funne 2321 funnel1_out: endpoint {
2664 2322 remote-endpoint =
2665 2323 <&merge_funnel_in1>;
2666 }; 2324 };
2667 }; 2325 };
2668 }; 2326 };
2669 }; 2327 };
2670 2328
2671 funnel@3023000 { 2329 funnel@3023000 {
2672 compatible = "arm,cor 2330 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2673 reg = <0x3023000 0x10 2331 reg = <0x3023000 0x1000>;
2674 2332
2675 clocks = <&rpmcc RPM_ 2333 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2676 clock-names = "apb_pc 2334 clock-names = "apb_pclk", "atclk";
2677 2335
2678 in-ports { <<
2679 port { <<
2680 funne <<
2681 <<
2682 <<
2683 }; <<
2684 }; <<
2685 }; <<
2686 2336
2687 out-ports { 2337 out-ports {
2688 port { 2338 port {
2689 funne 2339 funnel2_out: endpoint {
2690 2340 remote-endpoint =
2691 2341 <&merge_funnel_in2>;
2692 }; 2342 };
2693 }; 2343 };
2694 }; 2344 };
2695 }; 2345 };
2696 2346
2697 funnel@3025000 { 2347 funnel@3025000 {
2698 compatible = "arm,cor 2348 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2699 reg = <0x3025000 0x10 2349 reg = <0x3025000 0x1000>;
2700 2350
2701 clocks = <&rpmcc RPM_ 2351 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2702 clock-names = "apb_pc 2352 clock-names = "apb_pclk", "atclk";
2703 2353
2704 in-ports { 2354 in-ports {
2705 #address-cell 2355 #address-cells = <1>;
2706 #size-cells = 2356 #size-cells = <0>;
2707 2357
2708 port@0 { 2358 port@0 {
2709 reg = 2359 reg = <0>;
2710 merge 2360 merge_funnel_in0: endpoint {
2711 2361 remote-endpoint =
2712 2362 <&funnel0_out>;
2713 }; 2363 };
2714 }; 2364 };
2715 2365
2716 port@1 { 2366 port@1 {
2717 reg = 2367 reg = <1>;
2718 merge 2368 merge_funnel_in1: endpoint {
2719 2369 remote-endpoint =
2720 2370 <&funnel1_out>;
2721 }; 2371 };
2722 }; 2372 };
2723 2373
2724 port@2 { 2374 port@2 {
2725 reg = 2375 reg = <2>;
2726 merge 2376 merge_funnel_in2: endpoint {
2727 2377 remote-endpoint =
2728 2378 <&funnel2_out>;
2729 }; 2379 };
2730 }; 2380 };
2731 }; 2381 };
2732 2382
2733 out-ports { 2383 out-ports {
2734 port { 2384 port {
2735 merge 2385 merge_funnel_out: endpoint {
2736 2386 remote-endpoint =
2737 2387 <&etf_in>;
2738 }; 2388 };
2739 }; 2389 };
2740 }; 2390 };
2741 }; 2391 };
2742 2392
2743 replicator@3026000 { 2393 replicator@3026000 {
2744 compatible = "arm,cor 2394 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2745 reg = <0x3026000 0x10 2395 reg = <0x3026000 0x1000>;
2746 2396
2747 clocks = <&rpmcc RPM_ 2397 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2748 clock-names = "apb_pc 2398 clock-names = "apb_pclk", "atclk";
2749 2399
2750 in-ports { 2400 in-ports {
2751 port { 2401 port {
2752 repli 2402 replicator_in: endpoint {
2753 2403 remote-endpoint =
2754 2404 <&etf_out>;
2755 }; 2405 };
2756 }; 2406 };
2757 }; 2407 };
2758 2408
2759 out-ports { 2409 out-ports {
2760 #address-cell 2410 #address-cells = <1>;
2761 #size-cells = 2411 #size-cells = <0>;
2762 2412
2763 port@0 { 2413 port@0 {
2764 reg = 2414 reg = <0>;
2765 repli 2415 replicator_out0: endpoint {
2766 2416 remote-endpoint =
2767 2417 <&etr_in>;
2768 }; 2418 };
2769 }; 2419 };
2770 2420
2771 port@1 { 2421 port@1 {
2772 reg = 2422 reg = <1>;
2773 repli 2423 replicator_out1: endpoint {
2774 2424 remote-endpoint =
2775 2425 <&tpiu_in>;
2776 }; 2426 };
2777 }; 2427 };
2778 }; 2428 };
2779 }; 2429 };
2780 2430
2781 etf@3027000 { 2431 etf@3027000 {
2782 compatible = "arm,cor 2432 compatible = "arm,coresight-tmc", "arm,primecell";
2783 reg = <0x3027000 0x10 2433 reg = <0x3027000 0x1000>;
2784 2434
2785 clocks = <&rpmcc RPM_ 2435 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2786 clock-names = "apb_pc 2436 clock-names = "apb_pclk", "atclk";
2787 2437
2788 in-ports { 2438 in-ports {
2789 port { 2439 port {
2790 etf_i 2440 etf_in: endpoint {
2791 2441 remote-endpoint =
2792 2442 <&merge_funnel_out>;
2793 }; 2443 };
2794 }; 2444 };
2795 }; 2445 };
2796 2446
2797 out-ports { 2447 out-ports {
2798 port { 2448 port {
2799 etf_o 2449 etf_out: endpoint {
2800 2450 remote-endpoint =
2801 2451 <&replicator_in>;
2802 }; 2452 };
2803 }; 2453 };
2804 }; 2454 };
2805 }; 2455 };
2806 2456
2807 etr@3028000 { 2457 etr@3028000 {
2808 compatible = "arm,cor 2458 compatible = "arm,coresight-tmc", "arm,primecell";
2809 reg = <0x3028000 0x10 2459 reg = <0x3028000 0x1000>;
2810 2460
2811 clocks = <&rpmcc RPM_ 2461 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2812 clock-names = "apb_pc 2462 clock-names = "apb_pclk", "atclk";
2813 arm,scatter-gather; 2463 arm,scatter-gather;
2814 2464
2815 in-ports { 2465 in-ports {
2816 port { 2466 port {
2817 etr_i 2467 etr_in: endpoint {
2818 2468 remote-endpoint =
2819 2469 <&replicator_out0>;
2820 }; 2470 };
2821 }; 2471 };
2822 }; 2472 };
2823 }; 2473 };
2824 2474
2825 debug@3810000 { 2475 debug@3810000 {
2826 compatible = "arm,cor 2476 compatible = "arm,coresight-cpu-debug", "arm,primecell";
2827 reg = <0x3810000 0x10 2477 reg = <0x3810000 0x1000>;
2828 2478
2829 clocks = <&rpmcc RPM_ 2479 clocks = <&rpmcc RPM_QDSS_CLK>;
2830 clock-names = "apb_pc 2480 clock-names = "apb_pclk";
2831 2481
2832 cpu = <&CPU0>; 2482 cpu = <&CPU0>;
2833 }; 2483 };
2834 2484
2835 etm@3840000 { 2485 etm@3840000 {
2836 compatible = "arm,cor 2486 compatible = "arm,coresight-etm4x", "arm,primecell";
2837 reg = <0x3840000 0x10 2487 reg = <0x3840000 0x1000>;
2838 2488
2839 clocks = <&rpmcc RPM_ 2489 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2840 clock-names = "apb_pc 2490 clock-names = "apb_pclk", "atclk";
2841 2491
2842 cpu = <&CPU0>; 2492 cpu = <&CPU0>;
2843 2493
2844 out-ports { 2494 out-ports {
2845 port { 2495 port {
2846 etm0_ 2496 etm0_out: endpoint {
2847 2497 remote-endpoint =
2848 2498 <&apss_funnel0_in0>;
2849 }; 2499 };
2850 }; 2500 };
2851 }; 2501 };
2852 }; 2502 };
2853 2503
2854 debug@3910000 { 2504 debug@3910000 {
2855 compatible = "arm,cor 2505 compatible = "arm,coresight-cpu-debug", "arm,primecell";
2856 reg = <0x3910000 0x10 2506 reg = <0x3910000 0x1000>;
2857 2507
2858 clocks = <&rpmcc RPM_ 2508 clocks = <&rpmcc RPM_QDSS_CLK>;
2859 clock-names = "apb_pc 2509 clock-names = "apb_pclk";
2860 2510
2861 cpu = <&CPU1>; 2511 cpu = <&CPU1>;
2862 }; 2512 };
2863 2513
2864 etm@3940000 { 2514 etm@3940000 {
2865 compatible = "arm,cor 2515 compatible = "arm,coresight-etm4x", "arm,primecell";
2866 reg = <0x3940000 0x10 2516 reg = <0x3940000 0x1000>;
2867 2517
2868 clocks = <&rpmcc RPM_ 2518 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2869 clock-names = "apb_pc 2519 clock-names = "apb_pclk", "atclk";
2870 2520
2871 cpu = <&CPU1>; 2521 cpu = <&CPU1>;
2872 2522
2873 out-ports { 2523 out-ports {
2874 port { 2524 port {
2875 etm1_ 2525 etm1_out: endpoint {
2876 2526 remote-endpoint =
2877 2527 <&apss_funnel0_in1>;
2878 }; 2528 };
2879 }; 2529 };
2880 }; 2530 };
2881 }; 2531 };
2882 2532
2883 funnel@39b0000 { /* APSS Funn 2533 funnel@39b0000 { /* APSS Funnel 0 */
2884 compatible = "arm,cor 2534 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2885 reg = <0x39b0000 0x10 2535 reg = <0x39b0000 0x1000>;
2886 2536
2887 clocks = <&rpmcc RPM_ 2537 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2888 clock-names = "apb_pc 2538 clock-names = "apb_pclk", "atclk";
2889 2539
2890 in-ports { 2540 in-ports {
2891 #address-cell 2541 #address-cells = <1>;
2892 #size-cells = 2542 #size-cells = <0>;
2893 2543
2894 port@0 { 2544 port@0 {
2895 reg = 2545 reg = <0>;
2896 apss_ 2546 apss_funnel0_in0: endpoint {
2897 2547 remote-endpoint = <&etm0_out>;
2898 }; 2548 };
2899 }; 2549 };
2900 2550
2901 port@1 { 2551 port@1 {
2902 reg = 2552 reg = <1>;
2903 apss_ 2553 apss_funnel0_in1: endpoint {
2904 2554 remote-endpoint = <&etm1_out>;
2905 }; 2555 };
2906 }; 2556 };
2907 }; 2557 };
2908 2558
2909 out-ports { 2559 out-ports {
2910 port { 2560 port {
2911 apss_ 2561 apss_funnel0_out: endpoint {
2912 2562 remote-endpoint =
2913 2563 <&apss_merge_funnel_in0>;
2914 }; 2564 };
2915 }; 2565 };
2916 }; 2566 };
2917 }; 2567 };
2918 2568
2919 debug@3a10000 { 2569 debug@3a10000 {
2920 compatible = "arm,cor 2570 compatible = "arm,coresight-cpu-debug", "arm,primecell";
2921 reg = <0x3a10000 0x10 2571 reg = <0x3a10000 0x1000>;
2922 2572
2923 clocks = <&rpmcc RPM_ 2573 clocks = <&rpmcc RPM_QDSS_CLK>;
2924 clock-names = "apb_pc 2574 clock-names = "apb_pclk";
2925 2575
2926 cpu = <&CPU2>; 2576 cpu = <&CPU2>;
2927 }; 2577 };
2928 2578
2929 etm@3a40000 { 2579 etm@3a40000 {
2930 compatible = "arm,cor 2580 compatible = "arm,coresight-etm4x", "arm,primecell";
2931 reg = <0x3a40000 0x10 2581 reg = <0x3a40000 0x1000>;
2932 2582
2933 clocks = <&rpmcc RPM_ 2583 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2934 clock-names = "apb_pc 2584 clock-names = "apb_pclk", "atclk";
2935 2585
2936 cpu = <&CPU2>; 2586 cpu = <&CPU2>;
2937 2587
2938 out-ports { 2588 out-ports {
2939 port { 2589 port {
2940 etm2_ 2590 etm2_out: endpoint {
2941 2591 remote-endpoint =
2942 2592 <&apss_funnel1_in0>;
2943 }; 2593 };
2944 }; 2594 };
2945 }; 2595 };
2946 }; 2596 };
2947 2597
2948 debug@3b10000 { 2598 debug@3b10000 {
2949 compatible = "arm,cor 2599 compatible = "arm,coresight-cpu-debug", "arm,primecell";
2950 reg = <0x3b10000 0x10 2600 reg = <0x3b10000 0x1000>;
2951 2601
2952 clocks = <&rpmcc RPM_ 2602 clocks = <&rpmcc RPM_QDSS_CLK>;
2953 clock-names = "apb_pc 2603 clock-names = "apb_pclk";
2954 2604
2955 cpu = <&CPU3>; 2605 cpu = <&CPU3>;
2956 }; 2606 };
2957 2607
2958 etm@3b40000 { 2608 etm@3b40000 {
2959 compatible = "arm,cor 2609 compatible = "arm,coresight-etm4x", "arm,primecell";
2960 reg = <0x3b40000 0x10 2610 reg = <0x3b40000 0x1000>;
2961 2611
2962 clocks = <&rpmcc RPM_ 2612 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2963 clock-names = "apb_pc 2613 clock-names = "apb_pclk", "atclk";
2964 2614
2965 cpu = <&CPU3>; 2615 cpu = <&CPU3>;
2966 2616
2967 out-ports { 2617 out-ports {
2968 port { 2618 port {
2969 etm3_ 2619 etm3_out: endpoint {
2970 2620 remote-endpoint =
2971 2621 <&apss_funnel1_in1>;
2972 }; 2622 };
2973 }; 2623 };
2974 }; 2624 };
2975 }; 2625 };
2976 2626
2977 funnel@3bb0000 { /* APSS Funn 2627 funnel@3bb0000 { /* APSS Funnel 1 */
2978 compatible = "arm,cor 2628 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2979 reg = <0x3bb0000 0x10 2629 reg = <0x3bb0000 0x1000>;
2980 2630
2981 clocks = <&rpmcc RPM_ 2631 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2982 clock-names = "apb_pc 2632 clock-names = "apb_pclk", "atclk";
2983 2633
2984 in-ports { 2634 in-ports {
2985 #address-cell 2635 #address-cells = <1>;
2986 #size-cells = 2636 #size-cells = <0>;
2987 2637
2988 port@0 { 2638 port@0 {
2989 reg = 2639 reg = <0>;
2990 apss_ 2640 apss_funnel1_in0: endpoint {
2991 2641 remote-endpoint = <&etm2_out>;
2992 }; 2642 };
2993 }; 2643 };
2994 2644
2995 port@1 { 2645 port@1 {
2996 reg = 2646 reg = <1>;
2997 apss_ 2647 apss_funnel1_in1: endpoint {
2998 2648 remote-endpoint = <&etm3_out>;
2999 }; 2649 };
3000 }; 2650 };
3001 }; 2651 };
3002 2652
3003 out-ports { 2653 out-ports {
3004 port { 2654 port {
3005 apss_ 2655 apss_funnel1_out: endpoint {
3006 2656 remote-endpoint =
3007 2657 <&apss_merge_funnel_in1>;
3008 }; 2658 };
3009 }; 2659 };
3010 }; 2660 };
3011 }; 2661 };
3012 2662
3013 funnel@3bc0000 { 2663 funnel@3bc0000 {
3014 compatible = "arm,cor 2664 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3015 reg = <0x3bc0000 0x10 2665 reg = <0x3bc0000 0x1000>;
3016 2666
3017 clocks = <&rpmcc RPM_ 2667 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
3018 clock-names = "apb_pc 2668 clock-names = "apb_pclk", "atclk";
3019 2669
3020 in-ports { 2670 in-ports {
3021 #address-cell 2671 #address-cells = <1>;
3022 #size-cells = 2672 #size-cells = <0>;
3023 2673
3024 port@0 { 2674 port@0 {
3025 reg = 2675 reg = <0>;
3026 apss_ 2676 apss_merge_funnel_in0: endpoint {
3027 2677 remote-endpoint =
3028 2678 <&apss_funnel0_out>;
3029 }; 2679 };
3030 }; 2680 };
3031 2681
3032 port@1 { 2682 port@1 {
3033 reg = 2683 reg = <1>;
3034 apss_ 2684 apss_merge_funnel_in1: endpoint {
3035 2685 remote-endpoint =
3036 2686 <&apss_funnel1_out>;
3037 }; 2687 };
3038 }; 2688 };
3039 }; 2689 };
3040 2690
3041 out-ports { 2691 out-ports {
3042 port { 2692 port {
3043 apss_ 2693 apss_merge_funnel_out: endpoint {
3044 2694 remote-endpoint =
3045 2695 <&funnel1_in>;
3046 }; 2696 };
3047 }; 2697 };
3048 }; 2698 };
3049 }; 2699 };
3050 2700
3051 kryocc: clock-controller@6400 2701 kryocc: clock-controller@6400000 {
3052 compatible = "qcom,ms 2702 compatible = "qcom,msm8996-apcc";
3053 reg = <0x06400000 0x9 2703 reg = <0x06400000 0x90000>;
3054 2704
3055 clock-names = "xo", " !! 2705 clock-names = "xo";
3056 clocks = <&rpmcc RPM_ !! 2706 clocks = <&rpmcc RPM_SMD_BB_CLK1>;
3057 2707
3058 #clock-cells = <1>; 2708 #clock-cells = <1>;
3059 }; 2709 };
3060 2710
3061 usb3: usb@6af8800 { 2711 usb3: usb@6af8800 {
3062 compatible = "qcom,ms 2712 compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
3063 reg = <0x06af8800 0x4 2713 reg = <0x06af8800 0x400>;
3064 #address-cells = <1>; 2714 #address-cells = <1>;
3065 #size-cells = <1>; 2715 #size-cells = <1>;
3066 ranges; 2716 ranges;
3067 2717
3068 interrupts = <GIC_SPI 2718 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
3069 <GIC_SPI 2719 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
3070 interrupt-names = "hs 2720 interrupt-names = "hs_phy_irq", "ss_phy_irq";
3071 2721
3072 clocks = <&gcc GCC_SY 2722 clocks = <&gcc GCC_SYS_NOC_USB3_AXI_CLK>,
3073 <&gcc GCC_US 2723 <&gcc GCC_USB30_MASTER_CLK>,
3074 <&gcc GCC_AG 2724 <&gcc GCC_AGGRE2_USB3_AXI_CLK>,
3075 <&gcc GCC_US 2725 <&gcc GCC_USB30_SLEEP_CLK>,
3076 <&gcc GCC_US 2726 <&gcc GCC_USB30_MOCK_UTMI_CLK>;
3077 clock-names = "cfg_no 2727 clock-names = "cfg_noc",
3078 "core", 2728 "core",
3079 "iface" 2729 "iface",
3080 "sleep" 2730 "sleep",
3081 "mock_u 2731 "mock_utmi";
3082 2732
3083 assigned-clocks = <&g 2733 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
3084 <&g 2734 <&gcc GCC_USB30_MASTER_CLK>;
3085 assigned-clock-rates 2735 assigned-clock-rates = <19200000>, <120000000>;
3086 2736
3087 interconnects = <&a2n <<
3088 <&bim <<
3089 interconnect-names = <<
3090 <<
3091 power-domains = <&gcc 2737 power-domains = <&gcc USB30_GDSC>;
3092 status = "disabled"; 2738 status = "disabled";
3093 2739
3094 usb3_dwc3: usb@6a0000 2740 usb3_dwc3: usb@6a00000 {
3095 compatible = 2741 compatible = "snps,dwc3";
3096 reg = <0x06a0 2742 reg = <0x06a00000 0xcc00>;
3097 interrupts = !! 2743 interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>;
3098 phys = <&hsus !! 2744 phys = <&hsusb_phy1>, <&ssusb_phy_0>;
3099 phy-names = " 2745 phy-names = "usb2-phy", "usb3-phy";
3100 snps,hird-thr <<
3101 snps,dis_u2_s 2746 snps,dis_u2_susphy_quirk;
3102 snps,dis_enbl 2747 snps,dis_enblslpm_quirk;
3103 snps,is-utmi- <<
3104 snps,parkmode <<
3105 tx-fifo-resiz <<
3106 }; 2748 };
3107 }; 2749 };
3108 2750
3109 usb3phy: phy@7410000 { 2751 usb3phy: phy@7410000 {
3110 compatible = "qcom,ms 2752 compatible = "qcom,msm8996-qmp-usb3-phy";
3111 reg = <0x07410000 0x1 !! 2753 reg = <0x07410000 0x1c4>;
>> 2754 #address-cells = <1>;
>> 2755 #size-cells = <1>;
>> 2756 ranges;
3112 2757
3113 clocks = <&gcc GCC_US 2758 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
3114 <&gcc GCC_US !! 2759 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
3115 <&gcc GCC_US !! 2760 <&gcc GCC_USB3_CLKREF_CLK>;
3116 <&gcc GCC_US !! 2761 clock-names = "aux", "cfg_ahb", "ref";
3117 clock-names = "aux", <<
3118 "ref", <<
3119 "cfg_ah <<
3120 "pipe"; <<
3121 clock-output-names = <<
3122 #clock-cells = <0>; <<
3123 #phy-cells = <0>; <<
3124 2762
3125 resets = <&gcc GCC_US 2763 resets = <&gcc GCC_USB3_PHY_BCR>,
3126 <&gcc GCC_US !! 2764 <&gcc GCC_USB3PHY_PHY_BCR>;
3127 reset-names = "phy", !! 2765 reset-names = "phy", "common";
3128 "phy_ph <<
3129 <<
3130 status = "disabled"; 2766 status = "disabled";
>> 2767
>> 2768 ssusb_phy_0: phy@7410200 {
>> 2769 reg = <0x07410200 0x200>,
>> 2770 <0x07410400 0x130>,
>> 2771 <0x07410600 0x1a8>;
>> 2772 #phy-cells = <0>;
>> 2773
>> 2774 #clock-cells = <0>;
>> 2775 clock-output-names = "usb3_phy_pipe_clk_src";
>> 2776 clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
>> 2777 clock-names = "pipe0";
>> 2778 };
3131 }; 2779 };
3132 2780
3133 hsusb_phy1: phy@7411000 { 2781 hsusb_phy1: phy@7411000 {
3134 compatible = "qcom,ms 2782 compatible = "qcom,msm8996-qusb2-phy";
3135 reg = <0x07411000 0x1 2783 reg = <0x07411000 0x180>;
3136 #phy-cells = <0>; 2784 #phy-cells = <0>;
3137 2785
3138 clocks = <&gcc GCC_US 2786 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
3139 <&gcc GCC_RX1 2787 <&gcc GCC_RX1_USB2_CLKREF_CLK>;
3140 clock-names = "cfg_ah 2788 clock-names = "cfg_ahb", "ref";
3141 2789
3142 resets = <&gcc GCC_QU 2790 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
3143 nvmem-cells = <&qusb2 2791 nvmem-cells = <&qusb2p_hstx_trim>;
3144 status = "disabled"; 2792 status = "disabled";
3145 }; 2793 };
3146 2794
3147 hsusb_phy2: phy@7412000 { 2795 hsusb_phy2: phy@7412000 {
3148 compatible = "qcom,ms 2796 compatible = "qcom,msm8996-qusb2-phy";
3149 reg = <0x07412000 0x1 2797 reg = <0x07412000 0x180>;
3150 #phy-cells = <0>; 2798 #phy-cells = <0>;
3151 2799
3152 clocks = <&gcc GCC_US 2800 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
3153 <&gcc GCC_RX2 2801 <&gcc GCC_RX2_USB2_CLKREF_CLK>;
3154 clock-names = "cfg_ah 2802 clock-names = "cfg_ahb", "ref";
3155 2803
3156 resets = <&gcc GCC_QU 2804 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
3157 nvmem-cells = <&qusb2 2805 nvmem-cells = <&qusb2s_hstx_trim>;
3158 status = "disabled"; 2806 status = "disabled";
3159 }; 2807 };
3160 2808
3161 sdhc1: mmc@7464900 { !! 2809 sdhc1: sdhci@7464900 {
3162 compatible = "qcom,ms 2810 compatible = "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4";
3163 reg = <0x07464900 0x1 2811 reg = <0x07464900 0x11c>, <0x07464000 0x800>;
3164 reg-names = "hc", "co !! 2812 reg-names = "hc_mem", "core_mem";
3165 2813
3166 interrupts = <GIC_SPI 2814 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
3167 <GIC_ 2815 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
3168 interrupt-names = "hc 2816 interrupt-names = "hc_irq", "pwr_irq";
3169 2817
3170 clock-names = "iface" 2818 clock-names = "iface", "core", "xo";
3171 clocks = <&gcc GCC_SD 2819 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
3172 <&gcc GCC_SDC 2820 <&gcc GCC_SDCC1_APPS_CLK>,
3173 <&rpmcc RPM_S !! 2821 <&rpmcc RPM_SMD_BB_CLK1>;
3174 resets = <&gcc GCC_SD <<
3175 2822
3176 pinctrl-names = "defa 2823 pinctrl-names = "default", "sleep";
3177 pinctrl-0 = <&sdc1_st 2824 pinctrl-0 = <&sdc1_state_on>;
3178 pinctrl-1 = <&sdc1_st 2825 pinctrl-1 = <&sdc1_state_off>;
3179 2826
3180 bus-width = <8>; 2827 bus-width = <8>;
3181 non-removable; 2828 non-removable;
3182 status = "disabled"; 2829 status = "disabled";
3183 }; 2830 };
3184 2831
3185 sdhc2: mmc@74a4900 { !! 2832 sdhc2: sdhci@74a4900 {
3186 compatible = "qcom,ms 2833 compatible = "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4";
3187 reg = <0x074a4900 0x3 2834 reg = <0x074a4900 0x314>, <0x074a4000 0x800>;
3188 reg-names = "hc", "co !! 2835 reg-names = "hc_mem", "core_mem";
3189 2836
3190 interrupts = <GIC_SPI 2837 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
3191 <GIC_SP 2838 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
3192 interrupt-names = "hc 2839 interrupt-names = "hc_irq", "pwr_irq";
3193 2840
3194 clock-names = "iface" 2841 clock-names = "iface", "core", "xo";
3195 clocks = <&gcc GCC_SD 2842 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
3196 <&gcc GCC_SDC 2843 <&gcc GCC_SDCC2_APPS_CLK>,
3197 <&rpmcc RPM_S !! 2844 <&rpmcc RPM_SMD_BB_CLK1>;
3198 resets = <&gcc GCC_SD <<
3199 2845
3200 pinctrl-names = "defa 2846 pinctrl-names = "default", "sleep";
3201 pinctrl-0 = <&sdc2_st 2847 pinctrl-0 = <&sdc2_state_on>;
3202 pinctrl-1 = <&sdc2_st 2848 pinctrl-1 = <&sdc2_state_off>;
3203 2849
3204 bus-width = <4>; 2850 bus-width = <4>;
3205 status = "disabled"; 2851 status = "disabled";
3206 }; 2852 };
3207 2853
3208 blsp1_dma: dma-controller@754 2854 blsp1_dma: dma-controller@7544000 {
3209 compatible = "qcom,ba 2855 compatible = "qcom,bam-v1.7.0";
3210 reg = <0x07544000 0x2 2856 reg = <0x07544000 0x2b000>;
3211 interrupts = <GIC_SPI 2857 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
3212 clocks = <&gcc GCC_BL 2858 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
3213 clock-names = "bam_cl 2859 clock-names = "bam_clk";
3214 qcom,controlled-remot 2860 qcom,controlled-remotely;
3215 #dma-cells = <1>; 2861 #dma-cells = <1>;
3216 qcom,ee = <0>; 2862 qcom,ee = <0>;
3217 }; 2863 };
3218 2864
3219 blsp1_uart2: serial@7570000 { 2865 blsp1_uart2: serial@7570000 {
3220 compatible = "qcom,ms 2866 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
3221 reg = <0x07570000 0x1 2867 reg = <0x07570000 0x1000>;
3222 interrupts = <GIC_SPI 2868 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
3223 clocks = <&gcc GCC_BL 2869 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
3224 <&gcc GCC_BL 2870 <&gcc GCC_BLSP1_AHB_CLK>;
3225 clock-names = "core", 2871 clock-names = "core", "iface";
3226 pinctrl-names = "defa 2872 pinctrl-names = "default", "sleep";
3227 pinctrl-0 = <&blsp1_u 2873 pinctrl-0 = <&blsp1_uart2_default>;
3228 pinctrl-1 = <&blsp1_u 2874 pinctrl-1 = <&blsp1_uart2_sleep>;
3229 dmas = <&blsp1_dma 2> 2875 dmas = <&blsp1_dma 2>, <&blsp1_dma 3>;
3230 dma-names = "tx", "rx 2876 dma-names = "tx", "rx";
3231 status = "disabled"; 2877 status = "disabled";
3232 }; 2878 };
3233 2879
3234 blsp1_spi1: spi@7575000 { 2880 blsp1_spi1: spi@7575000 {
3235 compatible = "qcom,sp 2881 compatible = "qcom,spi-qup-v2.2.1";
3236 reg = <0x07575000 0x6 2882 reg = <0x07575000 0x600>;
3237 interrupts = <GIC_SPI 2883 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
3238 clocks = <&gcc GCC_BL 2884 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
3239 <&gcc GCC_BL 2885 <&gcc GCC_BLSP1_AHB_CLK>;
3240 clock-names = "core", 2886 clock-names = "core", "iface";
3241 pinctrl-names = "defa 2887 pinctrl-names = "default", "sleep";
3242 pinctrl-0 = <&blsp1_s 2888 pinctrl-0 = <&blsp1_spi1_default>;
3243 pinctrl-1 = <&blsp1_s 2889 pinctrl-1 = <&blsp1_spi1_sleep>;
3244 dmas = <&blsp1_dma 12 2890 dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
3245 dma-names = "tx", "rx 2891 dma-names = "tx", "rx";
3246 #address-cells = <1>; 2892 #address-cells = <1>;
3247 #size-cells = <0>; 2893 #size-cells = <0>;
3248 status = "disabled"; 2894 status = "disabled";
3249 }; 2895 };
3250 2896
3251 blsp1_i2c3: i2c@7577000 { 2897 blsp1_i2c3: i2c@7577000 {
3252 compatible = "qcom,i2 2898 compatible = "qcom,i2c-qup-v2.2.1";
3253 reg = <0x07577000 0x1 2899 reg = <0x07577000 0x1000>;
3254 interrupts = <GIC_SPI 2900 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
3255 clocks = <&gcc GCC_BL 2901 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
3256 <&gcc GCC_BL 2902 <&gcc GCC_BLSP1_AHB_CLK>;
3257 clock-names = "core", 2903 clock-names = "core", "iface";
3258 pinctrl-names = "defa 2904 pinctrl-names = "default", "sleep";
3259 pinctrl-0 = <&blsp1_i 2905 pinctrl-0 = <&blsp1_i2c3_default>;
3260 pinctrl-1 = <&blsp1_i 2906 pinctrl-1 = <&blsp1_i2c3_sleep>;
3261 dmas = <&blsp1_dma 16 2907 dmas = <&blsp1_dma 16>, <&blsp1_dma 17>;
3262 dma-names = "tx", "rx 2908 dma-names = "tx", "rx";
3263 #address-cells = <1>; 2909 #address-cells = <1>;
3264 #size-cells = <0>; 2910 #size-cells = <0>;
3265 status = "disabled"; 2911 status = "disabled";
3266 }; 2912 };
3267 2913
3268 blsp1_i2c6: i2c@757a000 { <<
3269 compatible = "qcom,i2 <<
3270 reg = <0x757a000 0x10 <<
3271 interrupts = <GIC_SPI <<
3272 clocks = <&gcc GCC_BL <<
3273 <&gcc GCC_BL <<
3274 clock-names = "core", <<
3275 pinctrl-names = "defa <<
3276 pinctrl-0 = <&blsp1_i <<
3277 pinctrl-1 = <&blsp1_i <<
3278 dmas = <&blsp1_dma 22 <<
3279 dma-names = "tx", "rx <<
3280 #address-cells = <1>; <<
3281 #size-cells = <0>; <<
3282 status = "disabled"; <<
3283 }; <<
3284 <<
3285 blsp2_dma: dma-controller@758 2914 blsp2_dma: dma-controller@7584000 {
3286 compatible = "qcom,ba 2915 compatible = "qcom,bam-v1.7.0";
3287 reg = <0x07584000 0x2 2916 reg = <0x07584000 0x2b000>;
3288 interrupts = <GIC_SPI 2917 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
3289 clocks = <&gcc GCC_BL 2918 clocks = <&gcc GCC_BLSP2_AHB_CLK>;
3290 clock-names = "bam_cl 2919 clock-names = "bam_clk";
3291 qcom,controlled-remot 2920 qcom,controlled-remotely;
3292 #dma-cells = <1>; 2921 #dma-cells = <1>;
3293 qcom,ee = <0>; 2922 qcom,ee = <0>;
3294 }; 2923 };
3295 2924
3296 blsp2_uart2: serial@75b0000 { 2925 blsp2_uart2: serial@75b0000 {
3297 compatible = "qcom,ms 2926 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
3298 reg = <0x075b0000 0x1 2927 reg = <0x075b0000 0x1000>;
3299 interrupts = <GIC_SPI 2928 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
3300 clocks = <&gcc GCC_BL 2929 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
3301 <&gcc GCC_BL 2930 <&gcc GCC_BLSP2_AHB_CLK>;
3302 clock-names = "core", 2931 clock-names = "core", "iface";
3303 status = "disabled"; 2932 status = "disabled";
3304 }; 2933 };
3305 2934
3306 blsp2_uart3: serial@75b1000 { 2935 blsp2_uart3: serial@75b1000 {
3307 compatible = "qcom,ms 2936 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
3308 reg = <0x075b1000 0x1 2937 reg = <0x075b1000 0x1000>;
3309 interrupts = <GIC_SPI 2938 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
3310 clocks = <&gcc GCC_BL 2939 clocks = <&gcc GCC_BLSP2_UART3_APPS_CLK>,
3311 <&gcc GCC_BL 2940 <&gcc GCC_BLSP2_AHB_CLK>;
3312 clock-names = "core", 2941 clock-names = "core", "iface";
3313 status = "disabled"; 2942 status = "disabled";
3314 }; 2943 };
3315 2944
3316 blsp2_i2c1: i2c@75b5000 { 2945 blsp2_i2c1: i2c@75b5000 {
3317 compatible = "qcom,i2 2946 compatible = "qcom,i2c-qup-v2.2.1";
3318 reg = <0x075b5000 0x1 2947 reg = <0x075b5000 0x1000>;
3319 interrupts = <GIC_SPI 2948 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
3320 clocks = <&gcc GCC_BL 2949 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
3321 <&gcc GCC_BL 2950 <&gcc GCC_BLSP2_AHB_CLK>;
3322 clock-names = "core", 2951 clock-names = "core", "iface";
3323 pinctrl-names = "defa 2952 pinctrl-names = "default", "sleep";
3324 pinctrl-0 = <&blsp2_i 2953 pinctrl-0 = <&blsp2_i2c1_default>;
3325 pinctrl-1 = <&blsp2_i 2954 pinctrl-1 = <&blsp2_i2c1_sleep>;
3326 dmas = <&blsp2_dma 12 2955 dmas = <&blsp2_dma 12>, <&blsp2_dma 13>;
3327 dma-names = "tx", "rx 2956 dma-names = "tx", "rx";
3328 #address-cells = <1>; 2957 #address-cells = <1>;
3329 #size-cells = <0>; 2958 #size-cells = <0>;
3330 status = "disabled"; 2959 status = "disabled";
3331 }; 2960 };
3332 2961
3333 blsp2_i2c2: i2c@75b6000 { 2962 blsp2_i2c2: i2c@75b6000 {
3334 compatible = "qcom,i2 2963 compatible = "qcom,i2c-qup-v2.2.1";
3335 reg = <0x075b6000 0x1 2964 reg = <0x075b6000 0x1000>;
3336 interrupts = <GIC_SPI 2965 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
3337 clocks = <&gcc GCC_BL 2966 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>,
3338 <&gcc GCC_BL 2967 <&gcc GCC_BLSP2_AHB_CLK>;
3339 clock-names = "core", 2968 clock-names = "core", "iface";
3340 pinctrl-names = "defa 2969 pinctrl-names = "default", "sleep";
3341 pinctrl-0 = <&blsp2_i 2970 pinctrl-0 = <&blsp2_i2c2_default>;
3342 pinctrl-1 = <&blsp2_i 2971 pinctrl-1 = <&blsp2_i2c2_sleep>;
3343 dmas = <&blsp2_dma 14 2972 dmas = <&blsp2_dma 14>, <&blsp2_dma 15>;
3344 dma-names = "tx", "rx 2973 dma-names = "tx", "rx";
3345 #address-cells = <1>; 2974 #address-cells = <1>;
3346 #size-cells = <0>; 2975 #size-cells = <0>;
3347 status = "disabled"; 2976 status = "disabled";
3348 }; 2977 };
3349 2978
3350 blsp2_i2c3: i2c@75b7000 { 2979 blsp2_i2c3: i2c@75b7000 {
3351 compatible = "qcom,i2 2980 compatible = "qcom,i2c-qup-v2.2.1";
3352 reg = <0x075b7000 0x1 2981 reg = <0x075b7000 0x1000>;
3353 interrupts = <GIC_SPI 2982 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
3354 clocks = <&gcc GCC_BL 2983 clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>,
3355 <&gcc GCC_BL 2984 <&gcc GCC_BLSP2_AHB_CLK>;
3356 clock-names = "core", 2985 clock-names = "core", "iface";
3357 clock-frequency = <40 2986 clock-frequency = <400000>;
3358 pinctrl-names = "defa 2987 pinctrl-names = "default", "sleep";
3359 pinctrl-0 = <&blsp2_i 2988 pinctrl-0 = <&blsp2_i2c3_default>;
3360 pinctrl-1 = <&blsp2_i 2989 pinctrl-1 = <&blsp2_i2c3_sleep>;
3361 dmas = <&blsp2_dma 16 2990 dmas = <&blsp2_dma 16>, <&blsp2_dma 17>;
3362 dma-names = "tx", "rx 2991 dma-names = "tx", "rx";
3363 #address-cells = <1>; 2992 #address-cells = <1>;
3364 #size-cells = <0>; 2993 #size-cells = <0>;
3365 status = "disabled"; 2994 status = "disabled";
3366 }; 2995 };
3367 2996
3368 blsp2_i2c5: i2c@75b9000 { 2997 blsp2_i2c5: i2c@75b9000 {
3369 compatible = "qcom,i2 2998 compatible = "qcom,i2c-qup-v2.2.1";
3370 reg = <0x75b9000 0x10 2999 reg = <0x75b9000 0x1000>;
3371 interrupts = <GIC_SPI 3000 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
3372 clocks = <&gcc GCC_BL 3001 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>,
3373 <&gcc GCC_BL 3002 <&gcc GCC_BLSP2_AHB_CLK>;
3374 clock-names = "core", 3003 clock-names = "core", "iface";
3375 pinctrl-names = "defa 3004 pinctrl-names = "default";
3376 pinctrl-0 = <&blsp2_i 3005 pinctrl-0 = <&blsp2_i2c5_default>;
3377 dmas = <&blsp2_dma 20 3006 dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
3378 dma-names = "tx", "rx 3007 dma-names = "tx", "rx";
3379 #address-cells = <1>; 3008 #address-cells = <1>;
3380 #size-cells = <0>; 3009 #size-cells = <0>;
3381 status = "disabled"; 3010 status = "disabled";
3382 }; 3011 };
3383 3012
3384 blsp2_i2c6: i2c@75ba000 { 3013 blsp2_i2c6: i2c@75ba000 {
3385 compatible = "qcom,i2 3014 compatible = "qcom,i2c-qup-v2.2.1";
3386 reg = <0x75ba000 0x10 3015 reg = <0x75ba000 0x1000>;
3387 interrupts = <GIC_SPI 3016 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
3388 clocks = <&gcc GCC_BL 3017 clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>,
3389 <&gcc GCC_BL 3018 <&gcc GCC_BLSP2_AHB_CLK>;
3390 clock-names = "core", 3019 clock-names = "core", "iface";
3391 pinctrl-names = "defa 3020 pinctrl-names = "default", "sleep";
3392 pinctrl-0 = <&blsp2_i 3021 pinctrl-0 = <&blsp2_i2c6_default>;
3393 pinctrl-1 = <&blsp2_i 3022 pinctrl-1 = <&blsp2_i2c6_sleep>;
3394 dmas = <&blsp2_dma 22 3023 dmas = <&blsp2_dma 22>, <&blsp2_dma 23>;
3395 dma-names = "tx", "rx 3024 dma-names = "tx", "rx";
3396 #address-cells = <1>; 3025 #address-cells = <1>;
3397 #size-cells = <0>; 3026 #size-cells = <0>;
3398 status = "disabled"; 3027 status = "disabled";
3399 }; 3028 };
3400 3029
3401 blsp2_spi6: spi@75ba000 { !! 3030 blsp2_spi6: spi@75ba000{
3402 compatible = "qcom,sp 3031 compatible = "qcom,spi-qup-v2.2.1";
3403 reg = <0x075ba000 0x6 3032 reg = <0x075ba000 0x600>;
3404 interrupts = <GIC_SPI 3033 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
3405 clocks = <&gcc GCC_BL 3034 clocks = <&gcc GCC_BLSP2_QUP6_SPI_APPS_CLK>,
3406 <&gcc GCC_BL 3035 <&gcc GCC_BLSP2_AHB_CLK>;
3407 clock-names = "core", 3036 clock-names = "core", "iface";
3408 pinctrl-names = "defa 3037 pinctrl-names = "default", "sleep";
3409 pinctrl-0 = <&blsp2_s 3038 pinctrl-0 = <&blsp2_spi6_default>;
3410 pinctrl-1 = <&blsp2_s 3039 pinctrl-1 = <&blsp2_spi6_sleep>;
3411 dmas = <&blsp2_dma 22 3040 dmas = <&blsp2_dma 22>, <&blsp2_dma 23>;
3412 dma-names = "tx", "rx 3041 dma-names = "tx", "rx";
3413 #address-cells = <1>; 3042 #address-cells = <1>;
3414 #size-cells = <0>; 3043 #size-cells = <0>;
3415 status = "disabled"; 3044 status = "disabled";
3416 }; 3045 };
3417 3046
3418 usb2: usb@76f8800 { 3047 usb2: usb@76f8800 {
3419 compatible = "qcom,ms 3048 compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
3420 reg = <0x076f8800 0x4 3049 reg = <0x076f8800 0x400>;
3421 #address-cells = <1>; 3050 #address-cells = <1>;
3422 #size-cells = <1>; 3051 #size-cells = <1>;
3423 ranges; 3052 ranges;
3424 3053
3425 interrupts = <GIC_SPI <<
3426 <GIC_SPI <<
3427 <GIC_SPI <<
3428 interrupt-names = "pw <<
3429 "qu <<
3430 "hs <<
3431 <<
3432 clocks = <&gcc GCC_PE 3054 clocks = <&gcc GCC_PERIPH_NOC_USB20_AHB_CLK>,
3433 <&gcc GCC_USB 3055 <&gcc GCC_USB20_MASTER_CLK>,
3434 <&gcc GCC_USB 3056 <&gcc GCC_USB20_MOCK_UTMI_CLK>,
3435 <&gcc GCC_USB 3057 <&gcc GCC_USB20_SLEEP_CLK>,
3436 <&gcc GCC_USB 3058 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
3437 clock-names = "cfg_no 3059 clock-names = "cfg_noc",
3438 "core", 3060 "core",
3439 "iface" 3061 "iface",
3440 "sleep" 3062 "sleep",
3441 "mock_u 3063 "mock_utmi";
3442 3064
3443 assigned-clocks = <&g 3065 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
3444 <&g 3066 <&gcc GCC_USB20_MASTER_CLK>;
3445 assigned-clock-rates 3067 assigned-clock-rates = <19200000>, <60000000>;
3446 3068
3447 power-domains = <&gcc 3069 power-domains = <&gcc USB30_GDSC>;
3448 qcom,select-utmi-as-p 3070 qcom,select-utmi-as-pipe-clk;
3449 status = "disabled"; 3071 status = "disabled";
3450 3072
3451 usb2_dwc3: usb@760000 3073 usb2_dwc3: usb@7600000 {
3452 compatible = 3074 compatible = "snps,dwc3";
3453 reg = <0x0760 3075 reg = <0x07600000 0xcc00>;
3454 interrupts = !! 3076 interrupts = <0 138 IRQ_TYPE_LEVEL_HIGH>;
3455 phys = <&hsus 3077 phys = <&hsusb_phy2>;
3456 phy-names = " 3078 phy-names = "usb2-phy";
3457 maximum-speed 3079 maximum-speed = "high-speed";
3458 snps,dis_u2_s 3080 snps,dis_u2_susphy_quirk;
3459 snps,dis_enbl 3081 snps,dis_enblslpm_quirk;
3460 }; 3082 };
3461 }; 3083 };
3462 3084
3463 slimbam: dma-controller@91840 3085 slimbam: dma-controller@9184000 {
3464 compatible = "qcom,ba 3086 compatible = "qcom,bam-v1.7.0";
3465 qcom,controlled-remot 3087 qcom,controlled-remotely;
3466 reg = <0x09184000 0x3 3088 reg = <0x09184000 0x32000>;
3467 num-channels = <31>; !! 3089 num-channels = <31>;
3468 interrupts = <GIC_SPI !! 3090 interrupts = <0 164 IRQ_TYPE_LEVEL_HIGH>;
3469 #dma-cells = <1>; 3091 #dma-cells = <1>;
3470 qcom,ee = <1>; 3092 qcom,ee = <1>;
3471 qcom,num-ees = <2>; 3093 qcom,num-ees = <2>;
3472 }; 3094 };
3473 3095
3474 slim_msm: slim-ngd@91c0000 { !! 3096 slim_msm: slim@91c0000 {
3475 compatible = "qcom,sl 3097 compatible = "qcom,slim-ngd-v1.5.0";
3476 reg = <0x091c0000 0x2 !! 3098 reg = <0x091c0000 0x2C000>;
3477 interrupts = <GIC_SPI !! 3099 reg-names = "ctrl";
3478 dmas = <&slimbam 3>, !! 3100 interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>;
3479 dma-names = "rx", "tx !! 3101 dmas = <&slimbam 3>, <&slimbam 4>,
>> 3102 <&slimbam 5>, <&slimbam 6>;
>> 3103 dma-names = "rx", "tx", "tx2", "rx2";
3480 #address-cells = <1>; 3104 #address-cells = <1>;
3481 #size-cells = <0>; 3105 #size-cells = <0>;
>> 3106 ngd@1 {
>> 3107 reg = <1>;
>> 3108 #address-cells = <1>;
>> 3109 #size-cells = <1>;
3482 3110
3483 status = "disabled"; !! 3111 tasha_ifd: tas-ifd {
>> 3112 compatible = "slim217,1a0";
>> 3113 reg = <0 0>;
>> 3114 };
>> 3115
>> 3116 wcd9335: codec@1{
>> 3117 pinctrl-0 = <&cdc_reset_active &wcd_intr_default>;
>> 3118 pinctrl-names = "default";
>> 3119
>> 3120 compatible = "slim217,1a0";
>> 3121 reg = <1 0>;
>> 3122
>> 3123 interrupt-parent = <&tlmm>;
>> 3124 interrupts = <54 IRQ_TYPE_LEVEL_HIGH>,
>> 3125 <53 IRQ_TYPE_LEVEL_HIGH>;
>> 3126 interrupt-names = "intr1", "intr2";
>> 3127 interrupt-controller;
>> 3128 #interrupt-cells = <1>;
>> 3129 reset-gpios = <&tlmm 64 0>;
>> 3130
>> 3131 slim-ifc-dev = <&tasha_ifd>;
>> 3132
>> 3133 #sound-dai-cells = <1>;
>> 3134 };
>> 3135 };
3484 }; 3136 };
3485 3137
3486 adsp_pil: remoteproc@9300000 3138 adsp_pil: remoteproc@9300000 {
3487 compatible = "qcom,ms 3139 compatible = "qcom,msm8996-adsp-pil";
3488 reg = <0x09300000 0x8 3140 reg = <0x09300000 0x80000>;
3489 3141
3490 interrupts-extended = 3142 interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>,
3491 3143 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3492 3144 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
3493 3145 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
3494 3146 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
3495 interrupt-names = "wd 3147 interrupt-names = "wdog", "fatal", "ready",
3496 "ha 3148 "handover", "stop-ack";
3497 3149
3498 clocks = <&rpmcc RPM_ !! 3150 clocks = <&rpmcc RPM_SMD_BB_CLK1>;
3499 clock-names = "xo"; 3151 clock-names = "xo";
3500 3152
3501 memory-region = <&ads 3153 memory-region = <&adsp_mem>;
3502 3154
3503 qcom,smem-states = <& 3155 qcom,smem-states = <&adsp_smp2p_out 0>;
3504 qcom,smem-state-names 3156 qcom,smem-state-names = "stop";
3505 3157
3506 power-domains = <&rpm 3158 power-domains = <&rpmpd MSM8996_VDDCX>;
3507 power-domain-names = 3159 power-domain-names = "cx";
3508 3160
3509 status = "disabled"; 3161 status = "disabled";
3510 3162
3511 glink-edge { <<
3512 interrupts = <<
3513 label = "lpas <<
3514 qcom,remote-p <<
3515 mboxes = <&ap <<
3516 }; <<
3517 <<
3518 <<
3519 smd-edge { 3163 smd-edge {
3520 interrupts = 3164 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
3521 3165
3522 label = "lpas 3166 label = "lpass";
3523 mboxes = <&ap 3167 mboxes = <&apcs_glb 8>;
3524 qcom,smd-edge 3168 qcom,smd-edge = <1>;
3525 qcom,remote-p 3169 qcom,remote-pid = <2>;
3526 !! 3170 #address-cells = <1>;
>> 3171 #size-cells = <0>;
3527 apr { 3172 apr {
3528 power 3173 power-domains = <&gcc HLOS1_VOTE_LPASS_ADSP_GDSC>;
3529 compa 3174 compatible = "qcom,apr-v2";
3530 qcom, 3175 qcom,smd-channels = "apr_audio_svc";
3531 qcom, 3176 qcom,domain = <APR_DOMAIN_ADSP>;
3532 #addr 3177 #address-cells = <1>;
3533 #size 3178 #size-cells = <0>;
3534 3179
3535 servi !! 3180 q6core {
3536 3181 reg = <APR_SVC_ADSP_CORE>;
3537 3182 compatible = "qcom,q6core";
3538 }; 3183 };
3539 3184
3540 q6afe !! 3185 q6afe: q6afe {
3541 3186 compatible = "qcom,q6afe";
3542 3187 reg = <APR_SVC_AFE>;
3543 3188 q6afedai: dais {
3544 3189 compatible = "qcom,q6afe-dais";
3545 3190 #address-cells = <1>;
3546 3191 #size-cells = <0>;
3547 3192 #sound-dai-cells = <1>;
3548 !! 3193 hdmi@1 {
3549 3194 reg = <1>;
3550 3195 };
3551 3196 };
3552 }; 3197 };
3553 3198
3554 q6asm !! 3199 q6asm: q6asm {
3555 3200 compatible = "qcom,q6asm";
3556 3201 reg = <APR_SVC_ASM>;
3557 3202 q6asmdai: dais {
3558 3203 compatible = "qcom,q6asm-dais";
3559 3204 #address-cells = <1>;
3560 3205 #size-cells = <0>;
3561 3206 #sound-dai-cells = <1>;
3562 3207 iommus = <&lpass_q6_smmu 1>;
3563 3208 };
3564 }; 3209 };
3565 3210
3566 q6adm !! 3211 q6adm: q6adm {
3567 3212 compatible = "qcom,q6adm";
3568 3213 reg = <APR_SVC_ADM>;
3569 3214 q6routing: routing {
3570 3215 compatible = "qcom,q6adm-routing";
3571 3216 #sound-dai-cells = <0>;
3572 3217 };
3573 }; 3218 };
3574 }; 3219 };
3575 3220
3576 fastrpc { <<
3577 compa <<
3578 qcom, <<
3579 label <<
3580 qcom, <<
3581 #addr <<
3582 #size <<
3583 <<
3584 cb@5 <<
3585 <<
3586 <<
3587 <<
3588 }; <<
3589 <<
3590 cb@6 <<
3591 <<
3592 <<
3593 <<
3594 }; <<
3595 <<
3596 cb@7 <<
3597 <<
3598 <<
3599 <<
3600 }; <<
3601 <<
3602 cb@8 <<
3603 <<
3604 <<
3605 <<
3606 }; <<
3607 <<
3608 cb@9 <<
3609 <<
3610 <<
3611 <<
3612 }; <<
3613 <<
3614 cb@10 <<
3615 <<
3616 <<
3617 <<
3618 }; <<
3619 <<
3620 cb@11 <<
3621 <<
3622 <<
3623 <<
3624 }; <<
3625 <<
3626 cb@12 <<
3627 <<
3628 <<
3629 <<
3630 }; <<
3631 }; <<
3632 }; 3221 };
3633 }; 3222 };
3634 3223
3635 apcs_glb: mailbox@9820000 { 3224 apcs_glb: mailbox@9820000 {
3636 compatible = "qcom,ms 3225 compatible = "qcom,msm8996-apcs-hmss-global";
3637 reg = <0x09820000 0x1 3226 reg = <0x09820000 0x1000>;
3638 3227
3639 #mbox-cells = <1>; 3228 #mbox-cells = <1>;
3640 #clock-cells = <0>; <<
3641 }; 3229 };
3642 3230
3643 timer@9840000 { 3231 timer@9840000 {
3644 #address-cells = <1>; 3232 #address-cells = <1>;
3645 #size-cells = <1>; 3233 #size-cells = <1>;
3646 ranges; 3234 ranges;
3647 compatible = "arm,arm 3235 compatible = "arm,armv7-timer-mem";
3648 reg = <0x09840000 0x1 3236 reg = <0x09840000 0x1000>;
3649 clock-frequency = <19 3237 clock-frequency = <19200000>;
3650 3238
3651 frame@9850000 { 3239 frame@9850000 {
3652 frame-number 3240 frame-number = <0>;
3653 interrupts = 3241 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
3654 3242 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
3655 reg = <0x0985 3243 reg = <0x09850000 0x1000>,
3656 <0x0986 3244 <0x09860000 0x1000>;
3657 }; 3245 };
3658 3246
3659 frame@9870000 { 3247 frame@9870000 {
3660 frame-number 3248 frame-number = <1>;
3661 interrupts = 3249 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
3662 reg = <0x0987 3250 reg = <0x09870000 0x1000>;
3663 status = "dis 3251 status = "disabled";
3664 }; 3252 };
3665 3253
3666 frame@9880000 { 3254 frame@9880000 {
3667 frame-number 3255 frame-number = <2>;
3668 interrupts = 3256 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
3669 reg = <0x0988 3257 reg = <0x09880000 0x1000>;
3670 status = "dis 3258 status = "disabled";
3671 }; 3259 };
3672 3260
3673 frame@9890000 { 3261 frame@9890000 {
3674 frame-number 3262 frame-number = <3>;
3675 interrupts = 3263 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
3676 reg = <0x0989 3264 reg = <0x09890000 0x1000>;
3677 status = "dis 3265 status = "disabled";
3678 }; 3266 };
3679 3267
3680 frame@98a0000 { 3268 frame@98a0000 {
3681 frame-number 3269 frame-number = <4>;
3682 interrupts = 3270 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
3683 reg = <0x098a 3271 reg = <0x098a0000 0x1000>;
3684 status = "dis 3272 status = "disabled";
3685 }; 3273 };
3686 3274
3687 frame@98b0000 { 3275 frame@98b0000 {
3688 frame-number 3276 frame-number = <5>;
3689 interrupts = 3277 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
3690 reg = <0x098b 3278 reg = <0x098b0000 0x1000>;
3691 status = "dis 3279 status = "disabled";
3692 }; 3280 };
3693 3281
3694 frame@98c0000 { 3282 frame@98c0000 {
3695 frame-number 3283 frame-number = <6>;
3696 interrupts = 3284 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
3697 reg = <0x098c 3285 reg = <0x098c0000 0x1000>;
3698 status = "dis 3286 status = "disabled";
3699 }; 3287 };
3700 }; 3288 };
3701 3289
3702 saw3: syscon@9a10000 { 3290 saw3: syscon@9a10000 {
3703 compatible = "syscon" 3291 compatible = "syscon";
3704 reg = <0x09a10000 0x1 3292 reg = <0x09a10000 0x1000>;
3705 }; 3293 };
3706 3294
3707 cbf: clock-controller@9a11000 <<
3708 compatible = "qcom,ms <<
3709 reg = <0x09a11000 0x1 <<
3710 clocks = <&rpmcc RPM_ <<
3711 #clock-cells = <0>; <<
3712 #interconnect-cells = <<
3713 }; <<
3714 <<
3715 intc: interrupt-controller@9b 3295 intc: interrupt-controller@9bc0000 {
3716 compatible = "qcom,ms 3296 compatible = "qcom,msm8996-gic-v3", "arm,gic-v3";
3717 #interrupt-cells = <3 3297 #interrupt-cells = <3>;
3718 interrupt-controller; 3298 interrupt-controller;
3719 #redistributor-region 3299 #redistributor-regions = <1>;
3720 redistributor-stride 3300 redistributor-stride = <0x0 0x40000>;
3721 reg = <0x09bc0000 0x1 3301 reg = <0x09bc0000 0x10000>,
3722 <0x09c00000 0x1 3302 <0x09c00000 0x100000>;
3723 interrupts = <GIC_PPI 3303 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
3724 }; 3304 };
3725 }; 3305 };
3726 3306
3727 sound: sound { 3307 sound: sound {
3728 }; 3308 };
3729 3309
3730 thermal-zones { 3310 thermal-zones {
3731 cpu0-thermal { 3311 cpu0-thermal {
3732 polling-delay-passive 3312 polling-delay-passive = <250>;
>> 3313 polling-delay = <1000>;
3733 3314
3734 thermal-sensors = <&t 3315 thermal-sensors = <&tsens0 3>;
3735 3316
3736 trips { 3317 trips {
3737 cpu0_alert0: 3318 cpu0_alert0: trip-point0 {
3738 tempe 3319 temperature = <75000>;
3739 hyste 3320 hysteresis = <2000>;
3740 type 3321 type = "passive";
3741 }; 3322 };
3742 3323
3743 cpu0_crit: cp !! 3324 cpu0_crit: cpu_crit {
3744 tempe 3325 temperature = <110000>;
3745 hyste 3326 hysteresis = <2000>;
3746 type 3327 type = "critical";
3747 }; 3328 };
3748 }; 3329 };
3749 }; 3330 };
3750 3331
3751 cpu1-thermal { 3332 cpu1-thermal {
3752 polling-delay-passive 3333 polling-delay-passive = <250>;
>> 3334 polling-delay = <1000>;
3753 3335
3754 thermal-sensors = <&t 3336 thermal-sensors = <&tsens0 5>;
3755 3337
3756 trips { 3338 trips {
3757 cpu1_alert0: 3339 cpu1_alert0: trip-point0 {
3758 tempe 3340 temperature = <75000>;
3759 hyste 3341 hysteresis = <2000>;
3760 type 3342 type = "passive";
3761 }; 3343 };
3762 3344
3763 cpu1_crit: cp !! 3345 cpu1_crit: cpu_crit {
3764 tempe 3346 temperature = <110000>;
3765 hyste 3347 hysteresis = <2000>;
3766 type 3348 type = "critical";
3767 }; 3349 };
3768 }; 3350 };
3769 }; 3351 };
3770 3352
3771 cpu2-thermal { 3353 cpu2-thermal {
3772 polling-delay-passive 3354 polling-delay-passive = <250>;
>> 3355 polling-delay = <1000>;
3773 3356
3774 thermal-sensors = <&t 3357 thermal-sensors = <&tsens0 8>;
3775 3358
3776 trips { 3359 trips {
3777 cpu2_alert0: 3360 cpu2_alert0: trip-point0 {
3778 tempe 3361 temperature = <75000>;
3779 hyste 3362 hysteresis = <2000>;
3780 type 3363 type = "passive";
3781 }; 3364 };
3782 3365
3783 cpu2_crit: cp !! 3366 cpu2_crit: cpu_crit {
3784 tempe 3367 temperature = <110000>;
3785 hyste 3368 hysteresis = <2000>;
3786 type 3369 type = "critical";
3787 }; 3370 };
3788 }; 3371 };
3789 }; 3372 };
3790 3373
3791 cpu3-thermal { 3374 cpu3-thermal {
3792 polling-delay-passive 3375 polling-delay-passive = <250>;
>> 3376 polling-delay = <1000>;
3793 3377
3794 thermal-sensors = <&t 3378 thermal-sensors = <&tsens0 10>;
3795 3379
3796 trips { 3380 trips {
3797 cpu3_alert0: 3381 cpu3_alert0: trip-point0 {
3798 tempe 3382 temperature = <75000>;
3799 hyste 3383 hysteresis = <2000>;
3800 type 3384 type = "passive";
3801 }; 3385 };
3802 3386
3803 cpu3_crit: cp !! 3387 cpu3_crit: cpu_crit {
3804 tempe 3388 temperature = <110000>;
3805 hyste 3389 hysteresis = <2000>;
3806 type 3390 type = "critical";
3807 }; 3391 };
3808 }; 3392 };
3809 }; 3393 };
3810 3394
3811 gpu-top-thermal { 3395 gpu-top-thermal {
3812 polling-delay-passive 3396 polling-delay-passive = <250>;
>> 3397 polling-delay = <1000>;
3813 3398
3814 thermal-sensors = <&t 3399 thermal-sensors = <&tsens1 6>;
3815 3400
3816 trips { 3401 trips {
3817 gpu1_alert0: 3402 gpu1_alert0: trip-point0 {
3818 tempe 3403 temperature = <90000>;
3819 hyste 3404 hysteresis = <2000>;
3820 type 3405 type = "passive";
3821 }; 3406 };
3822 }; 3407 };
3823 3408
3824 cooling-maps { 3409 cooling-maps {
3825 map0 { 3410 map0 {
3826 trip 3411 trip = <&gpu1_alert0>;
3827 cooli 3412 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3828 }; 3413 };
3829 }; 3414 };
3830 }; 3415 };
3831 3416
3832 gpu-bottom-thermal { 3417 gpu-bottom-thermal {
3833 polling-delay-passive 3418 polling-delay-passive = <250>;
>> 3419 polling-delay = <1000>;
3834 3420
3835 thermal-sensors = <&t 3421 thermal-sensors = <&tsens1 7>;
3836 3422
3837 trips { 3423 trips {
3838 gpu2_alert0: 3424 gpu2_alert0: trip-point0 {
3839 tempe 3425 temperature = <90000>;
3840 hyste 3426 hysteresis = <2000>;
3841 type 3427 type = "passive";
3842 }; 3428 };
3843 }; 3429 };
3844 3430
3845 cooling-maps { 3431 cooling-maps {
3846 map0 { 3432 map0 {
3847 trip 3433 trip = <&gpu2_alert0>;
3848 cooli 3434 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3849 }; 3435 };
3850 }; 3436 };
3851 }; 3437 };
3852 3438
3853 m4m-thermal { 3439 m4m-thermal {
3854 polling-delay-passive 3440 polling-delay-passive = <250>;
>> 3441 polling-delay = <1000>;
3855 3442
3856 thermal-sensors = <&t 3443 thermal-sensors = <&tsens0 1>;
3857 3444
3858 trips { 3445 trips {
3859 m4m_alert0: t 3446 m4m_alert0: trip-point0 {
3860 tempe 3447 temperature = <90000>;
3861 hyste 3448 hysteresis = <2000>;
3862 type 3449 type = "hot";
3863 }; 3450 };
3864 }; 3451 };
3865 }; 3452 };
3866 3453
3867 l3-or-venus-thermal { 3454 l3-or-venus-thermal {
3868 polling-delay-passive 3455 polling-delay-passive = <250>;
>> 3456 polling-delay = <1000>;
3869 3457
3870 thermal-sensors = <&t 3458 thermal-sensors = <&tsens0 2>;
3871 3459
3872 trips { 3460 trips {
3873 l3_or_venus_a 3461 l3_or_venus_alert0: trip-point0 {
3874 tempe 3462 temperature = <90000>;
3875 hyste 3463 hysteresis = <2000>;
3876 type 3464 type = "hot";
3877 }; 3465 };
3878 }; 3466 };
3879 }; 3467 };
3880 3468
3881 cluster0-l2-thermal { 3469 cluster0-l2-thermal {
3882 polling-delay-passive 3470 polling-delay-passive = <250>;
>> 3471 polling-delay = <1000>;
3883 3472
3884 thermal-sensors = <&t 3473 thermal-sensors = <&tsens0 7>;
3885 3474
3886 trips { 3475 trips {
3887 cluster0_l2_a 3476 cluster0_l2_alert0: trip-point0 {
3888 tempe 3477 temperature = <90000>;
3889 hyste 3478 hysteresis = <2000>;
3890 type 3479 type = "hot";
3891 }; 3480 };
3892 }; 3481 };
3893 }; 3482 };
3894 3483
3895 cluster1-l2-thermal { 3484 cluster1-l2-thermal {
3896 polling-delay-passive 3485 polling-delay-passive = <250>;
>> 3486 polling-delay = <1000>;
3897 3487
3898 thermal-sensors = <&t 3488 thermal-sensors = <&tsens0 12>;
3899 3489
3900 trips { 3490 trips {
3901 cluster1_l2_a 3491 cluster1_l2_alert0: trip-point0 {
3902 tempe 3492 temperature = <90000>;
3903 hyste 3493 hysteresis = <2000>;
3904 type 3494 type = "hot";
3905 }; 3495 };
3906 }; 3496 };
3907 }; 3497 };
3908 3498
3909 camera-thermal { 3499 camera-thermal {
3910 polling-delay-passive 3500 polling-delay-passive = <250>;
>> 3501 polling-delay = <1000>;
3911 3502
3912 thermal-sensors = <&t 3503 thermal-sensors = <&tsens1 1>;
3913 3504
3914 trips { 3505 trips {
3915 camera_alert0 3506 camera_alert0: trip-point0 {
3916 tempe 3507 temperature = <90000>;
3917 hyste 3508 hysteresis = <2000>;
3918 type 3509 type = "hot";
3919 }; 3510 };
3920 }; 3511 };
3921 }; 3512 };
3922 3513
3923 q6-dsp-thermal { 3514 q6-dsp-thermal {
3924 polling-delay-passive 3515 polling-delay-passive = <250>;
>> 3516 polling-delay = <1000>;
3925 3517
3926 thermal-sensors = <&t 3518 thermal-sensors = <&tsens1 2>;
3927 3519
3928 trips { 3520 trips {
3929 q6_dsp_alert0 3521 q6_dsp_alert0: trip-point0 {
3930 tempe 3522 temperature = <90000>;
3931 hyste 3523 hysteresis = <2000>;
3932 type 3524 type = "hot";
3933 }; 3525 };
3934 }; 3526 };
3935 }; 3527 };
3936 3528
3937 mem-thermal { 3529 mem-thermal {
3938 polling-delay-passive 3530 polling-delay-passive = <250>;
>> 3531 polling-delay = <1000>;
3939 3532
3940 thermal-sensors = <&t 3533 thermal-sensors = <&tsens1 3>;
3941 3534
3942 trips { 3535 trips {
3943 mem_alert0: t 3536 mem_alert0: trip-point0 {
3944 tempe 3537 temperature = <90000>;
3945 hyste 3538 hysteresis = <2000>;
3946 type 3539 type = "hot";
3947 }; 3540 };
3948 }; 3541 };
3949 }; 3542 };
3950 3543
3951 modemtx-thermal { 3544 modemtx-thermal {
3952 polling-delay-passive 3545 polling-delay-passive = <250>;
>> 3546 polling-delay = <1000>;
3953 3547
3954 thermal-sensors = <&t 3548 thermal-sensors = <&tsens1 4>;
3955 3549
3956 trips { 3550 trips {
3957 modemtx_alert 3551 modemtx_alert0: trip-point0 {
3958 tempe 3552 temperature = <90000>;
3959 hyste 3553 hysteresis = <2000>;
3960 type 3554 type = "hot";
3961 }; 3555 };
3962 }; 3556 };
3963 }; 3557 };
3964 }; 3558 };
3965 3559
3966 timer { 3560 timer {
3967 compatible = "arm,armv8-timer 3561 compatible = "arm,armv8-timer";
3968 interrupts = <GIC_PPI 13 IRQ_ 3562 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
3969 <GIC_PPI 14 IRQ_ 3563 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
3970 <GIC_PPI 11 IRQ_ 3564 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
3971 <GIC_PPI 10 IRQ_ 3565 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
3972 }; 3566 };
3973 }; 3567 };
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