1 // SPDX-License-Identifier: GPL-2.0-only 1 // SPDX-License-Identifier: GPL-2.0-only
2 /* !! 2 /* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
3 * Copyright (c) 2014-2015, The Linux Foundati <<
4 */ 3 */
5 4
6 #include <dt-bindings/interrupt-controller/arm 5 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,gcc-msm8996.h 6 #include <dt-bindings/clock/qcom,gcc-msm8996.h>
8 #include <dt-bindings/clock/qcom,mmcc-msm8996. 7 #include <dt-bindings/clock/qcom,mmcc-msm8996.h>
9 #include <dt-bindings/clock/qcom,rpmcc.h> 8 #include <dt-bindings/clock/qcom,rpmcc.h>
10 #include <dt-bindings/interconnect/qcom,msm899 <<
11 #include <dt-bindings/interconnect/qcom,msm899 <<
12 #include <dt-bindings/firmware/qcom,scm.h> <<
13 #include <dt-bindings/gpio/gpio.h> <<
14 #include <dt-bindings/power/qcom-rpmpd.h> <<
15 #include <dt-bindings/soc/qcom,apr.h> 9 #include <dt-bindings/soc/qcom,apr.h>
16 #include <dt-bindings/thermal/thermal.h> <<
17 10
18 / { 11 / {
19 interrupt-parent = <&intc>; 12 interrupt-parent = <&intc>;
20 13
21 #address-cells = <2>; 14 #address-cells = <2>;
22 #size-cells = <2>; 15 #size-cells = <2>;
23 16
24 chosen { }; 17 chosen { };
25 18
26 clocks { 19 clocks {
27 xo_board: xo-board { !! 20 xo_board: xo_board {
28 compatible = "fixed-cl 21 compatible = "fixed-clock";
29 #clock-cells = <0>; 22 #clock-cells = <0>;
30 clock-frequency = <192 23 clock-frequency = <19200000>;
31 clock-output-names = " 24 clock-output-names = "xo_board";
32 }; 25 };
33 26
34 sleep_clk: sleep-clk { !! 27 sleep_clk: sleep_clk {
35 compatible = "fixed-cl 28 compatible = "fixed-clock";
36 #clock-cells = <0>; 29 #clock-cells = <0>;
37 clock-frequency = <327 30 clock-frequency = <32764>;
38 clock-output-names = " 31 clock-output-names = "sleep_clk";
39 }; 32 };
40 }; 33 };
41 34
42 cpus { 35 cpus {
43 #address-cells = <2>; 36 #address-cells = <2>;
44 #size-cells = <0>; 37 #size-cells = <0>;
45 38
46 CPU0: cpu@0 { 39 CPU0: cpu@0 {
47 device_type = "cpu"; 40 device_type = "cpu";
48 compatible = "qcom,kry 41 compatible = "qcom,kryo";
49 reg = <0x0 0x0>; 42 reg = <0x0 0x0>;
50 enable-method = "psci" 43 enable-method = "psci";
51 cpu-idle-states = <&CP 44 cpu-idle-states = <&CPU_SLEEP_0>;
52 capacity-dmips-mhz = < 45 capacity-dmips-mhz = <1024>;
53 clocks = <&kryocc 0>; <<
54 interconnects = <&cbf <<
55 operating-points-v2 = <<
56 #cooling-cells = <2>; <<
57 next-level-cache = <&L 46 next-level-cache = <&L2_0>;
58 L2_0: l2-cache { 47 L2_0: l2-cache {
59 compatible = " !! 48 compatible = "cache";
60 cache-level = !! 49 cache-level = <2>;
61 cache-unified; <<
62 }; 50 };
63 }; 51 };
64 52
65 CPU1: cpu@1 { 53 CPU1: cpu@1 {
66 device_type = "cpu"; 54 device_type = "cpu";
67 compatible = "qcom,kry 55 compatible = "qcom,kryo";
68 reg = <0x0 0x1>; 56 reg = <0x0 0x1>;
69 enable-method = "psci" 57 enable-method = "psci";
70 cpu-idle-states = <&CP 58 cpu-idle-states = <&CPU_SLEEP_0>;
71 capacity-dmips-mhz = < 59 capacity-dmips-mhz = <1024>;
72 clocks = <&kryocc 0>; <<
73 interconnects = <&cbf <<
74 operating-points-v2 = <<
75 #cooling-cells = <2>; <<
76 next-level-cache = <&L 60 next-level-cache = <&L2_0>;
77 }; 61 };
78 62
79 CPU2: cpu@100 { 63 CPU2: cpu@100 {
80 device_type = "cpu"; 64 device_type = "cpu";
81 compatible = "qcom,kry 65 compatible = "qcom,kryo";
82 reg = <0x0 0x100>; 66 reg = <0x0 0x100>;
83 enable-method = "psci" 67 enable-method = "psci";
84 cpu-idle-states = <&CP 68 cpu-idle-states = <&CPU_SLEEP_0>;
85 capacity-dmips-mhz = < 69 capacity-dmips-mhz = <1024>;
86 clocks = <&kryocc 1>; <<
87 interconnects = <&cbf <<
88 operating-points-v2 = <<
89 #cooling-cells = <2>; <<
90 next-level-cache = <&L 70 next-level-cache = <&L2_1>;
91 L2_1: l2-cache { 71 L2_1: l2-cache {
92 compatible = " !! 72 compatible = "cache";
93 cache-level = !! 73 cache-level = <2>;
94 cache-unified; <<
95 }; 74 };
96 }; 75 };
97 76
98 CPU3: cpu@101 { 77 CPU3: cpu@101 {
99 device_type = "cpu"; 78 device_type = "cpu";
100 compatible = "qcom,kry 79 compatible = "qcom,kryo";
101 reg = <0x0 0x101>; 80 reg = <0x0 0x101>;
102 enable-method = "psci" 81 enable-method = "psci";
103 cpu-idle-states = <&CP 82 cpu-idle-states = <&CPU_SLEEP_0>;
104 capacity-dmips-mhz = < 83 capacity-dmips-mhz = <1024>;
105 clocks = <&kryocc 1>; <<
106 interconnects = <&cbf <<
107 operating-points-v2 = <<
108 #cooling-cells = <2>; <<
109 next-level-cache = <&L 84 next-level-cache = <&L2_1>;
110 }; 85 };
111 86
112 cpu-map { 87 cpu-map {
113 cluster0 { 88 cluster0 {
114 core0 { 89 core0 {
115 cpu = 90 cpu = <&CPU0>;
116 }; 91 };
117 92
118 core1 { 93 core1 {
119 cpu = 94 cpu = <&CPU1>;
120 }; 95 };
121 }; 96 };
122 97
123 cluster1 { 98 cluster1 {
124 core0 { 99 core0 {
125 cpu = 100 cpu = <&CPU2>;
126 }; 101 };
127 102
128 core1 { 103 core1 {
129 cpu = 104 cpu = <&CPU3>;
130 }; 105 };
131 }; 106 };
132 }; 107 };
133 108
134 idle-states { 109 idle-states {
135 entry-method = "psci"; 110 entry-method = "psci";
136 111
137 CPU_SLEEP_0: cpu-sleep 112 CPU_SLEEP_0: cpu-sleep-0 {
138 compatible = " 113 compatible = "arm,idle-state";
139 idle-state-nam 114 idle-state-name = "standalone-power-collapse";
140 arm,psci-suspe 115 arm,psci-suspend-param = <0x00000004>;
141 entry-latency- 116 entry-latency-us = <130>;
142 exit-latency-u 117 exit-latency-us = <80>;
143 min-residency- 118 min-residency-us = <300>;
144 }; 119 };
145 }; 120 };
146 }; 121 };
147 122
148 cluster0_opp: opp-table-cluster0 { <<
149 compatible = "operating-points <<
150 nvmem-cells = <&speedbin_efuse <<
151 opp-shared; <<
152 <<
153 /* Nominal fmax for now */ <<
154 opp-307200000 { <<
155 opp-hz = /bits/ 64 <30 <<
156 opp-supported-hw = <0x <<
157 clock-latency-ns = <20 <<
158 opp-peak-kBps = <30720 <<
159 }; <<
160 opp-422400000 { <<
161 opp-hz = /bits/ 64 <42 <<
162 opp-supported-hw = <0x <<
163 clock-latency-ns = <20 <<
164 opp-peak-kBps = <30720 <<
165 }; <<
166 opp-480000000 { <<
167 opp-hz = /bits/ 64 <48 <<
168 opp-supported-hw = <0x <<
169 clock-latency-ns = <20 <<
170 opp-peak-kBps = <30720 <<
171 }; <<
172 opp-556800000 { <<
173 opp-hz = /bits/ 64 <55 <<
174 opp-supported-hw = <0x <<
175 clock-latency-ns = <20 <<
176 opp-peak-kBps = <30720 <<
177 }; <<
178 opp-652800000 { <<
179 opp-hz = /bits/ 64 <65 <<
180 opp-supported-hw = <0x <<
181 clock-latency-ns = <20 <<
182 opp-peak-kBps = <38400 <<
183 }; <<
184 opp-729600000 { <<
185 opp-hz = /bits/ 64 <72 <<
186 opp-supported-hw = <0x <<
187 clock-latency-ns = <20 <<
188 opp-peak-kBps = <46080 <<
189 }; <<
190 opp-844800000 { <<
191 opp-hz = /bits/ 64 <84 <<
192 opp-supported-hw = <0x <<
193 clock-latency-ns = <20 <<
194 opp-peak-kBps = <53760 <<
195 }; <<
196 opp-960000000 { <<
197 opp-hz = /bits/ 64 <96 <<
198 opp-supported-hw = <0x <<
199 clock-latency-ns = <20 <<
200 opp-peak-kBps = <67200 <<
201 }; <<
202 opp-1036800000 { <<
203 opp-hz = /bits/ 64 <10 <<
204 opp-supported-hw = <0x <<
205 clock-latency-ns = <20 <<
206 opp-peak-kBps = <67200 <<
207 }; <<
208 opp-1113600000 { <<
209 opp-hz = /bits/ 64 <11 <<
210 opp-supported-hw = <0x <<
211 clock-latency-ns = <20 <<
212 opp-peak-kBps = <82560 <<
213 }; <<
214 opp-1190400000 { <<
215 opp-hz = /bits/ 64 <11 <<
216 opp-supported-hw = <0x <<
217 clock-latency-ns = <20 <<
218 opp-peak-kBps = <82560 <<
219 }; <<
220 opp-1228800000 { <<
221 opp-hz = /bits/ 64 <12 <<
222 opp-supported-hw = <0x <<
223 clock-latency-ns = <20 <<
224 opp-peak-kBps = <90240 <<
225 }; <<
226 opp-1324800000 { <<
227 opp-hz = /bits/ 64 <13 <<
228 opp-supported-hw = <0x <<
229 clock-latency-ns = <20 <<
230 opp-peak-kBps = <10560 <<
231 }; <<
232 opp-1363200000 { <<
233 opp-hz = /bits/ 64 <13 <<
234 opp-supported-hw = <0x <<
235 clock-latency-ns = <20 <<
236 opp-peak-kBps = <11328 <<
237 }; <<
238 opp-1401600000 { <<
239 opp-hz = /bits/ 64 <14 <<
240 opp-supported-hw = <0x <<
241 clock-latency-ns = <20 <<
242 opp-peak-kBps = <11328 <<
243 }; <<
244 opp-1478400000 { <<
245 opp-hz = /bits/ 64 <14 <<
246 opp-supported-hw = <0x <<
247 clock-latency-ns = <20 <<
248 opp-peak-kBps = <11904 <<
249 }; <<
250 opp-1497600000 { <<
251 opp-hz = /bits/ 64 <14 <<
252 opp-supported-hw = <0x <<
253 clock-latency-ns = <20 <<
254 opp-peak-kBps = <13056 <<
255 }; <<
256 opp-1593600000 { <<
257 opp-hz = /bits/ 64 <15 <<
258 opp-supported-hw = <0x <<
259 clock-latency-ns = <20 <<
260 opp-peak-kBps = <13824 <<
261 }; <<
262 }; <<
263 <<
264 cluster1_opp: opp-table-cluster1 { <<
265 compatible = "operating-points <<
266 nvmem-cells = <&speedbin_efuse <<
267 opp-shared; <<
268 <<
269 /* Nominal fmax for now */ <<
270 opp-307200000 { <<
271 opp-hz = /bits/ 64 <30 <<
272 opp-supported-hw = <0x <<
273 clock-latency-ns = <20 <<
274 opp-peak-kBps = <30720 <<
275 }; <<
276 opp-403200000 { <<
277 opp-hz = /bits/ 64 <40 <<
278 opp-supported-hw = <0x <<
279 clock-latency-ns = <20 <<
280 opp-peak-kBps = <30720 <<
281 }; <<
282 opp-480000000 { <<
283 opp-hz = /bits/ 64 <48 <<
284 opp-supported-hw = <0x <<
285 clock-latency-ns = <20 <<
286 opp-peak-kBps = <30720 <<
287 }; <<
288 opp-556800000 { <<
289 opp-hz = /bits/ 64 <55 <<
290 opp-supported-hw = <0x <<
291 clock-latency-ns = <20 <<
292 opp-peak-kBps = <30720 <<
293 }; <<
294 opp-652800000 { <<
295 opp-hz = /bits/ 64 <65 <<
296 opp-supported-hw = <0x <<
297 clock-latency-ns = <20 <<
298 opp-peak-kBps = <30720 <<
299 }; <<
300 opp-729600000 { <<
301 opp-hz = /bits/ 64 <72 <<
302 opp-supported-hw = <0x <<
303 clock-latency-ns = <20 <<
304 opp-peak-kBps = <30720 <<
305 }; <<
306 opp-806400000 { <<
307 opp-hz = /bits/ 64 <80 <<
308 opp-supported-hw = <0x <<
309 clock-latency-ns = <20 <<
310 opp-peak-kBps = <38400 <<
311 }; <<
312 opp-883200000 { <<
313 opp-hz = /bits/ 64 <88 <<
314 opp-supported-hw = <0x <<
315 clock-latency-ns = <20 <<
316 opp-peak-kBps = <46080 <<
317 }; <<
318 opp-940800000 { <<
319 opp-hz = /bits/ 64 <94 <<
320 opp-supported-hw = <0x <<
321 clock-latency-ns = <20 <<
322 opp-peak-kBps = <53760 <<
323 }; <<
324 opp-1036800000 { <<
325 opp-hz = /bits/ 64 <10 <<
326 opp-supported-hw = <0x <<
327 clock-latency-ns = <20 <<
328 opp-peak-kBps = <59520 <<
329 }; <<
330 opp-1113600000 { <<
331 opp-hz = /bits/ 64 <11 <<
332 opp-supported-hw = <0x <<
333 clock-latency-ns = <20 <<
334 opp-peak-kBps = <67200 <<
335 }; <<
336 opp-1190400000 { <<
337 opp-hz = /bits/ 64 <11 <<
338 opp-supported-hw = <0x <<
339 clock-latency-ns = <20 <<
340 opp-peak-kBps = <67200 <<
341 }; <<
342 opp-1248000000 { <<
343 opp-hz = /bits/ 64 <12 <<
344 opp-supported-hw = <0x <<
345 clock-latency-ns = <20 <<
346 opp-peak-kBps = <74880 <<
347 }; <<
348 opp-1324800000 { <<
349 opp-hz = /bits/ 64 <13 <<
350 opp-supported-hw = <0x <<
351 clock-latency-ns = <20 <<
352 opp-peak-kBps = <82560 <<
353 }; <<
354 opp-1401600000 { <<
355 opp-hz = /bits/ 64 <14 <<
356 opp-supported-hw = <0x <<
357 clock-latency-ns = <20 <<
358 opp-peak-kBps = <90240 <<
359 }; <<
360 opp-1478400000 { <<
361 opp-hz = /bits/ 64 <14 <<
362 opp-supported-hw = <0x <<
363 clock-latency-ns = <20 <<
364 opp-peak-kBps = <97920 <<
365 }; <<
366 opp-1555200000 { <<
367 opp-hz = /bits/ 64 <15 <<
368 opp-supported-hw = <0x <<
369 clock-latency-ns = <20 <<
370 opp-peak-kBps = <10560 <<
371 }; <<
372 opp-1632000000 { <<
373 opp-hz = /bits/ 64 <16 <<
374 opp-supported-hw = <0x <<
375 clock-latency-ns = <20 <<
376 opp-peak-kBps = <11904 <<
377 }; <<
378 opp-1708800000 { <<
379 opp-hz = /bits/ 64 <17 <<
380 opp-supported-hw = <0x <<
381 clock-latency-ns = <20 <<
382 opp-peak-kBps = <12288 <<
383 }; <<
384 opp-1785600000 { <<
385 opp-hz = /bits/ 64 <17 <<
386 opp-supported-hw = <0x <<
387 clock-latency-ns = <20 <<
388 opp-peak-kBps = <13056 <<
389 }; <<
390 opp-1804800000 { <<
391 opp-hz = /bits/ 64 <18 <<
392 opp-supported-hw = <0x <<
393 clock-latency-ns = <20 <<
394 opp-peak-kBps = <13056 <<
395 }; <<
396 opp-1824000000 { <<
397 opp-hz = /bits/ 64 <18 <<
398 opp-supported-hw = <0x <<
399 clock-latency-ns = <20 <<
400 opp-peak-kBps = <13824 <<
401 }; <<
402 opp-1900800000 { <<
403 opp-hz = /bits/ 64 <19 <<
404 opp-supported-hw = <0x <<
405 clock-latency-ns = <20 <<
406 opp-peak-kBps = <13056 <<
407 }; <<
408 opp-1920000000 { <<
409 opp-hz = /bits/ 64 <19 <<
410 opp-supported-hw = <0x <<
411 clock-latency-ns = <20 <<
412 opp-peak-kBps = <14592 <<
413 }; <<
414 opp-1996800000 { <<
415 opp-hz = /bits/ 64 <19 <<
416 opp-supported-hw = <0x <<
417 clock-latency-ns = <20 <<
418 opp-peak-kBps = <15936 <<
419 }; <<
420 opp-2073600000 { <<
421 opp-hz = /bits/ 64 <20 <<
422 opp-supported-hw = <0x <<
423 clock-latency-ns = <20 <<
424 opp-peak-kBps = <15936 <<
425 }; <<
426 opp-2150400000 { <<
427 opp-hz = /bits/ 64 <21 <<
428 opp-supported-hw = <0x <<
429 clock-latency-ns = <20 <<
430 opp-peak-kBps = <15936 <<
431 }; <<
432 }; <<
433 <<
434 firmware { 123 firmware {
435 scm { 124 scm {
436 compatible = "qcom,scm !! 125 compatible = "qcom,scm-msm8996";
437 qcom,dload-mode = <&tc !! 126 qcom,dload-mode = <&tcsr 0x13000>;
438 }; 127 };
439 }; 128 };
440 129
441 memory@80000000 { !! 130 tcsr_mutex: hwlock {
442 device_type = "memory"; !! 131 compatible = "qcom,tcsr-mutex";
443 /* We expect the bootloader to !! 132 syscon = <&tcsr_mutex_regs 0 0x1000>;
444 reg = <0x0 0x80000000 0x0 0x0> !! 133 #hwlock-cells = <1>;
445 }; 134 };
446 135
447 etm { !! 136 memory {
448 compatible = "qcom,coresight-r !! 137 device_type = "memory";
449 !! 138 /* We expect the bootloader to fill in the reg */
450 out-ports { !! 139 reg = <0 0 0 0>;
451 port { <<
452 modem_etm_out_ <<
453 remote <<
454 <&fu <<
455 }; <<
456 }; <<
457 }; <<
458 }; 140 };
459 141
460 psci { 142 psci {
461 compatible = "arm,psci-1.0"; 143 compatible = "arm,psci-1.0";
462 method = "smc"; 144 method = "smc";
463 }; 145 };
464 146
465 rpm: remoteproc { <<
466 compatible = "qcom,msm8996-rpm <<
467 <<
468 glink-edge { <<
469 compatible = "qcom,gli <<
470 interrupts = <GIC_SPI <<
471 qcom,rpm-msg-ram = <&r <<
472 mboxes = <&apcs_glb 0> <<
473 <<
474 rpm_requests: rpm-requ <<
475 compatible = " <<
476 qcom,glink-cha <<
477 <<
478 rpmcc: clock-c <<
479 compat <<
480 #clock <<
481 clocks <<
482 clock- <<
483 }; <<
484 <<
485 rpmpd: power-c <<
486 compat <<
487 #power <<
488 operat <<
489 <<
490 rpmpd_ <<
491 <<
492 <<
493 <<
494 <<
495 <<
496 <<
497 <<
498 <<
499 <<
500 <<
501 <<
502 <<
503 <<
504 <<
505 <<
506 <<
507 <<
508 <<
509 <<
510 <<
511 <<
512 <<
513 <<
514 <<
515 <<
516 }; <<
517 }; <<
518 }; <<
519 }; <<
520 }; <<
521 <<
522 reserved-memory { 147 reserved-memory {
523 #address-cells = <2>; 148 #address-cells = <2>;
524 #size-cells = <2>; 149 #size-cells = <2>;
525 ranges; 150 ranges;
526 151
527 hyp_mem: memory@85800000 { !! 152 mba_region: mba@91500000 {
528 reg = <0x0 0x85800000 !! 153 reg = <0x0 0x91500000 0x0 0x200000>;
>> 154 no-map;
>> 155 };
>> 156
>> 157 slpi_region: slpi@90b00000 {
>> 158 reg = <0x0 0x90b00000 0x0 0xa00000>;
529 no-map; 159 no-map;
530 }; 160 };
531 161
532 xbl_mem: memory@85e00000 { !! 162 venus_region: venus@90400000 {
533 reg = <0x0 0x85e00000 !! 163 reg = <0x0 0x90400000 0x0 0x700000>;
>> 164 no-map;
>> 165 };
>> 166
>> 167 adsp_region: adsp@8ea00000 {
>> 168 reg = <0x0 0x8ea00000 0x0 0x1a00000>;
>> 169 no-map;
>> 170 };
>> 171
>> 172 mpss_region: mpss@88800000 {
>> 173 reg = <0x0 0x88800000 0x0 0x6200000>;
534 no-map; 174 no-map;
535 }; 175 };
536 176
537 smem_mem: smem-mem@86000000 { 177 smem_mem: smem-mem@86000000 {
538 reg = <0x0 0x86000000 178 reg = <0x0 0x86000000 0x0 0x200000>;
539 no-map; 179 no-map;
540 }; 180 };
541 181
542 tz_mem: memory@86200000 { !! 182 memory@85800000 {
>> 183 reg = <0x0 0x85800000 0x0 0x800000>;
>> 184 no-map;
>> 185 };
>> 186
>> 187 memory@86200000 {
543 reg = <0x0 0x86200000 188 reg = <0x0 0x86200000 0x0 0x2600000>;
544 no-map; 189 no-map;
545 }; 190 };
546 191
547 rmtfs_mem: rmtfs { !! 192 rmtfs@86700000 {
548 compatible = "qcom,rmt 193 compatible = "qcom,rmtfs-mem";
549 194
550 size = <0x0 0x200000>; 195 size = <0x0 0x200000>;
551 alloc-ranges = <0x0 0x 196 alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>;
552 no-map; 197 no-map;
553 198
554 qcom,client-id = <1>; 199 qcom,client-id = <1>;
555 qcom,vmid = <QCOM_SCM_ !! 200 qcom,vmid = <15>;
556 }; 201 };
557 202
558 mpss_mem: mpss@88800000 { !! 203 zap_shader_region: gpu@8f200000 {
559 reg = <0x0 0x88800000 !! 204 compatible = "shared-dma-pool";
>> 205 reg = <0x0 0x90b00000 0x0 0xa00000>;
560 no-map; 206 no-map;
561 }; 207 };
>> 208 };
562 209
563 adsp_mem: adsp@8ea00000 { !! 210 rpm-glink {
564 reg = <0x0 0x8ea00000 !! 211 compatible = "qcom,glink-rpm";
565 no-map; <<
566 }; <<
567 212
568 slpi_mem: slpi@90500000 { !! 213 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
569 reg = <0x0 0x90500000 <<
570 no-map; <<
571 }; <<
572 214
573 gpu_mem: gpu@90f00000 { !! 215 qcom,rpm-msg-ram = <&rpm_msg_ram>;
574 compatible = "shared-d <<
575 reg = <0x0 0x90f00000 <<
576 no-map; <<
577 }; <<
578 216
579 venus_mem: venus@91000000 { !! 217 mboxes = <&apcs_glb 0>;
580 reg = <0x0 0x91000000 <<
581 no-map; <<
582 }; <<
583 218
584 mba_mem: mba@91500000 { !! 219 rpm_requests: rpm-requests {
585 reg = <0x0 0x91500000 !! 220 compatible = "qcom,rpm-msm8996";
586 no-map; !! 221 qcom,glink-channels = "rpm_requests";
587 }; <<
588 222
589 mdata_mem: mpss-metadata { !! 223 rpmcc: qcom,rpmcc {
590 alloc-ranges = <0x0 0x !! 224 compatible = "qcom,rpmcc-msm8996";
591 size = <0x0 0x4000>; !! 225 #clock-cells = <1>;
592 no-map; !! 226 };
>> 227
>> 228 rpmpd: power-controller {
>> 229 compatible = "qcom,msm8996-rpmpd";
>> 230 #power-domain-cells = <1>;
>> 231 operating-points-v2 = <&rpmpd_opp_table>;
>> 232
>> 233 rpmpd_opp_table: opp-table {
>> 234 compatible = "operating-points-v2";
>> 235
>> 236 rpmpd_opp1: opp1 {
>> 237 opp-level = <1>;
>> 238 };
>> 239
>> 240 rpmpd_opp2: opp2 {
>> 241 opp-level = <2>;
>> 242 };
>> 243
>> 244 rpmpd_opp3: opp3 {
>> 245 opp-level = <3>;
>> 246 };
>> 247
>> 248 rpmpd_opp4: opp4 {
>> 249 opp-level = <4>;
>> 250 };
>> 251
>> 252 rpmpd_opp5: opp5 {
>> 253 opp-level = <5>;
>> 254 };
>> 255
>> 256 rpmpd_opp6: opp6 {
>> 257 opp-level = <6>;
>> 258 };
>> 259 };
>> 260 };
593 }; 261 };
594 }; 262 };
595 263
596 smem { 264 smem {
597 compatible = "qcom,smem"; 265 compatible = "qcom,smem";
598 memory-region = <&smem_mem>; 266 memory-region = <&smem_mem>;
599 hwlocks = <&tcsr_mutex 3>; 267 hwlocks = <&tcsr_mutex 3>;
600 }; 268 };
601 269
602 smp2p-adsp { 270 smp2p-adsp {
603 compatible = "qcom,smp2p"; 271 compatible = "qcom,smp2p";
604 qcom,smem = <443>, <429>; 272 qcom,smem = <443>, <429>;
605 273
606 interrupts = <GIC_SPI 158 IRQ_ !! 274 interrupts = <0 158 IRQ_TYPE_EDGE_RISING>;
607 275
608 mboxes = <&apcs_glb 10>; 276 mboxes = <&apcs_glb 10>;
609 277
610 qcom,local-pid = <0>; 278 qcom,local-pid = <0>;
611 qcom,remote-pid = <2>; 279 qcom,remote-pid = <2>;
612 280
613 adsp_smp2p_out: master-kernel !! 281 smp2p_adsp_out: master-kernel {
614 qcom,entry-name = "mas 282 qcom,entry-name = "master-kernel";
615 #qcom,smem-state-cells 283 #qcom,smem-state-cells = <1>;
616 }; 284 };
617 285
618 adsp_smp2p_in: slave-kernel { !! 286 smp2p_adsp_in: slave-kernel {
619 qcom,entry-name = "sla 287 qcom,entry-name = "slave-kernel";
620 288
621 interrupt-controller; 289 interrupt-controller;
622 #interrupt-cells = <2> 290 #interrupt-cells = <2>;
623 }; 291 };
624 }; 292 };
625 293
626 smp2p-mpss { !! 294 smp2p-modem {
627 compatible = "qcom,smp2p"; 295 compatible = "qcom,smp2p";
628 qcom,smem = <435>, <428>; 296 qcom,smem = <435>, <428>;
629 297
630 interrupts = <GIC_SPI 451 IRQ_ 298 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
631 299
632 mboxes = <&apcs_glb 14>; 300 mboxes = <&apcs_glb 14>;
633 301
634 qcom,local-pid = <0>; 302 qcom,local-pid = <0>;
635 qcom,remote-pid = <1>; 303 qcom,remote-pid = <1>;
636 304
637 mpss_smp2p_out: master-kernel !! 305 modem_smp2p_out: master-kernel {
638 qcom,entry-name = "mas 306 qcom,entry-name = "master-kernel";
639 #qcom,smem-state-cells 307 #qcom,smem-state-cells = <1>;
640 }; 308 };
641 309
642 mpss_smp2p_in: slave-kernel { !! 310 modem_smp2p_in: slave-kernel {
643 qcom,entry-name = "sla 311 qcom,entry-name = "slave-kernel";
644 312
645 interrupt-controller; 313 interrupt-controller;
646 #interrupt-cells = <2> 314 #interrupt-cells = <2>;
647 }; 315 };
648 }; 316 };
649 317
650 smp2p-slpi { 318 smp2p-slpi {
651 compatible = "qcom,smp2p"; 319 compatible = "qcom,smp2p";
652 qcom,smem = <481>, <430>; 320 qcom,smem = <481>, <430>;
653 321
654 interrupts = <GIC_SPI 178 IRQ_ 322 interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>;
655 323
656 mboxes = <&apcs_glb 26>; 324 mboxes = <&apcs_glb 26>;
657 325
658 qcom,local-pid = <0>; 326 qcom,local-pid = <0>;
659 qcom,remote-pid = <3>; 327 qcom,remote-pid = <3>;
660 328
661 slpi_smp2p_out: master-kernel !! 329 smp2p_slpi_in: slave-kernel {
662 qcom,entry-name = "mas <<
663 #qcom,smem-state-cells <<
664 }; <<
665 <<
666 slpi_smp2p_in: slave-kernel { <<
667 qcom,entry-name = "sla 330 qcom,entry-name = "slave-kernel";
668 <<
669 interrupt-controller; 331 interrupt-controller;
670 #interrupt-cells = <2> 332 #interrupt-cells = <2>;
671 }; 333 };
>> 334
>> 335 smp2p_slpi_out: master-kernel {
>> 336 qcom,entry-name = "master-kernel";
>> 337 #qcom,smem-state-cells = <1>;
>> 338 };
672 }; 339 };
673 340
674 soc: soc@0 { !! 341 soc: soc {
675 #address-cells = <1>; 342 #address-cells = <1>;
676 #size-cells = <1>; 343 #size-cells = <1>;
677 ranges = <0 0 0 0xffffffff>; 344 ranges = <0 0 0 0xffffffff>;
678 compatible = "simple-bus"; 345 compatible = "simple-bus";
679 346
680 pcie_phy: phy-wrapper@34000 { !! 347 pcie_phy: phy@34000 {
681 compatible = "qcom,msm 348 compatible = "qcom,msm8996-qmp-pcie-phy";
682 reg = <0x00034000 0x48 349 reg = <0x00034000 0x488>;
>> 350 #clock-cells = <1>;
683 #address-cells = <1>; 351 #address-cells = <1>;
684 #size-cells = <1>; 352 #size-cells = <1>;
685 ranges = <0x0 0x000340 !! 353 ranges;
686 354
687 clocks = <&gcc GCC_PCI 355 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
688 <&gcc GCC_PCIE 356 <&gcc GCC_PCIE_PHY_CFG_AHB_CLK>,
689 <&gcc GCC_PCIE 357 <&gcc GCC_PCIE_CLKREF_CLK>;
690 clock-names = "aux", " 358 clock-names = "aux", "cfg_ahb", "ref";
691 359
692 resets = <&gcc GCC_PCI 360 resets = <&gcc GCC_PCIE_PHY_BCR>,
693 <&gcc GCC_PCIE 361 <&gcc GCC_PCIE_PHY_COM_BCR>,
694 <&gcc GCC_PCIE 362 <&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>;
695 reset-names = "phy", " 363 reset-names = "phy", "common", "cfg";
696 <<
697 status = "disabled"; 364 status = "disabled";
698 365
699 pciephy_0: phy@1000 { !! 366 pciephy_0: lane@35000 {
700 reg = <0x1000 !! 367 reg = <0x00035000 0x130>,
701 <0x1200 !! 368 <0x00035200 0x200>,
702 <0x1400 !! 369 <0x00035400 0x1dc>;
>> 370 #phy-cells = <0>;
703 371
>> 372 clock-output-names = "pcie_0_pipe_clk_src";
704 clocks = <&gcc 373 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
705 clock-names = 374 clock-names = "pipe0";
706 resets = <&gcc 375 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
707 reset-names = 376 reset-names = "lane0";
708 <<
709 #clock-cells = <<
710 clock-output-n <<
711 <<
712 #phy-cells = < <<
713 }; 377 };
714 378
715 pciephy_1: phy@2000 { !! 379 pciephy_1: lane@36000 {
716 reg = <0x2000 !! 380 reg = <0x00036000 0x130>,
717 <0x2200 !! 381 <0x00036200 0x200>,
718 <0x2400 !! 382 <0x00036400 0x1dc>;
>> 383 #phy-cells = <0>;
719 384
>> 385 clock-output-names = "pcie_1_pipe_clk_src";
720 clocks = <&gcc 386 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
721 clock-names = 387 clock-names = "pipe1";
722 resets = <&gcc 388 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
723 reset-names = 389 reset-names = "lane1";
724 <<
725 #clock-cells = <<
726 clock-output-n <<
727 <<
728 #phy-cells = < <<
729 }; 390 };
730 391
731 pciephy_2: phy@3000 { !! 392 pciephy_2: lane@37000 {
732 reg = <0x3000 !! 393 reg = <0x00037000 0x130>,
733 <0x3200 !! 394 <0x00037200 0x200>,
734 <0x3400 !! 395 <0x00037400 0x1dc>;
>> 396 #phy-cells = <0>;
735 397
>> 398 clock-output-names = "pcie_2_pipe_clk_src";
736 clocks = <&gcc 399 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>;
737 clock-names = 400 clock-names = "pipe2";
738 resets = <&gcc 401 resets = <&gcc GCC_PCIE_2_PHY_BCR>;
739 reset-names = 402 reset-names = "lane2";
740 <<
741 #clock-cells = <<
742 clock-output-n <<
743 <<
744 #phy-cells = < <<
745 }; 403 };
746 }; 404 };
747 405
748 rpm_msg_ram: sram@68000 { !! 406 rpm_msg_ram: memory@68000 {
749 compatible = "qcom,rpm 407 compatible = "qcom,rpm-msg-ram";
750 reg = <0x00068000 0x60 408 reg = <0x00068000 0x6000>;
751 }; 409 };
752 410
753 qfprom@74000 { 411 qfprom@74000 {
754 compatible = "qcom,msm !! 412 compatible = "qcom,qfprom";
755 reg = <0x00074000 0x8f 413 reg = <0x00074000 0x8ff>;
756 #address-cells = <1>; 414 #address-cells = <1>;
757 #size-cells = <1>; 415 #size-cells = <1>;
758 416
759 qusb2p_hstx_trim: hstx !! 417 qusb2p_hstx_trim: hstx_trim@24e {
760 reg = <0x24e 0 418 reg = <0x24e 0x2>;
761 bits = <5 4>; 419 bits = <5 4>;
762 }; 420 };
763 421
764 qusb2s_hstx_trim: hstx !! 422 qusb2s_hstx_trim: hstx_trim@24f {
765 reg = <0x24f 0 423 reg = <0x24f 0x1>;
766 bits = <1 4>; 424 bits = <1 4>;
767 }; 425 };
768 426
769 speedbin_efuse: speedb !! 427 gpu_speed_bin: gpu_speed_bin@133 {
770 reg = <0x133 0 428 reg = <0x133 0x1>;
771 bits = <5 3>; 429 bits = <5 3>;
772 }; 430 };
773 }; 431 };
774 432
775 rng: rng@83000 { 433 rng: rng@83000 {
776 compatible = "qcom,prn 434 compatible = "qcom,prng-ee";
777 reg = <0x00083000 0x10 435 reg = <0x00083000 0x1000>;
778 clocks = <&gcc GCC_PRN 436 clocks = <&gcc GCC_PRNG_AHB_CLK>;
779 clock-names = "core"; 437 clock-names = "core";
780 }; 438 };
781 439
782 gcc: clock-controller@300000 { 440 gcc: clock-controller@300000 {
783 compatible = "qcom,gcc 441 compatible = "qcom,gcc-msm8996";
784 #clock-cells = <1>; 442 #clock-cells = <1>;
785 #reset-cells = <1>; 443 #reset-cells = <1>;
786 #power-domain-cells = 444 #power-domain-cells = <1>;
787 reg = <0x00300000 0x90 445 reg = <0x00300000 0x90000>;
788 446
789 clocks = <&rpmcc RPM_S !! 447 clocks = <&rpmcc RPM_SMD_LN_BB_CLK>;
790 <&rpmcc RPM_S !! 448 clock-names = "cxo2";
791 <&sleep_clk>, <<
792 <&pciephy_0>, <<
793 <&pciephy_1>, <<
794 <&pciephy_2>, <<
795 <&usb3phy>, <<
796 <&ufsphy 0>, <<
797 <&ufsphy 1>, <<
798 <&ufsphy 2>; <<
799 clock-names = "cxo", <<
800 "cxo2", <<
801 "sleep_c <<
802 "pcie_0_ <<
803 "pcie_1_ <<
804 "pcie_2_ <<
805 "usb3_ph <<
806 "ufs_rx_ <<
807 "ufs_rx_ <<
808 "ufs_tx_ <<
809 }; <<
810 <<
811 bimc: interconnect@408000 { <<
812 compatible = "qcom,msm <<
813 reg = <0x00408000 0x5a <<
814 #interconnect-cells = <<
815 }; 449 };
816 450
817 tsens0: thermal-sensor@4a9000 451 tsens0: thermal-sensor@4a9000 {
818 compatible = "qcom,msm 452 compatible = "qcom,msm8996-tsens", "qcom,tsens-v2";
819 reg = <0x004a9000 0x10 453 reg = <0x004a9000 0x1000>, /* TM */
820 <0x004a8000 0x10 454 <0x004a8000 0x1000>; /* SROT */
821 #qcom,sensors = <13>; 455 #qcom,sensors = <13>;
822 interrupts = <GIC_SPI 456 interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
823 <GIC_SPI 457 <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
824 interrupt-names = "upl 458 interrupt-names = "uplow", "critical";
825 #thermal-sensor-cells 459 #thermal-sensor-cells = <1>;
826 }; 460 };
827 461
828 tsens1: thermal-sensor@4ad000 462 tsens1: thermal-sensor@4ad000 {
829 compatible = "qcom,msm 463 compatible = "qcom,msm8996-tsens", "qcom,tsens-v2";
830 reg = <0x004ad000 0x10 464 reg = <0x004ad000 0x1000>, /* TM */
831 <0x004ac000 0x10 465 <0x004ac000 0x1000>; /* SROT */
832 #qcom,sensors = <8>; 466 #qcom,sensors = <8>;
833 interrupts = <GIC_SPI 467 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
834 <GIC_SPI 468 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>;
835 interrupt-names = "upl 469 interrupt-names = "uplow", "critical";
836 #thermal-sensor-cells 470 #thermal-sensor-cells = <1>;
837 }; 471 };
838 472
839 cryptobam: dma-controller@6440 !! 473 tcsr_mutex_regs: syscon@740000 {
840 compatible = "qcom,bam !! 474 compatible = "syscon";
841 reg = <0x00644000 0x24 <<
842 interrupts = <GIC_SPI <<
843 clocks = <&gcc GCC_CE1 <<
844 clock-names = "bam_clk <<
845 #dma-cells = <1>; <<
846 qcom,ee = <0>; <<
847 qcom,controlled-remote <<
848 }; <<
849 <<
850 crypto: crypto@67a000 { <<
851 compatible = "qcom,cry <<
852 reg = <0x0067a000 0x60 <<
853 clocks = <&gcc GCC_CE1 <<
854 <&gcc GCC_CE1 <<
855 <&gcc GCC_CE1 <<
856 clock-names = "iface", <<
857 dmas = <&cryptobam 6>, <<
858 dma-names = "rx", "tx" <<
859 }; <<
860 <<
861 cnoc: interconnect@500000 { <<
862 compatible = "qcom,msm <<
863 reg = <0x00500000 0x10 <<
864 #interconnect-cells = <<
865 }; <<
866 <<
867 snoc: interconnect@524000 { <<
868 compatible = "qcom,msm <<
869 reg = <0x00524000 0x1c <<
870 #interconnect-cells = <<
871 }; <<
872 <<
873 a0noc: interconnect@543000 { <<
874 compatible = "qcom,msm <<
875 reg = <0x00543000 0x60 <<
876 #interconnect-cells = <<
877 clock-names = "aggre0_ <<
878 "aggre0_ <<
879 "aggre0_ <<
880 clocks = <&gcc GCC_AGG <<
881 <&gcc GCC_AGG <<
882 <&gcc GCC_AGG <<
883 power-domains = <&gcc <<
884 }; <<
885 <<
886 a1noc: interconnect@562000 { <<
887 compatible = "qcom,msm <<
888 reg = <0x00562000 0x50 <<
889 #interconnect-cells = <<
890 }; <<
891 <<
892 a2noc: interconnect@583000 { <<
893 compatible = "qcom,msm <<
894 reg = <0x00583000 0x70 <<
895 #interconnect-cells = <<
896 clock-names = "aggre2_ <<
897 clocks = <&gcc GCC_AGG <<
898 <&gcc GCC_UFS <<
899 }; <<
900 <<
901 mnoc: interconnect@5a4000 { <<
902 compatible = "qcom,msm <<
903 reg = <0x005a4000 0x1c <<
904 #interconnect-cells = <<
905 clock-names = "iface"; <<
906 clocks = <&mmcc AHB_CL <<
907 }; <<
908 <<
909 pnoc: interconnect@5c0000 { <<
910 compatible = "qcom,msm <<
911 reg = <0x005c0000 0x30 <<
912 #interconnect-cells = <<
913 }; <<
914 <<
915 tcsr_mutex: hwlock@740000 { <<
916 compatible = "qcom,tcs <<
917 reg = <0x00740000 0x20 475 reg = <0x00740000 0x20000>;
918 #hwlock-cells = <1>; <<
919 }; 476 };
920 477
921 tcsr_1: syscon@760000 { !! 478 tcsr: syscon@7a0000 {
922 compatible = "qcom,tcs <<
923 reg = <0x00760000 0x20 <<
924 }; <<
925 <<
926 tcsr_2: syscon@7a0000 { <<
927 compatible = "qcom,tcs 479 compatible = "qcom,tcsr-msm8996", "syscon";
928 reg = <0x007a0000 0x18 480 reg = <0x007a0000 0x18000>;
929 }; 481 };
930 482
931 mmcc: clock-controller@8c0000 483 mmcc: clock-controller@8c0000 {
932 compatible = "qcom,mmc 484 compatible = "qcom,mmcc-msm8996";
933 #clock-cells = <1>; 485 #clock-cells = <1>;
934 #reset-cells = <1>; 486 #reset-cells = <1>;
935 #power-domain-cells = 487 #power-domain-cells = <1>;
936 reg = <0x008c0000 0x40 488 reg = <0x008c0000 0x40000>;
937 clocks = <&xo_board>, <<
938 <&gcc GPLL0>, <<
939 <&gcc GCC_MMS <<
940 <&mdss_dsi0_p <<
941 <&mdss_dsi0_p <<
942 <&mdss_dsi1_p <<
943 <&mdss_dsi1_p <<
944 <&mdss_hdmi_p <<
945 clock-names = "xo", <<
946 "gpll0", <<
947 "gcc_mms <<
948 "dsi0pll <<
949 "dsi0pll <<
950 "dsi1pll <<
951 "dsi1pll <<
952 "hdmipll <<
953 assigned-clocks = <&mm 489 assigned-clocks = <&mmcc MMPLL9_PLL>,
954 <&mm 490 <&mmcc MMPLL1_PLL>,
955 <&mm 491 <&mmcc MMPLL3_PLL>,
956 <&mm 492 <&mmcc MMPLL4_PLL>,
957 <&mm 493 <&mmcc MMPLL5_PLL>;
958 assigned-clock-rates = 494 assigned-clock-rates = <624000000>,
959 495 <810000000>,
960 496 <980000000>,
961 497 <960000000>,
962 498 <825000000>;
963 }; 499 };
964 500
965 mdss: display-subsystem@900000 !! 501 mdss: mdss@900000 {
966 compatible = "qcom,mds 502 compatible = "qcom,mdss";
967 503
968 reg = <0x00900000 0x10 504 reg = <0x00900000 0x1000>,
969 <0x009b0000 0x10 505 <0x009b0000 0x1040>,
970 <0x009b8000 0x10 506 <0x009b8000 0x1040>;
971 reg-names = "mdss_phys 507 reg-names = "mdss_phys",
972 "vbif_phys 508 "vbif_phys",
973 "vbif_nrt_ 509 "vbif_nrt_phys";
974 510
975 power-domains = <&mmcc 511 power-domains = <&mmcc MDSS_GDSC>;
976 interrupts = <GIC_SPI 512 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
977 513
978 interrupt-controller; 514 interrupt-controller;
979 #interrupt-cells = <1> 515 #interrupt-cells = <1>;
980 516
981 clocks = <&mmcc MDSS_A !! 517 clocks = <&mmcc MDSS_AHB_CLK>;
982 <&mmcc MDSS_M !! 518 clock-names = "iface";
983 clock-names = "iface", <<
984 <<
985 resets = <&mmcc MDSS_B <<
986 519
987 #address-cells = <1>; 520 #address-cells = <1>;
988 #size-cells = <1>; 521 #size-cells = <1>;
989 ranges; 522 ranges;
990 523
991 status = "disabled"; !! 524 mdp: mdp@901000 {
992 !! 525 compatible = "qcom,mdp5";
993 mdp: display-controlle <<
994 compatible = " <<
995 reg = <0x00901 526 reg = <0x00901000 0x90000>;
996 reg-names = "m 527 reg-names = "mdp_phys";
997 528
998 interrupt-pare 529 interrupt-parent = <&mdss>;
999 interrupts = < !! 530 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
1000 531
1001 clocks = <&mm 532 clocks = <&mmcc MDSS_AHB_CLK>,
1002 <&mm 533 <&mmcc MDSS_AXI_CLK>,
1003 <&mm 534 <&mmcc MDSS_MDP_CLK>,
1004 <&mm 535 <&mmcc SMMU_MDP_AXI_CLK>,
1005 <&mm 536 <&mmcc MDSS_VSYNC_CLK>;
1006 clock-names = 537 clock-names = "iface",
1007 538 "bus",
1008 539 "core",
1009 540 "iommu",
1010 541 "vsync";
1011 542
1012 iommus = <&md 543 iommus = <&mdp_smmu 0>;
1013 544
1014 assigned-cloc <<
1015 <&mm <<
1016 assigned-cloc <<
1017 <192 <<
1018 <<
1019 interconnects <<
1020 <<
1021 <<
1022 interconnect- <<
1023 <<
1024 ports { 545 ports {
1025 #addr 546 #address-cells = <1>;
1026 #size 547 #size-cells = <0>;
1027 548
1028 port@ 549 port@0 {
1029 550 reg = <0>;
1030 551 mdp5_intf3_out: endpoint {
1031 !! 552 remote-endpoint = <&hdmi_in>;
1032 <<
1033 }; <<
1034 <<
1035 port@ <<
1036 <<
1037 <<
1038 <<
1039 <<
1040 }; <<
1041 <<
1042 port@ <<
1043 <<
1044 <<
1045 <<
1046 553 };
1047 }; 554 };
1048 }; 555 };
1049 }; 556 };
1050 557
1051 mdss_dsi0: dsi@994000 !! 558 hdmi: hdmi-tx@9a0000 {
1052 compatible = <<
1053 <<
1054 reg = <0x0099 <<
1055 reg-names = " <<
1056 <<
1057 interrupt-par <<
1058 interrupts = <<
1059 <<
1060 clocks = <&mm <<
1061 <&mm <<
1062 <&mm <<
1063 <&mm <<
1064 <&mm <<
1065 <&mm <<
1066 <&mm <<
1067 clock-names = <<
1068 <<
1069 <<
1070 <<
1071 <<
1072 <<
1073 <<
1074 assigned-cloc <<
1075 assigned-cloc <<
1076 <<
1077 phys = <&mdss <<
1078 status = "dis <<
1079 <<
1080 #address-cell <<
1081 #size-cells = <<
1082 <<
1083 ports { <<
1084 #addr <<
1085 #size <<
1086 <<
1087 port@ <<
1088 <<
1089 <<
1090 <<
1091 <<
1092 }; <<
1093 <<
1094 port@ <<
1095 <<
1096 <<
1097 <<
1098 }; <<
1099 }; <<
1100 }; <<
1101 <<
1102 mdss_dsi0_phy: phy@99 <<
1103 compatible = <<
1104 reg = <0x0099 <<
1105 <0x0099 <<
1106 <0x0099 <<
1107 reg-names = " <<
1108 " <<
1109 " <<
1110 <<
1111 #clock-cells <<
1112 #phy-cells = <<
1113 <<
1114 clocks = <&mm <<
1115 clock-names = <<
1116 status = "dis <<
1117 }; <<
1118 <<
1119 mdss_dsi1: dsi@996000 <<
1120 compatible = <<
1121 <<
1122 reg = <0x0099 <<
1123 reg-names = " <<
1124 <<
1125 interrupt-par <<
1126 interrupts = <<
1127 <<
1128 clocks = <&mm <<
1129 <&mm <<
1130 <&mm <<
1131 <&mm <<
1132 <&mm <<
1133 <&mm <<
1134 <&mm <<
1135 clock-names = <<
1136 <<
1137 <<
1138 <<
1139 <<
1140 <<
1141 <<
1142 assigned-cloc <<
1143 assigned-cloc <<
1144 <<
1145 phys = <&mdss <<
1146 status = "dis <<
1147 <<
1148 #address-cell <<
1149 #size-cells = <<
1150 <<
1151 ports { <<
1152 #addr <<
1153 #size <<
1154 <<
1155 port@ <<
1156 <<
1157 <<
1158 <<
1159 <<
1160 }; <<
1161 <<
1162 port@ <<
1163 <<
1164 <<
1165 <<
1166 }; <<
1167 }; <<
1168 }; <<
1169 <<
1170 mdss_dsi1_phy: phy@99 <<
1171 compatible = <<
1172 reg = <0x0099 <<
1173 <0x0099 <<
1174 <0x0099 <<
1175 reg-names = " <<
1176 " <<
1177 " <<
1178 <<
1179 #clock-cells <<
1180 #phy-cells = <<
1181 <<
1182 clocks = <&mm <<
1183 clock-names = <<
1184 status = "dis <<
1185 }; <<
1186 <<
1187 mdss_hdmi: hdmi-tx@9a <<
1188 compatible = 559 compatible = "qcom,hdmi-tx-8996";
1189 reg = <0x009a !! 560 reg = <0x009a0000 0x50c>,
1190 <0x0007 !! 561 <0x00070000 0x6158>,
1191 <0x009e !! 562 <0x009e0000 0xfff>;
1192 reg-names = " 563 reg-names = "core_physical",
1193 " 564 "qfprom_physical",
1194 " 565 "hdcp_physical";
1195 566
1196 interrupt-par 567 interrupt-parent = <&mdss>;
1197 interrupts = !! 568 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
1198 569
1199 clocks = <&mm 570 clocks = <&mmcc MDSS_MDP_CLK>,
1200 <&mm 571 <&mmcc MDSS_AHB_CLK>,
1201 <&mm 572 <&mmcc MDSS_HDMI_CLK>,
1202 <&mm 573 <&mmcc MDSS_HDMI_AHB_CLK>,
1203 <&mm 574 <&mmcc MDSS_EXTPCLK_CLK>;
1204 clock-names = 575 clock-names =
1205 "mdp_ 576 "mdp_core",
1206 "ifac 577 "iface",
1207 "core 578 "core",
1208 "alt_ 579 "alt_iface",
1209 "extp 580 "extp";
1210 581
1211 phys = <&mdss !! 582 phys = <&hdmi_phy>;
>> 583 phy-names = "hdmi_phy";
1212 #sound-dai-ce 584 #sound-dai-cells = <1>;
1213 585
1214 status = "dis <<
1215 <<
1216 ports { 586 ports {
1217 #addr 587 #address-cells = <1>;
1218 #size 588 #size-cells = <0>;
1219 589
1220 port@ 590 port@0 {
1221 591 reg = <0>;
1222 !! 592 hdmi_in: endpoint {
1223 593 remote-endpoint = <&mdp5_intf3_out>;
1224 594 };
1225 }; 595 };
1226 }; 596 };
1227 }; 597 };
1228 598
1229 mdss_hdmi_phy: phy@9a !! 599 hdmi_phy: hdmi-phy@9a0600 {
1230 #phy-cells = 600 #phy-cells = <0>;
1231 compatible = 601 compatible = "qcom,hdmi-phy-8996";
1232 reg = <0x009a 602 reg = <0x009a0600 0x1c4>,
1233 <0x009a 603 <0x009a0a00 0x124>,
1234 <0x009a 604 <0x009a0c00 0x124>,
1235 <0x009a 605 <0x009a0e00 0x124>,
1236 <0x009a 606 <0x009a1000 0x124>,
1237 <0x009a 607 <0x009a1200 0x0c8>;
1238 reg-names = " 608 reg-names = "hdmi_pll",
1239 " 609 "hdmi_tx_l0",
1240 " 610 "hdmi_tx_l1",
1241 " 611 "hdmi_tx_l2",
1242 " 612 "hdmi_tx_l3",
1243 " 613 "hdmi_phy";
1244 614
1245 clocks = <&mm 615 clocks = <&mmcc MDSS_AHB_CLK>,
1246 <&gc !! 616 <&gcc GCC_HDMI_CLKREF_CLK>;
1247 <&xo <<
1248 clock-names = 617 clock-names = "iface",
1249 !! 618 "ref";
1250 <<
1251 <<
1252 #clock-cells <<
1253 <<
1254 status = "dis <<
1255 }; 619 };
1256 }; 620 };
1257 !! 621 gpu@b00000 {
1258 gpu: gpu@b00000 { <<
1259 compatible = "qcom,ad 622 compatible = "qcom,adreno-530.2", "qcom,adreno";
>> 623 #stream-id-cells = <16>;
1260 624
1261 reg = <0x00b00000 0x3 625 reg = <0x00b00000 0x3f000>;
1262 reg-names = "kgsl_3d0 626 reg-names = "kgsl_3d0_reg_memory";
1263 627
1264 interrupts = <GIC_SPI !! 628 interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;
1265 629
1266 clocks = <&mmcc GPU_G 630 clocks = <&mmcc GPU_GX_GFX3D_CLK>,
1267 <&mmcc GPU_AH 631 <&mmcc GPU_AHB_CLK>,
1268 <&mmcc GPU_GX 632 <&mmcc GPU_GX_RBBMTIMER_CLK>,
1269 <&gcc GCC_BIM 633 <&gcc GCC_BIMC_GFX_CLK>,
1270 <&gcc GCC_MMS 634 <&gcc GCC_MMSS_BIMC_GFX_CLK>;
1271 635
1272 clock-names = "core", 636 clock-names = "core",
1273 "iface", 637 "iface",
1274 "rbbmtimer", 638 "rbbmtimer",
1275 "mem", 639 "mem",
1276 "mem_iface"; 640 "mem_iface";
1277 641
1278 interconnects = <&bim <<
1279 interconnect-names = <<
1280 <<
1281 power-domains = <&mmc 642 power-domains = <&mmcc GPU_GX_GDSC>;
1282 iommus = <&adreno_smm 643 iommus = <&adreno_smmu 0>;
1283 644
1284 nvmem-cells = <&speed !! 645 nvmem-cells = <&gpu_speed_bin>;
1285 nvmem-cell-names = "s 646 nvmem-cell-names = "speed_bin";
1286 647
1287 operating-points-v2 = !! 648 qcom,gpu-quirk-two-pass-use-wfi;
1288 !! 649 qcom,gpu-quirk-fault-detect-mask;
1289 status = "disabled"; <<
1290 650
1291 #cooling-cells = <2>; !! 651 operating-points-v2 = <&gpu_opp_table>;
1292 652
1293 gpu_opp_table: opp-ta 653 gpu_opp_table: opp-table {
1294 compatible = !! 654 compatible ="operating-points-v2";
1295 655
1296 /* 656 /*
1297 * 624Mhz is !! 657 * 624Mhz and 560Mhz are only available on speed
1298 * 560Mhz is !! 658 * bin (1 << 0). All the rest are available on
1299 * All the re !! 659 * all bins of the hardware
1300 */ 660 */
1301 opp-624000000 661 opp-624000000 {
1302 opp-h 662 opp-hz = /bits/ 64 <624000000>;
1303 opp-s !! 663 opp-supported-hw = <0x01>;
1304 }; 664 };
1305 opp-560000000 665 opp-560000000 {
1306 opp-h 666 opp-hz = /bits/ 64 <560000000>;
1307 opp-s !! 667 opp-supported-hw = <0x01>;
1308 }; 668 };
1309 opp-510000000 669 opp-510000000 {
1310 opp-h 670 opp-hz = /bits/ 64 <510000000>;
1311 opp-s !! 671 opp-supported-hw = <0xFF>;
1312 }; 672 };
1313 opp-401800000 673 opp-401800000 {
1314 opp-h 674 opp-hz = /bits/ 64 <401800000>;
1315 opp-s !! 675 opp-supported-hw = <0xFF>;
1316 }; 676 };
1317 opp-315000000 677 opp-315000000 {
1318 opp-h 678 opp-hz = /bits/ 64 <315000000>;
1319 opp-s !! 679 opp-supported-hw = <0xFF>;
1320 }; 680 };
1321 opp-214000000 681 opp-214000000 {
1322 opp-h 682 opp-hz = /bits/ 64 <214000000>;
1323 opp-s !! 683 opp-supported-hw = <0xFF>;
1324 }; 684 };
1325 opp-133000000 685 opp-133000000 {
1326 opp-h 686 opp-hz = /bits/ 64 <133000000>;
1327 opp-s !! 687 opp-supported-hw = <0xFF>;
1328 }; 688 };
1329 }; 689 };
1330 690
1331 zap-shader { 691 zap-shader {
1332 memory-region !! 692 memory-region = <&zap_shader_region>;
1333 }; 693 };
1334 }; 694 };
1335 695
1336 tlmm: pinctrl@1010000 { !! 696 msmgpio: pinctrl@1010000 {
1337 compatible = "qcom,ms 697 compatible = "qcom,msm8996-pinctrl";
1338 reg = <0x01010000 0x3 698 reg = <0x01010000 0x300000>;
1339 interrupts = <GIC_SPI 699 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1340 gpio-controller; 700 gpio-controller;
1341 gpio-ranges = <&tlmm !! 701 gpio-ranges = <&msmgpio 0 0 150>;
1342 #gpio-cells = <2>; 702 #gpio-cells = <2>;
1343 interrupt-controller; 703 interrupt-controller;
1344 #interrupt-cells = <2 704 #interrupt-cells = <2>;
1345 <<
1346 blsp1_spi1_default: b <<
1347 spi-pins { <<
1348 pins <<
1349 funct <<
1350 drive <<
1351 bias- <<
1352 }; <<
1353 <<
1354 cs-pins { <<
1355 pins <<
1356 funct <<
1357 drive <<
1358 bias- <<
1359 outpu <<
1360 }; <<
1361 }; <<
1362 <<
1363 blsp1_spi1_sleep: bls <<
1364 pins = "gpio0 <<
1365 function = "g <<
1366 drive-strengt <<
1367 bias-pull-dow <<
1368 }; <<
1369 <<
1370 blsp2_uart2_2pins_def <<
1371 pins = "gpio4 <<
1372 function = "b <<
1373 drive-strengt <<
1374 bias-disable; <<
1375 }; <<
1376 <<
1377 blsp2_uart2_2pins_sle <<
1378 pins = "gpio4 <<
1379 function = "g <<
1380 drive-strengt <<
1381 bias-disable; <<
1382 }; <<
1383 <<
1384 blsp2_i2c2_default: b <<
1385 pins = "gpio6 <<
1386 function = "b <<
1387 drive-strengt <<
1388 bias-disable; <<
1389 }; <<
1390 <<
1391 blsp2_i2c2_sleep: bls <<
1392 pins = "gpio6 <<
1393 function = "g <<
1394 drive-strengt <<
1395 bias-disable; <<
1396 }; <<
1397 <<
1398 blsp1_i2c6_default: b <<
1399 pins = "gpio2 <<
1400 function = "b <<
1401 drive-strengt <<
1402 bias-disable; <<
1403 }; <<
1404 <<
1405 blsp1_i2c6_sleep: bls <<
1406 pins = "gpio2 <<
1407 function = "g <<
1408 drive-strengt <<
1409 bias-pull-up; <<
1410 }; <<
1411 <<
1412 cci0_default: cci0-de <<
1413 pins = "gpio1 <<
1414 function = "c <<
1415 drive-strengt <<
1416 bias-disable; <<
1417 }; <<
1418 <<
1419 camera0_state_on: <<
1420 camera_rear_default: <<
1421 camera0_mclk: <<
1422 pins <<
1423 funct <<
1424 drive <<
1425 bias- <<
1426 }; <<
1427 <<
1428 camera0_rst: <<
1429 pins <<
1430 funct <<
1431 drive <<
1432 bias- <<
1433 }; <<
1434 <<
1435 camera0_pwdn: <<
1436 pins <<
1437 funct <<
1438 drive <<
1439 bias- <<
1440 }; <<
1441 }; <<
1442 <<
1443 cci1_default: cci1-de <<
1444 pins = "gpio1 <<
1445 function = "c <<
1446 drive-strengt <<
1447 bias-disable; <<
1448 }; <<
1449 <<
1450 camera1_state_on: <<
1451 camera_board_default: <<
1452 mclk1-pins { <<
1453 pins <<
1454 funct <<
1455 drive <<
1456 bias- <<
1457 }; <<
1458 <<
1459 pwdn-pins { <<
1460 pins <<
1461 funct <<
1462 drive <<
1463 bias- <<
1464 }; <<
1465 <<
1466 rst-pins { <<
1467 pins <<
1468 funct <<
1469 drive <<
1470 bias- <<
1471 }; <<
1472 }; <<
1473 <<
1474 camera2_state_on: <<
1475 camera_front_default: <<
1476 camera2_mclk: <<
1477 pins <<
1478 funct <<
1479 drive <<
1480 bias- <<
1481 }; <<
1482 <<
1483 camera2_rst: <<
1484 pins <<
1485 funct <<
1486 drive <<
1487 bias- <<
1488 }; <<
1489 <<
1490 pwdn-pins { <<
1491 pins <<
1492 funct <<
1493 drive <<
1494 bias- <<
1495 }; <<
1496 }; <<
1497 <<
1498 pcie0_state_on: pcie0 <<
1499 perst-pins { <<
1500 pins <<
1501 funct <<
1502 drive <<
1503 bias- <<
1504 }; <<
1505 <<
1506 clkreq-pins { <<
1507 pins <<
1508 funct <<
1509 drive <<
1510 bias- <<
1511 }; <<
1512 <<
1513 wake-pins { <<
1514 pins <<
1515 funct <<
1516 drive <<
1517 bias- <<
1518 }; <<
1519 }; <<
1520 <<
1521 pcie0_state_off: pcie <<
1522 perst-pins { <<
1523 pins <<
1524 funct <<
1525 drive <<
1526 bias- <<
1527 }; <<
1528 <<
1529 clkreq-pins { <<
1530 pins <<
1531 funct <<
1532 drive <<
1533 bias- <<
1534 }; <<
1535 <<
1536 wake-pins { <<
1537 pins <<
1538 funct <<
1539 drive <<
1540 bias- <<
1541 }; <<
1542 }; <<
1543 <<
1544 blsp1_uart2_default: <<
1545 pins = "gpio4 <<
1546 function = "b <<
1547 drive-strengt <<
1548 bias-disable; <<
1549 }; <<
1550 <<
1551 blsp1_uart2_sleep: bl <<
1552 pins = "gpio4 <<
1553 function = "g <<
1554 drive-strengt <<
1555 bias-disable; <<
1556 }; <<
1557 <<
1558 blsp1_i2c3_default: b <<
1559 pins = "gpio4 <<
1560 function = "b <<
1561 drive-strengt <<
1562 bias-disable; <<
1563 }; <<
1564 <<
1565 blsp1_i2c3_sleep: bls <<
1566 pins = "gpio4 <<
1567 function = "g <<
1568 drive-strengt <<
1569 bias-disable; <<
1570 }; <<
1571 <<
1572 blsp2_uart3_4pins_def <<
1573 pins = "gpio4 <<
1574 function = "b <<
1575 drive-strengt <<
1576 bias-disable; <<
1577 }; <<
1578 <<
1579 blsp2_uart3_4pins_sle <<
1580 pins = "gpio4 <<
1581 function = "b <<
1582 drive-strengt <<
1583 bias-disable; <<
1584 }; <<
1585 <<
1586 blsp2_i2c3_default: b <<
1587 pins = "gpio5 <<
1588 function = "b <<
1589 drive-strengt <<
1590 bias-disable; <<
1591 }; <<
1592 <<
1593 blsp2_i2c3_sleep: bls <<
1594 pins = "gpio5 <<
1595 function = "g <<
1596 drive-strengt <<
1597 bias-disable; <<
1598 }; <<
1599 <<
1600 wcd_intr_default: wcd <<
1601 pins = "gpio5 <<
1602 function = "g <<
1603 drive-strengt <<
1604 bias-pull-dow <<
1605 }; <<
1606 <<
1607 blsp2_i2c1_default: b <<
1608 pins = "gpio5 <<
1609 function = "b <<
1610 drive-strengt <<
1611 bias-disable; <<
1612 }; <<
1613 <<
1614 blsp2_i2c1_sleep: bls <<
1615 pins = "gpio5 <<
1616 function = "g <<
1617 drive-strengt <<
1618 bias-disable; <<
1619 }; <<
1620 <<
1621 blsp2_i2c5_default: b <<
1622 pins = "gpio6 <<
1623 function = "b <<
1624 drive-strengt <<
1625 bias-disable; <<
1626 }; <<
1627 <<
1628 /* Sleep state for BL <<
1629 <<
1630 cdc_reset_active: cdc <<
1631 pins = "gpio6 <<
1632 function = "g <<
1633 drive-strengt <<
1634 bias-pull-dow <<
1635 output-high; <<
1636 }; <<
1637 <<
1638 cdc_reset_sleep: cdc- <<
1639 pins = "gpio6 <<
1640 function = "g <<
1641 drive-strengt <<
1642 bias-disable; <<
1643 output-low; <<
1644 }; <<
1645 <<
1646 blsp2_spi6_default: b <<
1647 spi-pins { <<
1648 pins <<
1649 funct <<
1650 drive <<
1651 bias- <<
1652 }; <<
1653 <<
1654 cs-pins { <<
1655 pins <<
1656 funct <<
1657 drive <<
1658 bias- <<
1659 outpu <<
1660 }; <<
1661 }; <<
1662 <<
1663 blsp2_spi6_sleep: bls <<
1664 pins = "gpio8 <<
1665 function = "g <<
1666 drive-strengt <<
1667 bias-pull-dow <<
1668 }; <<
1669 <<
1670 blsp2_i2c6_default: b <<
1671 pins = "gpio8 <<
1672 function = "b <<
1673 drive-strengt <<
1674 bias-disable; <<
1675 }; <<
1676 <<
1677 blsp2_i2c6_sleep: bls <<
1678 pins = "gpio8 <<
1679 function = "g <<
1680 drive-strengt <<
1681 bias-disable; <<
1682 }; <<
1683 <<
1684 pcie1_state_on: pcie1 <<
1685 perst-pins { <<
1686 pins <<
1687 funct <<
1688 drive <<
1689 bias- <<
1690 }; <<
1691 <<
1692 clkreq-pins { <<
1693 pins <<
1694 funct <<
1695 drive <<
1696 bias- <<
1697 }; <<
1698 <<
1699 wake-pins { <<
1700 pins <<
1701 funct <<
1702 drive <<
1703 bias- <<
1704 }; <<
1705 }; <<
1706 <<
1707 pcie1_state_off: pcie <<
1708 /* Perst is m <<
1709 clkreq-pins { <<
1710 pins <<
1711 funct <<
1712 drive <<
1713 bias- <<
1714 }; <<
1715 <<
1716 wake-pins { <<
1717 pins <<
1718 funct <<
1719 drive <<
1720 bias- <<
1721 }; <<
1722 }; <<
1723 <<
1724 pcie2_state_on: pcie2 <<
1725 perst-pins { <<
1726 pins <<
1727 funct <<
1728 drive <<
1729 bias- <<
1730 }; <<
1731 <<
1732 clkreq-pins { <<
1733 pins <<
1734 funct <<
1735 drive <<
1736 bias- <<
1737 }; <<
1738 <<
1739 wake-pins { <<
1740 pins <<
1741 funct <<
1742 drive <<
1743 bias- <<
1744 }; <<
1745 }; <<
1746 <<
1747 pcie2_state_off: pcie <<
1748 /* Perst is m <<
1749 clkreq-pins { <<
1750 pins <<
1751 funct <<
1752 drive <<
1753 bias- <<
1754 }; <<
1755 <<
1756 wake-pins { <<
1757 pins <<
1758 funct <<
1759 drive <<
1760 bias- <<
1761 }; <<
1762 }; <<
1763 <<
1764 sdc1_state_on: sdc1-o <<
1765 clk-pins { <<
1766 pins <<
1767 bias- <<
1768 drive <<
1769 }; <<
1770 <<
1771 cmd-pins { <<
1772 pins <<
1773 bias- <<
1774 drive <<
1775 }; <<
1776 <<
1777 data-pins { <<
1778 pins <<
1779 bias- <<
1780 drive <<
1781 }; <<
1782 <<
1783 rclk-pins { <<
1784 pins <<
1785 bias- <<
1786 }; <<
1787 }; <<
1788 <<
1789 sdc1_state_off: sdc1- <<
1790 clk-pins { <<
1791 pins <<
1792 bias- <<
1793 drive <<
1794 }; <<
1795 <<
1796 cmd-pins { <<
1797 pins <<
1798 bias- <<
1799 drive <<
1800 }; <<
1801 <<
1802 data-pins { <<
1803 pins <<
1804 bias- <<
1805 drive <<
1806 }; <<
1807 <<
1808 rclk-pins { <<
1809 pins <<
1810 bias- <<
1811 }; <<
1812 }; <<
1813 <<
1814 sdc2_state_on: sdc2-o <<
1815 clk-pins { <<
1816 pins <<
1817 bias- <<
1818 drive <<
1819 }; <<
1820 <<
1821 cmd-pins { <<
1822 pins <<
1823 bias- <<
1824 drive <<
1825 }; <<
1826 <<
1827 data-pins { <<
1828 pins <<
1829 bias- <<
1830 drive <<
1831 }; <<
1832 }; <<
1833 <<
1834 sdc2_state_off: sdc2- <<
1835 clk-pins { <<
1836 pins <<
1837 bias- <<
1838 drive <<
1839 }; <<
1840 <<
1841 cmd-pins { <<
1842 pins <<
1843 bias- <<
1844 drive <<
1845 }; <<
1846 <<
1847 data-pins { <<
1848 pins <<
1849 bias- <<
1850 drive <<
1851 }; <<
1852 }; <<
1853 }; 705 };
1854 706
1855 sram@290000 { !! 707 spmi_bus: qcom,spmi@400f000 {
1856 compatible = "qcom,rp <<
1857 reg = <0x00290000 0x1 <<
1858 }; <<
1859 <<
1860 spmi_bus: spmi@400f000 { <<
1861 compatible = "qcom,sp 708 compatible = "qcom,spmi-pmic-arb";
1862 reg = <0x0400f000 0x1 709 reg = <0x0400f000 0x1000>,
1863 <0x04400000 0x8 710 <0x04400000 0x800000>,
1864 <0x04c00000 0x8 711 <0x04c00000 0x800000>,
1865 <0x05800000 0x2 712 <0x05800000 0x200000>,
1866 <0x0400a000 0x0 713 <0x0400a000 0x002100>;
1867 reg-names = "core", " 714 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1868 interrupt-names = "pe 715 interrupt-names = "periph_irq";
1869 interrupts = <GIC_SPI 716 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
1870 qcom,ee = <0>; 717 qcom,ee = <0>;
1871 qcom,channel = <0>; 718 qcom,channel = <0>;
1872 #address-cells = <2>; 719 #address-cells = <2>;
1873 #size-cells = <0>; 720 #size-cells = <0>;
1874 interrupt-controller; 721 interrupt-controller;
1875 #interrupt-cells = <4 722 #interrupt-cells = <4>;
1876 }; 723 };
1877 724
1878 bus@0 { !! 725 agnoc@0 {
1879 power-domains = <&gcc 726 power-domains = <&gcc AGGRE0_NOC_GDSC>;
1880 compatible = "simple- 727 compatible = "simple-pm-bus";
1881 #address-cells = <1>; 728 #address-cells = <1>;
1882 #size-cells = <1>; 729 #size-cells = <1>;
1883 ranges = <0x0 0x0 0xf !! 730 ranges;
1884 731
1885 pcie0: pcie@600000 { 732 pcie0: pcie@600000 {
1886 compatible = !! 733 compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
1887 status = "dis 734 status = "disabled";
1888 power-domains 735 power-domains = <&gcc PCIE0_GDSC>;
1889 bus-range = < 736 bus-range = <0x00 0xff>;
1890 num-lanes = < 737 num-lanes = <1>;
1891 738
1892 reg = <0x0060 739 reg = <0x00600000 0x2000>,
1893 <0x0c00 740 <0x0c000000 0xf1d>,
1894 <0x0c00 741 <0x0c000f20 0xa8>,
1895 <0x0c10 742 <0x0c100000 0x100000>;
1896 reg-names = " 743 reg-names = "parf", "dbi", "elbi","config";
1897 744
1898 phys = <&pcie 745 phys = <&pciephy_0>;
1899 phy-names = " 746 phy-names = "pciephy";
1900 747
1901 #address-cell 748 #address-cells = <3>;
1902 #size-cells = 749 #size-cells = <2>;
1903 ranges = <0x0 !! 750 ranges = <0x01000000 0x0 0x0c200000 0x0c200000 0x0 0x100000>,
1904 <0x0 !! 751 <0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>;
1905 <<
1906 device_type = <<
1907 752
1908 interrupts = 753 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
1909 interrupt-nam 754 interrupt-names = "msi";
1910 #interrupt-ce 755 #interrupt-cells = <1>;
1911 interrupt-map 756 interrupt-map-mask = <0 0 0 0x7>;
1912 interrupt-map 757 interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1913 758 <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1914 759 <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1915 760 <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1916 761
1917 pinctrl-names 762 pinctrl-names = "default", "sleep";
1918 pinctrl-0 = < !! 763 pinctrl-0 = <&pcie0_clkreq_default &pcie0_perst_default &pcie0_wake_default>;
1919 pinctrl-1 = < !! 764 pinctrl-1 = <&pcie0_clkreq_sleep &pcie0_perst_default &pcie0_wake_sleep>;
1920 765
1921 linux,pci-dom 766 linux,pci-domain = <0>;
1922 767
1923 clocks = <&gc 768 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
1924 <&gcc 769 <&gcc GCC_PCIE_0_AUX_CLK>,
1925 <&gcc 770 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1926 <&gcc 771 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1927 <&gcc 772 <&gcc GCC_PCIE_0_SLV_AXI_CLK>;
1928 773
1929 clock-names = !! 774 clock-names = "pipe",
1930 775 "aux",
1931 776 "cfg",
1932 777 "bus_master",
1933 778 "bus_slave";
1934 779
1935 pcie@0 { <<
1936 devic <<
1937 reg = <<
1938 bus-r <<
1939 <<
1940 #addr <<
1941 #size <<
1942 range <<
1943 }; <<
1944 }; 780 };
1945 781
1946 pcie1: pcie@608000 { 782 pcie1: pcie@608000 {
1947 compatible = !! 783 compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
1948 power-domains 784 power-domains = <&gcc PCIE1_GDSC>;
1949 bus-range = < 785 bus-range = <0x00 0xff>;
1950 num-lanes = < 786 num-lanes = <1>;
1951 787
1952 status = "dis !! 788 status = "disabled";
1953 789
1954 reg = <0x0060 790 reg = <0x00608000 0x2000>,
1955 <0x0d00 791 <0x0d000000 0xf1d>,
1956 <0x0d00 792 <0x0d000f20 0xa8>,
1957 <0x0d10 793 <0x0d100000 0x100000>;
1958 794
1959 reg-names = " 795 reg-names = "parf", "dbi", "elbi","config";
1960 796
1961 phys = <&pcie 797 phys = <&pciephy_1>;
1962 phy-names = " 798 phy-names = "pciephy";
1963 799
1964 #address-cell 800 #address-cells = <3>;
1965 #size-cells = 801 #size-cells = <2>;
1966 ranges = <0x0 !! 802 ranges = <0x01000000 0x0 0x0d200000 0x0d200000 0x0 0x100000>,
1967 <0x0 !! 803 <0x02000000 0x0 0x0d300000 0x0d300000 0x0 0xd00000>;
1968 <<
1969 device_type = <<
1970 804
1971 interrupts = 805 interrupts = <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>;
1972 interrupt-nam 806 interrupt-names = "msi";
1973 #interrupt-ce 807 #interrupt-cells = <1>;
1974 interrupt-map 808 interrupt-map-mask = <0 0 0 0x7>;
1975 interrupt-map 809 interrupt-map = <0 0 0 1 &intc 0 272 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1976 810 <0 0 0 2 &intc 0 273 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1977 811 <0 0 0 3 &intc 0 274 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1978 812 <0 0 0 4 &intc 0 275 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1979 813
1980 pinctrl-names 814 pinctrl-names = "default", "sleep";
1981 pinctrl-0 = < !! 815 pinctrl-0 = <&pcie1_clkreq_default &pcie1_perst_default &pcie1_wake_default>;
1982 pinctrl-1 = < !! 816 pinctrl-1 = <&pcie1_clkreq_sleep &pcie1_perst_default &pcie1_wake_sleep>;
1983 817
1984 linux,pci-dom 818 linux,pci-domain = <1>;
1985 819
1986 clocks = <&gc 820 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
1987 <&gcc 821 <&gcc GCC_PCIE_1_AUX_CLK>,
1988 <&gcc 822 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1989 <&gcc 823 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
1990 <&gcc 824 <&gcc GCC_PCIE_1_SLV_AXI_CLK>;
1991 825
1992 clock-names = !! 826 clock-names = "pipe",
1993 827 "aux",
1994 828 "cfg",
1995 829 "bus_master",
1996 830 "bus_slave";
1997 <<
1998 pcie@0 { <<
1999 devic <<
2000 reg = <<
2001 bus-r <<
2002 <<
2003 #addr <<
2004 #size <<
2005 range <<
2006 }; <<
2007 }; 831 };
2008 832
2009 pcie2: pcie@610000 { 833 pcie2: pcie@610000 {
2010 compatible = !! 834 compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
2011 power-domains 835 power-domains = <&gcc PCIE2_GDSC>;
2012 bus-range = < 836 bus-range = <0x00 0xff>;
2013 num-lanes = < 837 num-lanes = <1>;
2014 status = "dis 838 status = "disabled";
2015 reg = <0x0061 839 reg = <0x00610000 0x2000>,
2016 <0x0e00 840 <0x0e000000 0xf1d>,
2017 <0x0e00 841 <0x0e000f20 0xa8>,
2018 <0x0e10 842 <0x0e100000 0x100000>;
2019 843
2020 reg-names = " 844 reg-names = "parf", "dbi", "elbi","config";
2021 845
2022 phys = <&pcie 846 phys = <&pciephy_2>;
2023 phy-names = " 847 phy-names = "pciephy";
2024 848
2025 #address-cell 849 #address-cells = <3>;
2026 #size-cells = 850 #size-cells = <2>;
2027 ranges = <0x0 !! 851 ranges = <0x01000000 0x0 0x0e200000 0x0e200000 0x0 0x100000>,
2028 <0x0 !! 852 <0x02000000 0x0 0x0e300000 0x0e300000 0x0 0x1d00000>;
2029 853
2030 device_type = 854 device_type = "pci";
2031 855
2032 interrupts = 856 interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
2033 interrupt-nam 857 interrupt-names = "msi";
2034 #interrupt-ce 858 #interrupt-cells = <1>;
2035 interrupt-map 859 interrupt-map-mask = <0 0 0 0x7>;
2036 interrupt-map 860 interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2037 861 <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2038 862 <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2039 863 <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2040 864
2041 pinctrl-names 865 pinctrl-names = "default", "sleep";
2042 pinctrl-0 = < !! 866 pinctrl-0 = <&pcie2_clkreq_default &pcie2_perst_default &pcie2_wake_default>;
2043 pinctrl-1 = < !! 867 pinctrl-1 = <&pcie2_clkreq_sleep &pcie2_perst_default &pcie2_wake_sleep >;
2044 868
2045 linux,pci-dom 869 linux,pci-domain = <2>;
2046 clocks = <&gc 870 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,
2047 <&gcc 871 <&gcc GCC_PCIE_2_AUX_CLK>,
2048 <&gcc 872 <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
2049 <&gcc 873 <&gcc GCC_PCIE_2_MSTR_AXI_CLK>,
2050 <&gcc 874 <&gcc GCC_PCIE_2_SLV_AXI_CLK>;
2051 875
2052 clock-names = !! 876 clock-names = "pipe",
2053 877 "aux",
2054 878 "cfg",
2055 879 "bus_master",
2056 880 "bus_slave";
2057 <<
2058 pcie@0 { <<
2059 devic <<
2060 reg = <<
2061 bus-r <<
2062 <<
2063 #addr <<
2064 #size <<
2065 range <<
2066 }; <<
2067 }; 881 };
2068 }; 882 };
2069 883
2070 ufshc: ufshc@624000 { 884 ufshc: ufshc@624000 {
2071 compatible = "qcom,ms !! 885 compatible = "qcom,ufshc";
2072 "jedec,u <<
2073 reg = <0x00624000 0x2 886 reg = <0x00624000 0x2500>;
2074 interrupts = <GIC_SPI 887 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
2075 888
2076 phys = <&ufsphy>; !! 889 phys = <&ufsphy_lane>;
2077 phy-names = "ufsphy"; 890 phy-names = "ufsphy";
2078 891
2079 power-domains = <&gcc 892 power-domains = <&gcc UFS_GDSC>;
2080 893
2081 clock-names = 894 clock-names =
>> 895 "core_clk_src",
2082 "core_clk", 896 "core_clk",
2083 "bus_clk", 897 "bus_clk",
2084 "bus_aggr_clk 898 "bus_aggr_clk",
2085 "iface_clk", 899 "iface_clk",
>> 900 "core_clk_unipro_src",
2086 "core_clk_uni 901 "core_clk_unipro",
2087 "core_clk_ice 902 "core_clk_ice",
2088 "ref_clk", 903 "ref_clk",
2089 "tx_lane0_syn 904 "tx_lane0_sync_clk",
2090 "rx_lane0_syn 905 "rx_lane0_sync_clk";
2091 clocks = 906 clocks =
>> 907 <&gcc UFS_AXI_CLK_SRC>,
2092 <&gcc GCC_UFS 908 <&gcc GCC_UFS_AXI_CLK>,
2093 <&gcc GCC_SYS 909 <&gcc GCC_SYS_NOC_UFS_AXI_CLK>,
2094 <&gcc GCC_AGG 910 <&gcc GCC_AGGRE2_UFS_AXI_CLK>,
2095 <&gcc GCC_UFS 911 <&gcc GCC_UFS_AHB_CLK>,
>> 912 <&gcc UFS_ICE_CORE_CLK_SRC>,
2096 <&gcc GCC_UFS 913 <&gcc GCC_UFS_UNIPRO_CORE_CLK>,
2097 <&gcc GCC_UFS 914 <&gcc GCC_UFS_ICE_CORE_CLK>,
2098 <&rpmcc RPM_S 915 <&rpmcc RPM_SMD_LN_BB_CLK>,
2099 <&gcc GCC_UFS 916 <&gcc GCC_UFS_TX_SYMBOL_0_CLK>,
2100 <&gcc GCC_UFS 917 <&gcc GCC_UFS_RX_SYMBOL_0_CLK>;
2101 freq-table-hz = 918 freq-table-hz =
2102 <100000000 20 919 <100000000 200000000>,
2103 <0 0>, 920 <0 0>,
2104 <0 0>, 921 <0 0>,
2105 <0 0>, 922 <0 0>,
2106 <75000000 150 !! 923 <0 0>,
2107 <150000000 30 924 <150000000 300000000>,
2108 <0 0>, 925 <0 0>,
2109 <0 0>, 926 <0 0>,
>> 927 <0 0>,
>> 928 <0 0>,
2110 <0 0>; 929 <0 0>;
2111 930
2112 interconnects = <&a2n <<
2113 <&bim <<
2114 interconnect-names = <<
2115 <<
2116 lanes-per-direction = 931 lanes-per-direction = <1>;
2117 #reset-cells = <1>; 932 #reset-cells = <1>;
2118 status = "disabled"; 933 status = "disabled";
>> 934
>> 935 ufs_variant {
>> 936 compatible = "qcom,ufs_variant";
>> 937 };
2119 }; 938 };
2120 939
2121 ufsphy: phy@627000 { 940 ufsphy: phy@627000 {
2122 compatible = "qcom,ms 941 compatible = "qcom,msm8996-qmp-ufs-phy";
2123 reg = <0x00627000 0x1 !! 942 reg = <0x00627000 0x1c4>;
>> 943 #address-cells = <1>;
>> 944 #size-cells = <1>;
>> 945 ranges;
2124 946
2125 clocks = <&rpmcc RPM_ !! 947 clocks = <&gcc GCC_UFS_CLKREF_CLK>;
2126 clock-names = "ref", !! 948 clock-names = "ref";
2127 949
2128 resets = <&ufshc 0>; 950 resets = <&ufshc 0>;
2129 reset-names = "ufsphy 951 reset-names = "ufsphy";
2130 <<
2131 #clock-cells = <1>; <<
2132 #phy-cells = <0>; <<
2133 <<
2134 status = "disabled"; 952 status = "disabled";
>> 953
>> 954 ufsphy_lane: lanes@627400 {
>> 955 reg = <0x627400 0x12c>,
>> 956 <0x627600 0x200>,
>> 957 <0x627c00 0x1b4>;
>> 958 #phy-cells = <0>;
>> 959 };
2135 }; 960 };
2136 961
2137 camss: camss@a34000 { !! 962 camss: camss@a00000 {
2138 compatible = "qcom,ms 963 compatible = "qcom,msm8996-camss";
2139 reg = <0x00a34000 0x1 964 reg = <0x00a34000 0x1000>,
2140 <0x00a00030 0x4 965 <0x00a00030 0x4>,
2141 <0x00a35000 0x1 966 <0x00a35000 0x1000>,
2142 <0x00a00038 0x4 967 <0x00a00038 0x4>,
2143 <0x00a36000 0x1 968 <0x00a36000 0x1000>,
2144 <0x00a00040 0x4 969 <0x00a00040 0x4>,
2145 <0x00a30000 0x1 970 <0x00a30000 0x100>,
2146 <0x00a30400 0x1 971 <0x00a30400 0x100>,
2147 <0x00a30800 0x1 972 <0x00a30800 0x100>,
2148 <0x00a30c00 0x1 973 <0x00a30c00 0x100>,
2149 <0x00a31000 0x5 974 <0x00a31000 0x500>,
2150 <0x00a00020 0x1 975 <0x00a00020 0x10>,
2151 <0x00a10000 0x1 976 <0x00a10000 0x1000>,
2152 <0x00a14000 0x1 977 <0x00a14000 0x1000>;
2153 reg-names = "csiphy0" 978 reg-names = "csiphy0",
2154 "csiphy0_clk_ 979 "csiphy0_clk_mux",
2155 "csiphy1", 980 "csiphy1",
2156 "csiphy1_clk_ 981 "csiphy1_clk_mux",
2157 "csiphy2", 982 "csiphy2",
2158 "csiphy2_clk_ 983 "csiphy2_clk_mux",
2159 "csid0", 984 "csid0",
2160 "csid1", 985 "csid1",
2161 "csid2", 986 "csid2",
2162 "csid3", 987 "csid3",
2163 "ispif", 988 "ispif",
2164 "csi_clk_mux" 989 "csi_clk_mux",
2165 "vfe0", 990 "vfe0",
2166 "vfe1"; 991 "vfe1";
2167 interrupts = <GIC_SPI 992 interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
2168 <GIC_SPI 79 I 993 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
2169 <GIC_SPI 80 I 994 <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>,
2170 <GIC_SPI 296 995 <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>,
2171 <GIC_SPI 297 996 <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>,
2172 <GIC_SPI 298 997 <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>,
2173 <GIC_SPI 299 998 <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>,
2174 <GIC_SPI 309 999 <GIC_SPI 309 IRQ_TYPE_EDGE_RISING>,
2175 <GIC_SPI 314 1000 <GIC_SPI 314 IRQ_TYPE_EDGE_RISING>,
2176 <GIC_SPI 315 1001 <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>;
2177 interrupt-names = "cs 1002 interrupt-names = "csiphy0",
2178 "csiphy1", 1003 "csiphy1",
2179 "csiphy2", 1004 "csiphy2",
2180 "csid0", 1005 "csid0",
2181 "csid1", 1006 "csid1",
2182 "csid2", 1007 "csid2",
2183 "csid3", 1008 "csid3",
2184 "ispif", 1009 "ispif",
2185 "vfe0", 1010 "vfe0",
2186 "vfe1"; 1011 "vfe1";
2187 power-domains = <&mmc !! 1012 power-domains = <&mmcc VFE0_GDSC>;
2188 <&mmc <<
2189 clocks = <&mmcc CAMSS 1013 clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
2190 <&mmcc CAMSS_ 1014 <&mmcc CAMSS_ISPIF_AHB_CLK>,
2191 <&mmcc CAMSS_ 1015 <&mmcc CAMSS_CSI0PHYTIMER_CLK>,
2192 <&mmcc CAMSS_ 1016 <&mmcc CAMSS_CSI1PHYTIMER_CLK>,
2193 <&mmcc CAMSS_ 1017 <&mmcc CAMSS_CSI2PHYTIMER_CLK>,
2194 <&mmcc CAMSS_ 1018 <&mmcc CAMSS_CSI0_AHB_CLK>,
2195 <&mmcc CAMSS_ 1019 <&mmcc CAMSS_CSI0_CLK>,
2196 <&mmcc CAMSS_ 1020 <&mmcc CAMSS_CSI0PHY_CLK>,
2197 <&mmcc CAMSS_ 1021 <&mmcc CAMSS_CSI0PIX_CLK>,
2198 <&mmcc CAMSS_ 1022 <&mmcc CAMSS_CSI0RDI_CLK>,
2199 <&mmcc CAMSS_ 1023 <&mmcc CAMSS_CSI1_AHB_CLK>,
2200 <&mmcc CAMSS_ 1024 <&mmcc CAMSS_CSI1_CLK>,
2201 <&mmcc CAMSS_ 1025 <&mmcc CAMSS_CSI1PHY_CLK>,
2202 <&mmcc CAMSS_ 1026 <&mmcc CAMSS_CSI1PIX_CLK>,
2203 <&mmcc CAMSS_ 1027 <&mmcc CAMSS_CSI1RDI_CLK>,
2204 <&mmcc CAMSS_ 1028 <&mmcc CAMSS_CSI2_AHB_CLK>,
2205 <&mmcc CAMSS_ 1029 <&mmcc CAMSS_CSI2_CLK>,
2206 <&mmcc CAMSS_ 1030 <&mmcc CAMSS_CSI2PHY_CLK>,
2207 <&mmcc CAMSS_ 1031 <&mmcc CAMSS_CSI2PIX_CLK>,
2208 <&mmcc CAMSS_ 1032 <&mmcc CAMSS_CSI2RDI_CLK>,
2209 <&mmcc CAMSS_ 1033 <&mmcc CAMSS_CSI3_AHB_CLK>,
2210 <&mmcc CAMSS_ 1034 <&mmcc CAMSS_CSI3_CLK>,
2211 <&mmcc CAMSS_ 1035 <&mmcc CAMSS_CSI3PHY_CLK>,
2212 <&mmcc CAMSS_ 1036 <&mmcc CAMSS_CSI3PIX_CLK>,
2213 <&mmcc CAMSS_ 1037 <&mmcc CAMSS_CSI3RDI_CLK>,
2214 <&mmcc CAMSS_ 1038 <&mmcc CAMSS_AHB_CLK>,
2215 <&mmcc CAMSS_ 1039 <&mmcc CAMSS_VFE0_CLK>,
2216 <&mmcc CAMSS_ 1040 <&mmcc CAMSS_CSI_VFE0_CLK>,
2217 <&mmcc CAMSS_ 1041 <&mmcc CAMSS_VFE0_AHB_CLK>,
2218 <&mmcc CAMSS_ 1042 <&mmcc CAMSS_VFE0_STREAM_CLK>,
2219 <&mmcc CAMSS_ 1043 <&mmcc CAMSS_VFE1_CLK>,
2220 <&mmcc CAMSS_ 1044 <&mmcc CAMSS_CSI_VFE1_CLK>,
2221 <&mmcc CAMSS_ 1045 <&mmcc CAMSS_VFE1_AHB_CLK>,
2222 <&mmcc CAMSS_ 1046 <&mmcc CAMSS_VFE1_STREAM_CLK>,
2223 <&mmcc CAMSS_ 1047 <&mmcc CAMSS_VFE_AHB_CLK>,
2224 <&mmcc CAMSS_ 1048 <&mmcc CAMSS_VFE_AXI_CLK>;
2225 clock-names = "top_ah 1049 clock-names = "top_ahb",
2226 "ispif_ahb", 1050 "ispif_ahb",
2227 "csiphy0_time 1051 "csiphy0_timer",
2228 "csiphy1_time 1052 "csiphy1_timer",
2229 "csiphy2_time 1053 "csiphy2_timer",
2230 "csi0_ahb", 1054 "csi0_ahb",
2231 "csi0", 1055 "csi0",
2232 "csi0_phy", 1056 "csi0_phy",
2233 "csi0_pix", 1057 "csi0_pix",
2234 "csi0_rdi", 1058 "csi0_rdi",
2235 "csi1_ahb", 1059 "csi1_ahb",
2236 "csi1", 1060 "csi1",
2237 "csi1_phy", 1061 "csi1_phy",
2238 "csi1_pix", 1062 "csi1_pix",
2239 "csi1_rdi", 1063 "csi1_rdi",
2240 "csi2_ahb", 1064 "csi2_ahb",
2241 "csi2", 1065 "csi2",
2242 "csi2_phy", 1066 "csi2_phy",
2243 "csi2_pix", 1067 "csi2_pix",
2244 "csi2_rdi", 1068 "csi2_rdi",
2245 "csi3_ahb", 1069 "csi3_ahb",
2246 "csi3", 1070 "csi3",
2247 "csi3_phy", 1071 "csi3_phy",
2248 "csi3_pix", 1072 "csi3_pix",
2249 "csi3_rdi", 1073 "csi3_rdi",
2250 "ahb", 1074 "ahb",
2251 "vfe0", 1075 "vfe0",
2252 "csi_vfe0", 1076 "csi_vfe0",
2253 "vfe0_ahb", 1077 "vfe0_ahb",
2254 "vfe0_stream" 1078 "vfe0_stream",
2255 "vfe1", 1079 "vfe1",
2256 "csi_vfe1", 1080 "csi_vfe1",
2257 "vfe1_ahb", 1081 "vfe1_ahb",
2258 "vfe1_stream" 1082 "vfe1_stream",
2259 "vfe_ahb", 1083 "vfe_ahb",
2260 "vfe_axi"; 1084 "vfe_axi";
2261 iommus = <&vfe_smmu 0 1085 iommus = <&vfe_smmu 0>,
2262 <&vfe_smmu 1 1086 <&vfe_smmu 1>,
2263 <&vfe_smmu 2 1087 <&vfe_smmu 2>,
2264 <&vfe_smmu 3 1088 <&vfe_smmu 3>;
2265 status = "disabled"; 1089 status = "disabled";
2266 ports { 1090 ports {
2267 #address-cell 1091 #address-cells = <1>;
2268 #size-cells = 1092 #size-cells = <0>;
2269 }; 1093 };
2270 }; 1094 };
2271 1095
2272 cci: cci@a0c000 { 1096 cci: cci@a0c000 {
2273 compatible = "qcom,ms 1097 compatible = "qcom,msm8996-cci";
2274 #address-cells = <1>; 1098 #address-cells = <1>;
2275 #size-cells = <0>; 1099 #size-cells = <0>;
2276 reg = <0xa0c000 0x100 1100 reg = <0xa0c000 0x1000>;
2277 interrupts = <GIC_SPI 1101 interrupts = <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>;
2278 power-domains = <&mmc 1102 power-domains = <&mmcc CAMSS_GDSC>;
2279 clocks = <&mmcc CAMSS 1103 clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
2280 <&mmcc CAMSS 1104 <&mmcc CAMSS_CCI_AHB_CLK>,
2281 <&mmcc CAMSS 1105 <&mmcc CAMSS_CCI_CLK>,
2282 <&mmcc CAMSS 1106 <&mmcc CAMSS_AHB_CLK>;
2283 clock-names = "camss_ 1107 clock-names = "camss_top_ahb",
2284 "cci_ah 1108 "cci_ahb",
2285 "cci", 1109 "cci",
2286 "camss_ 1110 "camss_ahb";
2287 assigned-clocks = <&m 1111 assigned-clocks = <&mmcc CAMSS_CCI_AHB_CLK>,
2288 <&m 1112 <&mmcc CAMSS_CCI_CLK>;
2289 assigned-clock-rates 1113 assigned-clock-rates = <80000000>, <37500000>;
2290 pinctrl-names = "defa 1114 pinctrl-names = "default";
2291 pinctrl-0 = <&cci0_de 1115 pinctrl-0 = <&cci0_default &cci1_default>;
2292 status = "disabled"; 1116 status = "disabled";
2293 1117
2294 cci_i2c0: i2c-bus@0 { 1118 cci_i2c0: i2c-bus@0 {
2295 reg = <0>; 1119 reg = <0>;
2296 clock-frequen 1120 clock-frequency = <400000>;
2297 #address-cell 1121 #address-cells = <1>;
2298 #size-cells = 1122 #size-cells = <0>;
2299 }; 1123 };
2300 1124
2301 cci_i2c1: i2c-bus@1 { 1125 cci_i2c1: i2c-bus@1 {
2302 reg = <1>; 1126 reg = <1>;
2303 clock-frequen 1127 clock-frequency = <400000>;
2304 #address-cell 1128 #address-cells = <1>;
2305 #size-cells = 1129 #size-cells = <0>;
2306 }; 1130 };
2307 }; 1131 };
2308 1132
2309 adreno_smmu: iommu@b40000 { 1133 adreno_smmu: iommu@b40000 {
2310 compatible = "qcom,ms !! 1134 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2311 reg = <0x00b40000 0x1 1135 reg = <0x00b40000 0x10000>;
2312 1136
2313 #global-interrupts = 1137 #global-interrupts = <1>;
2314 interrupts = <GIC_SPI 1138 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
2315 <GIC_SPI 1139 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
2316 <GIC_SPI 1140 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
2317 #iommu-cells = <1>; 1141 #iommu-cells = <1>;
2318 1142
2319 clocks = <&gcc GCC_MM !! 1143 clocks = <&mmcc GPU_AHB_CLK>,
2320 <&mmcc GPU_A !! 1144 <&gcc GCC_MMSS_BIMC_GFX_CLK>;
2321 clock-names = "bus", !! 1145 clock-names = "iface", "bus";
2322 1146
2323 power-domains = <&mmc 1147 power-domains = <&mmcc GPU_GDSC>;
2324 }; 1148 };
2325 1149
2326 venus: video-codec@c00000 { !! 1150 video-codec@c00000 {
2327 compatible = "qcom,ms 1151 compatible = "qcom,msm8996-venus";
2328 reg = <0x00c00000 0xf 1152 reg = <0x00c00000 0xff000>;
2329 interrupts = <GIC_SPI 1153 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
2330 power-domains = <&mmc 1154 power-domains = <&mmcc VENUS_GDSC>;
2331 clocks = <&mmcc VIDEO 1155 clocks = <&mmcc VIDEO_CORE_CLK>,
2332 <&mmcc VIDEO 1156 <&mmcc VIDEO_AHB_CLK>,
2333 <&mmcc VIDEO 1157 <&mmcc VIDEO_AXI_CLK>,
2334 <&mmcc VIDEO 1158 <&mmcc VIDEO_MAXI_CLK>;
2335 clock-names = "core", 1159 clock-names = "core", "iface", "bus", "mbus";
2336 interconnects = <&mno <<
2337 <&bim <<
2338 interconnect-names = <<
2339 iommus = <&venus_smmu 1160 iommus = <&venus_smmu 0x00>,
2340 <&venus_smmu 1161 <&venus_smmu 0x01>,
2341 <&venus_smmu 1162 <&venus_smmu 0x0a>,
2342 <&venus_smmu 1163 <&venus_smmu 0x07>,
2343 <&venus_smmu 1164 <&venus_smmu 0x0e>,
2344 <&venus_smmu 1165 <&venus_smmu 0x0f>,
2345 <&venus_smmu 1166 <&venus_smmu 0x08>,
2346 <&venus_smmu 1167 <&venus_smmu 0x09>,
2347 <&venus_smmu 1168 <&venus_smmu 0x0b>,
2348 <&venus_smmu 1169 <&venus_smmu 0x0c>,
2349 <&venus_smmu 1170 <&venus_smmu 0x0d>,
2350 <&venus_smmu 1171 <&venus_smmu 0x10>,
2351 <&venus_smmu 1172 <&venus_smmu 0x11>,
2352 <&venus_smmu 1173 <&venus_smmu 0x21>,
2353 <&venus_smmu 1174 <&venus_smmu 0x28>,
2354 <&venus_smmu 1175 <&venus_smmu 0x29>,
2355 <&venus_smmu 1176 <&venus_smmu 0x2b>,
2356 <&venus_smmu 1177 <&venus_smmu 0x2c>,
2357 <&venus_smmu 1178 <&venus_smmu 0x2d>,
2358 <&venus_smmu 1179 <&venus_smmu 0x31>;
2359 memory-region = <&ven !! 1180 memory-region = <&venus_region>;
2360 status = "disabled"; !! 1181 status = "okay";
2361 1182
2362 video-decoder { 1183 video-decoder {
2363 compatible = 1184 compatible = "venus-decoder";
2364 clocks = <&mm 1185 clocks = <&mmcc VIDEO_SUBCORE0_CLK>;
2365 clock-names = 1186 clock-names = "core";
2366 power-domains 1187 power-domains = <&mmcc VENUS_CORE0_GDSC>;
2367 }; 1188 };
2368 1189
2369 video-encoder { 1190 video-encoder {
2370 compatible = 1191 compatible = "venus-encoder";
2371 clocks = <&mm 1192 clocks = <&mmcc VIDEO_SUBCORE1_CLK>;
2372 clock-names = 1193 clock-names = "core";
2373 power-domains 1194 power-domains = <&mmcc VENUS_CORE1_GDSC>;
2374 }; 1195 };
2375 }; 1196 };
2376 1197
2377 mdp_smmu: iommu@d00000 { 1198 mdp_smmu: iommu@d00000 {
2378 compatible = "qcom,ms 1199 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2379 reg = <0x00d00000 0x1 1200 reg = <0x00d00000 0x10000>;
2380 1201
2381 #global-interrupts = 1202 #global-interrupts = <1>;
2382 interrupts = <GIC_SPI 1203 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
2383 <GIC_SPI 1204 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
2384 <GIC_SPI 1205 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
2385 #iommu-cells = <1>; 1206 #iommu-cells = <1>;
2386 clocks = <&mmcc SMMU_ !! 1207 clocks = <&mmcc SMMU_MDP_AHB_CLK>,
2387 <&mmcc SMMU_ !! 1208 <&mmcc SMMU_MDP_AXI_CLK>;
2388 clock-names = "bus", !! 1209 clock-names = "iface", "bus";
2389 1210
2390 power-domains = <&mmc 1211 power-domains = <&mmcc MDSS_GDSC>;
2391 }; 1212 };
2392 1213
2393 venus_smmu: iommu@d40000 { 1214 venus_smmu: iommu@d40000 {
2394 compatible = "qcom,ms 1215 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2395 reg = <0x00d40000 0x2 1216 reg = <0x00d40000 0x20000>;
2396 #global-interrupts = 1217 #global-interrupts = <1>;
2397 interrupts = <GIC_SPI 1218 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>,
2398 <GIC_SPI 1219 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
2399 <GIC_SPI 1220 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
2400 <GIC_SPI 1221 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
2401 <GIC_SPI 1222 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
2402 <GIC_SPI 1223 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
2403 <GIC_SPI 1224 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
2404 <GIC_SPI 1225 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
2405 power-domains = <&mmc 1226 power-domains = <&mmcc MMAGIC_VIDEO_GDSC>;
2406 clocks = <&mmcc SMMU_ !! 1227 clocks = <&mmcc SMMU_VIDEO_AHB_CLK>,
2407 <&mmcc SMMU_ !! 1228 <&mmcc SMMU_VIDEO_AXI_CLK>;
2408 clock-names = "bus", !! 1229 clock-names = "iface", "bus";
2409 #iommu-cells = <1>; 1230 #iommu-cells = <1>;
2410 status = "okay"; 1231 status = "okay";
2411 }; 1232 };
2412 1233
2413 vfe_smmu: iommu@da0000 { 1234 vfe_smmu: iommu@da0000 {
2414 compatible = "qcom,ms 1235 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2415 reg = <0x00da0000 0x1 1236 reg = <0x00da0000 0x10000>;
2416 1237
2417 #global-interrupts = 1238 #global-interrupts = <1>;
2418 interrupts = <GIC_SPI 1239 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
2419 <GIC_SPI 1240 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
2420 <GIC_SPI 1241 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
2421 power-domains = <&mmc 1242 power-domains = <&mmcc MMAGIC_CAMSS_GDSC>;
2422 clocks = <&mmcc SMMU_ !! 1243 clocks = <&mmcc SMMU_VFE_AHB_CLK>,
2423 <&mmcc SMMU_ !! 1244 <&mmcc SMMU_VFE_AXI_CLK>;
2424 clock-names = "bus", !! 1245 clock-names = "iface",
>> 1246 "bus";
2425 #iommu-cells = <1>; 1247 #iommu-cells = <1>;
2426 }; 1248 };
2427 1249
2428 lpass_q6_smmu: iommu@1600000 1250 lpass_q6_smmu: iommu@1600000 {
2429 compatible = "qcom,ms 1251 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2430 reg = <0x01600000 0x2 1252 reg = <0x01600000 0x20000>;
2431 #iommu-cells = <1>; 1253 #iommu-cells = <1>;
2432 power-domains = <&gcc 1254 power-domains = <&gcc HLOS1_VOTE_LPASS_CORE_GDSC>;
2433 1255
2434 #global-interrupts = 1256 #global-interrupts = <1>;
2435 interrupts = <GIC_SPI 1257 interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
2436 <GIC_SPI 226 1258 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,
2437 <GIC_SPI 393 1259 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
2438 <GIC_SPI 394 1260 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
2439 <GIC_SPI 395 1261 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
2440 <GIC_SPI 396 1262 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
2441 <GIC_SPI 397 1263 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
2442 <GIC_SPI 398 1264 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
2443 <GIC_SPI 399 1265 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
2444 <GIC_SPI 400 1266 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
2445 <GIC_SPI 401 1267 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
2446 <GIC_SPI 402 1268 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
2447 <GIC_SPI 403 1269 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>;
2448 1270
2449 clocks = <&gcc GCC_HL !! 1271 clocks = <&gcc GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK>,
2450 <&gcc GCC_HL !! 1272 <&gcc GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>;
2451 clock-names = "bus", !! 1273 clock-names = "iface", "bus";
2452 }; <<
2453 <<
2454 slpi_pil: remoteproc@1c00000 <<
2455 compatible = "qcom,ms <<
2456 reg = <0x01c00000 0x4 <<
2457 <<
2458 interrupts-extended = <<
2459 <<
2460 <<
2461 <<
2462 <<
2463 interrupt-names = "wd <<
2464 "fa <<
2465 "re <<
2466 "ha <<
2467 "st <<
2468 <<
2469 clocks = <&xo_board>; <<
2470 clock-names = "xo"; <<
2471 <<
2472 memory-region = <&slp <<
2473 <<
2474 qcom,smem-states = <& <<
2475 qcom,smem-state-names <<
2476 <<
2477 power-domains = <&rpm <<
2478 power-domain-names = <<
2479 <<
2480 status = "disabled"; <<
2481 <<
2482 glink-edge { <<
2483 interrupts = <<
2484 label = "dsps <<
2485 qcom,remote-p <<
2486 mboxes = <&ap <<
2487 }; <<
2488 <<
2489 smd-edge { <<
2490 interrupts = <<
2491 <<
2492 label = "dsps <<
2493 mboxes = <&ap <<
2494 qcom,smd-edge <<
2495 qcom,remote-p <<
2496 }; <<
2497 }; <<
2498 <<
2499 mss_pil: remoteproc@2080000 { <<
2500 compatible = "qcom,ms <<
2501 reg = <0x2080000 0x10 <<
2502 <0x2180000 0x02 <<
2503 reg-names = "qdsp6", <<
2504 <<
2505 interrupts-extended = <<
2506 <<
2507 <<
2508 <<
2509 <<
2510 <<
2511 interrupt-names = "wd <<
2512 "ha <<
2513 "sh <<
2514 <<
2515 clocks = <&gcc GCC_MS <<
2516 <&gcc GCC_MS <<
2517 <&gcc GCC_BO <<
2518 <&xo_board>, <<
2519 <&gcc GCC_MS <<
2520 <&gcc GCC_MS <<
2521 <&gcc GCC_MS <<
2522 <&rpmcc RPM_ <<
2523 clock-names = "iface" <<
2524 "bus", <<
2525 "mem", <<
2526 "xo", <<
2527 "gpll0_ <<
2528 "snoc_a <<
2529 "mnoc_a <<
2530 "qdss"; <<
2531 <<
2532 resets = <&gcc GCC_MS <<
2533 reset-names = "mss_re <<
2534 <<
2535 power-domains = <&rpm <<
2536 <&rpm <<
2537 power-domain-names = <<
2538 <<
2539 qcom,smem-states = <& <<
2540 qcom,smem-state-names <<
2541 <<
2542 qcom,halt-regs = <&tc <<
2543 <<
2544 status = "disabled"; <<
2545 <<
2546 mba { <<
2547 memory-region <<
2548 }; <<
2549 <<
2550 mpss { <<
2551 memory-region <<
2552 }; <<
2553 <<
2554 metadata { <<
2555 memory-region <<
2556 }; <<
2557 <<
2558 glink-edge { <<
2559 interrupts = <<
2560 label = "mode <<
2561 qcom,remote-p <<
2562 mboxes = <&ap <<
2563 }; <<
2564 <<
2565 smd-edge { <<
2566 interrupts = <<
2567 <<
2568 label = "mpss <<
2569 mboxes = <&ap <<
2570 qcom,smd-edge <<
2571 qcom,remote-p <<
2572 }; <<
2573 }; 1274 };
2574 1275
2575 stm@3002000 { 1276 stm@3002000 {
2576 compatible = "arm,cor 1277 compatible = "arm,coresight-stm", "arm,primecell";
2577 reg = <0x3002000 0x10 1278 reg = <0x3002000 0x1000>,
2578 <0x8280000 0x18 1279 <0x8280000 0x180000>;
2579 reg-names = "stm-base 1280 reg-names = "stm-base", "stm-stimulus-base";
2580 1281
2581 clocks = <&rpmcc RPM_ 1282 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2582 clock-names = "apb_pc 1283 clock-names = "apb_pclk", "atclk";
2583 1284
2584 out-ports { 1285 out-ports {
2585 port { 1286 port {
2586 stm_o 1287 stm_out: endpoint {
2587 1288 remote-endpoint =
2588 1289 <&funnel0_in>;
2589 }; 1290 };
2590 }; 1291 };
2591 }; 1292 };
2592 }; 1293 };
2593 1294
2594 tpiu@3020000 { 1295 tpiu@3020000 {
2595 compatible = "arm,cor 1296 compatible = "arm,coresight-tpiu", "arm,primecell";
2596 reg = <0x3020000 0x10 1297 reg = <0x3020000 0x1000>;
2597 1298
2598 clocks = <&rpmcc RPM_ 1299 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2599 clock-names = "apb_pc 1300 clock-names = "apb_pclk", "atclk";
2600 1301
2601 in-ports { 1302 in-ports {
2602 port { 1303 port {
2603 tpiu_ 1304 tpiu_in: endpoint {
2604 1305 remote-endpoint =
2605 1306 <&replicator_out1>;
2606 }; 1307 };
2607 }; 1308 };
2608 }; 1309 };
2609 }; 1310 };
2610 1311
2611 funnel@3021000 { 1312 funnel@3021000 {
2612 compatible = "arm,cor 1313 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2613 reg = <0x3021000 0x10 1314 reg = <0x3021000 0x1000>;
2614 1315
2615 clocks = <&rpmcc RPM_ 1316 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2616 clock-names = "apb_pc 1317 clock-names = "apb_pclk", "atclk";
2617 1318
2618 in-ports { 1319 in-ports {
2619 #address-cell 1320 #address-cells = <1>;
2620 #size-cells = 1321 #size-cells = <0>;
2621 1322
2622 port@7 { 1323 port@7 {
2623 reg = 1324 reg = <7>;
2624 funne 1325 funnel0_in: endpoint {
2625 1326 remote-endpoint =
2626 1327 <&stm_out>;
2627 }; 1328 };
2628 }; 1329 };
2629 }; 1330 };
2630 1331
2631 out-ports { 1332 out-ports {
2632 port { 1333 port {
2633 funne 1334 funnel0_out: endpoint {
2634 1335 remote-endpoint =
2635 1336 <&merge_funnel_in0>;
2636 }; 1337 };
2637 }; 1338 };
2638 }; 1339 };
2639 }; 1340 };
2640 1341
2641 funnel@3022000 { 1342 funnel@3022000 {
2642 compatible = "arm,cor 1343 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2643 reg = <0x3022000 0x10 1344 reg = <0x3022000 0x1000>;
2644 1345
2645 clocks = <&rpmcc RPM_ 1346 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2646 clock-names = "apb_pc 1347 clock-names = "apb_pclk", "atclk";
2647 1348
2648 in-ports { 1349 in-ports {
2649 #address-cell 1350 #address-cells = <1>;
2650 #size-cells = 1351 #size-cells = <0>;
2651 1352
2652 port@6 { 1353 port@6 {
2653 reg = 1354 reg = <6>;
2654 funne 1355 funnel1_in: endpoint {
2655 1356 remote-endpoint =
2656 1357 <&apss_merge_funnel_out>;
2657 }; 1358 };
2658 }; 1359 };
2659 }; 1360 };
2660 1361
2661 out-ports { 1362 out-ports {
2662 port { 1363 port {
2663 funne 1364 funnel1_out: endpoint {
2664 1365 remote-endpoint =
2665 1366 <&merge_funnel_in1>;
2666 }; 1367 };
2667 }; 1368 };
2668 }; 1369 };
2669 }; 1370 };
2670 1371
2671 funnel@3023000 { 1372 funnel@3023000 {
2672 compatible = "arm,cor 1373 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2673 reg = <0x3023000 0x10 1374 reg = <0x3023000 0x1000>;
2674 1375
2675 clocks = <&rpmcc RPM_ 1376 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2676 clock-names = "apb_pc 1377 clock-names = "apb_pclk", "atclk";
2677 1378
2678 in-ports { <<
2679 port { <<
2680 funne <<
2681 <<
2682 <<
2683 }; <<
2684 }; <<
2685 }; <<
2686 1379
2687 out-ports { 1380 out-ports {
2688 port { 1381 port {
2689 funne 1382 funnel2_out: endpoint {
2690 1383 remote-endpoint =
2691 1384 <&merge_funnel_in2>;
2692 }; 1385 };
2693 }; 1386 };
2694 }; 1387 };
2695 }; 1388 };
2696 1389
2697 funnel@3025000 { 1390 funnel@3025000 {
2698 compatible = "arm,cor 1391 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2699 reg = <0x3025000 0x10 1392 reg = <0x3025000 0x1000>;
2700 1393
2701 clocks = <&rpmcc RPM_ 1394 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2702 clock-names = "apb_pc 1395 clock-names = "apb_pclk", "atclk";
2703 1396
2704 in-ports { 1397 in-ports {
2705 #address-cell 1398 #address-cells = <1>;
2706 #size-cells = 1399 #size-cells = <0>;
2707 1400
2708 port@0 { 1401 port@0 {
2709 reg = 1402 reg = <0>;
2710 merge 1403 merge_funnel_in0: endpoint {
2711 1404 remote-endpoint =
2712 1405 <&funnel0_out>;
2713 }; 1406 };
2714 }; 1407 };
2715 1408
2716 port@1 { 1409 port@1 {
2717 reg = 1410 reg = <1>;
2718 merge 1411 merge_funnel_in1: endpoint {
2719 1412 remote-endpoint =
2720 1413 <&funnel1_out>;
2721 }; 1414 };
2722 }; 1415 };
2723 1416
2724 port@2 { 1417 port@2 {
2725 reg = 1418 reg = <2>;
2726 merge 1419 merge_funnel_in2: endpoint {
2727 1420 remote-endpoint =
2728 1421 <&funnel2_out>;
2729 }; 1422 };
2730 }; 1423 };
2731 }; 1424 };
2732 1425
2733 out-ports { 1426 out-ports {
2734 port { 1427 port {
2735 merge 1428 merge_funnel_out: endpoint {
2736 1429 remote-endpoint =
2737 1430 <&etf_in>;
2738 }; 1431 };
2739 }; 1432 };
2740 }; 1433 };
2741 }; 1434 };
2742 1435
2743 replicator@3026000 { 1436 replicator@3026000 {
2744 compatible = "arm,cor 1437 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2745 reg = <0x3026000 0x10 1438 reg = <0x3026000 0x1000>;
2746 1439
2747 clocks = <&rpmcc RPM_ 1440 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2748 clock-names = "apb_pc 1441 clock-names = "apb_pclk", "atclk";
2749 1442
2750 in-ports { 1443 in-ports {
2751 port { 1444 port {
2752 repli 1445 replicator_in: endpoint {
2753 1446 remote-endpoint =
2754 1447 <&etf_out>;
2755 }; 1448 };
2756 }; 1449 };
2757 }; 1450 };
2758 1451
2759 out-ports { 1452 out-ports {
2760 #address-cell 1453 #address-cells = <1>;
2761 #size-cells = 1454 #size-cells = <0>;
2762 1455
2763 port@0 { 1456 port@0 {
2764 reg = 1457 reg = <0>;
2765 repli 1458 replicator_out0: endpoint {
2766 1459 remote-endpoint =
2767 1460 <&etr_in>;
2768 }; 1461 };
2769 }; 1462 };
2770 1463
2771 port@1 { 1464 port@1 {
2772 reg = 1465 reg = <1>;
2773 repli 1466 replicator_out1: endpoint {
2774 1467 remote-endpoint =
2775 1468 <&tpiu_in>;
2776 }; 1469 };
2777 }; 1470 };
2778 }; 1471 };
2779 }; 1472 };
2780 1473
2781 etf@3027000 { 1474 etf@3027000 {
2782 compatible = "arm,cor 1475 compatible = "arm,coresight-tmc", "arm,primecell";
2783 reg = <0x3027000 0x10 1476 reg = <0x3027000 0x1000>;
2784 1477
2785 clocks = <&rpmcc RPM_ 1478 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2786 clock-names = "apb_pc 1479 clock-names = "apb_pclk", "atclk";
2787 1480
2788 in-ports { 1481 in-ports {
2789 port { 1482 port {
2790 etf_i 1483 etf_in: endpoint {
2791 1484 remote-endpoint =
2792 1485 <&merge_funnel_out>;
2793 }; 1486 };
2794 }; 1487 };
2795 }; 1488 };
2796 1489
2797 out-ports { 1490 out-ports {
2798 port { 1491 port {
2799 etf_o 1492 etf_out: endpoint {
2800 1493 remote-endpoint =
2801 1494 <&replicator_in>;
2802 }; 1495 };
2803 }; 1496 };
2804 }; 1497 };
2805 }; 1498 };
2806 1499
2807 etr@3028000 { 1500 etr@3028000 {
2808 compatible = "arm,cor 1501 compatible = "arm,coresight-tmc", "arm,primecell";
2809 reg = <0x3028000 0x10 1502 reg = <0x3028000 0x1000>;
2810 1503
2811 clocks = <&rpmcc RPM_ 1504 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2812 clock-names = "apb_pc 1505 clock-names = "apb_pclk", "atclk";
2813 arm,scatter-gather; 1506 arm,scatter-gather;
2814 1507
2815 in-ports { 1508 in-ports {
2816 port { 1509 port {
2817 etr_i 1510 etr_in: endpoint {
2818 1511 remote-endpoint =
2819 1512 <&replicator_out0>;
2820 }; 1513 };
2821 }; 1514 };
2822 }; 1515 };
2823 }; 1516 };
2824 1517
2825 debug@3810000 { 1518 debug@3810000 {
2826 compatible = "arm,cor 1519 compatible = "arm,coresight-cpu-debug", "arm,primecell";
2827 reg = <0x3810000 0x10 1520 reg = <0x3810000 0x1000>;
2828 1521
2829 clocks = <&rpmcc RPM_ 1522 clocks = <&rpmcc RPM_QDSS_CLK>;
2830 clock-names = "apb_pc 1523 clock-names = "apb_pclk";
2831 1524
2832 cpu = <&CPU0>; 1525 cpu = <&CPU0>;
2833 }; 1526 };
2834 1527
2835 etm@3840000 { 1528 etm@3840000 {
2836 compatible = "arm,cor 1529 compatible = "arm,coresight-etm4x", "arm,primecell";
2837 reg = <0x3840000 0x10 1530 reg = <0x3840000 0x1000>;
2838 1531
2839 clocks = <&rpmcc RPM_ 1532 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2840 clock-names = "apb_pc 1533 clock-names = "apb_pclk", "atclk";
2841 1534
2842 cpu = <&CPU0>; 1535 cpu = <&CPU0>;
2843 1536
2844 out-ports { 1537 out-ports {
2845 port { 1538 port {
2846 etm0_ 1539 etm0_out: endpoint {
2847 1540 remote-endpoint =
2848 1541 <&apss_funnel0_in0>;
2849 }; 1542 };
2850 }; 1543 };
2851 }; 1544 };
2852 }; 1545 };
2853 1546
2854 debug@3910000 { 1547 debug@3910000 {
2855 compatible = "arm,cor 1548 compatible = "arm,coresight-cpu-debug", "arm,primecell";
2856 reg = <0x3910000 0x10 1549 reg = <0x3910000 0x1000>;
2857 1550
2858 clocks = <&rpmcc RPM_ 1551 clocks = <&rpmcc RPM_QDSS_CLK>;
2859 clock-names = "apb_pc 1552 clock-names = "apb_pclk";
2860 1553
2861 cpu = <&CPU1>; 1554 cpu = <&CPU1>;
2862 }; 1555 };
2863 1556
2864 etm@3940000 { 1557 etm@3940000 {
2865 compatible = "arm,cor 1558 compatible = "arm,coresight-etm4x", "arm,primecell";
2866 reg = <0x3940000 0x10 1559 reg = <0x3940000 0x1000>;
2867 1560
2868 clocks = <&rpmcc RPM_ 1561 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2869 clock-names = "apb_pc 1562 clock-names = "apb_pclk", "atclk";
2870 1563
2871 cpu = <&CPU1>; 1564 cpu = <&CPU1>;
2872 1565
2873 out-ports { 1566 out-ports {
2874 port { 1567 port {
2875 etm1_ 1568 etm1_out: endpoint {
2876 1569 remote-endpoint =
2877 1570 <&apss_funnel0_in1>;
2878 }; 1571 };
2879 }; 1572 };
2880 }; 1573 };
2881 }; 1574 };
2882 1575
2883 funnel@39b0000 { /* APSS Funn 1576 funnel@39b0000 { /* APSS Funnel 0 */
2884 compatible = "arm,cor 1577 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2885 reg = <0x39b0000 0x10 1578 reg = <0x39b0000 0x1000>;
2886 1579
2887 clocks = <&rpmcc RPM_ 1580 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2888 clock-names = "apb_pc 1581 clock-names = "apb_pclk", "atclk";
2889 1582
2890 in-ports { 1583 in-ports {
2891 #address-cell 1584 #address-cells = <1>;
2892 #size-cells = 1585 #size-cells = <0>;
2893 1586
2894 port@0 { 1587 port@0 {
2895 reg = 1588 reg = <0>;
2896 apss_ 1589 apss_funnel0_in0: endpoint {
2897 1590 remote-endpoint = <&etm0_out>;
2898 }; 1591 };
2899 }; 1592 };
2900 1593
2901 port@1 { 1594 port@1 {
2902 reg = 1595 reg = <1>;
2903 apss_ 1596 apss_funnel0_in1: endpoint {
2904 1597 remote-endpoint = <&etm1_out>;
2905 }; 1598 };
2906 }; 1599 };
2907 }; 1600 };
2908 1601
2909 out-ports { 1602 out-ports {
2910 port { 1603 port {
2911 apss_ 1604 apss_funnel0_out: endpoint {
2912 1605 remote-endpoint =
2913 1606 <&apss_merge_funnel_in0>;
2914 }; 1607 };
2915 }; 1608 };
2916 }; 1609 };
2917 }; 1610 };
2918 1611
2919 debug@3a10000 { 1612 debug@3a10000 {
2920 compatible = "arm,cor 1613 compatible = "arm,coresight-cpu-debug", "arm,primecell";
2921 reg = <0x3a10000 0x10 1614 reg = <0x3a10000 0x1000>;
2922 1615
2923 clocks = <&rpmcc RPM_ 1616 clocks = <&rpmcc RPM_QDSS_CLK>;
2924 clock-names = "apb_pc 1617 clock-names = "apb_pclk";
2925 1618
2926 cpu = <&CPU2>; 1619 cpu = <&CPU2>;
2927 }; 1620 };
2928 1621
2929 etm@3a40000 { 1622 etm@3a40000 {
2930 compatible = "arm,cor 1623 compatible = "arm,coresight-etm4x", "arm,primecell";
2931 reg = <0x3a40000 0x10 1624 reg = <0x3a40000 0x1000>;
2932 1625
2933 clocks = <&rpmcc RPM_ 1626 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2934 clock-names = "apb_pc 1627 clock-names = "apb_pclk", "atclk";
2935 1628
2936 cpu = <&CPU2>; 1629 cpu = <&CPU2>;
2937 1630
2938 out-ports { 1631 out-ports {
2939 port { 1632 port {
2940 etm2_ 1633 etm2_out: endpoint {
2941 1634 remote-endpoint =
2942 1635 <&apss_funnel1_in0>;
2943 }; 1636 };
2944 }; 1637 };
2945 }; 1638 };
2946 }; 1639 };
2947 1640
2948 debug@3b10000 { 1641 debug@3b10000 {
2949 compatible = "arm,cor 1642 compatible = "arm,coresight-cpu-debug", "arm,primecell";
2950 reg = <0x3b10000 0x10 1643 reg = <0x3b10000 0x1000>;
2951 1644
2952 clocks = <&rpmcc RPM_ 1645 clocks = <&rpmcc RPM_QDSS_CLK>;
2953 clock-names = "apb_pc 1646 clock-names = "apb_pclk";
2954 1647
2955 cpu = <&CPU3>; 1648 cpu = <&CPU3>;
2956 }; 1649 };
2957 1650
2958 etm@3b40000 { 1651 etm@3b40000 {
2959 compatible = "arm,cor 1652 compatible = "arm,coresight-etm4x", "arm,primecell";
2960 reg = <0x3b40000 0x10 1653 reg = <0x3b40000 0x1000>;
2961 1654
2962 clocks = <&rpmcc RPM_ 1655 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2963 clock-names = "apb_pc 1656 clock-names = "apb_pclk", "atclk";
2964 1657
2965 cpu = <&CPU3>; 1658 cpu = <&CPU3>;
2966 1659
2967 out-ports { 1660 out-ports {
2968 port { 1661 port {
2969 etm3_ 1662 etm3_out: endpoint {
2970 1663 remote-endpoint =
2971 1664 <&apss_funnel1_in1>;
2972 }; 1665 };
2973 }; 1666 };
2974 }; 1667 };
2975 }; 1668 };
2976 1669
2977 funnel@3bb0000 { /* APSS Funn 1670 funnel@3bb0000 { /* APSS Funnel 1 */
2978 compatible = "arm,cor 1671 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2979 reg = <0x3bb0000 0x10 1672 reg = <0x3bb0000 0x1000>;
2980 1673
2981 clocks = <&rpmcc RPM_ 1674 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2982 clock-names = "apb_pc 1675 clock-names = "apb_pclk", "atclk";
2983 1676
2984 in-ports { 1677 in-ports {
2985 #address-cell 1678 #address-cells = <1>;
2986 #size-cells = 1679 #size-cells = <0>;
2987 1680
2988 port@0 { 1681 port@0 {
2989 reg = 1682 reg = <0>;
2990 apss_ 1683 apss_funnel1_in0: endpoint {
2991 1684 remote-endpoint = <&etm2_out>;
2992 }; 1685 };
2993 }; 1686 };
2994 1687
2995 port@1 { 1688 port@1 {
2996 reg = 1689 reg = <1>;
2997 apss_ 1690 apss_funnel1_in1: endpoint {
2998 1691 remote-endpoint = <&etm3_out>;
2999 }; 1692 };
3000 }; 1693 };
3001 }; 1694 };
3002 1695
3003 out-ports { 1696 out-ports {
3004 port { 1697 port {
3005 apss_ 1698 apss_funnel1_out: endpoint {
3006 1699 remote-endpoint =
3007 1700 <&apss_merge_funnel_in1>;
3008 }; 1701 };
3009 }; 1702 };
3010 }; 1703 };
3011 }; 1704 };
3012 1705
3013 funnel@3bc0000 { 1706 funnel@3bc0000 {
3014 compatible = "arm,cor 1707 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3015 reg = <0x3bc0000 0x10 1708 reg = <0x3bc0000 0x1000>;
3016 1709
3017 clocks = <&rpmcc RPM_ 1710 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
3018 clock-names = "apb_pc 1711 clock-names = "apb_pclk", "atclk";
3019 1712
3020 in-ports { 1713 in-ports {
3021 #address-cell 1714 #address-cells = <1>;
3022 #size-cells = 1715 #size-cells = <0>;
3023 1716
3024 port@0 { 1717 port@0 {
3025 reg = 1718 reg = <0>;
3026 apss_ 1719 apss_merge_funnel_in0: endpoint {
3027 1720 remote-endpoint =
3028 1721 <&apss_funnel0_out>;
3029 }; 1722 };
3030 }; 1723 };
3031 1724
3032 port@1 { 1725 port@1 {
3033 reg = 1726 reg = <1>;
3034 apss_ 1727 apss_merge_funnel_in1: endpoint {
3035 1728 remote-endpoint =
3036 1729 <&apss_funnel1_out>;
3037 }; 1730 };
3038 }; 1731 };
3039 }; 1732 };
3040 1733
3041 out-ports { 1734 out-ports {
3042 port { 1735 port {
3043 apss_ 1736 apss_merge_funnel_out: endpoint {
3044 1737 remote-endpoint =
3045 1738 <&funnel1_in>;
3046 }; 1739 };
3047 }; 1740 };
3048 }; 1741 };
3049 }; 1742 };
3050 <<
3051 kryocc: clock-controller@6400 1743 kryocc: clock-controller@6400000 {
3052 compatible = "qcom,ms !! 1744 compatible = "qcom,apcc-msm8996";
3053 reg = <0x06400000 0x9 1745 reg = <0x06400000 0x90000>;
3054 <<
3055 clock-names = "xo", " <<
3056 clocks = <&rpmcc RPM_ <<
3057 <<
3058 #clock-cells = <1>; 1746 #clock-cells = <1>;
3059 }; 1747 };
3060 1748
3061 usb3: usb@6af8800 { 1749 usb3: usb@6af8800 {
3062 compatible = "qcom,ms 1750 compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
3063 reg = <0x06af8800 0x4 1751 reg = <0x06af8800 0x400>;
3064 #address-cells = <1>; 1752 #address-cells = <1>;
3065 #size-cells = <1>; 1753 #size-cells = <1>;
3066 ranges; 1754 ranges;
3067 1755
3068 interrupts = <GIC_SPI <<
3069 <GIC_SPI <<
3070 interrupt-names = "hs <<
3071 <<
3072 clocks = <&gcc GCC_SY 1756 clocks = <&gcc GCC_SYS_NOC_USB3_AXI_CLK>,
3073 <&gcc GCC_US !! 1757 <&gcc GCC_USB30_MASTER_CLK>,
3074 <&gcc GCC_AG !! 1758 <&gcc GCC_AGGRE2_USB3_AXI_CLK>,
3075 <&gcc GCC_US !! 1759 <&gcc GCC_USB30_MOCK_UTMI_CLK>,
3076 <&gcc GCC_US !! 1760 <&gcc GCC_USB30_SLEEP_CLK>,
3077 clock-names = "cfg_no !! 1761 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
3078 "core", <<
3079 "iface" <<
3080 "sleep" <<
3081 "mock_u <<
3082 1762
3083 assigned-clocks = <&g 1763 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
3084 <&g 1764 <&gcc GCC_USB30_MASTER_CLK>;
3085 assigned-clock-rates 1765 assigned-clock-rates = <19200000>, <120000000>;
3086 1766
3087 interconnects = <&a2n <<
3088 <&bim <<
3089 interconnect-names = <<
3090 <<
3091 power-domains = <&gcc 1767 power-domains = <&gcc USB30_GDSC>;
3092 status = "disabled"; 1768 status = "disabled";
3093 1769
3094 usb3_dwc3: usb@6a0000 !! 1770 dwc3@6a00000 {
3095 compatible = 1771 compatible = "snps,dwc3";
3096 reg = <0x06a0 1772 reg = <0x06a00000 0xcc00>;
3097 interrupts = !! 1773 interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>;
3098 phys = <&hsus !! 1774 phys = <&hsusb_phy1>, <&ssusb_phy_0>;
3099 phy-names = " 1775 phy-names = "usb2-phy", "usb3-phy";
3100 snps,hird-thr <<
3101 snps,dis_u2_s 1776 snps,dis_u2_susphy_quirk;
3102 snps,dis_enbl 1777 snps,dis_enblslpm_quirk;
3103 snps,is-utmi- <<
3104 snps,parkmode <<
3105 tx-fifo-resiz <<
3106 }; 1778 };
3107 }; 1779 };
3108 1780
3109 usb3phy: phy@7410000 { 1781 usb3phy: phy@7410000 {
3110 compatible = "qcom,ms 1782 compatible = "qcom,msm8996-qmp-usb3-phy";
3111 reg = <0x07410000 0x1 !! 1783 reg = <0x07410000 0x1c4>;
>> 1784 #clock-cells = <1>;
>> 1785 #address-cells = <1>;
>> 1786 #size-cells = <1>;
>> 1787 ranges;
3112 1788
3113 clocks = <&gcc GCC_US 1789 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
3114 <&gcc GCC_US !! 1790 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
3115 <&gcc GCC_US !! 1791 <&gcc GCC_USB3_CLKREF_CLK>;
3116 <&gcc GCC_US !! 1792 clock-names = "aux", "cfg_ahb", "ref";
3117 clock-names = "aux", <<
3118 "ref", <<
3119 "cfg_ah <<
3120 "pipe"; <<
3121 clock-output-names = <<
3122 #clock-cells = <0>; <<
3123 #phy-cells = <0>; <<
3124 1793
3125 resets = <&gcc GCC_US 1794 resets = <&gcc GCC_USB3_PHY_BCR>,
3126 <&gcc GCC_US !! 1795 <&gcc GCC_USB3PHY_PHY_BCR>;
3127 reset-names = "phy", !! 1796 reset-names = "phy", "common";
3128 "phy_ph <<
3129 <<
3130 status = "disabled"; 1797 status = "disabled";
>> 1798
>> 1799 ssusb_phy_0: lane@7410200 {
>> 1800 reg = <0x07410200 0x200>,
>> 1801 <0x07410400 0x130>,
>> 1802 <0x07410600 0x1a8>;
>> 1803 #phy-cells = <0>;
>> 1804
>> 1805 clock-output-names = "usb3_phy_pipe_clk_src";
>> 1806 clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
>> 1807 clock-names = "pipe0";
>> 1808 };
3131 }; 1809 };
3132 1810
3133 hsusb_phy1: phy@7411000 { 1811 hsusb_phy1: phy@7411000 {
3134 compatible = "qcom,ms 1812 compatible = "qcom,msm8996-qusb2-phy";
3135 reg = <0x07411000 0x1 1813 reg = <0x07411000 0x180>;
3136 #phy-cells = <0>; 1814 #phy-cells = <0>;
3137 1815
3138 clocks = <&gcc GCC_US 1816 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
3139 <&gcc GCC_RX1 1817 <&gcc GCC_RX1_USB2_CLKREF_CLK>;
3140 clock-names = "cfg_ah 1818 clock-names = "cfg_ahb", "ref";
3141 1819
3142 resets = <&gcc GCC_QU 1820 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
3143 nvmem-cells = <&qusb2 1821 nvmem-cells = <&qusb2p_hstx_trim>;
3144 status = "disabled"; 1822 status = "disabled";
3145 }; 1823 };
3146 1824
3147 hsusb_phy2: phy@7412000 { 1825 hsusb_phy2: phy@7412000 {
3148 compatible = "qcom,ms 1826 compatible = "qcom,msm8996-qusb2-phy";
3149 reg = <0x07412000 0x1 1827 reg = <0x07412000 0x180>;
3150 #phy-cells = <0>; 1828 #phy-cells = <0>;
3151 1829
3152 clocks = <&gcc GCC_US 1830 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
3153 <&gcc GCC_RX2 1831 <&gcc GCC_RX2_USB2_CLKREF_CLK>;
3154 clock-names = "cfg_ah 1832 clock-names = "cfg_ahb", "ref";
3155 1833
3156 resets = <&gcc GCC_QU 1834 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
3157 nvmem-cells = <&qusb2 1835 nvmem-cells = <&qusb2s_hstx_trim>;
3158 status = "disabled"; 1836 status = "disabled";
3159 }; 1837 };
3160 1838
3161 sdhc1: mmc@7464900 { !! 1839 sdhc2: sdhci@74a4900 {
3162 compatible = "qcom,ms !! 1840 status = "disabled";
3163 reg = <0x07464900 0x1 !! 1841 compatible = "qcom,sdhci-msm-v4";
3164 reg-names = "hc", "co !! 1842 reg = <0x074a4900 0x314>, <0x074a4000 0x800>;
3165 !! 1843 reg-names = "hc_mem", "core_mem";
3166 interrupts = <GIC_SPI !! 1844
3167 <GIC_ !! 1845 interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>,
3168 interrupt-names = "hc !! 1846 <0 221 IRQ_TYPE_LEVEL_HIGH>;
3169 !! 1847 interrupt-names = "hc_irq", "pwr_irq";
3170 clock-names = "iface" !! 1848
3171 clocks = <&gcc GCC_SD !! 1849 clock-names = "iface", "core", "xo";
3172 <&gcc GCC_SDC !! 1850 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
3173 <&rpmcc RPM_S !! 1851 <&gcc GCC_SDCC2_APPS_CLK>,
3174 resets = <&gcc GCC_SD !! 1852 <&xo_board>;
3175 !! 1853 bus-width = <4>;
3176 pinctrl-names = "defa <<
3177 pinctrl-0 = <&sdc1_st <<
3178 pinctrl-1 = <&sdc1_st <<
3179 <<
3180 bus-width = <8>; <<
3181 non-removable; <<
3182 status = "disabled"; <<
3183 }; <<
3184 <<
3185 sdhc2: mmc@74a4900 { <<
3186 compatible = "qcom,ms <<
3187 reg = <0x074a4900 0x3 <<
3188 reg-names = "hc", "co <<
3189 <<
3190 interrupts = <GIC_SPI <<
3191 <GIC_SP <<
3192 interrupt-names = "hc <<
3193 <<
3194 clock-names = "iface" <<
3195 clocks = <&gcc GCC_SD <<
3196 <&gcc GCC_SDC <<
3197 <&rpmcc RPM_S <<
3198 resets = <&gcc GCC_SD <<
3199 <<
3200 pinctrl-names = "defa <<
3201 pinctrl-0 = <&sdc2_st <<
3202 pinctrl-1 = <&sdc2_st <<
3203 <<
3204 bus-width = <4>; <<
3205 status = "disabled"; <<
3206 }; 1854 };
3207 1855
3208 blsp1_dma: dma-controller@754 !! 1856 blsp1_uart1: serial@7570000 {
3209 compatible = "qcom,ba <<
3210 reg = <0x07544000 0x2 <<
3211 interrupts = <GIC_SPI <<
3212 clocks = <&gcc GCC_BL <<
3213 clock-names = "bam_cl <<
3214 qcom,controlled-remot <<
3215 #dma-cells = <1>; <<
3216 qcom,ee = <0>; <<
3217 }; <<
3218 <<
3219 blsp1_uart2: serial@7570000 { <<
3220 compatible = "qcom,ms 1857 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
3221 reg = <0x07570000 0x1 1858 reg = <0x07570000 0x1000>;
3222 interrupts = <GIC_SPI 1859 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
3223 clocks = <&gcc GCC_BL 1860 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
3224 <&gcc GCC_BL 1861 <&gcc GCC_BLSP1_AHB_CLK>;
3225 clock-names = "core", 1862 clock-names = "core", "iface";
3226 pinctrl-names = "defa <<
3227 pinctrl-0 = <&blsp1_u <<
3228 pinctrl-1 = <&blsp1_u <<
3229 dmas = <&blsp1_dma 2> <<
3230 dma-names = "tx", "rx <<
3231 status = "disabled"; 1863 status = "disabled";
3232 }; 1864 };
3233 1865
3234 blsp1_spi1: spi@7575000 { !! 1866 blsp1_spi0: spi@7575000 {
3235 compatible = "qcom,sp 1867 compatible = "qcom,spi-qup-v2.2.1";
3236 reg = <0x07575000 0x6 1868 reg = <0x07575000 0x600>;
3237 interrupts = <GIC_SPI 1869 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
3238 clocks = <&gcc GCC_BL 1870 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
3239 <&gcc GCC_BL 1871 <&gcc GCC_BLSP1_AHB_CLK>;
3240 clock-names = "core", 1872 clock-names = "core", "iface";
3241 pinctrl-names = "defa 1873 pinctrl-names = "default", "sleep";
3242 pinctrl-0 = <&blsp1_s !! 1874 pinctrl-0 = <&blsp1_spi0_default>;
3243 pinctrl-1 = <&blsp1_s !! 1875 pinctrl-1 = <&blsp1_spi0_sleep>;
3244 dmas = <&blsp1_dma 12 <<
3245 dma-names = "tx", "rx <<
3246 #address-cells = <1>; 1876 #address-cells = <1>;
3247 #size-cells = <0>; 1877 #size-cells = <0>;
3248 status = "disabled"; 1878 status = "disabled";
3249 }; 1879 };
3250 1880
3251 blsp1_i2c3: i2c@7577000 { !! 1881 blsp1_i2c2: i2c@7577000 {
3252 compatible = "qcom,i2 1882 compatible = "qcom,i2c-qup-v2.2.1";
3253 reg = <0x07577000 0x1 1883 reg = <0x07577000 0x1000>;
3254 interrupts = <GIC_SPI 1884 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
3255 clocks = <&gcc GCC_BL !! 1885 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
3256 <&gcc GCC_BL !! 1886 <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
3257 clock-names = "core", !! 1887 clock-names = "iface", "core";
3258 pinctrl-names = "defa <<
3259 pinctrl-0 = <&blsp1_i <<
3260 pinctrl-1 = <&blsp1_i <<
3261 dmas = <&blsp1_dma 16 <<
3262 dma-names = "tx", "rx <<
3263 #address-cells = <1>; <<
3264 #size-cells = <0>; <<
3265 status = "disabled"; <<
3266 }; <<
3267 <<
3268 blsp1_i2c6: i2c@757a000 { <<
3269 compatible = "qcom,i2 <<
3270 reg = <0x757a000 0x10 <<
3271 interrupts = <GIC_SPI <<
3272 clocks = <&gcc GCC_BL <<
3273 <&gcc GCC_BL <<
3274 clock-names = "core", <<
3275 pinctrl-names = "defa 1888 pinctrl-names = "default", "sleep";
3276 pinctrl-0 = <&blsp1_i !! 1889 pinctrl-0 = <&blsp1_i2c2_default>;
3277 pinctrl-1 = <&blsp1_i !! 1890 pinctrl-1 = <&blsp1_i2c2_sleep>;
3278 dmas = <&blsp1_dma 22 <<
3279 dma-names = "tx", "rx <<
3280 #address-cells = <1>; 1891 #address-cells = <1>;
3281 #size-cells = <0>; 1892 #size-cells = <0>;
3282 status = "disabled"; 1893 status = "disabled";
3283 }; 1894 };
3284 1895
3285 blsp2_dma: dma-controller@758 !! 1896 blsp2_uart1: serial@75b0000 {
3286 compatible = "qcom,ba <<
3287 reg = <0x07584000 0x2 <<
3288 interrupts = <GIC_SPI <<
3289 clocks = <&gcc GCC_BL <<
3290 clock-names = "bam_cl <<
3291 qcom,controlled-remot <<
3292 #dma-cells = <1>; <<
3293 qcom,ee = <0>; <<
3294 }; <<
3295 <<
3296 blsp2_uart2: serial@75b0000 { <<
3297 compatible = "qcom,ms 1897 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
3298 reg = <0x075b0000 0x1 1898 reg = <0x075b0000 0x1000>;
3299 interrupts = <GIC_SPI 1899 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
3300 clocks = <&gcc GCC_BL 1900 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
3301 <&gcc GCC_BL 1901 <&gcc GCC_BLSP2_AHB_CLK>;
3302 clock-names = "core", 1902 clock-names = "core", "iface";
3303 status = "disabled"; 1903 status = "disabled";
3304 }; 1904 };
3305 1905
3306 blsp2_uart3: serial@75b1000 { !! 1906 blsp2_uart2: serial@75b1000 {
3307 compatible = "qcom,ms 1907 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
3308 reg = <0x075b1000 0x1 1908 reg = <0x075b1000 0x1000>;
3309 interrupts = <GIC_SPI 1909 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
3310 clocks = <&gcc GCC_BL 1910 clocks = <&gcc GCC_BLSP2_UART3_APPS_CLK>,
3311 <&gcc GCC_BL 1911 <&gcc GCC_BLSP2_AHB_CLK>;
3312 clock-names = "core", 1912 clock-names = "core", "iface";
3313 status = "disabled"; 1913 status = "disabled";
3314 }; 1914 };
3315 1915
3316 blsp2_i2c1: i2c@75b5000 { !! 1916 blsp2_i2c0: i2c@75b5000 {
3317 compatible = "qcom,i2 1917 compatible = "qcom,i2c-qup-v2.2.1";
3318 reg = <0x075b5000 0x1 1918 reg = <0x075b5000 0x1000>;
3319 interrupts = <GIC_SPI 1919 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
3320 clocks = <&gcc GCC_BL !! 1920 clocks = <&gcc GCC_BLSP2_AHB_CLK>,
3321 <&gcc GCC_BL !! 1921 <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>;
3322 clock-names = "core", !! 1922 clock-names = "iface", "core";
3323 pinctrl-names = "defa 1923 pinctrl-names = "default", "sleep";
3324 pinctrl-0 = <&blsp2_i !! 1924 pinctrl-0 = <&blsp2_i2c0_default>;
3325 pinctrl-1 = <&blsp2_i !! 1925 pinctrl-1 = <&blsp2_i2c0_sleep>;
3326 dmas = <&blsp2_dma 12 <<
3327 dma-names = "tx", "rx <<
3328 #address-cells = <1>; 1926 #address-cells = <1>;
3329 #size-cells = <0>; 1927 #size-cells = <0>;
3330 status = "disabled"; 1928 status = "disabled";
3331 }; 1929 };
3332 1930
3333 blsp2_i2c2: i2c@75b6000 { !! 1931 blsp2_i2c1: i2c@75b6000 {
3334 compatible = "qcom,i2 1932 compatible = "qcom,i2c-qup-v2.2.1";
3335 reg = <0x075b6000 0x1 1933 reg = <0x075b6000 0x1000>;
3336 interrupts = <GIC_SPI 1934 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
3337 clocks = <&gcc GCC_BL !! 1935 clocks = <&gcc GCC_BLSP2_AHB_CLK>,
3338 <&gcc GCC_BL !! 1936 <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>;
3339 clock-names = "core", !! 1937 clock-names = "iface", "core";
3340 pinctrl-names = "defa <<
3341 pinctrl-0 = <&blsp2_i <<
3342 pinctrl-1 = <&blsp2_i <<
3343 dmas = <&blsp2_dma 14 <<
3344 dma-names = "tx", "rx <<
3345 #address-cells = <1>; <<
3346 #size-cells = <0>; <<
3347 status = "disabled"; <<
3348 }; <<
3349 <<
3350 blsp2_i2c3: i2c@75b7000 { <<
3351 compatible = "qcom,i2 <<
3352 reg = <0x075b7000 0x1 <<
3353 interrupts = <GIC_SPI <<
3354 clocks = <&gcc GCC_BL <<
3355 <&gcc GCC_BL <<
3356 clock-names = "core", <<
3357 clock-frequency = <40 <<
3358 pinctrl-names = "defa <<
3359 pinctrl-0 = <&blsp2_i <<
3360 pinctrl-1 = <&blsp2_i <<
3361 dmas = <&blsp2_dma 16 <<
3362 dma-names = "tx", "rx <<
3363 #address-cells = <1>; <<
3364 #size-cells = <0>; <<
3365 status = "disabled"; <<
3366 }; <<
3367 <<
3368 blsp2_i2c5: i2c@75b9000 { <<
3369 compatible = "qcom,i2 <<
3370 reg = <0x75b9000 0x10 <<
3371 interrupts = <GIC_SPI <<
3372 clocks = <&gcc GCC_BL <<
3373 <&gcc GCC_BL <<
3374 clock-names = "core", <<
3375 pinctrl-names = "defa <<
3376 pinctrl-0 = <&blsp2_i <<
3377 dmas = <&blsp2_dma 20 <<
3378 dma-names = "tx", "rx <<
3379 #address-cells = <1>; <<
3380 #size-cells = <0>; <<
3381 status = "disabled"; <<
3382 }; <<
3383 <<
3384 blsp2_i2c6: i2c@75ba000 { <<
3385 compatible = "qcom,i2 <<
3386 reg = <0x75ba000 0x10 <<
3387 interrupts = <GIC_SPI <<
3388 clocks = <&gcc GCC_BL <<
3389 <&gcc GCC_BL <<
3390 clock-names = "core", <<
3391 pinctrl-names = "defa 1938 pinctrl-names = "default", "sleep";
3392 pinctrl-0 = <&blsp2_i !! 1939 pinctrl-0 = <&blsp2_i2c1_default>;
3393 pinctrl-1 = <&blsp2_i !! 1940 pinctrl-1 = <&blsp2_i2c1_sleep>;
3394 dmas = <&blsp2_dma 22 <<
3395 dma-names = "tx", "rx <<
3396 #address-cells = <1>; 1941 #address-cells = <1>;
3397 #size-cells = <0>; 1942 #size-cells = <0>;
3398 status = "disabled"; 1943 status = "disabled";
3399 }; 1944 };
3400 1945
3401 blsp2_spi6: spi@75ba000 { !! 1946 blsp2_spi5: spi@75ba000{
3402 compatible = "qcom,sp 1947 compatible = "qcom,spi-qup-v2.2.1";
3403 reg = <0x075ba000 0x6 1948 reg = <0x075ba000 0x600>;
3404 interrupts = <GIC_SPI 1949 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
3405 clocks = <&gcc GCC_BL 1950 clocks = <&gcc GCC_BLSP2_QUP6_SPI_APPS_CLK>,
3406 <&gcc GCC_BL 1951 <&gcc GCC_BLSP2_AHB_CLK>;
3407 clock-names = "core", 1952 clock-names = "core", "iface";
3408 pinctrl-names = "defa 1953 pinctrl-names = "default", "sleep";
3409 pinctrl-0 = <&blsp2_s !! 1954 pinctrl-0 = <&blsp2_spi5_default>;
3410 pinctrl-1 = <&blsp2_s !! 1955 pinctrl-1 = <&blsp2_spi5_sleep>;
3411 dmas = <&blsp2_dma 22 <<
3412 dma-names = "tx", "rx <<
3413 #address-cells = <1>; 1956 #address-cells = <1>;
3414 #size-cells = <0>; 1957 #size-cells = <0>;
3415 status = "disabled"; 1958 status = "disabled";
3416 }; 1959 };
3417 1960
3418 usb2: usb@76f8800 { 1961 usb2: usb@76f8800 {
3419 compatible = "qcom,ms 1962 compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
3420 reg = <0x076f8800 0x4 1963 reg = <0x076f8800 0x400>;
3421 #address-cells = <1>; 1964 #address-cells = <1>;
3422 #size-cells = <1>; 1965 #size-cells = <1>;
3423 ranges; 1966 ranges;
3424 1967
3425 interrupts = <GIC_SPI <<
3426 <GIC_SPI <<
3427 <GIC_SPI <<
3428 interrupt-names = "pw <<
3429 "qu <<
3430 "hs <<
3431 <<
3432 clocks = <&gcc GCC_PE 1968 clocks = <&gcc GCC_PERIPH_NOC_USB20_AHB_CLK>,
3433 <&gcc GCC_USB 1969 <&gcc GCC_USB20_MASTER_CLK>,
3434 <&gcc GCC_USB 1970 <&gcc GCC_USB20_MOCK_UTMI_CLK>,
3435 <&gcc GCC_USB 1971 <&gcc GCC_USB20_SLEEP_CLK>,
3436 <&gcc GCC_USB 1972 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
3437 clock-names = "cfg_no <<
3438 "core", <<
3439 "iface" <<
3440 "sleep" <<
3441 "mock_u <<
3442 1973
3443 assigned-clocks = <&g 1974 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
3444 <&g 1975 <&gcc GCC_USB20_MASTER_CLK>;
3445 assigned-clock-rates 1976 assigned-clock-rates = <19200000>, <60000000>;
3446 1977
3447 power-domains = <&gcc 1978 power-domains = <&gcc USB30_GDSC>;
3448 qcom,select-utmi-as-p <<
3449 status = "disabled"; 1979 status = "disabled";
3450 1980
3451 usb2_dwc3: usb@760000 !! 1981 dwc3@7600000 {
3452 compatible = 1982 compatible = "snps,dwc3";
3453 reg = <0x0760 1983 reg = <0x07600000 0xcc00>;
3454 interrupts = !! 1984 interrupts = <0 138 IRQ_TYPE_LEVEL_HIGH>;
3455 phys = <&hsus 1985 phys = <&hsusb_phy2>;
3456 phy-names = " 1986 phy-names = "usb2-phy";
3457 maximum-speed <<
3458 snps,dis_u2_s 1987 snps,dis_u2_susphy_quirk;
3459 snps,dis_enbl 1988 snps,dis_enblslpm_quirk;
3460 }; 1989 };
3461 }; 1990 };
3462 1991
3463 slimbam: dma-controller@91840 !! 1992 slimbam: dma@9184000 {
3464 compatible = "qcom,ba 1993 compatible = "qcom,bam-v1.7.0";
3465 qcom,controlled-remot 1994 qcom,controlled-remotely;
3466 reg = <0x09184000 0x3 1995 reg = <0x09184000 0x32000>;
3467 num-channels = <31>; !! 1996 num-channels = <31>;
3468 interrupts = <GIC_SPI !! 1997 interrupts = <0 164 IRQ_TYPE_LEVEL_HIGH>;
3469 #dma-cells = <1>; 1998 #dma-cells = <1>;
3470 qcom,ee = <1>; 1999 qcom,ee = <1>;
3471 qcom,num-ees = <2>; 2000 qcom,num-ees = <2>;
3472 }; 2001 };
3473 2002
3474 slim_msm: slim-ngd@91c0000 { !! 2003 slim_msm: slim@91c0000 {
3475 compatible = "qcom,sl 2004 compatible = "qcom,slim-ngd-v1.5.0";
3476 reg = <0x091c0000 0x2 !! 2005 reg = <0x091c0000 0x2C000>;
3477 interrupts = <GIC_SPI !! 2006 reg-names = "ctrl";
3478 dmas = <&slimbam 3>, !! 2007 interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>;
3479 dma-names = "rx", "tx !! 2008 dmas = <&slimbam 3>, <&slimbam 4>,
>> 2009 <&slimbam 5>, <&slimbam 6>;
>> 2010 dma-names = "rx", "tx", "tx2", "rx2";
3480 #address-cells = <1>; 2011 #address-cells = <1>;
3481 #size-cells = <0>; 2012 #size-cells = <0>;
>> 2013 ngd@1 {
>> 2014 reg = <1>;
>> 2015 #address-cells = <1>;
>> 2016 #size-cells = <1>;
3482 2017
3483 status = "disabled"; !! 2018 tasha_ifd: tas-ifd {
>> 2019 compatible = "slim217,1a0";
>> 2020 reg = <0 0>;
>> 2021 };
>> 2022
>> 2023 wcd9335: codec@1{
>> 2024 pinctrl-0 = <&cdc_reset_active &wcd_intr_default>;
>> 2025 pinctrl-names = "default";
>> 2026
>> 2027 compatible = "slim217,1a0";
>> 2028 reg = <1 0>;
>> 2029
>> 2030 interrupt-parent = <&msmgpio>;
>> 2031 interrupts = <54 IRQ_TYPE_LEVEL_HIGH>,
>> 2032 <53 IRQ_TYPE_LEVEL_HIGH>;
>> 2033 interrupt-names = "intr1", "intr2";
>> 2034 interrupt-controller;
>> 2035 #interrupt-cells = <1>;
>> 2036 reset-gpios = <&msmgpio 64 0>;
>> 2037
>> 2038 slim-ifc-dev = <&tasha_ifd>;
>> 2039
>> 2040 #sound-dai-cells = <1>;
>> 2041 };
>> 2042 };
3484 }; 2043 };
3485 2044
3486 adsp_pil: remoteproc@9300000 2045 adsp_pil: remoteproc@9300000 {
3487 compatible = "qcom,ms 2046 compatible = "qcom,msm8996-adsp-pil";
3488 reg = <0x09300000 0x8 2047 reg = <0x09300000 0x80000>;
3489 2048
3490 interrupts-extended = 2049 interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>,
3491 !! 2050 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
3492 !! 2051 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
3493 !! 2052 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
3494 !! 2053 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
3495 interrupt-names = "wd 2054 interrupt-names = "wdog", "fatal", "ready",
3496 "ha 2055 "handover", "stop-ack";
3497 2056
3498 clocks = <&rpmcc RPM_ !! 2057 clocks = <&xo_board>;
3499 clock-names = "xo"; 2058 clock-names = "xo";
3500 2059
3501 memory-region = <&ads !! 2060 memory-region = <&adsp_region>;
3502 2061
3503 qcom,smem-states = <& !! 2062 qcom,smem-states = <&smp2p_adsp_out 0>;
3504 qcom,smem-state-names 2063 qcom,smem-state-names = "stop";
3505 2064
3506 power-domains = <&rpm <<
3507 power-domain-names = <<
3508 <<
3509 status = "disabled"; <<
3510 <<
3511 glink-edge { <<
3512 interrupts = <<
3513 label = "lpas <<
3514 qcom,remote-p <<
3515 mboxes = <&ap <<
3516 }; <<
3517 <<
3518 <<
3519 smd-edge { 2065 smd-edge {
3520 interrupts = 2066 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
3521 2067
3522 label = "lpas 2068 label = "lpass";
3523 mboxes = <&ap 2069 mboxes = <&apcs_glb 8>;
3524 qcom,smd-edge 2070 qcom,smd-edge = <1>;
3525 qcom,remote-p 2071 qcom,remote-pid = <2>;
3526 !! 2072 #address-cells = <1>;
>> 2073 #size-cells = <0>;
3527 apr { 2074 apr {
3528 power 2075 power-domains = <&gcc HLOS1_VOTE_LPASS_ADSP_GDSC>;
3529 compa 2076 compatible = "qcom,apr-v2";
3530 qcom, 2077 qcom,smd-channels = "apr_audio_svc";
3531 qcom, !! 2078 qcom,apr-domain = <APR_DOMAIN_ADSP>;
3532 #addr 2079 #address-cells = <1>;
3533 #size 2080 #size-cells = <0>;
3534 2081
3535 servi !! 2082 q6core {
3536 2083 reg = <APR_SVC_ADSP_CORE>;
3537 2084 compatible = "qcom,q6core";
3538 }; 2085 };
3539 2086
3540 q6afe !! 2087 q6afe: q6afe {
3541 2088 compatible = "qcom,q6afe";
3542 2089 reg = <APR_SVC_AFE>;
3543 2090 q6afedai: dais {
3544 2091 compatible = "qcom,q6afe-dais";
3545 2092 #address-cells = <1>;
3546 2093 #size-cells = <0>;
3547 2094 #sound-dai-cells = <1>;
3548 !! 2095 hdmi@1 {
3549 2096 reg = <1>;
3550 2097 };
3551 2098 };
3552 }; 2099 };
3553 2100
3554 q6asm !! 2101 q6asm: q6asm {
3555 2102 compatible = "qcom,q6asm";
3556 2103 reg = <APR_SVC_ASM>;
3557 2104 q6asmdai: dais {
3558 2105 compatible = "qcom,q6asm-dais";
3559 2106 #address-cells = <1>;
3560 2107 #size-cells = <0>;
3561 2108 #sound-dai-cells = <1>;
3562 2109 iommus = <&lpass_q6_smmu 1>;
3563 2110 };
3564 }; 2111 };
3565 2112
3566 q6adm !! 2113 q6adm: q6adm {
3567 2114 compatible = "qcom,q6adm";
3568 2115 reg = <APR_SVC_ADM>;
3569 2116 q6routing: routing {
3570 2117 compatible = "qcom,q6adm-routing";
3571 2118 #sound-dai-cells = <0>;
3572 2119 };
3573 }; 2120 };
3574 }; 2121 };
3575 2122
3576 fastrpc { <<
3577 compa <<
3578 qcom, <<
3579 label <<
3580 qcom, <<
3581 #addr <<
3582 #size <<
3583 <<
3584 cb@5 <<
3585 <<
3586 <<
3587 <<
3588 }; <<
3589 <<
3590 cb@6 <<
3591 <<
3592 <<
3593 <<
3594 }; <<
3595 <<
3596 cb@7 <<
3597 <<
3598 <<
3599 <<
3600 }; <<
3601 <<
3602 cb@8 <<
3603 <<
3604 <<
3605 <<
3606 }; <<
3607 <<
3608 cb@9 <<
3609 <<
3610 <<
3611 <<
3612 }; <<
3613 <<
3614 cb@10 <<
3615 <<
3616 <<
3617 <<
3618 }; <<
3619 <<
3620 cb@11 <<
3621 <<
3622 <<
3623 <<
3624 }; <<
3625 <<
3626 cb@12 <<
3627 <<
3628 <<
3629 <<
3630 }; <<
3631 }; <<
3632 }; 2123 };
3633 }; 2124 };
3634 2125
3635 apcs_glb: mailbox@9820000 { 2126 apcs_glb: mailbox@9820000 {
3636 compatible = "qcom,ms 2127 compatible = "qcom,msm8996-apcs-hmss-global";
3637 reg = <0x09820000 0x1 2128 reg = <0x09820000 0x1000>;
3638 2129
3639 #mbox-cells = <1>; 2130 #mbox-cells = <1>;
3640 #clock-cells = <0>; <<
3641 }; 2131 };
3642 2132
3643 timer@9840000 { 2133 timer@9840000 {
3644 #address-cells = <1>; 2134 #address-cells = <1>;
3645 #size-cells = <1>; 2135 #size-cells = <1>;
3646 ranges; 2136 ranges;
3647 compatible = "arm,arm 2137 compatible = "arm,armv7-timer-mem";
3648 reg = <0x09840000 0x1 2138 reg = <0x09840000 0x1000>;
3649 clock-frequency = <19 2139 clock-frequency = <19200000>;
3650 2140
3651 frame@9850000 { 2141 frame@9850000 {
3652 frame-number 2142 frame-number = <0>;
3653 interrupts = 2143 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
3654 2144 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
3655 reg = <0x0985 2145 reg = <0x09850000 0x1000>,
3656 <0x0986 2146 <0x09860000 0x1000>;
3657 }; 2147 };
3658 2148
3659 frame@9870000 { 2149 frame@9870000 {
3660 frame-number 2150 frame-number = <1>;
3661 interrupts = 2151 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
3662 reg = <0x0987 2152 reg = <0x09870000 0x1000>;
3663 status = "dis 2153 status = "disabled";
3664 }; 2154 };
3665 2155
3666 frame@9880000 { 2156 frame@9880000 {
3667 frame-number 2157 frame-number = <2>;
3668 interrupts = 2158 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
3669 reg = <0x0988 2159 reg = <0x09880000 0x1000>;
3670 status = "dis 2160 status = "disabled";
3671 }; 2161 };
3672 2162
3673 frame@9890000 { 2163 frame@9890000 {
3674 frame-number 2164 frame-number = <3>;
3675 interrupts = 2165 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
3676 reg = <0x0989 2166 reg = <0x09890000 0x1000>;
3677 status = "dis 2167 status = "disabled";
3678 }; 2168 };
3679 2169
3680 frame@98a0000 { 2170 frame@98a0000 {
3681 frame-number 2171 frame-number = <4>;
3682 interrupts = 2172 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
3683 reg = <0x098a 2173 reg = <0x098a0000 0x1000>;
3684 status = "dis 2174 status = "disabled";
3685 }; 2175 };
3686 2176
3687 frame@98b0000 { 2177 frame@98b0000 {
3688 frame-number 2178 frame-number = <5>;
3689 interrupts = 2179 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
3690 reg = <0x098b 2180 reg = <0x098b0000 0x1000>;
3691 status = "dis 2181 status = "disabled";
3692 }; 2182 };
3693 2183
3694 frame@98c0000 { 2184 frame@98c0000 {
3695 frame-number 2185 frame-number = <6>;
3696 interrupts = 2186 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
3697 reg = <0x098c 2187 reg = <0x098c0000 0x1000>;
3698 status = "dis 2188 status = "disabled";
3699 }; 2189 };
3700 }; 2190 };
3701 2191
3702 saw3: syscon@9a10000 { 2192 saw3: syscon@9a10000 {
3703 compatible = "syscon" 2193 compatible = "syscon";
3704 reg = <0x09a10000 0x1 2194 reg = <0x09a10000 0x1000>;
3705 }; 2195 };
3706 2196
3707 cbf: clock-controller@9a11000 <<
3708 compatible = "qcom,ms <<
3709 reg = <0x09a11000 0x1 <<
3710 clocks = <&rpmcc RPM_ <<
3711 #clock-cells = <0>; <<
3712 #interconnect-cells = <<
3713 }; <<
3714 <<
3715 intc: interrupt-controller@9b 2197 intc: interrupt-controller@9bc0000 {
3716 compatible = "qcom,ms 2198 compatible = "qcom,msm8996-gic-v3", "arm,gic-v3";
3717 #interrupt-cells = <3 2199 #interrupt-cells = <3>;
3718 interrupt-controller; 2200 interrupt-controller;
3719 #redistributor-region 2201 #redistributor-regions = <1>;
3720 redistributor-stride 2202 redistributor-stride = <0x0 0x40000>;
3721 reg = <0x09bc0000 0x1 2203 reg = <0x09bc0000 0x10000>,
3722 <0x09c00000 0x1 2204 <0x09c00000 0x100000>;
3723 interrupts = <GIC_PPI 2205 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
3724 }; 2206 };
3725 }; 2207 };
3726 2208
3727 sound: sound { 2209 sound: sound {
3728 }; 2210 };
3729 2211
3730 thermal-zones { 2212 thermal-zones {
3731 cpu0-thermal { 2213 cpu0-thermal {
3732 polling-delay-passive 2214 polling-delay-passive = <250>;
>> 2215 polling-delay = <1000>;
3733 2216
3734 thermal-sensors = <&t 2217 thermal-sensors = <&tsens0 3>;
3735 2218
3736 trips { 2219 trips {
3737 cpu0_alert0: 2220 cpu0_alert0: trip-point0 {
3738 tempe 2221 temperature = <75000>;
3739 hyste 2222 hysteresis = <2000>;
3740 type 2223 type = "passive";
3741 }; 2224 };
3742 2225
3743 cpu0_crit: cp !! 2226 cpu0_crit: cpu_crit {
3744 tempe 2227 temperature = <110000>;
3745 hyste 2228 hysteresis = <2000>;
3746 type 2229 type = "critical";
3747 }; 2230 };
3748 }; 2231 };
3749 }; 2232 };
3750 2233
3751 cpu1-thermal { 2234 cpu1-thermal {
3752 polling-delay-passive 2235 polling-delay-passive = <250>;
>> 2236 polling-delay = <1000>;
3753 2237
3754 thermal-sensors = <&t 2238 thermal-sensors = <&tsens0 5>;
3755 2239
3756 trips { 2240 trips {
3757 cpu1_alert0: 2241 cpu1_alert0: trip-point0 {
3758 tempe 2242 temperature = <75000>;
3759 hyste 2243 hysteresis = <2000>;
3760 type 2244 type = "passive";
3761 }; 2245 };
3762 2246
3763 cpu1_crit: cp !! 2247 cpu1_crit: cpu_crit {
3764 tempe 2248 temperature = <110000>;
3765 hyste 2249 hysteresis = <2000>;
3766 type 2250 type = "critical";
3767 }; 2251 };
3768 }; 2252 };
3769 }; 2253 };
3770 2254
3771 cpu2-thermal { 2255 cpu2-thermal {
3772 polling-delay-passive 2256 polling-delay-passive = <250>;
>> 2257 polling-delay = <1000>;
3773 2258
3774 thermal-sensors = <&t 2259 thermal-sensors = <&tsens0 8>;
3775 2260
3776 trips { 2261 trips {
3777 cpu2_alert0: 2262 cpu2_alert0: trip-point0 {
3778 tempe 2263 temperature = <75000>;
3779 hyste 2264 hysteresis = <2000>;
3780 type 2265 type = "passive";
3781 }; 2266 };
3782 2267
3783 cpu2_crit: cp !! 2268 cpu2_crit: cpu_crit {
3784 tempe 2269 temperature = <110000>;
3785 hyste 2270 hysteresis = <2000>;
3786 type 2271 type = "critical";
3787 }; 2272 };
3788 }; 2273 };
3789 }; 2274 };
3790 2275
3791 cpu3-thermal { 2276 cpu3-thermal {
3792 polling-delay-passive 2277 polling-delay-passive = <250>;
>> 2278 polling-delay = <1000>;
3793 2279
3794 thermal-sensors = <&t 2280 thermal-sensors = <&tsens0 10>;
3795 2281
3796 trips { 2282 trips {
3797 cpu3_alert0: 2283 cpu3_alert0: trip-point0 {
3798 tempe 2284 temperature = <75000>;
3799 hyste 2285 hysteresis = <2000>;
3800 type 2286 type = "passive";
3801 }; 2287 };
3802 2288
3803 cpu3_crit: cp !! 2289 cpu3_crit: cpu_crit {
3804 tempe 2290 temperature = <110000>;
3805 hyste 2291 hysteresis = <2000>;
3806 type 2292 type = "critical";
3807 }; 2293 };
3808 }; 2294 };
3809 }; 2295 };
3810 2296
3811 gpu-top-thermal { !! 2297 gpu-thermal-top {
3812 polling-delay-passive 2298 polling-delay-passive = <250>;
>> 2299 polling-delay = <1000>;
3813 2300
3814 thermal-sensors = <&t 2301 thermal-sensors = <&tsens1 6>;
3815 2302
3816 trips { 2303 trips {
3817 gpu1_alert0: 2304 gpu1_alert0: trip-point0 {
3818 tempe 2305 temperature = <90000>;
3819 hyste 2306 hysteresis = <2000>;
3820 type !! 2307 type = "hot";
3821 }; <<
3822 }; <<
3823 <<
3824 cooling-maps { <<
3825 map0 { <<
3826 trip <<
3827 cooli <<
3828 }; 2308 };
3829 }; 2309 };
3830 }; 2310 };
3831 2311
3832 gpu-bottom-thermal { !! 2312 gpu-thermal-bottom {
3833 polling-delay-passive 2313 polling-delay-passive = <250>;
>> 2314 polling-delay = <1000>;
3834 2315
3835 thermal-sensors = <&t 2316 thermal-sensors = <&tsens1 7>;
3836 2317
3837 trips { 2318 trips {
3838 gpu2_alert0: 2319 gpu2_alert0: trip-point0 {
3839 tempe 2320 temperature = <90000>;
3840 hyste 2321 hysteresis = <2000>;
3841 type !! 2322 type = "hot";
3842 }; <<
3843 }; <<
3844 <<
3845 cooling-maps { <<
3846 map0 { <<
3847 trip <<
3848 cooli <<
3849 }; 2323 };
3850 }; 2324 };
3851 }; 2325 };
3852 2326
3853 m4m-thermal { 2327 m4m-thermal {
3854 polling-delay-passive 2328 polling-delay-passive = <250>;
>> 2329 polling-delay = <1000>;
3855 2330
3856 thermal-sensors = <&t 2331 thermal-sensors = <&tsens0 1>;
3857 2332
3858 trips { 2333 trips {
3859 m4m_alert0: t 2334 m4m_alert0: trip-point0 {
3860 tempe 2335 temperature = <90000>;
3861 hyste 2336 hysteresis = <2000>;
3862 type 2337 type = "hot";
3863 }; 2338 };
3864 }; 2339 };
3865 }; 2340 };
3866 2341
3867 l3-or-venus-thermal { 2342 l3-or-venus-thermal {
3868 polling-delay-passive 2343 polling-delay-passive = <250>;
>> 2344 polling-delay = <1000>;
3869 2345
3870 thermal-sensors = <&t 2346 thermal-sensors = <&tsens0 2>;
3871 2347
3872 trips { 2348 trips {
3873 l3_or_venus_a 2349 l3_or_venus_alert0: trip-point0 {
3874 tempe 2350 temperature = <90000>;
3875 hyste 2351 hysteresis = <2000>;
3876 type 2352 type = "hot";
3877 }; 2353 };
3878 }; 2354 };
3879 }; 2355 };
3880 2356
3881 cluster0-l2-thermal { 2357 cluster0-l2-thermal {
3882 polling-delay-passive 2358 polling-delay-passive = <250>;
>> 2359 polling-delay = <1000>;
3883 2360
3884 thermal-sensors = <&t 2361 thermal-sensors = <&tsens0 7>;
3885 2362
3886 trips { 2363 trips {
3887 cluster0_l2_a 2364 cluster0_l2_alert0: trip-point0 {
3888 tempe 2365 temperature = <90000>;
3889 hyste 2366 hysteresis = <2000>;
3890 type 2367 type = "hot";
3891 }; 2368 };
3892 }; 2369 };
3893 }; 2370 };
3894 2371
3895 cluster1-l2-thermal { 2372 cluster1-l2-thermal {
3896 polling-delay-passive 2373 polling-delay-passive = <250>;
>> 2374 polling-delay = <1000>;
3897 2375
3898 thermal-sensors = <&t 2376 thermal-sensors = <&tsens0 12>;
3899 2377
3900 trips { 2378 trips {
3901 cluster1_l2_a 2379 cluster1_l2_alert0: trip-point0 {
3902 tempe 2380 temperature = <90000>;
3903 hyste 2381 hysteresis = <2000>;
3904 type 2382 type = "hot";
3905 }; 2383 };
3906 }; 2384 };
3907 }; 2385 };
3908 2386
3909 camera-thermal { 2387 camera-thermal {
3910 polling-delay-passive 2388 polling-delay-passive = <250>;
>> 2389 polling-delay = <1000>;
3911 2390
3912 thermal-sensors = <&t 2391 thermal-sensors = <&tsens1 1>;
3913 2392
3914 trips { 2393 trips {
3915 camera_alert0 2394 camera_alert0: trip-point0 {
3916 tempe 2395 temperature = <90000>;
3917 hyste 2396 hysteresis = <2000>;
3918 type 2397 type = "hot";
3919 }; 2398 };
3920 }; 2399 };
3921 }; 2400 };
3922 2401
3923 q6-dsp-thermal { 2402 q6-dsp-thermal {
3924 polling-delay-passive 2403 polling-delay-passive = <250>;
>> 2404 polling-delay = <1000>;
3925 2405
3926 thermal-sensors = <&t 2406 thermal-sensors = <&tsens1 2>;
3927 2407
3928 trips { 2408 trips {
3929 q6_dsp_alert0 2409 q6_dsp_alert0: trip-point0 {
3930 tempe 2410 temperature = <90000>;
3931 hyste 2411 hysteresis = <2000>;
3932 type 2412 type = "hot";
3933 }; 2413 };
3934 }; 2414 };
3935 }; 2415 };
3936 2416
3937 mem-thermal { 2417 mem-thermal {
3938 polling-delay-passive 2418 polling-delay-passive = <250>;
>> 2419 polling-delay = <1000>;
3939 2420
3940 thermal-sensors = <&t 2421 thermal-sensors = <&tsens1 3>;
3941 2422
3942 trips { 2423 trips {
3943 mem_alert0: t 2424 mem_alert0: trip-point0 {
3944 tempe 2425 temperature = <90000>;
3945 hyste 2426 hysteresis = <2000>;
3946 type 2427 type = "hot";
3947 }; 2428 };
3948 }; 2429 };
3949 }; 2430 };
3950 2431
3951 modemtx-thermal { 2432 modemtx-thermal {
3952 polling-delay-passive 2433 polling-delay-passive = <250>;
>> 2434 polling-delay = <1000>;
3953 2435
3954 thermal-sensors = <&t 2436 thermal-sensors = <&tsens1 4>;
3955 2437
3956 trips { 2438 trips {
3957 modemtx_alert 2439 modemtx_alert0: trip-point0 {
3958 tempe 2440 temperature = <90000>;
3959 hyste 2441 hysteresis = <2000>;
3960 type 2442 type = "hot";
3961 }; 2443 };
3962 }; 2444 };
3963 }; 2445 };
3964 }; 2446 };
3965 2447
3966 timer { 2448 timer {
3967 compatible = "arm,armv8-timer 2449 compatible = "arm,armv8-timer";
3968 interrupts = <GIC_PPI 13 IRQ_ 2450 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
3969 <GIC_PPI 14 IRQ_ 2451 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
3970 <GIC_PPI 11 IRQ_ 2452 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
3971 <GIC_PPI 10 IRQ_ 2453 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
3972 }; 2454 };
3973 }; 2455 };
>> 2456 #include "msm8996-pins.dtsi"
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