1 // SPDX-License-Identifier: GPL-2.0-only 1 // SPDX-License-Identifier: GPL-2.0-only
2 /* 2 /*
3 * Copyright (c) 2014-2015, The Linux Foundati 3 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
4 */ 4 */
5 5
6 #include <dt-bindings/interrupt-controller/arm 6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,gcc-msm8996.h 7 #include <dt-bindings/clock/qcom,gcc-msm8996.h>
8 #include <dt-bindings/clock/qcom,mmcc-msm8996. 8 #include <dt-bindings/clock/qcom,mmcc-msm8996.h>
9 #include <dt-bindings/clock/qcom,rpmcc.h> 9 #include <dt-bindings/clock/qcom,rpmcc.h>
10 #include <dt-bindings/interconnect/qcom,msm899 10 #include <dt-bindings/interconnect/qcom,msm8996.h>
11 #include <dt-bindings/interconnect/qcom,msm899 <<
12 #include <dt-bindings/firmware/qcom,scm.h> <<
13 #include <dt-bindings/gpio/gpio.h> 11 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/power/qcom-rpmpd.h> 12 #include <dt-bindings/power/qcom-rpmpd.h>
15 #include <dt-bindings/soc/qcom,apr.h> 13 #include <dt-bindings/soc/qcom,apr.h>
16 #include <dt-bindings/thermal/thermal.h> 14 #include <dt-bindings/thermal/thermal.h>
17 15
18 / { 16 / {
19 interrupt-parent = <&intc>; 17 interrupt-parent = <&intc>;
20 18
21 #address-cells = <2>; 19 #address-cells = <2>;
22 #size-cells = <2>; 20 #size-cells = <2>;
23 21
24 chosen { }; 22 chosen { };
25 23
26 clocks { 24 clocks {
27 xo_board: xo-board { 25 xo_board: xo-board {
28 compatible = "fixed-cl 26 compatible = "fixed-clock";
29 #clock-cells = <0>; 27 #clock-cells = <0>;
30 clock-frequency = <192 28 clock-frequency = <19200000>;
31 clock-output-names = " 29 clock-output-names = "xo_board";
32 }; 30 };
33 31
34 sleep_clk: sleep-clk { 32 sleep_clk: sleep-clk {
35 compatible = "fixed-cl 33 compatible = "fixed-clock";
36 #clock-cells = <0>; 34 #clock-cells = <0>;
37 clock-frequency = <327 35 clock-frequency = <32764>;
38 clock-output-names = " 36 clock-output-names = "sleep_clk";
39 }; 37 };
40 }; 38 };
41 39
42 cpus { 40 cpus {
43 #address-cells = <2>; 41 #address-cells = <2>;
44 #size-cells = <0>; 42 #size-cells = <0>;
45 43
46 CPU0: cpu@0 { 44 CPU0: cpu@0 {
47 device_type = "cpu"; 45 device_type = "cpu";
48 compatible = "qcom,kry 46 compatible = "qcom,kryo";
49 reg = <0x0 0x0>; 47 reg = <0x0 0x0>;
50 enable-method = "psci" 48 enable-method = "psci";
51 cpu-idle-states = <&CP 49 cpu-idle-states = <&CPU_SLEEP_0>;
52 capacity-dmips-mhz = < 50 capacity-dmips-mhz = <1024>;
53 clocks = <&kryocc 0>; 51 clocks = <&kryocc 0>;
54 interconnects = <&cbf <<
55 operating-points-v2 = 52 operating-points-v2 = <&cluster0_opp>;
56 #cooling-cells = <2>; 53 #cooling-cells = <2>;
57 next-level-cache = <&L 54 next-level-cache = <&L2_0>;
58 L2_0: l2-cache { 55 L2_0: l2-cache {
59 compatible = " !! 56 compatible = "cache";
60 cache-level = !! 57 cache-level = <2>;
61 cache-unified; <<
62 }; 58 };
63 }; 59 };
64 60
65 CPU1: cpu@1 { 61 CPU1: cpu@1 {
66 device_type = "cpu"; 62 device_type = "cpu";
67 compatible = "qcom,kry 63 compatible = "qcom,kryo";
68 reg = <0x0 0x1>; 64 reg = <0x0 0x1>;
69 enable-method = "psci" 65 enable-method = "psci";
70 cpu-idle-states = <&CP 66 cpu-idle-states = <&CPU_SLEEP_0>;
71 capacity-dmips-mhz = < 67 capacity-dmips-mhz = <1024>;
72 clocks = <&kryocc 0>; 68 clocks = <&kryocc 0>;
73 interconnects = <&cbf <<
74 operating-points-v2 = 69 operating-points-v2 = <&cluster0_opp>;
75 #cooling-cells = <2>; 70 #cooling-cells = <2>;
76 next-level-cache = <&L 71 next-level-cache = <&L2_0>;
77 }; 72 };
78 73
79 CPU2: cpu@100 { 74 CPU2: cpu@100 {
80 device_type = "cpu"; 75 device_type = "cpu";
81 compatible = "qcom,kry 76 compatible = "qcom,kryo";
82 reg = <0x0 0x100>; 77 reg = <0x0 0x100>;
83 enable-method = "psci" 78 enable-method = "psci";
84 cpu-idle-states = <&CP 79 cpu-idle-states = <&CPU_SLEEP_0>;
85 capacity-dmips-mhz = < 80 capacity-dmips-mhz = <1024>;
86 clocks = <&kryocc 1>; 81 clocks = <&kryocc 1>;
87 interconnects = <&cbf <<
88 operating-points-v2 = 82 operating-points-v2 = <&cluster1_opp>;
89 #cooling-cells = <2>; 83 #cooling-cells = <2>;
90 next-level-cache = <&L 84 next-level-cache = <&L2_1>;
91 L2_1: l2-cache { 85 L2_1: l2-cache {
92 compatible = " !! 86 compatible = "cache";
93 cache-level = !! 87 cache-level = <2>;
94 cache-unified; <<
95 }; 88 };
96 }; 89 };
97 90
98 CPU3: cpu@101 { 91 CPU3: cpu@101 {
99 device_type = "cpu"; 92 device_type = "cpu";
100 compatible = "qcom,kry 93 compatible = "qcom,kryo";
101 reg = <0x0 0x101>; 94 reg = <0x0 0x101>;
102 enable-method = "psci" 95 enable-method = "psci";
103 cpu-idle-states = <&CP 96 cpu-idle-states = <&CPU_SLEEP_0>;
104 capacity-dmips-mhz = < 97 capacity-dmips-mhz = <1024>;
105 clocks = <&kryocc 1>; 98 clocks = <&kryocc 1>;
106 interconnects = <&cbf <<
107 operating-points-v2 = 99 operating-points-v2 = <&cluster1_opp>;
108 #cooling-cells = <2>; 100 #cooling-cells = <2>;
109 next-level-cache = <&L 101 next-level-cache = <&L2_1>;
110 }; 102 };
111 103
112 cpu-map { 104 cpu-map {
113 cluster0 { 105 cluster0 {
114 core0 { 106 core0 {
115 cpu = 107 cpu = <&CPU0>;
116 }; 108 };
117 109
118 core1 { 110 core1 {
119 cpu = 111 cpu = <&CPU1>;
120 }; 112 };
121 }; 113 };
122 114
123 cluster1 { 115 cluster1 {
124 core0 { 116 core0 {
125 cpu = 117 cpu = <&CPU2>;
126 }; 118 };
127 119
128 core1 { 120 core1 {
129 cpu = 121 cpu = <&CPU3>;
130 }; 122 };
131 }; 123 };
132 }; 124 };
133 125
134 idle-states { 126 idle-states {
135 entry-method = "psci"; 127 entry-method = "psci";
136 128
137 CPU_SLEEP_0: cpu-sleep 129 CPU_SLEEP_0: cpu-sleep-0 {
138 compatible = " 130 compatible = "arm,idle-state";
139 idle-state-nam 131 idle-state-name = "standalone-power-collapse";
140 arm,psci-suspe 132 arm,psci-suspend-param = <0x00000004>;
141 entry-latency- 133 entry-latency-us = <130>;
142 exit-latency-u 134 exit-latency-us = <80>;
143 min-residency- 135 min-residency-us = <300>;
144 }; 136 };
145 }; 137 };
146 }; 138 };
147 139
148 cluster0_opp: opp-table-cluster0 { 140 cluster0_opp: opp-table-cluster0 {
149 compatible = "operating-points 141 compatible = "operating-points-v2-kryo-cpu";
150 nvmem-cells = <&speedbin_efuse 142 nvmem-cells = <&speedbin_efuse>;
151 opp-shared; 143 opp-shared;
152 144
153 /* Nominal fmax for now */ 145 /* Nominal fmax for now */
154 opp-307200000 { 146 opp-307200000 {
155 opp-hz = /bits/ 64 <30 147 opp-hz = /bits/ 64 <307200000>;
156 opp-supported-hw = <0x 148 opp-supported-hw = <0xf>;
157 clock-latency-ns = <20 149 clock-latency-ns = <200000>;
158 opp-peak-kBps = <30720 <<
159 }; 150 };
160 opp-422400000 { 151 opp-422400000 {
161 opp-hz = /bits/ 64 <42 152 opp-hz = /bits/ 64 <422400000>;
162 opp-supported-hw = <0x 153 opp-supported-hw = <0xf>;
163 clock-latency-ns = <20 154 clock-latency-ns = <200000>;
164 opp-peak-kBps = <30720 <<
165 }; 155 };
166 opp-480000000 { 156 opp-480000000 {
167 opp-hz = /bits/ 64 <48 157 opp-hz = /bits/ 64 <480000000>;
168 opp-supported-hw = <0x 158 opp-supported-hw = <0xf>;
169 clock-latency-ns = <20 159 clock-latency-ns = <200000>;
170 opp-peak-kBps = <30720 <<
171 }; 160 };
172 opp-556800000 { 161 opp-556800000 {
173 opp-hz = /bits/ 64 <55 162 opp-hz = /bits/ 64 <556800000>;
174 opp-supported-hw = <0x 163 opp-supported-hw = <0xf>;
175 clock-latency-ns = <20 164 clock-latency-ns = <200000>;
176 opp-peak-kBps = <30720 <<
177 }; 165 };
178 opp-652800000 { 166 opp-652800000 {
179 opp-hz = /bits/ 64 <65 167 opp-hz = /bits/ 64 <652800000>;
180 opp-supported-hw = <0x 168 opp-supported-hw = <0xf>;
181 clock-latency-ns = <20 169 clock-latency-ns = <200000>;
182 opp-peak-kBps = <38400 <<
183 }; 170 };
184 opp-729600000 { 171 opp-729600000 {
185 opp-hz = /bits/ 64 <72 172 opp-hz = /bits/ 64 <729600000>;
186 opp-supported-hw = <0x 173 opp-supported-hw = <0xf>;
187 clock-latency-ns = <20 174 clock-latency-ns = <200000>;
188 opp-peak-kBps = <46080 <<
189 }; 175 };
190 opp-844800000 { 176 opp-844800000 {
191 opp-hz = /bits/ 64 <84 177 opp-hz = /bits/ 64 <844800000>;
192 opp-supported-hw = <0x 178 opp-supported-hw = <0xf>;
193 clock-latency-ns = <20 179 clock-latency-ns = <200000>;
194 opp-peak-kBps = <53760 <<
195 }; 180 };
196 opp-960000000 { 181 opp-960000000 {
197 opp-hz = /bits/ 64 <96 182 opp-hz = /bits/ 64 <960000000>;
198 opp-supported-hw = <0x 183 opp-supported-hw = <0xf>;
199 clock-latency-ns = <20 184 clock-latency-ns = <200000>;
200 opp-peak-kBps = <67200 <<
201 }; 185 };
202 opp-1036800000 { 186 opp-1036800000 {
203 opp-hz = /bits/ 64 <10 187 opp-hz = /bits/ 64 <1036800000>;
204 opp-supported-hw = <0x 188 opp-supported-hw = <0xf>;
205 clock-latency-ns = <20 189 clock-latency-ns = <200000>;
206 opp-peak-kBps = <67200 <<
207 }; 190 };
208 opp-1113600000 { 191 opp-1113600000 {
209 opp-hz = /bits/ 64 <11 192 opp-hz = /bits/ 64 <1113600000>;
210 opp-supported-hw = <0x 193 opp-supported-hw = <0xf>;
211 clock-latency-ns = <20 194 clock-latency-ns = <200000>;
212 opp-peak-kBps = <82560 <<
213 }; 195 };
214 opp-1190400000 { 196 opp-1190400000 {
215 opp-hz = /bits/ 64 <11 197 opp-hz = /bits/ 64 <1190400000>;
216 opp-supported-hw = <0x 198 opp-supported-hw = <0xf>;
217 clock-latency-ns = <20 199 clock-latency-ns = <200000>;
218 opp-peak-kBps = <82560 <<
219 }; 200 };
220 opp-1228800000 { 201 opp-1228800000 {
221 opp-hz = /bits/ 64 <12 202 opp-hz = /bits/ 64 <1228800000>;
222 opp-supported-hw = <0x 203 opp-supported-hw = <0xf>;
223 clock-latency-ns = <20 204 clock-latency-ns = <200000>;
224 opp-peak-kBps = <90240 <<
225 }; 205 };
226 opp-1324800000 { 206 opp-1324800000 {
227 opp-hz = /bits/ 64 <13 207 opp-hz = /bits/ 64 <1324800000>;
228 opp-supported-hw = <0x 208 opp-supported-hw = <0xd>;
229 clock-latency-ns = <20 209 clock-latency-ns = <200000>;
230 opp-peak-kBps = <10560 <<
231 }; 210 };
232 opp-1363200000 { 211 opp-1363200000 {
233 opp-hz = /bits/ 64 <13 212 opp-hz = /bits/ 64 <1363200000>;
234 opp-supported-hw = <0x 213 opp-supported-hw = <0x2>;
235 clock-latency-ns = <20 214 clock-latency-ns = <200000>;
236 opp-peak-kBps = <11328 <<
237 }; 215 };
238 opp-1401600000 { 216 opp-1401600000 {
239 opp-hz = /bits/ 64 <14 217 opp-hz = /bits/ 64 <1401600000>;
240 opp-supported-hw = <0x 218 opp-supported-hw = <0xd>;
241 clock-latency-ns = <20 219 clock-latency-ns = <200000>;
242 opp-peak-kBps = <11328 <<
243 }; 220 };
244 opp-1478400000 { 221 opp-1478400000 {
245 opp-hz = /bits/ 64 <14 222 opp-hz = /bits/ 64 <1478400000>;
246 opp-supported-hw = <0x 223 opp-supported-hw = <0x9>;
247 clock-latency-ns = <20 224 clock-latency-ns = <200000>;
248 opp-peak-kBps = <11904 <<
249 }; 225 };
250 opp-1497600000 { 226 opp-1497600000 {
251 opp-hz = /bits/ 64 <14 227 opp-hz = /bits/ 64 <1497600000>;
252 opp-supported-hw = <0x 228 opp-supported-hw = <0x04>;
253 clock-latency-ns = <20 229 clock-latency-ns = <200000>;
254 opp-peak-kBps = <13056 <<
255 }; 230 };
256 opp-1593600000 { 231 opp-1593600000 {
257 opp-hz = /bits/ 64 <15 232 opp-hz = /bits/ 64 <1593600000>;
258 opp-supported-hw = <0x 233 opp-supported-hw = <0x9>;
259 clock-latency-ns = <20 234 clock-latency-ns = <200000>;
260 opp-peak-kBps = <13824 <<
261 }; 235 };
262 }; 236 };
263 237
264 cluster1_opp: opp-table-cluster1 { 238 cluster1_opp: opp-table-cluster1 {
265 compatible = "operating-points 239 compatible = "operating-points-v2-kryo-cpu";
266 nvmem-cells = <&speedbin_efuse 240 nvmem-cells = <&speedbin_efuse>;
267 opp-shared; 241 opp-shared;
268 242
269 /* Nominal fmax for now */ 243 /* Nominal fmax for now */
270 opp-307200000 { 244 opp-307200000 {
271 opp-hz = /bits/ 64 <30 245 opp-hz = /bits/ 64 <307200000>;
272 opp-supported-hw = <0x 246 opp-supported-hw = <0xf>;
273 clock-latency-ns = <20 247 clock-latency-ns = <200000>;
274 opp-peak-kBps = <30720 <<
275 }; 248 };
276 opp-403200000 { 249 opp-403200000 {
277 opp-hz = /bits/ 64 <40 250 opp-hz = /bits/ 64 <403200000>;
278 opp-supported-hw = <0x 251 opp-supported-hw = <0xf>;
279 clock-latency-ns = <20 252 clock-latency-ns = <200000>;
280 opp-peak-kBps = <30720 <<
281 }; 253 };
282 opp-480000000 { 254 opp-480000000 {
283 opp-hz = /bits/ 64 <48 255 opp-hz = /bits/ 64 <480000000>;
284 opp-supported-hw = <0x 256 opp-supported-hw = <0xf>;
285 clock-latency-ns = <20 257 clock-latency-ns = <200000>;
286 opp-peak-kBps = <30720 <<
287 }; 258 };
288 opp-556800000 { 259 opp-556800000 {
289 opp-hz = /bits/ 64 <55 260 opp-hz = /bits/ 64 <556800000>;
290 opp-supported-hw = <0x 261 opp-supported-hw = <0xf>;
291 clock-latency-ns = <20 262 clock-latency-ns = <200000>;
292 opp-peak-kBps = <30720 <<
293 }; 263 };
294 opp-652800000 { 264 opp-652800000 {
295 opp-hz = /bits/ 64 <65 265 opp-hz = /bits/ 64 <652800000>;
296 opp-supported-hw = <0x 266 opp-supported-hw = <0xf>;
297 clock-latency-ns = <20 267 clock-latency-ns = <200000>;
298 opp-peak-kBps = <30720 <<
299 }; 268 };
300 opp-729600000 { 269 opp-729600000 {
301 opp-hz = /bits/ 64 <72 270 opp-hz = /bits/ 64 <729600000>;
302 opp-supported-hw = <0x 271 opp-supported-hw = <0xf>;
303 clock-latency-ns = <20 272 clock-latency-ns = <200000>;
304 opp-peak-kBps = <30720 <<
305 }; 273 };
306 opp-806400000 { 274 opp-806400000 {
307 opp-hz = /bits/ 64 <80 275 opp-hz = /bits/ 64 <806400000>;
308 opp-supported-hw = <0x 276 opp-supported-hw = <0xf>;
309 clock-latency-ns = <20 277 clock-latency-ns = <200000>;
310 opp-peak-kBps = <38400 <<
311 }; 278 };
312 opp-883200000 { 279 opp-883200000 {
313 opp-hz = /bits/ 64 <88 280 opp-hz = /bits/ 64 <883200000>;
314 opp-supported-hw = <0x 281 opp-supported-hw = <0xf>;
315 clock-latency-ns = <20 282 clock-latency-ns = <200000>;
316 opp-peak-kBps = <46080 <<
317 }; 283 };
318 opp-940800000 { 284 opp-940800000 {
319 opp-hz = /bits/ 64 <94 285 opp-hz = /bits/ 64 <940800000>;
320 opp-supported-hw = <0x 286 opp-supported-hw = <0xf>;
321 clock-latency-ns = <20 287 clock-latency-ns = <200000>;
322 opp-peak-kBps = <53760 <<
323 }; 288 };
324 opp-1036800000 { 289 opp-1036800000 {
325 opp-hz = /bits/ 64 <10 290 opp-hz = /bits/ 64 <1036800000>;
326 opp-supported-hw = <0x 291 opp-supported-hw = <0xf>;
327 clock-latency-ns = <20 292 clock-latency-ns = <200000>;
328 opp-peak-kBps = <59520 <<
329 }; 293 };
330 opp-1113600000 { 294 opp-1113600000 {
331 opp-hz = /bits/ 64 <11 295 opp-hz = /bits/ 64 <1113600000>;
332 opp-supported-hw = <0x 296 opp-supported-hw = <0xf>;
333 clock-latency-ns = <20 297 clock-latency-ns = <200000>;
334 opp-peak-kBps = <67200 <<
335 }; 298 };
336 opp-1190400000 { 299 opp-1190400000 {
337 opp-hz = /bits/ 64 <11 300 opp-hz = /bits/ 64 <1190400000>;
338 opp-supported-hw = <0x 301 opp-supported-hw = <0xf>;
339 clock-latency-ns = <20 302 clock-latency-ns = <200000>;
340 opp-peak-kBps = <67200 <<
341 }; 303 };
342 opp-1248000000 { 304 opp-1248000000 {
343 opp-hz = /bits/ 64 <12 305 opp-hz = /bits/ 64 <1248000000>;
344 opp-supported-hw = <0x 306 opp-supported-hw = <0xf>;
345 clock-latency-ns = <20 307 clock-latency-ns = <200000>;
346 opp-peak-kBps = <74880 <<
347 }; 308 };
348 opp-1324800000 { 309 opp-1324800000 {
349 opp-hz = /bits/ 64 <13 310 opp-hz = /bits/ 64 <1324800000>;
350 opp-supported-hw = <0x 311 opp-supported-hw = <0xf>;
351 clock-latency-ns = <20 312 clock-latency-ns = <200000>;
352 opp-peak-kBps = <82560 <<
353 }; 313 };
354 opp-1401600000 { 314 opp-1401600000 {
355 opp-hz = /bits/ 64 <14 315 opp-hz = /bits/ 64 <1401600000>;
356 opp-supported-hw = <0x 316 opp-supported-hw = <0xf>;
357 clock-latency-ns = <20 317 clock-latency-ns = <200000>;
358 opp-peak-kBps = <90240 <<
359 }; 318 };
360 opp-1478400000 { 319 opp-1478400000 {
361 opp-hz = /bits/ 64 <14 320 opp-hz = /bits/ 64 <1478400000>;
362 opp-supported-hw = <0x 321 opp-supported-hw = <0xf>;
363 clock-latency-ns = <20 322 clock-latency-ns = <200000>;
364 opp-peak-kBps = <97920 <<
365 }; 323 };
366 opp-1555200000 { 324 opp-1555200000 {
367 opp-hz = /bits/ 64 <15 325 opp-hz = /bits/ 64 <1555200000>;
368 opp-supported-hw = <0x 326 opp-supported-hw = <0xf>;
369 clock-latency-ns = <20 327 clock-latency-ns = <200000>;
370 opp-peak-kBps = <10560 <<
371 }; 328 };
372 opp-1632000000 { 329 opp-1632000000 {
373 opp-hz = /bits/ 64 <16 330 opp-hz = /bits/ 64 <1632000000>;
374 opp-supported-hw = <0x 331 opp-supported-hw = <0xf>;
375 clock-latency-ns = <20 332 clock-latency-ns = <200000>;
376 opp-peak-kBps = <11904 <<
377 }; 333 };
378 opp-1708800000 { 334 opp-1708800000 {
379 opp-hz = /bits/ 64 <17 335 opp-hz = /bits/ 64 <1708800000>;
380 opp-supported-hw = <0x 336 opp-supported-hw = <0xf>;
381 clock-latency-ns = <20 337 clock-latency-ns = <200000>;
382 opp-peak-kBps = <12288 <<
383 }; 338 };
384 opp-1785600000 { 339 opp-1785600000 {
385 opp-hz = /bits/ 64 <17 340 opp-hz = /bits/ 64 <1785600000>;
386 opp-supported-hw = <0x 341 opp-supported-hw = <0xf>;
387 clock-latency-ns = <20 342 clock-latency-ns = <200000>;
388 opp-peak-kBps = <13056 <<
389 }; 343 };
390 opp-1804800000 { 344 opp-1804800000 {
391 opp-hz = /bits/ 64 <18 345 opp-hz = /bits/ 64 <1804800000>;
392 opp-supported-hw = <0x 346 opp-supported-hw = <0xe>;
393 clock-latency-ns = <20 347 clock-latency-ns = <200000>;
394 opp-peak-kBps = <13056 <<
395 }; 348 };
396 opp-1824000000 { 349 opp-1824000000 {
397 opp-hz = /bits/ 64 <18 350 opp-hz = /bits/ 64 <1824000000>;
398 opp-supported-hw = <0x 351 opp-supported-hw = <0x1>;
399 clock-latency-ns = <20 352 clock-latency-ns = <200000>;
400 opp-peak-kBps = <13824 <<
401 }; 353 };
402 opp-1900800000 { 354 opp-1900800000 {
403 opp-hz = /bits/ 64 <19 355 opp-hz = /bits/ 64 <1900800000>;
404 opp-supported-hw = <0x 356 opp-supported-hw = <0x4>;
405 clock-latency-ns = <20 357 clock-latency-ns = <200000>;
406 opp-peak-kBps = <13056 <<
407 }; 358 };
408 opp-1920000000 { 359 opp-1920000000 {
409 opp-hz = /bits/ 64 <19 360 opp-hz = /bits/ 64 <1920000000>;
410 opp-supported-hw = <0x 361 opp-supported-hw = <0x1>;
411 clock-latency-ns = <20 362 clock-latency-ns = <200000>;
412 opp-peak-kBps = <14592 <<
413 }; 363 };
414 opp-1996800000 { 364 opp-1996800000 {
415 opp-hz = /bits/ 64 <19 365 opp-hz = /bits/ 64 <1996800000>;
416 opp-supported-hw = <0x 366 opp-supported-hw = <0x1>;
417 clock-latency-ns = <20 367 clock-latency-ns = <200000>;
418 opp-peak-kBps = <15936 <<
419 }; 368 };
420 opp-2073600000 { 369 opp-2073600000 {
421 opp-hz = /bits/ 64 <20 370 opp-hz = /bits/ 64 <2073600000>;
422 opp-supported-hw = <0x 371 opp-supported-hw = <0x1>;
423 clock-latency-ns = <20 372 clock-latency-ns = <200000>;
424 opp-peak-kBps = <15936 <<
425 }; 373 };
426 opp-2150400000 { 374 opp-2150400000 {
427 opp-hz = /bits/ 64 <21 375 opp-hz = /bits/ 64 <2150400000>;
428 opp-supported-hw = <0x 376 opp-supported-hw = <0x1>;
429 clock-latency-ns = <20 377 clock-latency-ns = <200000>;
430 opp-peak-kBps = <15936 <<
431 }; 378 };
432 }; 379 };
433 380
434 firmware { 381 firmware {
435 scm { 382 scm {
436 compatible = "qcom,scm 383 compatible = "qcom,scm-msm8996", "qcom,scm";
437 qcom,dload-mode = <&tc 384 qcom,dload-mode = <&tcsr_2 0x13000>;
438 }; 385 };
439 }; 386 };
440 387
441 memory@80000000 { 388 memory@80000000 {
442 device_type = "memory"; 389 device_type = "memory";
443 /* We expect the bootloader to 390 /* We expect the bootloader to fill in the reg */
444 reg = <0x0 0x80000000 0x0 0x0> 391 reg = <0x0 0x80000000 0x0 0x0>;
445 }; 392 };
446 393
447 etm { <<
448 compatible = "qcom,coresight-r <<
449 <<
450 out-ports { <<
451 port { <<
452 modem_etm_out_ <<
453 remote <<
454 <&fu <<
455 }; <<
456 }; <<
457 }; <<
458 }; <<
459 <<
460 psci { 394 psci {
461 compatible = "arm,psci-1.0"; 395 compatible = "arm,psci-1.0";
462 method = "smc"; 396 method = "smc";
463 }; 397 };
464 398
465 rpm: remoteproc { <<
466 compatible = "qcom,msm8996-rpm <<
467 <<
468 glink-edge { <<
469 compatible = "qcom,gli <<
470 interrupts = <GIC_SPI <<
471 qcom,rpm-msg-ram = <&r <<
472 mboxes = <&apcs_glb 0> <<
473 <<
474 rpm_requests: rpm-requ <<
475 compatible = " <<
476 qcom,glink-cha <<
477 <<
478 rpmcc: clock-c <<
479 compat <<
480 #clock <<
481 clocks <<
482 clock- <<
483 }; <<
484 <<
485 rpmpd: power-c <<
486 compat <<
487 #power <<
488 operat <<
489 <<
490 rpmpd_ <<
491 <<
492 <<
493 <<
494 <<
495 <<
496 <<
497 <<
498 <<
499 <<
500 <<
501 <<
502 <<
503 <<
504 <<
505 <<
506 <<
507 <<
508 <<
509 <<
510 <<
511 <<
512 <<
513 <<
514 <<
515 <<
516 }; <<
517 }; <<
518 }; <<
519 }; <<
520 }; <<
521 <<
522 reserved-memory { 399 reserved-memory {
523 #address-cells = <2>; 400 #address-cells = <2>;
524 #size-cells = <2>; 401 #size-cells = <2>;
525 ranges; 402 ranges;
526 403
527 hyp_mem: memory@85800000 { 404 hyp_mem: memory@85800000 {
528 reg = <0x0 0x85800000 405 reg = <0x0 0x85800000 0x0 0x600000>;
529 no-map; 406 no-map;
530 }; 407 };
531 408
532 xbl_mem: memory@85e00000 { 409 xbl_mem: memory@85e00000 {
533 reg = <0x0 0x85e00000 410 reg = <0x0 0x85e00000 0x0 0x200000>;
534 no-map; 411 no-map;
535 }; 412 };
536 413
537 smem_mem: smem-mem@86000000 { 414 smem_mem: smem-mem@86000000 {
538 reg = <0x0 0x86000000 415 reg = <0x0 0x86000000 0x0 0x200000>;
539 no-map; 416 no-map;
540 }; 417 };
541 418
542 tz_mem: memory@86200000 { 419 tz_mem: memory@86200000 {
543 reg = <0x0 0x86200000 420 reg = <0x0 0x86200000 0x0 0x2600000>;
544 no-map; 421 no-map;
545 }; 422 };
546 423
547 rmtfs_mem: rmtfs { 424 rmtfs_mem: rmtfs {
548 compatible = "qcom,rmt 425 compatible = "qcom,rmtfs-mem";
549 426
550 size = <0x0 0x200000>; 427 size = <0x0 0x200000>;
551 alloc-ranges = <0x0 0x 428 alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>;
552 no-map; 429 no-map;
553 430
554 qcom,client-id = <1>; 431 qcom,client-id = <1>;
555 qcom,vmid = <QCOM_SCM_ !! 432 qcom,vmid = <15>;
556 }; 433 };
557 434
558 mpss_mem: mpss@88800000 { 435 mpss_mem: mpss@88800000 {
559 reg = <0x0 0x88800000 436 reg = <0x0 0x88800000 0x0 0x6200000>;
560 no-map; 437 no-map;
561 }; 438 };
562 439
563 adsp_mem: adsp@8ea00000 { 440 adsp_mem: adsp@8ea00000 {
564 reg = <0x0 0x8ea00000 441 reg = <0x0 0x8ea00000 0x0 0x1b00000>;
565 no-map; 442 no-map;
566 }; 443 };
567 444
568 slpi_mem: slpi@90500000 { 445 slpi_mem: slpi@90500000 {
569 reg = <0x0 0x90500000 446 reg = <0x0 0x90500000 0x0 0xa00000>;
570 no-map; 447 no-map;
571 }; 448 };
572 449
573 gpu_mem: gpu@90f00000 { 450 gpu_mem: gpu@90f00000 {
574 compatible = "shared-d 451 compatible = "shared-dma-pool";
575 reg = <0x0 0x90f00000 452 reg = <0x0 0x90f00000 0x0 0x100000>;
576 no-map; 453 no-map;
577 }; 454 };
578 455
579 venus_mem: venus@91000000 { 456 venus_mem: venus@91000000 {
580 reg = <0x0 0x91000000 457 reg = <0x0 0x91000000 0x0 0x500000>;
581 no-map; 458 no-map;
582 }; 459 };
583 460
584 mba_mem: mba@91500000 { 461 mba_mem: mba@91500000 {
585 reg = <0x0 0x91500000 462 reg = <0x0 0x91500000 0x0 0x200000>;
586 no-map; 463 no-map;
587 }; 464 };
>> 465 };
588 466
589 mdata_mem: mpss-metadata { !! 467 rpm-glink {
590 alloc-ranges = <0x0 0x !! 468 compatible = "qcom,glink-rpm";
591 size = <0x0 0x4000>; !! 469
592 no-map; !! 470 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
>> 471
>> 472 qcom,rpm-msg-ram = <&rpm_msg_ram>;
>> 473
>> 474 mboxes = <&apcs_glb 0>;
>> 475
>> 476 rpm_requests: rpm-requests {
>> 477 compatible = "qcom,rpm-msm8996";
>> 478 qcom,glink-channels = "rpm_requests";
>> 479
>> 480 rpmcc: qcom,rpmcc {
>> 481 compatible = "qcom,rpmcc-msm8996", "qcom,rpmcc";
>> 482 #clock-cells = <1>;
>> 483 clocks = <&xo_board>;
>> 484 clock-names = "xo";
>> 485 };
>> 486
>> 487 rpmpd: power-controller {
>> 488 compatible = "qcom,msm8996-rpmpd";
>> 489 #power-domain-cells = <1>;
>> 490 operating-points-v2 = <&rpmpd_opp_table>;
>> 491
>> 492 rpmpd_opp_table: opp-table {
>> 493 compatible = "operating-points-v2";
>> 494
>> 495 rpmpd_opp1: opp1 {
>> 496 opp-level = <1>;
>> 497 };
>> 498
>> 499 rpmpd_opp2: opp2 {
>> 500 opp-level = <2>;
>> 501 };
>> 502
>> 503 rpmpd_opp3: opp3 {
>> 504 opp-level = <3>;
>> 505 };
>> 506
>> 507 rpmpd_opp4: opp4 {
>> 508 opp-level = <4>;
>> 509 };
>> 510
>> 511 rpmpd_opp5: opp5 {
>> 512 opp-level = <5>;
>> 513 };
>> 514
>> 515 rpmpd_opp6: opp6 {
>> 516 opp-level = <6>;
>> 517 };
>> 518 };
>> 519 };
593 }; 520 };
594 }; 521 };
595 522
596 smem { 523 smem {
597 compatible = "qcom,smem"; 524 compatible = "qcom,smem";
598 memory-region = <&smem_mem>; 525 memory-region = <&smem_mem>;
599 hwlocks = <&tcsr_mutex 3>; 526 hwlocks = <&tcsr_mutex 3>;
600 }; 527 };
601 528
602 smp2p-adsp { 529 smp2p-adsp {
603 compatible = "qcom,smp2p"; 530 compatible = "qcom,smp2p";
604 qcom,smem = <443>, <429>; 531 qcom,smem = <443>, <429>;
605 532
606 interrupts = <GIC_SPI 158 IRQ_ !! 533 interrupts = <0 158 IRQ_TYPE_EDGE_RISING>;
607 534
608 mboxes = <&apcs_glb 10>; 535 mboxes = <&apcs_glb 10>;
609 536
610 qcom,local-pid = <0>; 537 qcom,local-pid = <0>;
611 qcom,remote-pid = <2>; 538 qcom,remote-pid = <2>;
612 539
613 adsp_smp2p_out: master-kernel 540 adsp_smp2p_out: master-kernel {
614 qcom,entry-name = "mas 541 qcom,entry-name = "master-kernel";
615 #qcom,smem-state-cells 542 #qcom,smem-state-cells = <1>;
616 }; 543 };
617 544
618 adsp_smp2p_in: slave-kernel { 545 adsp_smp2p_in: slave-kernel {
619 qcom,entry-name = "sla 546 qcom,entry-name = "slave-kernel";
620 547
621 interrupt-controller; 548 interrupt-controller;
622 #interrupt-cells = <2> 549 #interrupt-cells = <2>;
623 }; 550 };
624 }; 551 };
625 552
626 smp2p-mpss { 553 smp2p-mpss {
627 compatible = "qcom,smp2p"; 554 compatible = "qcom,smp2p";
628 qcom,smem = <435>, <428>; 555 qcom,smem = <435>, <428>;
629 556
630 interrupts = <GIC_SPI 451 IRQ_ 557 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
631 558
632 mboxes = <&apcs_glb 14>; 559 mboxes = <&apcs_glb 14>;
633 560
634 qcom,local-pid = <0>; 561 qcom,local-pid = <0>;
635 qcom,remote-pid = <1>; 562 qcom,remote-pid = <1>;
636 563
637 mpss_smp2p_out: master-kernel 564 mpss_smp2p_out: master-kernel {
638 qcom,entry-name = "mas 565 qcom,entry-name = "master-kernel";
639 #qcom,smem-state-cells 566 #qcom,smem-state-cells = <1>;
640 }; 567 };
641 568
642 mpss_smp2p_in: slave-kernel { 569 mpss_smp2p_in: slave-kernel {
643 qcom,entry-name = "sla 570 qcom,entry-name = "slave-kernel";
644 571
645 interrupt-controller; 572 interrupt-controller;
646 #interrupt-cells = <2> 573 #interrupt-cells = <2>;
647 }; 574 };
648 }; 575 };
649 576
650 smp2p-slpi { 577 smp2p-slpi {
651 compatible = "qcom,smp2p"; 578 compatible = "qcom,smp2p";
652 qcom,smem = <481>, <430>; 579 qcom,smem = <481>, <430>;
653 580
654 interrupts = <GIC_SPI 178 IRQ_ 581 interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>;
655 582
656 mboxes = <&apcs_glb 26>; 583 mboxes = <&apcs_glb 26>;
657 584
658 qcom,local-pid = <0>; 585 qcom,local-pid = <0>;
659 qcom,remote-pid = <3>; 586 qcom,remote-pid = <3>;
660 587
661 slpi_smp2p_out: master-kernel 588 slpi_smp2p_out: master-kernel {
662 qcom,entry-name = "mas 589 qcom,entry-name = "master-kernel";
663 #qcom,smem-state-cells 590 #qcom,smem-state-cells = <1>;
664 }; 591 };
665 592
666 slpi_smp2p_in: slave-kernel { 593 slpi_smp2p_in: slave-kernel {
667 qcom,entry-name = "sla 594 qcom,entry-name = "slave-kernel";
668 595
669 interrupt-controller; 596 interrupt-controller;
670 #interrupt-cells = <2> 597 #interrupt-cells = <2>;
671 }; 598 };
672 }; 599 };
673 600
674 soc: soc@0 { !! 601 soc: soc {
675 #address-cells = <1>; 602 #address-cells = <1>;
676 #size-cells = <1>; 603 #size-cells = <1>;
677 ranges = <0 0 0 0xffffffff>; 604 ranges = <0 0 0 0xffffffff>;
678 compatible = "simple-bus"; 605 compatible = "simple-bus";
679 606
680 pcie_phy: phy-wrapper@34000 { 607 pcie_phy: phy-wrapper@34000 {
681 compatible = "qcom,msm 608 compatible = "qcom,msm8996-qmp-pcie-phy";
682 reg = <0x00034000 0x48 609 reg = <0x00034000 0x488>;
683 #address-cells = <1>; 610 #address-cells = <1>;
684 #size-cells = <1>; 611 #size-cells = <1>;
685 ranges = <0x0 0x000340 612 ranges = <0x0 0x00034000 0x4000>;
686 613
687 clocks = <&gcc GCC_PCI 614 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
688 <&gcc GCC_PCIE 615 <&gcc GCC_PCIE_PHY_CFG_AHB_CLK>,
689 <&gcc GCC_PCIE 616 <&gcc GCC_PCIE_CLKREF_CLK>;
690 clock-names = "aux", " 617 clock-names = "aux", "cfg_ahb", "ref";
691 618
692 resets = <&gcc GCC_PCI 619 resets = <&gcc GCC_PCIE_PHY_BCR>,
693 <&gcc GCC_PCIE 620 <&gcc GCC_PCIE_PHY_COM_BCR>,
694 <&gcc GCC_PCIE 621 <&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>;
695 reset-names = "phy", " 622 reset-names = "phy", "common", "cfg";
696 623
697 status = "disabled"; 624 status = "disabled";
698 625
699 pciephy_0: phy@1000 { 626 pciephy_0: phy@1000 {
700 reg = <0x1000 627 reg = <0x1000 0x130>,
701 <0x1200 628 <0x1200 0x200>,
702 <0x1400 629 <0x1400 0x1dc>;
703 630
704 clocks = <&gcc 631 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
705 clock-names = 632 clock-names = "pipe0";
706 resets = <&gcc 633 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
707 reset-names = 634 reset-names = "lane0";
708 635
709 #clock-cells = 636 #clock-cells = <0>;
710 clock-output-n 637 clock-output-names = "pcie_0_pipe_clk_src";
711 638
712 #phy-cells = < 639 #phy-cells = <0>;
713 }; 640 };
714 641
715 pciephy_1: phy@2000 { 642 pciephy_1: phy@2000 {
716 reg = <0x2000 643 reg = <0x2000 0x130>,
717 <0x2200 644 <0x2200 0x200>,
718 <0x2400 645 <0x2400 0x1dc>;
719 646
720 clocks = <&gcc 647 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
721 clock-names = 648 clock-names = "pipe1";
722 resets = <&gcc 649 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
723 reset-names = 650 reset-names = "lane1";
724 651
725 #clock-cells = 652 #clock-cells = <0>;
726 clock-output-n 653 clock-output-names = "pcie_1_pipe_clk_src";
727 654
728 #phy-cells = < 655 #phy-cells = <0>;
729 }; 656 };
730 657
731 pciephy_2: phy@3000 { 658 pciephy_2: phy@3000 {
732 reg = <0x3000 659 reg = <0x3000 0x130>,
733 <0x3200 660 <0x3200 0x200>,
734 <0x3400 661 <0x3400 0x1dc>;
735 662
736 clocks = <&gcc 663 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>;
737 clock-names = 664 clock-names = "pipe2";
738 resets = <&gcc 665 resets = <&gcc GCC_PCIE_2_PHY_BCR>;
739 reset-names = 666 reset-names = "lane2";
740 667
741 #clock-cells = 668 #clock-cells = <0>;
742 clock-output-n 669 clock-output-names = "pcie_2_pipe_clk_src";
743 670
744 #phy-cells = < 671 #phy-cells = <0>;
745 }; 672 };
746 }; 673 };
747 674
748 rpm_msg_ram: sram@68000 { 675 rpm_msg_ram: sram@68000 {
749 compatible = "qcom,rpm 676 compatible = "qcom,rpm-msg-ram";
750 reg = <0x00068000 0x60 677 reg = <0x00068000 0x6000>;
751 }; 678 };
752 679
753 qfprom@74000 { 680 qfprom@74000 {
754 compatible = "qcom,msm 681 compatible = "qcom,msm8996-qfprom", "qcom,qfprom";
755 reg = <0x00074000 0x8f 682 reg = <0x00074000 0x8ff>;
756 #address-cells = <1>; 683 #address-cells = <1>;
757 #size-cells = <1>; 684 #size-cells = <1>;
758 685
759 qusb2p_hstx_trim: hstx !! 686 qusb2p_hstx_trim: hstx_trim@24e {
760 reg = <0x24e 0 687 reg = <0x24e 0x2>;
761 bits = <5 4>; 688 bits = <5 4>;
762 }; 689 };
763 690
764 qusb2s_hstx_trim: hstx !! 691 qusb2s_hstx_trim: hstx_trim@24f {
765 reg = <0x24f 0 692 reg = <0x24f 0x1>;
766 bits = <1 4>; 693 bits = <1 4>;
767 }; 694 };
768 695
769 speedbin_efuse: speedb 696 speedbin_efuse: speedbin@133 {
770 reg = <0x133 0 697 reg = <0x133 0x1>;
771 bits = <5 3>; 698 bits = <5 3>;
772 }; 699 };
773 }; 700 };
774 701
775 rng: rng@83000 { 702 rng: rng@83000 {
776 compatible = "qcom,prn 703 compatible = "qcom,prng-ee";
777 reg = <0x00083000 0x10 704 reg = <0x00083000 0x1000>;
778 clocks = <&gcc GCC_PRN 705 clocks = <&gcc GCC_PRNG_AHB_CLK>;
779 clock-names = "core"; 706 clock-names = "core";
780 }; 707 };
781 708
782 gcc: clock-controller@300000 { 709 gcc: clock-controller@300000 {
783 compatible = "qcom,gcc 710 compatible = "qcom,gcc-msm8996";
784 #clock-cells = <1>; 711 #clock-cells = <1>;
785 #reset-cells = <1>; 712 #reset-cells = <1>;
786 #power-domain-cells = 713 #power-domain-cells = <1>;
787 reg = <0x00300000 0x90 714 reg = <0x00300000 0x90000>;
788 715
789 clocks = <&rpmcc RPM_S 716 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
790 <&rpmcc RPM_S 717 <&rpmcc RPM_SMD_LN_BB_CLK>,
791 <&sleep_clk>, 718 <&sleep_clk>,
792 <&pciephy_0>, 719 <&pciephy_0>,
793 <&pciephy_1>, 720 <&pciephy_1>,
794 <&pciephy_2>, 721 <&pciephy_2>,
795 <&usb3phy>, !! 722 <&ssusb_phy_0>,
796 <&ufsphy 0>, !! 723 <0>, <0>, <0>;
797 <&ufsphy 1>, <<
798 <&ufsphy 2>; <<
799 clock-names = "cxo", 724 clock-names = "cxo",
800 "cxo2", 725 "cxo2",
801 "sleep_c 726 "sleep_clk",
802 "pcie_0_ 727 "pcie_0_pipe_clk_src",
803 "pcie_1_ 728 "pcie_1_pipe_clk_src",
804 "pcie_2_ 729 "pcie_2_pipe_clk_src",
805 "usb3_ph 730 "usb3_phy_pipe_clk_src",
806 "ufs_rx_ 731 "ufs_rx_symbol_0_clk_src",
807 "ufs_rx_ 732 "ufs_rx_symbol_1_clk_src",
808 "ufs_tx_ 733 "ufs_tx_symbol_0_clk_src";
809 }; 734 };
810 735
811 bimc: interconnect@408000 { 736 bimc: interconnect@408000 {
812 compatible = "qcom,msm 737 compatible = "qcom,msm8996-bimc";
813 reg = <0x00408000 0x5a 738 reg = <0x00408000 0x5a000>;
814 #interconnect-cells = 739 #interconnect-cells = <1>;
>> 740 clock-names = "bus", "bus_a";
>> 741 clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
>> 742 <&rpmcc RPM_SMD_BIMC_A_CLK>;
815 }; 743 };
816 744
817 tsens0: thermal-sensor@4a9000 745 tsens0: thermal-sensor@4a9000 {
818 compatible = "qcom,msm 746 compatible = "qcom,msm8996-tsens", "qcom,tsens-v2";
819 reg = <0x004a9000 0x10 747 reg = <0x004a9000 0x1000>, /* TM */
820 <0x004a8000 0x10 748 <0x004a8000 0x1000>; /* SROT */
821 #qcom,sensors = <13>; 749 #qcom,sensors = <13>;
822 interrupts = <GIC_SPI 750 interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
823 <GIC_SPI 751 <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
824 interrupt-names = "upl 752 interrupt-names = "uplow", "critical";
825 #thermal-sensor-cells 753 #thermal-sensor-cells = <1>;
826 }; 754 };
827 755
828 tsens1: thermal-sensor@4ad000 756 tsens1: thermal-sensor@4ad000 {
829 compatible = "qcom,msm 757 compatible = "qcom,msm8996-tsens", "qcom,tsens-v2";
830 reg = <0x004ad000 0x10 758 reg = <0x004ad000 0x1000>, /* TM */
831 <0x004ac000 0x10 759 <0x004ac000 0x1000>; /* SROT */
832 #qcom,sensors = <8>; 760 #qcom,sensors = <8>;
833 interrupts = <GIC_SPI 761 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
834 <GIC_SPI 762 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>;
835 interrupt-names = "upl 763 interrupt-names = "uplow", "critical";
836 #thermal-sensor-cells 764 #thermal-sensor-cells = <1>;
837 }; 765 };
838 766
839 cryptobam: dma-controller@6440 767 cryptobam: dma-controller@644000 {
840 compatible = "qcom,bam 768 compatible = "qcom,bam-v1.7.0";
841 reg = <0x00644000 0x24 769 reg = <0x00644000 0x24000>;
842 interrupts = <GIC_SPI 770 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
843 clocks = <&gcc GCC_CE1 771 clocks = <&gcc GCC_CE1_CLK>;
844 clock-names = "bam_clk 772 clock-names = "bam_clk";
845 #dma-cells = <1>; 773 #dma-cells = <1>;
846 qcom,ee = <0>; 774 qcom,ee = <0>;
847 qcom,controlled-remote 775 qcom,controlled-remotely;
848 }; 776 };
849 777
850 crypto: crypto@67a000 { 778 crypto: crypto@67a000 {
851 compatible = "qcom,cry 779 compatible = "qcom,crypto-v5.4";
852 reg = <0x0067a000 0x60 780 reg = <0x0067a000 0x6000>;
853 clocks = <&gcc GCC_CE1 781 clocks = <&gcc GCC_CE1_AHB_CLK>,
854 <&gcc GCC_CE1 782 <&gcc GCC_CE1_AXI_CLK>,
855 <&gcc GCC_CE1 783 <&gcc GCC_CE1_CLK>;
856 clock-names = "iface", 784 clock-names = "iface", "bus", "core";
857 dmas = <&cryptobam 6>, 785 dmas = <&cryptobam 6>, <&cryptobam 7>;
858 dma-names = "rx", "tx" 786 dma-names = "rx", "tx";
859 }; 787 };
860 788
861 cnoc: interconnect@500000 { 789 cnoc: interconnect@500000 {
862 compatible = "qcom,msm 790 compatible = "qcom,msm8996-cnoc";
863 reg = <0x00500000 0x10 791 reg = <0x00500000 0x1000>;
864 #interconnect-cells = 792 #interconnect-cells = <1>;
>> 793 clock-names = "bus", "bus_a";
>> 794 clocks = <&rpmcc RPM_SMD_CNOC_CLK>,
>> 795 <&rpmcc RPM_SMD_CNOC_A_CLK>;
865 }; 796 };
866 797
867 snoc: interconnect@524000 { 798 snoc: interconnect@524000 {
868 compatible = "qcom,msm 799 compatible = "qcom,msm8996-snoc";
869 reg = <0x00524000 0x1c 800 reg = <0x00524000 0x1c000>;
870 #interconnect-cells = 801 #interconnect-cells = <1>;
>> 802 clock-names = "bus", "bus_a";
>> 803 clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
>> 804 <&rpmcc RPM_SMD_SNOC_A_CLK>;
871 }; 805 };
872 806
873 a0noc: interconnect@543000 { 807 a0noc: interconnect@543000 {
874 compatible = "qcom,msm 808 compatible = "qcom,msm8996-a0noc";
875 reg = <0x00543000 0x60 809 reg = <0x00543000 0x6000>;
876 #interconnect-cells = 810 #interconnect-cells = <1>;
877 clock-names = "aggre0_ 811 clock-names = "aggre0_snoc_axi",
878 "aggre0_ 812 "aggre0_cnoc_ahb",
879 "aggre0_ 813 "aggre0_noc_mpu_cfg";
880 clocks = <&gcc GCC_AGG 814 clocks = <&gcc GCC_AGGRE0_SNOC_AXI_CLK>,
881 <&gcc GCC_AGG 815 <&gcc GCC_AGGRE0_CNOC_AHB_CLK>,
882 <&gcc GCC_AGG 816 <&gcc GCC_AGGRE0_NOC_MPU_CFG_AHB_CLK>;
883 power-domains = <&gcc 817 power-domains = <&gcc AGGRE0_NOC_GDSC>;
884 }; 818 };
885 819
886 a1noc: interconnect@562000 { 820 a1noc: interconnect@562000 {
887 compatible = "qcom,msm 821 compatible = "qcom,msm8996-a1noc";
888 reg = <0x00562000 0x50 822 reg = <0x00562000 0x5000>;
889 #interconnect-cells = 823 #interconnect-cells = <1>;
>> 824 clock-names = "bus", "bus_a";
>> 825 clocks = <&rpmcc RPM_SMD_AGGR1_NOC_CLK>,
>> 826 <&rpmcc RPM_SMD_AGGR1_NOC_A_CLK>;
890 }; 827 };
891 828
892 a2noc: interconnect@583000 { 829 a2noc: interconnect@583000 {
893 compatible = "qcom,msm 830 compatible = "qcom,msm8996-a2noc";
894 reg = <0x00583000 0x70 831 reg = <0x00583000 0x7000>;
895 #interconnect-cells = 832 #interconnect-cells = <1>;
896 clock-names = "aggre2_ !! 833 clock-names = "bus", "bus_a", "aggre2_ufs_axi", "ufs_axi";
897 clocks = <&gcc GCC_AGG !! 834 clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>,
>> 835 <&rpmcc RPM_SMD_AGGR2_NOC_A_CLK>,
>> 836 <&gcc GCC_AGGRE2_UFS_AXI_CLK>,
898 <&gcc GCC_UFS 837 <&gcc GCC_UFS_AXI_CLK>;
899 }; 838 };
900 839
901 mnoc: interconnect@5a4000 { 840 mnoc: interconnect@5a4000 {
902 compatible = "qcom,msm 841 compatible = "qcom,msm8996-mnoc";
903 reg = <0x005a4000 0x1c 842 reg = <0x005a4000 0x1c000>;
904 #interconnect-cells = 843 #interconnect-cells = <1>;
905 clock-names = "iface"; !! 844 clock-names = "bus", "bus_a", "iface";
906 clocks = <&mmcc AHB_CL !! 845 clocks = <&rpmcc RPM_SMD_MMAXI_CLK>,
>> 846 <&rpmcc RPM_SMD_MMAXI_A_CLK>,
>> 847 <&mmcc AHB_CLK_SRC>;
907 }; 848 };
908 849
909 pnoc: interconnect@5c0000 { 850 pnoc: interconnect@5c0000 {
910 compatible = "qcom,msm 851 compatible = "qcom,msm8996-pnoc";
911 reg = <0x005c0000 0x30 852 reg = <0x005c0000 0x3000>;
912 #interconnect-cells = 853 #interconnect-cells = <1>;
>> 854 clock-names = "bus", "bus_a";
>> 855 clocks = <&rpmcc RPM_SMD_PCNOC_CLK>,
>> 856 <&rpmcc RPM_SMD_PCNOC_A_CLK>;
913 }; 857 };
914 858
915 tcsr_mutex: hwlock@740000 { 859 tcsr_mutex: hwlock@740000 {
916 compatible = "qcom,tcs 860 compatible = "qcom,tcsr-mutex";
917 reg = <0x00740000 0x20 861 reg = <0x00740000 0x20000>;
918 #hwlock-cells = <1>; 862 #hwlock-cells = <1>;
919 }; 863 };
920 864
921 tcsr_1: syscon@760000 { 865 tcsr_1: syscon@760000 {
922 compatible = "qcom,tcs 866 compatible = "qcom,tcsr-msm8996", "syscon";
923 reg = <0x00760000 0x20 867 reg = <0x00760000 0x20000>;
924 }; 868 };
925 869
926 tcsr_2: syscon@7a0000 { 870 tcsr_2: syscon@7a0000 {
927 compatible = "qcom,tcs 871 compatible = "qcom,tcsr-msm8996", "syscon";
928 reg = <0x007a0000 0x18 872 reg = <0x007a0000 0x18000>;
929 }; 873 };
930 874
931 mmcc: clock-controller@8c0000 875 mmcc: clock-controller@8c0000 {
932 compatible = "qcom,mmc 876 compatible = "qcom,mmcc-msm8996";
933 #clock-cells = <1>; 877 #clock-cells = <1>;
934 #reset-cells = <1>; 878 #reset-cells = <1>;
935 #power-domain-cells = 879 #power-domain-cells = <1>;
936 reg = <0x008c0000 0x40 880 reg = <0x008c0000 0x40000>;
937 clocks = <&xo_board>, 881 clocks = <&xo_board>,
938 <&gcc GPLL0>, <<
939 <&gcc GCC_MMS 882 <&gcc GCC_MMSS_NOC_CFG_AHB_CLK>,
940 <&mdss_dsi0_p !! 883 <&gcc GPLL0>,
941 <&mdss_dsi0_p !! 884 <&dsi0_phy 1>,
942 <&mdss_dsi1_p !! 885 <&dsi0_phy 0>,
943 <&mdss_dsi1_p !! 886 <&dsi1_phy 1>,
944 <&mdss_hdmi_p !! 887 <&dsi1_phy 0>,
>> 888 <&hdmi_phy>;
945 clock-names = "xo", 889 clock-names = "xo",
946 "gpll0", <<
947 "gcc_mms 890 "gcc_mmss_noc_cfg_ahb_clk",
>> 891 "gpll0",
948 "dsi0pll 892 "dsi0pll",
949 "dsi0pll 893 "dsi0pllbyte",
950 "dsi1pll 894 "dsi1pll",
951 "dsi1pll 895 "dsi1pllbyte",
952 "hdmipll 896 "hdmipll";
953 assigned-clocks = <&mm 897 assigned-clocks = <&mmcc MMPLL9_PLL>,
954 <&mm 898 <&mmcc MMPLL1_PLL>,
955 <&mm 899 <&mmcc MMPLL3_PLL>,
956 <&mm 900 <&mmcc MMPLL4_PLL>,
957 <&mm 901 <&mmcc MMPLL5_PLL>;
958 assigned-clock-rates = 902 assigned-clock-rates = <624000000>,
959 903 <810000000>,
960 904 <980000000>,
961 905 <960000000>,
962 906 <825000000>;
963 }; 907 };
964 908
965 mdss: display-subsystem@900000 !! 909 mdss: mdss@900000 {
966 compatible = "qcom,mds 910 compatible = "qcom,mdss";
967 911
968 reg = <0x00900000 0x10 912 reg = <0x00900000 0x1000>,
969 <0x009b0000 0x10 913 <0x009b0000 0x1040>,
970 <0x009b8000 0x10 914 <0x009b8000 0x1040>;
971 reg-names = "mdss_phys 915 reg-names = "mdss_phys",
972 "vbif_phys 916 "vbif_phys",
973 "vbif_nrt_ 917 "vbif_nrt_phys";
974 918
975 power-domains = <&mmcc 919 power-domains = <&mmcc MDSS_GDSC>;
976 interrupts = <GIC_SPI 920 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
977 921
978 interrupt-controller; 922 interrupt-controller;
979 #interrupt-cells = <1> 923 #interrupt-cells = <1>;
980 924
981 clocks = <&mmcc MDSS_A 925 clocks = <&mmcc MDSS_AHB_CLK>,
982 <&mmcc MDSS_M 926 <&mmcc MDSS_MDP_CLK>;
983 clock-names = "iface", 927 clock-names = "iface", "core";
984 928
985 resets = <&mmcc MDSS_B <<
986 <<
987 #address-cells = <1>; 929 #address-cells = <1>;
988 #size-cells = <1>; 930 #size-cells = <1>;
989 ranges; 931 ranges;
990 932
991 status = "disabled"; 933 status = "disabled";
992 934
993 mdp: display-controlle !! 935 mdp: mdp@901000 {
994 compatible = " !! 936 compatible = "qcom,mdp5";
995 reg = <0x00901 937 reg = <0x00901000 0x90000>;
996 reg-names = "m 938 reg-names = "mdp_phys";
997 939
998 interrupt-pare 940 interrupt-parent = <&mdss>;
999 interrupts = < 941 interrupts = <0>;
1000 942
1001 clocks = <&mm 943 clocks = <&mmcc MDSS_AHB_CLK>,
1002 <&mm 944 <&mmcc MDSS_AXI_CLK>,
1003 <&mm 945 <&mmcc MDSS_MDP_CLK>,
1004 <&mm 946 <&mmcc SMMU_MDP_AXI_CLK>,
1005 <&mm 947 <&mmcc MDSS_VSYNC_CLK>;
1006 clock-names = 948 clock-names = "iface",
1007 949 "bus",
1008 950 "core",
1009 951 "iommu",
1010 952 "vsync";
1011 953
1012 iommus = <&md 954 iommus = <&mdp_smmu 0>;
1013 955
1014 assigned-cloc 956 assigned-clocks = <&mmcc MDSS_MDP_CLK>,
1015 <&mm 957 <&mmcc MDSS_VSYNC_CLK>;
1016 assigned-cloc 958 assigned-clock-rates = <300000000>,
1017 <192 959 <19200000>;
1018 960
1019 interconnects 961 interconnects = <&mnoc MASTER_MDP_PORT0 &bimc SLAVE_EBI_CH0>,
1020 962 <&mnoc MASTER_MDP_PORT1 &bimc SLAVE_EBI_CH0>,
1021 963 <&mnoc MASTER_ROTATOR &bimc SLAVE_EBI_CH0>;
1022 interconnect- 964 interconnect-names = "mdp0-mem", "mdp1-mem", "rotator-mem";
1023 965
1024 ports { 966 ports {
1025 #addr 967 #address-cells = <1>;
1026 #size 968 #size-cells = <0>;
1027 969
1028 port@ 970 port@0 {
1029 971 reg = <0>;
1030 972 mdp5_intf3_out: endpoint {
1031 !! 973 remote-endpoint = <&hdmi_in>;
1032 974 };
1033 }; 975 };
1034 976
1035 port@ 977 port@1 {
1036 978 reg = <1>;
1037 979 mdp5_intf1_out: endpoint {
1038 !! 980 remote-endpoint = <&dsi0_in>;
1039 981 };
1040 }; 982 };
1041 983
1042 port@ 984 port@2 {
1043 985 reg = <2>;
1044 986 mdp5_intf2_out: endpoint {
1045 !! 987 remote-endpoint = <&dsi1_in>;
1046 988 };
1047 }; 989 };
1048 }; 990 };
1049 }; 991 };
1050 992
1051 mdss_dsi0: dsi@994000 !! 993 dsi0: dsi@994000 {
1052 compatible = !! 994 compatible = "qcom,mdss-dsi-ctrl";
1053 <<
1054 reg = <0x0099 995 reg = <0x00994000 0x400>;
1055 reg-names = " 996 reg-names = "dsi_ctrl";
1056 997
1057 interrupt-par 998 interrupt-parent = <&mdss>;
1058 interrupts = 999 interrupts = <4>;
1059 1000
1060 clocks = <&mm 1001 clocks = <&mmcc MDSS_MDP_CLK>,
1061 <&mm 1002 <&mmcc MDSS_BYTE0_CLK>,
1062 <&mm 1003 <&mmcc MDSS_AHB_CLK>,
1063 <&mm 1004 <&mmcc MDSS_AXI_CLK>,
1064 <&mm 1005 <&mmcc MMSS_MISC_AHB_CLK>,
1065 <&mm 1006 <&mmcc MDSS_PCLK0_CLK>,
1066 <&mm 1007 <&mmcc MDSS_ESC0_CLK>;
1067 clock-names = 1008 clock-names = "mdp_core",
1068 1009 "byte",
1069 1010 "iface",
1070 1011 "bus",
1071 1012 "core_mmss",
1072 1013 "pixel",
1073 1014 "core";
1074 assigned-cloc 1015 assigned-clocks = <&mmcc BYTE0_CLK_SRC>, <&mmcc PCLK0_CLK_SRC>;
1075 assigned-cloc !! 1016 assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
1076 1017
1077 phys = <&mdss !! 1018 phys = <&dsi0_phy>;
1078 status = "dis 1019 status = "disabled";
1079 1020
1080 #address-cell 1021 #address-cells = <1>;
1081 #size-cells = 1022 #size-cells = <0>;
1082 1023
1083 ports { 1024 ports {
1084 #addr 1025 #address-cells = <1>;
1085 #size 1026 #size-cells = <0>;
1086 1027
1087 port@ 1028 port@0 {
1088 1029 reg = <0>;
1089 !! 1030 dsi0_in: endpoint {
1090 1031 remote-endpoint = <&mdp5_intf1_out>;
1091 1032 };
1092 }; 1033 };
1093 1034
1094 port@ 1035 port@1 {
1095 1036 reg = <1>;
1096 !! 1037 dsi0_out: endpoint {
1097 1038 };
1098 }; 1039 };
1099 }; 1040 };
1100 }; 1041 };
1101 1042
1102 mdss_dsi0_phy: phy@99 !! 1043 dsi0_phy: phy@994400 {
1103 compatible = 1044 compatible = "qcom,dsi-phy-14nm";
1104 reg = <0x0099 1045 reg = <0x00994400 0x100>,
1105 <0x0099 1046 <0x00994500 0x300>,
1106 <0x0099 1047 <0x00994800 0x188>;
1107 reg-names = " 1048 reg-names = "dsi_phy",
1108 " 1049 "dsi_phy_lane",
1109 " 1050 "dsi_pll";
1110 1051
1111 #clock-cells 1052 #clock-cells = <1>;
1112 #phy-cells = 1053 #phy-cells = <0>;
1113 1054
1114 clocks = <&mm 1055 clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
1115 clock-names = 1056 clock-names = "iface", "ref";
1116 status = "dis 1057 status = "disabled";
1117 }; 1058 };
1118 1059
1119 mdss_dsi1: dsi@996000 !! 1060 dsi1: dsi@996000 {
1120 compatible = !! 1061 compatible = "qcom,mdss-dsi-ctrl";
1121 <<
1122 reg = <0x0099 1062 reg = <0x00996000 0x400>;
1123 reg-names = " 1063 reg-names = "dsi_ctrl";
1124 1064
1125 interrupt-par 1065 interrupt-parent = <&mdss>;
1126 interrupts = !! 1066 interrupts = <4>;
1127 1067
1128 clocks = <&mm 1068 clocks = <&mmcc MDSS_MDP_CLK>,
1129 <&mm 1069 <&mmcc MDSS_BYTE1_CLK>,
1130 <&mm 1070 <&mmcc MDSS_AHB_CLK>,
1131 <&mm 1071 <&mmcc MDSS_AXI_CLK>,
1132 <&mm 1072 <&mmcc MMSS_MISC_AHB_CLK>,
1133 <&mm 1073 <&mmcc MDSS_PCLK1_CLK>,
1134 <&mm 1074 <&mmcc MDSS_ESC1_CLK>;
1135 clock-names = 1075 clock-names = "mdp_core",
1136 1076 "byte",
1137 1077 "iface",
1138 1078 "bus",
1139 1079 "core_mmss",
1140 1080 "pixel",
1141 1081 "core";
1142 assigned-cloc 1082 assigned-clocks = <&mmcc BYTE1_CLK_SRC>, <&mmcc PCLK1_CLK_SRC>;
1143 assigned-cloc !! 1083 assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
1144 1084
1145 phys = <&mdss !! 1085 phys = <&dsi1_phy>;
1146 status = "dis 1086 status = "disabled";
1147 1087
1148 #address-cell 1088 #address-cells = <1>;
1149 #size-cells = 1089 #size-cells = <0>;
1150 1090
1151 ports { 1091 ports {
1152 #addr 1092 #address-cells = <1>;
1153 #size 1093 #size-cells = <0>;
1154 1094
1155 port@ 1095 port@0 {
1156 1096 reg = <0>;
1157 !! 1097 dsi1_in: endpoint {
1158 1098 remote-endpoint = <&mdp5_intf2_out>;
1159 1099 };
1160 }; 1100 };
1161 1101
1162 port@ 1102 port@1 {
1163 1103 reg = <1>;
1164 !! 1104 dsi1_out: endpoint {
1165 1105 };
1166 }; 1106 };
1167 }; 1107 };
1168 }; 1108 };
1169 1109
1170 mdss_dsi1_phy: phy@99 !! 1110 dsi1_phy: phy@996400 {
1171 compatible = 1111 compatible = "qcom,dsi-phy-14nm";
1172 reg = <0x0099 1112 reg = <0x00996400 0x100>,
1173 <0x0099 1113 <0x00996500 0x300>,
1174 <0x0099 1114 <0x00996800 0x188>;
1175 reg-names = " 1115 reg-names = "dsi_phy",
1176 " 1116 "dsi_phy_lane",
1177 " 1117 "dsi_pll";
1178 1118
1179 #clock-cells 1119 #clock-cells = <1>;
1180 #phy-cells = 1120 #phy-cells = <0>;
1181 1121
1182 clocks = <&mm 1122 clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
1183 clock-names = 1123 clock-names = "iface", "ref";
1184 status = "dis 1124 status = "disabled";
1185 }; 1125 };
1186 1126
1187 mdss_hdmi: hdmi-tx@9a !! 1127 hdmi: hdmi-tx@9a0000 {
1188 compatible = 1128 compatible = "qcom,hdmi-tx-8996";
1189 reg = <0x009a !! 1129 reg = <0x009a0000 0x50c>,
1190 <0x0007 !! 1130 <0x00070000 0x6158>,
1191 <0x009e !! 1131 <0x009e0000 0xfff>;
1192 reg-names = " 1132 reg-names = "core_physical",
1193 " 1133 "qfprom_physical",
1194 " 1134 "hdcp_physical";
1195 1135
1196 interrupt-par 1136 interrupt-parent = <&mdss>;
1197 interrupts = 1137 interrupts = <8>;
1198 1138
1199 clocks = <&mm 1139 clocks = <&mmcc MDSS_MDP_CLK>,
1200 <&mm 1140 <&mmcc MDSS_AHB_CLK>,
1201 <&mm 1141 <&mmcc MDSS_HDMI_CLK>,
1202 <&mm 1142 <&mmcc MDSS_HDMI_AHB_CLK>,
1203 <&mm 1143 <&mmcc MDSS_EXTPCLK_CLK>;
1204 clock-names = 1144 clock-names =
1205 "mdp_ 1145 "mdp_core",
1206 "ifac 1146 "iface",
1207 "core 1147 "core",
1208 "alt_ 1148 "alt_iface",
1209 "extp 1149 "extp";
1210 1150
1211 phys = <&mdss !! 1151 phys = <&hdmi_phy>;
1212 #sound-dai-ce 1152 #sound-dai-cells = <1>;
1213 1153
1214 status = "dis 1154 status = "disabled";
1215 1155
1216 ports { 1156 ports {
1217 #addr 1157 #address-cells = <1>;
1218 #size 1158 #size-cells = <0>;
1219 1159
1220 port@ 1160 port@0 {
1221 1161 reg = <0>;
1222 !! 1162 hdmi_in: endpoint {
1223 1163 remote-endpoint = <&mdp5_intf3_out>;
1224 1164 };
1225 }; 1165 };
1226 }; 1166 };
1227 }; 1167 };
1228 1168
1229 mdss_hdmi_phy: phy@9a !! 1169 hdmi_phy: phy@9a0600 {
1230 #phy-cells = 1170 #phy-cells = <0>;
1231 compatible = 1171 compatible = "qcom,hdmi-phy-8996";
1232 reg = <0x009a 1172 reg = <0x009a0600 0x1c4>,
1233 <0x009a 1173 <0x009a0a00 0x124>,
1234 <0x009a 1174 <0x009a0c00 0x124>,
1235 <0x009a 1175 <0x009a0e00 0x124>,
1236 <0x009a 1176 <0x009a1000 0x124>,
1237 <0x009a 1177 <0x009a1200 0x0c8>;
1238 reg-names = " 1178 reg-names = "hdmi_pll",
1239 " 1179 "hdmi_tx_l0",
1240 " 1180 "hdmi_tx_l1",
1241 " 1181 "hdmi_tx_l2",
1242 " 1182 "hdmi_tx_l3",
1243 " 1183 "hdmi_phy";
1244 1184
1245 clocks = <&mm 1185 clocks = <&mmcc MDSS_AHB_CLK>,
1246 <&gc 1186 <&gcc GCC_HDMI_CLKREF_CLK>,
1247 <&xo 1187 <&xo_board>;
1248 clock-names = 1188 clock-names = "iface",
1249 1189 "ref",
1250 1190 "xo";
1251 1191
1252 #clock-cells 1192 #clock-cells = <0>;
1253 1193
1254 status = "dis 1194 status = "disabled";
1255 }; 1195 };
1256 }; 1196 };
1257 1197
1258 gpu: gpu@b00000 { 1198 gpu: gpu@b00000 {
1259 compatible = "qcom,ad 1199 compatible = "qcom,adreno-530.2", "qcom,adreno";
1260 1200
1261 reg = <0x00b00000 0x3 1201 reg = <0x00b00000 0x3f000>;
1262 reg-names = "kgsl_3d0 1202 reg-names = "kgsl_3d0_reg_memory";
1263 1203
1264 interrupts = <GIC_SPI !! 1204 interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;
1265 1205
1266 clocks = <&mmcc GPU_G 1206 clocks = <&mmcc GPU_GX_GFX3D_CLK>,
1267 <&mmcc GPU_AH 1207 <&mmcc GPU_AHB_CLK>,
1268 <&mmcc GPU_GX 1208 <&mmcc GPU_GX_RBBMTIMER_CLK>,
1269 <&gcc GCC_BIM 1209 <&gcc GCC_BIMC_GFX_CLK>,
1270 <&gcc GCC_MMS 1210 <&gcc GCC_MMSS_BIMC_GFX_CLK>;
1271 1211
1272 clock-names = "core", 1212 clock-names = "core",
1273 "iface", 1213 "iface",
1274 "rbbmtimer", 1214 "rbbmtimer",
1275 "mem", 1215 "mem",
1276 "mem_iface"; 1216 "mem_iface";
1277 1217
1278 interconnects = <&bim 1218 interconnects = <&bimc MASTER_GRAPHICS_3D &bimc SLAVE_EBI_CH0>;
1279 interconnect-names = 1219 interconnect-names = "gfx-mem";
1280 1220
1281 power-domains = <&mmc 1221 power-domains = <&mmcc GPU_GX_GDSC>;
1282 iommus = <&adreno_smm 1222 iommus = <&adreno_smmu 0>;
1283 1223
1284 nvmem-cells = <&speed 1224 nvmem-cells = <&speedbin_efuse>;
1285 nvmem-cell-names = "s 1225 nvmem-cell-names = "speed_bin";
1286 1226
1287 operating-points-v2 = 1227 operating-points-v2 = <&gpu_opp_table>;
1288 1228
1289 status = "disabled"; 1229 status = "disabled";
1290 1230
1291 #cooling-cells = <2>; 1231 #cooling-cells = <2>;
1292 1232
1293 gpu_opp_table: opp-ta 1233 gpu_opp_table: opp-table {
1294 compatible = 1234 compatible = "operating-points-v2";
1295 1235
1296 /* 1236 /*
1297 * 624Mhz is 1237 * 624Mhz is only available on speed bins 0 and 3.
1298 * 560Mhz is 1238 * 560Mhz is only available on speed bins 0, 2 and 3.
1299 * All the re 1239 * All the rest are available on all bins of the hardware.
1300 */ 1240 */
1301 opp-624000000 1241 opp-624000000 {
1302 opp-h 1242 opp-hz = /bits/ 64 <624000000>;
1303 opp-s 1243 opp-supported-hw = <0x09>;
1304 }; 1244 };
1305 opp-560000000 1245 opp-560000000 {
1306 opp-h 1246 opp-hz = /bits/ 64 <560000000>;
1307 opp-s 1247 opp-supported-hw = <0x0d>;
1308 }; 1248 };
1309 opp-510000000 1249 opp-510000000 {
1310 opp-h 1250 opp-hz = /bits/ 64 <510000000>;
1311 opp-s !! 1251 opp-supported-hw = <0xFF>;
1312 }; 1252 };
1313 opp-401800000 1253 opp-401800000 {
1314 opp-h 1254 opp-hz = /bits/ 64 <401800000>;
1315 opp-s !! 1255 opp-supported-hw = <0xFF>;
1316 }; 1256 };
1317 opp-315000000 1257 opp-315000000 {
1318 opp-h 1258 opp-hz = /bits/ 64 <315000000>;
1319 opp-s !! 1259 opp-supported-hw = <0xFF>;
1320 }; 1260 };
1321 opp-214000000 1261 opp-214000000 {
1322 opp-h 1262 opp-hz = /bits/ 64 <214000000>;
1323 opp-s !! 1263 opp-supported-hw = <0xFF>;
1324 }; 1264 };
1325 opp-133000000 1265 opp-133000000 {
1326 opp-h 1266 opp-hz = /bits/ 64 <133000000>;
1327 opp-s !! 1267 opp-supported-hw = <0xFF>;
1328 }; 1268 };
1329 }; 1269 };
1330 1270
1331 zap-shader { 1271 zap-shader {
1332 memory-region 1272 memory-region = <&gpu_mem>;
1333 }; 1273 };
1334 }; 1274 };
1335 1275
1336 tlmm: pinctrl@1010000 { 1276 tlmm: pinctrl@1010000 {
1337 compatible = "qcom,ms 1277 compatible = "qcom,msm8996-pinctrl";
1338 reg = <0x01010000 0x3 1278 reg = <0x01010000 0x300000>;
1339 interrupts = <GIC_SPI 1279 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1340 gpio-controller; 1280 gpio-controller;
1341 gpio-ranges = <&tlmm 1281 gpio-ranges = <&tlmm 0 0 150>;
1342 #gpio-cells = <2>; 1282 #gpio-cells = <2>;
1343 interrupt-controller; 1283 interrupt-controller;
1344 #interrupt-cells = <2 1284 #interrupt-cells = <2>;
1345 1285
1346 blsp1_spi1_default: b 1286 blsp1_spi1_default: blsp1-spi1-default-state {
1347 spi-pins { 1287 spi-pins {
1348 pins 1288 pins = "gpio0", "gpio1", "gpio3";
1349 funct 1289 function = "blsp_spi1";
1350 drive 1290 drive-strength = <12>;
1351 bias- 1291 bias-disable;
1352 }; 1292 };
1353 1293
1354 cs-pins { 1294 cs-pins {
1355 pins 1295 pins = "gpio2";
1356 funct 1296 function = "gpio";
1357 drive 1297 drive-strength = <16>;
1358 bias- 1298 bias-disable;
1359 outpu 1299 output-high;
1360 }; 1300 };
1361 }; 1301 };
1362 1302
1363 blsp1_spi1_sleep: bls 1303 blsp1_spi1_sleep: blsp1-spi1-sleep-state {
1364 pins = "gpio0 1304 pins = "gpio0", "gpio1", "gpio2", "gpio3";
1365 function = "g 1305 function = "gpio";
1366 drive-strengt 1306 drive-strength = <2>;
1367 bias-pull-dow 1307 bias-pull-down;
1368 }; 1308 };
1369 1309
1370 blsp2_uart2_2pins_def 1310 blsp2_uart2_2pins_default: blsp2-uart2-2pins-state {
1371 pins = "gpio4 1311 pins = "gpio4", "gpio5";
1372 function = "b 1312 function = "blsp_uart8";
1373 drive-strengt 1313 drive-strength = <16>;
1374 bias-disable; 1314 bias-disable;
1375 }; 1315 };
1376 1316
1377 blsp2_uart2_2pins_sle 1317 blsp2_uart2_2pins_sleep: blsp2-uart2-2pins-sleep-state {
1378 pins = "gpio4 1318 pins = "gpio4", "gpio5";
1379 function = "g 1319 function = "gpio";
1380 drive-strengt 1320 drive-strength = <2>;
1381 bias-disable; 1321 bias-disable;
1382 }; 1322 };
1383 1323
1384 blsp2_i2c2_default: b 1324 blsp2_i2c2_default: blsp2-i2c2-state {
1385 pins = "gpio6 1325 pins = "gpio6", "gpio7";
1386 function = "b 1326 function = "blsp_i2c8";
1387 drive-strengt 1327 drive-strength = <16>;
1388 bias-disable; 1328 bias-disable;
1389 }; 1329 };
1390 1330
1391 blsp2_i2c2_sleep: bls 1331 blsp2_i2c2_sleep: blsp2-i2c2-sleep-state {
1392 pins = "gpio6 1332 pins = "gpio6", "gpio7";
1393 function = "g 1333 function = "gpio";
1394 drive-strengt 1334 drive-strength = <2>;
1395 bias-disable; 1335 bias-disable;
1396 }; 1336 };
1397 1337
1398 blsp1_i2c6_default: b 1338 blsp1_i2c6_default: blsp1-i2c6-state {
1399 pins = "gpio2 1339 pins = "gpio27", "gpio28";
1400 function = "b 1340 function = "blsp_i2c6";
1401 drive-strengt 1341 drive-strength = <16>;
1402 bias-disable; 1342 bias-disable;
1403 }; 1343 };
1404 1344
1405 blsp1_i2c6_sleep: bls 1345 blsp1_i2c6_sleep: blsp1-i2c6-sleep-state {
1406 pins = "gpio2 1346 pins = "gpio27", "gpio28";
1407 function = "g 1347 function = "gpio";
1408 drive-strengt 1348 drive-strength = <2>;
1409 bias-pull-up; 1349 bias-pull-up;
1410 }; 1350 };
1411 1351
1412 cci0_default: cci0-de 1352 cci0_default: cci0-default-state {
1413 pins = "gpio1 1353 pins = "gpio17", "gpio18";
1414 function = "c 1354 function = "cci_i2c";
1415 drive-strengt 1355 drive-strength = <16>;
1416 bias-disable; 1356 bias-disable;
1417 }; 1357 };
1418 1358
1419 camera0_state_on: 1359 camera0_state_on:
1420 camera_rear_default: 1360 camera_rear_default: camera-rear-default-state {
1421 camera0_mclk: 1361 camera0_mclk: mclk0-pins {
1422 pins 1362 pins = "gpio13";
1423 funct 1363 function = "cam_mclk";
1424 drive 1364 drive-strength = <16>;
1425 bias- 1365 bias-disable;
1426 }; 1366 };
1427 1367
1428 camera0_rst: 1368 camera0_rst: rst-pins {
1429 pins 1369 pins = "gpio25";
1430 funct 1370 function = "gpio";
1431 drive 1371 drive-strength = <16>;
1432 bias- 1372 bias-disable;
1433 }; 1373 };
1434 1374
1435 camera0_pwdn: 1375 camera0_pwdn: pwdn-pins {
1436 pins 1376 pins = "gpio26";
1437 funct 1377 function = "gpio";
1438 drive 1378 drive-strength = <16>;
1439 bias- 1379 bias-disable;
1440 }; 1380 };
1441 }; 1381 };
1442 1382
1443 cci1_default: cci1-de 1383 cci1_default: cci1-default-state {
1444 pins = "gpio1 1384 pins = "gpio19", "gpio20";
1445 function = "c 1385 function = "cci_i2c";
1446 drive-strengt 1386 drive-strength = <16>;
1447 bias-disable; 1387 bias-disable;
1448 }; 1388 };
1449 1389
1450 camera1_state_on: 1390 camera1_state_on:
1451 camera_board_default: 1391 camera_board_default: camera-board-default-state {
1452 mclk1-pins { 1392 mclk1-pins {
1453 pins 1393 pins = "gpio14";
1454 funct 1394 function = "cam_mclk";
1455 drive 1395 drive-strength = <16>;
1456 bias- 1396 bias-disable;
1457 }; 1397 };
1458 1398
1459 pwdn-pins { 1399 pwdn-pins {
1460 pins 1400 pins = "gpio98";
1461 funct 1401 function = "gpio";
1462 drive 1402 drive-strength = <16>;
1463 bias- 1403 bias-disable;
1464 }; 1404 };
1465 1405
1466 rst-pins { 1406 rst-pins {
1467 pins 1407 pins = "gpio104";
1468 funct 1408 function = "gpio";
1469 drive 1409 drive-strength = <16>;
1470 bias- 1410 bias-disable;
1471 }; 1411 };
1472 }; 1412 };
1473 1413
1474 camera2_state_on: 1414 camera2_state_on:
1475 camera_front_default: 1415 camera_front_default: camera-front-default-state {
1476 camera2_mclk: 1416 camera2_mclk: mclk2-pins {
1477 pins 1417 pins = "gpio15";
1478 funct 1418 function = "cam_mclk";
1479 drive 1419 drive-strength = <16>;
1480 bias- 1420 bias-disable;
1481 }; 1421 };
1482 1422
1483 camera2_rst: 1423 camera2_rst: rst-pins {
1484 pins 1424 pins = "gpio23";
1485 funct 1425 function = "gpio";
1486 drive 1426 drive-strength = <16>;
1487 bias- 1427 bias-disable;
1488 }; 1428 };
1489 1429
1490 pwdn-pins { 1430 pwdn-pins {
1491 pins 1431 pins = "gpio133";
1492 funct 1432 function = "gpio";
1493 drive 1433 drive-strength = <16>;
1494 bias- 1434 bias-disable;
1495 }; 1435 };
1496 }; 1436 };
1497 1437
1498 pcie0_state_on: pcie0 1438 pcie0_state_on: pcie0-state-on-state {
1499 perst-pins { 1439 perst-pins {
1500 pins 1440 pins = "gpio35";
1501 funct 1441 function = "gpio";
1502 drive 1442 drive-strength = <2>;
1503 bias- 1443 bias-pull-down;
1504 }; 1444 };
1505 1445
1506 clkreq-pins { 1446 clkreq-pins {
1507 pins 1447 pins = "gpio36";
1508 funct 1448 function = "pci_e0";
1509 drive 1449 drive-strength = <2>;
1510 bias- 1450 bias-pull-up;
1511 }; 1451 };
1512 1452
1513 wake-pins { 1453 wake-pins {
1514 pins 1454 pins = "gpio37";
1515 funct 1455 function = "gpio";
1516 drive 1456 drive-strength = <2>;
1517 bias- 1457 bias-pull-up;
1518 }; 1458 };
1519 }; 1459 };
1520 1460
1521 pcie0_state_off: pcie 1461 pcie0_state_off: pcie0-state-off-state {
1522 perst-pins { 1462 perst-pins {
1523 pins 1463 pins = "gpio35";
1524 funct 1464 function = "gpio";
1525 drive 1465 drive-strength = <2>;
1526 bias- 1466 bias-pull-down;
1527 }; 1467 };
1528 1468
1529 clkreq-pins { 1469 clkreq-pins {
1530 pins 1470 pins = "gpio36";
1531 funct 1471 function = "gpio";
1532 drive 1472 drive-strength = <2>;
1533 bias- 1473 bias-disable;
1534 }; 1474 };
1535 1475
1536 wake-pins { 1476 wake-pins {
1537 pins 1477 pins = "gpio37";
1538 funct 1478 function = "gpio";
1539 drive 1479 drive-strength = <2>;
1540 bias- 1480 bias-disable;
1541 }; 1481 };
1542 }; 1482 };
1543 1483
1544 blsp1_uart2_default: 1484 blsp1_uart2_default: blsp1-uart2-default-state {
1545 pins = "gpio4 1485 pins = "gpio41", "gpio42", "gpio43", "gpio44";
1546 function = "b 1486 function = "blsp_uart2";
1547 drive-strengt 1487 drive-strength = <16>;
1548 bias-disable; 1488 bias-disable;
1549 }; 1489 };
1550 1490
1551 blsp1_uart2_sleep: bl 1491 blsp1_uart2_sleep: blsp1-uart2-sleep-state {
1552 pins = "gpio4 1492 pins = "gpio41", "gpio42", "gpio43", "gpio44";
1553 function = "g 1493 function = "gpio";
1554 drive-strengt 1494 drive-strength = <2>;
1555 bias-disable; 1495 bias-disable;
1556 }; 1496 };
1557 1497
1558 blsp1_i2c3_default: b 1498 blsp1_i2c3_default: blsp1-i2c3-default-state {
1559 pins = "gpio4 1499 pins = "gpio47", "gpio48";
1560 function = "b 1500 function = "blsp_i2c3";
1561 drive-strengt 1501 drive-strength = <16>;
1562 bias-disable; 1502 bias-disable;
1563 }; 1503 };
1564 1504
1565 blsp1_i2c3_sleep: bls 1505 blsp1_i2c3_sleep: blsp1-i2c3-sleep-state {
1566 pins = "gpio4 1506 pins = "gpio47", "gpio48";
1567 function = "g 1507 function = "gpio";
1568 drive-strengt 1508 drive-strength = <2>;
1569 bias-disable; 1509 bias-disable;
1570 }; 1510 };
1571 1511
1572 blsp2_uart3_4pins_def 1512 blsp2_uart3_4pins_default: blsp2-uart3-4pins-state {
1573 pins = "gpio4 1513 pins = "gpio49", "gpio50", "gpio51", "gpio52";
1574 function = "b 1514 function = "blsp_uart9";
1575 drive-strengt 1515 drive-strength = <16>;
1576 bias-disable; 1516 bias-disable;
1577 }; 1517 };
1578 1518
1579 blsp2_uart3_4pins_sle 1519 blsp2_uart3_4pins_sleep: blsp2-uart3-4pins-sleep-state {
1580 pins = "gpio4 1520 pins = "gpio49", "gpio50", "gpio51", "gpio52";
1581 function = "b 1521 function = "blsp_uart9";
1582 drive-strengt 1522 drive-strength = <2>;
1583 bias-disable; 1523 bias-disable;
1584 }; 1524 };
1585 1525
1586 blsp2_i2c3_default: b 1526 blsp2_i2c3_default: blsp2-i2c3-state-state {
1587 pins = "gpio5 1527 pins = "gpio51", "gpio52";
1588 function = "b 1528 function = "blsp_i2c9";
1589 drive-strengt 1529 drive-strength = <16>;
1590 bias-disable; 1530 bias-disable;
1591 }; 1531 };
1592 1532
1593 blsp2_i2c3_sleep: bls 1533 blsp2_i2c3_sleep: blsp2-i2c3-sleep-state {
1594 pins = "gpio5 1534 pins = "gpio51", "gpio52";
1595 function = "g 1535 function = "gpio";
1596 drive-strengt 1536 drive-strength = <2>;
1597 bias-disable; 1537 bias-disable;
1598 }; 1538 };
1599 1539
1600 wcd_intr_default: wcd 1540 wcd_intr_default: wcd-intr-default-state {
1601 pins = "gpio5 1541 pins = "gpio54";
1602 function = "g 1542 function = "gpio";
1603 drive-strengt 1543 drive-strength = <2>;
1604 bias-pull-dow 1544 bias-pull-down;
>> 1545 input-enable;
1605 }; 1546 };
1606 1547
1607 blsp2_i2c1_default: b 1548 blsp2_i2c1_default: blsp2-i2c1-state {
1608 pins = "gpio5 1549 pins = "gpio55", "gpio56";
1609 function = "b 1550 function = "blsp_i2c7";
1610 drive-strengt 1551 drive-strength = <16>;
1611 bias-disable; 1552 bias-disable;
1612 }; 1553 };
1613 1554
1614 blsp2_i2c1_sleep: bls 1555 blsp2_i2c1_sleep: blsp2-i2c1-sleep-state {
1615 pins = "gpio5 1556 pins = "gpio55", "gpio56";
1616 function = "g 1557 function = "gpio";
1617 drive-strengt 1558 drive-strength = <2>;
1618 bias-disable; 1559 bias-disable;
1619 }; 1560 };
1620 1561
1621 blsp2_i2c5_default: b 1562 blsp2_i2c5_default: blsp2-i2c5-state {
1622 pins = "gpio6 1563 pins = "gpio60", "gpio61";
1623 function = "b 1564 function = "blsp_i2c11";
1624 drive-strengt 1565 drive-strength = <2>;
1625 bias-disable; 1566 bias-disable;
1626 }; 1567 };
1627 1568
1628 /* Sleep state for BL 1569 /* Sleep state for BLSP2_I2C5 is missing.. */
1629 1570
1630 cdc_reset_active: cdc 1571 cdc_reset_active: cdc-reset-active-state {
1631 pins = "gpio6 1572 pins = "gpio64";
1632 function = "g 1573 function = "gpio";
1633 drive-strengt 1574 drive-strength = <16>;
1634 bias-pull-dow 1575 bias-pull-down;
1635 output-high; 1576 output-high;
1636 }; 1577 };
1637 1578
1638 cdc_reset_sleep: cdc- 1579 cdc_reset_sleep: cdc-reset-sleep-state {
1639 pins = "gpio6 1580 pins = "gpio64";
1640 function = "g 1581 function = "gpio";
1641 drive-strengt 1582 drive-strength = <16>;
1642 bias-disable; 1583 bias-disable;
1643 output-low; 1584 output-low;
1644 }; 1585 };
1645 1586
1646 blsp2_spi6_default: b 1587 blsp2_spi6_default: blsp2-spi6-default-state {
1647 spi-pins { 1588 spi-pins {
1648 pins 1589 pins = "gpio85", "gpio86", "gpio88";
1649 funct 1590 function = "blsp_spi12";
1650 drive 1591 drive-strength = <12>;
1651 bias- 1592 bias-disable;
1652 }; 1593 };
1653 1594
1654 cs-pins { 1595 cs-pins {
1655 pins 1596 pins = "gpio87";
1656 funct 1597 function = "gpio";
1657 drive 1598 drive-strength = <16>;
1658 bias- 1599 bias-disable;
1659 outpu 1600 output-high;
1660 }; 1601 };
1661 }; 1602 };
1662 1603
1663 blsp2_spi6_sleep: bls 1604 blsp2_spi6_sleep: blsp2-spi6-sleep-state {
1664 pins = "gpio8 1605 pins = "gpio85", "gpio86", "gpio87", "gpio88";
1665 function = "g 1606 function = "gpio";
1666 drive-strengt 1607 drive-strength = <2>;
1667 bias-pull-dow 1608 bias-pull-down;
1668 }; 1609 };
1669 1610
1670 blsp2_i2c6_default: b 1611 blsp2_i2c6_default: blsp2-i2c6-state {
1671 pins = "gpio8 1612 pins = "gpio87", "gpio88";
1672 function = "b 1613 function = "blsp_i2c12";
1673 drive-strengt 1614 drive-strength = <16>;
1674 bias-disable; 1615 bias-disable;
1675 }; 1616 };
1676 1617
1677 blsp2_i2c6_sleep: bls 1618 blsp2_i2c6_sleep: blsp2-i2c6-sleep-state {
1678 pins = "gpio8 1619 pins = "gpio87", "gpio88";
1679 function = "g 1620 function = "gpio";
1680 drive-strengt 1621 drive-strength = <2>;
1681 bias-disable; 1622 bias-disable;
1682 }; 1623 };
1683 1624
1684 pcie1_state_on: pcie1 1625 pcie1_state_on: pcie1-on-state {
1685 perst-pins { 1626 perst-pins {
1686 pins 1627 pins = "gpio130";
1687 funct 1628 function = "gpio";
1688 drive 1629 drive-strength = <2>;
1689 bias- 1630 bias-pull-down;
1690 }; 1631 };
1691 1632
1692 clkreq-pins { 1633 clkreq-pins {
1693 pins 1634 pins = "gpio131";
1694 funct 1635 function = "pci_e1";
1695 drive 1636 drive-strength = <2>;
1696 bias- 1637 bias-pull-up;
1697 }; 1638 };
1698 1639
1699 wake-pins { 1640 wake-pins {
1700 pins 1641 pins = "gpio132";
1701 funct 1642 function = "gpio";
1702 drive 1643 drive-strength = <2>;
1703 bias- 1644 bias-pull-down;
1704 }; 1645 };
1705 }; 1646 };
1706 1647
1707 pcie1_state_off: pcie 1648 pcie1_state_off: pcie1-off-state {
1708 /* Perst is m 1649 /* Perst is missing? */
1709 clkreq-pins { 1650 clkreq-pins {
1710 pins 1651 pins = "gpio131";
1711 funct 1652 function = "gpio";
1712 drive 1653 drive-strength = <2>;
1713 bias- 1654 bias-disable;
1714 }; 1655 };
1715 1656
1716 wake-pins { 1657 wake-pins {
1717 pins 1658 pins = "gpio132";
1718 funct 1659 function = "gpio";
1719 drive 1660 drive-strength = <2>;
1720 bias- 1661 bias-disable;
1721 }; 1662 };
1722 }; 1663 };
1723 1664
1724 pcie2_state_on: pcie2 1665 pcie2_state_on: pcie2-on-state {
1725 perst-pins { 1666 perst-pins {
1726 pins 1667 pins = "gpio114";
1727 funct 1668 function = "gpio";
1728 drive 1669 drive-strength = <2>;
1729 bias- 1670 bias-pull-down;
1730 }; 1671 };
1731 1672
1732 clkreq-pins { 1673 clkreq-pins {
1733 pins 1674 pins = "gpio115";
1734 funct 1675 function = "pci_e2";
1735 drive 1676 drive-strength = <2>;
1736 bias- 1677 bias-pull-up;
1737 }; 1678 };
1738 1679
1739 wake-pins { 1680 wake-pins {
1740 pins 1681 pins = "gpio116";
1741 funct 1682 function = "gpio";
1742 drive 1683 drive-strength = <2>;
1743 bias- 1684 bias-pull-down;
1744 }; 1685 };
1745 }; 1686 };
1746 1687
1747 pcie2_state_off: pcie 1688 pcie2_state_off: pcie2-off-state {
1748 /* Perst is m 1689 /* Perst is missing? */
1749 clkreq-pins { 1690 clkreq-pins {
1750 pins 1691 pins = "gpio115";
1751 funct 1692 function = "gpio";
1752 drive 1693 drive-strength = <2>;
1753 bias- 1694 bias-disable;
1754 }; 1695 };
1755 1696
1756 wake-pins { 1697 wake-pins {
1757 pins 1698 pins = "gpio116";
1758 funct 1699 function = "gpio";
1759 drive 1700 drive-strength = <2>;
1760 bias- 1701 bias-disable;
1761 }; 1702 };
1762 }; 1703 };
1763 1704
1764 sdc1_state_on: sdc1-o 1705 sdc1_state_on: sdc1-on-state {
1765 clk-pins { 1706 clk-pins {
1766 pins 1707 pins = "sdc1_clk";
1767 bias- 1708 bias-disable;
1768 drive 1709 drive-strength = <16>;
1769 }; 1710 };
1770 1711
1771 cmd-pins { 1712 cmd-pins {
1772 pins 1713 pins = "sdc1_cmd";
1773 bias- 1714 bias-pull-up;
1774 drive 1715 drive-strength = <10>;
1775 }; 1716 };
1776 1717
1777 data-pins { 1718 data-pins {
1778 pins 1719 pins = "sdc1_data";
1779 bias- 1720 bias-pull-up;
1780 drive 1721 drive-strength = <10>;
1781 }; 1722 };
1782 1723
1783 rclk-pins { 1724 rclk-pins {
1784 pins 1725 pins = "sdc1_rclk";
1785 bias- 1726 bias-pull-down;
1786 }; 1727 };
1787 }; 1728 };
1788 1729
1789 sdc1_state_off: sdc1- 1730 sdc1_state_off: sdc1-off-state {
1790 clk-pins { 1731 clk-pins {
1791 pins 1732 pins = "sdc1_clk";
1792 bias- 1733 bias-disable;
1793 drive 1734 drive-strength = <2>;
1794 }; 1735 };
1795 1736
1796 cmd-pins { 1737 cmd-pins {
1797 pins 1738 pins = "sdc1_cmd";
1798 bias- 1739 bias-pull-up;
1799 drive 1740 drive-strength = <2>;
1800 }; 1741 };
1801 1742
1802 data-pins { 1743 data-pins {
1803 pins 1744 pins = "sdc1_data";
1804 bias- 1745 bias-pull-up;
1805 drive 1746 drive-strength = <2>;
1806 }; 1747 };
1807 1748
1808 rclk-pins { 1749 rclk-pins {
1809 pins 1750 pins = "sdc1_rclk";
1810 bias- 1751 bias-pull-down;
1811 }; 1752 };
1812 }; 1753 };
1813 1754
1814 sdc2_state_on: sdc2-o 1755 sdc2_state_on: sdc2-on-state {
1815 clk-pins { 1756 clk-pins {
1816 pins 1757 pins = "sdc2_clk";
1817 bias- 1758 bias-disable;
1818 drive 1759 drive-strength = <16>;
1819 }; 1760 };
1820 1761
1821 cmd-pins { 1762 cmd-pins {
1822 pins 1763 pins = "sdc2_cmd";
1823 bias- 1764 bias-pull-up;
1824 drive 1765 drive-strength = <10>;
1825 }; 1766 };
1826 1767
1827 data-pins { 1768 data-pins {
1828 pins 1769 pins = "sdc2_data";
1829 bias- 1770 bias-pull-up;
1830 drive 1771 drive-strength = <10>;
1831 }; 1772 };
1832 }; 1773 };
1833 1774
1834 sdc2_state_off: sdc2- 1775 sdc2_state_off: sdc2-off-state {
1835 clk-pins { 1776 clk-pins {
1836 pins 1777 pins = "sdc2_clk";
1837 bias- 1778 bias-disable;
1838 drive 1779 drive-strength = <2>;
1839 }; 1780 };
1840 1781
1841 cmd-pins { 1782 cmd-pins {
1842 pins 1783 pins = "sdc2_cmd";
1843 bias- 1784 bias-pull-up;
1844 drive 1785 drive-strength = <2>;
1845 }; 1786 };
1846 1787
1847 data-pins { 1788 data-pins {
1848 pins 1789 pins = "sdc2_data";
1849 bias- 1790 bias-pull-up;
1850 drive 1791 drive-strength = <2>;
1851 }; 1792 };
1852 }; 1793 };
1853 }; 1794 };
1854 1795
1855 sram@290000 { 1796 sram@290000 {
1856 compatible = "qcom,rp 1797 compatible = "qcom,rpm-stats";
1857 reg = <0x00290000 0x1 1798 reg = <0x00290000 0x10000>;
1858 }; 1799 };
1859 1800
1860 spmi_bus: spmi@400f000 { 1801 spmi_bus: spmi@400f000 {
1861 compatible = "qcom,sp 1802 compatible = "qcom,spmi-pmic-arb";
1862 reg = <0x0400f000 0x1 1803 reg = <0x0400f000 0x1000>,
1863 <0x04400000 0x8 1804 <0x04400000 0x800000>,
1864 <0x04c00000 0x8 1805 <0x04c00000 0x800000>,
1865 <0x05800000 0x2 1806 <0x05800000 0x200000>,
1866 <0x0400a000 0x0 1807 <0x0400a000 0x002100>;
1867 reg-names = "core", " 1808 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1868 interrupt-names = "pe 1809 interrupt-names = "periph_irq";
1869 interrupts = <GIC_SPI 1810 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
1870 qcom,ee = <0>; 1811 qcom,ee = <0>;
1871 qcom,channel = <0>; 1812 qcom,channel = <0>;
1872 #address-cells = <2>; 1813 #address-cells = <2>;
1873 #size-cells = <0>; 1814 #size-cells = <0>;
1874 interrupt-controller; 1815 interrupt-controller;
1875 #interrupt-cells = <4 1816 #interrupt-cells = <4>;
1876 }; 1817 };
1877 1818
1878 bus@0 { !! 1819 agnoc@0 {
1879 power-domains = <&gcc 1820 power-domains = <&gcc AGGRE0_NOC_GDSC>;
1880 compatible = "simple- 1821 compatible = "simple-pm-bus";
1881 #address-cells = <1>; 1822 #address-cells = <1>;
1882 #size-cells = <1>; 1823 #size-cells = <1>;
1883 ranges = <0x0 0x0 0xf !! 1824 ranges;
1884 1825
1885 pcie0: pcie@600000 { 1826 pcie0: pcie@600000 {
1886 compatible = 1827 compatible = "qcom,pcie-msm8996";
1887 status = "dis 1828 status = "disabled";
1888 power-domains 1829 power-domains = <&gcc PCIE0_GDSC>;
1889 bus-range = < 1830 bus-range = <0x00 0xff>;
1890 num-lanes = < 1831 num-lanes = <1>;
1891 1832
1892 reg = <0x0060 1833 reg = <0x00600000 0x2000>,
1893 <0x0c00 1834 <0x0c000000 0xf1d>,
1894 <0x0c00 1835 <0x0c000f20 0xa8>,
1895 <0x0c10 1836 <0x0c100000 0x100000>;
1896 reg-names = " 1837 reg-names = "parf", "dbi", "elbi","config";
1897 1838
1898 phys = <&pcie 1839 phys = <&pciephy_0>;
1899 phy-names = " 1840 phy-names = "pciephy";
1900 1841
1901 #address-cell 1842 #address-cells = <3>;
1902 #size-cells = 1843 #size-cells = <2>;
1903 ranges = <0x0 1844 ranges = <0x01000000 0x0 0x00000000 0x0c200000 0x0 0x100000>,
1904 <0x0 1845 <0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>;
1905 1846
1906 device_type = 1847 device_type = "pci";
1907 1848
1908 interrupts = 1849 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
1909 interrupt-nam 1850 interrupt-names = "msi";
1910 #interrupt-ce 1851 #interrupt-cells = <1>;
1911 interrupt-map 1852 interrupt-map-mask = <0 0 0 0x7>;
1912 interrupt-map 1853 interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1913 1854 <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1914 1855 <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1915 1856 <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1916 1857
1917 pinctrl-names 1858 pinctrl-names = "default", "sleep";
1918 pinctrl-0 = < 1859 pinctrl-0 = <&pcie0_state_on>;
1919 pinctrl-1 = < 1860 pinctrl-1 = <&pcie0_state_off>;
1920 1861
1921 linux,pci-dom 1862 linux,pci-domain = <0>;
1922 1863
1923 clocks = <&gc 1864 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
1924 <&gcc 1865 <&gcc GCC_PCIE_0_AUX_CLK>,
1925 <&gcc 1866 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1926 <&gcc 1867 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1927 <&gcc 1868 <&gcc GCC_PCIE_0_SLV_AXI_CLK>;
1928 1869
1929 clock-names = 1870 clock-names = "pipe",
1930 1871 "aux",
1931 1872 "cfg",
1932 1873 "bus_master",
1933 1874 "bus_slave";
1934 1875
1935 pcie@0 { <<
1936 devic <<
1937 reg = <<
1938 bus-r <<
1939 <<
1940 #addr <<
1941 #size <<
1942 range <<
1943 }; <<
1944 }; 1876 };
1945 1877
1946 pcie1: pcie@608000 { 1878 pcie1: pcie@608000 {
1947 compatible = 1879 compatible = "qcom,pcie-msm8996";
1948 power-domains 1880 power-domains = <&gcc PCIE1_GDSC>;
1949 bus-range = < 1881 bus-range = <0x00 0xff>;
1950 num-lanes = < 1882 num-lanes = <1>;
1951 1883
1952 status = "dis 1884 status = "disabled";
1953 1885
1954 reg = <0x0060 1886 reg = <0x00608000 0x2000>,
1955 <0x0d00 1887 <0x0d000000 0xf1d>,
1956 <0x0d00 1888 <0x0d000f20 0xa8>,
1957 <0x0d10 1889 <0x0d100000 0x100000>;
1958 1890
1959 reg-names = " 1891 reg-names = "parf", "dbi", "elbi","config";
1960 1892
1961 phys = <&pcie 1893 phys = <&pciephy_1>;
1962 phy-names = " 1894 phy-names = "pciephy";
1963 1895
1964 #address-cell 1896 #address-cells = <3>;
1965 #size-cells = 1897 #size-cells = <2>;
1966 ranges = <0x0 1898 ranges = <0x01000000 0x0 0x00000000 0x0d200000 0x0 0x100000>,
1967 <0x0 1899 <0x02000000 0x0 0x0d300000 0x0d300000 0x0 0xd00000>;
1968 1900
1969 device_type = 1901 device_type = "pci";
1970 1902
1971 interrupts = 1903 interrupts = <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>;
1972 interrupt-nam 1904 interrupt-names = "msi";
1973 #interrupt-ce 1905 #interrupt-cells = <1>;
1974 interrupt-map 1906 interrupt-map-mask = <0 0 0 0x7>;
1975 interrupt-map 1907 interrupt-map = <0 0 0 1 &intc 0 272 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1976 1908 <0 0 0 2 &intc 0 273 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1977 1909 <0 0 0 3 &intc 0 274 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1978 1910 <0 0 0 4 &intc 0 275 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1979 1911
1980 pinctrl-names 1912 pinctrl-names = "default", "sleep";
1981 pinctrl-0 = < 1913 pinctrl-0 = <&pcie1_state_on>;
1982 pinctrl-1 = < 1914 pinctrl-1 = <&pcie1_state_off>;
1983 1915
1984 linux,pci-dom 1916 linux,pci-domain = <1>;
1985 1917
1986 clocks = <&gc 1918 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
1987 <&gcc 1919 <&gcc GCC_PCIE_1_AUX_CLK>,
1988 <&gcc 1920 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1989 <&gcc 1921 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
1990 <&gcc 1922 <&gcc GCC_PCIE_1_SLV_AXI_CLK>;
1991 1923
1992 clock-names = 1924 clock-names = "pipe",
1993 1925 "aux",
1994 1926 "cfg",
1995 1927 "bus_master",
1996 1928 "bus_slave";
1997 <<
1998 pcie@0 { <<
1999 devic <<
2000 reg = <<
2001 bus-r <<
2002 <<
2003 #addr <<
2004 #size <<
2005 range <<
2006 }; <<
2007 }; 1929 };
2008 1930
2009 pcie2: pcie@610000 { 1931 pcie2: pcie@610000 {
2010 compatible = 1932 compatible = "qcom,pcie-msm8996";
2011 power-domains 1933 power-domains = <&gcc PCIE2_GDSC>;
2012 bus-range = < 1934 bus-range = <0x00 0xff>;
2013 num-lanes = < 1935 num-lanes = <1>;
2014 status = "dis 1936 status = "disabled";
2015 reg = <0x0061 1937 reg = <0x00610000 0x2000>,
2016 <0x0e00 1938 <0x0e000000 0xf1d>,
2017 <0x0e00 1939 <0x0e000f20 0xa8>,
2018 <0x0e10 1940 <0x0e100000 0x100000>;
2019 1941
2020 reg-names = " 1942 reg-names = "parf", "dbi", "elbi","config";
2021 1943
2022 phys = <&pcie 1944 phys = <&pciephy_2>;
2023 phy-names = " 1945 phy-names = "pciephy";
2024 1946
2025 #address-cell 1947 #address-cells = <3>;
2026 #size-cells = 1948 #size-cells = <2>;
2027 ranges = <0x0 1949 ranges = <0x01000000 0x0 0x00000000 0x0e200000 0x0 0x100000>,
2028 <0x0 1950 <0x02000000 0x0 0x0e300000 0x0e300000 0x0 0x1d00000>;
2029 1951
2030 device_type = 1952 device_type = "pci";
2031 1953
2032 interrupts = 1954 interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
2033 interrupt-nam 1955 interrupt-names = "msi";
2034 #interrupt-ce 1956 #interrupt-cells = <1>;
2035 interrupt-map 1957 interrupt-map-mask = <0 0 0 0x7>;
2036 interrupt-map 1958 interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2037 1959 <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2038 1960 <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2039 1961 <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2040 1962
2041 pinctrl-names 1963 pinctrl-names = "default", "sleep";
2042 pinctrl-0 = < 1964 pinctrl-0 = <&pcie2_state_on>;
2043 pinctrl-1 = < 1965 pinctrl-1 = <&pcie2_state_off>;
2044 1966
2045 linux,pci-dom 1967 linux,pci-domain = <2>;
2046 clocks = <&gc 1968 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,
2047 <&gcc 1969 <&gcc GCC_PCIE_2_AUX_CLK>,
2048 <&gcc 1970 <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
2049 <&gcc 1971 <&gcc GCC_PCIE_2_MSTR_AXI_CLK>,
2050 <&gcc 1972 <&gcc GCC_PCIE_2_SLV_AXI_CLK>;
2051 1973
2052 clock-names = 1974 clock-names = "pipe",
2053 1975 "aux",
2054 1976 "cfg",
2055 1977 "bus_master",
2056 1978 "bus_slave";
2057 <<
2058 pcie@0 { <<
2059 devic <<
2060 reg = <<
2061 bus-r <<
2062 <<
2063 #addr <<
2064 #size <<
2065 range <<
2066 }; <<
2067 }; 1979 };
2068 }; 1980 };
2069 1981
2070 ufshc: ufshc@624000 { 1982 ufshc: ufshc@624000 {
2071 compatible = "qcom,ms 1983 compatible = "qcom,msm8996-ufshc", "qcom,ufshc",
2072 "jedec,u 1984 "jedec,ufs-2.0";
2073 reg = <0x00624000 0x2 1985 reg = <0x00624000 0x2500>;
2074 interrupts = <GIC_SPI 1986 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
2075 1987
2076 phys = <&ufsphy>; !! 1988 phys = <&ufsphy_lane>;
2077 phy-names = "ufsphy"; 1989 phy-names = "ufsphy";
2078 1990
2079 power-domains = <&gcc 1991 power-domains = <&gcc UFS_GDSC>;
2080 1992
2081 clock-names = 1993 clock-names =
>> 1994 "core_clk_src",
2082 "core_clk", 1995 "core_clk",
2083 "bus_clk", 1996 "bus_clk",
2084 "bus_aggr_clk 1997 "bus_aggr_clk",
2085 "iface_clk", 1998 "iface_clk",
>> 1999 "core_clk_unipro_src",
2086 "core_clk_uni 2000 "core_clk_unipro",
2087 "core_clk_ice 2001 "core_clk_ice",
2088 "ref_clk", 2002 "ref_clk",
2089 "tx_lane0_syn 2003 "tx_lane0_sync_clk",
2090 "rx_lane0_syn 2004 "rx_lane0_sync_clk";
2091 clocks = 2005 clocks =
>> 2006 <&gcc UFS_AXI_CLK_SRC>,
2092 <&gcc GCC_UFS 2007 <&gcc GCC_UFS_AXI_CLK>,
2093 <&gcc GCC_SYS 2008 <&gcc GCC_SYS_NOC_UFS_AXI_CLK>,
2094 <&gcc GCC_AGG 2009 <&gcc GCC_AGGRE2_UFS_AXI_CLK>,
2095 <&gcc GCC_UFS 2010 <&gcc GCC_UFS_AHB_CLK>,
>> 2011 <&gcc UFS_ICE_CORE_CLK_SRC>,
2096 <&gcc GCC_UFS 2012 <&gcc GCC_UFS_UNIPRO_CORE_CLK>,
2097 <&gcc GCC_UFS 2013 <&gcc GCC_UFS_ICE_CORE_CLK>,
2098 <&rpmcc RPM_S 2014 <&rpmcc RPM_SMD_LN_BB_CLK>,
2099 <&gcc GCC_UFS 2015 <&gcc GCC_UFS_TX_SYMBOL_0_CLK>,
2100 <&gcc GCC_UFS 2016 <&gcc GCC_UFS_RX_SYMBOL_0_CLK>;
2101 freq-table-hz = 2017 freq-table-hz =
2102 <100000000 20 2018 <100000000 200000000>,
2103 <0 0>, 2019 <0 0>,
2104 <0 0>, 2020 <0 0>,
2105 <0 0>, 2021 <0 0>,
2106 <75000000 150 !! 2022 <0 0>,
2107 <150000000 30 2023 <150000000 300000000>,
2108 <0 0>, 2024 <0 0>,
2109 <0 0>, 2025 <0 0>,
>> 2026 <0 0>,
>> 2027 <0 0>,
2110 <0 0>; 2028 <0 0>;
2111 2029
2112 interconnects = <&a2n <<
2113 <&bim <<
2114 interconnect-names = <<
2115 <<
2116 lanes-per-direction = 2030 lanes-per-direction = <1>;
2117 #reset-cells = <1>; 2031 #reset-cells = <1>;
2118 status = "disabled"; 2032 status = "disabled";
2119 }; 2033 };
2120 2034
2121 ufsphy: phy@627000 { 2035 ufsphy: phy@627000 {
2122 compatible = "qcom,ms 2036 compatible = "qcom,msm8996-qmp-ufs-phy";
2123 reg = <0x00627000 0x1 !! 2037 reg = <0x00627000 0x1c4>;
>> 2038 #address-cells = <1>;
>> 2039 #size-cells = <1>;
>> 2040 ranges;
2124 2041
2125 clocks = <&rpmcc RPM_ !! 2042 clocks = <&gcc GCC_UFS_CLKREF_CLK>;
2126 clock-names = "ref", !! 2043 clock-names = "ref";
2127 2044
2128 resets = <&ufshc 0>; 2045 resets = <&ufshc 0>;
2129 reset-names = "ufsphy 2046 reset-names = "ufsphy";
2130 <<
2131 #clock-cells = <1>; <<
2132 #phy-cells = <0>; <<
2133 <<
2134 status = "disabled"; 2047 status = "disabled";
>> 2048
>> 2049 ufsphy_lane: phy@627400 {
>> 2050 reg = <0x627400 0x12c>,
>> 2051 <0x627600 0x200>,
>> 2052 <0x627c00 0x1b4>;
>> 2053 #phy-cells = <0>;
>> 2054 };
2135 }; 2055 };
2136 2056
2137 camss: camss@a34000 { !! 2057 camss: camss@a00000 {
2138 compatible = "qcom,ms 2058 compatible = "qcom,msm8996-camss";
2139 reg = <0x00a34000 0x1 2059 reg = <0x00a34000 0x1000>,
2140 <0x00a00030 0x4 2060 <0x00a00030 0x4>,
2141 <0x00a35000 0x1 2061 <0x00a35000 0x1000>,
2142 <0x00a00038 0x4 2062 <0x00a00038 0x4>,
2143 <0x00a36000 0x1 2063 <0x00a36000 0x1000>,
2144 <0x00a00040 0x4 2064 <0x00a00040 0x4>,
2145 <0x00a30000 0x1 2065 <0x00a30000 0x100>,
2146 <0x00a30400 0x1 2066 <0x00a30400 0x100>,
2147 <0x00a30800 0x1 2067 <0x00a30800 0x100>,
2148 <0x00a30c00 0x1 2068 <0x00a30c00 0x100>,
2149 <0x00a31000 0x5 2069 <0x00a31000 0x500>,
2150 <0x00a00020 0x1 2070 <0x00a00020 0x10>,
2151 <0x00a10000 0x1 2071 <0x00a10000 0x1000>,
2152 <0x00a14000 0x1 2072 <0x00a14000 0x1000>;
2153 reg-names = "csiphy0" 2073 reg-names = "csiphy0",
2154 "csiphy0_clk_ 2074 "csiphy0_clk_mux",
2155 "csiphy1", 2075 "csiphy1",
2156 "csiphy1_clk_ 2076 "csiphy1_clk_mux",
2157 "csiphy2", 2077 "csiphy2",
2158 "csiphy2_clk_ 2078 "csiphy2_clk_mux",
2159 "csid0", 2079 "csid0",
2160 "csid1", 2080 "csid1",
2161 "csid2", 2081 "csid2",
2162 "csid3", 2082 "csid3",
2163 "ispif", 2083 "ispif",
2164 "csi_clk_mux" 2084 "csi_clk_mux",
2165 "vfe0", 2085 "vfe0",
2166 "vfe1"; 2086 "vfe1";
2167 interrupts = <GIC_SPI 2087 interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
2168 <GIC_SPI 79 I 2088 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
2169 <GIC_SPI 80 I 2089 <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>,
2170 <GIC_SPI 296 2090 <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>,
2171 <GIC_SPI 297 2091 <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>,
2172 <GIC_SPI 298 2092 <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>,
2173 <GIC_SPI 299 2093 <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>,
2174 <GIC_SPI 309 2094 <GIC_SPI 309 IRQ_TYPE_EDGE_RISING>,
2175 <GIC_SPI 314 2095 <GIC_SPI 314 IRQ_TYPE_EDGE_RISING>,
2176 <GIC_SPI 315 2096 <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>;
2177 interrupt-names = "cs 2097 interrupt-names = "csiphy0",
2178 "csiphy1", 2098 "csiphy1",
2179 "csiphy2", 2099 "csiphy2",
2180 "csid0", 2100 "csid0",
2181 "csid1", 2101 "csid1",
2182 "csid2", 2102 "csid2",
2183 "csid3", 2103 "csid3",
2184 "ispif", 2104 "ispif",
2185 "vfe0", 2105 "vfe0",
2186 "vfe1"; 2106 "vfe1";
2187 power-domains = <&mmc 2107 power-domains = <&mmcc VFE0_GDSC>,
2188 <&mmc 2108 <&mmcc VFE1_GDSC>;
2189 clocks = <&mmcc CAMSS 2109 clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
2190 <&mmcc CAMSS_ 2110 <&mmcc CAMSS_ISPIF_AHB_CLK>,
2191 <&mmcc CAMSS_ 2111 <&mmcc CAMSS_CSI0PHYTIMER_CLK>,
2192 <&mmcc CAMSS_ 2112 <&mmcc CAMSS_CSI1PHYTIMER_CLK>,
2193 <&mmcc CAMSS_ 2113 <&mmcc CAMSS_CSI2PHYTIMER_CLK>,
2194 <&mmcc CAMSS_ 2114 <&mmcc CAMSS_CSI0_AHB_CLK>,
2195 <&mmcc CAMSS_ 2115 <&mmcc CAMSS_CSI0_CLK>,
2196 <&mmcc CAMSS_ 2116 <&mmcc CAMSS_CSI0PHY_CLK>,
2197 <&mmcc CAMSS_ 2117 <&mmcc CAMSS_CSI0PIX_CLK>,
2198 <&mmcc CAMSS_ 2118 <&mmcc CAMSS_CSI0RDI_CLK>,
2199 <&mmcc CAMSS_ 2119 <&mmcc CAMSS_CSI1_AHB_CLK>,
2200 <&mmcc CAMSS_ 2120 <&mmcc CAMSS_CSI1_CLK>,
2201 <&mmcc CAMSS_ 2121 <&mmcc CAMSS_CSI1PHY_CLK>,
2202 <&mmcc CAMSS_ 2122 <&mmcc CAMSS_CSI1PIX_CLK>,
2203 <&mmcc CAMSS_ 2123 <&mmcc CAMSS_CSI1RDI_CLK>,
2204 <&mmcc CAMSS_ 2124 <&mmcc CAMSS_CSI2_AHB_CLK>,
2205 <&mmcc CAMSS_ 2125 <&mmcc CAMSS_CSI2_CLK>,
2206 <&mmcc CAMSS_ 2126 <&mmcc CAMSS_CSI2PHY_CLK>,
2207 <&mmcc CAMSS_ 2127 <&mmcc CAMSS_CSI2PIX_CLK>,
2208 <&mmcc CAMSS_ 2128 <&mmcc CAMSS_CSI2RDI_CLK>,
2209 <&mmcc CAMSS_ 2129 <&mmcc CAMSS_CSI3_AHB_CLK>,
2210 <&mmcc CAMSS_ 2130 <&mmcc CAMSS_CSI3_CLK>,
2211 <&mmcc CAMSS_ 2131 <&mmcc CAMSS_CSI3PHY_CLK>,
2212 <&mmcc CAMSS_ 2132 <&mmcc CAMSS_CSI3PIX_CLK>,
2213 <&mmcc CAMSS_ 2133 <&mmcc CAMSS_CSI3RDI_CLK>,
2214 <&mmcc CAMSS_ 2134 <&mmcc CAMSS_AHB_CLK>,
2215 <&mmcc CAMSS_ 2135 <&mmcc CAMSS_VFE0_CLK>,
2216 <&mmcc CAMSS_ 2136 <&mmcc CAMSS_CSI_VFE0_CLK>,
2217 <&mmcc CAMSS_ 2137 <&mmcc CAMSS_VFE0_AHB_CLK>,
2218 <&mmcc CAMSS_ 2138 <&mmcc CAMSS_VFE0_STREAM_CLK>,
2219 <&mmcc CAMSS_ 2139 <&mmcc CAMSS_VFE1_CLK>,
2220 <&mmcc CAMSS_ 2140 <&mmcc CAMSS_CSI_VFE1_CLK>,
2221 <&mmcc CAMSS_ 2141 <&mmcc CAMSS_VFE1_AHB_CLK>,
2222 <&mmcc CAMSS_ 2142 <&mmcc CAMSS_VFE1_STREAM_CLK>,
2223 <&mmcc CAMSS_ 2143 <&mmcc CAMSS_VFE_AHB_CLK>,
2224 <&mmcc CAMSS_ 2144 <&mmcc CAMSS_VFE_AXI_CLK>;
2225 clock-names = "top_ah 2145 clock-names = "top_ahb",
2226 "ispif_ahb", 2146 "ispif_ahb",
2227 "csiphy0_time 2147 "csiphy0_timer",
2228 "csiphy1_time 2148 "csiphy1_timer",
2229 "csiphy2_time 2149 "csiphy2_timer",
2230 "csi0_ahb", 2150 "csi0_ahb",
2231 "csi0", 2151 "csi0",
2232 "csi0_phy", 2152 "csi0_phy",
2233 "csi0_pix", 2153 "csi0_pix",
2234 "csi0_rdi", 2154 "csi0_rdi",
2235 "csi1_ahb", 2155 "csi1_ahb",
2236 "csi1", 2156 "csi1",
2237 "csi1_phy", 2157 "csi1_phy",
2238 "csi1_pix", 2158 "csi1_pix",
2239 "csi1_rdi", 2159 "csi1_rdi",
2240 "csi2_ahb", 2160 "csi2_ahb",
2241 "csi2", 2161 "csi2",
2242 "csi2_phy", 2162 "csi2_phy",
2243 "csi2_pix", 2163 "csi2_pix",
2244 "csi2_rdi", 2164 "csi2_rdi",
2245 "csi3_ahb", 2165 "csi3_ahb",
2246 "csi3", 2166 "csi3",
2247 "csi3_phy", 2167 "csi3_phy",
2248 "csi3_pix", 2168 "csi3_pix",
2249 "csi3_rdi", 2169 "csi3_rdi",
2250 "ahb", 2170 "ahb",
2251 "vfe0", 2171 "vfe0",
2252 "csi_vfe0", 2172 "csi_vfe0",
2253 "vfe0_ahb", 2173 "vfe0_ahb",
2254 "vfe0_stream" 2174 "vfe0_stream",
2255 "vfe1", 2175 "vfe1",
2256 "csi_vfe1", 2176 "csi_vfe1",
2257 "vfe1_ahb", 2177 "vfe1_ahb",
2258 "vfe1_stream" 2178 "vfe1_stream",
2259 "vfe_ahb", 2179 "vfe_ahb",
2260 "vfe_axi"; 2180 "vfe_axi";
2261 iommus = <&vfe_smmu 0 2181 iommus = <&vfe_smmu 0>,
2262 <&vfe_smmu 1 2182 <&vfe_smmu 1>,
2263 <&vfe_smmu 2 2183 <&vfe_smmu 2>,
2264 <&vfe_smmu 3 2184 <&vfe_smmu 3>;
2265 status = "disabled"; 2185 status = "disabled";
2266 ports { 2186 ports {
2267 #address-cell 2187 #address-cells = <1>;
2268 #size-cells = 2188 #size-cells = <0>;
2269 }; 2189 };
2270 }; 2190 };
2271 2191
2272 cci: cci@a0c000 { 2192 cci: cci@a0c000 {
2273 compatible = "qcom,ms 2193 compatible = "qcom,msm8996-cci";
2274 #address-cells = <1>; 2194 #address-cells = <1>;
2275 #size-cells = <0>; 2195 #size-cells = <0>;
2276 reg = <0xa0c000 0x100 2196 reg = <0xa0c000 0x1000>;
2277 interrupts = <GIC_SPI 2197 interrupts = <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>;
2278 power-domains = <&mmc 2198 power-domains = <&mmcc CAMSS_GDSC>;
2279 clocks = <&mmcc CAMSS 2199 clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
2280 <&mmcc CAMSS 2200 <&mmcc CAMSS_CCI_AHB_CLK>,
2281 <&mmcc CAMSS 2201 <&mmcc CAMSS_CCI_CLK>,
2282 <&mmcc CAMSS 2202 <&mmcc CAMSS_AHB_CLK>;
2283 clock-names = "camss_ 2203 clock-names = "camss_top_ahb",
2284 "cci_ah 2204 "cci_ahb",
2285 "cci", 2205 "cci",
2286 "camss_ 2206 "camss_ahb";
2287 assigned-clocks = <&m 2207 assigned-clocks = <&mmcc CAMSS_CCI_AHB_CLK>,
2288 <&m 2208 <&mmcc CAMSS_CCI_CLK>;
2289 assigned-clock-rates 2209 assigned-clock-rates = <80000000>, <37500000>;
2290 pinctrl-names = "defa 2210 pinctrl-names = "default";
2291 pinctrl-0 = <&cci0_de 2211 pinctrl-0 = <&cci0_default &cci1_default>;
2292 status = "disabled"; 2212 status = "disabled";
2293 2213
2294 cci_i2c0: i2c-bus@0 { 2214 cci_i2c0: i2c-bus@0 {
2295 reg = <0>; 2215 reg = <0>;
2296 clock-frequen 2216 clock-frequency = <400000>;
2297 #address-cell 2217 #address-cells = <1>;
2298 #size-cells = 2218 #size-cells = <0>;
2299 }; 2219 };
2300 2220
2301 cci_i2c1: i2c-bus@1 { 2221 cci_i2c1: i2c-bus@1 {
2302 reg = <1>; 2222 reg = <1>;
2303 clock-frequen 2223 clock-frequency = <400000>;
2304 #address-cell 2224 #address-cells = <1>;
2305 #size-cells = 2225 #size-cells = <0>;
2306 }; 2226 };
2307 }; 2227 };
2308 2228
2309 adreno_smmu: iommu@b40000 { 2229 adreno_smmu: iommu@b40000 {
2310 compatible = "qcom,ms 2230 compatible = "qcom,msm8996-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
2311 reg = <0x00b40000 0x1 2231 reg = <0x00b40000 0x10000>;
2312 2232
2313 #global-interrupts = 2233 #global-interrupts = <1>;
2314 interrupts = <GIC_SPI 2234 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
2315 <GIC_SPI 2235 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
2316 <GIC_SPI 2236 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
2317 #iommu-cells = <1>; 2237 #iommu-cells = <1>;
2318 2238
2319 clocks = <&gcc GCC_MM 2239 clocks = <&gcc GCC_MMSS_BIMC_GFX_CLK>,
2320 <&mmcc GPU_A 2240 <&mmcc GPU_AHB_CLK>;
2321 clock-names = "bus", 2241 clock-names = "bus", "iface";
2322 2242
2323 power-domains = <&mmc 2243 power-domains = <&mmcc GPU_GDSC>;
2324 }; 2244 };
2325 2245
2326 venus: video-codec@c00000 { 2246 venus: video-codec@c00000 {
2327 compatible = "qcom,ms 2247 compatible = "qcom,msm8996-venus";
2328 reg = <0x00c00000 0xf 2248 reg = <0x00c00000 0xff000>;
2329 interrupts = <GIC_SPI 2249 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
2330 power-domains = <&mmc 2250 power-domains = <&mmcc VENUS_GDSC>;
2331 clocks = <&mmcc VIDEO 2251 clocks = <&mmcc VIDEO_CORE_CLK>,
2332 <&mmcc VIDEO 2252 <&mmcc VIDEO_AHB_CLK>,
2333 <&mmcc VIDEO 2253 <&mmcc VIDEO_AXI_CLK>,
2334 <&mmcc VIDEO 2254 <&mmcc VIDEO_MAXI_CLK>;
2335 clock-names = "core", 2255 clock-names = "core", "iface", "bus", "mbus";
2336 interconnects = <&mno 2256 interconnects = <&mnoc MASTER_VIDEO_P0 &bimc SLAVE_EBI_CH0>,
2337 <&bim 2257 <&bimc MASTER_AMPSS_M0 &mnoc SLAVE_VENUS_CFG>;
2338 interconnect-names = 2258 interconnect-names = "video-mem", "cpu-cfg";
2339 iommus = <&venus_smmu 2259 iommus = <&venus_smmu 0x00>,
2340 <&venus_smmu 2260 <&venus_smmu 0x01>,
2341 <&venus_smmu 2261 <&venus_smmu 0x0a>,
2342 <&venus_smmu 2262 <&venus_smmu 0x07>,
2343 <&venus_smmu 2263 <&venus_smmu 0x0e>,
2344 <&venus_smmu 2264 <&venus_smmu 0x0f>,
2345 <&venus_smmu 2265 <&venus_smmu 0x08>,
2346 <&venus_smmu 2266 <&venus_smmu 0x09>,
2347 <&venus_smmu 2267 <&venus_smmu 0x0b>,
2348 <&venus_smmu 2268 <&venus_smmu 0x0c>,
2349 <&venus_smmu 2269 <&venus_smmu 0x0d>,
2350 <&venus_smmu 2270 <&venus_smmu 0x10>,
2351 <&venus_smmu 2271 <&venus_smmu 0x11>,
2352 <&venus_smmu 2272 <&venus_smmu 0x21>,
2353 <&venus_smmu 2273 <&venus_smmu 0x28>,
2354 <&venus_smmu 2274 <&venus_smmu 0x29>,
2355 <&venus_smmu 2275 <&venus_smmu 0x2b>,
2356 <&venus_smmu 2276 <&venus_smmu 0x2c>,
2357 <&venus_smmu 2277 <&venus_smmu 0x2d>,
2358 <&venus_smmu 2278 <&venus_smmu 0x31>;
2359 memory-region = <&ven 2279 memory-region = <&venus_mem>;
2360 status = "disabled"; 2280 status = "disabled";
2361 2281
2362 video-decoder { 2282 video-decoder {
2363 compatible = 2283 compatible = "venus-decoder";
2364 clocks = <&mm 2284 clocks = <&mmcc VIDEO_SUBCORE0_CLK>;
2365 clock-names = 2285 clock-names = "core";
2366 power-domains 2286 power-domains = <&mmcc VENUS_CORE0_GDSC>;
2367 }; 2287 };
2368 2288
2369 video-encoder { 2289 video-encoder {
2370 compatible = 2290 compatible = "venus-encoder";
2371 clocks = <&mm 2291 clocks = <&mmcc VIDEO_SUBCORE1_CLK>;
2372 clock-names = 2292 clock-names = "core";
2373 power-domains 2293 power-domains = <&mmcc VENUS_CORE1_GDSC>;
2374 }; 2294 };
2375 }; 2295 };
2376 2296
2377 mdp_smmu: iommu@d00000 { 2297 mdp_smmu: iommu@d00000 {
2378 compatible = "qcom,ms 2298 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2379 reg = <0x00d00000 0x1 2299 reg = <0x00d00000 0x10000>;
2380 2300
2381 #global-interrupts = 2301 #global-interrupts = <1>;
2382 interrupts = <GIC_SPI 2302 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
2383 <GIC_SPI 2303 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
2384 <GIC_SPI 2304 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
2385 #iommu-cells = <1>; 2305 #iommu-cells = <1>;
2386 clocks = <&mmcc SMMU_ 2306 clocks = <&mmcc SMMU_MDP_AXI_CLK>,
2387 <&mmcc SMMU_ 2307 <&mmcc SMMU_MDP_AHB_CLK>;
2388 clock-names = "bus", 2308 clock-names = "bus", "iface";
2389 2309
2390 power-domains = <&mmc 2310 power-domains = <&mmcc MDSS_GDSC>;
2391 }; 2311 };
2392 2312
2393 venus_smmu: iommu@d40000 { 2313 venus_smmu: iommu@d40000 {
2394 compatible = "qcom,ms 2314 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2395 reg = <0x00d40000 0x2 2315 reg = <0x00d40000 0x20000>;
2396 #global-interrupts = 2316 #global-interrupts = <1>;
2397 interrupts = <GIC_SPI 2317 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>,
2398 <GIC_SPI 2318 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
2399 <GIC_SPI 2319 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
2400 <GIC_SPI 2320 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
2401 <GIC_SPI 2321 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
2402 <GIC_SPI 2322 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
2403 <GIC_SPI 2323 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
2404 <GIC_SPI 2324 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
2405 power-domains = <&mmc 2325 power-domains = <&mmcc MMAGIC_VIDEO_GDSC>;
2406 clocks = <&mmcc SMMU_ 2326 clocks = <&mmcc SMMU_VIDEO_AXI_CLK>,
2407 <&mmcc SMMU_ 2327 <&mmcc SMMU_VIDEO_AHB_CLK>;
2408 clock-names = "bus", 2328 clock-names = "bus", "iface";
2409 #iommu-cells = <1>; 2329 #iommu-cells = <1>;
2410 status = "okay"; 2330 status = "okay";
2411 }; 2331 };
2412 2332
2413 vfe_smmu: iommu@da0000 { 2333 vfe_smmu: iommu@da0000 {
2414 compatible = "qcom,ms 2334 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2415 reg = <0x00da0000 0x1 2335 reg = <0x00da0000 0x10000>;
2416 2336
2417 #global-interrupts = 2337 #global-interrupts = <1>;
2418 interrupts = <GIC_SPI 2338 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
2419 <GIC_SPI 2339 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
2420 <GIC_SPI 2340 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
2421 power-domains = <&mmc 2341 power-domains = <&mmcc MMAGIC_CAMSS_GDSC>;
2422 clocks = <&mmcc SMMU_ 2342 clocks = <&mmcc SMMU_VFE_AXI_CLK>,
2423 <&mmcc SMMU_ 2343 <&mmcc SMMU_VFE_AHB_CLK>;
2424 clock-names = "bus", 2344 clock-names = "bus", "iface";
2425 #iommu-cells = <1>; 2345 #iommu-cells = <1>;
2426 }; 2346 };
2427 2347
2428 lpass_q6_smmu: iommu@1600000 2348 lpass_q6_smmu: iommu@1600000 {
2429 compatible = "qcom,ms 2349 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2430 reg = <0x01600000 0x2 2350 reg = <0x01600000 0x20000>;
2431 #iommu-cells = <1>; 2351 #iommu-cells = <1>;
2432 power-domains = <&gcc 2352 power-domains = <&gcc HLOS1_VOTE_LPASS_CORE_GDSC>;
2433 2353
2434 #global-interrupts = 2354 #global-interrupts = <1>;
2435 interrupts = <GIC_SPI 2355 interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
2436 <GIC_SPI 226 2356 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,
2437 <GIC_SPI 393 2357 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
2438 <GIC_SPI 394 2358 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
2439 <GIC_SPI 395 2359 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
2440 <GIC_SPI 396 2360 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
2441 <GIC_SPI 397 2361 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
2442 <GIC_SPI 398 2362 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
2443 <GIC_SPI 399 2363 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
2444 <GIC_SPI 400 2364 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
2445 <GIC_SPI 401 2365 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
2446 <GIC_SPI 402 2366 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
2447 <GIC_SPI 403 2367 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>;
2448 2368
2449 clocks = <&gcc GCC_HL 2369 clocks = <&gcc GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>,
2450 <&gcc GCC_HL 2370 <&gcc GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK>;
2451 clock-names = "bus", 2371 clock-names = "bus", "iface";
2452 }; 2372 };
2453 2373
2454 slpi_pil: remoteproc@1c00000 2374 slpi_pil: remoteproc@1c00000 {
2455 compatible = "qcom,ms 2375 compatible = "qcom,msm8996-slpi-pil";
2456 reg = <0x01c00000 0x4 2376 reg = <0x01c00000 0x4000>;
2457 2377
2458 interrupts-extended = 2378 interrupts-extended = <&intc 0 390 IRQ_TYPE_EDGE_RISING>,
2459 2379 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2460 2380 <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2461 2381 <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2462 2382 <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
2463 interrupt-names = "wd 2383 interrupt-names = "wdog",
2464 "fa 2384 "fatal",
2465 "re 2385 "ready",
2466 "ha 2386 "handover",
2467 "st 2387 "stop-ack";
2468 2388
2469 clocks = <&xo_board>; !! 2389 clocks = <&xo_board>,
2470 clock-names = "xo"; !! 2390 <&rpmcc RPM_SMD_AGGR2_NOC_CLK>;
>> 2391 clock-names = "xo", "aggre2";
2471 2392
2472 memory-region = <&slp 2393 memory-region = <&slpi_mem>;
2473 2394
2474 qcom,smem-states = <& 2395 qcom,smem-states = <&slpi_smp2p_out 0>;
2475 qcom,smem-state-names 2396 qcom,smem-state-names = "stop";
2476 2397
2477 power-domains = <&rpm 2398 power-domains = <&rpmpd MSM8996_VDDSSCX>;
2478 power-domain-names = 2399 power-domain-names = "ssc_cx";
2479 2400
2480 status = "disabled"; 2401 status = "disabled";
2481 2402
2482 glink-edge { <<
2483 interrupts = <<
2484 label = "dsps <<
2485 qcom,remote-p <<
2486 mboxes = <&ap <<
2487 }; <<
2488 <<
2489 smd-edge { 2403 smd-edge {
2490 interrupts = 2404 interrupts = <GIC_SPI 176 IRQ_TYPE_EDGE_RISING>;
2491 2405
2492 label = "dsps 2406 label = "dsps";
2493 mboxes = <&ap 2407 mboxes = <&apcs_glb 25>;
2494 qcom,smd-edge 2408 qcom,smd-edge = <3>;
2495 qcom,remote-p 2409 qcom,remote-pid = <3>;
2496 }; 2410 };
2497 }; 2411 };
2498 2412
2499 mss_pil: remoteproc@2080000 { 2413 mss_pil: remoteproc@2080000 {
2500 compatible = "qcom,ms 2414 compatible = "qcom,msm8996-mss-pil";
2501 reg = <0x2080000 0x10 2415 reg = <0x2080000 0x100>,
2502 <0x2180000 0x02 2416 <0x2180000 0x020>;
2503 reg-names = "qdsp6", 2417 reg-names = "qdsp6", "rmb";
2504 2418
2505 interrupts-extended = 2419 interrupts-extended = <&intc 0 448 IRQ_TYPE_EDGE_RISING>,
2506 2420 <&mpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2507 2421 <&mpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2508 2422 <&mpss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2509 2423 <&mpss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
2510 2424 <&mpss_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
2511 interrupt-names = "wd 2425 interrupt-names = "wdog", "fatal", "ready",
2512 "ha 2426 "handover", "stop-ack",
2513 "sh 2427 "shutdown-ack";
2514 2428
2515 clocks = <&gcc GCC_MS 2429 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
2516 <&gcc GCC_MS 2430 <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>,
2517 <&gcc GCC_BO 2431 <&gcc GCC_BOOT_ROM_AHB_CLK>,
2518 <&xo_board>, 2432 <&xo_board>,
2519 <&gcc GCC_MS 2433 <&gcc GCC_MSS_GPLL0_DIV_CLK>,
2520 <&gcc GCC_MS 2434 <&gcc GCC_MSS_SNOC_AXI_CLK>,
2521 <&gcc GCC_MS 2435 <&gcc GCC_MSS_MNOC_BIMC_AXI_CLK>,
>> 2436 <&rpmcc RPM_SMD_PCNOC_CLK>,
2522 <&rpmcc RPM_ 2437 <&rpmcc RPM_SMD_QDSS_CLK>;
2523 clock-names = "iface" !! 2438 clock-names = "iface", "bus", "mem", "xo", "gpll0_mss",
2524 "bus", !! 2439 "snoc_axi", "mnoc_axi", "pnoc", "qdss";
2525 "mem", <<
2526 "xo", <<
2527 "gpll0_ <<
2528 "snoc_a <<
2529 "mnoc_a <<
2530 "qdss"; <<
2531 2440
2532 resets = <&gcc GCC_MS 2441 resets = <&gcc GCC_MSS_RESTART>;
2533 reset-names = "mss_re 2442 reset-names = "mss_restart";
2534 2443
2535 power-domains = <&rpm 2444 power-domains = <&rpmpd MSM8996_VDDCX>,
2536 <&rpm 2445 <&rpmpd MSM8996_VDDMX>;
2537 power-domain-names = 2446 power-domain-names = "cx", "mx";
2538 2447
2539 qcom,smem-states = <& 2448 qcom,smem-states = <&mpss_smp2p_out 0>;
2540 qcom,smem-state-names 2449 qcom,smem-state-names = "stop";
2541 2450
2542 qcom,halt-regs = <&tc 2451 qcom,halt-regs = <&tcsr_1 0x3000 0x5000 0x4000>;
2543 2452
2544 status = "disabled"; 2453 status = "disabled";
2545 2454
2546 mba { 2455 mba {
2547 memory-region 2456 memory-region = <&mba_mem>;
2548 }; 2457 };
2549 2458
2550 mpss { 2459 mpss {
2551 memory-region 2460 memory-region = <&mpss_mem>;
2552 }; 2461 };
2553 2462
2554 metadata { <<
2555 memory-region <<
2556 }; <<
2557 <<
2558 glink-edge { <<
2559 interrupts = <<
2560 label = "mode <<
2561 qcom,remote-p <<
2562 mboxes = <&ap <<
2563 }; <<
2564 <<
2565 smd-edge { 2463 smd-edge {
2566 interrupts = 2464 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
2567 2465
2568 label = "mpss 2466 label = "mpss";
2569 mboxes = <&ap 2467 mboxes = <&apcs_glb 12>;
2570 qcom,smd-edge 2468 qcom,smd-edge = <0>;
2571 qcom,remote-p 2469 qcom,remote-pid = <1>;
2572 }; 2470 };
2573 }; 2471 };
2574 2472
2575 stm@3002000 { 2473 stm@3002000 {
2576 compatible = "arm,cor 2474 compatible = "arm,coresight-stm", "arm,primecell";
2577 reg = <0x3002000 0x10 2475 reg = <0x3002000 0x1000>,
2578 <0x8280000 0x18 2476 <0x8280000 0x180000>;
2579 reg-names = "stm-base 2477 reg-names = "stm-base", "stm-stimulus-base";
2580 2478
2581 clocks = <&rpmcc RPM_ 2479 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2582 clock-names = "apb_pc 2480 clock-names = "apb_pclk", "atclk";
2583 2481
2584 out-ports { 2482 out-ports {
2585 port { 2483 port {
2586 stm_o 2484 stm_out: endpoint {
2587 2485 remote-endpoint =
2588 2486 <&funnel0_in>;
2589 }; 2487 };
2590 }; 2488 };
2591 }; 2489 };
2592 }; 2490 };
2593 2491
2594 tpiu@3020000 { 2492 tpiu@3020000 {
2595 compatible = "arm,cor 2493 compatible = "arm,coresight-tpiu", "arm,primecell";
2596 reg = <0x3020000 0x10 2494 reg = <0x3020000 0x1000>;
2597 2495
2598 clocks = <&rpmcc RPM_ 2496 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2599 clock-names = "apb_pc 2497 clock-names = "apb_pclk", "atclk";
2600 2498
2601 in-ports { 2499 in-ports {
2602 port { 2500 port {
2603 tpiu_ 2501 tpiu_in: endpoint {
2604 2502 remote-endpoint =
2605 2503 <&replicator_out1>;
2606 }; 2504 };
2607 }; 2505 };
2608 }; 2506 };
2609 }; 2507 };
2610 2508
2611 funnel@3021000 { 2509 funnel@3021000 {
2612 compatible = "arm,cor 2510 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2613 reg = <0x3021000 0x10 2511 reg = <0x3021000 0x1000>;
2614 2512
2615 clocks = <&rpmcc RPM_ 2513 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2616 clock-names = "apb_pc 2514 clock-names = "apb_pclk", "atclk";
2617 2515
2618 in-ports { 2516 in-ports {
2619 #address-cell 2517 #address-cells = <1>;
2620 #size-cells = 2518 #size-cells = <0>;
2621 2519
2622 port@7 { 2520 port@7 {
2623 reg = 2521 reg = <7>;
2624 funne 2522 funnel0_in: endpoint {
2625 2523 remote-endpoint =
2626 2524 <&stm_out>;
2627 }; 2525 };
2628 }; 2526 };
2629 }; 2527 };
2630 2528
2631 out-ports { 2529 out-ports {
2632 port { 2530 port {
2633 funne 2531 funnel0_out: endpoint {
2634 2532 remote-endpoint =
2635 2533 <&merge_funnel_in0>;
2636 }; 2534 };
2637 }; 2535 };
2638 }; 2536 };
2639 }; 2537 };
2640 2538
2641 funnel@3022000 { 2539 funnel@3022000 {
2642 compatible = "arm,cor 2540 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2643 reg = <0x3022000 0x10 2541 reg = <0x3022000 0x1000>;
2644 2542
2645 clocks = <&rpmcc RPM_ 2543 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2646 clock-names = "apb_pc 2544 clock-names = "apb_pclk", "atclk";
2647 2545
2648 in-ports { 2546 in-ports {
2649 #address-cell 2547 #address-cells = <1>;
2650 #size-cells = 2548 #size-cells = <0>;
2651 2549
2652 port@6 { 2550 port@6 {
2653 reg = 2551 reg = <6>;
2654 funne 2552 funnel1_in: endpoint {
2655 2553 remote-endpoint =
2656 2554 <&apss_merge_funnel_out>;
2657 }; 2555 };
2658 }; 2556 };
2659 }; 2557 };
2660 2558
2661 out-ports { 2559 out-ports {
2662 port { 2560 port {
2663 funne 2561 funnel1_out: endpoint {
2664 2562 remote-endpoint =
2665 2563 <&merge_funnel_in1>;
2666 }; 2564 };
2667 }; 2565 };
2668 }; 2566 };
2669 }; 2567 };
2670 2568
2671 funnel@3023000 { 2569 funnel@3023000 {
2672 compatible = "arm,cor 2570 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2673 reg = <0x3023000 0x10 2571 reg = <0x3023000 0x1000>;
2674 2572
2675 clocks = <&rpmcc RPM_ 2573 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2676 clock-names = "apb_pc 2574 clock-names = "apb_pclk", "atclk";
2677 2575
2678 in-ports { <<
2679 port { <<
2680 funne <<
2681 <<
2682 <<
2683 }; <<
2684 }; <<
2685 }; <<
2686 2576
2687 out-ports { 2577 out-ports {
2688 port { 2578 port {
2689 funne 2579 funnel2_out: endpoint {
2690 2580 remote-endpoint =
2691 2581 <&merge_funnel_in2>;
2692 }; 2582 };
2693 }; 2583 };
2694 }; 2584 };
2695 }; 2585 };
2696 2586
2697 funnel@3025000 { 2587 funnel@3025000 {
2698 compatible = "arm,cor 2588 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2699 reg = <0x3025000 0x10 2589 reg = <0x3025000 0x1000>;
2700 2590
2701 clocks = <&rpmcc RPM_ 2591 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2702 clock-names = "apb_pc 2592 clock-names = "apb_pclk", "atclk";
2703 2593
2704 in-ports { 2594 in-ports {
2705 #address-cell 2595 #address-cells = <1>;
2706 #size-cells = 2596 #size-cells = <0>;
2707 2597
2708 port@0 { 2598 port@0 {
2709 reg = 2599 reg = <0>;
2710 merge 2600 merge_funnel_in0: endpoint {
2711 2601 remote-endpoint =
2712 2602 <&funnel0_out>;
2713 }; 2603 };
2714 }; 2604 };
2715 2605
2716 port@1 { 2606 port@1 {
2717 reg = 2607 reg = <1>;
2718 merge 2608 merge_funnel_in1: endpoint {
2719 2609 remote-endpoint =
2720 2610 <&funnel1_out>;
2721 }; 2611 };
2722 }; 2612 };
2723 2613
2724 port@2 { 2614 port@2 {
2725 reg = 2615 reg = <2>;
2726 merge 2616 merge_funnel_in2: endpoint {
2727 2617 remote-endpoint =
2728 2618 <&funnel2_out>;
2729 }; 2619 };
2730 }; 2620 };
2731 }; 2621 };
2732 2622
2733 out-ports { 2623 out-ports {
2734 port { 2624 port {
2735 merge 2625 merge_funnel_out: endpoint {
2736 2626 remote-endpoint =
2737 2627 <&etf_in>;
2738 }; 2628 };
2739 }; 2629 };
2740 }; 2630 };
2741 }; 2631 };
2742 2632
2743 replicator@3026000 { 2633 replicator@3026000 {
2744 compatible = "arm,cor 2634 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2745 reg = <0x3026000 0x10 2635 reg = <0x3026000 0x1000>;
2746 2636
2747 clocks = <&rpmcc RPM_ 2637 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2748 clock-names = "apb_pc 2638 clock-names = "apb_pclk", "atclk";
2749 2639
2750 in-ports { 2640 in-ports {
2751 port { 2641 port {
2752 repli 2642 replicator_in: endpoint {
2753 2643 remote-endpoint =
2754 2644 <&etf_out>;
2755 }; 2645 };
2756 }; 2646 };
2757 }; 2647 };
2758 2648
2759 out-ports { 2649 out-ports {
2760 #address-cell 2650 #address-cells = <1>;
2761 #size-cells = 2651 #size-cells = <0>;
2762 2652
2763 port@0 { 2653 port@0 {
2764 reg = 2654 reg = <0>;
2765 repli 2655 replicator_out0: endpoint {
2766 2656 remote-endpoint =
2767 2657 <&etr_in>;
2768 }; 2658 };
2769 }; 2659 };
2770 2660
2771 port@1 { 2661 port@1 {
2772 reg = 2662 reg = <1>;
2773 repli 2663 replicator_out1: endpoint {
2774 2664 remote-endpoint =
2775 2665 <&tpiu_in>;
2776 }; 2666 };
2777 }; 2667 };
2778 }; 2668 };
2779 }; 2669 };
2780 2670
2781 etf@3027000 { 2671 etf@3027000 {
2782 compatible = "arm,cor 2672 compatible = "arm,coresight-tmc", "arm,primecell";
2783 reg = <0x3027000 0x10 2673 reg = <0x3027000 0x1000>;
2784 2674
2785 clocks = <&rpmcc RPM_ 2675 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2786 clock-names = "apb_pc 2676 clock-names = "apb_pclk", "atclk";
2787 2677
2788 in-ports { 2678 in-ports {
2789 port { 2679 port {
2790 etf_i 2680 etf_in: endpoint {
2791 2681 remote-endpoint =
2792 2682 <&merge_funnel_out>;
2793 }; 2683 };
2794 }; 2684 };
2795 }; 2685 };
2796 2686
2797 out-ports { 2687 out-ports {
2798 port { 2688 port {
2799 etf_o 2689 etf_out: endpoint {
2800 2690 remote-endpoint =
2801 2691 <&replicator_in>;
2802 }; 2692 };
2803 }; 2693 };
2804 }; 2694 };
2805 }; 2695 };
2806 2696
2807 etr@3028000 { 2697 etr@3028000 {
2808 compatible = "arm,cor 2698 compatible = "arm,coresight-tmc", "arm,primecell";
2809 reg = <0x3028000 0x10 2699 reg = <0x3028000 0x1000>;
2810 2700
2811 clocks = <&rpmcc RPM_ 2701 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2812 clock-names = "apb_pc 2702 clock-names = "apb_pclk", "atclk";
2813 arm,scatter-gather; 2703 arm,scatter-gather;
2814 2704
2815 in-ports { 2705 in-ports {
2816 port { 2706 port {
2817 etr_i 2707 etr_in: endpoint {
2818 2708 remote-endpoint =
2819 2709 <&replicator_out0>;
2820 }; 2710 };
2821 }; 2711 };
2822 }; 2712 };
2823 }; 2713 };
2824 2714
2825 debug@3810000 { 2715 debug@3810000 {
2826 compatible = "arm,cor 2716 compatible = "arm,coresight-cpu-debug", "arm,primecell";
2827 reg = <0x3810000 0x10 2717 reg = <0x3810000 0x1000>;
2828 2718
2829 clocks = <&rpmcc RPM_ 2719 clocks = <&rpmcc RPM_QDSS_CLK>;
2830 clock-names = "apb_pc 2720 clock-names = "apb_pclk";
2831 2721
2832 cpu = <&CPU0>; 2722 cpu = <&CPU0>;
2833 }; 2723 };
2834 2724
2835 etm@3840000 { 2725 etm@3840000 {
2836 compatible = "arm,cor 2726 compatible = "arm,coresight-etm4x", "arm,primecell";
2837 reg = <0x3840000 0x10 2727 reg = <0x3840000 0x1000>;
2838 2728
2839 clocks = <&rpmcc RPM_ 2729 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2840 clock-names = "apb_pc 2730 clock-names = "apb_pclk", "atclk";
2841 2731
2842 cpu = <&CPU0>; 2732 cpu = <&CPU0>;
2843 2733
2844 out-ports { 2734 out-ports {
2845 port { 2735 port {
2846 etm0_ 2736 etm0_out: endpoint {
2847 2737 remote-endpoint =
2848 2738 <&apss_funnel0_in0>;
2849 }; 2739 };
2850 }; 2740 };
2851 }; 2741 };
2852 }; 2742 };
2853 2743
2854 debug@3910000 { 2744 debug@3910000 {
2855 compatible = "arm,cor 2745 compatible = "arm,coresight-cpu-debug", "arm,primecell";
2856 reg = <0x3910000 0x10 2746 reg = <0x3910000 0x1000>;
2857 2747
2858 clocks = <&rpmcc RPM_ 2748 clocks = <&rpmcc RPM_QDSS_CLK>;
2859 clock-names = "apb_pc 2749 clock-names = "apb_pclk";
2860 2750
2861 cpu = <&CPU1>; 2751 cpu = <&CPU1>;
2862 }; 2752 };
2863 2753
2864 etm@3940000 { 2754 etm@3940000 {
2865 compatible = "arm,cor 2755 compatible = "arm,coresight-etm4x", "arm,primecell";
2866 reg = <0x3940000 0x10 2756 reg = <0x3940000 0x1000>;
2867 2757
2868 clocks = <&rpmcc RPM_ 2758 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2869 clock-names = "apb_pc 2759 clock-names = "apb_pclk", "atclk";
2870 2760
2871 cpu = <&CPU1>; 2761 cpu = <&CPU1>;
2872 2762
2873 out-ports { 2763 out-ports {
2874 port { 2764 port {
2875 etm1_ 2765 etm1_out: endpoint {
2876 2766 remote-endpoint =
2877 2767 <&apss_funnel0_in1>;
2878 }; 2768 };
2879 }; 2769 };
2880 }; 2770 };
2881 }; 2771 };
2882 2772
2883 funnel@39b0000 { /* APSS Funn 2773 funnel@39b0000 { /* APSS Funnel 0 */
2884 compatible = "arm,cor 2774 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2885 reg = <0x39b0000 0x10 2775 reg = <0x39b0000 0x1000>;
2886 2776
2887 clocks = <&rpmcc RPM_ 2777 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2888 clock-names = "apb_pc 2778 clock-names = "apb_pclk", "atclk";
2889 2779
2890 in-ports { 2780 in-ports {
2891 #address-cell 2781 #address-cells = <1>;
2892 #size-cells = 2782 #size-cells = <0>;
2893 2783
2894 port@0 { 2784 port@0 {
2895 reg = 2785 reg = <0>;
2896 apss_ 2786 apss_funnel0_in0: endpoint {
2897 2787 remote-endpoint = <&etm0_out>;
2898 }; 2788 };
2899 }; 2789 };
2900 2790
2901 port@1 { 2791 port@1 {
2902 reg = 2792 reg = <1>;
2903 apss_ 2793 apss_funnel0_in1: endpoint {
2904 2794 remote-endpoint = <&etm1_out>;
2905 }; 2795 };
2906 }; 2796 };
2907 }; 2797 };
2908 2798
2909 out-ports { 2799 out-ports {
2910 port { 2800 port {
2911 apss_ 2801 apss_funnel0_out: endpoint {
2912 2802 remote-endpoint =
2913 2803 <&apss_merge_funnel_in0>;
2914 }; 2804 };
2915 }; 2805 };
2916 }; 2806 };
2917 }; 2807 };
2918 2808
2919 debug@3a10000 { 2809 debug@3a10000 {
2920 compatible = "arm,cor 2810 compatible = "arm,coresight-cpu-debug", "arm,primecell";
2921 reg = <0x3a10000 0x10 2811 reg = <0x3a10000 0x1000>;
2922 2812
2923 clocks = <&rpmcc RPM_ 2813 clocks = <&rpmcc RPM_QDSS_CLK>;
2924 clock-names = "apb_pc 2814 clock-names = "apb_pclk";
2925 2815
2926 cpu = <&CPU2>; 2816 cpu = <&CPU2>;
2927 }; 2817 };
2928 2818
2929 etm@3a40000 { 2819 etm@3a40000 {
2930 compatible = "arm,cor 2820 compatible = "arm,coresight-etm4x", "arm,primecell";
2931 reg = <0x3a40000 0x10 2821 reg = <0x3a40000 0x1000>;
2932 2822
2933 clocks = <&rpmcc RPM_ 2823 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2934 clock-names = "apb_pc 2824 clock-names = "apb_pclk", "atclk";
2935 2825
2936 cpu = <&CPU2>; 2826 cpu = <&CPU2>;
2937 2827
2938 out-ports { 2828 out-ports {
2939 port { 2829 port {
2940 etm2_ 2830 etm2_out: endpoint {
2941 2831 remote-endpoint =
2942 2832 <&apss_funnel1_in0>;
2943 }; 2833 };
2944 }; 2834 };
2945 }; 2835 };
2946 }; 2836 };
2947 2837
2948 debug@3b10000 { 2838 debug@3b10000 {
2949 compatible = "arm,cor 2839 compatible = "arm,coresight-cpu-debug", "arm,primecell";
2950 reg = <0x3b10000 0x10 2840 reg = <0x3b10000 0x1000>;
2951 2841
2952 clocks = <&rpmcc RPM_ 2842 clocks = <&rpmcc RPM_QDSS_CLK>;
2953 clock-names = "apb_pc 2843 clock-names = "apb_pclk";
2954 2844
2955 cpu = <&CPU3>; 2845 cpu = <&CPU3>;
2956 }; 2846 };
2957 2847
2958 etm@3b40000 { 2848 etm@3b40000 {
2959 compatible = "arm,cor 2849 compatible = "arm,coresight-etm4x", "arm,primecell";
2960 reg = <0x3b40000 0x10 2850 reg = <0x3b40000 0x1000>;
2961 2851
2962 clocks = <&rpmcc RPM_ 2852 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2963 clock-names = "apb_pc 2853 clock-names = "apb_pclk", "atclk";
2964 2854
2965 cpu = <&CPU3>; 2855 cpu = <&CPU3>;
2966 2856
2967 out-ports { 2857 out-ports {
2968 port { 2858 port {
2969 etm3_ 2859 etm3_out: endpoint {
2970 2860 remote-endpoint =
2971 2861 <&apss_funnel1_in1>;
2972 }; 2862 };
2973 }; 2863 };
2974 }; 2864 };
2975 }; 2865 };
2976 2866
2977 funnel@3bb0000 { /* APSS Funn 2867 funnel@3bb0000 { /* APSS Funnel 1 */
2978 compatible = "arm,cor 2868 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2979 reg = <0x3bb0000 0x10 2869 reg = <0x3bb0000 0x1000>;
2980 2870
2981 clocks = <&rpmcc RPM_ 2871 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2982 clock-names = "apb_pc 2872 clock-names = "apb_pclk", "atclk";
2983 2873
2984 in-ports { 2874 in-ports {
2985 #address-cell 2875 #address-cells = <1>;
2986 #size-cells = 2876 #size-cells = <0>;
2987 2877
2988 port@0 { 2878 port@0 {
2989 reg = 2879 reg = <0>;
2990 apss_ 2880 apss_funnel1_in0: endpoint {
2991 2881 remote-endpoint = <&etm2_out>;
2992 }; 2882 };
2993 }; 2883 };
2994 2884
2995 port@1 { 2885 port@1 {
2996 reg = 2886 reg = <1>;
2997 apss_ 2887 apss_funnel1_in1: endpoint {
2998 2888 remote-endpoint = <&etm3_out>;
2999 }; 2889 };
3000 }; 2890 };
3001 }; 2891 };
3002 2892
3003 out-ports { 2893 out-ports {
3004 port { 2894 port {
3005 apss_ 2895 apss_funnel1_out: endpoint {
3006 2896 remote-endpoint =
3007 2897 <&apss_merge_funnel_in1>;
3008 }; 2898 };
3009 }; 2899 };
3010 }; 2900 };
3011 }; 2901 };
3012 2902
3013 funnel@3bc0000 { 2903 funnel@3bc0000 {
3014 compatible = "arm,cor 2904 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3015 reg = <0x3bc0000 0x10 2905 reg = <0x3bc0000 0x1000>;
3016 2906
3017 clocks = <&rpmcc RPM_ 2907 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
3018 clock-names = "apb_pc 2908 clock-names = "apb_pclk", "atclk";
3019 2909
3020 in-ports { 2910 in-ports {
3021 #address-cell 2911 #address-cells = <1>;
3022 #size-cells = 2912 #size-cells = <0>;
3023 2913
3024 port@0 { 2914 port@0 {
3025 reg = 2915 reg = <0>;
3026 apss_ 2916 apss_merge_funnel_in0: endpoint {
3027 2917 remote-endpoint =
3028 2918 <&apss_funnel0_out>;
3029 }; 2919 };
3030 }; 2920 };
3031 2921
3032 port@1 { 2922 port@1 {
3033 reg = 2923 reg = <1>;
3034 apss_ 2924 apss_merge_funnel_in1: endpoint {
3035 2925 remote-endpoint =
3036 2926 <&apss_funnel1_out>;
3037 }; 2927 };
3038 }; 2928 };
3039 }; 2929 };
3040 2930
3041 out-ports { 2931 out-ports {
3042 port { 2932 port {
3043 apss_ 2933 apss_merge_funnel_out: endpoint {
3044 2934 remote-endpoint =
3045 2935 <&funnel1_in>;
3046 }; 2936 };
3047 }; 2937 };
3048 }; 2938 };
3049 }; 2939 };
3050 2940
3051 kryocc: clock-controller@6400 2941 kryocc: clock-controller@6400000 {
3052 compatible = "qcom,ms 2942 compatible = "qcom,msm8996-apcc";
3053 reg = <0x06400000 0x9 2943 reg = <0x06400000 0x90000>;
3054 2944
3055 clock-names = "xo", " 2945 clock-names = "xo", "sys_apcs_aux";
3056 clocks = <&rpmcc RPM_ 2946 clocks = <&rpmcc RPM_SMD_XO_A_CLK_SRC>, <&apcs_glb>;
3057 2947
3058 #clock-cells = <1>; 2948 #clock-cells = <1>;
3059 }; 2949 };
3060 2950
3061 usb3: usb@6af8800 { 2951 usb3: usb@6af8800 {
3062 compatible = "qcom,ms 2952 compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
3063 reg = <0x06af8800 0x4 2953 reg = <0x06af8800 0x400>;
3064 #address-cells = <1>; 2954 #address-cells = <1>;
3065 #size-cells = <1>; 2955 #size-cells = <1>;
3066 ranges; 2956 ranges;
3067 2957
3068 interrupts = <GIC_SPI 2958 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
3069 <GIC_SPI 2959 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
3070 interrupt-names = "hs 2960 interrupt-names = "hs_phy_irq", "ss_phy_irq";
3071 2961
3072 clocks = <&gcc GCC_SY 2962 clocks = <&gcc GCC_SYS_NOC_USB3_AXI_CLK>,
3073 <&gcc GCC_US 2963 <&gcc GCC_USB30_MASTER_CLK>,
3074 <&gcc GCC_AG 2964 <&gcc GCC_AGGRE2_USB3_AXI_CLK>,
3075 <&gcc GCC_US 2965 <&gcc GCC_USB30_SLEEP_CLK>,
3076 <&gcc GCC_US 2966 <&gcc GCC_USB30_MOCK_UTMI_CLK>;
3077 clock-names = "cfg_no 2967 clock-names = "cfg_noc",
3078 "core", 2968 "core",
3079 "iface" 2969 "iface",
3080 "sleep" 2970 "sleep",
3081 "mock_u 2971 "mock_utmi";
3082 2972
3083 assigned-clocks = <&g 2973 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
3084 <&g 2974 <&gcc GCC_USB30_MASTER_CLK>;
3085 assigned-clock-rates 2975 assigned-clock-rates = <19200000>, <120000000>;
3086 2976
3087 interconnects = <&a2n 2977 interconnects = <&a2noc MASTER_USB3 &bimc SLAVE_EBI_CH0>,
3088 <&bim 2978 <&bimc MASTER_AMPSS_M0 &snoc SLAVE_USB3>;
3089 interconnect-names = 2979 interconnect-names = "usb-ddr", "apps-usb";
3090 2980
3091 power-domains = <&gcc 2981 power-domains = <&gcc USB30_GDSC>;
3092 status = "disabled"; 2982 status = "disabled";
3093 2983
3094 usb3_dwc3: usb@6a0000 2984 usb3_dwc3: usb@6a00000 {
3095 compatible = 2985 compatible = "snps,dwc3";
3096 reg = <0x06a0 2986 reg = <0x06a00000 0xcc00>;
3097 interrupts = !! 2987 interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>;
3098 phys = <&hsus !! 2988 phys = <&hsusb_phy1>, <&ssusb_phy_0>;
3099 phy-names = " 2989 phy-names = "usb2-phy", "usb3-phy";
3100 snps,hird-thr <<
3101 snps,dis_u2_s 2990 snps,dis_u2_susphy_quirk;
3102 snps,dis_enbl 2991 snps,dis_enblslpm_quirk;
3103 snps,is-utmi- <<
3104 snps,parkmode <<
3105 tx-fifo-resiz <<
3106 }; 2992 };
3107 }; 2993 };
3108 2994
3109 usb3phy: phy@7410000 { 2995 usb3phy: phy@7410000 {
3110 compatible = "qcom,ms 2996 compatible = "qcom,msm8996-qmp-usb3-phy";
3111 reg = <0x07410000 0x1 !! 2997 reg = <0x07410000 0x1c4>;
>> 2998 #address-cells = <1>;
>> 2999 #size-cells = <1>;
>> 3000 ranges;
3112 3001
3113 clocks = <&gcc GCC_US 3002 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
3114 <&gcc GCC_US !! 3003 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
3115 <&gcc GCC_US !! 3004 <&gcc GCC_USB3_CLKREF_CLK>;
3116 <&gcc GCC_US !! 3005 clock-names = "aux", "cfg_ahb", "ref";
3117 clock-names = "aux", <<
3118 "ref", <<
3119 "cfg_ah <<
3120 "pipe"; <<
3121 clock-output-names = <<
3122 #clock-cells = <0>; <<
3123 #phy-cells = <0>; <<
3124 3006
3125 resets = <&gcc GCC_US 3007 resets = <&gcc GCC_USB3_PHY_BCR>,
3126 <&gcc GCC_US !! 3008 <&gcc GCC_USB3PHY_PHY_BCR>;
3127 reset-names = "phy", !! 3009 reset-names = "phy", "common";
3128 "phy_ph <<
3129 <<
3130 status = "disabled"; 3010 status = "disabled";
>> 3011
>> 3012 ssusb_phy_0: phy@7410200 {
>> 3013 reg = <0x07410200 0x200>,
>> 3014 <0x07410400 0x130>,
>> 3015 <0x07410600 0x1a8>;
>> 3016 #phy-cells = <0>;
>> 3017
>> 3018 #clock-cells = <0>;
>> 3019 clock-output-names = "usb3_phy_pipe_clk_src";
>> 3020 clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
>> 3021 clock-names = "pipe0";
>> 3022 };
3131 }; 3023 };
3132 3024
3133 hsusb_phy1: phy@7411000 { 3025 hsusb_phy1: phy@7411000 {
3134 compatible = "qcom,ms 3026 compatible = "qcom,msm8996-qusb2-phy";
3135 reg = <0x07411000 0x1 3027 reg = <0x07411000 0x180>;
3136 #phy-cells = <0>; 3028 #phy-cells = <0>;
3137 3029
3138 clocks = <&gcc GCC_US 3030 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
3139 <&gcc GCC_RX1 3031 <&gcc GCC_RX1_USB2_CLKREF_CLK>;
3140 clock-names = "cfg_ah 3032 clock-names = "cfg_ahb", "ref";
3141 3033
3142 resets = <&gcc GCC_QU 3034 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
3143 nvmem-cells = <&qusb2 3035 nvmem-cells = <&qusb2p_hstx_trim>;
3144 status = "disabled"; 3036 status = "disabled";
3145 }; 3037 };
3146 3038
3147 hsusb_phy2: phy@7412000 { 3039 hsusb_phy2: phy@7412000 {
3148 compatible = "qcom,ms 3040 compatible = "qcom,msm8996-qusb2-phy";
3149 reg = <0x07412000 0x1 3041 reg = <0x07412000 0x180>;
3150 #phy-cells = <0>; 3042 #phy-cells = <0>;
3151 3043
3152 clocks = <&gcc GCC_US 3044 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
3153 <&gcc GCC_RX2 3045 <&gcc GCC_RX2_USB2_CLKREF_CLK>;
3154 clock-names = "cfg_ah 3046 clock-names = "cfg_ahb", "ref";
3155 3047
3156 resets = <&gcc GCC_QU 3048 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
3157 nvmem-cells = <&qusb2 3049 nvmem-cells = <&qusb2s_hstx_trim>;
3158 status = "disabled"; 3050 status = "disabled";
3159 }; 3051 };
3160 3052
3161 sdhc1: mmc@7464900 { 3053 sdhc1: mmc@7464900 {
3162 compatible = "qcom,ms 3054 compatible = "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4";
3163 reg = <0x07464900 0x1 3055 reg = <0x07464900 0x11c>, <0x07464000 0x800>;
3164 reg-names = "hc", "co 3056 reg-names = "hc", "core";
3165 3057
3166 interrupts = <GIC_SPI 3058 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
3167 <GIC_ 3059 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
3168 interrupt-names = "hc 3060 interrupt-names = "hc_irq", "pwr_irq";
3169 3061
3170 clock-names = "iface" 3062 clock-names = "iface", "core", "xo";
3171 clocks = <&gcc GCC_SD 3063 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
3172 <&gcc GCC_SDC 3064 <&gcc GCC_SDCC1_APPS_CLK>,
3173 <&rpmcc RPM_S 3065 <&rpmcc RPM_SMD_XO_CLK_SRC>;
3174 resets = <&gcc GCC_SD 3066 resets = <&gcc GCC_SDCC1_BCR>;
3175 3067
3176 pinctrl-names = "defa 3068 pinctrl-names = "default", "sleep";
3177 pinctrl-0 = <&sdc1_st 3069 pinctrl-0 = <&sdc1_state_on>;
3178 pinctrl-1 = <&sdc1_st 3070 pinctrl-1 = <&sdc1_state_off>;
3179 3071
3180 bus-width = <8>; 3072 bus-width = <8>;
3181 non-removable; 3073 non-removable;
3182 status = "disabled"; 3074 status = "disabled";
3183 }; 3075 };
3184 3076
3185 sdhc2: mmc@74a4900 { 3077 sdhc2: mmc@74a4900 {
3186 compatible = "qcom,ms 3078 compatible = "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4";
3187 reg = <0x074a4900 0x3 3079 reg = <0x074a4900 0x314>, <0x074a4000 0x800>;
3188 reg-names = "hc", "co 3080 reg-names = "hc", "core";
3189 3081
3190 interrupts = <GIC_SPI 3082 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
3191 <GIC_SP 3083 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
3192 interrupt-names = "hc 3084 interrupt-names = "hc_irq", "pwr_irq";
3193 3085
3194 clock-names = "iface" 3086 clock-names = "iface", "core", "xo";
3195 clocks = <&gcc GCC_SD 3087 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
3196 <&gcc GCC_SDC 3088 <&gcc GCC_SDCC2_APPS_CLK>,
3197 <&rpmcc RPM_S 3089 <&rpmcc RPM_SMD_XO_CLK_SRC>;
3198 resets = <&gcc GCC_SD 3090 resets = <&gcc GCC_SDCC2_BCR>;
3199 3091
3200 pinctrl-names = "defa 3092 pinctrl-names = "default", "sleep";
3201 pinctrl-0 = <&sdc2_st 3093 pinctrl-0 = <&sdc2_state_on>;
3202 pinctrl-1 = <&sdc2_st 3094 pinctrl-1 = <&sdc2_state_off>;
3203 3095
3204 bus-width = <4>; 3096 bus-width = <4>;
3205 status = "disabled"; 3097 status = "disabled";
3206 }; 3098 };
3207 3099
3208 blsp1_dma: dma-controller@754 3100 blsp1_dma: dma-controller@7544000 {
3209 compatible = "qcom,ba 3101 compatible = "qcom,bam-v1.7.0";
3210 reg = <0x07544000 0x2 3102 reg = <0x07544000 0x2b000>;
3211 interrupts = <GIC_SPI 3103 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
3212 clocks = <&gcc GCC_BL 3104 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
3213 clock-names = "bam_cl 3105 clock-names = "bam_clk";
3214 qcom,controlled-remot 3106 qcom,controlled-remotely;
3215 #dma-cells = <1>; 3107 #dma-cells = <1>;
3216 qcom,ee = <0>; 3108 qcom,ee = <0>;
3217 }; 3109 };
3218 3110
3219 blsp1_uart2: serial@7570000 { 3111 blsp1_uart2: serial@7570000 {
3220 compatible = "qcom,ms 3112 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
3221 reg = <0x07570000 0x1 3113 reg = <0x07570000 0x1000>;
3222 interrupts = <GIC_SPI 3114 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
3223 clocks = <&gcc GCC_BL 3115 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
3224 <&gcc GCC_BL 3116 <&gcc GCC_BLSP1_AHB_CLK>;
3225 clock-names = "core", 3117 clock-names = "core", "iface";
3226 pinctrl-names = "defa 3118 pinctrl-names = "default", "sleep";
3227 pinctrl-0 = <&blsp1_u 3119 pinctrl-0 = <&blsp1_uart2_default>;
3228 pinctrl-1 = <&blsp1_u 3120 pinctrl-1 = <&blsp1_uart2_sleep>;
3229 dmas = <&blsp1_dma 2> 3121 dmas = <&blsp1_dma 2>, <&blsp1_dma 3>;
3230 dma-names = "tx", "rx 3122 dma-names = "tx", "rx";
3231 status = "disabled"; 3123 status = "disabled";
3232 }; 3124 };
3233 3125
3234 blsp1_spi1: spi@7575000 { 3126 blsp1_spi1: spi@7575000 {
3235 compatible = "qcom,sp 3127 compatible = "qcom,spi-qup-v2.2.1";
3236 reg = <0x07575000 0x6 3128 reg = <0x07575000 0x600>;
3237 interrupts = <GIC_SPI 3129 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
3238 clocks = <&gcc GCC_BL 3130 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
3239 <&gcc GCC_BL 3131 <&gcc GCC_BLSP1_AHB_CLK>;
3240 clock-names = "core", 3132 clock-names = "core", "iface";
3241 pinctrl-names = "defa 3133 pinctrl-names = "default", "sleep";
3242 pinctrl-0 = <&blsp1_s 3134 pinctrl-0 = <&blsp1_spi1_default>;
3243 pinctrl-1 = <&blsp1_s 3135 pinctrl-1 = <&blsp1_spi1_sleep>;
3244 dmas = <&blsp1_dma 12 3136 dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
3245 dma-names = "tx", "rx 3137 dma-names = "tx", "rx";
3246 #address-cells = <1>; 3138 #address-cells = <1>;
3247 #size-cells = <0>; 3139 #size-cells = <0>;
3248 status = "disabled"; 3140 status = "disabled";
3249 }; 3141 };
3250 3142
3251 blsp1_i2c3: i2c@7577000 { 3143 blsp1_i2c3: i2c@7577000 {
3252 compatible = "qcom,i2 3144 compatible = "qcom,i2c-qup-v2.2.1";
3253 reg = <0x07577000 0x1 3145 reg = <0x07577000 0x1000>;
3254 interrupts = <GIC_SPI 3146 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
3255 clocks = <&gcc GCC_BL 3147 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
3256 <&gcc GCC_BL 3148 <&gcc GCC_BLSP1_AHB_CLK>;
3257 clock-names = "core", 3149 clock-names = "core", "iface";
3258 pinctrl-names = "defa 3150 pinctrl-names = "default", "sleep";
3259 pinctrl-0 = <&blsp1_i 3151 pinctrl-0 = <&blsp1_i2c3_default>;
3260 pinctrl-1 = <&blsp1_i 3152 pinctrl-1 = <&blsp1_i2c3_sleep>;
3261 dmas = <&blsp1_dma 16 3153 dmas = <&blsp1_dma 16>, <&blsp1_dma 17>;
3262 dma-names = "tx", "rx 3154 dma-names = "tx", "rx";
3263 #address-cells = <1>; 3155 #address-cells = <1>;
3264 #size-cells = <0>; 3156 #size-cells = <0>;
3265 status = "disabled"; 3157 status = "disabled";
3266 }; 3158 };
3267 3159
3268 blsp1_i2c6: i2c@757a000 { 3160 blsp1_i2c6: i2c@757a000 {
3269 compatible = "qcom,i2 3161 compatible = "qcom,i2c-qup-v2.2.1";
3270 reg = <0x757a000 0x10 3162 reg = <0x757a000 0x1000>;
3271 interrupts = <GIC_SPI 3163 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
3272 clocks = <&gcc GCC_BL 3164 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
3273 <&gcc GCC_BL 3165 <&gcc GCC_BLSP1_AHB_CLK>;
3274 clock-names = "core", 3166 clock-names = "core", "iface";
3275 pinctrl-names = "defa 3167 pinctrl-names = "default", "sleep";
3276 pinctrl-0 = <&blsp1_i 3168 pinctrl-0 = <&blsp1_i2c6_default>;
3277 pinctrl-1 = <&blsp1_i 3169 pinctrl-1 = <&blsp1_i2c6_sleep>;
3278 dmas = <&blsp1_dma 22 3170 dmas = <&blsp1_dma 22>, <&blsp1_dma 23>;
3279 dma-names = "tx", "rx 3171 dma-names = "tx", "rx";
3280 #address-cells = <1>; 3172 #address-cells = <1>;
3281 #size-cells = <0>; 3173 #size-cells = <0>;
3282 status = "disabled"; 3174 status = "disabled";
3283 }; 3175 };
3284 3176
3285 blsp2_dma: dma-controller@758 3177 blsp2_dma: dma-controller@7584000 {
3286 compatible = "qcom,ba 3178 compatible = "qcom,bam-v1.7.0";
3287 reg = <0x07584000 0x2 3179 reg = <0x07584000 0x2b000>;
3288 interrupts = <GIC_SPI 3180 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
3289 clocks = <&gcc GCC_BL 3181 clocks = <&gcc GCC_BLSP2_AHB_CLK>;
3290 clock-names = "bam_cl 3182 clock-names = "bam_clk";
3291 qcom,controlled-remot 3183 qcom,controlled-remotely;
3292 #dma-cells = <1>; 3184 #dma-cells = <1>;
3293 qcom,ee = <0>; 3185 qcom,ee = <0>;
3294 }; 3186 };
3295 3187
3296 blsp2_uart2: serial@75b0000 { 3188 blsp2_uart2: serial@75b0000 {
3297 compatible = "qcom,ms 3189 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
3298 reg = <0x075b0000 0x1 3190 reg = <0x075b0000 0x1000>;
3299 interrupts = <GIC_SPI 3191 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
3300 clocks = <&gcc GCC_BL 3192 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
3301 <&gcc GCC_BL 3193 <&gcc GCC_BLSP2_AHB_CLK>;
3302 clock-names = "core", 3194 clock-names = "core", "iface";
3303 status = "disabled"; 3195 status = "disabled";
3304 }; 3196 };
3305 3197
3306 blsp2_uart3: serial@75b1000 { 3198 blsp2_uart3: serial@75b1000 {
3307 compatible = "qcom,ms 3199 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
3308 reg = <0x075b1000 0x1 3200 reg = <0x075b1000 0x1000>;
3309 interrupts = <GIC_SPI 3201 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
3310 clocks = <&gcc GCC_BL 3202 clocks = <&gcc GCC_BLSP2_UART3_APPS_CLK>,
3311 <&gcc GCC_BL 3203 <&gcc GCC_BLSP2_AHB_CLK>;
3312 clock-names = "core", 3204 clock-names = "core", "iface";
3313 status = "disabled"; 3205 status = "disabled";
3314 }; 3206 };
3315 3207
3316 blsp2_i2c1: i2c@75b5000 { 3208 blsp2_i2c1: i2c@75b5000 {
3317 compatible = "qcom,i2 3209 compatible = "qcom,i2c-qup-v2.2.1";
3318 reg = <0x075b5000 0x1 3210 reg = <0x075b5000 0x1000>;
3319 interrupts = <GIC_SPI 3211 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
3320 clocks = <&gcc GCC_BL 3212 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
3321 <&gcc GCC_BL 3213 <&gcc GCC_BLSP2_AHB_CLK>;
3322 clock-names = "core", 3214 clock-names = "core", "iface";
3323 pinctrl-names = "defa 3215 pinctrl-names = "default", "sleep";
3324 pinctrl-0 = <&blsp2_i 3216 pinctrl-0 = <&blsp2_i2c1_default>;
3325 pinctrl-1 = <&blsp2_i 3217 pinctrl-1 = <&blsp2_i2c1_sleep>;
3326 dmas = <&blsp2_dma 12 3218 dmas = <&blsp2_dma 12>, <&blsp2_dma 13>;
3327 dma-names = "tx", "rx 3219 dma-names = "tx", "rx";
3328 #address-cells = <1>; 3220 #address-cells = <1>;
3329 #size-cells = <0>; 3221 #size-cells = <0>;
3330 status = "disabled"; 3222 status = "disabled";
3331 }; 3223 };
3332 3224
3333 blsp2_i2c2: i2c@75b6000 { 3225 blsp2_i2c2: i2c@75b6000 {
3334 compatible = "qcom,i2 3226 compatible = "qcom,i2c-qup-v2.2.1";
3335 reg = <0x075b6000 0x1 3227 reg = <0x075b6000 0x1000>;
3336 interrupts = <GIC_SPI 3228 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
3337 clocks = <&gcc GCC_BL 3229 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>,
3338 <&gcc GCC_BL 3230 <&gcc GCC_BLSP2_AHB_CLK>;
3339 clock-names = "core", 3231 clock-names = "core", "iface";
3340 pinctrl-names = "defa 3232 pinctrl-names = "default", "sleep";
3341 pinctrl-0 = <&blsp2_i 3233 pinctrl-0 = <&blsp2_i2c2_default>;
3342 pinctrl-1 = <&blsp2_i 3234 pinctrl-1 = <&blsp2_i2c2_sleep>;
3343 dmas = <&blsp2_dma 14 3235 dmas = <&blsp2_dma 14>, <&blsp2_dma 15>;
3344 dma-names = "tx", "rx 3236 dma-names = "tx", "rx";
3345 #address-cells = <1>; 3237 #address-cells = <1>;
3346 #size-cells = <0>; 3238 #size-cells = <0>;
3347 status = "disabled"; 3239 status = "disabled";
3348 }; 3240 };
3349 3241
3350 blsp2_i2c3: i2c@75b7000 { 3242 blsp2_i2c3: i2c@75b7000 {
3351 compatible = "qcom,i2 3243 compatible = "qcom,i2c-qup-v2.2.1";
3352 reg = <0x075b7000 0x1 3244 reg = <0x075b7000 0x1000>;
3353 interrupts = <GIC_SPI 3245 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
3354 clocks = <&gcc GCC_BL 3246 clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>,
3355 <&gcc GCC_BL 3247 <&gcc GCC_BLSP2_AHB_CLK>;
3356 clock-names = "core", 3248 clock-names = "core", "iface";
3357 clock-frequency = <40 3249 clock-frequency = <400000>;
3358 pinctrl-names = "defa 3250 pinctrl-names = "default", "sleep";
3359 pinctrl-0 = <&blsp2_i 3251 pinctrl-0 = <&blsp2_i2c3_default>;
3360 pinctrl-1 = <&blsp2_i 3252 pinctrl-1 = <&blsp2_i2c3_sleep>;
3361 dmas = <&blsp2_dma 16 3253 dmas = <&blsp2_dma 16>, <&blsp2_dma 17>;
3362 dma-names = "tx", "rx 3254 dma-names = "tx", "rx";
3363 #address-cells = <1>; 3255 #address-cells = <1>;
3364 #size-cells = <0>; 3256 #size-cells = <0>;
3365 status = "disabled"; 3257 status = "disabled";
3366 }; 3258 };
3367 3259
3368 blsp2_i2c5: i2c@75b9000 { 3260 blsp2_i2c5: i2c@75b9000 {
3369 compatible = "qcom,i2 3261 compatible = "qcom,i2c-qup-v2.2.1";
3370 reg = <0x75b9000 0x10 3262 reg = <0x75b9000 0x1000>;
3371 interrupts = <GIC_SPI 3263 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
3372 clocks = <&gcc GCC_BL 3264 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>,
3373 <&gcc GCC_BL 3265 <&gcc GCC_BLSP2_AHB_CLK>;
3374 clock-names = "core", 3266 clock-names = "core", "iface";
3375 pinctrl-names = "defa 3267 pinctrl-names = "default";
3376 pinctrl-0 = <&blsp2_i 3268 pinctrl-0 = <&blsp2_i2c5_default>;
3377 dmas = <&blsp2_dma 20 3269 dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
3378 dma-names = "tx", "rx 3270 dma-names = "tx", "rx";
3379 #address-cells = <1>; 3271 #address-cells = <1>;
3380 #size-cells = <0>; 3272 #size-cells = <0>;
3381 status = "disabled"; 3273 status = "disabled";
3382 }; 3274 };
3383 3275
3384 blsp2_i2c6: i2c@75ba000 { 3276 blsp2_i2c6: i2c@75ba000 {
3385 compatible = "qcom,i2 3277 compatible = "qcom,i2c-qup-v2.2.1";
3386 reg = <0x75ba000 0x10 3278 reg = <0x75ba000 0x1000>;
3387 interrupts = <GIC_SPI 3279 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
3388 clocks = <&gcc GCC_BL 3280 clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>,
3389 <&gcc GCC_BL 3281 <&gcc GCC_BLSP2_AHB_CLK>;
3390 clock-names = "core", 3282 clock-names = "core", "iface";
3391 pinctrl-names = "defa 3283 pinctrl-names = "default", "sleep";
3392 pinctrl-0 = <&blsp2_i 3284 pinctrl-0 = <&blsp2_i2c6_default>;
3393 pinctrl-1 = <&blsp2_i 3285 pinctrl-1 = <&blsp2_i2c6_sleep>;
3394 dmas = <&blsp2_dma 22 3286 dmas = <&blsp2_dma 22>, <&blsp2_dma 23>;
3395 dma-names = "tx", "rx 3287 dma-names = "tx", "rx";
3396 #address-cells = <1>; 3288 #address-cells = <1>;
3397 #size-cells = <0>; 3289 #size-cells = <0>;
3398 status = "disabled"; 3290 status = "disabled";
3399 }; 3291 };
3400 3292
3401 blsp2_spi6: spi@75ba000 { !! 3293 blsp2_spi6: spi@75ba000{
3402 compatible = "qcom,sp 3294 compatible = "qcom,spi-qup-v2.2.1";
3403 reg = <0x075ba000 0x6 3295 reg = <0x075ba000 0x600>;
3404 interrupts = <GIC_SPI 3296 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
3405 clocks = <&gcc GCC_BL 3297 clocks = <&gcc GCC_BLSP2_QUP6_SPI_APPS_CLK>,
3406 <&gcc GCC_BL 3298 <&gcc GCC_BLSP2_AHB_CLK>;
3407 clock-names = "core", 3299 clock-names = "core", "iface";
3408 pinctrl-names = "defa 3300 pinctrl-names = "default", "sleep";
3409 pinctrl-0 = <&blsp2_s 3301 pinctrl-0 = <&blsp2_spi6_default>;
3410 pinctrl-1 = <&blsp2_s 3302 pinctrl-1 = <&blsp2_spi6_sleep>;
3411 dmas = <&blsp2_dma 22 3303 dmas = <&blsp2_dma 22>, <&blsp2_dma 23>;
3412 dma-names = "tx", "rx 3304 dma-names = "tx", "rx";
3413 #address-cells = <1>; 3305 #address-cells = <1>;
3414 #size-cells = <0>; 3306 #size-cells = <0>;
3415 status = "disabled"; 3307 status = "disabled";
3416 }; 3308 };
3417 3309
3418 usb2: usb@76f8800 { 3310 usb2: usb@76f8800 {
3419 compatible = "qcom,ms 3311 compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
3420 reg = <0x076f8800 0x4 3312 reg = <0x076f8800 0x400>;
3421 #address-cells = <1>; 3313 #address-cells = <1>;
3422 #size-cells = <1>; 3314 #size-cells = <1>;
3423 ranges; 3315 ranges;
3424 3316
3425 interrupts = <GIC_SPI <<
3426 <GIC_SPI <<
3427 <GIC_SPI <<
3428 interrupt-names = "pw <<
3429 "qu <<
3430 "hs <<
3431 <<
3432 clocks = <&gcc GCC_PE 3317 clocks = <&gcc GCC_PERIPH_NOC_USB20_AHB_CLK>,
3433 <&gcc GCC_USB 3318 <&gcc GCC_USB20_MASTER_CLK>,
3434 <&gcc GCC_USB 3319 <&gcc GCC_USB20_MOCK_UTMI_CLK>,
3435 <&gcc GCC_USB 3320 <&gcc GCC_USB20_SLEEP_CLK>,
3436 <&gcc GCC_USB 3321 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
3437 clock-names = "cfg_no 3322 clock-names = "cfg_noc",
3438 "core", 3323 "core",
3439 "iface" 3324 "iface",
3440 "sleep" 3325 "sleep",
3441 "mock_u 3326 "mock_utmi";
3442 3327
3443 assigned-clocks = <&g 3328 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
3444 <&g 3329 <&gcc GCC_USB20_MASTER_CLK>;
3445 assigned-clock-rates 3330 assigned-clock-rates = <19200000>, <60000000>;
3446 3331
3447 power-domains = <&gcc 3332 power-domains = <&gcc USB30_GDSC>;
3448 qcom,select-utmi-as-p 3333 qcom,select-utmi-as-pipe-clk;
3449 status = "disabled"; 3334 status = "disabled";
3450 3335
3451 usb2_dwc3: usb@760000 3336 usb2_dwc3: usb@7600000 {
3452 compatible = 3337 compatible = "snps,dwc3";
3453 reg = <0x0760 3338 reg = <0x07600000 0xcc00>;
3454 interrupts = !! 3339 interrupts = <0 138 IRQ_TYPE_LEVEL_HIGH>;
3455 phys = <&hsus 3340 phys = <&hsusb_phy2>;
3456 phy-names = " 3341 phy-names = "usb2-phy";
3457 maximum-speed 3342 maximum-speed = "high-speed";
3458 snps,dis_u2_s 3343 snps,dis_u2_susphy_quirk;
3459 snps,dis_enbl 3344 snps,dis_enblslpm_quirk;
3460 }; 3345 };
3461 }; 3346 };
3462 3347
3463 slimbam: dma-controller@91840 3348 slimbam: dma-controller@9184000 {
3464 compatible = "qcom,ba 3349 compatible = "qcom,bam-v1.7.0";
3465 qcom,controlled-remot 3350 qcom,controlled-remotely;
3466 reg = <0x09184000 0x3 3351 reg = <0x09184000 0x32000>;
3467 num-channels = <31>; 3352 num-channels = <31>;
3468 interrupts = <GIC_SPI !! 3353 interrupts = <0 164 IRQ_TYPE_LEVEL_HIGH>;
3469 #dma-cells = <1>; 3354 #dma-cells = <1>;
3470 qcom,ee = <1>; 3355 qcom,ee = <1>;
3471 qcom,num-ees = <2>; 3356 qcom,num-ees = <2>;
3472 }; 3357 };
3473 3358
3474 slim_msm: slim-ngd@91c0000 { 3359 slim_msm: slim-ngd@91c0000 {
3475 compatible = "qcom,sl 3360 compatible = "qcom,slim-ngd-v1.5.0";
3476 reg = <0x091c0000 0x2 !! 3361 reg = <0x091c0000 0x2C000>;
3477 interrupts = <GIC_SPI !! 3362 interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>;
3478 dmas = <&slimbam 3>, 3363 dmas = <&slimbam 3>, <&slimbam 4>;
3479 dma-names = "rx", "tx 3364 dma-names = "rx", "tx";
3480 #address-cells = <1>; 3365 #address-cells = <1>;
3481 #size-cells = <0>; 3366 #size-cells = <0>;
>> 3367 slim@1 {
>> 3368 reg = <1>;
>> 3369 #address-cells = <2>;
>> 3370 #size-cells = <0>;
3482 3371
3483 status = "disabled"; !! 3372 tasha_ifd: tas-ifd@0,0 {
>> 3373 compatible = "slim217,1a0";
>> 3374 reg = <0 0>;
>> 3375 };
>> 3376
>> 3377 wcd9335: codec@1,0 {
>> 3378 pinctrl-0 = <&cdc_reset_active &wcd_intr_default>;
>> 3379 pinctrl-names = "default";
>> 3380
>> 3381 compatible = "slim217,1a0";
>> 3382 reg = <1 0>;
>> 3383
>> 3384 interrupt-parent = <&tlmm>;
>> 3385 interrupts = <54 IRQ_TYPE_LEVEL_HIGH>,
>> 3386 <53 IRQ_TYPE_LEVEL_HIGH>;
>> 3387 interrupt-names = "intr1", "intr2";
>> 3388 interrupt-controller;
>> 3389 #interrupt-cells = <1>;
>> 3390 reset-gpios = <&tlmm 64 GPIO_ACTIVE_LOW>;
>> 3391
>> 3392 slim-ifc-dev = <&tasha_ifd>;
>> 3393
>> 3394 #sound-dai-cells = <1>;
>> 3395 };
>> 3396 };
3484 }; 3397 };
3485 3398
3486 adsp_pil: remoteproc@9300000 3399 adsp_pil: remoteproc@9300000 {
3487 compatible = "qcom,ms 3400 compatible = "qcom,msm8996-adsp-pil";
3488 reg = <0x09300000 0x8 3401 reg = <0x09300000 0x80000>;
3489 3402
3490 interrupts-extended = 3403 interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>,
3491 3404 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3492 3405 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
3493 3406 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
3494 3407 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
3495 interrupt-names = "wd 3408 interrupt-names = "wdog", "fatal", "ready",
3496 "ha 3409 "handover", "stop-ack";
3497 3410
3498 clocks = <&rpmcc RPM_ 3411 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
3499 clock-names = "xo"; 3412 clock-names = "xo";
3500 3413
3501 memory-region = <&ads 3414 memory-region = <&adsp_mem>;
3502 3415
3503 qcom,smem-states = <& 3416 qcom,smem-states = <&adsp_smp2p_out 0>;
3504 qcom,smem-state-names 3417 qcom,smem-state-names = "stop";
3505 3418
3506 power-domains = <&rpm 3419 power-domains = <&rpmpd MSM8996_VDDCX>;
3507 power-domain-names = 3420 power-domain-names = "cx";
3508 3421
3509 status = "disabled"; 3422 status = "disabled";
3510 3423
3511 glink-edge { <<
3512 interrupts = <<
3513 label = "lpas <<
3514 qcom,remote-p <<
3515 mboxes = <&ap <<
3516 }; <<
3517 <<
3518 <<
3519 smd-edge { 3424 smd-edge {
3520 interrupts = 3425 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
3521 3426
3522 label = "lpas 3427 label = "lpass";
3523 mboxes = <&ap 3428 mboxes = <&apcs_glb 8>;
3524 qcom,smd-edge 3429 qcom,smd-edge = <1>;
3525 qcom,remote-p 3430 qcom,remote-pid = <2>;
3526 !! 3431 #address-cells = <1>;
>> 3432 #size-cells = <0>;
3527 apr { 3433 apr {
3528 power 3434 power-domains = <&gcc HLOS1_VOTE_LPASS_ADSP_GDSC>;
3529 compa 3435 compatible = "qcom,apr-v2";
3530 qcom, 3436 qcom,smd-channels = "apr_audio_svc";
3531 qcom, 3437 qcom,domain = <APR_DOMAIN_ADSP>;
3532 #addr 3438 #address-cells = <1>;
3533 #size 3439 #size-cells = <0>;
3534 3440
3535 servi 3441 service@3 {
3536 3442 reg = <APR_SVC_ADSP_CORE>;
3537 3443 compatible = "qcom,q6core";
3538 }; 3444 };
3539 3445
3540 q6afe 3446 q6afe: service@4 {
3541 3447 compatible = "qcom,q6afe";
3542 3448 reg = <APR_SVC_AFE>;
3543 3449 q6afedai: dais {
3544 3450 compatible = "qcom,q6afe-dais";
3545 3451 #address-cells = <1>;
3546 3452 #size-cells = <0>;
3547 3453 #sound-dai-cells = <1>;
3548 3454 dai@1 {
3549 3455 reg = <1>;
3550 3456 };
3551 3457 };
3552 }; 3458 };
3553 3459
3554 q6asm 3460 q6asm: service@7 {
3555 3461 compatible = "qcom,q6asm";
3556 3462 reg = <APR_SVC_ASM>;
3557 3463 q6asmdai: dais {
3558 3464 compatible = "qcom,q6asm-dais";
3559 3465 #address-cells = <1>;
3560 3466 #size-cells = <0>;
3561 3467 #sound-dai-cells = <1>;
3562 3468 iommus = <&lpass_q6_smmu 1>;
3563 3469 };
3564 }; 3470 };
3565 3471
3566 q6adm 3472 q6adm: service@8 {
3567 3473 compatible = "qcom,q6adm";
3568 3474 reg = <APR_SVC_ADM>;
3569 3475 q6routing: routing {
3570 3476 compatible = "qcom,q6adm-routing";
3571 3477 #sound-dai-cells = <0>;
3572 3478 };
3573 }; 3479 };
3574 }; 3480 };
3575 3481
3576 fastrpc { <<
3577 compa <<
3578 qcom, <<
3579 label <<
3580 qcom, <<
3581 #addr <<
3582 #size <<
3583 <<
3584 cb@5 <<
3585 <<
3586 <<
3587 <<
3588 }; <<
3589 <<
3590 cb@6 <<
3591 <<
3592 <<
3593 <<
3594 }; <<
3595 <<
3596 cb@7 <<
3597 <<
3598 <<
3599 <<
3600 }; <<
3601 <<
3602 cb@8 <<
3603 <<
3604 <<
3605 <<
3606 }; <<
3607 <<
3608 cb@9 <<
3609 <<
3610 <<
3611 <<
3612 }; <<
3613 <<
3614 cb@10 <<
3615 <<
3616 <<
3617 <<
3618 }; <<
3619 <<
3620 cb@11 <<
3621 <<
3622 <<
3623 <<
3624 }; <<
3625 <<
3626 cb@12 <<
3627 <<
3628 <<
3629 <<
3630 }; <<
3631 }; <<
3632 }; 3482 };
3633 }; 3483 };
3634 3484
3635 apcs_glb: mailbox@9820000 { 3485 apcs_glb: mailbox@9820000 {
3636 compatible = "qcom,ms 3486 compatible = "qcom,msm8996-apcs-hmss-global";
3637 reg = <0x09820000 0x1 3487 reg = <0x09820000 0x1000>;
3638 3488
3639 #mbox-cells = <1>; 3489 #mbox-cells = <1>;
3640 #clock-cells = <0>; <<
3641 }; 3490 };
3642 3491
3643 timer@9840000 { 3492 timer@9840000 {
3644 #address-cells = <1>; 3493 #address-cells = <1>;
3645 #size-cells = <1>; 3494 #size-cells = <1>;
3646 ranges; 3495 ranges;
3647 compatible = "arm,arm 3496 compatible = "arm,armv7-timer-mem";
3648 reg = <0x09840000 0x1 3497 reg = <0x09840000 0x1000>;
3649 clock-frequency = <19 3498 clock-frequency = <19200000>;
3650 3499
3651 frame@9850000 { 3500 frame@9850000 {
3652 frame-number 3501 frame-number = <0>;
3653 interrupts = 3502 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
3654 3503 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
3655 reg = <0x0985 3504 reg = <0x09850000 0x1000>,
3656 <0x0986 3505 <0x09860000 0x1000>;
3657 }; 3506 };
3658 3507
3659 frame@9870000 { 3508 frame@9870000 {
3660 frame-number 3509 frame-number = <1>;
3661 interrupts = 3510 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
3662 reg = <0x0987 3511 reg = <0x09870000 0x1000>;
3663 status = "dis 3512 status = "disabled";
3664 }; 3513 };
3665 3514
3666 frame@9880000 { 3515 frame@9880000 {
3667 frame-number 3516 frame-number = <2>;
3668 interrupts = 3517 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
3669 reg = <0x0988 3518 reg = <0x09880000 0x1000>;
3670 status = "dis 3519 status = "disabled";
3671 }; 3520 };
3672 3521
3673 frame@9890000 { 3522 frame@9890000 {
3674 frame-number 3523 frame-number = <3>;
3675 interrupts = 3524 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
3676 reg = <0x0989 3525 reg = <0x09890000 0x1000>;
3677 status = "dis 3526 status = "disabled";
3678 }; 3527 };
3679 3528
3680 frame@98a0000 { 3529 frame@98a0000 {
3681 frame-number 3530 frame-number = <4>;
3682 interrupts = 3531 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
3683 reg = <0x098a 3532 reg = <0x098a0000 0x1000>;
3684 status = "dis 3533 status = "disabled";
3685 }; 3534 };
3686 3535
3687 frame@98b0000 { 3536 frame@98b0000 {
3688 frame-number 3537 frame-number = <5>;
3689 interrupts = 3538 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
3690 reg = <0x098b 3539 reg = <0x098b0000 0x1000>;
3691 status = "dis 3540 status = "disabled";
3692 }; 3541 };
3693 3542
3694 frame@98c0000 { 3543 frame@98c0000 {
3695 frame-number 3544 frame-number = <6>;
3696 interrupts = 3545 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
3697 reg = <0x098c 3546 reg = <0x098c0000 0x1000>;
3698 status = "dis 3547 status = "disabled";
3699 }; 3548 };
3700 }; 3549 };
3701 3550
3702 saw3: syscon@9a10000 { 3551 saw3: syscon@9a10000 {
3703 compatible = "syscon" 3552 compatible = "syscon";
3704 reg = <0x09a10000 0x1 3553 reg = <0x09a10000 0x1000>;
3705 }; 3554 };
3706 3555
3707 cbf: clock-controller@9a11000 <<
3708 compatible = "qcom,ms <<
3709 reg = <0x09a11000 0x1 <<
3710 clocks = <&rpmcc RPM_ <<
3711 #clock-cells = <0>; <<
3712 #interconnect-cells = <<
3713 }; <<
3714 <<
3715 intc: interrupt-controller@9b 3556 intc: interrupt-controller@9bc0000 {
3716 compatible = "qcom,ms 3557 compatible = "qcom,msm8996-gic-v3", "arm,gic-v3";
3717 #interrupt-cells = <3 3558 #interrupt-cells = <3>;
3718 interrupt-controller; 3559 interrupt-controller;
3719 #redistributor-region 3560 #redistributor-regions = <1>;
3720 redistributor-stride 3561 redistributor-stride = <0x0 0x40000>;
3721 reg = <0x09bc0000 0x1 3562 reg = <0x09bc0000 0x10000>,
3722 <0x09c00000 0x1 3563 <0x09c00000 0x100000>;
3723 interrupts = <GIC_PPI 3564 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
3724 }; 3565 };
3725 }; 3566 };
3726 3567
3727 sound: sound { 3568 sound: sound {
3728 }; 3569 };
3729 3570
3730 thermal-zones { 3571 thermal-zones {
3731 cpu0-thermal { 3572 cpu0-thermal {
3732 polling-delay-passive 3573 polling-delay-passive = <250>;
>> 3574 polling-delay = <1000>;
3733 3575
3734 thermal-sensors = <&t 3576 thermal-sensors = <&tsens0 3>;
3735 3577
3736 trips { 3578 trips {
3737 cpu0_alert0: 3579 cpu0_alert0: trip-point0 {
3738 tempe 3580 temperature = <75000>;
3739 hyste 3581 hysteresis = <2000>;
3740 type 3582 type = "passive";
3741 }; 3583 };
3742 3584
3743 cpu0_crit: cp !! 3585 cpu0_crit: cpu_crit {
3744 tempe 3586 temperature = <110000>;
3745 hyste 3587 hysteresis = <2000>;
3746 type 3588 type = "critical";
3747 }; 3589 };
3748 }; 3590 };
3749 }; 3591 };
3750 3592
3751 cpu1-thermal { 3593 cpu1-thermal {
3752 polling-delay-passive 3594 polling-delay-passive = <250>;
>> 3595 polling-delay = <1000>;
3753 3596
3754 thermal-sensors = <&t 3597 thermal-sensors = <&tsens0 5>;
3755 3598
3756 trips { 3599 trips {
3757 cpu1_alert0: 3600 cpu1_alert0: trip-point0 {
3758 tempe 3601 temperature = <75000>;
3759 hyste 3602 hysteresis = <2000>;
3760 type 3603 type = "passive";
3761 }; 3604 };
3762 3605
3763 cpu1_crit: cp !! 3606 cpu1_crit: cpu_crit {
3764 tempe 3607 temperature = <110000>;
3765 hyste 3608 hysteresis = <2000>;
3766 type 3609 type = "critical";
3767 }; 3610 };
3768 }; 3611 };
3769 }; 3612 };
3770 3613
3771 cpu2-thermal { 3614 cpu2-thermal {
3772 polling-delay-passive 3615 polling-delay-passive = <250>;
>> 3616 polling-delay = <1000>;
3773 3617
3774 thermal-sensors = <&t 3618 thermal-sensors = <&tsens0 8>;
3775 3619
3776 trips { 3620 trips {
3777 cpu2_alert0: 3621 cpu2_alert0: trip-point0 {
3778 tempe 3622 temperature = <75000>;
3779 hyste 3623 hysteresis = <2000>;
3780 type 3624 type = "passive";
3781 }; 3625 };
3782 3626
3783 cpu2_crit: cp !! 3627 cpu2_crit: cpu_crit {
3784 tempe 3628 temperature = <110000>;
3785 hyste 3629 hysteresis = <2000>;
3786 type 3630 type = "critical";
3787 }; 3631 };
3788 }; 3632 };
3789 }; 3633 };
3790 3634
3791 cpu3-thermal { 3635 cpu3-thermal {
3792 polling-delay-passive 3636 polling-delay-passive = <250>;
>> 3637 polling-delay = <1000>;
3793 3638
3794 thermal-sensors = <&t 3639 thermal-sensors = <&tsens0 10>;
3795 3640
3796 trips { 3641 trips {
3797 cpu3_alert0: 3642 cpu3_alert0: trip-point0 {
3798 tempe 3643 temperature = <75000>;
3799 hyste 3644 hysteresis = <2000>;
3800 type 3645 type = "passive";
3801 }; 3646 };
3802 3647
3803 cpu3_crit: cp !! 3648 cpu3_crit: cpu_crit {
3804 tempe 3649 temperature = <110000>;
3805 hyste 3650 hysteresis = <2000>;
3806 type 3651 type = "critical";
3807 }; 3652 };
3808 }; 3653 };
3809 }; 3654 };
3810 3655
3811 gpu-top-thermal { 3656 gpu-top-thermal {
3812 polling-delay-passive 3657 polling-delay-passive = <250>;
>> 3658 polling-delay = <1000>;
3813 3659
3814 thermal-sensors = <&t 3660 thermal-sensors = <&tsens1 6>;
3815 3661
3816 trips { 3662 trips {
3817 gpu1_alert0: 3663 gpu1_alert0: trip-point0 {
3818 tempe 3664 temperature = <90000>;
3819 hyste 3665 hysteresis = <2000>;
3820 type 3666 type = "passive";
3821 }; 3667 };
3822 }; 3668 };
3823 3669
3824 cooling-maps { 3670 cooling-maps {
3825 map0 { 3671 map0 {
3826 trip 3672 trip = <&gpu1_alert0>;
3827 cooli 3673 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3828 }; 3674 };
3829 }; 3675 };
3830 }; 3676 };
3831 3677
3832 gpu-bottom-thermal { 3678 gpu-bottom-thermal {
3833 polling-delay-passive 3679 polling-delay-passive = <250>;
>> 3680 polling-delay = <1000>;
3834 3681
3835 thermal-sensors = <&t 3682 thermal-sensors = <&tsens1 7>;
3836 3683
3837 trips { 3684 trips {
3838 gpu2_alert0: 3685 gpu2_alert0: trip-point0 {
3839 tempe 3686 temperature = <90000>;
3840 hyste 3687 hysteresis = <2000>;
3841 type 3688 type = "passive";
3842 }; 3689 };
3843 }; 3690 };
3844 3691
3845 cooling-maps { 3692 cooling-maps {
3846 map0 { 3693 map0 {
3847 trip 3694 trip = <&gpu2_alert0>;
3848 cooli 3695 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3849 }; 3696 };
3850 }; 3697 };
3851 }; 3698 };
3852 3699
3853 m4m-thermal { 3700 m4m-thermal {
3854 polling-delay-passive 3701 polling-delay-passive = <250>;
>> 3702 polling-delay = <1000>;
3855 3703
3856 thermal-sensors = <&t 3704 thermal-sensors = <&tsens0 1>;
3857 3705
3858 trips { 3706 trips {
3859 m4m_alert0: t 3707 m4m_alert0: trip-point0 {
3860 tempe 3708 temperature = <90000>;
3861 hyste 3709 hysteresis = <2000>;
3862 type 3710 type = "hot";
3863 }; 3711 };
3864 }; 3712 };
3865 }; 3713 };
3866 3714
3867 l3-or-venus-thermal { 3715 l3-or-venus-thermal {
3868 polling-delay-passive 3716 polling-delay-passive = <250>;
>> 3717 polling-delay = <1000>;
3869 3718
3870 thermal-sensors = <&t 3719 thermal-sensors = <&tsens0 2>;
3871 3720
3872 trips { 3721 trips {
3873 l3_or_venus_a 3722 l3_or_venus_alert0: trip-point0 {
3874 tempe 3723 temperature = <90000>;
3875 hyste 3724 hysteresis = <2000>;
3876 type 3725 type = "hot";
3877 }; 3726 };
3878 }; 3727 };
3879 }; 3728 };
3880 3729
3881 cluster0-l2-thermal { 3730 cluster0-l2-thermal {
3882 polling-delay-passive 3731 polling-delay-passive = <250>;
>> 3732 polling-delay = <1000>;
3883 3733
3884 thermal-sensors = <&t 3734 thermal-sensors = <&tsens0 7>;
3885 3735
3886 trips { 3736 trips {
3887 cluster0_l2_a 3737 cluster0_l2_alert0: trip-point0 {
3888 tempe 3738 temperature = <90000>;
3889 hyste 3739 hysteresis = <2000>;
3890 type 3740 type = "hot";
3891 }; 3741 };
3892 }; 3742 };
3893 }; 3743 };
3894 3744
3895 cluster1-l2-thermal { 3745 cluster1-l2-thermal {
3896 polling-delay-passive 3746 polling-delay-passive = <250>;
>> 3747 polling-delay = <1000>;
3897 3748
3898 thermal-sensors = <&t 3749 thermal-sensors = <&tsens0 12>;
3899 3750
3900 trips { 3751 trips {
3901 cluster1_l2_a 3752 cluster1_l2_alert0: trip-point0 {
3902 tempe 3753 temperature = <90000>;
3903 hyste 3754 hysteresis = <2000>;
3904 type 3755 type = "hot";
3905 }; 3756 };
3906 }; 3757 };
3907 }; 3758 };
3908 3759
3909 camera-thermal { 3760 camera-thermal {
3910 polling-delay-passive 3761 polling-delay-passive = <250>;
>> 3762 polling-delay = <1000>;
3911 3763
3912 thermal-sensors = <&t 3764 thermal-sensors = <&tsens1 1>;
3913 3765
3914 trips { 3766 trips {
3915 camera_alert0 3767 camera_alert0: trip-point0 {
3916 tempe 3768 temperature = <90000>;
3917 hyste 3769 hysteresis = <2000>;
3918 type 3770 type = "hot";
3919 }; 3771 };
3920 }; 3772 };
3921 }; 3773 };
3922 3774
3923 q6-dsp-thermal { 3775 q6-dsp-thermal {
3924 polling-delay-passive 3776 polling-delay-passive = <250>;
>> 3777 polling-delay = <1000>;
3925 3778
3926 thermal-sensors = <&t 3779 thermal-sensors = <&tsens1 2>;
3927 3780
3928 trips { 3781 trips {
3929 q6_dsp_alert0 3782 q6_dsp_alert0: trip-point0 {
3930 tempe 3783 temperature = <90000>;
3931 hyste 3784 hysteresis = <2000>;
3932 type 3785 type = "hot";
3933 }; 3786 };
3934 }; 3787 };
3935 }; 3788 };
3936 3789
3937 mem-thermal { 3790 mem-thermal {
3938 polling-delay-passive 3791 polling-delay-passive = <250>;
>> 3792 polling-delay = <1000>;
3939 3793
3940 thermal-sensors = <&t 3794 thermal-sensors = <&tsens1 3>;
3941 3795
3942 trips { 3796 trips {
3943 mem_alert0: t 3797 mem_alert0: trip-point0 {
3944 tempe 3798 temperature = <90000>;
3945 hyste 3799 hysteresis = <2000>;
3946 type 3800 type = "hot";
3947 }; 3801 };
3948 }; 3802 };
3949 }; 3803 };
3950 3804
3951 modemtx-thermal { 3805 modemtx-thermal {
3952 polling-delay-passive 3806 polling-delay-passive = <250>;
>> 3807 polling-delay = <1000>;
3953 3808
3954 thermal-sensors = <&t 3809 thermal-sensors = <&tsens1 4>;
3955 3810
3956 trips { 3811 trips {
3957 modemtx_alert 3812 modemtx_alert0: trip-point0 {
3958 tempe 3813 temperature = <90000>;
3959 hyste 3814 hysteresis = <2000>;
3960 type 3815 type = "hot";
3961 }; 3816 };
3962 }; 3817 };
3963 }; 3818 };
3964 }; 3819 };
3965 3820
3966 timer { 3821 timer {
3967 compatible = "arm,armv8-timer 3822 compatible = "arm,armv8-timer";
3968 interrupts = <GIC_PPI 13 IRQ_ 3823 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
3969 <GIC_PPI 14 IRQ_ 3824 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
3970 <GIC_PPI 11 IRQ_ 3825 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
3971 <GIC_PPI 10 IRQ_ 3826 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
3972 }; 3827 };
3973 }; 3828 };
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