1 // SPDX-License-Identifier: GPL-2.0-only 1 // SPDX-License-Identifier: GPL-2.0-only
2 /* 2 /*
3 * Copyright (c) 2014-2015, The Linux Foundati 3 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
4 */ 4 */
5 5
6 #include <dt-bindings/interrupt-controller/arm 6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,gcc-msm8996.h 7 #include <dt-bindings/clock/qcom,gcc-msm8996.h>
8 #include <dt-bindings/clock/qcom,mmcc-msm8996. 8 #include <dt-bindings/clock/qcom,mmcc-msm8996.h>
9 #include <dt-bindings/clock/qcom,rpmcc.h> 9 #include <dt-bindings/clock/qcom,rpmcc.h>
10 #include <dt-bindings/interconnect/qcom,msm899 10 #include <dt-bindings/interconnect/qcom,msm8996.h>
11 #include <dt-bindings/interconnect/qcom,msm899 <<
12 #include <dt-bindings/firmware/qcom,scm.h> <<
13 #include <dt-bindings/gpio/gpio.h> 11 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/power/qcom-rpmpd.h> 12 #include <dt-bindings/power/qcom-rpmpd.h>
15 #include <dt-bindings/soc/qcom,apr.h> 13 #include <dt-bindings/soc/qcom,apr.h>
16 #include <dt-bindings/thermal/thermal.h> 14 #include <dt-bindings/thermal/thermal.h>
17 15
18 / { 16 / {
19 interrupt-parent = <&intc>; 17 interrupt-parent = <&intc>;
20 18
21 #address-cells = <2>; 19 #address-cells = <2>;
22 #size-cells = <2>; 20 #size-cells = <2>;
23 21
24 chosen { }; 22 chosen { };
25 23
26 clocks { 24 clocks {
27 xo_board: xo-board { 25 xo_board: xo-board {
28 compatible = "fixed-cl 26 compatible = "fixed-clock";
29 #clock-cells = <0>; 27 #clock-cells = <0>;
30 clock-frequency = <192 28 clock-frequency = <19200000>;
31 clock-output-names = " 29 clock-output-names = "xo_board";
32 }; 30 };
33 31
34 sleep_clk: sleep-clk { 32 sleep_clk: sleep-clk {
35 compatible = "fixed-cl 33 compatible = "fixed-clock";
36 #clock-cells = <0>; 34 #clock-cells = <0>;
37 clock-frequency = <327 35 clock-frequency = <32764>;
38 clock-output-names = " 36 clock-output-names = "sleep_clk";
39 }; 37 };
40 }; 38 };
41 39
42 cpus { 40 cpus {
43 #address-cells = <2>; 41 #address-cells = <2>;
44 #size-cells = <0>; 42 #size-cells = <0>;
45 43
46 CPU0: cpu@0 { 44 CPU0: cpu@0 {
47 device_type = "cpu"; 45 device_type = "cpu";
48 compatible = "qcom,kry 46 compatible = "qcom,kryo";
49 reg = <0x0 0x0>; 47 reg = <0x0 0x0>;
50 enable-method = "psci" 48 enable-method = "psci";
51 cpu-idle-states = <&CP 49 cpu-idle-states = <&CPU_SLEEP_0>;
52 capacity-dmips-mhz = < 50 capacity-dmips-mhz = <1024>;
53 clocks = <&kryocc 0>; 51 clocks = <&kryocc 0>;
54 interconnects = <&cbf <<
55 operating-points-v2 = 52 operating-points-v2 = <&cluster0_opp>;
56 #cooling-cells = <2>; 53 #cooling-cells = <2>;
57 next-level-cache = <&L 54 next-level-cache = <&L2_0>;
58 L2_0: l2-cache { 55 L2_0: l2-cache {
59 compatible = " 56 compatible = "cache";
60 cache-level = 57 cache-level = <2>;
61 cache-unified; 58 cache-unified;
62 }; 59 };
63 }; 60 };
64 61
65 CPU1: cpu@1 { 62 CPU1: cpu@1 {
66 device_type = "cpu"; 63 device_type = "cpu";
67 compatible = "qcom,kry 64 compatible = "qcom,kryo";
68 reg = <0x0 0x1>; 65 reg = <0x0 0x1>;
69 enable-method = "psci" 66 enable-method = "psci";
70 cpu-idle-states = <&CP 67 cpu-idle-states = <&CPU_SLEEP_0>;
71 capacity-dmips-mhz = < 68 capacity-dmips-mhz = <1024>;
72 clocks = <&kryocc 0>; 69 clocks = <&kryocc 0>;
73 interconnects = <&cbf <<
74 operating-points-v2 = 70 operating-points-v2 = <&cluster0_opp>;
75 #cooling-cells = <2>; 71 #cooling-cells = <2>;
76 next-level-cache = <&L 72 next-level-cache = <&L2_0>;
77 }; 73 };
78 74
79 CPU2: cpu@100 { 75 CPU2: cpu@100 {
80 device_type = "cpu"; 76 device_type = "cpu";
81 compatible = "qcom,kry 77 compatible = "qcom,kryo";
82 reg = <0x0 0x100>; 78 reg = <0x0 0x100>;
83 enable-method = "psci" 79 enable-method = "psci";
84 cpu-idle-states = <&CP 80 cpu-idle-states = <&CPU_SLEEP_0>;
85 capacity-dmips-mhz = < 81 capacity-dmips-mhz = <1024>;
86 clocks = <&kryocc 1>; 82 clocks = <&kryocc 1>;
87 interconnects = <&cbf <<
88 operating-points-v2 = 83 operating-points-v2 = <&cluster1_opp>;
89 #cooling-cells = <2>; 84 #cooling-cells = <2>;
90 next-level-cache = <&L 85 next-level-cache = <&L2_1>;
91 L2_1: l2-cache { 86 L2_1: l2-cache {
92 compatible = " 87 compatible = "cache";
93 cache-level = 88 cache-level = <2>;
94 cache-unified; 89 cache-unified;
95 }; 90 };
96 }; 91 };
97 92
98 CPU3: cpu@101 { 93 CPU3: cpu@101 {
99 device_type = "cpu"; 94 device_type = "cpu";
100 compatible = "qcom,kry 95 compatible = "qcom,kryo";
101 reg = <0x0 0x101>; 96 reg = <0x0 0x101>;
102 enable-method = "psci" 97 enable-method = "psci";
103 cpu-idle-states = <&CP 98 cpu-idle-states = <&CPU_SLEEP_0>;
104 capacity-dmips-mhz = < 99 capacity-dmips-mhz = <1024>;
105 clocks = <&kryocc 1>; 100 clocks = <&kryocc 1>;
106 interconnects = <&cbf <<
107 operating-points-v2 = 101 operating-points-v2 = <&cluster1_opp>;
108 #cooling-cells = <2>; 102 #cooling-cells = <2>;
109 next-level-cache = <&L 103 next-level-cache = <&L2_1>;
110 }; 104 };
111 105
112 cpu-map { 106 cpu-map {
113 cluster0 { 107 cluster0 {
114 core0 { 108 core0 {
115 cpu = 109 cpu = <&CPU0>;
116 }; 110 };
117 111
118 core1 { 112 core1 {
119 cpu = 113 cpu = <&CPU1>;
120 }; 114 };
121 }; 115 };
122 116
123 cluster1 { 117 cluster1 {
124 core0 { 118 core0 {
125 cpu = 119 cpu = <&CPU2>;
126 }; 120 };
127 121
128 core1 { 122 core1 {
129 cpu = 123 cpu = <&CPU3>;
130 }; 124 };
131 }; 125 };
132 }; 126 };
133 127
134 idle-states { 128 idle-states {
135 entry-method = "psci"; 129 entry-method = "psci";
136 130
137 CPU_SLEEP_0: cpu-sleep 131 CPU_SLEEP_0: cpu-sleep-0 {
138 compatible = " 132 compatible = "arm,idle-state";
139 idle-state-nam 133 idle-state-name = "standalone-power-collapse";
140 arm,psci-suspe 134 arm,psci-suspend-param = <0x00000004>;
141 entry-latency- 135 entry-latency-us = <130>;
142 exit-latency-u 136 exit-latency-us = <80>;
143 min-residency- 137 min-residency-us = <300>;
144 }; 138 };
145 }; 139 };
146 }; 140 };
147 141
148 cluster0_opp: opp-table-cluster0 { 142 cluster0_opp: opp-table-cluster0 {
149 compatible = "operating-points 143 compatible = "operating-points-v2-kryo-cpu";
150 nvmem-cells = <&speedbin_efuse 144 nvmem-cells = <&speedbin_efuse>;
151 opp-shared; 145 opp-shared;
152 146
153 /* Nominal fmax for now */ 147 /* Nominal fmax for now */
154 opp-307200000 { 148 opp-307200000 {
155 opp-hz = /bits/ 64 <30 149 opp-hz = /bits/ 64 <307200000>;
156 opp-supported-hw = <0x 150 opp-supported-hw = <0xf>;
157 clock-latency-ns = <20 151 clock-latency-ns = <200000>;
158 opp-peak-kBps = <30720 <<
159 }; 152 };
160 opp-422400000 { 153 opp-422400000 {
161 opp-hz = /bits/ 64 <42 154 opp-hz = /bits/ 64 <422400000>;
162 opp-supported-hw = <0x 155 opp-supported-hw = <0xf>;
163 clock-latency-ns = <20 156 clock-latency-ns = <200000>;
164 opp-peak-kBps = <30720 <<
165 }; 157 };
166 opp-480000000 { 158 opp-480000000 {
167 opp-hz = /bits/ 64 <48 159 opp-hz = /bits/ 64 <480000000>;
168 opp-supported-hw = <0x 160 opp-supported-hw = <0xf>;
169 clock-latency-ns = <20 161 clock-latency-ns = <200000>;
170 opp-peak-kBps = <30720 <<
171 }; 162 };
172 opp-556800000 { 163 opp-556800000 {
173 opp-hz = /bits/ 64 <55 164 opp-hz = /bits/ 64 <556800000>;
174 opp-supported-hw = <0x 165 opp-supported-hw = <0xf>;
175 clock-latency-ns = <20 166 clock-latency-ns = <200000>;
176 opp-peak-kBps = <30720 <<
177 }; 167 };
178 opp-652800000 { 168 opp-652800000 {
179 opp-hz = /bits/ 64 <65 169 opp-hz = /bits/ 64 <652800000>;
180 opp-supported-hw = <0x 170 opp-supported-hw = <0xf>;
181 clock-latency-ns = <20 171 clock-latency-ns = <200000>;
182 opp-peak-kBps = <38400 <<
183 }; 172 };
184 opp-729600000 { 173 opp-729600000 {
185 opp-hz = /bits/ 64 <72 174 opp-hz = /bits/ 64 <729600000>;
186 opp-supported-hw = <0x 175 opp-supported-hw = <0xf>;
187 clock-latency-ns = <20 176 clock-latency-ns = <200000>;
188 opp-peak-kBps = <46080 <<
189 }; 177 };
190 opp-844800000 { 178 opp-844800000 {
191 opp-hz = /bits/ 64 <84 179 opp-hz = /bits/ 64 <844800000>;
192 opp-supported-hw = <0x 180 opp-supported-hw = <0xf>;
193 clock-latency-ns = <20 181 clock-latency-ns = <200000>;
194 opp-peak-kBps = <53760 <<
195 }; 182 };
196 opp-960000000 { 183 opp-960000000 {
197 opp-hz = /bits/ 64 <96 184 opp-hz = /bits/ 64 <960000000>;
198 opp-supported-hw = <0x 185 opp-supported-hw = <0xf>;
199 clock-latency-ns = <20 186 clock-latency-ns = <200000>;
200 opp-peak-kBps = <67200 <<
201 }; 187 };
202 opp-1036800000 { 188 opp-1036800000 {
203 opp-hz = /bits/ 64 <10 189 opp-hz = /bits/ 64 <1036800000>;
204 opp-supported-hw = <0x 190 opp-supported-hw = <0xf>;
205 clock-latency-ns = <20 191 clock-latency-ns = <200000>;
206 opp-peak-kBps = <67200 <<
207 }; 192 };
208 opp-1113600000 { 193 opp-1113600000 {
209 opp-hz = /bits/ 64 <11 194 opp-hz = /bits/ 64 <1113600000>;
210 opp-supported-hw = <0x 195 opp-supported-hw = <0xf>;
211 clock-latency-ns = <20 196 clock-latency-ns = <200000>;
212 opp-peak-kBps = <82560 <<
213 }; 197 };
214 opp-1190400000 { 198 opp-1190400000 {
215 opp-hz = /bits/ 64 <11 199 opp-hz = /bits/ 64 <1190400000>;
216 opp-supported-hw = <0x 200 opp-supported-hw = <0xf>;
217 clock-latency-ns = <20 201 clock-latency-ns = <200000>;
218 opp-peak-kBps = <82560 <<
219 }; 202 };
220 opp-1228800000 { 203 opp-1228800000 {
221 opp-hz = /bits/ 64 <12 204 opp-hz = /bits/ 64 <1228800000>;
222 opp-supported-hw = <0x 205 opp-supported-hw = <0xf>;
223 clock-latency-ns = <20 206 clock-latency-ns = <200000>;
224 opp-peak-kBps = <90240 <<
225 }; 207 };
226 opp-1324800000 { 208 opp-1324800000 {
227 opp-hz = /bits/ 64 <13 209 opp-hz = /bits/ 64 <1324800000>;
228 opp-supported-hw = <0x 210 opp-supported-hw = <0xd>;
229 clock-latency-ns = <20 211 clock-latency-ns = <200000>;
230 opp-peak-kBps = <10560 <<
231 }; 212 };
232 opp-1363200000 { 213 opp-1363200000 {
233 opp-hz = /bits/ 64 <13 214 opp-hz = /bits/ 64 <1363200000>;
234 opp-supported-hw = <0x 215 opp-supported-hw = <0x2>;
235 clock-latency-ns = <20 216 clock-latency-ns = <200000>;
236 opp-peak-kBps = <11328 <<
237 }; 217 };
238 opp-1401600000 { 218 opp-1401600000 {
239 opp-hz = /bits/ 64 <14 219 opp-hz = /bits/ 64 <1401600000>;
240 opp-supported-hw = <0x 220 opp-supported-hw = <0xd>;
241 clock-latency-ns = <20 221 clock-latency-ns = <200000>;
242 opp-peak-kBps = <11328 <<
243 }; 222 };
244 opp-1478400000 { 223 opp-1478400000 {
245 opp-hz = /bits/ 64 <14 224 opp-hz = /bits/ 64 <1478400000>;
246 opp-supported-hw = <0x 225 opp-supported-hw = <0x9>;
247 clock-latency-ns = <20 226 clock-latency-ns = <200000>;
248 opp-peak-kBps = <11904 <<
249 }; 227 };
250 opp-1497600000 { 228 opp-1497600000 {
251 opp-hz = /bits/ 64 <14 229 opp-hz = /bits/ 64 <1497600000>;
252 opp-supported-hw = <0x 230 opp-supported-hw = <0x04>;
253 clock-latency-ns = <20 231 clock-latency-ns = <200000>;
254 opp-peak-kBps = <13056 <<
255 }; 232 };
256 opp-1593600000 { 233 opp-1593600000 {
257 opp-hz = /bits/ 64 <15 234 opp-hz = /bits/ 64 <1593600000>;
258 opp-supported-hw = <0x 235 opp-supported-hw = <0x9>;
259 clock-latency-ns = <20 236 clock-latency-ns = <200000>;
260 opp-peak-kBps = <13824 <<
261 }; 237 };
262 }; 238 };
263 239
264 cluster1_opp: opp-table-cluster1 { 240 cluster1_opp: opp-table-cluster1 {
265 compatible = "operating-points 241 compatible = "operating-points-v2-kryo-cpu";
266 nvmem-cells = <&speedbin_efuse 242 nvmem-cells = <&speedbin_efuse>;
267 opp-shared; 243 opp-shared;
268 244
269 /* Nominal fmax for now */ 245 /* Nominal fmax for now */
270 opp-307200000 { 246 opp-307200000 {
271 opp-hz = /bits/ 64 <30 247 opp-hz = /bits/ 64 <307200000>;
272 opp-supported-hw = <0x 248 opp-supported-hw = <0xf>;
273 clock-latency-ns = <20 249 clock-latency-ns = <200000>;
274 opp-peak-kBps = <30720 <<
275 }; 250 };
276 opp-403200000 { 251 opp-403200000 {
277 opp-hz = /bits/ 64 <40 252 opp-hz = /bits/ 64 <403200000>;
278 opp-supported-hw = <0x 253 opp-supported-hw = <0xf>;
279 clock-latency-ns = <20 254 clock-latency-ns = <200000>;
280 opp-peak-kBps = <30720 <<
281 }; 255 };
282 opp-480000000 { 256 opp-480000000 {
283 opp-hz = /bits/ 64 <48 257 opp-hz = /bits/ 64 <480000000>;
284 opp-supported-hw = <0x 258 opp-supported-hw = <0xf>;
285 clock-latency-ns = <20 259 clock-latency-ns = <200000>;
286 opp-peak-kBps = <30720 <<
287 }; 260 };
288 opp-556800000 { 261 opp-556800000 {
289 opp-hz = /bits/ 64 <55 262 opp-hz = /bits/ 64 <556800000>;
290 opp-supported-hw = <0x 263 opp-supported-hw = <0xf>;
291 clock-latency-ns = <20 264 clock-latency-ns = <200000>;
292 opp-peak-kBps = <30720 <<
293 }; 265 };
294 opp-652800000 { 266 opp-652800000 {
295 opp-hz = /bits/ 64 <65 267 opp-hz = /bits/ 64 <652800000>;
296 opp-supported-hw = <0x 268 opp-supported-hw = <0xf>;
297 clock-latency-ns = <20 269 clock-latency-ns = <200000>;
298 opp-peak-kBps = <30720 <<
299 }; 270 };
300 opp-729600000 { 271 opp-729600000 {
301 opp-hz = /bits/ 64 <72 272 opp-hz = /bits/ 64 <729600000>;
302 opp-supported-hw = <0x 273 opp-supported-hw = <0xf>;
303 clock-latency-ns = <20 274 clock-latency-ns = <200000>;
304 opp-peak-kBps = <30720 <<
305 }; 275 };
306 opp-806400000 { 276 opp-806400000 {
307 opp-hz = /bits/ 64 <80 277 opp-hz = /bits/ 64 <806400000>;
308 opp-supported-hw = <0x 278 opp-supported-hw = <0xf>;
309 clock-latency-ns = <20 279 clock-latency-ns = <200000>;
310 opp-peak-kBps = <38400 <<
311 }; 280 };
312 opp-883200000 { 281 opp-883200000 {
313 opp-hz = /bits/ 64 <88 282 opp-hz = /bits/ 64 <883200000>;
314 opp-supported-hw = <0x 283 opp-supported-hw = <0xf>;
315 clock-latency-ns = <20 284 clock-latency-ns = <200000>;
316 opp-peak-kBps = <46080 <<
317 }; 285 };
318 opp-940800000 { 286 opp-940800000 {
319 opp-hz = /bits/ 64 <94 287 opp-hz = /bits/ 64 <940800000>;
320 opp-supported-hw = <0x 288 opp-supported-hw = <0xf>;
321 clock-latency-ns = <20 289 clock-latency-ns = <200000>;
322 opp-peak-kBps = <53760 <<
323 }; 290 };
324 opp-1036800000 { 291 opp-1036800000 {
325 opp-hz = /bits/ 64 <10 292 opp-hz = /bits/ 64 <1036800000>;
326 opp-supported-hw = <0x 293 opp-supported-hw = <0xf>;
327 clock-latency-ns = <20 294 clock-latency-ns = <200000>;
328 opp-peak-kBps = <59520 <<
329 }; 295 };
330 opp-1113600000 { 296 opp-1113600000 {
331 opp-hz = /bits/ 64 <11 297 opp-hz = /bits/ 64 <1113600000>;
332 opp-supported-hw = <0x 298 opp-supported-hw = <0xf>;
333 clock-latency-ns = <20 299 clock-latency-ns = <200000>;
334 opp-peak-kBps = <67200 <<
335 }; 300 };
336 opp-1190400000 { 301 opp-1190400000 {
337 opp-hz = /bits/ 64 <11 302 opp-hz = /bits/ 64 <1190400000>;
338 opp-supported-hw = <0x 303 opp-supported-hw = <0xf>;
339 clock-latency-ns = <20 304 clock-latency-ns = <200000>;
340 opp-peak-kBps = <67200 <<
341 }; 305 };
342 opp-1248000000 { 306 opp-1248000000 {
343 opp-hz = /bits/ 64 <12 307 opp-hz = /bits/ 64 <1248000000>;
344 opp-supported-hw = <0x 308 opp-supported-hw = <0xf>;
345 clock-latency-ns = <20 309 clock-latency-ns = <200000>;
346 opp-peak-kBps = <74880 <<
347 }; 310 };
348 opp-1324800000 { 311 opp-1324800000 {
349 opp-hz = /bits/ 64 <13 312 opp-hz = /bits/ 64 <1324800000>;
350 opp-supported-hw = <0x 313 opp-supported-hw = <0xf>;
351 clock-latency-ns = <20 314 clock-latency-ns = <200000>;
352 opp-peak-kBps = <82560 <<
353 }; 315 };
354 opp-1401600000 { 316 opp-1401600000 {
355 opp-hz = /bits/ 64 <14 317 opp-hz = /bits/ 64 <1401600000>;
356 opp-supported-hw = <0x 318 opp-supported-hw = <0xf>;
357 clock-latency-ns = <20 319 clock-latency-ns = <200000>;
358 opp-peak-kBps = <90240 <<
359 }; 320 };
360 opp-1478400000 { 321 opp-1478400000 {
361 opp-hz = /bits/ 64 <14 322 opp-hz = /bits/ 64 <1478400000>;
362 opp-supported-hw = <0x 323 opp-supported-hw = <0xf>;
363 clock-latency-ns = <20 324 clock-latency-ns = <200000>;
364 opp-peak-kBps = <97920 <<
365 }; 325 };
366 opp-1555200000 { 326 opp-1555200000 {
367 opp-hz = /bits/ 64 <15 327 opp-hz = /bits/ 64 <1555200000>;
368 opp-supported-hw = <0x 328 opp-supported-hw = <0xf>;
369 clock-latency-ns = <20 329 clock-latency-ns = <200000>;
370 opp-peak-kBps = <10560 <<
371 }; 330 };
372 opp-1632000000 { 331 opp-1632000000 {
373 opp-hz = /bits/ 64 <16 332 opp-hz = /bits/ 64 <1632000000>;
374 opp-supported-hw = <0x 333 opp-supported-hw = <0xf>;
375 clock-latency-ns = <20 334 clock-latency-ns = <200000>;
376 opp-peak-kBps = <11904 <<
377 }; 335 };
378 opp-1708800000 { 336 opp-1708800000 {
379 opp-hz = /bits/ 64 <17 337 opp-hz = /bits/ 64 <1708800000>;
380 opp-supported-hw = <0x 338 opp-supported-hw = <0xf>;
381 clock-latency-ns = <20 339 clock-latency-ns = <200000>;
382 opp-peak-kBps = <12288 <<
383 }; 340 };
384 opp-1785600000 { 341 opp-1785600000 {
385 opp-hz = /bits/ 64 <17 342 opp-hz = /bits/ 64 <1785600000>;
386 opp-supported-hw = <0x 343 opp-supported-hw = <0xf>;
387 clock-latency-ns = <20 344 clock-latency-ns = <200000>;
388 opp-peak-kBps = <13056 <<
389 }; 345 };
390 opp-1804800000 { 346 opp-1804800000 {
391 opp-hz = /bits/ 64 <18 347 opp-hz = /bits/ 64 <1804800000>;
392 opp-supported-hw = <0x 348 opp-supported-hw = <0xe>;
393 clock-latency-ns = <20 349 clock-latency-ns = <200000>;
394 opp-peak-kBps = <13056 <<
395 }; 350 };
396 opp-1824000000 { 351 opp-1824000000 {
397 opp-hz = /bits/ 64 <18 352 opp-hz = /bits/ 64 <1824000000>;
398 opp-supported-hw = <0x 353 opp-supported-hw = <0x1>;
399 clock-latency-ns = <20 354 clock-latency-ns = <200000>;
400 opp-peak-kBps = <13824 <<
401 }; 355 };
402 opp-1900800000 { 356 opp-1900800000 {
403 opp-hz = /bits/ 64 <19 357 opp-hz = /bits/ 64 <1900800000>;
404 opp-supported-hw = <0x 358 opp-supported-hw = <0x4>;
405 clock-latency-ns = <20 359 clock-latency-ns = <200000>;
406 opp-peak-kBps = <13056 <<
407 }; 360 };
408 opp-1920000000 { 361 opp-1920000000 {
409 opp-hz = /bits/ 64 <19 362 opp-hz = /bits/ 64 <1920000000>;
410 opp-supported-hw = <0x 363 opp-supported-hw = <0x1>;
411 clock-latency-ns = <20 364 clock-latency-ns = <200000>;
412 opp-peak-kBps = <14592 <<
413 }; 365 };
414 opp-1996800000 { 366 opp-1996800000 {
415 opp-hz = /bits/ 64 <19 367 opp-hz = /bits/ 64 <1996800000>;
416 opp-supported-hw = <0x 368 opp-supported-hw = <0x1>;
417 clock-latency-ns = <20 369 clock-latency-ns = <200000>;
418 opp-peak-kBps = <15936 <<
419 }; 370 };
420 opp-2073600000 { 371 opp-2073600000 {
421 opp-hz = /bits/ 64 <20 372 opp-hz = /bits/ 64 <2073600000>;
422 opp-supported-hw = <0x 373 opp-supported-hw = <0x1>;
423 clock-latency-ns = <20 374 clock-latency-ns = <200000>;
424 opp-peak-kBps = <15936 <<
425 }; 375 };
426 opp-2150400000 { 376 opp-2150400000 {
427 opp-hz = /bits/ 64 <21 377 opp-hz = /bits/ 64 <2150400000>;
428 opp-supported-hw = <0x 378 opp-supported-hw = <0x1>;
429 clock-latency-ns = <20 379 clock-latency-ns = <200000>;
430 opp-peak-kBps = <15936 <<
431 }; 380 };
432 }; 381 };
433 382
434 firmware { 383 firmware {
435 scm { 384 scm {
436 compatible = "qcom,scm 385 compatible = "qcom,scm-msm8996", "qcom,scm";
437 qcom,dload-mode = <&tc 386 qcom,dload-mode = <&tcsr_2 0x13000>;
438 }; 387 };
439 }; 388 };
440 389
441 memory@80000000 { 390 memory@80000000 {
442 device_type = "memory"; 391 device_type = "memory";
443 /* We expect the bootloader to 392 /* We expect the bootloader to fill in the reg */
444 reg = <0x0 0x80000000 0x0 0x0> 393 reg = <0x0 0x80000000 0x0 0x0>;
445 }; 394 };
446 395
447 etm { <<
448 compatible = "qcom,coresight-r <<
449 <<
450 out-ports { <<
451 port { <<
452 modem_etm_out_ <<
453 remote <<
454 <&fu <<
455 }; <<
456 }; <<
457 }; <<
458 }; <<
459 <<
460 psci { 396 psci {
461 compatible = "arm,psci-1.0"; 397 compatible = "arm,psci-1.0";
462 method = "smc"; 398 method = "smc";
463 }; 399 };
464 400
465 rpm: remoteproc { <<
466 compatible = "qcom,msm8996-rpm <<
467 <<
468 glink-edge { <<
469 compatible = "qcom,gli <<
470 interrupts = <GIC_SPI <<
471 qcom,rpm-msg-ram = <&r <<
472 mboxes = <&apcs_glb 0> <<
473 <<
474 rpm_requests: rpm-requ <<
475 compatible = " <<
476 qcom,glink-cha <<
477 <<
478 rpmcc: clock-c <<
479 compat <<
480 #clock <<
481 clocks <<
482 clock- <<
483 }; <<
484 <<
485 rpmpd: power-c <<
486 compat <<
487 #power <<
488 operat <<
489 <<
490 rpmpd_ <<
491 <<
492 <<
493 <<
494 <<
495 <<
496 <<
497 <<
498 <<
499 <<
500 <<
501 <<
502 <<
503 <<
504 <<
505 <<
506 <<
507 <<
508 <<
509 <<
510 <<
511 <<
512 <<
513 <<
514 <<
515 <<
516 }; <<
517 }; <<
518 }; <<
519 }; <<
520 }; <<
521 <<
522 reserved-memory { 401 reserved-memory {
523 #address-cells = <2>; 402 #address-cells = <2>;
524 #size-cells = <2>; 403 #size-cells = <2>;
525 ranges; 404 ranges;
526 405
527 hyp_mem: memory@85800000 { 406 hyp_mem: memory@85800000 {
528 reg = <0x0 0x85800000 407 reg = <0x0 0x85800000 0x0 0x600000>;
529 no-map; 408 no-map;
530 }; 409 };
531 410
532 xbl_mem: memory@85e00000 { 411 xbl_mem: memory@85e00000 {
533 reg = <0x0 0x85e00000 412 reg = <0x0 0x85e00000 0x0 0x200000>;
534 no-map; 413 no-map;
535 }; 414 };
536 415
537 smem_mem: smem-mem@86000000 { 416 smem_mem: smem-mem@86000000 {
538 reg = <0x0 0x86000000 417 reg = <0x0 0x86000000 0x0 0x200000>;
539 no-map; 418 no-map;
540 }; 419 };
541 420
542 tz_mem: memory@86200000 { 421 tz_mem: memory@86200000 {
543 reg = <0x0 0x86200000 422 reg = <0x0 0x86200000 0x0 0x2600000>;
544 no-map; 423 no-map;
545 }; 424 };
546 425
547 rmtfs_mem: rmtfs { 426 rmtfs_mem: rmtfs {
548 compatible = "qcom,rmt 427 compatible = "qcom,rmtfs-mem";
549 428
550 size = <0x0 0x200000>; 429 size = <0x0 0x200000>;
551 alloc-ranges = <0x0 0x 430 alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>;
552 no-map; 431 no-map;
553 432
554 qcom,client-id = <1>; 433 qcom,client-id = <1>;
555 qcom,vmid = <QCOM_SCM_ !! 434 qcom,vmid = <15>;
556 }; 435 };
557 436
558 mpss_mem: mpss@88800000 { 437 mpss_mem: mpss@88800000 {
559 reg = <0x0 0x88800000 438 reg = <0x0 0x88800000 0x0 0x6200000>;
560 no-map; 439 no-map;
561 }; 440 };
562 441
563 adsp_mem: adsp@8ea00000 { 442 adsp_mem: adsp@8ea00000 {
564 reg = <0x0 0x8ea00000 443 reg = <0x0 0x8ea00000 0x0 0x1b00000>;
565 no-map; 444 no-map;
566 }; 445 };
567 446
568 slpi_mem: slpi@90500000 { 447 slpi_mem: slpi@90500000 {
569 reg = <0x0 0x90500000 448 reg = <0x0 0x90500000 0x0 0xa00000>;
570 no-map; 449 no-map;
571 }; 450 };
572 451
573 gpu_mem: gpu@90f00000 { 452 gpu_mem: gpu@90f00000 {
574 compatible = "shared-d 453 compatible = "shared-dma-pool";
575 reg = <0x0 0x90f00000 454 reg = <0x0 0x90f00000 0x0 0x100000>;
576 no-map; 455 no-map;
577 }; 456 };
578 457
579 venus_mem: venus@91000000 { 458 venus_mem: venus@91000000 {
580 reg = <0x0 0x91000000 459 reg = <0x0 0x91000000 0x0 0x500000>;
581 no-map; 460 no-map;
582 }; 461 };
583 462
584 mba_mem: mba@91500000 { 463 mba_mem: mba@91500000 {
585 reg = <0x0 0x91500000 464 reg = <0x0 0x91500000 0x0 0x200000>;
586 no-map; 465 no-map;
587 }; 466 };
588 467
589 mdata_mem: mpss-metadata { 468 mdata_mem: mpss-metadata {
590 alloc-ranges = <0x0 0x 469 alloc-ranges = <0x0 0xa0000000 0x0 0x20000000>;
591 size = <0x0 0x4000>; 470 size = <0x0 0x4000>;
592 no-map; 471 no-map;
593 }; 472 };
594 }; 473 };
595 474
>> 475 rpm-glink {
>> 476 compatible = "qcom,glink-rpm";
>> 477
>> 478 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
>> 479
>> 480 qcom,rpm-msg-ram = <&rpm_msg_ram>;
>> 481
>> 482 mboxes = <&apcs_glb 0>;
>> 483
>> 484 rpm_requests: rpm-requests {
>> 485 compatible = "qcom,rpm-msm8996";
>> 486 qcom,glink-channels = "rpm_requests";
>> 487
>> 488 rpmcc: clock-controller {
>> 489 compatible = "qcom,rpmcc-msm8996", "qcom,rpmcc";
>> 490 #clock-cells = <1>;
>> 491 clocks = <&xo_board>;
>> 492 clock-names = "xo";
>> 493 };
>> 494
>> 495 rpmpd: power-controller {
>> 496 compatible = "qcom,msm8996-rpmpd";
>> 497 #power-domain-cells = <1>;
>> 498 operating-points-v2 = <&rpmpd_opp_table>;
>> 499
>> 500 rpmpd_opp_table: opp-table {
>> 501 compatible = "operating-points-v2";
>> 502
>> 503 rpmpd_opp1: opp1 {
>> 504 opp-level = <1>;
>> 505 };
>> 506
>> 507 rpmpd_opp2: opp2 {
>> 508 opp-level = <2>;
>> 509 };
>> 510
>> 511 rpmpd_opp3: opp3 {
>> 512 opp-level = <3>;
>> 513 };
>> 514
>> 515 rpmpd_opp4: opp4 {
>> 516 opp-level = <4>;
>> 517 };
>> 518
>> 519 rpmpd_opp5: opp5 {
>> 520 opp-level = <5>;
>> 521 };
>> 522
>> 523 rpmpd_opp6: opp6 {
>> 524 opp-level = <6>;
>> 525 };
>> 526 };
>> 527 };
>> 528 };
>> 529 };
>> 530
596 smem { 531 smem {
597 compatible = "qcom,smem"; 532 compatible = "qcom,smem";
598 memory-region = <&smem_mem>; 533 memory-region = <&smem_mem>;
599 hwlocks = <&tcsr_mutex 3>; 534 hwlocks = <&tcsr_mutex 3>;
600 }; 535 };
601 536
602 smp2p-adsp { 537 smp2p-adsp {
603 compatible = "qcom,smp2p"; 538 compatible = "qcom,smp2p";
604 qcom,smem = <443>, <429>; 539 qcom,smem = <443>, <429>;
605 540
606 interrupts = <GIC_SPI 158 IRQ_ !! 541 interrupts = <0 158 IRQ_TYPE_EDGE_RISING>;
607 542
608 mboxes = <&apcs_glb 10>; 543 mboxes = <&apcs_glb 10>;
609 544
610 qcom,local-pid = <0>; 545 qcom,local-pid = <0>;
611 qcom,remote-pid = <2>; 546 qcom,remote-pid = <2>;
612 547
613 adsp_smp2p_out: master-kernel 548 adsp_smp2p_out: master-kernel {
614 qcom,entry-name = "mas 549 qcom,entry-name = "master-kernel";
615 #qcom,smem-state-cells 550 #qcom,smem-state-cells = <1>;
616 }; 551 };
617 552
618 adsp_smp2p_in: slave-kernel { 553 adsp_smp2p_in: slave-kernel {
619 qcom,entry-name = "sla 554 qcom,entry-name = "slave-kernel";
620 555
621 interrupt-controller; 556 interrupt-controller;
622 #interrupt-cells = <2> 557 #interrupt-cells = <2>;
623 }; 558 };
624 }; 559 };
625 560
626 smp2p-mpss { 561 smp2p-mpss {
627 compatible = "qcom,smp2p"; 562 compatible = "qcom,smp2p";
628 qcom,smem = <435>, <428>; 563 qcom,smem = <435>, <428>;
629 564
630 interrupts = <GIC_SPI 451 IRQ_ 565 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
631 566
632 mboxes = <&apcs_glb 14>; 567 mboxes = <&apcs_glb 14>;
633 568
634 qcom,local-pid = <0>; 569 qcom,local-pid = <0>;
635 qcom,remote-pid = <1>; 570 qcom,remote-pid = <1>;
636 571
637 mpss_smp2p_out: master-kernel 572 mpss_smp2p_out: master-kernel {
638 qcom,entry-name = "mas 573 qcom,entry-name = "master-kernel";
639 #qcom,smem-state-cells 574 #qcom,smem-state-cells = <1>;
640 }; 575 };
641 576
642 mpss_smp2p_in: slave-kernel { 577 mpss_smp2p_in: slave-kernel {
643 qcom,entry-name = "sla 578 qcom,entry-name = "slave-kernel";
644 579
645 interrupt-controller; 580 interrupt-controller;
646 #interrupt-cells = <2> 581 #interrupt-cells = <2>;
647 }; 582 };
648 }; 583 };
649 584
650 smp2p-slpi { 585 smp2p-slpi {
651 compatible = "qcom,smp2p"; 586 compatible = "qcom,smp2p";
652 qcom,smem = <481>, <430>; 587 qcom,smem = <481>, <430>;
653 588
654 interrupts = <GIC_SPI 178 IRQ_ 589 interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>;
655 590
656 mboxes = <&apcs_glb 26>; 591 mboxes = <&apcs_glb 26>;
657 592
658 qcom,local-pid = <0>; 593 qcom,local-pid = <0>;
659 qcom,remote-pid = <3>; 594 qcom,remote-pid = <3>;
660 595
661 slpi_smp2p_out: master-kernel 596 slpi_smp2p_out: master-kernel {
662 qcom,entry-name = "mas 597 qcom,entry-name = "master-kernel";
663 #qcom,smem-state-cells 598 #qcom,smem-state-cells = <1>;
664 }; 599 };
665 600
666 slpi_smp2p_in: slave-kernel { 601 slpi_smp2p_in: slave-kernel {
667 qcom,entry-name = "sla 602 qcom,entry-name = "slave-kernel";
668 603
669 interrupt-controller; 604 interrupt-controller;
670 #interrupt-cells = <2> 605 #interrupt-cells = <2>;
671 }; 606 };
672 }; 607 };
673 608
674 soc: soc@0 { !! 609 soc: soc {
675 #address-cells = <1>; 610 #address-cells = <1>;
676 #size-cells = <1>; 611 #size-cells = <1>;
677 ranges = <0 0 0 0xffffffff>; 612 ranges = <0 0 0 0xffffffff>;
678 compatible = "simple-bus"; 613 compatible = "simple-bus";
679 614
680 pcie_phy: phy-wrapper@34000 { 615 pcie_phy: phy-wrapper@34000 {
681 compatible = "qcom,msm 616 compatible = "qcom,msm8996-qmp-pcie-phy";
682 reg = <0x00034000 0x48 617 reg = <0x00034000 0x488>;
683 #address-cells = <1>; 618 #address-cells = <1>;
684 #size-cells = <1>; 619 #size-cells = <1>;
685 ranges = <0x0 0x000340 620 ranges = <0x0 0x00034000 0x4000>;
686 621
687 clocks = <&gcc GCC_PCI 622 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
688 <&gcc GCC_PCIE 623 <&gcc GCC_PCIE_PHY_CFG_AHB_CLK>,
689 <&gcc GCC_PCIE 624 <&gcc GCC_PCIE_CLKREF_CLK>;
690 clock-names = "aux", " 625 clock-names = "aux", "cfg_ahb", "ref";
691 626
692 resets = <&gcc GCC_PCI 627 resets = <&gcc GCC_PCIE_PHY_BCR>,
693 <&gcc GCC_PCIE 628 <&gcc GCC_PCIE_PHY_COM_BCR>,
694 <&gcc GCC_PCIE 629 <&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>;
695 reset-names = "phy", " 630 reset-names = "phy", "common", "cfg";
696 631
697 status = "disabled"; 632 status = "disabled";
698 633
699 pciephy_0: phy@1000 { 634 pciephy_0: phy@1000 {
700 reg = <0x1000 635 reg = <0x1000 0x130>,
701 <0x1200 636 <0x1200 0x200>,
702 <0x1400 637 <0x1400 0x1dc>;
703 638
704 clocks = <&gcc 639 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
705 clock-names = 640 clock-names = "pipe0";
706 resets = <&gcc 641 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
707 reset-names = 642 reset-names = "lane0";
708 643
709 #clock-cells = 644 #clock-cells = <0>;
710 clock-output-n 645 clock-output-names = "pcie_0_pipe_clk_src";
711 646
712 #phy-cells = < 647 #phy-cells = <0>;
713 }; 648 };
714 649
715 pciephy_1: phy@2000 { 650 pciephy_1: phy@2000 {
716 reg = <0x2000 651 reg = <0x2000 0x130>,
717 <0x2200 652 <0x2200 0x200>,
718 <0x2400 653 <0x2400 0x1dc>;
719 654
720 clocks = <&gcc 655 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
721 clock-names = 656 clock-names = "pipe1";
722 resets = <&gcc 657 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
723 reset-names = 658 reset-names = "lane1";
724 659
725 #clock-cells = 660 #clock-cells = <0>;
726 clock-output-n 661 clock-output-names = "pcie_1_pipe_clk_src";
727 662
728 #phy-cells = < 663 #phy-cells = <0>;
729 }; 664 };
730 665
731 pciephy_2: phy@3000 { 666 pciephy_2: phy@3000 {
732 reg = <0x3000 667 reg = <0x3000 0x130>,
733 <0x3200 668 <0x3200 0x200>,
734 <0x3400 669 <0x3400 0x1dc>;
735 670
736 clocks = <&gcc 671 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>;
737 clock-names = 672 clock-names = "pipe2";
738 resets = <&gcc 673 resets = <&gcc GCC_PCIE_2_PHY_BCR>;
739 reset-names = 674 reset-names = "lane2";
740 675
741 #clock-cells = 676 #clock-cells = <0>;
742 clock-output-n 677 clock-output-names = "pcie_2_pipe_clk_src";
743 678
744 #phy-cells = < 679 #phy-cells = <0>;
745 }; 680 };
746 }; 681 };
747 682
748 rpm_msg_ram: sram@68000 { 683 rpm_msg_ram: sram@68000 {
749 compatible = "qcom,rpm 684 compatible = "qcom,rpm-msg-ram";
750 reg = <0x00068000 0x60 685 reg = <0x00068000 0x6000>;
751 }; 686 };
752 687
753 qfprom@74000 { 688 qfprom@74000 {
754 compatible = "qcom,msm 689 compatible = "qcom,msm8996-qfprom", "qcom,qfprom";
755 reg = <0x00074000 0x8f 690 reg = <0x00074000 0x8ff>;
756 #address-cells = <1>; 691 #address-cells = <1>;
757 #size-cells = <1>; 692 #size-cells = <1>;
758 693
759 qusb2p_hstx_trim: hstx !! 694 qusb2p_hstx_trim: hstx_trim@24e {
760 reg = <0x24e 0 695 reg = <0x24e 0x2>;
761 bits = <5 4>; 696 bits = <5 4>;
762 }; 697 };
763 698
764 qusb2s_hstx_trim: hstx !! 699 qusb2s_hstx_trim: hstx_trim@24f {
765 reg = <0x24f 0 700 reg = <0x24f 0x1>;
766 bits = <1 4>; 701 bits = <1 4>;
767 }; 702 };
768 703
769 speedbin_efuse: speedb 704 speedbin_efuse: speedbin@133 {
770 reg = <0x133 0 705 reg = <0x133 0x1>;
771 bits = <5 3>; 706 bits = <5 3>;
772 }; 707 };
773 }; 708 };
774 709
775 rng: rng@83000 { 710 rng: rng@83000 {
776 compatible = "qcom,prn 711 compatible = "qcom,prng-ee";
777 reg = <0x00083000 0x10 712 reg = <0x00083000 0x1000>;
778 clocks = <&gcc GCC_PRN 713 clocks = <&gcc GCC_PRNG_AHB_CLK>;
779 clock-names = "core"; 714 clock-names = "core";
780 }; 715 };
781 716
782 gcc: clock-controller@300000 { 717 gcc: clock-controller@300000 {
783 compatible = "qcom,gcc 718 compatible = "qcom,gcc-msm8996";
784 #clock-cells = <1>; 719 #clock-cells = <1>;
785 #reset-cells = <1>; 720 #reset-cells = <1>;
786 #power-domain-cells = 721 #power-domain-cells = <1>;
787 reg = <0x00300000 0x90 722 reg = <0x00300000 0x90000>;
788 723
789 clocks = <&rpmcc RPM_S 724 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
790 <&rpmcc RPM_S 725 <&rpmcc RPM_SMD_LN_BB_CLK>,
791 <&sleep_clk>, 726 <&sleep_clk>,
792 <&pciephy_0>, 727 <&pciephy_0>,
793 <&pciephy_1>, 728 <&pciephy_1>,
794 <&pciephy_2>, 729 <&pciephy_2>,
795 <&usb3phy>, !! 730 <&ssusb_phy_0>,
796 <&ufsphy 0>, !! 731 <&ufsphy_lane 0>,
797 <&ufsphy 1>, !! 732 <&ufsphy_lane 1>,
798 <&ufsphy 2>; !! 733 <&ufsphy_lane 2>;
799 clock-names = "cxo", 734 clock-names = "cxo",
800 "cxo2", 735 "cxo2",
801 "sleep_c 736 "sleep_clk",
802 "pcie_0_ 737 "pcie_0_pipe_clk_src",
803 "pcie_1_ 738 "pcie_1_pipe_clk_src",
804 "pcie_2_ 739 "pcie_2_pipe_clk_src",
805 "usb3_ph 740 "usb3_phy_pipe_clk_src",
806 "ufs_rx_ 741 "ufs_rx_symbol_0_clk_src",
807 "ufs_rx_ 742 "ufs_rx_symbol_1_clk_src",
808 "ufs_tx_ 743 "ufs_tx_symbol_0_clk_src";
809 }; 744 };
810 745
811 bimc: interconnect@408000 { 746 bimc: interconnect@408000 {
812 compatible = "qcom,msm 747 compatible = "qcom,msm8996-bimc";
813 reg = <0x00408000 0x5a 748 reg = <0x00408000 0x5a000>;
814 #interconnect-cells = 749 #interconnect-cells = <1>;
>> 750 clock-names = "bus", "bus_a";
>> 751 clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
>> 752 <&rpmcc RPM_SMD_BIMC_A_CLK>;
815 }; 753 };
816 754
817 tsens0: thermal-sensor@4a9000 755 tsens0: thermal-sensor@4a9000 {
818 compatible = "qcom,msm 756 compatible = "qcom,msm8996-tsens", "qcom,tsens-v2";
819 reg = <0x004a9000 0x10 757 reg = <0x004a9000 0x1000>, /* TM */
820 <0x004a8000 0x10 758 <0x004a8000 0x1000>; /* SROT */
821 #qcom,sensors = <13>; 759 #qcom,sensors = <13>;
822 interrupts = <GIC_SPI 760 interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
823 <GIC_SPI 761 <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
824 interrupt-names = "upl 762 interrupt-names = "uplow", "critical";
825 #thermal-sensor-cells 763 #thermal-sensor-cells = <1>;
826 }; 764 };
827 765
828 tsens1: thermal-sensor@4ad000 766 tsens1: thermal-sensor@4ad000 {
829 compatible = "qcom,msm 767 compatible = "qcom,msm8996-tsens", "qcom,tsens-v2";
830 reg = <0x004ad000 0x10 768 reg = <0x004ad000 0x1000>, /* TM */
831 <0x004ac000 0x10 769 <0x004ac000 0x1000>; /* SROT */
832 #qcom,sensors = <8>; 770 #qcom,sensors = <8>;
833 interrupts = <GIC_SPI 771 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
834 <GIC_SPI 772 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>;
835 interrupt-names = "upl 773 interrupt-names = "uplow", "critical";
836 #thermal-sensor-cells 774 #thermal-sensor-cells = <1>;
837 }; 775 };
838 776
839 cryptobam: dma-controller@6440 777 cryptobam: dma-controller@644000 {
840 compatible = "qcom,bam 778 compatible = "qcom,bam-v1.7.0";
841 reg = <0x00644000 0x24 779 reg = <0x00644000 0x24000>;
842 interrupts = <GIC_SPI 780 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
843 clocks = <&gcc GCC_CE1 781 clocks = <&gcc GCC_CE1_CLK>;
844 clock-names = "bam_clk 782 clock-names = "bam_clk";
845 #dma-cells = <1>; 783 #dma-cells = <1>;
846 qcom,ee = <0>; 784 qcom,ee = <0>;
847 qcom,controlled-remote 785 qcom,controlled-remotely;
848 }; 786 };
849 787
850 crypto: crypto@67a000 { 788 crypto: crypto@67a000 {
851 compatible = "qcom,cry 789 compatible = "qcom,crypto-v5.4";
852 reg = <0x0067a000 0x60 790 reg = <0x0067a000 0x6000>;
853 clocks = <&gcc GCC_CE1 791 clocks = <&gcc GCC_CE1_AHB_CLK>,
854 <&gcc GCC_CE1 792 <&gcc GCC_CE1_AXI_CLK>,
855 <&gcc GCC_CE1 793 <&gcc GCC_CE1_CLK>;
856 clock-names = "iface", 794 clock-names = "iface", "bus", "core";
857 dmas = <&cryptobam 6>, 795 dmas = <&cryptobam 6>, <&cryptobam 7>;
858 dma-names = "rx", "tx" 796 dma-names = "rx", "tx";
859 }; 797 };
860 798
861 cnoc: interconnect@500000 { 799 cnoc: interconnect@500000 {
862 compatible = "qcom,msm 800 compatible = "qcom,msm8996-cnoc";
863 reg = <0x00500000 0x10 801 reg = <0x00500000 0x1000>;
864 #interconnect-cells = 802 #interconnect-cells = <1>;
>> 803 clock-names = "bus", "bus_a";
>> 804 clocks = <&rpmcc RPM_SMD_CNOC_CLK>,
>> 805 <&rpmcc RPM_SMD_CNOC_A_CLK>;
865 }; 806 };
866 807
867 snoc: interconnect@524000 { 808 snoc: interconnect@524000 {
868 compatible = "qcom,msm 809 compatible = "qcom,msm8996-snoc";
869 reg = <0x00524000 0x1c 810 reg = <0x00524000 0x1c000>;
870 #interconnect-cells = 811 #interconnect-cells = <1>;
>> 812 clock-names = "bus", "bus_a";
>> 813 clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
>> 814 <&rpmcc RPM_SMD_SNOC_A_CLK>;
871 }; 815 };
872 816
873 a0noc: interconnect@543000 { 817 a0noc: interconnect@543000 {
874 compatible = "qcom,msm 818 compatible = "qcom,msm8996-a0noc";
875 reg = <0x00543000 0x60 819 reg = <0x00543000 0x6000>;
876 #interconnect-cells = 820 #interconnect-cells = <1>;
877 clock-names = "aggre0_ 821 clock-names = "aggre0_snoc_axi",
878 "aggre0_ 822 "aggre0_cnoc_ahb",
879 "aggre0_ 823 "aggre0_noc_mpu_cfg";
880 clocks = <&gcc GCC_AGG 824 clocks = <&gcc GCC_AGGRE0_SNOC_AXI_CLK>,
881 <&gcc GCC_AGG 825 <&gcc GCC_AGGRE0_CNOC_AHB_CLK>,
882 <&gcc GCC_AGG 826 <&gcc GCC_AGGRE0_NOC_MPU_CFG_AHB_CLK>;
883 power-domains = <&gcc 827 power-domains = <&gcc AGGRE0_NOC_GDSC>;
884 }; 828 };
885 829
886 a1noc: interconnect@562000 { 830 a1noc: interconnect@562000 {
887 compatible = "qcom,msm 831 compatible = "qcom,msm8996-a1noc";
888 reg = <0x00562000 0x50 832 reg = <0x00562000 0x5000>;
889 #interconnect-cells = 833 #interconnect-cells = <1>;
>> 834 clock-names = "bus", "bus_a";
>> 835 clocks = <&rpmcc RPM_SMD_AGGR1_NOC_CLK>,
>> 836 <&rpmcc RPM_SMD_AGGR1_NOC_A_CLK>;
890 }; 837 };
891 838
892 a2noc: interconnect@583000 { 839 a2noc: interconnect@583000 {
893 compatible = "qcom,msm 840 compatible = "qcom,msm8996-a2noc";
894 reg = <0x00583000 0x70 841 reg = <0x00583000 0x7000>;
895 #interconnect-cells = 842 #interconnect-cells = <1>;
896 clock-names = "aggre2_ !! 843 clock-names = "bus", "bus_a", "aggre2_ufs_axi", "ufs_axi";
897 clocks = <&gcc GCC_AGG !! 844 clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>,
>> 845 <&rpmcc RPM_SMD_AGGR2_NOC_A_CLK>,
>> 846 <&gcc GCC_AGGRE2_UFS_AXI_CLK>,
898 <&gcc GCC_UFS 847 <&gcc GCC_UFS_AXI_CLK>;
899 }; 848 };
900 849
901 mnoc: interconnect@5a4000 { 850 mnoc: interconnect@5a4000 {
902 compatible = "qcom,msm 851 compatible = "qcom,msm8996-mnoc";
903 reg = <0x005a4000 0x1c 852 reg = <0x005a4000 0x1c000>;
904 #interconnect-cells = 853 #interconnect-cells = <1>;
905 clock-names = "iface"; !! 854 clock-names = "bus", "bus_a", "iface";
906 clocks = <&mmcc AHB_CL !! 855 clocks = <&rpmcc RPM_SMD_MMAXI_CLK>,
>> 856 <&rpmcc RPM_SMD_MMAXI_A_CLK>,
>> 857 <&mmcc AHB_CLK_SRC>;
907 }; 858 };
908 859
909 pnoc: interconnect@5c0000 { 860 pnoc: interconnect@5c0000 {
910 compatible = "qcom,msm 861 compatible = "qcom,msm8996-pnoc";
911 reg = <0x005c0000 0x30 862 reg = <0x005c0000 0x3000>;
912 #interconnect-cells = 863 #interconnect-cells = <1>;
>> 864 clock-names = "bus", "bus_a";
>> 865 clocks = <&rpmcc RPM_SMD_PCNOC_CLK>,
>> 866 <&rpmcc RPM_SMD_PCNOC_A_CLK>;
913 }; 867 };
914 868
915 tcsr_mutex: hwlock@740000 { 869 tcsr_mutex: hwlock@740000 {
916 compatible = "qcom,tcs 870 compatible = "qcom,tcsr-mutex";
917 reg = <0x00740000 0x20 871 reg = <0x00740000 0x20000>;
918 #hwlock-cells = <1>; 872 #hwlock-cells = <1>;
919 }; 873 };
920 874
921 tcsr_1: syscon@760000 { 875 tcsr_1: syscon@760000 {
922 compatible = "qcom,tcs 876 compatible = "qcom,tcsr-msm8996", "syscon";
923 reg = <0x00760000 0x20 877 reg = <0x00760000 0x20000>;
924 }; 878 };
925 879
926 tcsr_2: syscon@7a0000 { 880 tcsr_2: syscon@7a0000 {
927 compatible = "qcom,tcs 881 compatible = "qcom,tcsr-msm8996", "syscon";
928 reg = <0x007a0000 0x18 882 reg = <0x007a0000 0x18000>;
929 }; 883 };
930 884
931 mmcc: clock-controller@8c0000 885 mmcc: clock-controller@8c0000 {
932 compatible = "qcom,mmc 886 compatible = "qcom,mmcc-msm8996";
933 #clock-cells = <1>; 887 #clock-cells = <1>;
934 #reset-cells = <1>; 888 #reset-cells = <1>;
935 #power-domain-cells = 889 #power-domain-cells = <1>;
936 reg = <0x008c0000 0x40 890 reg = <0x008c0000 0x40000>;
937 clocks = <&xo_board>, 891 clocks = <&xo_board>,
938 <&gcc GPLL0>, <<
939 <&gcc GCC_MMS 892 <&gcc GCC_MMSS_NOC_CFG_AHB_CLK>,
940 <&mdss_dsi0_p !! 893 <&gcc GPLL0>,
941 <&mdss_dsi0_p !! 894 <&dsi0_phy 1>,
942 <&mdss_dsi1_p !! 895 <&dsi0_phy 0>,
943 <&mdss_dsi1_p !! 896 <&dsi1_phy 1>,
944 <&mdss_hdmi_p !! 897 <&dsi1_phy 0>,
>> 898 <&hdmi_phy>;
945 clock-names = "xo", 899 clock-names = "xo",
946 "gpll0", <<
947 "gcc_mms 900 "gcc_mmss_noc_cfg_ahb_clk",
>> 901 "gpll0",
948 "dsi0pll 902 "dsi0pll",
949 "dsi0pll 903 "dsi0pllbyte",
950 "dsi1pll 904 "dsi1pll",
951 "dsi1pll 905 "dsi1pllbyte",
952 "hdmipll 906 "hdmipll";
953 assigned-clocks = <&mm 907 assigned-clocks = <&mmcc MMPLL9_PLL>,
954 <&mm 908 <&mmcc MMPLL1_PLL>,
955 <&mm 909 <&mmcc MMPLL3_PLL>,
956 <&mm 910 <&mmcc MMPLL4_PLL>,
957 <&mm 911 <&mmcc MMPLL5_PLL>;
958 assigned-clock-rates = 912 assigned-clock-rates = <624000000>,
959 913 <810000000>,
960 914 <980000000>,
961 915 <960000000>,
962 916 <825000000>;
963 }; 917 };
964 918
965 mdss: display-subsystem@900000 919 mdss: display-subsystem@900000 {
966 compatible = "qcom,mds 920 compatible = "qcom,mdss";
967 921
968 reg = <0x00900000 0x10 922 reg = <0x00900000 0x1000>,
969 <0x009b0000 0x10 923 <0x009b0000 0x1040>,
970 <0x009b8000 0x10 924 <0x009b8000 0x1040>;
971 reg-names = "mdss_phys 925 reg-names = "mdss_phys",
972 "vbif_phys 926 "vbif_phys",
973 "vbif_nrt_ 927 "vbif_nrt_phys";
974 928
975 power-domains = <&mmcc 929 power-domains = <&mmcc MDSS_GDSC>;
976 interrupts = <GIC_SPI 930 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
977 931
978 interrupt-controller; 932 interrupt-controller;
979 #interrupt-cells = <1> 933 #interrupt-cells = <1>;
980 934
981 clocks = <&mmcc MDSS_A 935 clocks = <&mmcc MDSS_AHB_CLK>,
982 <&mmcc MDSS_M 936 <&mmcc MDSS_MDP_CLK>;
983 clock-names = "iface", 937 clock-names = "iface", "core";
984 938
985 resets = <&mmcc MDSS_B <<
986 <<
987 #address-cells = <1>; 939 #address-cells = <1>;
988 #size-cells = <1>; 940 #size-cells = <1>;
989 ranges; 941 ranges;
990 942
991 status = "disabled"; 943 status = "disabled";
992 944
993 mdp: display-controlle 945 mdp: display-controller@901000 {
994 compatible = " 946 compatible = "qcom,msm8996-mdp5", "qcom,mdp5";
995 reg = <0x00901 947 reg = <0x00901000 0x90000>;
996 reg-names = "m 948 reg-names = "mdp_phys";
997 949
998 interrupt-pare 950 interrupt-parent = <&mdss>;
999 interrupts = < 951 interrupts = <0>;
1000 952
1001 clocks = <&mm 953 clocks = <&mmcc MDSS_AHB_CLK>,
1002 <&mm 954 <&mmcc MDSS_AXI_CLK>,
1003 <&mm 955 <&mmcc MDSS_MDP_CLK>,
1004 <&mm 956 <&mmcc SMMU_MDP_AXI_CLK>,
1005 <&mm 957 <&mmcc MDSS_VSYNC_CLK>;
1006 clock-names = 958 clock-names = "iface",
1007 959 "bus",
1008 960 "core",
1009 961 "iommu",
1010 962 "vsync";
1011 963
1012 iommus = <&md 964 iommus = <&mdp_smmu 0>;
1013 965
1014 assigned-cloc 966 assigned-clocks = <&mmcc MDSS_MDP_CLK>,
1015 <&mm 967 <&mmcc MDSS_VSYNC_CLK>;
1016 assigned-cloc 968 assigned-clock-rates = <300000000>,
1017 <192 969 <19200000>;
1018 970
1019 interconnects 971 interconnects = <&mnoc MASTER_MDP_PORT0 &bimc SLAVE_EBI_CH0>,
1020 972 <&mnoc MASTER_MDP_PORT1 &bimc SLAVE_EBI_CH0>,
1021 973 <&mnoc MASTER_ROTATOR &bimc SLAVE_EBI_CH0>;
1022 interconnect- 974 interconnect-names = "mdp0-mem", "mdp1-mem", "rotator-mem";
1023 975
1024 ports { 976 ports {
1025 #addr 977 #address-cells = <1>;
1026 #size 978 #size-cells = <0>;
1027 979
1028 port@ 980 port@0 {
1029 981 reg = <0>;
1030 982 mdp5_intf3_out: endpoint {
1031 !! 983 remote-endpoint = <&hdmi_in>;
1032 984 };
1033 }; 985 };
1034 986
1035 port@ 987 port@1 {
1036 988 reg = <1>;
1037 989 mdp5_intf1_out: endpoint {
1038 !! 990 remote-endpoint = <&dsi0_in>;
1039 991 };
1040 }; 992 };
1041 993
1042 port@ 994 port@2 {
1043 995 reg = <2>;
1044 996 mdp5_intf2_out: endpoint {
1045 !! 997 remote-endpoint = <&dsi1_in>;
1046 998 };
1047 }; 999 };
1048 }; 1000 };
1049 }; 1001 };
1050 1002
1051 mdss_dsi0: dsi@994000 !! 1003 dsi0: dsi@994000 {
1052 compatible = 1004 compatible = "qcom,msm8996-dsi-ctrl",
1053 1005 "qcom,mdss-dsi-ctrl";
1054 reg = <0x0099 1006 reg = <0x00994000 0x400>;
1055 reg-names = " 1007 reg-names = "dsi_ctrl";
1056 1008
1057 interrupt-par 1009 interrupt-parent = <&mdss>;
1058 interrupts = 1010 interrupts = <4>;
1059 1011
1060 clocks = <&mm 1012 clocks = <&mmcc MDSS_MDP_CLK>,
1061 <&mm 1013 <&mmcc MDSS_BYTE0_CLK>,
1062 <&mm 1014 <&mmcc MDSS_AHB_CLK>,
1063 <&mm 1015 <&mmcc MDSS_AXI_CLK>,
1064 <&mm 1016 <&mmcc MMSS_MISC_AHB_CLK>,
1065 <&mm 1017 <&mmcc MDSS_PCLK0_CLK>,
1066 <&mm 1018 <&mmcc MDSS_ESC0_CLK>;
1067 clock-names = 1019 clock-names = "mdp_core",
1068 1020 "byte",
1069 1021 "iface",
1070 1022 "bus",
1071 1023 "core_mmss",
1072 1024 "pixel",
1073 1025 "core";
1074 assigned-cloc 1026 assigned-clocks = <&mmcc BYTE0_CLK_SRC>, <&mmcc PCLK0_CLK_SRC>;
1075 assigned-cloc !! 1027 assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
1076 1028
1077 phys = <&mdss !! 1029 phys = <&dsi0_phy>;
1078 status = "dis 1030 status = "disabled";
1079 1031
1080 #address-cell 1032 #address-cells = <1>;
1081 #size-cells = 1033 #size-cells = <0>;
1082 1034
1083 ports { 1035 ports {
1084 #addr 1036 #address-cells = <1>;
1085 #size 1037 #size-cells = <0>;
1086 1038
1087 port@ 1039 port@0 {
1088 1040 reg = <0>;
1089 !! 1041 dsi0_in: endpoint {
1090 1042 remote-endpoint = <&mdp5_intf1_out>;
1091 1043 };
1092 }; 1044 };
1093 1045
1094 port@ 1046 port@1 {
1095 1047 reg = <1>;
1096 !! 1048 dsi0_out: endpoint {
1097 1049 };
1098 }; 1050 };
1099 }; 1051 };
1100 }; 1052 };
1101 1053
1102 mdss_dsi0_phy: phy@99 !! 1054 dsi0_phy: phy@994400 {
1103 compatible = 1055 compatible = "qcom,dsi-phy-14nm";
1104 reg = <0x0099 1056 reg = <0x00994400 0x100>,
1105 <0x0099 1057 <0x00994500 0x300>,
1106 <0x0099 1058 <0x00994800 0x188>;
1107 reg-names = " 1059 reg-names = "dsi_phy",
1108 " 1060 "dsi_phy_lane",
1109 " 1061 "dsi_pll";
1110 1062
1111 #clock-cells 1063 #clock-cells = <1>;
1112 #phy-cells = 1064 #phy-cells = <0>;
1113 1065
1114 clocks = <&mm 1066 clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
1115 clock-names = 1067 clock-names = "iface", "ref";
1116 status = "dis 1068 status = "disabled";
1117 }; 1069 };
1118 1070
1119 mdss_dsi1: dsi@996000 !! 1071 dsi1: dsi@996000 {
1120 compatible = 1072 compatible = "qcom,msm8996-dsi-ctrl",
1121 1073 "qcom,mdss-dsi-ctrl";
1122 reg = <0x0099 1074 reg = <0x00996000 0x400>;
1123 reg-names = " 1075 reg-names = "dsi_ctrl";
1124 1076
1125 interrupt-par 1077 interrupt-parent = <&mdss>;
1126 interrupts = 1078 interrupts = <5>;
1127 1079
1128 clocks = <&mm 1080 clocks = <&mmcc MDSS_MDP_CLK>,
1129 <&mm 1081 <&mmcc MDSS_BYTE1_CLK>,
1130 <&mm 1082 <&mmcc MDSS_AHB_CLK>,
1131 <&mm 1083 <&mmcc MDSS_AXI_CLK>,
1132 <&mm 1084 <&mmcc MMSS_MISC_AHB_CLK>,
1133 <&mm 1085 <&mmcc MDSS_PCLK1_CLK>,
1134 <&mm 1086 <&mmcc MDSS_ESC1_CLK>;
1135 clock-names = 1087 clock-names = "mdp_core",
1136 1088 "byte",
1137 1089 "iface",
1138 1090 "bus",
1139 1091 "core_mmss",
1140 1092 "pixel",
1141 1093 "core";
1142 assigned-cloc 1094 assigned-clocks = <&mmcc BYTE1_CLK_SRC>, <&mmcc PCLK1_CLK_SRC>;
1143 assigned-cloc !! 1095 assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
1144 1096
1145 phys = <&mdss !! 1097 phys = <&dsi1_phy>;
1146 status = "dis 1098 status = "disabled";
1147 1099
1148 #address-cell 1100 #address-cells = <1>;
1149 #size-cells = 1101 #size-cells = <0>;
1150 1102
1151 ports { 1103 ports {
1152 #addr 1104 #address-cells = <1>;
1153 #size 1105 #size-cells = <0>;
1154 1106
1155 port@ 1107 port@0 {
1156 1108 reg = <0>;
1157 !! 1109 dsi1_in: endpoint {
1158 1110 remote-endpoint = <&mdp5_intf2_out>;
1159 1111 };
1160 }; 1112 };
1161 1113
1162 port@ 1114 port@1 {
1163 1115 reg = <1>;
1164 !! 1116 dsi1_out: endpoint {
1165 1117 };
1166 }; 1118 };
1167 }; 1119 };
1168 }; 1120 };
1169 1121
1170 mdss_dsi1_phy: phy@99 !! 1122 dsi1_phy: phy@996400 {
1171 compatible = 1123 compatible = "qcom,dsi-phy-14nm";
1172 reg = <0x0099 1124 reg = <0x00996400 0x100>,
1173 <0x0099 1125 <0x00996500 0x300>,
1174 <0x0099 1126 <0x00996800 0x188>;
1175 reg-names = " 1127 reg-names = "dsi_phy",
1176 " 1128 "dsi_phy_lane",
1177 " 1129 "dsi_pll";
1178 1130
1179 #clock-cells 1131 #clock-cells = <1>;
1180 #phy-cells = 1132 #phy-cells = <0>;
1181 1133
1182 clocks = <&mm 1134 clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
1183 clock-names = 1135 clock-names = "iface", "ref";
1184 status = "dis 1136 status = "disabled";
1185 }; 1137 };
1186 1138
1187 mdss_hdmi: hdmi-tx@9a !! 1139 hdmi: hdmi-tx@9a0000 {
1188 compatible = 1140 compatible = "qcom,hdmi-tx-8996";
1189 reg = <0x009a !! 1141 reg = <0x009a0000 0x50c>,
1190 <0x0007 !! 1142 <0x00070000 0x6158>,
1191 <0x009e !! 1143 <0x009e0000 0xfff>;
1192 reg-names = " 1144 reg-names = "core_physical",
1193 " 1145 "qfprom_physical",
1194 " 1146 "hdcp_physical";
1195 1147
1196 interrupt-par 1148 interrupt-parent = <&mdss>;
1197 interrupts = 1149 interrupts = <8>;
1198 1150
1199 clocks = <&mm 1151 clocks = <&mmcc MDSS_MDP_CLK>,
1200 <&mm 1152 <&mmcc MDSS_AHB_CLK>,
1201 <&mm 1153 <&mmcc MDSS_HDMI_CLK>,
1202 <&mm 1154 <&mmcc MDSS_HDMI_AHB_CLK>,
1203 <&mm 1155 <&mmcc MDSS_EXTPCLK_CLK>;
1204 clock-names = 1156 clock-names =
1205 "mdp_ 1157 "mdp_core",
1206 "ifac 1158 "iface",
1207 "core 1159 "core",
1208 "alt_ 1160 "alt_iface",
1209 "extp 1161 "extp";
1210 1162
1211 phys = <&mdss !! 1163 phys = <&hdmi_phy>;
1212 #sound-dai-ce 1164 #sound-dai-cells = <1>;
1213 1165
1214 status = "dis 1166 status = "disabled";
1215 1167
1216 ports { 1168 ports {
1217 #addr 1169 #address-cells = <1>;
1218 #size 1170 #size-cells = <0>;
1219 1171
1220 port@ 1172 port@0 {
1221 1173 reg = <0>;
1222 !! 1174 hdmi_in: endpoint {
1223 1175 remote-endpoint = <&mdp5_intf3_out>;
1224 1176 };
1225 }; 1177 };
1226 }; 1178 };
1227 }; 1179 };
1228 1180
1229 mdss_hdmi_phy: phy@9a !! 1181 hdmi_phy: phy@9a0600 {
1230 #phy-cells = 1182 #phy-cells = <0>;
1231 compatible = 1183 compatible = "qcom,hdmi-phy-8996";
1232 reg = <0x009a 1184 reg = <0x009a0600 0x1c4>,
1233 <0x009a 1185 <0x009a0a00 0x124>,
1234 <0x009a 1186 <0x009a0c00 0x124>,
1235 <0x009a 1187 <0x009a0e00 0x124>,
1236 <0x009a 1188 <0x009a1000 0x124>,
1237 <0x009a 1189 <0x009a1200 0x0c8>;
1238 reg-names = " 1190 reg-names = "hdmi_pll",
1239 " 1191 "hdmi_tx_l0",
1240 " 1192 "hdmi_tx_l1",
1241 " 1193 "hdmi_tx_l2",
1242 " 1194 "hdmi_tx_l3",
1243 " 1195 "hdmi_phy";
1244 1196
1245 clocks = <&mm 1197 clocks = <&mmcc MDSS_AHB_CLK>,
1246 <&gc 1198 <&gcc GCC_HDMI_CLKREF_CLK>,
1247 <&xo 1199 <&xo_board>;
1248 clock-names = 1200 clock-names = "iface",
1249 1201 "ref",
1250 1202 "xo";
1251 1203
1252 #clock-cells 1204 #clock-cells = <0>;
1253 1205
1254 status = "dis 1206 status = "disabled";
1255 }; 1207 };
1256 }; 1208 };
1257 1209
1258 gpu: gpu@b00000 { 1210 gpu: gpu@b00000 {
1259 compatible = "qcom,ad 1211 compatible = "qcom,adreno-530.2", "qcom,adreno";
1260 1212
1261 reg = <0x00b00000 0x3 1213 reg = <0x00b00000 0x3f000>;
1262 reg-names = "kgsl_3d0 1214 reg-names = "kgsl_3d0_reg_memory";
1263 1215
1264 interrupts = <GIC_SPI !! 1216 interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;
1265 1217
1266 clocks = <&mmcc GPU_G 1218 clocks = <&mmcc GPU_GX_GFX3D_CLK>,
1267 <&mmcc GPU_AH 1219 <&mmcc GPU_AHB_CLK>,
1268 <&mmcc GPU_GX 1220 <&mmcc GPU_GX_RBBMTIMER_CLK>,
1269 <&gcc GCC_BIM 1221 <&gcc GCC_BIMC_GFX_CLK>,
1270 <&gcc GCC_MMS 1222 <&gcc GCC_MMSS_BIMC_GFX_CLK>;
1271 1223
1272 clock-names = "core", 1224 clock-names = "core",
1273 "iface", 1225 "iface",
1274 "rbbmtimer", 1226 "rbbmtimer",
1275 "mem", 1227 "mem",
1276 "mem_iface"; 1228 "mem_iface";
1277 1229
1278 interconnects = <&bim 1230 interconnects = <&bimc MASTER_GRAPHICS_3D &bimc SLAVE_EBI_CH0>;
1279 interconnect-names = 1231 interconnect-names = "gfx-mem";
1280 1232
1281 power-domains = <&mmc 1233 power-domains = <&mmcc GPU_GX_GDSC>;
1282 iommus = <&adreno_smm 1234 iommus = <&adreno_smmu 0>;
1283 1235
1284 nvmem-cells = <&speed 1236 nvmem-cells = <&speedbin_efuse>;
1285 nvmem-cell-names = "s 1237 nvmem-cell-names = "speed_bin";
1286 1238
1287 operating-points-v2 = 1239 operating-points-v2 = <&gpu_opp_table>;
1288 1240
1289 status = "disabled"; 1241 status = "disabled";
1290 1242
1291 #cooling-cells = <2>; 1243 #cooling-cells = <2>;
1292 1244
1293 gpu_opp_table: opp-ta 1245 gpu_opp_table: opp-table {
1294 compatible = 1246 compatible = "operating-points-v2";
1295 1247
1296 /* 1248 /*
1297 * 624Mhz is 1249 * 624Mhz is only available on speed bins 0 and 3.
1298 * 560Mhz is 1250 * 560Mhz is only available on speed bins 0, 2 and 3.
1299 * All the re 1251 * All the rest are available on all bins of the hardware.
1300 */ 1252 */
1301 opp-624000000 1253 opp-624000000 {
1302 opp-h 1254 opp-hz = /bits/ 64 <624000000>;
1303 opp-s 1255 opp-supported-hw = <0x09>;
1304 }; 1256 };
1305 opp-560000000 1257 opp-560000000 {
1306 opp-h 1258 opp-hz = /bits/ 64 <560000000>;
1307 opp-s 1259 opp-supported-hw = <0x0d>;
1308 }; 1260 };
1309 opp-510000000 1261 opp-510000000 {
1310 opp-h 1262 opp-hz = /bits/ 64 <510000000>;
1311 opp-s 1263 opp-supported-hw = <0xff>;
1312 }; 1264 };
1313 opp-401800000 1265 opp-401800000 {
1314 opp-h 1266 opp-hz = /bits/ 64 <401800000>;
1315 opp-s 1267 opp-supported-hw = <0xff>;
1316 }; 1268 };
1317 opp-315000000 1269 opp-315000000 {
1318 opp-h 1270 opp-hz = /bits/ 64 <315000000>;
1319 opp-s 1271 opp-supported-hw = <0xff>;
1320 }; 1272 };
1321 opp-214000000 1273 opp-214000000 {
1322 opp-h 1274 opp-hz = /bits/ 64 <214000000>;
1323 opp-s 1275 opp-supported-hw = <0xff>;
1324 }; 1276 };
1325 opp-133000000 1277 opp-133000000 {
1326 opp-h 1278 opp-hz = /bits/ 64 <133000000>;
1327 opp-s 1279 opp-supported-hw = <0xff>;
1328 }; 1280 };
1329 }; 1281 };
1330 1282
1331 zap-shader { 1283 zap-shader {
1332 memory-region 1284 memory-region = <&gpu_mem>;
1333 }; 1285 };
1334 }; 1286 };
1335 1287
1336 tlmm: pinctrl@1010000 { 1288 tlmm: pinctrl@1010000 {
1337 compatible = "qcom,ms 1289 compatible = "qcom,msm8996-pinctrl";
1338 reg = <0x01010000 0x3 1290 reg = <0x01010000 0x300000>;
1339 interrupts = <GIC_SPI 1291 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1340 gpio-controller; 1292 gpio-controller;
1341 gpio-ranges = <&tlmm 1293 gpio-ranges = <&tlmm 0 0 150>;
1342 #gpio-cells = <2>; 1294 #gpio-cells = <2>;
1343 interrupt-controller; 1295 interrupt-controller;
1344 #interrupt-cells = <2 1296 #interrupt-cells = <2>;
1345 1297
1346 blsp1_spi1_default: b 1298 blsp1_spi1_default: blsp1-spi1-default-state {
1347 spi-pins { 1299 spi-pins {
1348 pins 1300 pins = "gpio0", "gpio1", "gpio3";
1349 funct 1301 function = "blsp_spi1";
1350 drive 1302 drive-strength = <12>;
1351 bias- 1303 bias-disable;
1352 }; 1304 };
1353 1305
1354 cs-pins { 1306 cs-pins {
1355 pins 1307 pins = "gpio2";
1356 funct 1308 function = "gpio";
1357 drive 1309 drive-strength = <16>;
1358 bias- 1310 bias-disable;
1359 outpu 1311 output-high;
1360 }; 1312 };
1361 }; 1313 };
1362 1314
1363 blsp1_spi1_sleep: bls 1315 blsp1_spi1_sleep: blsp1-spi1-sleep-state {
1364 pins = "gpio0 1316 pins = "gpio0", "gpio1", "gpio2", "gpio3";
1365 function = "g 1317 function = "gpio";
1366 drive-strengt 1318 drive-strength = <2>;
1367 bias-pull-dow 1319 bias-pull-down;
1368 }; 1320 };
1369 1321
1370 blsp2_uart2_2pins_def 1322 blsp2_uart2_2pins_default: blsp2-uart2-2pins-state {
1371 pins = "gpio4 1323 pins = "gpio4", "gpio5";
1372 function = "b 1324 function = "blsp_uart8";
1373 drive-strengt 1325 drive-strength = <16>;
1374 bias-disable; 1326 bias-disable;
1375 }; 1327 };
1376 1328
1377 blsp2_uart2_2pins_sle 1329 blsp2_uart2_2pins_sleep: blsp2-uart2-2pins-sleep-state {
1378 pins = "gpio4 1330 pins = "gpio4", "gpio5";
1379 function = "g 1331 function = "gpio";
1380 drive-strengt 1332 drive-strength = <2>;
1381 bias-disable; 1333 bias-disable;
1382 }; 1334 };
1383 1335
1384 blsp2_i2c2_default: b 1336 blsp2_i2c2_default: blsp2-i2c2-state {
1385 pins = "gpio6 1337 pins = "gpio6", "gpio7";
1386 function = "b 1338 function = "blsp_i2c8";
1387 drive-strengt 1339 drive-strength = <16>;
1388 bias-disable; 1340 bias-disable;
1389 }; 1341 };
1390 1342
1391 blsp2_i2c2_sleep: bls 1343 blsp2_i2c2_sleep: blsp2-i2c2-sleep-state {
1392 pins = "gpio6 1344 pins = "gpio6", "gpio7";
1393 function = "g 1345 function = "gpio";
1394 drive-strengt 1346 drive-strength = <2>;
1395 bias-disable; 1347 bias-disable;
1396 }; 1348 };
1397 1349
1398 blsp1_i2c6_default: b 1350 blsp1_i2c6_default: blsp1-i2c6-state {
1399 pins = "gpio2 1351 pins = "gpio27", "gpio28";
1400 function = "b 1352 function = "blsp_i2c6";
1401 drive-strengt 1353 drive-strength = <16>;
1402 bias-disable; 1354 bias-disable;
1403 }; 1355 };
1404 1356
1405 blsp1_i2c6_sleep: bls 1357 blsp1_i2c6_sleep: blsp1-i2c6-sleep-state {
1406 pins = "gpio2 1358 pins = "gpio27", "gpio28";
1407 function = "g 1359 function = "gpio";
1408 drive-strengt 1360 drive-strength = <2>;
1409 bias-pull-up; 1361 bias-pull-up;
1410 }; 1362 };
1411 1363
1412 cci0_default: cci0-de 1364 cci0_default: cci0-default-state {
1413 pins = "gpio1 1365 pins = "gpio17", "gpio18";
1414 function = "c 1366 function = "cci_i2c";
1415 drive-strengt 1367 drive-strength = <16>;
1416 bias-disable; 1368 bias-disable;
1417 }; 1369 };
1418 1370
1419 camera0_state_on: 1371 camera0_state_on:
1420 camera_rear_default: 1372 camera_rear_default: camera-rear-default-state {
1421 camera0_mclk: 1373 camera0_mclk: mclk0-pins {
1422 pins 1374 pins = "gpio13";
1423 funct 1375 function = "cam_mclk";
1424 drive 1376 drive-strength = <16>;
1425 bias- 1377 bias-disable;
1426 }; 1378 };
1427 1379
1428 camera0_rst: 1380 camera0_rst: rst-pins {
1429 pins 1381 pins = "gpio25";
1430 funct 1382 function = "gpio";
1431 drive 1383 drive-strength = <16>;
1432 bias- 1384 bias-disable;
1433 }; 1385 };
1434 1386
1435 camera0_pwdn: 1387 camera0_pwdn: pwdn-pins {
1436 pins 1388 pins = "gpio26";
1437 funct 1389 function = "gpio";
1438 drive 1390 drive-strength = <16>;
1439 bias- 1391 bias-disable;
1440 }; 1392 };
1441 }; 1393 };
1442 1394
1443 cci1_default: cci1-de 1395 cci1_default: cci1-default-state {
1444 pins = "gpio1 1396 pins = "gpio19", "gpio20";
1445 function = "c 1397 function = "cci_i2c";
1446 drive-strengt 1398 drive-strength = <16>;
1447 bias-disable; 1399 bias-disable;
1448 }; 1400 };
1449 1401
1450 camera1_state_on: 1402 camera1_state_on:
1451 camera_board_default: 1403 camera_board_default: camera-board-default-state {
1452 mclk1-pins { 1404 mclk1-pins {
1453 pins 1405 pins = "gpio14";
1454 funct 1406 function = "cam_mclk";
1455 drive 1407 drive-strength = <16>;
1456 bias- 1408 bias-disable;
1457 }; 1409 };
1458 1410
1459 pwdn-pins { 1411 pwdn-pins {
1460 pins 1412 pins = "gpio98";
1461 funct 1413 function = "gpio";
1462 drive 1414 drive-strength = <16>;
1463 bias- 1415 bias-disable;
1464 }; 1416 };
1465 1417
1466 rst-pins { 1418 rst-pins {
1467 pins 1419 pins = "gpio104";
1468 funct 1420 function = "gpio";
1469 drive 1421 drive-strength = <16>;
1470 bias- 1422 bias-disable;
1471 }; 1423 };
1472 }; 1424 };
1473 1425
1474 camera2_state_on: 1426 camera2_state_on:
1475 camera_front_default: 1427 camera_front_default: camera-front-default-state {
1476 camera2_mclk: 1428 camera2_mclk: mclk2-pins {
1477 pins 1429 pins = "gpio15";
1478 funct 1430 function = "cam_mclk";
1479 drive 1431 drive-strength = <16>;
1480 bias- 1432 bias-disable;
1481 }; 1433 };
1482 1434
1483 camera2_rst: 1435 camera2_rst: rst-pins {
1484 pins 1436 pins = "gpio23";
1485 funct 1437 function = "gpio";
1486 drive 1438 drive-strength = <16>;
1487 bias- 1439 bias-disable;
1488 }; 1440 };
1489 1441
1490 pwdn-pins { 1442 pwdn-pins {
1491 pins 1443 pins = "gpio133";
1492 funct 1444 function = "gpio";
1493 drive 1445 drive-strength = <16>;
1494 bias- 1446 bias-disable;
1495 }; 1447 };
1496 }; 1448 };
1497 1449
1498 pcie0_state_on: pcie0 1450 pcie0_state_on: pcie0-state-on-state {
1499 perst-pins { 1451 perst-pins {
1500 pins 1452 pins = "gpio35";
1501 funct 1453 function = "gpio";
1502 drive 1454 drive-strength = <2>;
1503 bias- 1455 bias-pull-down;
1504 }; 1456 };
1505 1457
1506 clkreq-pins { 1458 clkreq-pins {
1507 pins 1459 pins = "gpio36";
1508 funct 1460 function = "pci_e0";
1509 drive 1461 drive-strength = <2>;
1510 bias- 1462 bias-pull-up;
1511 }; 1463 };
1512 1464
1513 wake-pins { 1465 wake-pins {
1514 pins 1466 pins = "gpio37";
1515 funct 1467 function = "gpio";
1516 drive 1468 drive-strength = <2>;
1517 bias- 1469 bias-pull-up;
1518 }; 1470 };
1519 }; 1471 };
1520 1472
1521 pcie0_state_off: pcie 1473 pcie0_state_off: pcie0-state-off-state {
1522 perst-pins { 1474 perst-pins {
1523 pins 1475 pins = "gpio35";
1524 funct 1476 function = "gpio";
1525 drive 1477 drive-strength = <2>;
1526 bias- 1478 bias-pull-down;
1527 }; 1479 };
1528 1480
1529 clkreq-pins { 1481 clkreq-pins {
1530 pins 1482 pins = "gpio36";
1531 funct 1483 function = "gpio";
1532 drive 1484 drive-strength = <2>;
1533 bias- 1485 bias-disable;
1534 }; 1486 };
1535 1487
1536 wake-pins { 1488 wake-pins {
1537 pins 1489 pins = "gpio37";
1538 funct 1490 function = "gpio";
1539 drive 1491 drive-strength = <2>;
1540 bias- 1492 bias-disable;
1541 }; 1493 };
1542 }; 1494 };
1543 1495
1544 blsp1_uart2_default: 1496 blsp1_uart2_default: blsp1-uart2-default-state {
1545 pins = "gpio4 1497 pins = "gpio41", "gpio42", "gpio43", "gpio44";
1546 function = "b 1498 function = "blsp_uart2";
1547 drive-strengt 1499 drive-strength = <16>;
1548 bias-disable; 1500 bias-disable;
1549 }; 1501 };
1550 1502
1551 blsp1_uart2_sleep: bl 1503 blsp1_uart2_sleep: blsp1-uart2-sleep-state {
1552 pins = "gpio4 1504 pins = "gpio41", "gpio42", "gpio43", "gpio44";
1553 function = "g 1505 function = "gpio";
1554 drive-strengt 1506 drive-strength = <2>;
1555 bias-disable; 1507 bias-disable;
1556 }; 1508 };
1557 1509
1558 blsp1_i2c3_default: b 1510 blsp1_i2c3_default: blsp1-i2c3-default-state {
1559 pins = "gpio4 1511 pins = "gpio47", "gpio48";
1560 function = "b 1512 function = "blsp_i2c3";
1561 drive-strengt 1513 drive-strength = <16>;
1562 bias-disable; 1514 bias-disable;
1563 }; 1515 };
1564 1516
1565 blsp1_i2c3_sleep: bls 1517 blsp1_i2c3_sleep: blsp1-i2c3-sleep-state {
1566 pins = "gpio4 1518 pins = "gpio47", "gpio48";
1567 function = "g 1519 function = "gpio";
1568 drive-strengt 1520 drive-strength = <2>;
1569 bias-disable; 1521 bias-disable;
1570 }; 1522 };
1571 1523
1572 blsp2_uart3_4pins_def 1524 blsp2_uart3_4pins_default: blsp2-uart3-4pins-state {
1573 pins = "gpio4 1525 pins = "gpio49", "gpio50", "gpio51", "gpio52";
1574 function = "b 1526 function = "blsp_uart9";
1575 drive-strengt 1527 drive-strength = <16>;
1576 bias-disable; 1528 bias-disable;
1577 }; 1529 };
1578 1530
1579 blsp2_uart3_4pins_sle 1531 blsp2_uart3_4pins_sleep: blsp2-uart3-4pins-sleep-state {
1580 pins = "gpio4 1532 pins = "gpio49", "gpio50", "gpio51", "gpio52";
1581 function = "b 1533 function = "blsp_uart9";
1582 drive-strengt 1534 drive-strength = <2>;
1583 bias-disable; 1535 bias-disable;
1584 }; 1536 };
1585 1537
1586 blsp2_i2c3_default: b 1538 blsp2_i2c3_default: blsp2-i2c3-state-state {
1587 pins = "gpio5 1539 pins = "gpio51", "gpio52";
1588 function = "b 1540 function = "blsp_i2c9";
1589 drive-strengt 1541 drive-strength = <16>;
1590 bias-disable; 1542 bias-disable;
1591 }; 1543 };
1592 1544
1593 blsp2_i2c3_sleep: bls 1545 blsp2_i2c3_sleep: blsp2-i2c3-sleep-state {
1594 pins = "gpio5 1546 pins = "gpio51", "gpio52";
1595 function = "g 1547 function = "gpio";
1596 drive-strengt 1548 drive-strength = <2>;
1597 bias-disable; 1549 bias-disable;
1598 }; 1550 };
1599 1551
1600 wcd_intr_default: wcd 1552 wcd_intr_default: wcd-intr-default-state {
1601 pins = "gpio5 1553 pins = "gpio54";
1602 function = "g 1554 function = "gpio";
1603 drive-strengt 1555 drive-strength = <2>;
1604 bias-pull-dow 1556 bias-pull-down;
1605 }; 1557 };
1606 1558
1607 blsp2_i2c1_default: b 1559 blsp2_i2c1_default: blsp2-i2c1-state {
1608 pins = "gpio5 1560 pins = "gpio55", "gpio56";
1609 function = "b 1561 function = "blsp_i2c7";
1610 drive-strengt 1562 drive-strength = <16>;
1611 bias-disable; 1563 bias-disable;
1612 }; 1564 };
1613 1565
1614 blsp2_i2c1_sleep: bls 1566 blsp2_i2c1_sleep: blsp2-i2c1-sleep-state {
1615 pins = "gpio5 1567 pins = "gpio55", "gpio56";
1616 function = "g 1568 function = "gpio";
1617 drive-strengt 1569 drive-strength = <2>;
1618 bias-disable; 1570 bias-disable;
1619 }; 1571 };
1620 1572
1621 blsp2_i2c5_default: b 1573 blsp2_i2c5_default: blsp2-i2c5-state {
1622 pins = "gpio6 1574 pins = "gpio60", "gpio61";
1623 function = "b 1575 function = "blsp_i2c11";
1624 drive-strengt 1576 drive-strength = <2>;
1625 bias-disable; 1577 bias-disable;
1626 }; 1578 };
1627 1579
1628 /* Sleep state for BL 1580 /* Sleep state for BLSP2_I2C5 is missing.. */
1629 1581
1630 cdc_reset_active: cdc 1582 cdc_reset_active: cdc-reset-active-state {
1631 pins = "gpio6 1583 pins = "gpio64";
1632 function = "g 1584 function = "gpio";
1633 drive-strengt 1585 drive-strength = <16>;
1634 bias-pull-dow 1586 bias-pull-down;
1635 output-high; 1587 output-high;
1636 }; 1588 };
1637 1589
1638 cdc_reset_sleep: cdc- 1590 cdc_reset_sleep: cdc-reset-sleep-state {
1639 pins = "gpio6 1591 pins = "gpio64";
1640 function = "g 1592 function = "gpio";
1641 drive-strengt 1593 drive-strength = <16>;
1642 bias-disable; 1594 bias-disable;
1643 output-low; 1595 output-low;
1644 }; 1596 };
1645 1597
1646 blsp2_spi6_default: b 1598 blsp2_spi6_default: blsp2-spi6-default-state {
1647 spi-pins { 1599 spi-pins {
1648 pins 1600 pins = "gpio85", "gpio86", "gpio88";
1649 funct 1601 function = "blsp_spi12";
1650 drive 1602 drive-strength = <12>;
1651 bias- 1603 bias-disable;
1652 }; 1604 };
1653 1605
1654 cs-pins { 1606 cs-pins {
1655 pins 1607 pins = "gpio87";
1656 funct 1608 function = "gpio";
1657 drive 1609 drive-strength = <16>;
1658 bias- 1610 bias-disable;
1659 outpu 1611 output-high;
1660 }; 1612 };
1661 }; 1613 };
1662 1614
1663 blsp2_spi6_sleep: bls 1615 blsp2_spi6_sleep: blsp2-spi6-sleep-state {
1664 pins = "gpio8 1616 pins = "gpio85", "gpio86", "gpio87", "gpio88";
1665 function = "g 1617 function = "gpio";
1666 drive-strengt 1618 drive-strength = <2>;
1667 bias-pull-dow 1619 bias-pull-down;
1668 }; 1620 };
1669 1621
1670 blsp2_i2c6_default: b 1622 blsp2_i2c6_default: blsp2-i2c6-state {
1671 pins = "gpio8 1623 pins = "gpio87", "gpio88";
1672 function = "b 1624 function = "blsp_i2c12";
1673 drive-strengt 1625 drive-strength = <16>;
1674 bias-disable; 1626 bias-disable;
1675 }; 1627 };
1676 1628
1677 blsp2_i2c6_sleep: bls 1629 blsp2_i2c6_sleep: blsp2-i2c6-sleep-state {
1678 pins = "gpio8 1630 pins = "gpio87", "gpio88";
1679 function = "g 1631 function = "gpio";
1680 drive-strengt 1632 drive-strength = <2>;
1681 bias-disable; 1633 bias-disable;
1682 }; 1634 };
1683 1635
1684 pcie1_state_on: pcie1 1636 pcie1_state_on: pcie1-on-state {
1685 perst-pins { 1637 perst-pins {
1686 pins 1638 pins = "gpio130";
1687 funct 1639 function = "gpio";
1688 drive 1640 drive-strength = <2>;
1689 bias- 1641 bias-pull-down;
1690 }; 1642 };
1691 1643
1692 clkreq-pins { 1644 clkreq-pins {
1693 pins 1645 pins = "gpio131";
1694 funct 1646 function = "pci_e1";
1695 drive 1647 drive-strength = <2>;
1696 bias- 1648 bias-pull-up;
1697 }; 1649 };
1698 1650
1699 wake-pins { 1651 wake-pins {
1700 pins 1652 pins = "gpio132";
1701 funct 1653 function = "gpio";
1702 drive 1654 drive-strength = <2>;
1703 bias- 1655 bias-pull-down;
1704 }; 1656 };
1705 }; 1657 };
1706 1658
1707 pcie1_state_off: pcie 1659 pcie1_state_off: pcie1-off-state {
1708 /* Perst is m 1660 /* Perst is missing? */
1709 clkreq-pins { 1661 clkreq-pins {
1710 pins 1662 pins = "gpio131";
1711 funct 1663 function = "gpio";
1712 drive 1664 drive-strength = <2>;
1713 bias- 1665 bias-disable;
1714 }; 1666 };
1715 1667
1716 wake-pins { 1668 wake-pins {
1717 pins 1669 pins = "gpio132";
1718 funct 1670 function = "gpio";
1719 drive 1671 drive-strength = <2>;
1720 bias- 1672 bias-disable;
1721 }; 1673 };
1722 }; 1674 };
1723 1675
1724 pcie2_state_on: pcie2 1676 pcie2_state_on: pcie2-on-state {
1725 perst-pins { 1677 perst-pins {
1726 pins 1678 pins = "gpio114";
1727 funct 1679 function = "gpio";
1728 drive 1680 drive-strength = <2>;
1729 bias- 1681 bias-pull-down;
1730 }; 1682 };
1731 1683
1732 clkreq-pins { 1684 clkreq-pins {
1733 pins 1685 pins = "gpio115";
1734 funct 1686 function = "pci_e2";
1735 drive 1687 drive-strength = <2>;
1736 bias- 1688 bias-pull-up;
1737 }; 1689 };
1738 1690
1739 wake-pins { 1691 wake-pins {
1740 pins 1692 pins = "gpio116";
1741 funct 1693 function = "gpio";
1742 drive 1694 drive-strength = <2>;
1743 bias- 1695 bias-pull-down;
1744 }; 1696 };
1745 }; 1697 };
1746 1698
1747 pcie2_state_off: pcie 1699 pcie2_state_off: pcie2-off-state {
1748 /* Perst is m 1700 /* Perst is missing? */
1749 clkreq-pins { 1701 clkreq-pins {
1750 pins 1702 pins = "gpio115";
1751 funct 1703 function = "gpio";
1752 drive 1704 drive-strength = <2>;
1753 bias- 1705 bias-disable;
1754 }; 1706 };
1755 1707
1756 wake-pins { 1708 wake-pins {
1757 pins 1709 pins = "gpio116";
1758 funct 1710 function = "gpio";
1759 drive 1711 drive-strength = <2>;
1760 bias- 1712 bias-disable;
1761 }; 1713 };
1762 }; 1714 };
1763 1715
1764 sdc1_state_on: sdc1-o 1716 sdc1_state_on: sdc1-on-state {
1765 clk-pins { 1717 clk-pins {
1766 pins 1718 pins = "sdc1_clk";
1767 bias- 1719 bias-disable;
1768 drive 1720 drive-strength = <16>;
1769 }; 1721 };
1770 1722
1771 cmd-pins { 1723 cmd-pins {
1772 pins 1724 pins = "sdc1_cmd";
1773 bias- 1725 bias-pull-up;
1774 drive 1726 drive-strength = <10>;
1775 }; 1727 };
1776 1728
1777 data-pins { 1729 data-pins {
1778 pins 1730 pins = "sdc1_data";
1779 bias- 1731 bias-pull-up;
1780 drive 1732 drive-strength = <10>;
1781 }; 1733 };
1782 1734
1783 rclk-pins { 1735 rclk-pins {
1784 pins 1736 pins = "sdc1_rclk";
1785 bias- 1737 bias-pull-down;
1786 }; 1738 };
1787 }; 1739 };
1788 1740
1789 sdc1_state_off: sdc1- 1741 sdc1_state_off: sdc1-off-state {
1790 clk-pins { 1742 clk-pins {
1791 pins 1743 pins = "sdc1_clk";
1792 bias- 1744 bias-disable;
1793 drive 1745 drive-strength = <2>;
1794 }; 1746 };
1795 1747
1796 cmd-pins { 1748 cmd-pins {
1797 pins 1749 pins = "sdc1_cmd";
1798 bias- 1750 bias-pull-up;
1799 drive 1751 drive-strength = <2>;
1800 }; 1752 };
1801 1753
1802 data-pins { 1754 data-pins {
1803 pins 1755 pins = "sdc1_data";
1804 bias- 1756 bias-pull-up;
1805 drive 1757 drive-strength = <2>;
1806 }; 1758 };
1807 1759
1808 rclk-pins { 1760 rclk-pins {
1809 pins 1761 pins = "sdc1_rclk";
1810 bias- 1762 bias-pull-down;
1811 }; 1763 };
1812 }; 1764 };
1813 1765
1814 sdc2_state_on: sdc2-o 1766 sdc2_state_on: sdc2-on-state {
1815 clk-pins { 1767 clk-pins {
1816 pins 1768 pins = "sdc2_clk";
1817 bias- 1769 bias-disable;
1818 drive 1770 drive-strength = <16>;
1819 }; 1771 };
1820 1772
1821 cmd-pins { 1773 cmd-pins {
1822 pins 1774 pins = "sdc2_cmd";
1823 bias- 1775 bias-pull-up;
1824 drive 1776 drive-strength = <10>;
1825 }; 1777 };
1826 1778
1827 data-pins { 1779 data-pins {
1828 pins 1780 pins = "sdc2_data";
1829 bias- 1781 bias-pull-up;
1830 drive 1782 drive-strength = <10>;
1831 }; 1783 };
1832 }; 1784 };
1833 1785
1834 sdc2_state_off: sdc2- 1786 sdc2_state_off: sdc2-off-state {
1835 clk-pins { 1787 clk-pins {
1836 pins 1788 pins = "sdc2_clk";
1837 bias- 1789 bias-disable;
1838 drive 1790 drive-strength = <2>;
1839 }; 1791 };
1840 1792
1841 cmd-pins { 1793 cmd-pins {
1842 pins 1794 pins = "sdc2_cmd";
1843 bias- 1795 bias-pull-up;
1844 drive 1796 drive-strength = <2>;
1845 }; 1797 };
1846 1798
1847 data-pins { 1799 data-pins {
1848 pins 1800 pins = "sdc2_data";
1849 bias- 1801 bias-pull-up;
1850 drive 1802 drive-strength = <2>;
1851 }; 1803 };
1852 }; 1804 };
1853 }; 1805 };
1854 1806
1855 sram@290000 { 1807 sram@290000 {
1856 compatible = "qcom,rp 1808 compatible = "qcom,rpm-stats";
1857 reg = <0x00290000 0x1 1809 reg = <0x00290000 0x10000>;
1858 }; 1810 };
1859 1811
1860 spmi_bus: spmi@400f000 { 1812 spmi_bus: spmi@400f000 {
1861 compatible = "qcom,sp 1813 compatible = "qcom,spmi-pmic-arb";
1862 reg = <0x0400f000 0x1 1814 reg = <0x0400f000 0x1000>,
1863 <0x04400000 0x8 1815 <0x04400000 0x800000>,
1864 <0x04c00000 0x8 1816 <0x04c00000 0x800000>,
1865 <0x05800000 0x2 1817 <0x05800000 0x200000>,
1866 <0x0400a000 0x0 1818 <0x0400a000 0x002100>;
1867 reg-names = "core", " 1819 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1868 interrupt-names = "pe 1820 interrupt-names = "periph_irq";
1869 interrupts = <GIC_SPI 1821 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
1870 qcom,ee = <0>; 1822 qcom,ee = <0>;
1871 qcom,channel = <0>; 1823 qcom,channel = <0>;
1872 #address-cells = <2>; 1824 #address-cells = <2>;
1873 #size-cells = <0>; 1825 #size-cells = <0>;
1874 interrupt-controller; 1826 interrupt-controller;
1875 #interrupt-cells = <4 1827 #interrupt-cells = <4>;
1876 }; 1828 };
1877 1829
1878 bus@0 { 1830 bus@0 {
1879 power-domains = <&gcc 1831 power-domains = <&gcc AGGRE0_NOC_GDSC>;
1880 compatible = "simple- 1832 compatible = "simple-pm-bus";
1881 #address-cells = <1>; 1833 #address-cells = <1>;
1882 #size-cells = <1>; 1834 #size-cells = <1>;
1883 ranges = <0x0 0x0 0xf !! 1835 ranges;
1884 1836
1885 pcie0: pcie@600000 { 1837 pcie0: pcie@600000 {
1886 compatible = 1838 compatible = "qcom,pcie-msm8996";
1887 status = "dis 1839 status = "disabled";
1888 power-domains 1840 power-domains = <&gcc PCIE0_GDSC>;
1889 bus-range = < 1841 bus-range = <0x00 0xff>;
1890 num-lanes = < 1842 num-lanes = <1>;
1891 1843
1892 reg = <0x0060 1844 reg = <0x00600000 0x2000>,
1893 <0x0c00 1845 <0x0c000000 0xf1d>,
1894 <0x0c00 1846 <0x0c000f20 0xa8>,
1895 <0x0c10 1847 <0x0c100000 0x100000>;
1896 reg-names = " 1848 reg-names = "parf", "dbi", "elbi","config";
1897 1849
1898 phys = <&pcie 1850 phys = <&pciephy_0>;
1899 phy-names = " 1851 phy-names = "pciephy";
1900 1852
1901 #address-cell 1853 #address-cells = <3>;
1902 #size-cells = 1854 #size-cells = <2>;
1903 ranges = <0x0 1855 ranges = <0x01000000 0x0 0x00000000 0x0c200000 0x0 0x100000>,
1904 <0x0 1856 <0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>;
1905 1857
1906 device_type = 1858 device_type = "pci";
1907 1859
1908 interrupts = 1860 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
1909 interrupt-nam 1861 interrupt-names = "msi";
1910 #interrupt-ce 1862 #interrupt-cells = <1>;
1911 interrupt-map 1863 interrupt-map-mask = <0 0 0 0x7>;
1912 interrupt-map 1864 interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1913 1865 <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1914 1866 <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1915 1867 <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1916 1868
1917 pinctrl-names 1869 pinctrl-names = "default", "sleep";
1918 pinctrl-0 = < 1870 pinctrl-0 = <&pcie0_state_on>;
1919 pinctrl-1 = < 1871 pinctrl-1 = <&pcie0_state_off>;
1920 1872
1921 linux,pci-dom 1873 linux,pci-domain = <0>;
1922 1874
1923 clocks = <&gc 1875 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
1924 <&gcc 1876 <&gcc GCC_PCIE_0_AUX_CLK>,
1925 <&gcc 1877 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1926 <&gcc 1878 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1927 <&gcc 1879 <&gcc GCC_PCIE_0_SLV_AXI_CLK>;
1928 1880
1929 clock-names = 1881 clock-names = "pipe",
1930 1882 "aux",
1931 1883 "cfg",
1932 1884 "bus_master",
1933 1885 "bus_slave";
1934 <<
1935 pcie@0 { <<
1936 devic <<
1937 reg = <<
1938 bus-r <<
1939 <<
1940 #addr <<
1941 #size <<
1942 range <<
1943 }; <<
1944 }; 1886 };
1945 1887
1946 pcie1: pcie@608000 { 1888 pcie1: pcie@608000 {
1947 compatible = 1889 compatible = "qcom,pcie-msm8996";
1948 power-domains 1890 power-domains = <&gcc PCIE1_GDSC>;
1949 bus-range = < 1891 bus-range = <0x00 0xff>;
1950 num-lanes = < 1892 num-lanes = <1>;
1951 1893
1952 status = "dis 1894 status = "disabled";
1953 1895
1954 reg = <0x0060 1896 reg = <0x00608000 0x2000>,
1955 <0x0d00 1897 <0x0d000000 0xf1d>,
1956 <0x0d00 1898 <0x0d000f20 0xa8>,
1957 <0x0d10 1899 <0x0d100000 0x100000>;
1958 1900
1959 reg-names = " 1901 reg-names = "parf", "dbi", "elbi","config";
1960 1902
1961 phys = <&pcie 1903 phys = <&pciephy_1>;
1962 phy-names = " 1904 phy-names = "pciephy";
1963 1905
1964 #address-cell 1906 #address-cells = <3>;
1965 #size-cells = 1907 #size-cells = <2>;
1966 ranges = <0x0 1908 ranges = <0x01000000 0x0 0x00000000 0x0d200000 0x0 0x100000>,
1967 <0x0 1909 <0x02000000 0x0 0x0d300000 0x0d300000 0x0 0xd00000>;
1968 1910
1969 device_type = 1911 device_type = "pci";
1970 1912
1971 interrupts = 1913 interrupts = <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>;
1972 interrupt-nam 1914 interrupt-names = "msi";
1973 #interrupt-ce 1915 #interrupt-cells = <1>;
1974 interrupt-map 1916 interrupt-map-mask = <0 0 0 0x7>;
1975 interrupt-map 1917 interrupt-map = <0 0 0 1 &intc 0 272 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1976 1918 <0 0 0 2 &intc 0 273 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1977 1919 <0 0 0 3 &intc 0 274 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1978 1920 <0 0 0 4 &intc 0 275 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1979 1921
1980 pinctrl-names 1922 pinctrl-names = "default", "sleep";
1981 pinctrl-0 = < 1923 pinctrl-0 = <&pcie1_state_on>;
1982 pinctrl-1 = < 1924 pinctrl-1 = <&pcie1_state_off>;
1983 1925
1984 linux,pci-dom 1926 linux,pci-domain = <1>;
1985 1927
1986 clocks = <&gc 1928 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
1987 <&gcc 1929 <&gcc GCC_PCIE_1_AUX_CLK>,
1988 <&gcc 1930 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1989 <&gcc 1931 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
1990 <&gcc 1932 <&gcc GCC_PCIE_1_SLV_AXI_CLK>;
1991 1933
1992 clock-names = 1934 clock-names = "pipe",
1993 1935 "aux",
1994 1936 "cfg",
1995 1937 "bus_master",
1996 1938 "bus_slave";
1997 <<
1998 pcie@0 { <<
1999 devic <<
2000 reg = <<
2001 bus-r <<
2002 <<
2003 #addr <<
2004 #size <<
2005 range <<
2006 }; <<
2007 }; 1939 };
2008 1940
2009 pcie2: pcie@610000 { 1941 pcie2: pcie@610000 {
2010 compatible = 1942 compatible = "qcom,pcie-msm8996";
2011 power-domains 1943 power-domains = <&gcc PCIE2_GDSC>;
2012 bus-range = < 1944 bus-range = <0x00 0xff>;
2013 num-lanes = < 1945 num-lanes = <1>;
2014 status = "dis 1946 status = "disabled";
2015 reg = <0x0061 1947 reg = <0x00610000 0x2000>,
2016 <0x0e00 1948 <0x0e000000 0xf1d>,
2017 <0x0e00 1949 <0x0e000f20 0xa8>,
2018 <0x0e10 1950 <0x0e100000 0x100000>;
2019 1951
2020 reg-names = " 1952 reg-names = "parf", "dbi", "elbi","config";
2021 1953
2022 phys = <&pcie 1954 phys = <&pciephy_2>;
2023 phy-names = " 1955 phy-names = "pciephy";
2024 1956
2025 #address-cell 1957 #address-cells = <3>;
2026 #size-cells = 1958 #size-cells = <2>;
2027 ranges = <0x0 1959 ranges = <0x01000000 0x0 0x00000000 0x0e200000 0x0 0x100000>,
2028 <0x0 1960 <0x02000000 0x0 0x0e300000 0x0e300000 0x0 0x1d00000>;
2029 1961
2030 device_type = 1962 device_type = "pci";
2031 1963
2032 interrupts = 1964 interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
2033 interrupt-nam 1965 interrupt-names = "msi";
2034 #interrupt-ce 1966 #interrupt-cells = <1>;
2035 interrupt-map 1967 interrupt-map-mask = <0 0 0 0x7>;
2036 interrupt-map 1968 interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2037 1969 <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2038 1970 <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2039 1971 <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2040 1972
2041 pinctrl-names 1973 pinctrl-names = "default", "sleep";
2042 pinctrl-0 = < 1974 pinctrl-0 = <&pcie2_state_on>;
2043 pinctrl-1 = < 1975 pinctrl-1 = <&pcie2_state_off>;
2044 1976
2045 linux,pci-dom 1977 linux,pci-domain = <2>;
2046 clocks = <&gc 1978 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,
2047 <&gcc 1979 <&gcc GCC_PCIE_2_AUX_CLK>,
2048 <&gcc 1980 <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
2049 <&gcc 1981 <&gcc GCC_PCIE_2_MSTR_AXI_CLK>,
2050 <&gcc 1982 <&gcc GCC_PCIE_2_SLV_AXI_CLK>;
2051 1983
2052 clock-names = 1984 clock-names = "pipe",
2053 1985 "aux",
2054 1986 "cfg",
2055 1987 "bus_master",
2056 1988 "bus_slave";
2057 <<
2058 pcie@0 { <<
2059 devic <<
2060 reg = <<
2061 bus-r <<
2062 <<
2063 #addr <<
2064 #size <<
2065 range <<
2066 }; <<
2067 }; 1989 };
2068 }; 1990 };
2069 1991
2070 ufshc: ufshc@624000 { 1992 ufshc: ufshc@624000 {
2071 compatible = "qcom,ms 1993 compatible = "qcom,msm8996-ufshc", "qcom,ufshc",
2072 "jedec,u 1994 "jedec,ufs-2.0";
2073 reg = <0x00624000 0x2 1995 reg = <0x00624000 0x2500>;
2074 interrupts = <GIC_SPI 1996 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
2075 1997
2076 phys = <&ufsphy>; !! 1998 phys = <&ufsphy_lane>;
2077 phy-names = "ufsphy"; 1999 phy-names = "ufsphy";
2078 2000
2079 power-domains = <&gcc 2001 power-domains = <&gcc UFS_GDSC>;
2080 2002
2081 clock-names = 2003 clock-names =
>> 2004 "core_clk_src",
2082 "core_clk", 2005 "core_clk",
2083 "bus_clk", 2006 "bus_clk",
2084 "bus_aggr_clk 2007 "bus_aggr_clk",
2085 "iface_clk", 2008 "iface_clk",
>> 2009 "core_clk_unipro_src",
2086 "core_clk_uni 2010 "core_clk_unipro",
2087 "core_clk_ice 2011 "core_clk_ice",
2088 "ref_clk", 2012 "ref_clk",
2089 "tx_lane0_syn 2013 "tx_lane0_sync_clk",
2090 "rx_lane0_syn 2014 "rx_lane0_sync_clk";
2091 clocks = 2015 clocks =
>> 2016 <&gcc UFS_AXI_CLK_SRC>,
2092 <&gcc GCC_UFS 2017 <&gcc GCC_UFS_AXI_CLK>,
2093 <&gcc GCC_SYS 2018 <&gcc GCC_SYS_NOC_UFS_AXI_CLK>,
2094 <&gcc GCC_AGG 2019 <&gcc GCC_AGGRE2_UFS_AXI_CLK>,
2095 <&gcc GCC_UFS 2020 <&gcc GCC_UFS_AHB_CLK>,
>> 2021 <&gcc UFS_ICE_CORE_CLK_SRC>,
2096 <&gcc GCC_UFS 2022 <&gcc GCC_UFS_UNIPRO_CORE_CLK>,
2097 <&gcc GCC_UFS 2023 <&gcc GCC_UFS_ICE_CORE_CLK>,
2098 <&rpmcc RPM_S 2024 <&rpmcc RPM_SMD_LN_BB_CLK>,
2099 <&gcc GCC_UFS 2025 <&gcc GCC_UFS_TX_SYMBOL_0_CLK>,
2100 <&gcc GCC_UFS 2026 <&gcc GCC_UFS_RX_SYMBOL_0_CLK>;
2101 freq-table-hz = 2027 freq-table-hz =
2102 <100000000 20 2028 <100000000 200000000>,
2103 <0 0>, 2029 <0 0>,
2104 <0 0>, 2030 <0 0>,
2105 <0 0>, 2031 <0 0>,
2106 <75000000 150 !! 2032 <0 0>,
2107 <150000000 30 2033 <150000000 300000000>,
2108 <0 0>, 2034 <0 0>,
2109 <0 0>, 2035 <0 0>,
>> 2036 <0 0>,
>> 2037 <0 0>,
2110 <0 0>; 2038 <0 0>;
2111 2039
2112 interconnects = <&a2n 2040 interconnects = <&a2noc MASTER_UFS &bimc SLAVE_EBI_CH0>,
2113 <&bim 2041 <&bimc MASTER_AMPSS_M0 &cnoc SLAVE_UFS_CFG>;
2114 interconnect-names = 2042 interconnect-names = "ufs-ddr", "cpu-ufs";
2115 2043
2116 lanes-per-direction = 2044 lanes-per-direction = <1>;
2117 #reset-cells = <1>; 2045 #reset-cells = <1>;
2118 status = "disabled"; 2046 status = "disabled";
2119 }; 2047 };
2120 2048
2121 ufsphy: phy@627000 { 2049 ufsphy: phy@627000 {
2122 compatible = "qcom,ms 2050 compatible = "qcom,msm8996-qmp-ufs-phy";
2123 reg = <0x00627000 0x1 !! 2051 reg = <0x00627000 0x1c4>;
>> 2052 #address-cells = <1>;
>> 2053 #size-cells = <1>;
>> 2054 ranges;
2124 2055
2125 clocks = <&rpmcc RPM_ !! 2056 clocks = <&gcc GCC_UFS_CLKREF_CLK>;
2126 clock-names = "ref", !! 2057 clock-names = "ref";
2127 2058
2128 resets = <&ufshc 0>; 2059 resets = <&ufshc 0>;
2129 reset-names = "ufsphy 2060 reset-names = "ufsphy";
2130 <<
2131 #clock-cells = <1>; <<
2132 #phy-cells = <0>; <<
2133 <<
2134 status = "disabled"; 2061 status = "disabled";
>> 2062
>> 2063 ufsphy_lane: phy@627400 {
>> 2064 reg = <0x627400 0x12c>,
>> 2065 <0x627600 0x200>,
>> 2066 <0x627c00 0x1b4>;
>> 2067 #clock-cells = <1>;
>> 2068 #phy-cells = <0>;
>> 2069 };
2135 }; 2070 };
2136 2071
2137 camss: camss@a34000 { 2072 camss: camss@a34000 {
2138 compatible = "qcom,ms 2073 compatible = "qcom,msm8996-camss";
2139 reg = <0x00a34000 0x1 2074 reg = <0x00a34000 0x1000>,
2140 <0x00a00030 0x4 2075 <0x00a00030 0x4>,
2141 <0x00a35000 0x1 2076 <0x00a35000 0x1000>,
2142 <0x00a00038 0x4 2077 <0x00a00038 0x4>,
2143 <0x00a36000 0x1 2078 <0x00a36000 0x1000>,
2144 <0x00a00040 0x4 2079 <0x00a00040 0x4>,
2145 <0x00a30000 0x1 2080 <0x00a30000 0x100>,
2146 <0x00a30400 0x1 2081 <0x00a30400 0x100>,
2147 <0x00a30800 0x1 2082 <0x00a30800 0x100>,
2148 <0x00a30c00 0x1 2083 <0x00a30c00 0x100>,
2149 <0x00a31000 0x5 2084 <0x00a31000 0x500>,
2150 <0x00a00020 0x1 2085 <0x00a00020 0x10>,
2151 <0x00a10000 0x1 2086 <0x00a10000 0x1000>,
2152 <0x00a14000 0x1 2087 <0x00a14000 0x1000>;
2153 reg-names = "csiphy0" 2088 reg-names = "csiphy0",
2154 "csiphy0_clk_ 2089 "csiphy0_clk_mux",
2155 "csiphy1", 2090 "csiphy1",
2156 "csiphy1_clk_ 2091 "csiphy1_clk_mux",
2157 "csiphy2", 2092 "csiphy2",
2158 "csiphy2_clk_ 2093 "csiphy2_clk_mux",
2159 "csid0", 2094 "csid0",
2160 "csid1", 2095 "csid1",
2161 "csid2", 2096 "csid2",
2162 "csid3", 2097 "csid3",
2163 "ispif", 2098 "ispif",
2164 "csi_clk_mux" 2099 "csi_clk_mux",
2165 "vfe0", 2100 "vfe0",
2166 "vfe1"; 2101 "vfe1";
2167 interrupts = <GIC_SPI 2102 interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
2168 <GIC_SPI 79 I 2103 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
2169 <GIC_SPI 80 I 2104 <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>,
2170 <GIC_SPI 296 2105 <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>,
2171 <GIC_SPI 297 2106 <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>,
2172 <GIC_SPI 298 2107 <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>,
2173 <GIC_SPI 299 2108 <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>,
2174 <GIC_SPI 309 2109 <GIC_SPI 309 IRQ_TYPE_EDGE_RISING>,
2175 <GIC_SPI 314 2110 <GIC_SPI 314 IRQ_TYPE_EDGE_RISING>,
2176 <GIC_SPI 315 2111 <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>;
2177 interrupt-names = "cs 2112 interrupt-names = "csiphy0",
2178 "csiphy1", 2113 "csiphy1",
2179 "csiphy2", 2114 "csiphy2",
2180 "csid0", 2115 "csid0",
2181 "csid1", 2116 "csid1",
2182 "csid2", 2117 "csid2",
2183 "csid3", 2118 "csid3",
2184 "ispif", 2119 "ispif",
2185 "vfe0", 2120 "vfe0",
2186 "vfe1"; 2121 "vfe1";
2187 power-domains = <&mmc 2122 power-domains = <&mmcc VFE0_GDSC>,
2188 <&mmc 2123 <&mmcc VFE1_GDSC>;
2189 clocks = <&mmcc CAMSS 2124 clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
2190 <&mmcc CAMSS_ 2125 <&mmcc CAMSS_ISPIF_AHB_CLK>,
2191 <&mmcc CAMSS_ 2126 <&mmcc CAMSS_CSI0PHYTIMER_CLK>,
2192 <&mmcc CAMSS_ 2127 <&mmcc CAMSS_CSI1PHYTIMER_CLK>,
2193 <&mmcc CAMSS_ 2128 <&mmcc CAMSS_CSI2PHYTIMER_CLK>,
2194 <&mmcc CAMSS_ 2129 <&mmcc CAMSS_CSI0_AHB_CLK>,
2195 <&mmcc CAMSS_ 2130 <&mmcc CAMSS_CSI0_CLK>,
2196 <&mmcc CAMSS_ 2131 <&mmcc CAMSS_CSI0PHY_CLK>,
2197 <&mmcc CAMSS_ 2132 <&mmcc CAMSS_CSI0PIX_CLK>,
2198 <&mmcc CAMSS_ 2133 <&mmcc CAMSS_CSI0RDI_CLK>,
2199 <&mmcc CAMSS_ 2134 <&mmcc CAMSS_CSI1_AHB_CLK>,
2200 <&mmcc CAMSS_ 2135 <&mmcc CAMSS_CSI1_CLK>,
2201 <&mmcc CAMSS_ 2136 <&mmcc CAMSS_CSI1PHY_CLK>,
2202 <&mmcc CAMSS_ 2137 <&mmcc CAMSS_CSI1PIX_CLK>,
2203 <&mmcc CAMSS_ 2138 <&mmcc CAMSS_CSI1RDI_CLK>,
2204 <&mmcc CAMSS_ 2139 <&mmcc CAMSS_CSI2_AHB_CLK>,
2205 <&mmcc CAMSS_ 2140 <&mmcc CAMSS_CSI2_CLK>,
2206 <&mmcc CAMSS_ 2141 <&mmcc CAMSS_CSI2PHY_CLK>,
2207 <&mmcc CAMSS_ 2142 <&mmcc CAMSS_CSI2PIX_CLK>,
2208 <&mmcc CAMSS_ 2143 <&mmcc CAMSS_CSI2RDI_CLK>,
2209 <&mmcc CAMSS_ 2144 <&mmcc CAMSS_CSI3_AHB_CLK>,
2210 <&mmcc CAMSS_ 2145 <&mmcc CAMSS_CSI3_CLK>,
2211 <&mmcc CAMSS_ 2146 <&mmcc CAMSS_CSI3PHY_CLK>,
2212 <&mmcc CAMSS_ 2147 <&mmcc CAMSS_CSI3PIX_CLK>,
2213 <&mmcc CAMSS_ 2148 <&mmcc CAMSS_CSI3RDI_CLK>,
2214 <&mmcc CAMSS_ 2149 <&mmcc CAMSS_AHB_CLK>,
2215 <&mmcc CAMSS_ 2150 <&mmcc CAMSS_VFE0_CLK>,
2216 <&mmcc CAMSS_ 2151 <&mmcc CAMSS_CSI_VFE0_CLK>,
2217 <&mmcc CAMSS_ 2152 <&mmcc CAMSS_VFE0_AHB_CLK>,
2218 <&mmcc CAMSS_ 2153 <&mmcc CAMSS_VFE0_STREAM_CLK>,
2219 <&mmcc CAMSS_ 2154 <&mmcc CAMSS_VFE1_CLK>,
2220 <&mmcc CAMSS_ 2155 <&mmcc CAMSS_CSI_VFE1_CLK>,
2221 <&mmcc CAMSS_ 2156 <&mmcc CAMSS_VFE1_AHB_CLK>,
2222 <&mmcc CAMSS_ 2157 <&mmcc CAMSS_VFE1_STREAM_CLK>,
2223 <&mmcc CAMSS_ 2158 <&mmcc CAMSS_VFE_AHB_CLK>,
2224 <&mmcc CAMSS_ 2159 <&mmcc CAMSS_VFE_AXI_CLK>;
2225 clock-names = "top_ah 2160 clock-names = "top_ahb",
2226 "ispif_ahb", 2161 "ispif_ahb",
2227 "csiphy0_time 2162 "csiphy0_timer",
2228 "csiphy1_time 2163 "csiphy1_timer",
2229 "csiphy2_time 2164 "csiphy2_timer",
2230 "csi0_ahb", 2165 "csi0_ahb",
2231 "csi0", 2166 "csi0",
2232 "csi0_phy", 2167 "csi0_phy",
2233 "csi0_pix", 2168 "csi0_pix",
2234 "csi0_rdi", 2169 "csi0_rdi",
2235 "csi1_ahb", 2170 "csi1_ahb",
2236 "csi1", 2171 "csi1",
2237 "csi1_phy", 2172 "csi1_phy",
2238 "csi1_pix", 2173 "csi1_pix",
2239 "csi1_rdi", 2174 "csi1_rdi",
2240 "csi2_ahb", 2175 "csi2_ahb",
2241 "csi2", 2176 "csi2",
2242 "csi2_phy", 2177 "csi2_phy",
2243 "csi2_pix", 2178 "csi2_pix",
2244 "csi2_rdi", 2179 "csi2_rdi",
2245 "csi3_ahb", 2180 "csi3_ahb",
2246 "csi3", 2181 "csi3",
2247 "csi3_phy", 2182 "csi3_phy",
2248 "csi3_pix", 2183 "csi3_pix",
2249 "csi3_rdi", 2184 "csi3_rdi",
2250 "ahb", 2185 "ahb",
2251 "vfe0", 2186 "vfe0",
2252 "csi_vfe0", 2187 "csi_vfe0",
2253 "vfe0_ahb", 2188 "vfe0_ahb",
2254 "vfe0_stream" 2189 "vfe0_stream",
2255 "vfe1", 2190 "vfe1",
2256 "csi_vfe1", 2191 "csi_vfe1",
2257 "vfe1_ahb", 2192 "vfe1_ahb",
2258 "vfe1_stream" 2193 "vfe1_stream",
2259 "vfe_ahb", 2194 "vfe_ahb",
2260 "vfe_axi"; 2195 "vfe_axi";
2261 iommus = <&vfe_smmu 0 2196 iommus = <&vfe_smmu 0>,
2262 <&vfe_smmu 1 2197 <&vfe_smmu 1>,
2263 <&vfe_smmu 2 2198 <&vfe_smmu 2>,
2264 <&vfe_smmu 3 2199 <&vfe_smmu 3>;
2265 status = "disabled"; 2200 status = "disabled";
2266 ports { 2201 ports {
2267 #address-cell 2202 #address-cells = <1>;
2268 #size-cells = 2203 #size-cells = <0>;
2269 }; 2204 };
2270 }; 2205 };
2271 2206
2272 cci: cci@a0c000 { 2207 cci: cci@a0c000 {
2273 compatible = "qcom,ms 2208 compatible = "qcom,msm8996-cci";
2274 #address-cells = <1>; 2209 #address-cells = <1>;
2275 #size-cells = <0>; 2210 #size-cells = <0>;
2276 reg = <0xa0c000 0x100 2211 reg = <0xa0c000 0x1000>;
2277 interrupts = <GIC_SPI 2212 interrupts = <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>;
2278 power-domains = <&mmc 2213 power-domains = <&mmcc CAMSS_GDSC>;
2279 clocks = <&mmcc CAMSS 2214 clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
2280 <&mmcc CAMSS 2215 <&mmcc CAMSS_CCI_AHB_CLK>,
2281 <&mmcc CAMSS 2216 <&mmcc CAMSS_CCI_CLK>,
2282 <&mmcc CAMSS 2217 <&mmcc CAMSS_AHB_CLK>;
2283 clock-names = "camss_ 2218 clock-names = "camss_top_ahb",
2284 "cci_ah 2219 "cci_ahb",
2285 "cci", 2220 "cci",
2286 "camss_ 2221 "camss_ahb";
2287 assigned-clocks = <&m 2222 assigned-clocks = <&mmcc CAMSS_CCI_AHB_CLK>,
2288 <&m 2223 <&mmcc CAMSS_CCI_CLK>;
2289 assigned-clock-rates 2224 assigned-clock-rates = <80000000>, <37500000>;
2290 pinctrl-names = "defa 2225 pinctrl-names = "default";
2291 pinctrl-0 = <&cci0_de 2226 pinctrl-0 = <&cci0_default &cci1_default>;
2292 status = "disabled"; 2227 status = "disabled";
2293 2228
2294 cci_i2c0: i2c-bus@0 { 2229 cci_i2c0: i2c-bus@0 {
2295 reg = <0>; 2230 reg = <0>;
2296 clock-frequen 2231 clock-frequency = <400000>;
2297 #address-cell 2232 #address-cells = <1>;
2298 #size-cells = 2233 #size-cells = <0>;
2299 }; 2234 };
2300 2235
2301 cci_i2c1: i2c-bus@1 { 2236 cci_i2c1: i2c-bus@1 {
2302 reg = <1>; 2237 reg = <1>;
2303 clock-frequen 2238 clock-frequency = <400000>;
2304 #address-cell 2239 #address-cells = <1>;
2305 #size-cells = 2240 #size-cells = <0>;
2306 }; 2241 };
2307 }; 2242 };
2308 2243
2309 adreno_smmu: iommu@b40000 { 2244 adreno_smmu: iommu@b40000 {
2310 compatible = "qcom,ms 2245 compatible = "qcom,msm8996-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
2311 reg = <0x00b40000 0x1 2246 reg = <0x00b40000 0x10000>;
2312 2247
2313 #global-interrupts = 2248 #global-interrupts = <1>;
2314 interrupts = <GIC_SPI 2249 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
2315 <GIC_SPI 2250 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
2316 <GIC_SPI 2251 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
2317 #iommu-cells = <1>; 2252 #iommu-cells = <1>;
2318 2253
2319 clocks = <&gcc GCC_MM 2254 clocks = <&gcc GCC_MMSS_BIMC_GFX_CLK>,
2320 <&mmcc GPU_A 2255 <&mmcc GPU_AHB_CLK>;
2321 clock-names = "bus", 2256 clock-names = "bus", "iface";
2322 2257
2323 power-domains = <&mmc 2258 power-domains = <&mmcc GPU_GDSC>;
2324 }; 2259 };
2325 2260
2326 venus: video-codec@c00000 { 2261 venus: video-codec@c00000 {
2327 compatible = "qcom,ms 2262 compatible = "qcom,msm8996-venus";
2328 reg = <0x00c00000 0xf 2263 reg = <0x00c00000 0xff000>;
2329 interrupts = <GIC_SPI 2264 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
2330 power-domains = <&mmc 2265 power-domains = <&mmcc VENUS_GDSC>;
2331 clocks = <&mmcc VIDEO 2266 clocks = <&mmcc VIDEO_CORE_CLK>,
2332 <&mmcc VIDEO 2267 <&mmcc VIDEO_AHB_CLK>,
2333 <&mmcc VIDEO 2268 <&mmcc VIDEO_AXI_CLK>,
2334 <&mmcc VIDEO 2269 <&mmcc VIDEO_MAXI_CLK>;
2335 clock-names = "core", 2270 clock-names = "core", "iface", "bus", "mbus";
2336 interconnects = <&mno 2271 interconnects = <&mnoc MASTER_VIDEO_P0 &bimc SLAVE_EBI_CH0>,
2337 <&bim 2272 <&bimc MASTER_AMPSS_M0 &mnoc SLAVE_VENUS_CFG>;
2338 interconnect-names = 2273 interconnect-names = "video-mem", "cpu-cfg";
2339 iommus = <&venus_smmu 2274 iommus = <&venus_smmu 0x00>,
2340 <&venus_smmu 2275 <&venus_smmu 0x01>,
2341 <&venus_smmu 2276 <&venus_smmu 0x0a>,
2342 <&venus_smmu 2277 <&venus_smmu 0x07>,
2343 <&venus_smmu 2278 <&venus_smmu 0x0e>,
2344 <&venus_smmu 2279 <&venus_smmu 0x0f>,
2345 <&venus_smmu 2280 <&venus_smmu 0x08>,
2346 <&venus_smmu 2281 <&venus_smmu 0x09>,
2347 <&venus_smmu 2282 <&venus_smmu 0x0b>,
2348 <&venus_smmu 2283 <&venus_smmu 0x0c>,
2349 <&venus_smmu 2284 <&venus_smmu 0x0d>,
2350 <&venus_smmu 2285 <&venus_smmu 0x10>,
2351 <&venus_smmu 2286 <&venus_smmu 0x11>,
2352 <&venus_smmu 2287 <&venus_smmu 0x21>,
2353 <&venus_smmu 2288 <&venus_smmu 0x28>,
2354 <&venus_smmu 2289 <&venus_smmu 0x29>,
2355 <&venus_smmu 2290 <&venus_smmu 0x2b>,
2356 <&venus_smmu 2291 <&venus_smmu 0x2c>,
2357 <&venus_smmu 2292 <&venus_smmu 0x2d>,
2358 <&venus_smmu 2293 <&venus_smmu 0x31>;
2359 memory-region = <&ven 2294 memory-region = <&venus_mem>;
2360 status = "disabled"; 2295 status = "disabled";
2361 2296
2362 video-decoder { 2297 video-decoder {
2363 compatible = 2298 compatible = "venus-decoder";
2364 clocks = <&mm 2299 clocks = <&mmcc VIDEO_SUBCORE0_CLK>;
2365 clock-names = 2300 clock-names = "core";
2366 power-domains 2301 power-domains = <&mmcc VENUS_CORE0_GDSC>;
2367 }; 2302 };
2368 2303
2369 video-encoder { 2304 video-encoder {
2370 compatible = 2305 compatible = "venus-encoder";
2371 clocks = <&mm 2306 clocks = <&mmcc VIDEO_SUBCORE1_CLK>;
2372 clock-names = 2307 clock-names = "core";
2373 power-domains 2308 power-domains = <&mmcc VENUS_CORE1_GDSC>;
2374 }; 2309 };
2375 }; 2310 };
2376 2311
2377 mdp_smmu: iommu@d00000 { 2312 mdp_smmu: iommu@d00000 {
2378 compatible = "qcom,ms 2313 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2379 reg = <0x00d00000 0x1 2314 reg = <0x00d00000 0x10000>;
2380 2315
2381 #global-interrupts = 2316 #global-interrupts = <1>;
2382 interrupts = <GIC_SPI 2317 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
2383 <GIC_SPI 2318 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
2384 <GIC_SPI 2319 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
2385 #iommu-cells = <1>; 2320 #iommu-cells = <1>;
2386 clocks = <&mmcc SMMU_ 2321 clocks = <&mmcc SMMU_MDP_AXI_CLK>,
2387 <&mmcc SMMU_ 2322 <&mmcc SMMU_MDP_AHB_CLK>;
2388 clock-names = "bus", 2323 clock-names = "bus", "iface";
2389 2324
2390 power-domains = <&mmc 2325 power-domains = <&mmcc MDSS_GDSC>;
2391 }; 2326 };
2392 2327
2393 venus_smmu: iommu@d40000 { 2328 venus_smmu: iommu@d40000 {
2394 compatible = "qcom,ms 2329 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2395 reg = <0x00d40000 0x2 2330 reg = <0x00d40000 0x20000>;
2396 #global-interrupts = 2331 #global-interrupts = <1>;
2397 interrupts = <GIC_SPI 2332 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>,
2398 <GIC_SPI 2333 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
2399 <GIC_SPI 2334 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
2400 <GIC_SPI 2335 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
2401 <GIC_SPI 2336 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
2402 <GIC_SPI 2337 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
2403 <GIC_SPI 2338 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
2404 <GIC_SPI 2339 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
2405 power-domains = <&mmc 2340 power-domains = <&mmcc MMAGIC_VIDEO_GDSC>;
2406 clocks = <&mmcc SMMU_ 2341 clocks = <&mmcc SMMU_VIDEO_AXI_CLK>,
2407 <&mmcc SMMU_ 2342 <&mmcc SMMU_VIDEO_AHB_CLK>;
2408 clock-names = "bus", 2343 clock-names = "bus", "iface";
2409 #iommu-cells = <1>; 2344 #iommu-cells = <1>;
2410 status = "okay"; 2345 status = "okay";
2411 }; 2346 };
2412 2347
2413 vfe_smmu: iommu@da0000 { 2348 vfe_smmu: iommu@da0000 {
2414 compatible = "qcom,ms 2349 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2415 reg = <0x00da0000 0x1 2350 reg = <0x00da0000 0x10000>;
2416 2351
2417 #global-interrupts = 2352 #global-interrupts = <1>;
2418 interrupts = <GIC_SPI 2353 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
2419 <GIC_SPI 2354 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
2420 <GIC_SPI 2355 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
2421 power-domains = <&mmc 2356 power-domains = <&mmcc MMAGIC_CAMSS_GDSC>;
2422 clocks = <&mmcc SMMU_ 2357 clocks = <&mmcc SMMU_VFE_AXI_CLK>,
2423 <&mmcc SMMU_ 2358 <&mmcc SMMU_VFE_AHB_CLK>;
2424 clock-names = "bus", 2359 clock-names = "bus", "iface";
2425 #iommu-cells = <1>; 2360 #iommu-cells = <1>;
2426 }; 2361 };
2427 2362
2428 lpass_q6_smmu: iommu@1600000 2363 lpass_q6_smmu: iommu@1600000 {
2429 compatible = "qcom,ms 2364 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2430 reg = <0x01600000 0x2 2365 reg = <0x01600000 0x20000>;
2431 #iommu-cells = <1>; 2366 #iommu-cells = <1>;
2432 power-domains = <&gcc 2367 power-domains = <&gcc HLOS1_VOTE_LPASS_CORE_GDSC>;
2433 2368
2434 #global-interrupts = 2369 #global-interrupts = <1>;
2435 interrupts = <GIC_SPI 2370 interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
2436 <GIC_SPI 226 2371 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,
2437 <GIC_SPI 393 2372 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
2438 <GIC_SPI 394 2373 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
2439 <GIC_SPI 395 2374 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
2440 <GIC_SPI 396 2375 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
2441 <GIC_SPI 397 2376 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
2442 <GIC_SPI 398 2377 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
2443 <GIC_SPI 399 2378 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
2444 <GIC_SPI 400 2379 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
2445 <GIC_SPI 401 2380 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
2446 <GIC_SPI 402 2381 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
2447 <GIC_SPI 403 2382 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>;
2448 2383
2449 clocks = <&gcc GCC_HL 2384 clocks = <&gcc GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>,
2450 <&gcc GCC_HL 2385 <&gcc GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK>;
2451 clock-names = "bus", 2386 clock-names = "bus", "iface";
2452 }; 2387 };
2453 2388
2454 slpi_pil: remoteproc@1c00000 2389 slpi_pil: remoteproc@1c00000 {
2455 compatible = "qcom,ms 2390 compatible = "qcom,msm8996-slpi-pil";
2456 reg = <0x01c00000 0x4 2391 reg = <0x01c00000 0x4000>;
2457 2392
2458 interrupts-extended = 2393 interrupts-extended = <&intc 0 390 IRQ_TYPE_EDGE_RISING>,
2459 2394 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2460 2395 <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2461 2396 <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2462 2397 <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
2463 interrupt-names = "wd 2398 interrupt-names = "wdog",
2464 "fa 2399 "fatal",
2465 "re 2400 "ready",
2466 "ha 2401 "handover",
2467 "st 2402 "stop-ack";
2468 2403
2469 clocks = <&xo_board>; !! 2404 clocks = <&xo_board>,
2470 clock-names = "xo"; !! 2405 <&rpmcc RPM_SMD_AGGR2_NOC_CLK>;
>> 2406 clock-names = "xo", "aggre2";
2471 2407
2472 memory-region = <&slp 2408 memory-region = <&slpi_mem>;
2473 2409
2474 qcom,smem-states = <& 2410 qcom,smem-states = <&slpi_smp2p_out 0>;
2475 qcom,smem-state-names 2411 qcom,smem-state-names = "stop";
2476 2412
2477 power-domains = <&rpm 2413 power-domains = <&rpmpd MSM8996_VDDSSCX>;
2478 power-domain-names = 2414 power-domain-names = "ssc_cx";
2479 2415
2480 status = "disabled"; 2416 status = "disabled";
2481 2417
2482 glink-edge { <<
2483 interrupts = <<
2484 label = "dsps <<
2485 qcom,remote-p <<
2486 mboxes = <&ap <<
2487 }; <<
2488 <<
2489 smd-edge { 2418 smd-edge {
2490 interrupts = 2419 interrupts = <GIC_SPI 176 IRQ_TYPE_EDGE_RISING>;
2491 2420
2492 label = "dsps 2421 label = "dsps";
2493 mboxes = <&ap 2422 mboxes = <&apcs_glb 25>;
2494 qcom,smd-edge 2423 qcom,smd-edge = <3>;
2495 qcom,remote-p 2424 qcom,remote-pid = <3>;
2496 }; 2425 };
2497 }; 2426 };
2498 2427
2499 mss_pil: remoteproc@2080000 { 2428 mss_pil: remoteproc@2080000 {
2500 compatible = "qcom,ms 2429 compatible = "qcom,msm8996-mss-pil";
2501 reg = <0x2080000 0x10 2430 reg = <0x2080000 0x100>,
2502 <0x2180000 0x02 2431 <0x2180000 0x020>;
2503 reg-names = "qdsp6", 2432 reg-names = "qdsp6", "rmb";
2504 2433
2505 interrupts-extended = 2434 interrupts-extended = <&intc 0 448 IRQ_TYPE_EDGE_RISING>,
2506 2435 <&mpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2507 2436 <&mpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2508 2437 <&mpss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2509 2438 <&mpss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
2510 2439 <&mpss_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
2511 interrupt-names = "wd 2440 interrupt-names = "wdog", "fatal", "ready",
2512 "ha 2441 "handover", "stop-ack",
2513 "sh 2442 "shutdown-ack";
2514 2443
2515 clocks = <&gcc GCC_MS 2444 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
2516 <&gcc GCC_MS 2445 <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>,
2517 <&gcc GCC_BO 2446 <&gcc GCC_BOOT_ROM_AHB_CLK>,
2518 <&xo_board>, 2447 <&xo_board>,
2519 <&gcc GCC_MS 2448 <&gcc GCC_MSS_GPLL0_DIV_CLK>,
2520 <&gcc GCC_MS 2449 <&gcc GCC_MSS_SNOC_AXI_CLK>,
2521 <&gcc GCC_MS 2450 <&gcc GCC_MSS_MNOC_BIMC_AXI_CLK>,
>> 2451 <&rpmcc RPM_SMD_PCNOC_CLK>,
2522 <&rpmcc RPM_ 2452 <&rpmcc RPM_SMD_QDSS_CLK>;
2523 clock-names = "iface" !! 2453 clock-names = "iface", "bus", "mem", "xo", "gpll0_mss",
2524 "bus", !! 2454 "snoc_axi", "mnoc_axi", "pnoc", "qdss";
2525 "mem", <<
2526 "xo", <<
2527 "gpll0_ <<
2528 "snoc_a <<
2529 "mnoc_a <<
2530 "qdss"; <<
2531 2455
2532 resets = <&gcc GCC_MS 2456 resets = <&gcc GCC_MSS_RESTART>;
2533 reset-names = "mss_re 2457 reset-names = "mss_restart";
2534 2458
2535 power-domains = <&rpm 2459 power-domains = <&rpmpd MSM8996_VDDCX>,
2536 <&rpm 2460 <&rpmpd MSM8996_VDDMX>;
2537 power-domain-names = 2461 power-domain-names = "cx", "mx";
2538 2462
2539 qcom,smem-states = <& 2463 qcom,smem-states = <&mpss_smp2p_out 0>;
2540 qcom,smem-state-names 2464 qcom,smem-state-names = "stop";
2541 2465
2542 qcom,halt-regs = <&tc 2466 qcom,halt-regs = <&tcsr_1 0x3000 0x5000 0x4000>;
2543 2467
2544 status = "disabled"; 2468 status = "disabled";
2545 2469
2546 mba { 2470 mba {
2547 memory-region 2471 memory-region = <&mba_mem>;
2548 }; 2472 };
2549 2473
2550 mpss { 2474 mpss {
2551 memory-region 2475 memory-region = <&mpss_mem>;
2552 }; 2476 };
2553 2477
2554 metadata { 2478 metadata {
2555 memory-region 2479 memory-region = <&mdata_mem>;
2556 }; 2480 };
2557 2481
2558 glink-edge { <<
2559 interrupts = <<
2560 label = "mode <<
2561 qcom,remote-p <<
2562 mboxes = <&ap <<
2563 }; <<
2564 <<
2565 smd-edge { 2482 smd-edge {
2566 interrupts = 2483 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
2567 2484
2568 label = "mpss 2485 label = "mpss";
2569 mboxes = <&ap 2486 mboxes = <&apcs_glb 12>;
2570 qcom,smd-edge 2487 qcom,smd-edge = <0>;
2571 qcom,remote-p 2488 qcom,remote-pid = <1>;
2572 }; 2489 };
2573 }; 2490 };
2574 2491
2575 stm@3002000 { 2492 stm@3002000 {
2576 compatible = "arm,cor 2493 compatible = "arm,coresight-stm", "arm,primecell";
2577 reg = <0x3002000 0x10 2494 reg = <0x3002000 0x1000>,
2578 <0x8280000 0x18 2495 <0x8280000 0x180000>;
2579 reg-names = "stm-base 2496 reg-names = "stm-base", "stm-stimulus-base";
2580 2497
2581 clocks = <&rpmcc RPM_ 2498 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2582 clock-names = "apb_pc 2499 clock-names = "apb_pclk", "atclk";
2583 2500
2584 out-ports { 2501 out-ports {
2585 port { 2502 port {
2586 stm_o 2503 stm_out: endpoint {
2587 2504 remote-endpoint =
2588 2505 <&funnel0_in>;
2589 }; 2506 };
2590 }; 2507 };
2591 }; 2508 };
2592 }; 2509 };
2593 2510
2594 tpiu@3020000 { 2511 tpiu@3020000 {
2595 compatible = "arm,cor 2512 compatible = "arm,coresight-tpiu", "arm,primecell";
2596 reg = <0x3020000 0x10 2513 reg = <0x3020000 0x1000>;
2597 2514
2598 clocks = <&rpmcc RPM_ 2515 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2599 clock-names = "apb_pc 2516 clock-names = "apb_pclk", "atclk";
2600 2517
2601 in-ports { 2518 in-ports {
2602 port { 2519 port {
2603 tpiu_ 2520 tpiu_in: endpoint {
2604 2521 remote-endpoint =
2605 2522 <&replicator_out1>;
2606 }; 2523 };
2607 }; 2524 };
2608 }; 2525 };
2609 }; 2526 };
2610 2527
2611 funnel@3021000 { 2528 funnel@3021000 {
2612 compatible = "arm,cor 2529 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2613 reg = <0x3021000 0x10 2530 reg = <0x3021000 0x1000>;
2614 2531
2615 clocks = <&rpmcc RPM_ 2532 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2616 clock-names = "apb_pc 2533 clock-names = "apb_pclk", "atclk";
2617 2534
2618 in-ports { 2535 in-ports {
2619 #address-cell 2536 #address-cells = <1>;
2620 #size-cells = 2537 #size-cells = <0>;
2621 2538
2622 port@7 { 2539 port@7 {
2623 reg = 2540 reg = <7>;
2624 funne 2541 funnel0_in: endpoint {
2625 2542 remote-endpoint =
2626 2543 <&stm_out>;
2627 }; 2544 };
2628 }; 2545 };
2629 }; 2546 };
2630 2547
2631 out-ports { 2548 out-ports {
2632 port { 2549 port {
2633 funne 2550 funnel0_out: endpoint {
2634 2551 remote-endpoint =
2635 2552 <&merge_funnel_in0>;
2636 }; 2553 };
2637 }; 2554 };
2638 }; 2555 };
2639 }; 2556 };
2640 2557
2641 funnel@3022000 { 2558 funnel@3022000 {
2642 compatible = "arm,cor 2559 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2643 reg = <0x3022000 0x10 2560 reg = <0x3022000 0x1000>;
2644 2561
2645 clocks = <&rpmcc RPM_ 2562 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2646 clock-names = "apb_pc 2563 clock-names = "apb_pclk", "atclk";
2647 2564
2648 in-ports { 2565 in-ports {
2649 #address-cell 2566 #address-cells = <1>;
2650 #size-cells = 2567 #size-cells = <0>;
2651 2568
2652 port@6 { 2569 port@6 {
2653 reg = 2570 reg = <6>;
2654 funne 2571 funnel1_in: endpoint {
2655 2572 remote-endpoint =
2656 2573 <&apss_merge_funnel_out>;
2657 }; 2574 };
2658 }; 2575 };
2659 }; 2576 };
2660 2577
2661 out-ports { 2578 out-ports {
2662 port { 2579 port {
2663 funne 2580 funnel1_out: endpoint {
2664 2581 remote-endpoint =
2665 2582 <&merge_funnel_in1>;
2666 }; 2583 };
2667 }; 2584 };
2668 }; 2585 };
2669 }; 2586 };
2670 2587
2671 funnel@3023000 { 2588 funnel@3023000 {
2672 compatible = "arm,cor 2589 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2673 reg = <0x3023000 0x10 2590 reg = <0x3023000 0x1000>;
2674 2591
2675 clocks = <&rpmcc RPM_ 2592 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2676 clock-names = "apb_pc 2593 clock-names = "apb_pclk", "atclk";
2677 2594
2678 in-ports { <<
2679 port { <<
2680 funne <<
2681 <<
2682 <<
2683 }; <<
2684 }; <<
2685 }; <<
2686 2595
2687 out-ports { 2596 out-ports {
2688 port { 2597 port {
2689 funne 2598 funnel2_out: endpoint {
2690 2599 remote-endpoint =
2691 2600 <&merge_funnel_in2>;
2692 }; 2601 };
2693 }; 2602 };
2694 }; 2603 };
2695 }; 2604 };
2696 2605
2697 funnel@3025000 { 2606 funnel@3025000 {
2698 compatible = "arm,cor 2607 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2699 reg = <0x3025000 0x10 2608 reg = <0x3025000 0x1000>;
2700 2609
2701 clocks = <&rpmcc RPM_ 2610 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2702 clock-names = "apb_pc 2611 clock-names = "apb_pclk", "atclk";
2703 2612
2704 in-ports { 2613 in-ports {
2705 #address-cell 2614 #address-cells = <1>;
2706 #size-cells = 2615 #size-cells = <0>;
2707 2616
2708 port@0 { 2617 port@0 {
2709 reg = 2618 reg = <0>;
2710 merge 2619 merge_funnel_in0: endpoint {
2711 2620 remote-endpoint =
2712 2621 <&funnel0_out>;
2713 }; 2622 };
2714 }; 2623 };
2715 2624
2716 port@1 { 2625 port@1 {
2717 reg = 2626 reg = <1>;
2718 merge 2627 merge_funnel_in1: endpoint {
2719 2628 remote-endpoint =
2720 2629 <&funnel1_out>;
2721 }; 2630 };
2722 }; 2631 };
2723 2632
2724 port@2 { 2633 port@2 {
2725 reg = 2634 reg = <2>;
2726 merge 2635 merge_funnel_in2: endpoint {
2727 2636 remote-endpoint =
2728 2637 <&funnel2_out>;
2729 }; 2638 };
2730 }; 2639 };
2731 }; 2640 };
2732 2641
2733 out-ports { 2642 out-ports {
2734 port { 2643 port {
2735 merge 2644 merge_funnel_out: endpoint {
2736 2645 remote-endpoint =
2737 2646 <&etf_in>;
2738 }; 2647 };
2739 }; 2648 };
2740 }; 2649 };
2741 }; 2650 };
2742 2651
2743 replicator@3026000 { 2652 replicator@3026000 {
2744 compatible = "arm,cor 2653 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2745 reg = <0x3026000 0x10 2654 reg = <0x3026000 0x1000>;
2746 2655
2747 clocks = <&rpmcc RPM_ 2656 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2748 clock-names = "apb_pc 2657 clock-names = "apb_pclk", "atclk";
2749 2658
2750 in-ports { 2659 in-ports {
2751 port { 2660 port {
2752 repli 2661 replicator_in: endpoint {
2753 2662 remote-endpoint =
2754 2663 <&etf_out>;
2755 }; 2664 };
2756 }; 2665 };
2757 }; 2666 };
2758 2667
2759 out-ports { 2668 out-ports {
2760 #address-cell 2669 #address-cells = <1>;
2761 #size-cells = 2670 #size-cells = <0>;
2762 2671
2763 port@0 { 2672 port@0 {
2764 reg = 2673 reg = <0>;
2765 repli 2674 replicator_out0: endpoint {
2766 2675 remote-endpoint =
2767 2676 <&etr_in>;
2768 }; 2677 };
2769 }; 2678 };
2770 2679
2771 port@1 { 2680 port@1 {
2772 reg = 2681 reg = <1>;
2773 repli 2682 replicator_out1: endpoint {
2774 2683 remote-endpoint =
2775 2684 <&tpiu_in>;
2776 }; 2685 };
2777 }; 2686 };
2778 }; 2687 };
2779 }; 2688 };
2780 2689
2781 etf@3027000 { 2690 etf@3027000 {
2782 compatible = "arm,cor 2691 compatible = "arm,coresight-tmc", "arm,primecell";
2783 reg = <0x3027000 0x10 2692 reg = <0x3027000 0x1000>;
2784 2693
2785 clocks = <&rpmcc RPM_ 2694 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2786 clock-names = "apb_pc 2695 clock-names = "apb_pclk", "atclk";
2787 2696
2788 in-ports { 2697 in-ports {
2789 port { 2698 port {
2790 etf_i 2699 etf_in: endpoint {
2791 2700 remote-endpoint =
2792 2701 <&merge_funnel_out>;
2793 }; 2702 };
2794 }; 2703 };
2795 }; 2704 };
2796 2705
2797 out-ports { 2706 out-ports {
2798 port { 2707 port {
2799 etf_o 2708 etf_out: endpoint {
2800 2709 remote-endpoint =
2801 2710 <&replicator_in>;
2802 }; 2711 };
2803 }; 2712 };
2804 }; 2713 };
2805 }; 2714 };
2806 2715
2807 etr@3028000 { 2716 etr@3028000 {
2808 compatible = "arm,cor 2717 compatible = "arm,coresight-tmc", "arm,primecell";
2809 reg = <0x3028000 0x10 2718 reg = <0x3028000 0x1000>;
2810 2719
2811 clocks = <&rpmcc RPM_ 2720 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2812 clock-names = "apb_pc 2721 clock-names = "apb_pclk", "atclk";
2813 arm,scatter-gather; 2722 arm,scatter-gather;
2814 2723
2815 in-ports { 2724 in-ports {
2816 port { 2725 port {
2817 etr_i 2726 etr_in: endpoint {
2818 2727 remote-endpoint =
2819 2728 <&replicator_out0>;
2820 }; 2729 };
2821 }; 2730 };
2822 }; 2731 };
2823 }; 2732 };
2824 2733
2825 debug@3810000 { 2734 debug@3810000 {
2826 compatible = "arm,cor 2735 compatible = "arm,coresight-cpu-debug", "arm,primecell";
2827 reg = <0x3810000 0x10 2736 reg = <0x3810000 0x1000>;
2828 2737
2829 clocks = <&rpmcc RPM_ 2738 clocks = <&rpmcc RPM_QDSS_CLK>;
2830 clock-names = "apb_pc 2739 clock-names = "apb_pclk";
2831 2740
2832 cpu = <&CPU0>; 2741 cpu = <&CPU0>;
2833 }; 2742 };
2834 2743
2835 etm@3840000 { 2744 etm@3840000 {
2836 compatible = "arm,cor 2745 compatible = "arm,coresight-etm4x", "arm,primecell";
2837 reg = <0x3840000 0x10 2746 reg = <0x3840000 0x1000>;
2838 2747
2839 clocks = <&rpmcc RPM_ 2748 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2840 clock-names = "apb_pc 2749 clock-names = "apb_pclk", "atclk";
2841 2750
2842 cpu = <&CPU0>; 2751 cpu = <&CPU0>;
2843 2752
2844 out-ports { 2753 out-ports {
2845 port { 2754 port {
2846 etm0_ 2755 etm0_out: endpoint {
2847 2756 remote-endpoint =
2848 2757 <&apss_funnel0_in0>;
2849 }; 2758 };
2850 }; 2759 };
2851 }; 2760 };
2852 }; 2761 };
2853 2762
2854 debug@3910000 { 2763 debug@3910000 {
2855 compatible = "arm,cor 2764 compatible = "arm,coresight-cpu-debug", "arm,primecell";
2856 reg = <0x3910000 0x10 2765 reg = <0x3910000 0x1000>;
2857 2766
2858 clocks = <&rpmcc RPM_ 2767 clocks = <&rpmcc RPM_QDSS_CLK>;
2859 clock-names = "apb_pc 2768 clock-names = "apb_pclk";
2860 2769
2861 cpu = <&CPU1>; 2770 cpu = <&CPU1>;
2862 }; 2771 };
2863 2772
2864 etm@3940000 { 2773 etm@3940000 {
2865 compatible = "arm,cor 2774 compatible = "arm,coresight-etm4x", "arm,primecell";
2866 reg = <0x3940000 0x10 2775 reg = <0x3940000 0x1000>;
2867 2776
2868 clocks = <&rpmcc RPM_ 2777 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2869 clock-names = "apb_pc 2778 clock-names = "apb_pclk", "atclk";
2870 2779
2871 cpu = <&CPU1>; 2780 cpu = <&CPU1>;
2872 2781
2873 out-ports { 2782 out-ports {
2874 port { 2783 port {
2875 etm1_ 2784 etm1_out: endpoint {
2876 2785 remote-endpoint =
2877 2786 <&apss_funnel0_in1>;
2878 }; 2787 };
2879 }; 2788 };
2880 }; 2789 };
2881 }; 2790 };
2882 2791
2883 funnel@39b0000 { /* APSS Funn 2792 funnel@39b0000 { /* APSS Funnel 0 */
2884 compatible = "arm,cor 2793 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2885 reg = <0x39b0000 0x10 2794 reg = <0x39b0000 0x1000>;
2886 2795
2887 clocks = <&rpmcc RPM_ 2796 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2888 clock-names = "apb_pc 2797 clock-names = "apb_pclk", "atclk";
2889 2798
2890 in-ports { 2799 in-ports {
2891 #address-cell 2800 #address-cells = <1>;
2892 #size-cells = 2801 #size-cells = <0>;
2893 2802
2894 port@0 { 2803 port@0 {
2895 reg = 2804 reg = <0>;
2896 apss_ 2805 apss_funnel0_in0: endpoint {
2897 2806 remote-endpoint = <&etm0_out>;
2898 }; 2807 };
2899 }; 2808 };
2900 2809
2901 port@1 { 2810 port@1 {
2902 reg = 2811 reg = <1>;
2903 apss_ 2812 apss_funnel0_in1: endpoint {
2904 2813 remote-endpoint = <&etm1_out>;
2905 }; 2814 };
2906 }; 2815 };
2907 }; 2816 };
2908 2817
2909 out-ports { 2818 out-ports {
2910 port { 2819 port {
2911 apss_ 2820 apss_funnel0_out: endpoint {
2912 2821 remote-endpoint =
2913 2822 <&apss_merge_funnel_in0>;
2914 }; 2823 };
2915 }; 2824 };
2916 }; 2825 };
2917 }; 2826 };
2918 2827
2919 debug@3a10000 { 2828 debug@3a10000 {
2920 compatible = "arm,cor 2829 compatible = "arm,coresight-cpu-debug", "arm,primecell";
2921 reg = <0x3a10000 0x10 2830 reg = <0x3a10000 0x1000>;
2922 2831
2923 clocks = <&rpmcc RPM_ 2832 clocks = <&rpmcc RPM_QDSS_CLK>;
2924 clock-names = "apb_pc 2833 clock-names = "apb_pclk";
2925 2834
2926 cpu = <&CPU2>; 2835 cpu = <&CPU2>;
2927 }; 2836 };
2928 2837
2929 etm@3a40000 { 2838 etm@3a40000 {
2930 compatible = "arm,cor 2839 compatible = "arm,coresight-etm4x", "arm,primecell";
2931 reg = <0x3a40000 0x10 2840 reg = <0x3a40000 0x1000>;
2932 2841
2933 clocks = <&rpmcc RPM_ 2842 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2934 clock-names = "apb_pc 2843 clock-names = "apb_pclk", "atclk";
2935 2844
2936 cpu = <&CPU2>; 2845 cpu = <&CPU2>;
2937 2846
2938 out-ports { 2847 out-ports {
2939 port { 2848 port {
2940 etm2_ 2849 etm2_out: endpoint {
2941 2850 remote-endpoint =
2942 2851 <&apss_funnel1_in0>;
2943 }; 2852 };
2944 }; 2853 };
2945 }; 2854 };
2946 }; 2855 };
2947 2856
2948 debug@3b10000 { 2857 debug@3b10000 {
2949 compatible = "arm,cor 2858 compatible = "arm,coresight-cpu-debug", "arm,primecell";
2950 reg = <0x3b10000 0x10 2859 reg = <0x3b10000 0x1000>;
2951 2860
2952 clocks = <&rpmcc RPM_ 2861 clocks = <&rpmcc RPM_QDSS_CLK>;
2953 clock-names = "apb_pc 2862 clock-names = "apb_pclk";
2954 2863
2955 cpu = <&CPU3>; 2864 cpu = <&CPU3>;
2956 }; 2865 };
2957 2866
2958 etm@3b40000 { 2867 etm@3b40000 {
2959 compatible = "arm,cor 2868 compatible = "arm,coresight-etm4x", "arm,primecell";
2960 reg = <0x3b40000 0x10 2869 reg = <0x3b40000 0x1000>;
2961 2870
2962 clocks = <&rpmcc RPM_ 2871 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2963 clock-names = "apb_pc 2872 clock-names = "apb_pclk", "atclk";
2964 2873
2965 cpu = <&CPU3>; 2874 cpu = <&CPU3>;
2966 2875
2967 out-ports { 2876 out-ports {
2968 port { 2877 port {
2969 etm3_ 2878 etm3_out: endpoint {
2970 2879 remote-endpoint =
2971 2880 <&apss_funnel1_in1>;
2972 }; 2881 };
2973 }; 2882 };
2974 }; 2883 };
2975 }; 2884 };
2976 2885
2977 funnel@3bb0000 { /* APSS Funn 2886 funnel@3bb0000 { /* APSS Funnel 1 */
2978 compatible = "arm,cor 2887 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2979 reg = <0x3bb0000 0x10 2888 reg = <0x3bb0000 0x1000>;
2980 2889
2981 clocks = <&rpmcc RPM_ 2890 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2982 clock-names = "apb_pc 2891 clock-names = "apb_pclk", "atclk";
2983 2892
2984 in-ports { 2893 in-ports {
2985 #address-cell 2894 #address-cells = <1>;
2986 #size-cells = 2895 #size-cells = <0>;
2987 2896
2988 port@0 { 2897 port@0 {
2989 reg = 2898 reg = <0>;
2990 apss_ 2899 apss_funnel1_in0: endpoint {
2991 2900 remote-endpoint = <&etm2_out>;
2992 }; 2901 };
2993 }; 2902 };
2994 2903
2995 port@1 { 2904 port@1 {
2996 reg = 2905 reg = <1>;
2997 apss_ 2906 apss_funnel1_in1: endpoint {
2998 2907 remote-endpoint = <&etm3_out>;
2999 }; 2908 };
3000 }; 2909 };
3001 }; 2910 };
3002 2911
3003 out-ports { 2912 out-ports {
3004 port { 2913 port {
3005 apss_ 2914 apss_funnel1_out: endpoint {
3006 2915 remote-endpoint =
3007 2916 <&apss_merge_funnel_in1>;
3008 }; 2917 };
3009 }; 2918 };
3010 }; 2919 };
3011 }; 2920 };
3012 2921
3013 funnel@3bc0000 { 2922 funnel@3bc0000 {
3014 compatible = "arm,cor 2923 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3015 reg = <0x3bc0000 0x10 2924 reg = <0x3bc0000 0x1000>;
3016 2925
3017 clocks = <&rpmcc RPM_ 2926 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
3018 clock-names = "apb_pc 2927 clock-names = "apb_pclk", "atclk";
3019 2928
3020 in-ports { 2929 in-ports {
3021 #address-cell 2930 #address-cells = <1>;
3022 #size-cells = 2931 #size-cells = <0>;
3023 2932
3024 port@0 { 2933 port@0 {
3025 reg = 2934 reg = <0>;
3026 apss_ 2935 apss_merge_funnel_in0: endpoint {
3027 2936 remote-endpoint =
3028 2937 <&apss_funnel0_out>;
3029 }; 2938 };
3030 }; 2939 };
3031 2940
3032 port@1 { 2941 port@1 {
3033 reg = 2942 reg = <1>;
3034 apss_ 2943 apss_merge_funnel_in1: endpoint {
3035 2944 remote-endpoint =
3036 2945 <&apss_funnel1_out>;
3037 }; 2946 };
3038 }; 2947 };
3039 }; 2948 };
3040 2949
3041 out-ports { 2950 out-ports {
3042 port { 2951 port {
3043 apss_ 2952 apss_merge_funnel_out: endpoint {
3044 2953 remote-endpoint =
3045 2954 <&funnel1_in>;
3046 }; 2955 };
3047 }; 2956 };
3048 }; 2957 };
3049 }; 2958 };
3050 2959
3051 kryocc: clock-controller@6400 2960 kryocc: clock-controller@6400000 {
3052 compatible = "qcom,ms 2961 compatible = "qcom,msm8996-apcc";
3053 reg = <0x06400000 0x9 2962 reg = <0x06400000 0x90000>;
3054 2963
3055 clock-names = "xo", " 2964 clock-names = "xo", "sys_apcs_aux";
3056 clocks = <&rpmcc RPM_ 2965 clocks = <&rpmcc RPM_SMD_XO_A_CLK_SRC>, <&apcs_glb>;
3057 2966
3058 #clock-cells = <1>; 2967 #clock-cells = <1>;
3059 }; 2968 };
3060 2969
3061 usb3: usb@6af8800 { 2970 usb3: usb@6af8800 {
3062 compatible = "qcom,ms 2971 compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
3063 reg = <0x06af8800 0x4 2972 reg = <0x06af8800 0x400>;
3064 #address-cells = <1>; 2973 #address-cells = <1>;
3065 #size-cells = <1>; 2974 #size-cells = <1>;
3066 ranges; 2975 ranges;
3067 2976
3068 interrupts = <GIC_SPI 2977 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
3069 <GIC_SPI 2978 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
3070 interrupt-names = "hs 2979 interrupt-names = "hs_phy_irq", "ss_phy_irq";
3071 2980
3072 clocks = <&gcc GCC_SY 2981 clocks = <&gcc GCC_SYS_NOC_USB3_AXI_CLK>,
3073 <&gcc GCC_US 2982 <&gcc GCC_USB30_MASTER_CLK>,
3074 <&gcc GCC_AG 2983 <&gcc GCC_AGGRE2_USB3_AXI_CLK>,
3075 <&gcc GCC_US 2984 <&gcc GCC_USB30_SLEEP_CLK>,
3076 <&gcc GCC_US 2985 <&gcc GCC_USB30_MOCK_UTMI_CLK>;
3077 clock-names = "cfg_no 2986 clock-names = "cfg_noc",
3078 "core", 2987 "core",
3079 "iface" 2988 "iface",
3080 "sleep" 2989 "sleep",
3081 "mock_u 2990 "mock_utmi";
3082 2991
3083 assigned-clocks = <&g 2992 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
3084 <&g 2993 <&gcc GCC_USB30_MASTER_CLK>;
3085 assigned-clock-rates 2994 assigned-clock-rates = <19200000>, <120000000>;
3086 2995
3087 interconnects = <&a2n 2996 interconnects = <&a2noc MASTER_USB3 &bimc SLAVE_EBI_CH0>,
3088 <&bim 2997 <&bimc MASTER_AMPSS_M0 &snoc SLAVE_USB3>;
3089 interconnect-names = 2998 interconnect-names = "usb-ddr", "apps-usb";
3090 2999
3091 power-domains = <&gcc 3000 power-domains = <&gcc USB30_GDSC>;
3092 status = "disabled"; 3001 status = "disabled";
3093 3002
3094 usb3_dwc3: usb@6a0000 3003 usb3_dwc3: usb@6a00000 {
3095 compatible = 3004 compatible = "snps,dwc3";
3096 reg = <0x06a0 3005 reg = <0x06a00000 0xcc00>;
3097 interrupts = !! 3006 interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>;
3098 phys = <&hsus !! 3007 phys = <&hsusb_phy1>, <&ssusb_phy_0>;
3099 phy-names = " 3008 phy-names = "usb2-phy", "usb3-phy";
3100 snps,hird-thr 3009 snps,hird-threshold = /bits/ 8 <0>;
3101 snps,dis_u2_s 3010 snps,dis_u2_susphy_quirk;
3102 snps,dis_enbl 3011 snps,dis_enblslpm_quirk;
3103 snps,is-utmi- 3012 snps,is-utmi-l1-suspend;
3104 snps,parkmode <<
3105 tx-fifo-resiz 3013 tx-fifo-resize;
3106 }; 3014 };
3107 }; 3015 };
3108 3016
3109 usb3phy: phy@7410000 { 3017 usb3phy: phy@7410000 {
3110 compatible = "qcom,ms 3018 compatible = "qcom,msm8996-qmp-usb3-phy";
3111 reg = <0x07410000 0x1 !! 3019 reg = <0x07410000 0x1c4>;
>> 3020 #address-cells = <1>;
>> 3021 #size-cells = <1>;
>> 3022 ranges;
3112 3023
3113 clocks = <&gcc GCC_US 3024 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
3114 <&gcc GCC_US !! 3025 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
3115 <&gcc GCC_US !! 3026 <&gcc GCC_USB3_CLKREF_CLK>;
3116 <&gcc GCC_US !! 3027 clock-names = "aux", "cfg_ahb", "ref";
3117 clock-names = "aux", <<
3118 "ref", <<
3119 "cfg_ah <<
3120 "pipe"; <<
3121 clock-output-names = <<
3122 #clock-cells = <0>; <<
3123 #phy-cells = <0>; <<
3124 3028
3125 resets = <&gcc GCC_US 3029 resets = <&gcc GCC_USB3_PHY_BCR>,
3126 <&gcc GCC_US !! 3030 <&gcc GCC_USB3PHY_PHY_BCR>;
3127 reset-names = "phy", !! 3031 reset-names = "phy", "common";
3128 "phy_ph <<
3129 <<
3130 status = "disabled"; 3032 status = "disabled";
>> 3033
>> 3034 ssusb_phy_0: phy@7410200 {
>> 3035 reg = <0x07410200 0x200>,
>> 3036 <0x07410400 0x130>,
>> 3037 <0x07410600 0x1a8>;
>> 3038 #phy-cells = <0>;
>> 3039
>> 3040 #clock-cells = <0>;
>> 3041 clock-output-names = "usb3_phy_pipe_clk_src";
>> 3042 clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
>> 3043 clock-names = "pipe0";
>> 3044 };
3131 }; 3045 };
3132 3046
3133 hsusb_phy1: phy@7411000 { 3047 hsusb_phy1: phy@7411000 {
3134 compatible = "qcom,ms 3048 compatible = "qcom,msm8996-qusb2-phy";
3135 reg = <0x07411000 0x1 3049 reg = <0x07411000 0x180>;
3136 #phy-cells = <0>; 3050 #phy-cells = <0>;
3137 3051
3138 clocks = <&gcc GCC_US 3052 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
3139 <&gcc GCC_RX1 3053 <&gcc GCC_RX1_USB2_CLKREF_CLK>;
3140 clock-names = "cfg_ah 3054 clock-names = "cfg_ahb", "ref";
3141 3055
3142 resets = <&gcc GCC_QU 3056 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
3143 nvmem-cells = <&qusb2 3057 nvmem-cells = <&qusb2p_hstx_trim>;
3144 status = "disabled"; 3058 status = "disabled";
3145 }; 3059 };
3146 3060
3147 hsusb_phy2: phy@7412000 { 3061 hsusb_phy2: phy@7412000 {
3148 compatible = "qcom,ms 3062 compatible = "qcom,msm8996-qusb2-phy";
3149 reg = <0x07412000 0x1 3063 reg = <0x07412000 0x180>;
3150 #phy-cells = <0>; 3064 #phy-cells = <0>;
3151 3065
3152 clocks = <&gcc GCC_US 3066 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
3153 <&gcc GCC_RX2 3067 <&gcc GCC_RX2_USB2_CLKREF_CLK>;
3154 clock-names = "cfg_ah 3068 clock-names = "cfg_ahb", "ref";
3155 3069
3156 resets = <&gcc GCC_QU 3070 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
3157 nvmem-cells = <&qusb2 3071 nvmem-cells = <&qusb2s_hstx_trim>;
3158 status = "disabled"; 3072 status = "disabled";
3159 }; 3073 };
3160 3074
3161 sdhc1: mmc@7464900 { 3075 sdhc1: mmc@7464900 {
3162 compatible = "qcom,ms 3076 compatible = "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4";
3163 reg = <0x07464900 0x1 3077 reg = <0x07464900 0x11c>, <0x07464000 0x800>;
3164 reg-names = "hc", "co 3078 reg-names = "hc", "core";
3165 3079
3166 interrupts = <GIC_SPI 3080 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
3167 <GIC_ 3081 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
3168 interrupt-names = "hc 3082 interrupt-names = "hc_irq", "pwr_irq";
3169 3083
3170 clock-names = "iface" 3084 clock-names = "iface", "core", "xo";
3171 clocks = <&gcc GCC_SD 3085 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
3172 <&gcc GCC_SDC 3086 <&gcc GCC_SDCC1_APPS_CLK>,
3173 <&rpmcc RPM_S 3087 <&rpmcc RPM_SMD_XO_CLK_SRC>;
3174 resets = <&gcc GCC_SD 3088 resets = <&gcc GCC_SDCC1_BCR>;
3175 3089
3176 pinctrl-names = "defa 3090 pinctrl-names = "default", "sleep";
3177 pinctrl-0 = <&sdc1_st 3091 pinctrl-0 = <&sdc1_state_on>;
3178 pinctrl-1 = <&sdc1_st 3092 pinctrl-1 = <&sdc1_state_off>;
3179 3093
3180 bus-width = <8>; 3094 bus-width = <8>;
3181 non-removable; 3095 non-removable;
3182 status = "disabled"; 3096 status = "disabled";
3183 }; 3097 };
3184 3098
3185 sdhc2: mmc@74a4900 { 3099 sdhc2: mmc@74a4900 {
3186 compatible = "qcom,ms 3100 compatible = "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4";
3187 reg = <0x074a4900 0x3 3101 reg = <0x074a4900 0x314>, <0x074a4000 0x800>;
3188 reg-names = "hc", "co 3102 reg-names = "hc", "core";
3189 3103
3190 interrupts = <GIC_SPI 3104 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
3191 <GIC_SP 3105 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
3192 interrupt-names = "hc 3106 interrupt-names = "hc_irq", "pwr_irq";
3193 3107
3194 clock-names = "iface" 3108 clock-names = "iface", "core", "xo";
3195 clocks = <&gcc GCC_SD 3109 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
3196 <&gcc GCC_SDC 3110 <&gcc GCC_SDCC2_APPS_CLK>,
3197 <&rpmcc RPM_S 3111 <&rpmcc RPM_SMD_XO_CLK_SRC>;
3198 resets = <&gcc GCC_SD 3112 resets = <&gcc GCC_SDCC2_BCR>;
3199 3113
3200 pinctrl-names = "defa 3114 pinctrl-names = "default", "sleep";
3201 pinctrl-0 = <&sdc2_st 3115 pinctrl-0 = <&sdc2_state_on>;
3202 pinctrl-1 = <&sdc2_st 3116 pinctrl-1 = <&sdc2_state_off>;
3203 3117
3204 bus-width = <4>; 3118 bus-width = <4>;
3205 status = "disabled"; 3119 status = "disabled";
3206 }; 3120 };
3207 3121
3208 blsp1_dma: dma-controller@754 3122 blsp1_dma: dma-controller@7544000 {
3209 compatible = "qcom,ba 3123 compatible = "qcom,bam-v1.7.0";
3210 reg = <0x07544000 0x2 3124 reg = <0x07544000 0x2b000>;
3211 interrupts = <GIC_SPI 3125 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
3212 clocks = <&gcc GCC_BL 3126 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
3213 clock-names = "bam_cl 3127 clock-names = "bam_clk";
3214 qcom,controlled-remot 3128 qcom,controlled-remotely;
3215 #dma-cells = <1>; 3129 #dma-cells = <1>;
3216 qcom,ee = <0>; 3130 qcom,ee = <0>;
3217 }; 3131 };
3218 3132
3219 blsp1_uart2: serial@7570000 { 3133 blsp1_uart2: serial@7570000 {
3220 compatible = "qcom,ms 3134 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
3221 reg = <0x07570000 0x1 3135 reg = <0x07570000 0x1000>;
3222 interrupts = <GIC_SPI 3136 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
3223 clocks = <&gcc GCC_BL 3137 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
3224 <&gcc GCC_BL 3138 <&gcc GCC_BLSP1_AHB_CLK>;
3225 clock-names = "core", 3139 clock-names = "core", "iface";
3226 pinctrl-names = "defa 3140 pinctrl-names = "default", "sleep";
3227 pinctrl-0 = <&blsp1_u 3141 pinctrl-0 = <&blsp1_uart2_default>;
3228 pinctrl-1 = <&blsp1_u 3142 pinctrl-1 = <&blsp1_uart2_sleep>;
3229 dmas = <&blsp1_dma 2> 3143 dmas = <&blsp1_dma 2>, <&blsp1_dma 3>;
3230 dma-names = "tx", "rx 3144 dma-names = "tx", "rx";
3231 status = "disabled"; 3145 status = "disabled";
3232 }; 3146 };
3233 3147
3234 blsp1_spi1: spi@7575000 { 3148 blsp1_spi1: spi@7575000 {
3235 compatible = "qcom,sp 3149 compatible = "qcom,spi-qup-v2.2.1";
3236 reg = <0x07575000 0x6 3150 reg = <0x07575000 0x600>;
3237 interrupts = <GIC_SPI 3151 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
3238 clocks = <&gcc GCC_BL 3152 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
3239 <&gcc GCC_BL 3153 <&gcc GCC_BLSP1_AHB_CLK>;
3240 clock-names = "core", 3154 clock-names = "core", "iface";
3241 pinctrl-names = "defa 3155 pinctrl-names = "default", "sleep";
3242 pinctrl-0 = <&blsp1_s 3156 pinctrl-0 = <&blsp1_spi1_default>;
3243 pinctrl-1 = <&blsp1_s 3157 pinctrl-1 = <&blsp1_spi1_sleep>;
3244 dmas = <&blsp1_dma 12 3158 dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
3245 dma-names = "tx", "rx 3159 dma-names = "tx", "rx";
3246 #address-cells = <1>; 3160 #address-cells = <1>;
3247 #size-cells = <0>; 3161 #size-cells = <0>;
3248 status = "disabled"; 3162 status = "disabled";
3249 }; 3163 };
3250 3164
3251 blsp1_i2c3: i2c@7577000 { 3165 blsp1_i2c3: i2c@7577000 {
3252 compatible = "qcom,i2 3166 compatible = "qcom,i2c-qup-v2.2.1";
3253 reg = <0x07577000 0x1 3167 reg = <0x07577000 0x1000>;
3254 interrupts = <GIC_SPI 3168 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
3255 clocks = <&gcc GCC_BL 3169 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
3256 <&gcc GCC_BL 3170 <&gcc GCC_BLSP1_AHB_CLK>;
3257 clock-names = "core", 3171 clock-names = "core", "iface";
3258 pinctrl-names = "defa 3172 pinctrl-names = "default", "sleep";
3259 pinctrl-0 = <&blsp1_i 3173 pinctrl-0 = <&blsp1_i2c3_default>;
3260 pinctrl-1 = <&blsp1_i 3174 pinctrl-1 = <&blsp1_i2c3_sleep>;
3261 dmas = <&blsp1_dma 16 3175 dmas = <&blsp1_dma 16>, <&blsp1_dma 17>;
3262 dma-names = "tx", "rx 3176 dma-names = "tx", "rx";
3263 #address-cells = <1>; 3177 #address-cells = <1>;
3264 #size-cells = <0>; 3178 #size-cells = <0>;
3265 status = "disabled"; 3179 status = "disabled";
3266 }; 3180 };
3267 3181
3268 blsp1_i2c6: i2c@757a000 { 3182 blsp1_i2c6: i2c@757a000 {
3269 compatible = "qcom,i2 3183 compatible = "qcom,i2c-qup-v2.2.1";
3270 reg = <0x757a000 0x10 3184 reg = <0x757a000 0x1000>;
3271 interrupts = <GIC_SPI 3185 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
3272 clocks = <&gcc GCC_BL 3186 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
3273 <&gcc GCC_BL 3187 <&gcc GCC_BLSP1_AHB_CLK>;
3274 clock-names = "core", 3188 clock-names = "core", "iface";
3275 pinctrl-names = "defa 3189 pinctrl-names = "default", "sleep";
3276 pinctrl-0 = <&blsp1_i 3190 pinctrl-0 = <&blsp1_i2c6_default>;
3277 pinctrl-1 = <&blsp1_i 3191 pinctrl-1 = <&blsp1_i2c6_sleep>;
3278 dmas = <&blsp1_dma 22 3192 dmas = <&blsp1_dma 22>, <&blsp1_dma 23>;
3279 dma-names = "tx", "rx 3193 dma-names = "tx", "rx";
3280 #address-cells = <1>; 3194 #address-cells = <1>;
3281 #size-cells = <0>; 3195 #size-cells = <0>;
3282 status = "disabled"; 3196 status = "disabled";
3283 }; 3197 };
3284 3198
3285 blsp2_dma: dma-controller@758 3199 blsp2_dma: dma-controller@7584000 {
3286 compatible = "qcom,ba 3200 compatible = "qcom,bam-v1.7.0";
3287 reg = <0x07584000 0x2 3201 reg = <0x07584000 0x2b000>;
3288 interrupts = <GIC_SPI 3202 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
3289 clocks = <&gcc GCC_BL 3203 clocks = <&gcc GCC_BLSP2_AHB_CLK>;
3290 clock-names = "bam_cl 3204 clock-names = "bam_clk";
3291 qcom,controlled-remot 3205 qcom,controlled-remotely;
3292 #dma-cells = <1>; 3206 #dma-cells = <1>;
3293 qcom,ee = <0>; 3207 qcom,ee = <0>;
3294 }; 3208 };
3295 3209
3296 blsp2_uart2: serial@75b0000 { 3210 blsp2_uart2: serial@75b0000 {
3297 compatible = "qcom,ms 3211 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
3298 reg = <0x075b0000 0x1 3212 reg = <0x075b0000 0x1000>;
3299 interrupts = <GIC_SPI 3213 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
3300 clocks = <&gcc GCC_BL 3214 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
3301 <&gcc GCC_BL 3215 <&gcc GCC_BLSP2_AHB_CLK>;
3302 clock-names = "core", 3216 clock-names = "core", "iface";
3303 status = "disabled"; 3217 status = "disabled";
3304 }; 3218 };
3305 3219
3306 blsp2_uart3: serial@75b1000 { 3220 blsp2_uart3: serial@75b1000 {
3307 compatible = "qcom,ms 3221 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
3308 reg = <0x075b1000 0x1 3222 reg = <0x075b1000 0x1000>;
3309 interrupts = <GIC_SPI 3223 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
3310 clocks = <&gcc GCC_BL 3224 clocks = <&gcc GCC_BLSP2_UART3_APPS_CLK>,
3311 <&gcc GCC_BL 3225 <&gcc GCC_BLSP2_AHB_CLK>;
3312 clock-names = "core", 3226 clock-names = "core", "iface";
3313 status = "disabled"; 3227 status = "disabled";
3314 }; 3228 };
3315 3229
3316 blsp2_i2c1: i2c@75b5000 { 3230 blsp2_i2c1: i2c@75b5000 {
3317 compatible = "qcom,i2 3231 compatible = "qcom,i2c-qup-v2.2.1";
3318 reg = <0x075b5000 0x1 3232 reg = <0x075b5000 0x1000>;
3319 interrupts = <GIC_SPI 3233 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
3320 clocks = <&gcc GCC_BL 3234 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
3321 <&gcc GCC_BL 3235 <&gcc GCC_BLSP2_AHB_CLK>;
3322 clock-names = "core", 3236 clock-names = "core", "iface";
3323 pinctrl-names = "defa 3237 pinctrl-names = "default", "sleep";
3324 pinctrl-0 = <&blsp2_i 3238 pinctrl-0 = <&blsp2_i2c1_default>;
3325 pinctrl-1 = <&blsp2_i 3239 pinctrl-1 = <&blsp2_i2c1_sleep>;
3326 dmas = <&blsp2_dma 12 3240 dmas = <&blsp2_dma 12>, <&blsp2_dma 13>;
3327 dma-names = "tx", "rx 3241 dma-names = "tx", "rx";
3328 #address-cells = <1>; 3242 #address-cells = <1>;
3329 #size-cells = <0>; 3243 #size-cells = <0>;
3330 status = "disabled"; 3244 status = "disabled";
3331 }; 3245 };
3332 3246
3333 blsp2_i2c2: i2c@75b6000 { 3247 blsp2_i2c2: i2c@75b6000 {
3334 compatible = "qcom,i2 3248 compatible = "qcom,i2c-qup-v2.2.1";
3335 reg = <0x075b6000 0x1 3249 reg = <0x075b6000 0x1000>;
3336 interrupts = <GIC_SPI 3250 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
3337 clocks = <&gcc GCC_BL 3251 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>,
3338 <&gcc GCC_BL 3252 <&gcc GCC_BLSP2_AHB_CLK>;
3339 clock-names = "core", 3253 clock-names = "core", "iface";
3340 pinctrl-names = "defa 3254 pinctrl-names = "default", "sleep";
3341 pinctrl-0 = <&blsp2_i 3255 pinctrl-0 = <&blsp2_i2c2_default>;
3342 pinctrl-1 = <&blsp2_i 3256 pinctrl-1 = <&blsp2_i2c2_sleep>;
3343 dmas = <&blsp2_dma 14 3257 dmas = <&blsp2_dma 14>, <&blsp2_dma 15>;
3344 dma-names = "tx", "rx 3258 dma-names = "tx", "rx";
3345 #address-cells = <1>; 3259 #address-cells = <1>;
3346 #size-cells = <0>; 3260 #size-cells = <0>;
3347 status = "disabled"; 3261 status = "disabled";
3348 }; 3262 };
3349 3263
3350 blsp2_i2c3: i2c@75b7000 { 3264 blsp2_i2c3: i2c@75b7000 {
3351 compatible = "qcom,i2 3265 compatible = "qcom,i2c-qup-v2.2.1";
3352 reg = <0x075b7000 0x1 3266 reg = <0x075b7000 0x1000>;
3353 interrupts = <GIC_SPI 3267 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
3354 clocks = <&gcc GCC_BL 3268 clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>,
3355 <&gcc GCC_BL 3269 <&gcc GCC_BLSP2_AHB_CLK>;
3356 clock-names = "core", 3270 clock-names = "core", "iface";
3357 clock-frequency = <40 3271 clock-frequency = <400000>;
3358 pinctrl-names = "defa 3272 pinctrl-names = "default", "sleep";
3359 pinctrl-0 = <&blsp2_i 3273 pinctrl-0 = <&blsp2_i2c3_default>;
3360 pinctrl-1 = <&blsp2_i 3274 pinctrl-1 = <&blsp2_i2c3_sleep>;
3361 dmas = <&blsp2_dma 16 3275 dmas = <&blsp2_dma 16>, <&blsp2_dma 17>;
3362 dma-names = "tx", "rx 3276 dma-names = "tx", "rx";
3363 #address-cells = <1>; 3277 #address-cells = <1>;
3364 #size-cells = <0>; 3278 #size-cells = <0>;
3365 status = "disabled"; 3279 status = "disabled";
3366 }; 3280 };
3367 3281
3368 blsp2_i2c5: i2c@75b9000 { 3282 blsp2_i2c5: i2c@75b9000 {
3369 compatible = "qcom,i2 3283 compatible = "qcom,i2c-qup-v2.2.1";
3370 reg = <0x75b9000 0x10 3284 reg = <0x75b9000 0x1000>;
3371 interrupts = <GIC_SPI 3285 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
3372 clocks = <&gcc GCC_BL 3286 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>,
3373 <&gcc GCC_BL 3287 <&gcc GCC_BLSP2_AHB_CLK>;
3374 clock-names = "core", 3288 clock-names = "core", "iface";
3375 pinctrl-names = "defa 3289 pinctrl-names = "default";
3376 pinctrl-0 = <&blsp2_i 3290 pinctrl-0 = <&blsp2_i2c5_default>;
3377 dmas = <&blsp2_dma 20 3291 dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
3378 dma-names = "tx", "rx 3292 dma-names = "tx", "rx";
3379 #address-cells = <1>; 3293 #address-cells = <1>;
3380 #size-cells = <0>; 3294 #size-cells = <0>;
3381 status = "disabled"; 3295 status = "disabled";
3382 }; 3296 };
3383 3297
3384 blsp2_i2c6: i2c@75ba000 { 3298 blsp2_i2c6: i2c@75ba000 {
3385 compatible = "qcom,i2 3299 compatible = "qcom,i2c-qup-v2.2.1";
3386 reg = <0x75ba000 0x10 3300 reg = <0x75ba000 0x1000>;
3387 interrupts = <GIC_SPI 3301 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
3388 clocks = <&gcc GCC_BL 3302 clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>,
3389 <&gcc GCC_BL 3303 <&gcc GCC_BLSP2_AHB_CLK>;
3390 clock-names = "core", 3304 clock-names = "core", "iface";
3391 pinctrl-names = "defa 3305 pinctrl-names = "default", "sleep";
3392 pinctrl-0 = <&blsp2_i 3306 pinctrl-0 = <&blsp2_i2c6_default>;
3393 pinctrl-1 = <&blsp2_i 3307 pinctrl-1 = <&blsp2_i2c6_sleep>;
3394 dmas = <&blsp2_dma 22 3308 dmas = <&blsp2_dma 22>, <&blsp2_dma 23>;
3395 dma-names = "tx", "rx 3309 dma-names = "tx", "rx";
3396 #address-cells = <1>; 3310 #address-cells = <1>;
3397 #size-cells = <0>; 3311 #size-cells = <0>;
3398 status = "disabled"; 3312 status = "disabled";
3399 }; 3313 };
3400 3314
3401 blsp2_spi6: spi@75ba000 { 3315 blsp2_spi6: spi@75ba000 {
3402 compatible = "qcom,sp 3316 compatible = "qcom,spi-qup-v2.2.1";
3403 reg = <0x075ba000 0x6 3317 reg = <0x075ba000 0x600>;
3404 interrupts = <GIC_SPI 3318 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
3405 clocks = <&gcc GCC_BL 3319 clocks = <&gcc GCC_BLSP2_QUP6_SPI_APPS_CLK>,
3406 <&gcc GCC_BL 3320 <&gcc GCC_BLSP2_AHB_CLK>;
3407 clock-names = "core", 3321 clock-names = "core", "iface";
3408 pinctrl-names = "defa 3322 pinctrl-names = "default", "sleep";
3409 pinctrl-0 = <&blsp2_s 3323 pinctrl-0 = <&blsp2_spi6_default>;
3410 pinctrl-1 = <&blsp2_s 3324 pinctrl-1 = <&blsp2_spi6_sleep>;
3411 dmas = <&blsp2_dma 22 3325 dmas = <&blsp2_dma 22>, <&blsp2_dma 23>;
3412 dma-names = "tx", "rx 3326 dma-names = "tx", "rx";
3413 #address-cells = <1>; 3327 #address-cells = <1>;
3414 #size-cells = <0>; 3328 #size-cells = <0>;
3415 status = "disabled"; 3329 status = "disabled";
3416 }; 3330 };
3417 3331
3418 usb2: usb@76f8800 { 3332 usb2: usb@76f8800 {
3419 compatible = "qcom,ms 3333 compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
3420 reg = <0x076f8800 0x4 3334 reg = <0x076f8800 0x400>;
3421 #address-cells = <1>; 3335 #address-cells = <1>;
3422 #size-cells = <1>; 3336 #size-cells = <1>;
3423 ranges; 3337 ranges;
3424 3338
3425 interrupts = <GIC_SPI !! 3339 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
3426 <GIC_SPI !! 3340 interrupt-names = "hs_phy_irq";
3427 <GIC_SPI <<
3428 interrupt-names = "pw <<
3429 "qu <<
3430 "hs <<
3431 3341
3432 clocks = <&gcc GCC_PE 3342 clocks = <&gcc GCC_PERIPH_NOC_USB20_AHB_CLK>,
3433 <&gcc GCC_USB 3343 <&gcc GCC_USB20_MASTER_CLK>,
3434 <&gcc GCC_USB 3344 <&gcc GCC_USB20_MOCK_UTMI_CLK>,
3435 <&gcc GCC_USB 3345 <&gcc GCC_USB20_SLEEP_CLK>,
3436 <&gcc GCC_USB 3346 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
3437 clock-names = "cfg_no 3347 clock-names = "cfg_noc",
3438 "core", 3348 "core",
3439 "iface" 3349 "iface",
3440 "sleep" 3350 "sleep",
3441 "mock_u 3351 "mock_utmi";
3442 3352
3443 assigned-clocks = <&g 3353 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
3444 <&g 3354 <&gcc GCC_USB20_MASTER_CLK>;
3445 assigned-clock-rates 3355 assigned-clock-rates = <19200000>, <60000000>;
3446 3356
3447 power-domains = <&gcc 3357 power-domains = <&gcc USB30_GDSC>;
3448 qcom,select-utmi-as-p 3358 qcom,select-utmi-as-pipe-clk;
3449 status = "disabled"; 3359 status = "disabled";
3450 3360
3451 usb2_dwc3: usb@760000 3361 usb2_dwc3: usb@7600000 {
3452 compatible = 3362 compatible = "snps,dwc3";
3453 reg = <0x0760 3363 reg = <0x07600000 0xcc00>;
3454 interrupts = !! 3364 interrupts = <0 138 IRQ_TYPE_LEVEL_HIGH>;
3455 phys = <&hsus 3365 phys = <&hsusb_phy2>;
3456 phy-names = " 3366 phy-names = "usb2-phy";
3457 maximum-speed 3367 maximum-speed = "high-speed";
3458 snps,dis_u2_s 3368 snps,dis_u2_susphy_quirk;
3459 snps,dis_enbl 3369 snps,dis_enblslpm_quirk;
3460 }; 3370 };
3461 }; 3371 };
3462 3372
3463 slimbam: dma-controller@91840 3373 slimbam: dma-controller@9184000 {
3464 compatible = "qcom,ba 3374 compatible = "qcom,bam-v1.7.0";
3465 qcom,controlled-remot 3375 qcom,controlled-remotely;
3466 reg = <0x09184000 0x3 3376 reg = <0x09184000 0x32000>;
3467 num-channels = <31>; 3377 num-channels = <31>;
3468 interrupts = <GIC_SPI !! 3378 interrupts = <0 164 IRQ_TYPE_LEVEL_HIGH>;
3469 #dma-cells = <1>; 3379 #dma-cells = <1>;
3470 qcom,ee = <1>; 3380 qcom,ee = <1>;
3471 qcom,num-ees = <2>; 3381 qcom,num-ees = <2>;
3472 }; 3382 };
3473 3383
3474 slim_msm: slim-ngd@91c0000 { 3384 slim_msm: slim-ngd@91c0000 {
3475 compatible = "qcom,sl 3385 compatible = "qcom,slim-ngd-v1.5.0";
3476 reg = <0x091c0000 0x2 3386 reg = <0x091c0000 0x2c000>;
3477 interrupts = <GIC_SPI !! 3387 interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>;
3478 dmas = <&slimbam 3>, 3388 dmas = <&slimbam 3>, <&slimbam 4>;
3479 dma-names = "rx", "tx 3389 dma-names = "rx", "tx";
3480 #address-cells = <1>; 3390 #address-cells = <1>;
3481 #size-cells = <0>; 3391 #size-cells = <0>;
3482 3392
3483 status = "disabled"; 3393 status = "disabled";
3484 }; 3394 };
3485 3395
3486 adsp_pil: remoteproc@9300000 3396 adsp_pil: remoteproc@9300000 {
3487 compatible = "qcom,ms 3397 compatible = "qcom,msm8996-adsp-pil";
3488 reg = <0x09300000 0x8 3398 reg = <0x09300000 0x80000>;
3489 3399
3490 interrupts-extended = 3400 interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>,
3491 3401 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3492 3402 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
3493 3403 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
3494 3404 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
3495 interrupt-names = "wd 3405 interrupt-names = "wdog", "fatal", "ready",
3496 "ha 3406 "handover", "stop-ack";
3497 3407
3498 clocks = <&rpmcc RPM_ 3408 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
3499 clock-names = "xo"; 3409 clock-names = "xo";
3500 3410
3501 memory-region = <&ads 3411 memory-region = <&adsp_mem>;
3502 3412
3503 qcom,smem-states = <& 3413 qcom,smem-states = <&adsp_smp2p_out 0>;
3504 qcom,smem-state-names 3414 qcom,smem-state-names = "stop";
3505 3415
3506 power-domains = <&rpm 3416 power-domains = <&rpmpd MSM8996_VDDCX>;
3507 power-domain-names = 3417 power-domain-names = "cx";
3508 3418
3509 status = "disabled"; 3419 status = "disabled";
3510 3420
3511 glink-edge { <<
3512 interrupts = <<
3513 label = "lpas <<
3514 qcom,remote-p <<
3515 mboxes = <&ap <<
3516 }; <<
3517 <<
3518 <<
3519 smd-edge { 3421 smd-edge {
3520 interrupts = 3422 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
3521 3423
3522 label = "lpas 3424 label = "lpass";
3523 mboxes = <&ap 3425 mboxes = <&apcs_glb 8>;
3524 qcom,smd-edge 3426 qcom,smd-edge = <1>;
3525 qcom,remote-p 3427 qcom,remote-pid = <2>;
3526 3428
3527 apr { 3429 apr {
3528 power 3430 power-domains = <&gcc HLOS1_VOTE_LPASS_ADSP_GDSC>;
3529 compa 3431 compatible = "qcom,apr-v2";
3530 qcom, 3432 qcom,smd-channels = "apr_audio_svc";
3531 qcom, 3433 qcom,domain = <APR_DOMAIN_ADSP>;
3532 #addr 3434 #address-cells = <1>;
3533 #size 3435 #size-cells = <0>;
3534 3436
3535 servi 3437 service@3 {
3536 3438 reg = <APR_SVC_ADSP_CORE>;
3537 3439 compatible = "qcom,q6core";
3538 }; 3440 };
3539 3441
3540 q6afe 3442 q6afe: service@4 {
3541 3443 compatible = "qcom,q6afe";
3542 3444 reg = <APR_SVC_AFE>;
3543 3445 q6afedai: dais {
3544 3446 compatible = "qcom,q6afe-dais";
3545 3447 #address-cells = <1>;
3546 3448 #size-cells = <0>;
3547 3449 #sound-dai-cells = <1>;
3548 3450 dai@1 {
3549 3451 reg = <1>;
3550 3452 };
3551 3453 };
3552 }; 3454 };
3553 3455
3554 q6asm 3456 q6asm: service@7 {
3555 3457 compatible = "qcom,q6asm";
3556 3458 reg = <APR_SVC_ASM>;
3557 3459 q6asmdai: dais {
3558 3460 compatible = "qcom,q6asm-dais";
3559 3461 #address-cells = <1>;
3560 3462 #size-cells = <0>;
3561 3463 #sound-dai-cells = <1>;
3562 3464 iommus = <&lpass_q6_smmu 1>;
3563 3465 };
3564 }; 3466 };
3565 3467
3566 q6adm 3468 q6adm: service@8 {
3567 3469 compatible = "qcom,q6adm";
3568 3470 reg = <APR_SVC_ADM>;
3569 3471 q6routing: routing {
3570 3472 compatible = "qcom,q6adm-routing";
3571 3473 #sound-dai-cells = <0>;
3572 3474 };
3573 }; 3475 };
3574 }; 3476 };
3575 <<
3576 fastrpc { <<
3577 compa <<
3578 qcom, <<
3579 label <<
3580 qcom, <<
3581 #addr <<
3582 #size <<
3583 <<
3584 cb@5 <<
3585 <<
3586 <<
3587 <<
3588 }; <<
3589 <<
3590 cb@6 <<
3591 <<
3592 <<
3593 <<
3594 }; <<
3595 <<
3596 cb@7 <<
3597 <<
3598 <<
3599 <<
3600 }; <<
3601 <<
3602 cb@8 <<
3603 <<
3604 <<
3605 <<
3606 }; <<
3607 <<
3608 cb@9 <<
3609 <<
3610 <<
3611 <<
3612 }; <<
3613 <<
3614 cb@10 <<
3615 <<
3616 <<
3617 <<
3618 }; <<
3619 <<
3620 cb@11 <<
3621 <<
3622 <<
3623 <<
3624 }; <<
3625 <<
3626 cb@12 <<
3627 <<
3628 <<
3629 <<
3630 }; <<
3631 }; <<
3632 }; 3477 };
3633 }; 3478 };
3634 3479
3635 apcs_glb: mailbox@9820000 { 3480 apcs_glb: mailbox@9820000 {
3636 compatible = "qcom,ms 3481 compatible = "qcom,msm8996-apcs-hmss-global";
3637 reg = <0x09820000 0x1 3482 reg = <0x09820000 0x1000>;
3638 3483
3639 #mbox-cells = <1>; 3484 #mbox-cells = <1>;
3640 #clock-cells = <0>; 3485 #clock-cells = <0>;
3641 }; 3486 };
3642 3487
3643 timer@9840000 { 3488 timer@9840000 {
3644 #address-cells = <1>; 3489 #address-cells = <1>;
3645 #size-cells = <1>; 3490 #size-cells = <1>;
3646 ranges; 3491 ranges;
3647 compatible = "arm,arm 3492 compatible = "arm,armv7-timer-mem";
3648 reg = <0x09840000 0x1 3493 reg = <0x09840000 0x1000>;
3649 clock-frequency = <19 3494 clock-frequency = <19200000>;
3650 3495
3651 frame@9850000 { 3496 frame@9850000 {
3652 frame-number 3497 frame-number = <0>;
3653 interrupts = 3498 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
3654 3499 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
3655 reg = <0x0985 3500 reg = <0x09850000 0x1000>,
3656 <0x0986 3501 <0x09860000 0x1000>;
3657 }; 3502 };
3658 3503
3659 frame@9870000 { 3504 frame@9870000 {
3660 frame-number 3505 frame-number = <1>;
3661 interrupts = 3506 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
3662 reg = <0x0987 3507 reg = <0x09870000 0x1000>;
3663 status = "dis 3508 status = "disabled";
3664 }; 3509 };
3665 3510
3666 frame@9880000 { 3511 frame@9880000 {
3667 frame-number 3512 frame-number = <2>;
3668 interrupts = 3513 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
3669 reg = <0x0988 3514 reg = <0x09880000 0x1000>;
3670 status = "dis 3515 status = "disabled";
3671 }; 3516 };
3672 3517
3673 frame@9890000 { 3518 frame@9890000 {
3674 frame-number 3519 frame-number = <3>;
3675 interrupts = 3520 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
3676 reg = <0x0989 3521 reg = <0x09890000 0x1000>;
3677 status = "dis 3522 status = "disabled";
3678 }; 3523 };
3679 3524
3680 frame@98a0000 { 3525 frame@98a0000 {
3681 frame-number 3526 frame-number = <4>;
3682 interrupts = 3527 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
3683 reg = <0x098a 3528 reg = <0x098a0000 0x1000>;
3684 status = "dis 3529 status = "disabled";
3685 }; 3530 };
3686 3531
3687 frame@98b0000 { 3532 frame@98b0000 {
3688 frame-number 3533 frame-number = <5>;
3689 interrupts = 3534 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
3690 reg = <0x098b 3535 reg = <0x098b0000 0x1000>;
3691 status = "dis 3536 status = "disabled";
3692 }; 3537 };
3693 3538
3694 frame@98c0000 { 3539 frame@98c0000 {
3695 frame-number 3540 frame-number = <6>;
3696 interrupts = 3541 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
3697 reg = <0x098c 3542 reg = <0x098c0000 0x1000>;
3698 status = "dis 3543 status = "disabled";
3699 }; 3544 };
3700 }; 3545 };
3701 3546
3702 saw3: syscon@9a10000 { 3547 saw3: syscon@9a10000 {
3703 compatible = "syscon" 3548 compatible = "syscon";
3704 reg = <0x09a10000 0x1 3549 reg = <0x09a10000 0x1000>;
3705 }; 3550 };
3706 3551
3707 cbf: clock-controller@9a11000 3552 cbf: clock-controller@9a11000 {
3708 compatible = "qcom,ms 3553 compatible = "qcom,msm8996-cbf";
3709 reg = <0x09a11000 0x1 3554 reg = <0x09a11000 0x10000>;
3710 clocks = <&rpmcc RPM_ 3555 clocks = <&rpmcc RPM_SMD_XO_A_CLK_SRC>, <&apcs_glb>;
3711 #clock-cells = <0>; 3556 #clock-cells = <0>;
3712 #interconnect-cells = <<
3713 }; 3557 };
3714 3558
3715 intc: interrupt-controller@9b 3559 intc: interrupt-controller@9bc0000 {
3716 compatible = "qcom,ms 3560 compatible = "qcom,msm8996-gic-v3", "arm,gic-v3";
3717 #interrupt-cells = <3 3561 #interrupt-cells = <3>;
3718 interrupt-controller; 3562 interrupt-controller;
3719 #redistributor-region 3563 #redistributor-regions = <1>;
3720 redistributor-stride 3564 redistributor-stride = <0x0 0x40000>;
3721 reg = <0x09bc0000 0x1 3565 reg = <0x09bc0000 0x10000>,
3722 <0x09c00000 0x1 3566 <0x09c00000 0x100000>;
3723 interrupts = <GIC_PPI 3567 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
3724 }; 3568 };
3725 }; 3569 };
3726 3570
3727 sound: sound { 3571 sound: sound {
3728 }; 3572 };
3729 3573
3730 thermal-zones { 3574 thermal-zones {
3731 cpu0-thermal { 3575 cpu0-thermal {
3732 polling-delay-passive 3576 polling-delay-passive = <250>;
>> 3577 polling-delay = <1000>;
3733 3578
3734 thermal-sensors = <&t 3579 thermal-sensors = <&tsens0 3>;
3735 3580
3736 trips { 3581 trips {
3737 cpu0_alert0: 3582 cpu0_alert0: trip-point0 {
3738 tempe 3583 temperature = <75000>;
3739 hyste 3584 hysteresis = <2000>;
3740 type 3585 type = "passive";
3741 }; 3586 };
3742 3587
3743 cpu0_crit: cp 3588 cpu0_crit: cpu-crit {
3744 tempe 3589 temperature = <110000>;
3745 hyste 3590 hysteresis = <2000>;
3746 type 3591 type = "critical";
3747 }; 3592 };
3748 }; 3593 };
3749 }; 3594 };
3750 3595
3751 cpu1-thermal { 3596 cpu1-thermal {
3752 polling-delay-passive 3597 polling-delay-passive = <250>;
>> 3598 polling-delay = <1000>;
3753 3599
3754 thermal-sensors = <&t 3600 thermal-sensors = <&tsens0 5>;
3755 3601
3756 trips { 3602 trips {
3757 cpu1_alert0: 3603 cpu1_alert0: trip-point0 {
3758 tempe 3604 temperature = <75000>;
3759 hyste 3605 hysteresis = <2000>;
3760 type 3606 type = "passive";
3761 }; 3607 };
3762 3608
3763 cpu1_crit: cp 3609 cpu1_crit: cpu-crit {
3764 tempe 3610 temperature = <110000>;
3765 hyste 3611 hysteresis = <2000>;
3766 type 3612 type = "critical";
3767 }; 3613 };
3768 }; 3614 };
3769 }; 3615 };
3770 3616
3771 cpu2-thermal { 3617 cpu2-thermal {
3772 polling-delay-passive 3618 polling-delay-passive = <250>;
>> 3619 polling-delay = <1000>;
3773 3620
3774 thermal-sensors = <&t 3621 thermal-sensors = <&tsens0 8>;
3775 3622
3776 trips { 3623 trips {
3777 cpu2_alert0: 3624 cpu2_alert0: trip-point0 {
3778 tempe 3625 temperature = <75000>;
3779 hyste 3626 hysteresis = <2000>;
3780 type 3627 type = "passive";
3781 }; 3628 };
3782 3629
3783 cpu2_crit: cp 3630 cpu2_crit: cpu-crit {
3784 tempe 3631 temperature = <110000>;
3785 hyste 3632 hysteresis = <2000>;
3786 type 3633 type = "critical";
3787 }; 3634 };
3788 }; 3635 };
3789 }; 3636 };
3790 3637
3791 cpu3-thermal { 3638 cpu3-thermal {
3792 polling-delay-passive 3639 polling-delay-passive = <250>;
>> 3640 polling-delay = <1000>;
3793 3641
3794 thermal-sensors = <&t 3642 thermal-sensors = <&tsens0 10>;
3795 3643
3796 trips { 3644 trips {
3797 cpu3_alert0: 3645 cpu3_alert0: trip-point0 {
3798 tempe 3646 temperature = <75000>;
3799 hyste 3647 hysteresis = <2000>;
3800 type 3648 type = "passive";
3801 }; 3649 };
3802 3650
3803 cpu3_crit: cp 3651 cpu3_crit: cpu-crit {
3804 tempe 3652 temperature = <110000>;
3805 hyste 3653 hysteresis = <2000>;
3806 type 3654 type = "critical";
3807 }; 3655 };
3808 }; 3656 };
3809 }; 3657 };
3810 3658
3811 gpu-top-thermal { 3659 gpu-top-thermal {
3812 polling-delay-passive 3660 polling-delay-passive = <250>;
>> 3661 polling-delay = <1000>;
3813 3662
3814 thermal-sensors = <&t 3663 thermal-sensors = <&tsens1 6>;
3815 3664
3816 trips { 3665 trips {
3817 gpu1_alert0: 3666 gpu1_alert0: trip-point0 {
3818 tempe 3667 temperature = <90000>;
3819 hyste 3668 hysteresis = <2000>;
3820 type 3669 type = "passive";
3821 }; 3670 };
3822 }; 3671 };
3823 3672
3824 cooling-maps { 3673 cooling-maps {
3825 map0 { 3674 map0 {
3826 trip 3675 trip = <&gpu1_alert0>;
3827 cooli 3676 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3828 }; 3677 };
3829 }; 3678 };
3830 }; 3679 };
3831 3680
3832 gpu-bottom-thermal { 3681 gpu-bottom-thermal {
3833 polling-delay-passive 3682 polling-delay-passive = <250>;
>> 3683 polling-delay = <1000>;
3834 3684
3835 thermal-sensors = <&t 3685 thermal-sensors = <&tsens1 7>;
3836 3686
3837 trips { 3687 trips {
3838 gpu2_alert0: 3688 gpu2_alert0: trip-point0 {
3839 tempe 3689 temperature = <90000>;
3840 hyste 3690 hysteresis = <2000>;
3841 type 3691 type = "passive";
3842 }; 3692 };
3843 }; 3693 };
3844 3694
3845 cooling-maps { 3695 cooling-maps {
3846 map0 { 3696 map0 {
3847 trip 3697 trip = <&gpu2_alert0>;
3848 cooli 3698 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3849 }; 3699 };
3850 }; 3700 };
3851 }; 3701 };
3852 3702
3853 m4m-thermal { 3703 m4m-thermal {
3854 polling-delay-passive 3704 polling-delay-passive = <250>;
>> 3705 polling-delay = <1000>;
3855 3706
3856 thermal-sensors = <&t 3707 thermal-sensors = <&tsens0 1>;
3857 3708
3858 trips { 3709 trips {
3859 m4m_alert0: t 3710 m4m_alert0: trip-point0 {
3860 tempe 3711 temperature = <90000>;
3861 hyste 3712 hysteresis = <2000>;
3862 type 3713 type = "hot";
3863 }; 3714 };
3864 }; 3715 };
3865 }; 3716 };
3866 3717
3867 l3-or-venus-thermal { 3718 l3-or-venus-thermal {
3868 polling-delay-passive 3719 polling-delay-passive = <250>;
>> 3720 polling-delay = <1000>;
3869 3721
3870 thermal-sensors = <&t 3722 thermal-sensors = <&tsens0 2>;
3871 3723
3872 trips { 3724 trips {
3873 l3_or_venus_a 3725 l3_or_venus_alert0: trip-point0 {
3874 tempe 3726 temperature = <90000>;
3875 hyste 3727 hysteresis = <2000>;
3876 type 3728 type = "hot";
3877 }; 3729 };
3878 }; 3730 };
3879 }; 3731 };
3880 3732
3881 cluster0-l2-thermal { 3733 cluster0-l2-thermal {
3882 polling-delay-passive 3734 polling-delay-passive = <250>;
>> 3735 polling-delay = <1000>;
3883 3736
3884 thermal-sensors = <&t 3737 thermal-sensors = <&tsens0 7>;
3885 3738
3886 trips { 3739 trips {
3887 cluster0_l2_a 3740 cluster0_l2_alert0: trip-point0 {
3888 tempe 3741 temperature = <90000>;
3889 hyste 3742 hysteresis = <2000>;
3890 type 3743 type = "hot";
3891 }; 3744 };
3892 }; 3745 };
3893 }; 3746 };
3894 3747
3895 cluster1-l2-thermal { 3748 cluster1-l2-thermal {
3896 polling-delay-passive 3749 polling-delay-passive = <250>;
>> 3750 polling-delay = <1000>;
3897 3751
3898 thermal-sensors = <&t 3752 thermal-sensors = <&tsens0 12>;
3899 3753
3900 trips { 3754 trips {
3901 cluster1_l2_a 3755 cluster1_l2_alert0: trip-point0 {
3902 tempe 3756 temperature = <90000>;
3903 hyste 3757 hysteresis = <2000>;
3904 type 3758 type = "hot";
3905 }; 3759 };
3906 }; 3760 };
3907 }; 3761 };
3908 3762
3909 camera-thermal { 3763 camera-thermal {
3910 polling-delay-passive 3764 polling-delay-passive = <250>;
>> 3765 polling-delay = <1000>;
3911 3766
3912 thermal-sensors = <&t 3767 thermal-sensors = <&tsens1 1>;
3913 3768
3914 trips { 3769 trips {
3915 camera_alert0 3770 camera_alert0: trip-point0 {
3916 tempe 3771 temperature = <90000>;
3917 hyste 3772 hysteresis = <2000>;
3918 type 3773 type = "hot";
3919 }; 3774 };
3920 }; 3775 };
3921 }; 3776 };
3922 3777
3923 q6-dsp-thermal { 3778 q6-dsp-thermal {
3924 polling-delay-passive 3779 polling-delay-passive = <250>;
>> 3780 polling-delay = <1000>;
3925 3781
3926 thermal-sensors = <&t 3782 thermal-sensors = <&tsens1 2>;
3927 3783
3928 trips { 3784 trips {
3929 q6_dsp_alert0 3785 q6_dsp_alert0: trip-point0 {
3930 tempe 3786 temperature = <90000>;
3931 hyste 3787 hysteresis = <2000>;
3932 type 3788 type = "hot";
3933 }; 3789 };
3934 }; 3790 };
3935 }; 3791 };
3936 3792
3937 mem-thermal { 3793 mem-thermal {
3938 polling-delay-passive 3794 polling-delay-passive = <250>;
>> 3795 polling-delay = <1000>;
3939 3796
3940 thermal-sensors = <&t 3797 thermal-sensors = <&tsens1 3>;
3941 3798
3942 trips { 3799 trips {
3943 mem_alert0: t 3800 mem_alert0: trip-point0 {
3944 tempe 3801 temperature = <90000>;
3945 hyste 3802 hysteresis = <2000>;
3946 type 3803 type = "hot";
3947 }; 3804 };
3948 }; 3805 };
3949 }; 3806 };
3950 3807
3951 modemtx-thermal { 3808 modemtx-thermal {
3952 polling-delay-passive 3809 polling-delay-passive = <250>;
>> 3810 polling-delay = <1000>;
3953 3811
3954 thermal-sensors = <&t 3812 thermal-sensors = <&tsens1 4>;
3955 3813
3956 trips { 3814 trips {
3957 modemtx_alert 3815 modemtx_alert0: trip-point0 {
3958 tempe 3816 temperature = <90000>;
3959 hyste 3817 hysteresis = <2000>;
3960 type 3818 type = "hot";
3961 }; 3819 };
3962 }; 3820 };
3963 }; 3821 };
3964 }; 3822 };
3965 3823
3966 timer { 3824 timer {
3967 compatible = "arm,armv8-timer 3825 compatible = "arm,armv8-timer";
3968 interrupts = <GIC_PPI 13 IRQ_ 3826 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
3969 <GIC_PPI 14 IRQ_ 3827 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
3970 <GIC_PPI 11 IRQ_ 3828 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
3971 <GIC_PPI 10 IRQ_ 3829 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
3972 }; 3830 };
3973 }; 3831 };
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